1 // SPDX-License-Identifier: GPL-2.0 1 // SPDX-License-Identifier: GPL-2.0
2 /* 2 /*
3 * Device Tree Source for the R-Car E3 (R8A779 3 * Device Tree Source for the R-Car E3 (R8A77990) SoC
4 * 4 *
5 * Copyright (C) 2018-2019 Renesas Electronics 5 * Copyright (C) 2018-2019 Renesas Electronics Corp.
6 */ 6 */
7 7
8 #include <dt-bindings/clock/r8a77990-cpg-mssr. 8 #include <dt-bindings/clock/r8a77990-cpg-mssr.h>
9 #include <dt-bindings/interrupt-controller/arm 9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/power/r8a77990-sysc.h> 10 #include <dt-bindings/power/r8a77990-sysc.h>
11 11
12 / { 12 / {
13 compatible = "renesas,r8a77990"; 13 compatible = "renesas,r8a77990";
14 #address-cells = <2>; 14 #address-cells = <2>;
15 #size-cells = <2>; 15 #size-cells = <2>;
16 16
>> 17 aliases {
>> 18 i2c0 = &i2c0;
>> 19 i2c1 = &i2c1;
>> 20 i2c2 = &i2c2;
>> 21 i2c3 = &i2c3;
>> 22 i2c4 = &i2c4;
>> 23 i2c5 = &i2c5;
>> 24 i2c6 = &i2c6;
>> 25 i2c7 = &i2c7;
>> 26 };
>> 27
17 /* 28 /*
18 * The external audio clocks are confi 29 * The external audio clocks are configured as 0 Hz fixed frequency
19 * clocks by default. 30 * clocks by default.
20 * Boards that provide audio clocks sh 31 * Boards that provide audio clocks should override them.
21 */ 32 */
22 audio_clk_a: audio_clk_a { 33 audio_clk_a: audio_clk_a {
23 compatible = "fixed-clock"; 34 compatible = "fixed-clock";
24 #clock-cells = <0>; 35 #clock-cells = <0>;
25 clock-frequency = <0>; 36 clock-frequency = <0>;
26 }; 37 };
27 38
28 audio_clk_b: audio_clk_b { 39 audio_clk_b: audio_clk_b {
29 compatible = "fixed-clock"; 40 compatible = "fixed-clock";
30 #clock-cells = <0>; 41 #clock-cells = <0>;
31 clock-frequency = <0>; 42 clock-frequency = <0>;
32 }; 43 };
33 44
34 audio_clk_c: audio_clk_c { 45 audio_clk_c: audio_clk_c {
35 compatible = "fixed-clock"; 46 compatible = "fixed-clock";
36 #clock-cells = <0>; 47 #clock-cells = <0>;
37 clock-frequency = <0>; 48 clock-frequency = <0>;
38 }; 49 };
39 50
40 /* External CAN clock - to be overridd 51 /* External CAN clock - to be overridden by boards that provide it */
41 can_clk: can { 52 can_clk: can {
42 compatible = "fixed-clock"; 53 compatible = "fixed-clock";
43 #clock-cells = <0>; 54 #clock-cells = <0>;
44 clock-frequency = <0>; 55 clock-frequency = <0>;
45 }; 56 };
46 57
47 cluster1_opp: opp-table-1 { !! 58 cluster1_opp: opp_table10 {
48 compatible = "operating-points 59 compatible = "operating-points-v2";
49 opp-shared; 60 opp-shared;
50 opp-800000000 { 61 opp-800000000 {
51 opp-hz = /bits/ 64 <80 62 opp-hz = /bits/ 64 <800000000>;
52 clock-latency-ns = <30 63 clock-latency-ns = <300000>;
53 }; 64 };
54 opp-1000000000 { 65 opp-1000000000 {
55 opp-hz = /bits/ 64 <10 66 opp-hz = /bits/ 64 <1000000000>;
56 clock-latency-ns = <30 67 clock-latency-ns = <300000>;
57 }; 68 };
58 opp-1200000000 { 69 opp-1200000000 {
59 opp-hz = /bits/ 64 <12 70 opp-hz = /bits/ 64 <1200000000>;
60 clock-latency-ns = <30 71 clock-latency-ns = <300000>;
61 opp-suspend; 72 opp-suspend;
62 }; 73 };
63 }; 74 };
64 75
65 cpus { 76 cpus {
66 #address-cells = <1>; 77 #address-cells = <1>;
67 #size-cells = <0>; 78 #size-cells = <0>;
68 79
69 a53_0: cpu@0 { 80 a53_0: cpu@0 {
70 compatible = "arm,cort 81 compatible = "arm,cortex-a53";
71 reg = <0>; 82 reg = <0>;
72 device_type = "cpu"; 83 device_type = "cpu";
73 #cooling-cells = <2>; 84 #cooling-cells = <2>;
74 power-domains = <&sysc 85 power-domains = <&sysc R8A77990_PD_CA53_CPU0>;
75 next-level-cache = <&L 86 next-level-cache = <&L2_CA53>;
76 enable-method = "psci" 87 enable-method = "psci";
77 cpu-idle-states = <&CP 88 cpu-idle-states = <&CPU_SLEEP_0>;
78 dynamic-power-coeffici 89 dynamic-power-coefficient = <277>;
79 clocks = <&cpg CPG_COR !! 90 clocks =<&cpg CPG_CORE R8A77990_CLK_Z2>;
80 operating-points-v2 = 91 operating-points-v2 = <&cluster1_opp>;
81 }; 92 };
82 93
83 a53_1: cpu@1 { 94 a53_1: cpu@1 {
84 compatible = "arm,cort 95 compatible = "arm,cortex-a53";
85 reg = <1>; 96 reg = <1>;
86 device_type = "cpu"; 97 device_type = "cpu";
87 power-domains = <&sysc 98 power-domains = <&sysc R8A77990_PD_CA53_CPU1>;
88 next-level-cache = <&L 99 next-level-cache = <&L2_CA53>;
89 enable-method = "psci" 100 enable-method = "psci";
90 cpu-idle-states = <&CP 101 cpu-idle-states = <&CPU_SLEEP_0>;
91 clocks = <&cpg CPG_COR !! 102 clocks =<&cpg CPG_CORE R8A77990_CLK_Z2>;
92 operating-points-v2 = 103 operating-points-v2 = <&cluster1_opp>;
93 }; 104 };
94 105
95 L2_CA53: cache-controller-0 { 106 L2_CA53: cache-controller-0 {
96 compatible = "cache"; 107 compatible = "cache";
97 power-domains = <&sysc 108 power-domains = <&sysc R8A77990_PD_CA53_SCU>;
98 cache-unified; 109 cache-unified;
99 cache-level = <2>; 110 cache-level = <2>;
100 }; 111 };
101 112
102 idle-states { 113 idle-states {
103 entry-method = "psci"; 114 entry-method = "psci";
104 115
105 CPU_SLEEP_0: cpu-sleep 116 CPU_SLEEP_0: cpu-sleep-0 {
106 compatible = " 117 compatible = "arm,idle-state";
107 arm,psci-suspe 118 arm,psci-suspend-param = <0x0010000>;
108 local-timer-st 119 local-timer-stop;
109 entry-latency- 120 entry-latency-us = <700>;
110 exit-latency-u 121 exit-latency-us = <700>;
111 min-residency- 122 min-residency-us = <5000>;
112 }; 123 };
113 }; 124 };
114 }; 125 };
115 126
116 extal_clk: extal { 127 extal_clk: extal {
117 compatible = "fixed-clock"; 128 compatible = "fixed-clock";
118 #clock-cells = <0>; 129 #clock-cells = <0>;
119 /* This value must be overridd 130 /* This value must be overridden by the board */
120 clock-frequency = <0>; 131 clock-frequency = <0>;
121 }; 132 };
122 133
123 /* External PCIe clock - can be overri 134 /* External PCIe clock - can be overridden by the board */
124 pcie_bus_clk: pcie_bus { 135 pcie_bus_clk: pcie_bus {
125 compatible = "fixed-clock"; 136 compatible = "fixed-clock";
126 #clock-cells = <0>; 137 #clock-cells = <0>;
127 clock-frequency = <0>; 138 clock-frequency = <0>;
128 }; 139 };
129 140
130 pmu_a53 { 141 pmu_a53 {
131 compatible = "arm,cortex-a53-p 142 compatible = "arm,cortex-a53-pmu";
132 interrupts-extended = <&gic GI 143 interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
133 <&gic GI 144 <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
134 interrupt-affinity = <&a53_0>, 145 interrupt-affinity = <&a53_0>, <&a53_1>;
135 }; 146 };
136 147
137 psci { 148 psci {
138 compatible = "arm,psci-1.0", " 149 compatible = "arm,psci-1.0", "arm,psci-0.2";
139 method = "smc"; 150 method = "smc";
140 }; 151 };
141 152
142 /* External SCIF clock - to be overrid 153 /* External SCIF clock - to be overridden by boards that provide it */
143 scif_clk: scif { 154 scif_clk: scif {
144 compatible = "fixed-clock"; 155 compatible = "fixed-clock";
145 #clock-cells = <0>; 156 #clock-cells = <0>;
146 clock-frequency = <0>; 157 clock-frequency = <0>;
147 }; 158 };
148 159
149 soc: soc { 160 soc: soc {
150 compatible = "simple-bus"; 161 compatible = "simple-bus";
151 interrupt-parent = <&gic>; 162 interrupt-parent = <&gic>;
152 #address-cells = <2>; 163 #address-cells = <2>;
153 #size-cells = <2>; 164 #size-cells = <2>;
154 ranges; 165 ranges;
155 166
156 rwdt: watchdog@e6020000 { 167 rwdt: watchdog@e6020000 {
157 compatible = "renesas, 168 compatible = "renesas,r8a77990-wdt",
158 "renesas, 169 "renesas,rcar-gen3-wdt";
159 reg = <0 0xe6020000 0 170 reg = <0 0xe6020000 0 0x0c>;
160 interrupts = <GIC_SPI <<
161 clocks = <&cpg CPG_MOD 171 clocks = <&cpg CPG_MOD 402>;
162 power-domains = <&sysc 172 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
163 resets = <&cpg 402>; 173 resets = <&cpg 402>;
164 status = "disabled"; 174 status = "disabled";
165 }; 175 };
166 176
167 gpio0: gpio@e6050000 { 177 gpio0: gpio@e6050000 {
168 compatible = "renesas, 178 compatible = "renesas,gpio-r8a77990",
169 "renesas, 179 "renesas,rcar-gen3-gpio";
170 reg = <0 0xe6050000 0 180 reg = <0 0xe6050000 0 0x50>;
171 interrupts = <GIC_SPI 181 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
172 #gpio-cells = <2>; 182 #gpio-cells = <2>;
173 gpio-controller; 183 gpio-controller;
174 gpio-ranges = <&pfc 0 184 gpio-ranges = <&pfc 0 0 18>;
175 #interrupt-cells = <2> 185 #interrupt-cells = <2>;
176 interrupt-controller; 186 interrupt-controller;
177 clocks = <&cpg CPG_MOD 187 clocks = <&cpg CPG_MOD 912>;
178 power-domains = <&sysc 188 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
179 resets = <&cpg 912>; 189 resets = <&cpg 912>;
180 }; 190 };
181 191
182 gpio1: gpio@e6051000 { 192 gpio1: gpio@e6051000 {
183 compatible = "renesas, 193 compatible = "renesas,gpio-r8a77990",
184 "renesas, 194 "renesas,rcar-gen3-gpio";
185 reg = <0 0xe6051000 0 195 reg = <0 0xe6051000 0 0x50>;
186 interrupts = <GIC_SPI 196 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
187 #gpio-cells = <2>; 197 #gpio-cells = <2>;
188 gpio-controller; 198 gpio-controller;
189 gpio-ranges = <&pfc 0 199 gpio-ranges = <&pfc 0 32 23>;
190 #interrupt-cells = <2> 200 #interrupt-cells = <2>;
191 interrupt-controller; 201 interrupt-controller;
192 clocks = <&cpg CPG_MOD 202 clocks = <&cpg CPG_MOD 911>;
193 power-domains = <&sysc 203 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
194 resets = <&cpg 911>; 204 resets = <&cpg 911>;
195 }; 205 };
196 206
197 gpio2: gpio@e6052000 { 207 gpio2: gpio@e6052000 {
198 compatible = "renesas, 208 compatible = "renesas,gpio-r8a77990",
199 "renesas, 209 "renesas,rcar-gen3-gpio";
200 reg = <0 0xe6052000 0 210 reg = <0 0xe6052000 0 0x50>;
201 interrupts = <GIC_SPI 211 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
202 #gpio-cells = <2>; 212 #gpio-cells = <2>;
203 gpio-controller; 213 gpio-controller;
204 gpio-ranges = <&pfc 0 214 gpio-ranges = <&pfc 0 64 26>;
205 #interrupt-cells = <2> 215 #interrupt-cells = <2>;
206 interrupt-controller; 216 interrupt-controller;
207 clocks = <&cpg CPG_MOD 217 clocks = <&cpg CPG_MOD 910>;
208 power-domains = <&sysc 218 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
209 resets = <&cpg 910>; 219 resets = <&cpg 910>;
210 }; 220 };
211 221
212 gpio3: gpio@e6053000 { 222 gpio3: gpio@e6053000 {
213 compatible = "renesas, 223 compatible = "renesas,gpio-r8a77990",
214 "renesas, 224 "renesas,rcar-gen3-gpio";
215 reg = <0 0xe6053000 0 225 reg = <0 0xe6053000 0 0x50>;
216 interrupts = <GIC_SPI 226 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
217 #gpio-cells = <2>; 227 #gpio-cells = <2>;
218 gpio-controller; 228 gpio-controller;
219 gpio-ranges = <&pfc 0 229 gpio-ranges = <&pfc 0 96 16>;
220 #interrupt-cells = <2> 230 #interrupt-cells = <2>;
221 interrupt-controller; 231 interrupt-controller;
222 clocks = <&cpg CPG_MOD 232 clocks = <&cpg CPG_MOD 909>;
223 power-domains = <&sysc 233 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
224 resets = <&cpg 909>; 234 resets = <&cpg 909>;
225 }; 235 };
226 236
227 gpio4: gpio@e6054000 { 237 gpio4: gpio@e6054000 {
228 compatible = "renesas, 238 compatible = "renesas,gpio-r8a77990",
229 "renesas, 239 "renesas,rcar-gen3-gpio";
230 reg = <0 0xe6054000 0 240 reg = <0 0xe6054000 0 0x50>;
231 interrupts = <GIC_SPI 241 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
232 #gpio-cells = <2>; 242 #gpio-cells = <2>;
233 gpio-controller; 243 gpio-controller;
234 gpio-ranges = <&pfc 0 244 gpio-ranges = <&pfc 0 128 11>;
235 #interrupt-cells = <2> 245 #interrupt-cells = <2>;
236 interrupt-controller; 246 interrupt-controller;
237 clocks = <&cpg CPG_MOD 247 clocks = <&cpg CPG_MOD 908>;
238 power-domains = <&sysc 248 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
239 resets = <&cpg 908>; 249 resets = <&cpg 908>;
240 }; 250 };
241 251
242 gpio5: gpio@e6055000 { 252 gpio5: gpio@e6055000 {
243 compatible = "renesas, 253 compatible = "renesas,gpio-r8a77990",
244 "renesas, 254 "renesas,rcar-gen3-gpio";
245 reg = <0 0xe6055000 0 255 reg = <0 0xe6055000 0 0x50>;
246 interrupts = <GIC_SPI 256 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
247 #gpio-cells = <2>; 257 #gpio-cells = <2>;
248 gpio-controller; 258 gpio-controller;
249 gpio-ranges = <&pfc 0 259 gpio-ranges = <&pfc 0 160 20>;
250 #interrupt-cells = <2> 260 #interrupt-cells = <2>;
251 interrupt-controller; 261 interrupt-controller;
252 clocks = <&cpg CPG_MOD 262 clocks = <&cpg CPG_MOD 907>;
253 power-domains = <&sysc 263 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
254 resets = <&cpg 907>; 264 resets = <&cpg 907>;
255 }; 265 };
256 266
257 gpio6: gpio@e6055400 { 267 gpio6: gpio@e6055400 {
258 compatible = "renesas, 268 compatible = "renesas,gpio-r8a77990",
259 "renesas, 269 "renesas,rcar-gen3-gpio";
260 reg = <0 0xe6055400 0 270 reg = <0 0xe6055400 0 0x50>;
261 interrupts = <GIC_SPI 271 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
262 #gpio-cells = <2>; 272 #gpio-cells = <2>;
263 gpio-controller; 273 gpio-controller;
264 gpio-ranges = <&pfc 0 274 gpio-ranges = <&pfc 0 192 18>;
265 #interrupt-cells = <2> 275 #interrupt-cells = <2>;
266 interrupt-controller; 276 interrupt-controller;
267 clocks = <&cpg CPG_MOD 277 clocks = <&cpg CPG_MOD 906>;
268 power-domains = <&sysc 278 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
269 resets = <&cpg 906>; 279 resets = <&cpg 906>;
270 }; 280 };
271 281
272 pfc: pinctrl@e6060000 { 282 pfc: pinctrl@e6060000 {
273 compatible = "renesas, 283 compatible = "renesas,pfc-r8a77990";
274 reg = <0 0xe6060000 0 284 reg = <0 0xe6060000 0 0x508>;
275 }; 285 };
276 286
277 i2c_dvfs: i2c@e60b0000 { 287 i2c_dvfs: i2c@e60b0000 {
278 #address-cells = <1>; 288 #address-cells = <1>;
279 #size-cells = <0>; 289 #size-cells = <0>;
280 compatible = "renesas, 290 compatible = "renesas,iic-r8a77990",
281 "renesas, 291 "renesas,rcar-gen3-iic",
282 "renesas, 292 "renesas,rmobile-iic";
283 reg = <0 0xe60b0000 0 293 reg = <0 0xe60b0000 0 0x425>;
284 interrupts = <GIC_SPI 294 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
285 clocks = <&cpg CPG_MOD 295 clocks = <&cpg CPG_MOD 926>;
286 power-domains = <&sysc 296 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
287 resets = <&cpg 926>; 297 resets = <&cpg 926>;
288 dmas = <&dmac0 0x11>, 298 dmas = <&dmac0 0x11>, <&dmac0 0x10>;
289 dma-names = "tx", "rx" 299 dma-names = "tx", "rx";
290 status = "disabled"; 300 status = "disabled";
291 }; 301 };
292 302
293 cmt0: timer@e60f0000 { 303 cmt0: timer@e60f0000 {
294 compatible = "renesas, 304 compatible = "renesas,r8a77990-cmt0",
295 "renesas, 305 "renesas,rcar-gen3-cmt0";
296 reg = <0 0xe60f0000 0 306 reg = <0 0xe60f0000 0 0x1004>;
297 interrupts = <GIC_SPI 307 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
298 <GIC_SPI 308 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
299 clocks = <&cpg CPG_MOD 309 clocks = <&cpg CPG_MOD 303>;
300 clock-names = "fck"; 310 clock-names = "fck";
301 power-domains = <&sysc 311 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
302 resets = <&cpg 303>; 312 resets = <&cpg 303>;
303 status = "disabled"; 313 status = "disabled";
304 }; 314 };
305 315
306 cmt1: timer@e6130000 { 316 cmt1: timer@e6130000 {
307 compatible = "renesas, 317 compatible = "renesas,r8a77990-cmt1",
308 "renesas, 318 "renesas,rcar-gen3-cmt1";
309 reg = <0 0xe6130000 0 319 reg = <0 0xe6130000 0 0x1004>;
310 interrupts = <GIC_SPI 320 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
311 <GIC_SPI 321 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
312 <GIC_SPI 322 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
313 <GIC_SPI 323 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
314 <GIC_SPI 324 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
315 <GIC_SPI 325 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
316 <GIC_SPI 326 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
317 <GIC_SPI 327 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
318 clocks = <&cpg CPG_MOD 328 clocks = <&cpg CPG_MOD 302>;
319 clock-names = "fck"; 329 clock-names = "fck";
320 power-domains = <&sysc 330 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
321 resets = <&cpg 302>; 331 resets = <&cpg 302>;
322 status = "disabled"; 332 status = "disabled";
323 }; 333 };
324 334
325 cmt2: timer@e6140000 { 335 cmt2: timer@e6140000 {
326 compatible = "renesas, 336 compatible = "renesas,r8a77990-cmt1",
327 "renesas, 337 "renesas,rcar-gen3-cmt1";
328 reg = <0 0xe6140000 0 338 reg = <0 0xe6140000 0 0x1004>;
329 interrupts = <GIC_SPI 339 interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
330 <GIC_SPI 340 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
331 <GIC_SPI 341 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
332 <GIC_SPI 342 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
333 <GIC_SPI 343 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
334 <GIC_SPI 344 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
335 <GIC_SPI 345 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
336 <GIC_SPI 346 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>;
337 clocks = <&cpg CPG_MOD 347 clocks = <&cpg CPG_MOD 301>;
338 clock-names = "fck"; 348 clock-names = "fck";
339 power-domains = <&sysc 349 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
340 resets = <&cpg 301>; 350 resets = <&cpg 301>;
341 status = "disabled"; 351 status = "disabled";
342 }; 352 };
343 353
344 cmt3: timer@e6148000 { 354 cmt3: timer@e6148000 {
345 compatible = "renesas, 355 compatible = "renesas,r8a77990-cmt1",
346 "renesas, 356 "renesas,rcar-gen3-cmt1";
347 reg = <0 0xe6148000 0 357 reg = <0 0xe6148000 0 0x1004>;
348 interrupts = <GIC_SPI 358 interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>,
349 <GIC_SPI 359 <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>,
350 <GIC_SPI 360 <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>,
351 <GIC_SPI 361 <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>,
352 <GIC_SPI 362 <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>,
353 <GIC_SPI 363 <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>,
354 <GIC_SPI 364 <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>,
355 <GIC_SPI 365 <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>;
356 clocks = <&cpg CPG_MOD 366 clocks = <&cpg CPG_MOD 300>;
357 clock-names = "fck"; 367 clock-names = "fck";
358 power-domains = <&sysc 368 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
359 resets = <&cpg 300>; 369 resets = <&cpg 300>;
360 status = "disabled"; 370 status = "disabled";
361 }; 371 };
362 372
363 cpg: clock-controller@e6150000 373 cpg: clock-controller@e6150000 {
364 compatible = "renesas, 374 compatible = "renesas,r8a77990-cpg-mssr";
365 reg = <0 0xe6150000 0 375 reg = <0 0xe6150000 0 0x1000>;
366 clocks = <&extal_clk>; 376 clocks = <&extal_clk>;
367 clock-names = "extal"; 377 clock-names = "extal";
368 #clock-cells = <2>; 378 #clock-cells = <2>;
369 #power-domain-cells = 379 #power-domain-cells = <0>;
370 #reset-cells = <1>; 380 #reset-cells = <1>;
371 }; 381 };
372 382
373 rst: reset-controller@e6160000 383 rst: reset-controller@e6160000 {
374 compatible = "renesas, 384 compatible = "renesas,r8a77990-rst";
375 reg = <0 0xe6160000 0 385 reg = <0 0xe6160000 0 0x0200>;
376 }; 386 };
377 387
378 sysc: system-controller@e61800 388 sysc: system-controller@e6180000 {
379 compatible = "renesas, 389 compatible = "renesas,r8a77990-sysc";
380 reg = <0 0xe6180000 0 390 reg = <0 0xe6180000 0 0x0400>;
381 #power-domain-cells = 391 #power-domain-cells = <1>;
382 }; 392 };
383 393
384 thermal: thermal@e6190000 { 394 thermal: thermal@e6190000 {
385 compatible = "renesas, 395 compatible = "renesas,thermal-r8a77990";
386 reg = <0 0xe6190000 0 396 reg = <0 0xe6190000 0 0x10>, <0 0xe6190100 0 0x38>;
387 interrupts = <GIC_SPI 397 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
388 <GIC_SPI 398 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
389 <GIC_SPI 399 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
390 clocks = <&cpg CPG_MOD 400 clocks = <&cpg CPG_MOD 522>;
391 power-domains = <&sysc 401 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
392 resets = <&cpg 522>; 402 resets = <&cpg 522>;
393 #thermal-sensor-cells 403 #thermal-sensor-cells = <0>;
394 }; 404 };
395 405
396 intc_ex: interrupt-controller@ 406 intc_ex: interrupt-controller@e61c0000 {
397 compatible = "renesas, 407 compatible = "renesas,intc-ex-r8a77990", "renesas,irqc";
398 #interrupt-cells = <2> 408 #interrupt-cells = <2>;
399 interrupt-controller; 409 interrupt-controller;
400 reg = <0 0xe61c0000 0 410 reg = <0 0xe61c0000 0 0x200>;
401 interrupts = <GIC_SPI 411 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
402 <GIC_SPI 412 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
403 <GIC_SPI 413 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
404 <GIC_SPI 414 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
405 <GIC_SPI 415 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
406 <GIC_SPI 416 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
407 clocks = <&cpg CPG_MOD 417 clocks = <&cpg CPG_MOD 407>;
408 power-domains = <&sysc 418 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
409 resets = <&cpg 407>; 419 resets = <&cpg 407>;
410 }; 420 };
411 421
412 tmu0: timer@e61e0000 { 422 tmu0: timer@e61e0000 {
413 compatible = "renesas, 423 compatible = "renesas,tmu-r8a77990", "renesas,tmu";
414 reg = <0 0xe61e0000 0 424 reg = <0 0xe61e0000 0 0x30>;
415 interrupts = <GIC_SPI 425 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
416 <GIC_SPI 426 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
417 <GIC_SPI 427 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
418 interrupt-names = "tun <<
419 clocks = <&cpg CPG_MOD 428 clocks = <&cpg CPG_MOD 125>;
420 clock-names = "fck"; 429 clock-names = "fck";
421 power-domains = <&sysc 430 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
422 resets = <&cpg 125>; 431 resets = <&cpg 125>;
423 status = "disabled"; 432 status = "disabled";
424 }; 433 };
425 434
426 tmu1: timer@e6fc0000 { 435 tmu1: timer@e6fc0000 {
427 compatible = "renesas, 436 compatible = "renesas,tmu-r8a77990", "renesas,tmu";
428 reg = <0 0xe6fc0000 0 437 reg = <0 0xe6fc0000 0 0x30>;
429 interrupts = <GIC_SPI 438 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
430 <GIC_SPI 439 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
431 <GIC_SPI !! 440 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
432 <GIC_SPI <<
433 interrupt-names = "tun <<
434 clocks = <&cpg CPG_MOD 441 clocks = <&cpg CPG_MOD 124>;
435 clock-names = "fck"; 442 clock-names = "fck";
436 power-domains = <&sysc 443 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
437 resets = <&cpg 124>; 444 resets = <&cpg 124>;
438 status = "disabled"; 445 status = "disabled";
439 }; 446 };
440 447
441 tmu2: timer@e6fd0000 { 448 tmu2: timer@e6fd0000 {
442 compatible = "renesas, 449 compatible = "renesas,tmu-r8a77990", "renesas,tmu";
443 reg = <0 0xe6fd0000 0 450 reg = <0 0xe6fd0000 0 0x30>;
444 interrupts = <GIC_SPI 451 interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>,
445 <GIC_SPI 452 <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
446 <GIC_SPI !! 453 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
447 <GIC_SPI <<
448 interrupt-names = "tun <<
449 clocks = <&cpg CPG_MOD 454 clocks = <&cpg CPG_MOD 123>;
450 clock-names = "fck"; 455 clock-names = "fck";
451 power-domains = <&sysc 456 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
452 resets = <&cpg 123>; 457 resets = <&cpg 123>;
453 status = "disabled"; 458 status = "disabled";
454 }; 459 };
455 460
456 tmu3: timer@e6fe0000 { 461 tmu3: timer@e6fe0000 {
457 compatible = "renesas, 462 compatible = "renesas,tmu-r8a77990", "renesas,tmu";
458 reg = <0 0xe6fe0000 0 463 reg = <0 0xe6fe0000 0 0x30>;
459 interrupts = <GIC_SPI 464 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
460 <GIC_SPI 465 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
461 <GIC_SPI 466 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
462 interrupt-names = "tun <<
463 clocks = <&cpg CPG_MOD 467 clocks = <&cpg CPG_MOD 122>;
464 clock-names = "fck"; 468 clock-names = "fck";
465 power-domains = <&sysc 469 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
466 resets = <&cpg 122>; 470 resets = <&cpg 122>;
467 status = "disabled"; 471 status = "disabled";
468 }; 472 };
469 473
470 tmu4: timer@ffc00000 { 474 tmu4: timer@ffc00000 {
471 compatible = "renesas, 475 compatible = "renesas,tmu-r8a77990", "renesas,tmu";
472 reg = <0 0xffc00000 0 476 reg = <0 0xffc00000 0 0x30>;
473 interrupts = <GIC_SPI 477 interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
474 <GIC_SPI 478 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
475 <GIC_SPI 479 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>;
476 interrupt-names = "tun <<
477 clocks = <&cpg CPG_MOD 480 clocks = <&cpg CPG_MOD 121>;
478 clock-names = "fck"; 481 clock-names = "fck";
479 power-domains = <&sysc 482 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
480 resets = <&cpg 121>; 483 resets = <&cpg 121>;
481 status = "disabled"; 484 status = "disabled";
482 }; 485 };
483 486
484 i2c0: i2c@e6500000 { 487 i2c0: i2c@e6500000 {
485 #address-cells = <1>; 488 #address-cells = <1>;
486 #size-cells = <0>; 489 #size-cells = <0>;
487 compatible = "renesas, 490 compatible = "renesas,i2c-r8a77990",
488 "renesas, 491 "renesas,rcar-gen3-i2c";
489 reg = <0 0xe6500000 0 492 reg = <0 0xe6500000 0 0x40>;
490 interrupts = <GIC_SPI 493 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
491 clocks = <&cpg CPG_MOD 494 clocks = <&cpg CPG_MOD 931>;
492 power-domains = <&sysc 495 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
493 resets = <&cpg 931>; 496 resets = <&cpg 931>;
494 dmas = <&dmac1 0x91>, 497 dmas = <&dmac1 0x91>, <&dmac1 0x90>,
495 <&dmac2 0x91>, 498 <&dmac2 0x91>, <&dmac2 0x90>;
496 dma-names = "tx", "rx" 499 dma-names = "tx", "rx", "tx", "rx";
497 i2c-scl-internal-delay 500 i2c-scl-internal-delay-ns = <110>;
498 status = "disabled"; 501 status = "disabled";
499 }; 502 };
500 503
501 i2c1: i2c@e6508000 { 504 i2c1: i2c@e6508000 {
502 #address-cells = <1>; 505 #address-cells = <1>;
503 #size-cells = <0>; 506 #size-cells = <0>;
504 compatible = "renesas, 507 compatible = "renesas,i2c-r8a77990",
505 "renesas, 508 "renesas,rcar-gen3-i2c";
506 reg = <0 0xe6508000 0 509 reg = <0 0xe6508000 0 0x40>;
507 interrupts = <GIC_SPI 510 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
508 clocks = <&cpg CPG_MOD 511 clocks = <&cpg CPG_MOD 930>;
509 power-domains = <&sysc 512 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
510 resets = <&cpg 930>; 513 resets = <&cpg 930>;
511 dmas = <&dmac1 0x93>, 514 dmas = <&dmac1 0x93>, <&dmac1 0x92>,
512 <&dmac2 0x93>, 515 <&dmac2 0x93>, <&dmac2 0x92>;
513 dma-names = "tx", "rx" 516 dma-names = "tx", "rx", "tx", "rx";
514 i2c-scl-internal-delay 517 i2c-scl-internal-delay-ns = <6>;
515 status = "disabled"; 518 status = "disabled";
516 }; 519 };
517 520
518 i2c2: i2c@e6510000 { 521 i2c2: i2c@e6510000 {
519 #address-cells = <1>; 522 #address-cells = <1>;
520 #size-cells = <0>; 523 #size-cells = <0>;
521 compatible = "renesas, 524 compatible = "renesas,i2c-r8a77990",
522 "renesas, 525 "renesas,rcar-gen3-i2c";
523 reg = <0 0xe6510000 0 526 reg = <0 0xe6510000 0 0x40>;
524 interrupts = <GIC_SPI 527 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
525 clocks = <&cpg CPG_MOD 528 clocks = <&cpg CPG_MOD 929>;
526 power-domains = <&sysc 529 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
527 resets = <&cpg 929>; 530 resets = <&cpg 929>;
528 dmas = <&dmac1 0x95>, 531 dmas = <&dmac1 0x95>, <&dmac1 0x94>,
529 <&dmac2 0x95>, 532 <&dmac2 0x95>, <&dmac2 0x94>;
530 dma-names = "tx", "rx" 533 dma-names = "tx", "rx", "tx", "rx";
531 i2c-scl-internal-delay 534 i2c-scl-internal-delay-ns = <6>;
532 status = "disabled"; 535 status = "disabled";
533 }; 536 };
534 537
535 i2c3: i2c@e66d0000 { 538 i2c3: i2c@e66d0000 {
536 #address-cells = <1>; 539 #address-cells = <1>;
537 #size-cells = <0>; 540 #size-cells = <0>;
538 compatible = "renesas, 541 compatible = "renesas,i2c-r8a77990",
539 "renesas, 542 "renesas,rcar-gen3-i2c";
540 reg = <0 0xe66d0000 0 543 reg = <0 0xe66d0000 0 0x40>;
541 interrupts = <GIC_SPI 544 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
542 clocks = <&cpg CPG_MOD 545 clocks = <&cpg CPG_MOD 928>;
543 power-domains = <&sysc 546 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
544 resets = <&cpg 928>; 547 resets = <&cpg 928>;
545 dmas = <&dmac0 0x97>, 548 dmas = <&dmac0 0x97>, <&dmac0 0x96>;
546 dma-names = "tx", "rx" 549 dma-names = "tx", "rx";
547 i2c-scl-internal-delay 550 i2c-scl-internal-delay-ns = <110>;
548 status = "disabled"; 551 status = "disabled";
549 }; 552 };
550 553
551 i2c4: i2c@e66d8000 { 554 i2c4: i2c@e66d8000 {
552 #address-cells = <1>; 555 #address-cells = <1>;
553 #size-cells = <0>; 556 #size-cells = <0>;
554 compatible = "renesas, 557 compatible = "renesas,i2c-r8a77990",
555 "renesas, 558 "renesas,rcar-gen3-i2c";
556 reg = <0 0xe66d8000 0 559 reg = <0 0xe66d8000 0 0x40>;
557 interrupts = <GIC_SPI 560 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
558 clocks = <&cpg CPG_MOD 561 clocks = <&cpg CPG_MOD 927>;
559 power-domains = <&sysc 562 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
560 resets = <&cpg 927>; 563 resets = <&cpg 927>;
561 dmas = <&dmac0 0x99>, 564 dmas = <&dmac0 0x99>, <&dmac0 0x98>;
562 dma-names = "tx", "rx" 565 dma-names = "tx", "rx";
563 i2c-scl-internal-delay 566 i2c-scl-internal-delay-ns = <6>;
564 status = "disabled"; 567 status = "disabled";
565 }; 568 };
566 569
567 i2c5: i2c@e66e0000 { 570 i2c5: i2c@e66e0000 {
568 #address-cells = <1>; 571 #address-cells = <1>;
569 #size-cells = <0>; 572 #size-cells = <0>;
570 compatible = "renesas, 573 compatible = "renesas,i2c-r8a77990",
571 "renesas, 574 "renesas,rcar-gen3-i2c";
572 reg = <0 0xe66e0000 0 575 reg = <0 0xe66e0000 0 0x40>;
573 interrupts = <GIC_SPI 576 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
574 clocks = <&cpg CPG_MOD 577 clocks = <&cpg CPG_MOD 919>;
575 power-domains = <&sysc 578 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
576 resets = <&cpg 919>; 579 resets = <&cpg 919>;
577 dmas = <&dmac0 0x9b>, 580 dmas = <&dmac0 0x9b>, <&dmac0 0x9a>;
578 dma-names = "tx", "rx" 581 dma-names = "tx", "rx";
579 i2c-scl-internal-delay 582 i2c-scl-internal-delay-ns = <6>;
580 status = "disabled"; 583 status = "disabled";
581 }; 584 };
582 585
583 i2c6: i2c@e66e8000 { 586 i2c6: i2c@e66e8000 {
584 #address-cells = <1>; 587 #address-cells = <1>;
585 #size-cells = <0>; 588 #size-cells = <0>;
586 compatible = "renesas, 589 compatible = "renesas,i2c-r8a77990",
587 "renesas, 590 "renesas,rcar-gen3-i2c";
588 reg = <0 0xe66e8000 0 591 reg = <0 0xe66e8000 0 0x40>;
589 interrupts = <GIC_SPI 592 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
590 clocks = <&cpg CPG_MOD 593 clocks = <&cpg CPG_MOD 918>;
591 power-domains = <&sysc 594 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
592 resets = <&cpg 918>; 595 resets = <&cpg 918>;
593 dmas = <&dmac0 0x9d>, 596 dmas = <&dmac0 0x9d>, <&dmac0 0x9c>;
594 dma-names = "tx", "rx" 597 dma-names = "tx", "rx";
595 i2c-scl-internal-delay 598 i2c-scl-internal-delay-ns = <6>;
596 status = "disabled"; 599 status = "disabled";
597 }; 600 };
598 601
599 i2c7: i2c@e6690000 { 602 i2c7: i2c@e6690000 {
600 #address-cells = <1>; 603 #address-cells = <1>;
601 #size-cells = <0>; 604 #size-cells = <0>;
602 compatible = "renesas, 605 compatible = "renesas,i2c-r8a77990",
603 "renesas, 606 "renesas,rcar-gen3-i2c";
604 reg = <0 0xe6690000 0 607 reg = <0 0xe6690000 0 0x40>;
605 interrupts = <GIC_SPI 608 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
606 clocks = <&cpg CPG_MOD 609 clocks = <&cpg CPG_MOD 1003>;
607 power-domains = <&sysc 610 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
608 resets = <&cpg 1003>; 611 resets = <&cpg 1003>;
609 i2c-scl-internal-delay 612 i2c-scl-internal-delay-ns = <6>;
610 status = "disabled"; 613 status = "disabled";
611 }; 614 };
612 615
613 hscif0: serial@e6540000 { 616 hscif0: serial@e6540000 {
614 compatible = "renesas, 617 compatible = "renesas,hscif-r8a77990",
615 "renesas, 618 "renesas,rcar-gen3-hscif",
616 "renesas, 619 "renesas,hscif";
617 reg = <0 0xe6540000 0 620 reg = <0 0xe6540000 0 0x60>;
618 interrupts = <GIC_SPI 621 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
619 clocks = <&cpg CPG_MOD 622 clocks = <&cpg CPG_MOD 520>,
620 <&cpg CPG_COR 623 <&cpg CPG_CORE R8A77990_CLK_S3D1C>,
621 <&scif_clk>; 624 <&scif_clk>;
622 clock-names = "fck", " 625 clock-names = "fck", "brg_int", "scif_clk";
623 dmas = <&dmac1 0x31>, 626 dmas = <&dmac1 0x31>, <&dmac1 0x30>,
624 <&dmac2 0x31>, 627 <&dmac2 0x31>, <&dmac2 0x30>;
625 dma-names = "tx", "rx" 628 dma-names = "tx", "rx", "tx", "rx";
626 power-domains = <&sysc 629 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
627 resets = <&cpg 520>; 630 resets = <&cpg 520>;
628 status = "disabled"; 631 status = "disabled";
629 }; 632 };
630 633
631 hscif1: serial@e6550000 { 634 hscif1: serial@e6550000 {
632 compatible = "renesas, 635 compatible = "renesas,hscif-r8a77990",
633 "renesas, 636 "renesas,rcar-gen3-hscif",
634 "renesas, 637 "renesas,hscif";
635 reg = <0 0xe6550000 0 638 reg = <0 0xe6550000 0 0x60>;
636 interrupts = <GIC_SPI 639 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
637 clocks = <&cpg CPG_MOD 640 clocks = <&cpg CPG_MOD 519>,
638 <&cpg CPG_COR 641 <&cpg CPG_CORE R8A77990_CLK_S3D1C>,
639 <&scif_clk>; 642 <&scif_clk>;
640 clock-names = "fck", " 643 clock-names = "fck", "brg_int", "scif_clk";
641 dmas = <&dmac1 0x33>, 644 dmas = <&dmac1 0x33>, <&dmac1 0x32>,
642 <&dmac2 0x33>, 645 <&dmac2 0x33>, <&dmac2 0x32>;
643 dma-names = "tx", "rx" 646 dma-names = "tx", "rx", "tx", "rx";
644 power-domains = <&sysc 647 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
645 resets = <&cpg 519>; 648 resets = <&cpg 519>;
646 status = "disabled"; 649 status = "disabled";
647 }; 650 };
648 651
649 hscif2: serial@e6560000 { 652 hscif2: serial@e6560000 {
650 compatible = "renesas, 653 compatible = "renesas,hscif-r8a77990",
651 "renesas, 654 "renesas,rcar-gen3-hscif",
652 "renesas, 655 "renesas,hscif";
653 reg = <0 0xe6560000 0 656 reg = <0 0xe6560000 0 0x60>;
654 interrupts = <GIC_SPI 657 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
655 clocks = <&cpg CPG_MOD 658 clocks = <&cpg CPG_MOD 518>,
656 <&cpg CPG_COR 659 <&cpg CPG_CORE R8A77990_CLK_S3D1C>,
657 <&scif_clk>; 660 <&scif_clk>;
658 clock-names = "fck", " 661 clock-names = "fck", "brg_int", "scif_clk";
659 dmas = <&dmac1 0x35>, 662 dmas = <&dmac1 0x35>, <&dmac1 0x34>,
660 <&dmac2 0x35>, 663 <&dmac2 0x35>, <&dmac2 0x34>;
661 dma-names = "tx", "rx" 664 dma-names = "tx", "rx", "tx", "rx";
662 power-domains = <&sysc 665 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
663 resets = <&cpg 518>; 666 resets = <&cpg 518>;
664 status = "disabled"; 667 status = "disabled";
665 }; 668 };
666 669
667 hscif3: serial@e66a0000 { 670 hscif3: serial@e66a0000 {
668 compatible = "renesas, 671 compatible = "renesas,hscif-r8a77990",
669 "renesas, 672 "renesas,rcar-gen3-hscif",
670 "renesas, 673 "renesas,hscif";
671 reg = <0 0xe66a0000 0 674 reg = <0 0xe66a0000 0 0x60>;
672 interrupts = <GIC_SPI 675 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
673 clocks = <&cpg CPG_MOD 676 clocks = <&cpg CPG_MOD 517>,
674 <&cpg CPG_COR 677 <&cpg CPG_CORE R8A77990_CLK_S3D1C>,
675 <&scif_clk>; 678 <&scif_clk>;
676 clock-names = "fck", " 679 clock-names = "fck", "brg_int", "scif_clk";
677 dmas = <&dmac0 0x37>, 680 dmas = <&dmac0 0x37>, <&dmac0 0x36>;
678 dma-names = "tx", "rx" 681 dma-names = "tx", "rx";
679 power-domains = <&sysc 682 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
680 resets = <&cpg 517>; 683 resets = <&cpg 517>;
681 status = "disabled"; 684 status = "disabled";
682 }; 685 };
683 686
684 hscif4: serial@e66b0000 { 687 hscif4: serial@e66b0000 {
685 compatible = "renesas, 688 compatible = "renesas,hscif-r8a77990",
686 "renesas, 689 "renesas,rcar-gen3-hscif",
687 "renesas, 690 "renesas,hscif";
688 reg = <0 0xe66b0000 0 691 reg = <0 0xe66b0000 0 0x60>;
689 interrupts = <GIC_SPI 692 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
690 clocks = <&cpg CPG_MOD 693 clocks = <&cpg CPG_MOD 516>,
691 <&cpg CPG_COR 694 <&cpg CPG_CORE R8A77990_CLK_S3D1C>,
692 <&scif_clk>; 695 <&scif_clk>;
693 clock-names = "fck", " 696 clock-names = "fck", "brg_int", "scif_clk";
694 dmas = <&dmac0 0x39>, 697 dmas = <&dmac0 0x39>, <&dmac0 0x38>;
695 dma-names = "tx", "rx" 698 dma-names = "tx", "rx";
696 power-domains = <&sysc 699 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
697 resets = <&cpg 516>; 700 resets = <&cpg 516>;
698 status = "disabled"; 701 status = "disabled";
699 }; 702 };
700 703
701 hsusb: usb@e6590000 { 704 hsusb: usb@e6590000 {
702 compatible = "renesas, 705 compatible = "renesas,usbhs-r8a77990",
703 "renesas, 706 "renesas,rcar-gen3-usbhs";
704 reg = <0 0xe6590000 0 707 reg = <0 0xe6590000 0 0x200>;
705 interrupts = <GIC_SPI 708 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
706 clocks = <&cpg CPG_MOD 709 clocks = <&cpg CPG_MOD 704>, <&cpg CPG_MOD 703>;
707 dmas = <&usb_dmac0 0>, 710 dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
708 <&usb_dmac1 0>, 711 <&usb_dmac1 0>, <&usb_dmac1 1>;
709 dma-names = "ch0", "ch 712 dma-names = "ch0", "ch1", "ch2", "ch3";
710 renesas,buswait = <11> 713 renesas,buswait = <11>;
711 phys = <&usb2_phy0 3>; 714 phys = <&usb2_phy0 3>;
712 phy-names = "usb"; 715 phy-names = "usb";
713 power-domains = <&sysc 716 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
714 resets = <&cpg 704>, < 717 resets = <&cpg 704>, <&cpg 703>;
715 status = "disabled"; 718 status = "disabled";
716 }; 719 };
717 720
718 usb_dmac0: dma-controller@e65a 721 usb_dmac0: dma-controller@e65a0000 {
719 compatible = "renesas, 722 compatible = "renesas,r8a77990-usb-dmac",
720 "renesas, 723 "renesas,usb-dmac";
721 reg = <0 0xe65a0000 0 724 reg = <0 0xe65a0000 0 0x100>;
722 interrupts = <GIC_SPI 725 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
723 <GIC_SPI 726 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
724 interrupt-names = "ch0 727 interrupt-names = "ch0", "ch1";
725 clocks = <&cpg CPG_MOD 728 clocks = <&cpg CPG_MOD 330>;
726 power-domains = <&sysc 729 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
727 resets = <&cpg 330>; 730 resets = <&cpg 330>;
728 #dma-cells = <1>; 731 #dma-cells = <1>;
729 dma-channels = <2>; 732 dma-channels = <2>;
730 }; 733 };
731 734
732 usb_dmac1: dma-controller@e65b 735 usb_dmac1: dma-controller@e65b0000 {
733 compatible = "renesas, 736 compatible = "renesas,r8a77990-usb-dmac",
734 "renesas, 737 "renesas,usb-dmac";
735 reg = <0 0xe65b0000 0 738 reg = <0 0xe65b0000 0 0x100>;
736 interrupts = <GIC_SPI 739 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
737 <GIC_SPI 740 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
738 interrupt-names = "ch0 741 interrupt-names = "ch0", "ch1";
739 clocks = <&cpg CPG_MOD 742 clocks = <&cpg CPG_MOD 331>;
740 power-domains = <&sysc 743 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
741 resets = <&cpg 331>; 744 resets = <&cpg 331>;
742 #dma-cells = <1>; 745 #dma-cells = <1>;
743 dma-channels = <2>; 746 dma-channels = <2>;
744 }; 747 };
745 748
746 arm_cc630p: crypto@e6601000 { 749 arm_cc630p: crypto@e6601000 {
747 compatible = "arm,cryp 750 compatible = "arm,cryptocell-630p-ree";
748 interrupts = <GIC_SPI 751 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
749 reg = <0x0 0xe6601000 752 reg = <0x0 0xe6601000 0 0x1000>;
750 clocks = <&cpg CPG_MOD 753 clocks = <&cpg CPG_MOD 229>;
751 resets = <&cpg 229>; 754 resets = <&cpg 229>;
752 power-domains = <&sysc 755 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
753 }; 756 };
754 757
755 dmac0: dma-controller@e6700000 758 dmac0: dma-controller@e6700000 {
756 compatible = "renesas, 759 compatible = "renesas,dmac-r8a77990",
757 "renesas, 760 "renesas,rcar-dmac";
758 reg = <0 0xe6700000 0 761 reg = <0 0xe6700000 0 0x10000>;
759 interrupts = <GIC_SPI 762 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
760 <GIC_SPI 763 <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
761 <GIC_SPI 764 <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
762 <GIC_SPI 765 <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
763 <GIC_SPI 766 <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
764 <GIC_SPI 767 <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
765 <GIC_SPI 768 <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
766 <GIC_SPI 769 <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
767 <GIC_SPI 770 <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
768 <GIC_SPI 771 <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
769 <GIC_SPI 772 <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>,
770 <GIC_SPI 773 <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
771 <GIC_SPI 774 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
772 <GIC_SPI 775 <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
773 <GIC_SPI 776 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
774 <GIC_SPI 777 <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
775 <GIC_SPI 778 <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>;
776 interrupt-names = "err 779 interrupt-names = "error",
777 "ch0", 780 "ch0", "ch1", "ch2", "ch3",
778 "ch4", 781 "ch4", "ch5", "ch6", "ch7",
779 "ch8", 782 "ch8", "ch9", "ch10", "ch11",
780 "ch12" 783 "ch12", "ch13", "ch14", "ch15";
781 clocks = <&cpg CPG_MOD 784 clocks = <&cpg CPG_MOD 219>;
782 clock-names = "fck"; 785 clock-names = "fck";
783 power-domains = <&sysc 786 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
784 resets = <&cpg 219>; 787 resets = <&cpg 219>;
785 #dma-cells = <1>; 788 #dma-cells = <1>;
786 dma-channels = <16>; 789 dma-channels = <16>;
787 iommus = <&ipmmu_ds0 0 790 iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>,
788 <&ipmmu_ds0 2>, 791 <&ipmmu_ds0 2>, <&ipmmu_ds0 3>,
789 <&ipmmu_ds0 4>, 792 <&ipmmu_ds0 4>, <&ipmmu_ds0 5>,
790 <&ipmmu_ds0 6>, 793 <&ipmmu_ds0 6>, <&ipmmu_ds0 7>,
791 <&ipmmu_ds0 8>, 794 <&ipmmu_ds0 8>, <&ipmmu_ds0 9>,
792 <&ipmmu_ds0 10> 795 <&ipmmu_ds0 10>, <&ipmmu_ds0 11>,
793 <&ipmmu_ds0 12> 796 <&ipmmu_ds0 12>, <&ipmmu_ds0 13>,
794 <&ipmmu_ds0 14> 797 <&ipmmu_ds0 14>, <&ipmmu_ds0 15>;
795 }; 798 };
796 799
797 dmac1: dma-controller@e7300000 800 dmac1: dma-controller@e7300000 {
798 compatible = "renesas, 801 compatible = "renesas,dmac-r8a77990",
799 "renesas, 802 "renesas,rcar-dmac";
800 reg = <0 0xe7300000 0 803 reg = <0 0xe7300000 0 0x10000>;
801 interrupts = <GIC_SPI 804 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
802 <GIC_SPI 805 <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
803 <GIC_SPI 806 <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
804 <GIC_SPI 807 <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
805 <GIC_SPI 808 <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
806 <GIC_SPI 809 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
807 <GIC_SPI 810 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
808 <GIC_SPI 811 <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
809 <GIC_SPI 812 <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>,
810 <GIC_SPI 813 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
811 <GIC_SPI 814 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
812 <GIC_SPI 815 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
813 <GIC_SPI 816 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
814 <GIC_SPI 817 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
815 <GIC_SPI 818 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
816 <GIC_SPI 819 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
817 <GIC_SPI 820 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>;
818 interrupt-names = "err 821 interrupt-names = "error",
819 "ch0", 822 "ch0", "ch1", "ch2", "ch3",
820 "ch4", 823 "ch4", "ch5", "ch6", "ch7",
821 "ch8", 824 "ch8", "ch9", "ch10", "ch11",
822 "ch12" 825 "ch12", "ch13", "ch14", "ch15";
823 clocks = <&cpg CPG_MOD 826 clocks = <&cpg CPG_MOD 218>;
824 clock-names = "fck"; 827 clock-names = "fck";
825 power-domains = <&sysc 828 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
826 resets = <&cpg 218>; 829 resets = <&cpg 218>;
827 #dma-cells = <1>; 830 #dma-cells = <1>;
828 dma-channels = <16>; 831 dma-channels = <16>;
829 iommus = <&ipmmu_ds1 0 832 iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>,
830 <&ipmmu_ds1 2>, 833 <&ipmmu_ds1 2>, <&ipmmu_ds1 3>,
831 <&ipmmu_ds1 4>, 834 <&ipmmu_ds1 4>, <&ipmmu_ds1 5>,
832 <&ipmmu_ds1 6>, 835 <&ipmmu_ds1 6>, <&ipmmu_ds1 7>,
833 <&ipmmu_ds1 8>, 836 <&ipmmu_ds1 8>, <&ipmmu_ds1 9>,
834 <&ipmmu_ds1 10> 837 <&ipmmu_ds1 10>, <&ipmmu_ds1 11>,
835 <&ipmmu_ds1 12> 838 <&ipmmu_ds1 12>, <&ipmmu_ds1 13>,
836 <&ipmmu_ds1 14> 839 <&ipmmu_ds1 14>, <&ipmmu_ds1 15>;
837 }; 840 };
838 841
839 dmac2: dma-controller@e7310000 842 dmac2: dma-controller@e7310000 {
840 compatible = "renesas, 843 compatible = "renesas,dmac-r8a77990",
841 "renesas, 844 "renesas,rcar-dmac";
842 reg = <0 0xe7310000 0 845 reg = <0 0xe7310000 0 0x10000>;
843 interrupts = <GIC_SPI 846 interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
844 <GIC_SPI 847 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
845 <GIC_SPI 848 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
846 <GIC_SPI 849 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
847 <GIC_SPI 850 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
848 <GIC_SPI 851 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
849 <GIC_SPI 852 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
850 <GIC_SPI 853 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
851 <GIC_SPI 854 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
852 <GIC_SPI 855 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
853 <GIC_SPI 856 <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>,
854 <GIC_SPI 857 <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>,
855 <GIC_SPI 858 <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>,
856 <GIC_SPI 859 <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>,
857 <GIC_SPI 860 <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>,
858 <GIC_SPI 861 <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH>,
859 <GIC_SPI 862 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>;
860 interrupt-names = "err 863 interrupt-names = "error",
861 "ch0", 864 "ch0", "ch1", "ch2", "ch3",
862 "ch4", 865 "ch4", "ch5", "ch6", "ch7",
863 "ch8", 866 "ch8", "ch9", "ch10", "ch11",
864 "ch12" 867 "ch12", "ch13", "ch14", "ch15";
865 clocks = <&cpg CPG_MOD 868 clocks = <&cpg CPG_MOD 217>;
866 clock-names = "fck"; 869 clock-names = "fck";
867 power-domains = <&sysc 870 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
868 resets = <&cpg 217>; 871 resets = <&cpg 217>;
869 #dma-cells = <1>; 872 #dma-cells = <1>;
870 dma-channels = <16>; 873 dma-channels = <16>;
871 iommus = <&ipmmu_ds1 1 874 iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>,
872 <&ipmmu_ds1 18> 875 <&ipmmu_ds1 18>, <&ipmmu_ds1 19>,
873 <&ipmmu_ds1 20> 876 <&ipmmu_ds1 20>, <&ipmmu_ds1 21>,
874 <&ipmmu_ds1 22> 877 <&ipmmu_ds1 22>, <&ipmmu_ds1 23>,
875 <&ipmmu_ds1 24> 878 <&ipmmu_ds1 24>, <&ipmmu_ds1 25>,
876 <&ipmmu_ds1 26> 879 <&ipmmu_ds1 26>, <&ipmmu_ds1 27>,
877 <&ipmmu_ds1 28> 880 <&ipmmu_ds1 28>, <&ipmmu_ds1 29>,
878 <&ipmmu_ds1 30> 881 <&ipmmu_ds1 30>, <&ipmmu_ds1 31>;
879 }; 882 };
880 883
881 ipmmu_ds0: iommu@e6740000 { 884 ipmmu_ds0: iommu@e6740000 {
882 compatible = "renesas, 885 compatible = "renesas,ipmmu-r8a77990";
883 reg = <0 0xe6740000 0 886 reg = <0 0xe6740000 0 0x1000>;
884 renesas,ipmmu-main = < 887 renesas,ipmmu-main = <&ipmmu_mm 0>;
885 power-domains = <&sysc 888 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
886 #iommu-cells = <1>; 889 #iommu-cells = <1>;
887 }; 890 };
888 891
889 ipmmu_ds1: iommu@e7740000 { 892 ipmmu_ds1: iommu@e7740000 {
890 compatible = "renesas, 893 compatible = "renesas,ipmmu-r8a77990";
891 reg = <0 0xe7740000 0 894 reg = <0 0xe7740000 0 0x1000>;
892 renesas,ipmmu-main = < 895 renesas,ipmmu-main = <&ipmmu_mm 1>;
893 power-domains = <&sysc 896 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
894 #iommu-cells = <1>; 897 #iommu-cells = <1>;
895 }; 898 };
896 899
897 ipmmu_hc: iommu@e6570000 { 900 ipmmu_hc: iommu@e6570000 {
898 compatible = "renesas, 901 compatible = "renesas,ipmmu-r8a77990";
899 reg = <0 0xe6570000 0 902 reg = <0 0xe6570000 0 0x1000>;
900 renesas,ipmmu-main = < 903 renesas,ipmmu-main = <&ipmmu_mm 2>;
901 power-domains = <&sysc 904 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
902 #iommu-cells = <1>; 905 #iommu-cells = <1>;
903 }; 906 };
904 907
905 ipmmu_mm: iommu@e67b0000 { 908 ipmmu_mm: iommu@e67b0000 {
906 compatible = "renesas, 909 compatible = "renesas,ipmmu-r8a77990";
907 reg = <0 0xe67b0000 0 910 reg = <0 0xe67b0000 0 0x1000>;
908 interrupts = <GIC_SPI 911 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
909 <GIC_SPI 912 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
910 power-domains = <&sysc 913 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
911 #iommu-cells = <1>; 914 #iommu-cells = <1>;
912 }; 915 };
913 916
914 ipmmu_mp: iommu@ec670000 { 917 ipmmu_mp: iommu@ec670000 {
915 compatible = "renesas, 918 compatible = "renesas,ipmmu-r8a77990";
916 reg = <0 0xec670000 0 919 reg = <0 0xec670000 0 0x1000>;
917 renesas,ipmmu-main = < 920 renesas,ipmmu-main = <&ipmmu_mm 4>;
918 power-domains = <&sysc 921 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
919 #iommu-cells = <1>; 922 #iommu-cells = <1>;
920 }; 923 };
921 924
922 ipmmu_pv0: iommu@fd800000 { 925 ipmmu_pv0: iommu@fd800000 {
923 compatible = "renesas, 926 compatible = "renesas,ipmmu-r8a77990";
924 reg = <0 0xfd800000 0 927 reg = <0 0xfd800000 0 0x1000>;
925 renesas,ipmmu-main = < 928 renesas,ipmmu-main = <&ipmmu_mm 6>;
926 power-domains = <&sysc 929 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
927 #iommu-cells = <1>; 930 #iommu-cells = <1>;
928 }; 931 };
929 932
930 ipmmu_rt: iommu@ffc80000 { 933 ipmmu_rt: iommu@ffc80000 {
931 compatible = "renesas, 934 compatible = "renesas,ipmmu-r8a77990";
932 reg = <0 0xffc80000 0 935 reg = <0 0xffc80000 0 0x1000>;
933 renesas,ipmmu-main = < 936 renesas,ipmmu-main = <&ipmmu_mm 10>;
934 power-domains = <&sysc 937 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
935 #iommu-cells = <1>; 938 #iommu-cells = <1>;
936 }; 939 };
937 940
938 ipmmu_vc0: iommu@fe6b0000 { 941 ipmmu_vc0: iommu@fe6b0000 {
939 compatible = "renesas, 942 compatible = "renesas,ipmmu-r8a77990";
940 reg = <0 0xfe6b0000 0 943 reg = <0 0xfe6b0000 0 0x1000>;
941 renesas,ipmmu-main = < 944 renesas,ipmmu-main = <&ipmmu_mm 12>;
942 power-domains = <&sysc 945 power-domains = <&sysc R8A77990_PD_A3VC>;
943 #iommu-cells = <1>; 946 #iommu-cells = <1>;
944 }; 947 };
945 948
946 ipmmu_vi0: iommu@febd0000 { 949 ipmmu_vi0: iommu@febd0000 {
947 compatible = "renesas, 950 compatible = "renesas,ipmmu-r8a77990";
948 reg = <0 0xfebd0000 0 951 reg = <0 0xfebd0000 0 0x1000>;
949 renesas,ipmmu-main = < 952 renesas,ipmmu-main = <&ipmmu_mm 14>;
950 power-domains = <&sysc 953 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
951 #iommu-cells = <1>; 954 #iommu-cells = <1>;
952 }; 955 };
953 956
954 ipmmu_vp0: iommu@fe990000 { 957 ipmmu_vp0: iommu@fe990000 {
955 compatible = "renesas, 958 compatible = "renesas,ipmmu-r8a77990";
956 reg = <0 0xfe990000 0 959 reg = <0 0xfe990000 0 0x1000>;
957 renesas,ipmmu-main = < 960 renesas,ipmmu-main = <&ipmmu_mm 16>;
958 power-domains = <&sysc 961 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
959 #iommu-cells = <1>; 962 #iommu-cells = <1>;
960 }; 963 };
961 964
962 avb: ethernet@e6800000 { 965 avb: ethernet@e6800000 {
963 compatible = "renesas, 966 compatible = "renesas,etheravb-r8a77990",
964 "renesas, 967 "renesas,etheravb-rcar-gen3";
965 reg = <0 0xe6800000 0 968 reg = <0 0xe6800000 0 0x800>;
966 interrupts = <GIC_SPI 969 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
967 <GIC_SPI 970 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
968 <GIC_SPI 971 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
969 <GIC_SPI 972 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
970 <GIC_SPI 973 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
971 <GIC_SPI 974 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
972 <GIC_SPI 975 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
973 <GIC_SPI 976 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
974 <GIC_SPI 977 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
975 <GIC_SPI 978 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
976 <GIC_SPI 979 <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
977 <GIC_SPI 980 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
978 <GIC_SPI 981 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
979 <GIC_SPI 982 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
980 <GIC_SPI 983 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
981 <GIC_SPI 984 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
982 <GIC_SPI 985 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
983 <GIC_SPI 986 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
984 <GIC_SPI 987 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
985 <GIC_SPI 988 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
986 <GIC_SPI 989 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
987 <GIC_SPI 990 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
988 <GIC_SPI 991 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
989 <GIC_SPI 992 <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
990 <GIC_SPI 993 <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
991 interrupt-names = "ch0 994 interrupt-names = "ch0", "ch1", "ch2", "ch3",
992 "ch4 995 "ch4", "ch5", "ch6", "ch7",
993 "ch8 996 "ch8", "ch9", "ch10", "ch11",
994 "ch1 997 "ch12", "ch13", "ch14", "ch15",
995 "ch1 998 "ch16", "ch17", "ch18", "ch19",
996 "ch2 999 "ch20", "ch21", "ch22", "ch23",
997 "ch2 1000 "ch24";
998 clocks = <&cpg CPG_MOD 1001 clocks = <&cpg CPG_MOD 812>;
999 clock-names = "fck"; 1002 clock-names = "fck";
1000 power-domains = <&sys 1003 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1001 resets = <&cpg 812>; 1004 resets = <&cpg 812>;
1002 phy-mode = "rgmii"; 1005 phy-mode = "rgmii";
1003 rx-internal-delay-ps 1006 rx-internal-delay-ps = <0>;
1004 iommus = <&ipmmu_ds0 1007 iommus = <&ipmmu_ds0 16>;
1005 #address-cells = <1>; 1008 #address-cells = <1>;
1006 #size-cells = <0>; 1009 #size-cells = <0>;
1007 status = "disabled"; 1010 status = "disabled";
1008 }; 1011 };
1009 1012
1010 can0: can@e6c30000 { 1013 can0: can@e6c30000 {
1011 compatible = "renesas 1014 compatible = "renesas,can-r8a77990",
1012 "renesas 1015 "renesas,rcar-gen3-can";
1013 reg = <0 0xe6c30000 0 1016 reg = <0 0xe6c30000 0 0x1000>;
1014 interrupts = <GIC_SPI 1017 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
1015 clocks = <&cpg CPG_MO 1018 clocks = <&cpg CPG_MOD 916>,
1016 <&cpg CPG_CORE 1019 <&cpg CPG_CORE R8A77990_CLK_CANFD>,
1017 <&can_clk>; 1020 <&can_clk>;
1018 clock-names = "clkp1" 1021 clock-names = "clkp1", "clkp2", "can_clk";
1019 assigned-clocks = <&c 1022 assigned-clocks = <&cpg CPG_CORE R8A77990_CLK_CANFD>;
1020 assigned-clock-rates 1023 assigned-clock-rates = <40000000>;
1021 power-domains = <&sys 1024 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1022 resets = <&cpg 916>; 1025 resets = <&cpg 916>;
1023 status = "disabled"; 1026 status = "disabled";
1024 }; 1027 };
1025 1028
1026 can1: can@e6c38000 { 1029 can1: can@e6c38000 {
1027 compatible = "renesas 1030 compatible = "renesas,can-r8a77990",
1028 "renesas 1031 "renesas,rcar-gen3-can";
1029 reg = <0 0xe6c38000 0 1032 reg = <0 0xe6c38000 0 0x1000>;
1030 interrupts = <GIC_SPI 1033 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
1031 clocks = <&cpg CPG_MO 1034 clocks = <&cpg CPG_MOD 915>,
1032 <&cpg CPG_CORE 1035 <&cpg CPG_CORE R8A77990_CLK_CANFD>,
1033 <&can_clk>; 1036 <&can_clk>;
1034 clock-names = "clkp1" 1037 clock-names = "clkp1", "clkp2", "can_clk";
1035 assigned-clocks = <&c 1038 assigned-clocks = <&cpg CPG_CORE R8A77990_CLK_CANFD>;
1036 assigned-clock-rates 1039 assigned-clock-rates = <40000000>;
1037 power-domains = <&sys 1040 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1038 resets = <&cpg 915>; 1041 resets = <&cpg 915>;
1039 status = "disabled"; 1042 status = "disabled";
1040 }; 1043 };
1041 1044
1042 canfd: can@e66c0000 { 1045 canfd: can@e66c0000 {
1043 compatible = "renesas 1046 compatible = "renesas,r8a77990-canfd",
1044 "renesas 1047 "renesas,rcar-gen3-canfd";
1045 reg = <0 0xe66c0000 0 1048 reg = <0 0xe66c0000 0 0x8000>;
1046 interrupts = <GIC_SPI 1049 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
1047 <GIC_SPI 3 1050 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
1048 interrupt-names = "ch <<
1049 clocks = <&cpg CPG_MO 1051 clocks = <&cpg CPG_MOD 914>,
1050 <&cpg CPG_CORE 1052 <&cpg CPG_CORE R8A77990_CLK_CANFD>,
1051 <&can_clk>; 1053 <&can_clk>;
1052 clock-names = "fck", 1054 clock-names = "fck", "canfd", "can_clk";
1053 assigned-clocks = <&c 1055 assigned-clocks = <&cpg CPG_CORE R8A77990_CLK_CANFD>;
1054 assigned-clock-rates 1056 assigned-clock-rates = <40000000>;
1055 power-domains = <&sys 1057 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1056 resets = <&cpg 914>; 1058 resets = <&cpg 914>;
1057 status = "disabled"; 1059 status = "disabled";
1058 1060
1059 channel0 { 1061 channel0 {
1060 status = "dis 1062 status = "disabled";
1061 }; 1063 };
1062 1064
1063 channel1 { 1065 channel1 {
1064 status = "dis 1066 status = "disabled";
1065 }; 1067 };
1066 }; 1068 };
1067 1069
1068 pwm0: pwm@e6e30000 { 1070 pwm0: pwm@e6e30000 {
1069 compatible = "renesas 1071 compatible = "renesas,pwm-r8a77990", "renesas,pwm-rcar";
1070 reg = <0 0xe6e30000 0 1072 reg = <0 0xe6e30000 0 0x8>;
1071 clocks = <&cpg CPG_MO 1073 clocks = <&cpg CPG_MOD 523>;
1072 power-domains = <&sys 1074 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1073 resets = <&cpg 523>; 1075 resets = <&cpg 523>;
1074 #pwm-cells = <2>; 1076 #pwm-cells = <2>;
1075 status = "disabled"; 1077 status = "disabled";
1076 }; 1078 };
1077 1079
1078 pwm1: pwm@e6e31000 { 1080 pwm1: pwm@e6e31000 {
1079 compatible = "renesas 1081 compatible = "renesas,pwm-r8a77990", "renesas,pwm-rcar";
1080 reg = <0 0xe6e31000 0 1082 reg = <0 0xe6e31000 0 0x8>;
1081 clocks = <&cpg CPG_MO 1083 clocks = <&cpg CPG_MOD 523>;
1082 power-domains = <&sys 1084 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1083 resets = <&cpg 523>; 1085 resets = <&cpg 523>;
1084 #pwm-cells = <2>; 1086 #pwm-cells = <2>;
1085 status = "disabled"; 1087 status = "disabled";
1086 }; 1088 };
1087 1089
1088 pwm2: pwm@e6e32000 { 1090 pwm2: pwm@e6e32000 {
1089 compatible = "renesas 1091 compatible = "renesas,pwm-r8a77990", "renesas,pwm-rcar";
1090 reg = <0 0xe6e32000 0 1092 reg = <0 0xe6e32000 0 0x8>;
1091 clocks = <&cpg CPG_MO 1093 clocks = <&cpg CPG_MOD 523>;
1092 power-domains = <&sys 1094 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1093 resets = <&cpg 523>; 1095 resets = <&cpg 523>;
1094 #pwm-cells = <2>; 1096 #pwm-cells = <2>;
1095 status = "disabled"; 1097 status = "disabled";
1096 }; 1098 };
1097 1099
1098 pwm3: pwm@e6e33000 { 1100 pwm3: pwm@e6e33000 {
1099 compatible = "renesas 1101 compatible = "renesas,pwm-r8a77990", "renesas,pwm-rcar";
1100 reg = <0 0xe6e33000 0 1102 reg = <0 0xe6e33000 0 0x8>;
1101 clocks = <&cpg CPG_MO 1103 clocks = <&cpg CPG_MOD 523>;
1102 power-domains = <&sys 1104 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1103 resets = <&cpg 523>; 1105 resets = <&cpg 523>;
1104 #pwm-cells = <2>; 1106 #pwm-cells = <2>;
1105 status = "disabled"; 1107 status = "disabled";
1106 }; 1108 };
1107 1109
1108 pwm4: pwm@e6e34000 { 1110 pwm4: pwm@e6e34000 {
1109 compatible = "renesas 1111 compatible = "renesas,pwm-r8a77990", "renesas,pwm-rcar";
1110 reg = <0 0xe6e34000 0 1112 reg = <0 0xe6e34000 0 0x8>;
1111 clocks = <&cpg CPG_MO 1113 clocks = <&cpg CPG_MOD 523>;
1112 power-domains = <&sys 1114 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1113 resets = <&cpg 523>; 1115 resets = <&cpg 523>;
1114 #pwm-cells = <2>; 1116 #pwm-cells = <2>;
1115 status = "disabled"; 1117 status = "disabled";
1116 }; 1118 };
1117 1119
1118 pwm5: pwm@e6e35000 { 1120 pwm5: pwm@e6e35000 {
1119 compatible = "renesas 1121 compatible = "renesas,pwm-r8a77990", "renesas,pwm-rcar";
1120 reg = <0 0xe6e35000 0 1122 reg = <0 0xe6e35000 0 0x8>;
1121 clocks = <&cpg CPG_MO 1123 clocks = <&cpg CPG_MOD 523>;
1122 power-domains = <&sys 1124 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1123 resets = <&cpg 523>; 1125 resets = <&cpg 523>;
1124 #pwm-cells = <2>; 1126 #pwm-cells = <2>;
1125 status = "disabled"; 1127 status = "disabled";
1126 }; 1128 };
1127 1129
1128 pwm6: pwm@e6e36000 { 1130 pwm6: pwm@e6e36000 {
1129 compatible = "renesas 1131 compatible = "renesas,pwm-r8a77990", "renesas,pwm-rcar";
1130 reg = <0 0xe6e36000 0 1132 reg = <0 0xe6e36000 0 0x8>;
1131 clocks = <&cpg CPG_MO 1133 clocks = <&cpg CPG_MOD 523>;
1132 power-domains = <&sys 1134 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1133 resets = <&cpg 523>; 1135 resets = <&cpg 523>;
1134 #pwm-cells = <2>; 1136 #pwm-cells = <2>;
1135 status = "disabled"; 1137 status = "disabled";
1136 }; 1138 };
1137 1139
1138 scif0: serial@e6e60000 { 1140 scif0: serial@e6e60000 {
1139 compatible = "renesas 1141 compatible = "renesas,scif-r8a77990",
1140 "renesas 1142 "renesas,rcar-gen3-scif", "renesas,scif";
1141 reg = <0 0xe6e60000 0 1143 reg = <0 0xe6e60000 0 64>;
1142 interrupts = <GIC_SPI 1144 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
1143 clocks = <&cpg CPG_MO 1145 clocks = <&cpg CPG_MOD 207>,
1144 <&cpg CPG_CO 1146 <&cpg CPG_CORE R8A77990_CLK_S3D1C>,
1145 <&scif_clk>; 1147 <&scif_clk>;
1146 clock-names = "fck", 1148 clock-names = "fck", "brg_int", "scif_clk";
1147 dmas = <&dmac1 0x51>, 1149 dmas = <&dmac1 0x51>, <&dmac1 0x50>,
1148 <&dmac2 0x51>, 1150 <&dmac2 0x51>, <&dmac2 0x50>;
1149 dma-names = "tx", "rx 1151 dma-names = "tx", "rx", "tx", "rx";
1150 power-domains = <&sys 1152 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1151 resets = <&cpg 207>; 1153 resets = <&cpg 207>;
1152 status = "disabled"; 1154 status = "disabled";
1153 }; 1155 };
1154 1156
1155 scif1: serial@e6e68000 { 1157 scif1: serial@e6e68000 {
1156 compatible = "renesas 1158 compatible = "renesas,scif-r8a77990",
1157 "renesas 1159 "renesas,rcar-gen3-scif", "renesas,scif";
1158 reg = <0 0xe6e68000 0 1160 reg = <0 0xe6e68000 0 64>;
1159 interrupts = <GIC_SPI 1161 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
1160 clocks = <&cpg CPG_MO 1162 clocks = <&cpg CPG_MOD 206>,
1161 <&cpg CPG_CO 1163 <&cpg CPG_CORE R8A77990_CLK_S3D1C>,
1162 <&scif_clk>; 1164 <&scif_clk>;
1163 clock-names = "fck", 1165 clock-names = "fck", "brg_int", "scif_clk";
1164 dmas = <&dmac1 0x53>, 1166 dmas = <&dmac1 0x53>, <&dmac1 0x52>,
1165 <&dmac2 0x53>, 1167 <&dmac2 0x53>, <&dmac2 0x52>;
1166 dma-names = "tx", "rx 1168 dma-names = "tx", "rx", "tx", "rx";
1167 power-domains = <&sys 1169 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1168 resets = <&cpg 206>; 1170 resets = <&cpg 206>;
1169 status = "disabled"; 1171 status = "disabled";
1170 }; 1172 };
1171 1173
1172 scif2: serial@e6e88000 { 1174 scif2: serial@e6e88000 {
1173 compatible = "renesas 1175 compatible = "renesas,scif-r8a77990",
1174 "renesas 1176 "renesas,rcar-gen3-scif", "renesas,scif";
1175 reg = <0 0xe6e88000 0 1177 reg = <0 0xe6e88000 0 64>;
1176 interrupts = <GIC_SPI 1178 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
1177 clocks = <&cpg CPG_MO 1179 clocks = <&cpg CPG_MOD 310>,
1178 <&cpg CPG_CO 1180 <&cpg CPG_CORE R8A77990_CLK_S3D1C>,
1179 <&scif_clk>; 1181 <&scif_clk>;
1180 clock-names = "fck", 1182 clock-names = "fck", "brg_int", "scif_clk";
1181 dmas = <&dmac1 0x13>, 1183 dmas = <&dmac1 0x13>, <&dmac1 0x12>,
1182 <&dmac2 0x13>, 1184 <&dmac2 0x13>, <&dmac2 0x12>;
1183 dma-names = "tx", "rx 1185 dma-names = "tx", "rx", "tx", "rx";
1184 power-domains = <&sys 1186 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1185 resets = <&cpg 310>; 1187 resets = <&cpg 310>;
1186 status = "disabled"; 1188 status = "disabled";
1187 }; 1189 };
1188 1190
1189 scif3: serial@e6c50000 { 1191 scif3: serial@e6c50000 {
1190 compatible = "renesas 1192 compatible = "renesas,scif-r8a77990",
1191 "renesas 1193 "renesas,rcar-gen3-scif", "renesas,scif";
1192 reg = <0 0xe6c50000 0 1194 reg = <0 0xe6c50000 0 64>;
1193 interrupts = <GIC_SPI 1195 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
1194 clocks = <&cpg CPG_MO 1196 clocks = <&cpg CPG_MOD 204>,
1195 <&cpg CPG_CO 1197 <&cpg CPG_CORE R8A77990_CLK_S3D1C>,
1196 <&scif_clk>; 1198 <&scif_clk>;
1197 clock-names = "fck", 1199 clock-names = "fck", "brg_int", "scif_clk";
1198 dmas = <&dmac0 0x57>, 1200 dmas = <&dmac0 0x57>, <&dmac0 0x56>;
1199 dma-names = "tx", "rx 1201 dma-names = "tx", "rx";
1200 power-domains = <&sys 1202 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1201 resets = <&cpg 204>; 1203 resets = <&cpg 204>;
1202 status = "disabled"; 1204 status = "disabled";
1203 }; 1205 };
1204 1206
1205 scif4: serial@e6c40000 { 1207 scif4: serial@e6c40000 {
1206 compatible = "renesas 1208 compatible = "renesas,scif-r8a77990",
1207 "renesas 1209 "renesas,rcar-gen3-scif", "renesas,scif";
1208 reg = <0 0xe6c40000 0 1210 reg = <0 0xe6c40000 0 64>;
1209 interrupts = <GIC_SPI 1211 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1210 clocks = <&cpg CPG_MO 1212 clocks = <&cpg CPG_MOD 203>,
1211 <&cpg CPG_CO 1213 <&cpg CPG_CORE R8A77990_CLK_S3D1C>,
1212 <&scif_clk>; 1214 <&scif_clk>;
1213 clock-names = "fck", 1215 clock-names = "fck", "brg_int", "scif_clk";
1214 dmas = <&dmac0 0x59>, 1216 dmas = <&dmac0 0x59>, <&dmac0 0x58>;
1215 dma-names = "tx", "rx 1217 dma-names = "tx", "rx";
1216 power-domains = <&sys 1218 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1217 resets = <&cpg 203>; 1219 resets = <&cpg 203>;
1218 status = "disabled"; 1220 status = "disabled";
1219 }; 1221 };
1220 1222
1221 scif5: serial@e6f30000 { 1223 scif5: serial@e6f30000 {
1222 compatible = "renesas 1224 compatible = "renesas,scif-r8a77990",
1223 "renesas 1225 "renesas,rcar-gen3-scif", "renesas,scif";
1224 reg = <0 0xe6f30000 0 1226 reg = <0 0xe6f30000 0 64>;
1225 interrupts = <GIC_SPI 1227 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1226 clocks = <&cpg CPG_MO 1228 clocks = <&cpg CPG_MOD 202>,
1227 <&cpg CPG_CO 1229 <&cpg CPG_CORE R8A77990_CLK_S3D1C>,
1228 <&scif_clk>; 1230 <&scif_clk>;
1229 clock-names = "fck", 1231 clock-names = "fck", "brg_int", "scif_clk";
1230 dmas = <&dmac0 0x5b>, 1232 dmas = <&dmac0 0x5b>, <&dmac0 0x5a>;
1231 dma-names = "tx", "rx 1233 dma-names = "tx", "rx";
1232 power-domains = <&sys 1234 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1233 resets = <&cpg 202>; 1235 resets = <&cpg 202>;
1234 status = "disabled"; 1236 status = "disabled";
1235 }; 1237 };
1236 1238
1237 msiof0: spi@e6e90000 { 1239 msiof0: spi@e6e90000 {
1238 compatible = "renesas 1240 compatible = "renesas,msiof-r8a77990",
1239 "renesas 1241 "renesas,rcar-gen3-msiof";
1240 reg = <0 0xe6e90000 0 1242 reg = <0 0xe6e90000 0 0x0064>;
1241 interrupts = <GIC_SPI 1243 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
1242 clocks = <&cpg CPG_MO 1244 clocks = <&cpg CPG_MOD 211>;
1243 dmas = <&dmac1 0x41>, 1245 dmas = <&dmac1 0x41>, <&dmac1 0x40>,
1244 <&dmac2 0x41>, 1246 <&dmac2 0x41>, <&dmac2 0x40>;
1245 dma-names = "tx", "rx 1247 dma-names = "tx", "rx", "tx", "rx";
1246 power-domains = <&sys 1248 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1247 resets = <&cpg 211>; 1249 resets = <&cpg 211>;
1248 #address-cells = <1>; 1250 #address-cells = <1>;
1249 #size-cells = <0>; 1251 #size-cells = <0>;
1250 status = "disabled"; 1252 status = "disabled";
1251 }; 1253 };
1252 1254
1253 msiof1: spi@e6ea0000 { 1255 msiof1: spi@e6ea0000 {
1254 compatible = "renesas 1256 compatible = "renesas,msiof-r8a77990",
1255 "renesas 1257 "renesas,rcar-gen3-msiof";
1256 reg = <0 0xe6ea0000 0 1258 reg = <0 0xe6ea0000 0 0x0064>;
1257 interrupts = <GIC_SPI 1259 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
1258 clocks = <&cpg CPG_MO 1260 clocks = <&cpg CPG_MOD 210>;
1259 dmas = <&dmac0 0x43>, 1261 dmas = <&dmac0 0x43>, <&dmac0 0x42>;
1260 dma-names = "tx", "rx 1262 dma-names = "tx", "rx";
1261 power-domains = <&sys 1263 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1262 resets = <&cpg 210>; 1264 resets = <&cpg 210>;
1263 #address-cells = <1>; 1265 #address-cells = <1>;
1264 #size-cells = <0>; 1266 #size-cells = <0>;
1265 status = "disabled"; 1267 status = "disabled";
1266 }; 1268 };
1267 1269
1268 msiof2: spi@e6c00000 { 1270 msiof2: spi@e6c00000 {
1269 compatible = "renesas 1271 compatible = "renesas,msiof-r8a77990",
1270 "renesas 1272 "renesas,rcar-gen3-msiof";
1271 reg = <0 0xe6c00000 0 1273 reg = <0 0xe6c00000 0 0x0064>;
1272 interrupts = <GIC_SPI 1274 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
1273 clocks = <&cpg CPG_MO 1275 clocks = <&cpg CPG_MOD 209>;
1274 dmas = <&dmac0 0x45>, 1276 dmas = <&dmac0 0x45>, <&dmac0 0x44>;
1275 dma-names = "tx", "rx 1277 dma-names = "tx", "rx";
1276 power-domains = <&sys 1278 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1277 resets = <&cpg 209>; 1279 resets = <&cpg 209>;
1278 #address-cells = <1>; 1280 #address-cells = <1>;
1279 #size-cells = <0>; 1281 #size-cells = <0>;
1280 status = "disabled"; 1282 status = "disabled";
1281 }; 1283 };
1282 1284
1283 msiof3: spi@e6c10000 { 1285 msiof3: spi@e6c10000 {
1284 compatible = "renesas 1286 compatible = "renesas,msiof-r8a77990",
1285 "renesas 1287 "renesas,rcar-gen3-msiof";
1286 reg = <0 0xe6c10000 0 1288 reg = <0 0xe6c10000 0 0x0064>;
1287 interrupts = <GIC_SPI 1289 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
1288 clocks = <&cpg CPG_MO 1290 clocks = <&cpg CPG_MOD 208>;
1289 dmas = <&dmac0 0x47>, 1291 dmas = <&dmac0 0x47>, <&dmac0 0x46>;
1290 dma-names = "tx", "rx 1292 dma-names = "tx", "rx";
1291 power-domains = <&sys 1293 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1292 resets = <&cpg 208>; 1294 resets = <&cpg 208>;
1293 #address-cells = <1>; 1295 #address-cells = <1>;
1294 #size-cells = <0>; 1296 #size-cells = <0>;
1295 status = "disabled"; 1297 status = "disabled";
1296 }; 1298 };
1297 1299
1298 vin4: video@e6ef4000 { 1300 vin4: video@e6ef4000 {
1299 compatible = "renesas 1301 compatible = "renesas,vin-r8a77990";
1300 reg = <0 0xe6ef4000 0 1302 reg = <0 0xe6ef4000 0 0x1000>;
1301 interrupts = <GIC_SPI 1303 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
1302 clocks = <&cpg CPG_MO 1304 clocks = <&cpg CPG_MOD 807>;
1303 power-domains = <&sys 1305 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1304 resets = <&cpg 807>; 1306 resets = <&cpg 807>;
1305 renesas,id = <4>; 1307 renesas,id = <4>;
1306 status = "disabled"; 1308 status = "disabled";
1307 1309
1308 ports { 1310 ports {
1309 #address-cell 1311 #address-cells = <1>;
1310 #size-cells = 1312 #size-cells = <0>;
1311 1313
1312 port@1 { 1314 port@1 {
1313 #addr 1315 #address-cells = <1>;
1314 #size 1316 #size-cells = <0>;
1315 1317
1316 reg = 1318 reg = <1>;
1317 1319
1318 vin4c 1320 vin4csi40: endpoint@2 {
1319 1321 reg = <2>;
1320 !! 1322 remote-endpoint= <&csi40vin4>;
1321 }; 1323 };
1322 }; 1324 };
1323 }; 1325 };
1324 }; 1326 };
1325 1327
1326 vin5: video@e6ef5000 { 1328 vin5: video@e6ef5000 {
1327 compatible = "renesas 1329 compatible = "renesas,vin-r8a77990";
1328 reg = <0 0xe6ef5000 0 1330 reg = <0 0xe6ef5000 0 0x1000>;
1329 interrupts = <GIC_SPI 1331 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
1330 clocks = <&cpg CPG_MO 1332 clocks = <&cpg CPG_MOD 806>;
1331 power-domains = <&sys 1333 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1332 resets = <&cpg 806>; 1334 resets = <&cpg 806>;
1333 renesas,id = <5>; 1335 renesas,id = <5>;
1334 status = "disabled"; 1336 status = "disabled";
1335 1337
1336 ports { 1338 ports {
1337 #address-cell 1339 #address-cells = <1>;
1338 #size-cells = 1340 #size-cells = <0>;
1339 1341
1340 port@1 { 1342 port@1 {
1341 #addr 1343 #address-cells = <1>;
1342 #size 1344 #size-cells = <0>;
1343 1345
1344 reg = 1346 reg = <1>;
1345 1347
1346 vin5c 1348 vin5csi40: endpoint@2 {
1347 1349 reg = <2>;
1348 !! 1350 remote-endpoint= <&csi40vin5>;
1349 }; 1351 };
1350 }; 1352 };
1351 }; 1353 };
1352 }; 1354 };
1353 1355
1354 drif00: rif@e6f40000 { 1356 drif00: rif@e6f40000 {
1355 compatible = "renesas 1357 compatible = "renesas,r8a77990-drif",
1356 "renesas 1358 "renesas,rcar-gen3-drif";
1357 reg = <0 0xe6f40000 0 1359 reg = <0 0xe6f40000 0 0x84>;
1358 interrupts = <GIC_SPI 1360 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1359 clocks = <&cpg CPG_MO 1361 clocks = <&cpg CPG_MOD 515>;
1360 clock-names = "fck"; 1362 clock-names = "fck";
1361 dmas = <&dmac1 0x20>, 1363 dmas = <&dmac1 0x20>, <&dmac2 0x20>;
1362 dma-names = "rx", "rx 1364 dma-names = "rx", "rx";
1363 power-domains = <&sys 1365 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1364 resets = <&cpg 515>; 1366 resets = <&cpg 515>;
1365 renesas,bonding = <&d 1367 renesas,bonding = <&drif01>;
1366 status = "disabled"; 1368 status = "disabled";
1367 }; 1369 };
1368 1370
1369 drif01: rif@e6f50000 { 1371 drif01: rif@e6f50000 {
1370 compatible = "renesas 1372 compatible = "renesas,r8a77990-drif",
1371 "renesas 1373 "renesas,rcar-gen3-drif";
1372 reg = <0 0xe6f50000 0 1374 reg = <0 0xe6f50000 0 0x84>;
1373 interrupts = <GIC_SPI 1375 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
1374 clocks = <&cpg CPG_MO 1376 clocks = <&cpg CPG_MOD 514>;
1375 clock-names = "fck"; 1377 clock-names = "fck";
1376 dmas = <&dmac1 0x22>, 1378 dmas = <&dmac1 0x22>, <&dmac2 0x22>;
1377 dma-names = "rx", "rx 1379 dma-names = "rx", "rx";
1378 power-domains = <&sys 1380 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1379 resets = <&cpg 514>; 1381 resets = <&cpg 514>;
1380 renesas,bonding = <&d 1382 renesas,bonding = <&drif00>;
1381 status = "disabled"; 1383 status = "disabled";
1382 }; 1384 };
1383 1385
1384 drif10: rif@e6f60000 { 1386 drif10: rif@e6f60000 {
1385 compatible = "renesas 1387 compatible = "renesas,r8a77990-drif",
1386 "renesas 1388 "renesas,rcar-gen3-drif";
1387 reg = <0 0xe6f60000 0 1389 reg = <0 0xe6f60000 0 0x84>;
1388 interrupts = <GIC_SPI 1390 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1389 clocks = <&cpg CPG_MO 1391 clocks = <&cpg CPG_MOD 513>;
1390 clock-names = "fck"; 1392 clock-names = "fck";
1391 dmas = <&dmac1 0x24>, 1393 dmas = <&dmac1 0x24>, <&dmac2 0x24>;
1392 dma-names = "rx", "rx 1394 dma-names = "rx", "rx";
1393 power-domains = <&sys 1395 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1394 resets = <&cpg 513>; 1396 resets = <&cpg 513>;
1395 renesas,bonding = <&d 1397 renesas,bonding = <&drif11>;
1396 status = "disabled"; 1398 status = "disabled";
1397 }; 1399 };
1398 1400
1399 drif11: rif@e6f70000 { 1401 drif11: rif@e6f70000 {
1400 compatible = "renesas 1402 compatible = "renesas,r8a77990-drif",
1401 "renesas 1403 "renesas,rcar-gen3-drif";
1402 reg = <0 0xe6f70000 0 1404 reg = <0 0xe6f70000 0 0x84>;
1403 interrupts = <GIC_SPI 1405 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1404 clocks = <&cpg CPG_MO 1406 clocks = <&cpg CPG_MOD 512>;
1405 clock-names = "fck"; 1407 clock-names = "fck";
1406 dmas = <&dmac1 0x26>, 1408 dmas = <&dmac1 0x26>, <&dmac2 0x26>;
1407 dma-names = "rx", "rx 1409 dma-names = "rx", "rx";
1408 power-domains = <&sys 1410 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1409 resets = <&cpg 512>; 1411 resets = <&cpg 512>;
1410 renesas,bonding = <&d 1412 renesas,bonding = <&drif10>;
1411 status = "disabled"; 1413 status = "disabled";
1412 }; 1414 };
1413 1415
1414 drif20: rif@e6f80000 { 1416 drif20: rif@e6f80000 {
1415 compatible = "renesas 1417 compatible = "renesas,r8a77990-drif",
1416 "renesas 1418 "renesas,rcar-gen3-drif";
1417 reg = <0 0xe6f80000 0 1419 reg = <0 0xe6f80000 0 0x84>;
1418 interrupts = <GIC_SPI 1420 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
1419 clocks = <&cpg CPG_MO 1421 clocks = <&cpg CPG_MOD 511>;
1420 clock-names = "fck"; 1422 clock-names = "fck";
1421 dmas = <&dmac0 0x28>; 1423 dmas = <&dmac0 0x28>;
1422 dma-names = "rx"; 1424 dma-names = "rx";
1423 power-domains = <&sys 1425 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1424 resets = <&cpg 511>; 1426 resets = <&cpg 511>;
1425 renesas,bonding = <&d 1427 renesas,bonding = <&drif21>;
1426 status = "disabled"; 1428 status = "disabled";
1427 }; 1429 };
1428 1430
1429 drif21: rif@e6f90000 { 1431 drif21: rif@e6f90000 {
1430 compatible = "renesas 1432 compatible = "renesas,r8a77990-drif",
1431 "renesas 1433 "renesas,rcar-gen3-drif";
1432 reg = <0 0xe6f90000 0 1434 reg = <0 0xe6f90000 0 0x84>;
1433 interrupts = <GIC_SPI 1435 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
1434 clocks = <&cpg CPG_MO 1436 clocks = <&cpg CPG_MOD 510>;
1435 clock-names = "fck"; 1437 clock-names = "fck";
1436 dmas = <&dmac0 0x2a>; 1438 dmas = <&dmac0 0x2a>;
1437 dma-names = "rx"; 1439 dma-names = "rx";
1438 power-domains = <&sys 1440 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1439 resets = <&cpg 510>; 1441 resets = <&cpg 510>;
1440 renesas,bonding = <&d 1442 renesas,bonding = <&drif20>;
1441 status = "disabled"; 1443 status = "disabled";
1442 }; 1444 };
1443 1445
1444 drif30: rif@e6fa0000 { 1446 drif30: rif@e6fa0000 {
1445 compatible = "renesas 1447 compatible = "renesas,r8a77990-drif",
1446 "renesas 1448 "renesas,rcar-gen3-drif";
1447 reg = <0 0xe6fa0000 0 1449 reg = <0 0xe6fa0000 0 0x84>;
1448 interrupts = <GIC_SPI 1450 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
1449 clocks = <&cpg CPG_MO 1451 clocks = <&cpg CPG_MOD 509>;
1450 clock-names = "fck"; 1452 clock-names = "fck";
1451 dmas = <&dmac0 0x2c>; 1453 dmas = <&dmac0 0x2c>;
1452 dma-names = "rx"; 1454 dma-names = "rx";
1453 power-domains = <&sys 1455 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1454 resets = <&cpg 509>; 1456 resets = <&cpg 509>;
1455 renesas,bonding = <&d 1457 renesas,bonding = <&drif31>;
1456 status = "disabled"; 1458 status = "disabled";
1457 }; 1459 };
1458 1460
1459 drif31: rif@e6fb0000 { 1461 drif31: rif@e6fb0000 {
1460 compatible = "renesas 1462 compatible = "renesas,r8a77990-drif",
1461 "renesas 1463 "renesas,rcar-gen3-drif";
1462 reg = <0 0xe6fb0000 0 1464 reg = <0 0xe6fb0000 0 0x84>;
1463 interrupts = <GIC_SPI 1465 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
1464 clocks = <&cpg CPG_MO 1466 clocks = <&cpg CPG_MOD 508>;
1465 clock-names = "fck"; 1467 clock-names = "fck";
1466 dmas = <&dmac0 0x2e>; 1468 dmas = <&dmac0 0x2e>;
1467 dma-names = "rx"; 1469 dma-names = "rx";
1468 power-domains = <&sys 1470 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1469 resets = <&cpg 508>; 1471 resets = <&cpg 508>;
1470 renesas,bonding = <&d 1472 renesas,bonding = <&drif30>;
1471 status = "disabled"; 1473 status = "disabled";
1472 }; 1474 };
1473 1475
1474 rcar_sound: sound@ec500000 { 1476 rcar_sound: sound@ec500000 {
1475 /* 1477 /*
1476 * #sound-dai-cells i !! 1478 * #sound-dai-cells is required
1477 * 1479 *
1478 * Single DAI : #soun 1480 * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
1479 * Multi DAI : #soun 1481 * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>;
1480 */ 1482 */
1481 /* 1483 /*
1482 * #clock-cells is re 1484 * #clock-cells is required for audio_clkout0/1/2/3
1483 * 1485 *
1484 * clkout : #cl 1486 * clkout : #clock-cells = <0>; <&rcar_sound>;
1485 * clkout0/1/2/3: #cl 1487 * clkout0/1/2/3: #clock-cells = <1>; <&rcar_sound N>;
1486 */ 1488 */
1487 compatible = "renesas !! 1489 compatible = "renesas,rcar_sound-r8a77990", "renesas,rcar_sound-gen3";
1488 reg = <0 0xec500000 0 !! 1490 reg = <0 0xec500000 0 0x1000>, /* SCU */
1489 <0 0xec5a0000 0 !! 1491 <0 0xec5a0000 0 0x100>, /* ADG */
1490 <0 0xec540000 0 !! 1492 <0 0xec540000 0 0x1000>, /* SSIU */
1491 <0 0xec541000 0 !! 1493 <0 0xec541000 0 0x280>, /* SSI */
1492 <0 0xec760000 0 !! 1494 <0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/
1493 reg-names = "scu", "a 1495 reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
1494 1496
1495 clocks = <&cpg CPG_MO 1497 clocks = <&cpg CPG_MOD 1005>,
1496 <&cpg CPG_MO 1498 <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
1497 <&cpg CPG_MO 1499 <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
1498 <&cpg CPG_MO 1500 <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
1499 <&cpg CPG_MO 1501 <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
1500 <&cpg CPG_MO 1502 <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
1501 <&cpg CPG_MO 1503 <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
1502 <&cpg CPG_MO 1504 <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
1503 <&cpg CPG_MO 1505 <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
1504 <&cpg CPG_MO 1506 <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
1505 <&cpg CPG_MO 1507 <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
1506 <&cpg CPG_MO 1508 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
1507 <&cpg CPG_MO 1509 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
1508 <&cpg CPG_MO 1510 <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
1509 <&audio_clk_ 1511 <&audio_clk_a>, <&audio_clk_b>,
1510 <&audio_clk_ 1512 <&audio_clk_c>,
1511 <&cpg CPG_MO !! 1513 <&cpg CPG_CORE R8A77990_CLK_ZA2>;
1512 clock-names = "ssi-al 1514 clock-names = "ssi-all",
1513 "ssi.9" 1515 "ssi.9", "ssi.8", "ssi.7", "ssi.6",
1514 "ssi.5" 1516 "ssi.5", "ssi.4", "ssi.3", "ssi.2",
1515 "ssi.1" 1517 "ssi.1", "ssi.0",
1516 "src.9" 1518 "src.9", "src.8", "src.7", "src.6",
1517 "src.5" 1519 "src.5", "src.4", "src.3", "src.2",
1518 "src.1" 1520 "src.1", "src.0",
1519 "mix.1" 1521 "mix.1", "mix.0",
1520 "ctu.1" 1522 "ctu.1", "ctu.0",
1521 "dvc.0" 1523 "dvc.0", "dvc.1",
1522 "clk_a" 1524 "clk_a", "clk_b", "clk_c", "clk_i";
1523 power-domains = <&sys 1525 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1524 resets = <&cpg 1005>, 1526 resets = <&cpg 1005>,
1525 <&cpg 1006>, 1527 <&cpg 1006>, <&cpg 1007>,
1526 <&cpg 1008>, 1528 <&cpg 1008>, <&cpg 1009>,
1527 <&cpg 1010>, 1529 <&cpg 1010>, <&cpg 1011>,
1528 <&cpg 1012>, 1530 <&cpg 1012>, <&cpg 1013>,
1529 <&cpg 1014>, 1531 <&cpg 1014>, <&cpg 1015>;
1530 reset-names = "ssi-al 1532 reset-names = "ssi-all",
1531 "ssi.9" 1533 "ssi.9", "ssi.8", "ssi.7", "ssi.6",
1532 "ssi.5" 1534 "ssi.5", "ssi.4", "ssi.3", "ssi.2",
1533 "ssi.1" 1535 "ssi.1", "ssi.0";
1534 status = "disabled"; 1536 status = "disabled";
1535 1537
1536 rcar_sound,ctu { 1538 rcar_sound,ctu {
1537 ctu00: ctu-0 1539 ctu00: ctu-0 { };
1538 ctu01: ctu-1 1540 ctu01: ctu-1 { };
1539 ctu02: ctu-2 1541 ctu02: ctu-2 { };
1540 ctu03: ctu-3 1542 ctu03: ctu-3 { };
1541 ctu10: ctu-4 1543 ctu10: ctu-4 { };
1542 ctu11: ctu-5 1544 ctu11: ctu-5 { };
1543 ctu12: ctu-6 1545 ctu12: ctu-6 { };
1544 ctu13: ctu-7 1546 ctu13: ctu-7 { };
1545 }; 1547 };
1546 1548
1547 rcar_sound,dvc { 1549 rcar_sound,dvc {
1548 dvc0: dvc-0 { 1550 dvc0: dvc-0 {
1549 dmas 1551 dmas = <&audma0 0xbc>;
1550 dma-n 1552 dma-names = "tx";
1551 }; 1553 };
1552 dvc1: dvc-1 { 1554 dvc1: dvc-1 {
1553 dmas 1555 dmas = <&audma0 0xbe>;
1554 dma-n 1556 dma-names = "tx";
1555 }; 1557 };
1556 }; 1558 };
1557 1559
1558 rcar_sound,mix { 1560 rcar_sound,mix {
1559 mix0: mix-0 { 1561 mix0: mix-0 { };
1560 mix1: mix-1 { 1562 mix1: mix-1 { };
1561 }; 1563 };
1562 1564
1563 rcar_sound,src { 1565 rcar_sound,src {
1564 src0: src-0 { 1566 src0: src-0 {
1565 inter 1567 interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
1566 dmas 1568 dmas = <&audma0 0x85>, <&audma0 0x9a>;
1567 dma-n 1569 dma-names = "rx", "tx";
1568 }; 1570 };
1569 src1: src-1 { 1571 src1: src-1 {
1570 inter 1572 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1571 dmas 1573 dmas = <&audma0 0x87>, <&audma0 0x9c>;
1572 dma-n 1574 dma-names = "rx", "tx";
1573 }; 1575 };
1574 src2: src-2 { 1576 src2: src-2 {
1575 inter 1577 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1576 dmas 1578 dmas = <&audma0 0x89>, <&audma0 0x9e>;
1577 dma-n 1579 dma-names = "rx", "tx";
1578 }; 1580 };
1579 src3: src-3 { 1581 src3: src-3 {
1580 inter 1582 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1581 dmas 1583 dmas = <&audma0 0x8b>, <&audma0 0xa0>;
1582 dma-n 1584 dma-names = "rx", "tx";
1583 }; 1585 };
1584 src4: src-4 { 1586 src4: src-4 {
1585 inter 1587 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1586 dmas 1588 dmas = <&audma0 0x8d>, <&audma0 0xb0>;
1587 dma-n 1589 dma-names = "rx", "tx";
1588 }; 1590 };
1589 src5: src-5 { 1591 src5: src-5 {
1590 inter 1592 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1591 dmas 1593 dmas = <&audma0 0x8f>, <&audma0 0xb2>;
1592 dma-n 1594 dma-names = "rx", "tx";
1593 }; 1595 };
1594 src6: src-6 { 1596 src6: src-6 {
1595 inter 1597 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1596 dmas 1598 dmas = <&audma0 0x91>, <&audma0 0xb4>;
1597 dma-n 1599 dma-names = "rx", "tx";
1598 }; 1600 };
1599 src7: src-7 { 1601 src7: src-7 {
1600 inter 1602 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
1601 dmas 1603 dmas = <&audma0 0x93>, <&audma0 0xb6>;
1602 dma-n 1604 dma-names = "rx", "tx";
1603 }; 1605 };
1604 src8: src-8 { 1606 src8: src-8 {
1605 inter 1607 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
1606 dmas 1608 dmas = <&audma0 0x95>, <&audma0 0xb8>;
1607 dma-n 1609 dma-names = "rx", "tx";
1608 }; 1610 };
1609 src9: src-9 { 1611 src9: src-9 {
1610 inter 1612 interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>;
1611 dmas 1613 dmas = <&audma0 0x97>, <&audma0 0xba>;
1612 dma-n 1614 dma-names = "rx", "tx";
1613 }; 1615 };
1614 }; 1616 };
1615 1617
1616 rcar_sound,ssi { 1618 rcar_sound,ssi {
1617 ssi0: ssi-0 { 1619 ssi0: ssi-0 {
1618 inter 1620 interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
1619 dmas 1621 dmas = <&audma0 0x01>, <&audma0 0x02>,
1620 1622 <&audma0 0x15>, <&audma0 0x16>;
1621 dma-n 1623 dma-names = "rx", "tx", "rxu", "txu";
1622 }; 1624 };
1623 ssi1: ssi-1 { 1625 ssi1: ssi-1 {
1624 inter 1626 interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
1625 dmas 1627 dmas = <&audma0 0x03>, <&audma0 0x04>,
1626 1628 <&audma0 0x49>, <&audma0 0x4a>;
1627 dma-n 1629 dma-names = "rx", "tx", "rxu", "txu";
1628 }; 1630 };
1629 ssi2: ssi-2 { 1631 ssi2: ssi-2 {
1630 inter 1632 interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>;
1631 dmas 1633 dmas = <&audma0 0x05>, <&audma0 0x06>,
1632 1634 <&audma0 0x63>, <&audma0 0x64>;
1633 dma-n 1635 dma-names = "rx", "tx", "rxu", "txu";
1634 }; 1636 };
1635 ssi3: ssi-3 { 1637 ssi3: ssi-3 {
1636 inter 1638 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
1637 dmas 1639 dmas = <&audma0 0x07>, <&audma0 0x08>,
1638 1640 <&audma0 0x6f>, <&audma0 0x70>;
1639 dma-n 1641 dma-names = "rx", "tx", "rxu", "txu";
1640 }; 1642 };
1641 ssi4: ssi-4 { 1643 ssi4: ssi-4 {
1642 inter 1644 interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
1643 dmas 1645 dmas = <&audma0 0x09>, <&audma0 0x0a>,
1644 1646 <&audma0 0x71>, <&audma0 0x72>;
1645 dma-n 1647 dma-names = "rx", "tx", "rxu", "txu";
1646 }; 1648 };
1647 ssi5: ssi-5 { 1649 ssi5: ssi-5 {
1648 inter 1650 interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
1649 dmas 1651 dmas = <&audma0 0x0b>, <&audma0 0x0c>,
1650 1652 <&audma0 0x73>, <&audma0 0x74>;
1651 dma-n 1653 dma-names = "rx", "tx", "rxu", "txu";
1652 }; 1654 };
1653 ssi6: ssi-6 { 1655 ssi6: ssi-6 {
1654 inter 1656 interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>;
1655 dmas 1657 dmas = <&audma0 0x0d>, <&audma0 0x0e>,
1656 1658 <&audma0 0x75>, <&audma0 0x76>;
1657 dma-n 1659 dma-names = "rx", "tx", "rxu", "txu";
1658 }; 1660 };
1659 ssi7: ssi-7 { 1661 ssi7: ssi-7 {
1660 inter 1662 interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>;
1661 dmas 1663 dmas = <&audma0 0x0f>, <&audma0 0x10>,
1662 1664 <&audma0 0x79>, <&audma0 0x7a>;
1663 dma-n 1665 dma-names = "rx", "tx", "rxu", "txu";
1664 }; 1666 };
1665 ssi8: ssi-8 { 1667 ssi8: ssi-8 {
1666 inter 1668 interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>;
1667 dmas 1669 dmas = <&audma0 0x11>, <&audma0 0x12>,
1668 1670 <&audma0 0x7b>, <&audma0 0x7c>;
1669 dma-n 1671 dma-names = "rx", "tx", "rxu", "txu";
1670 }; 1672 };
1671 ssi9: ssi-9 { 1673 ssi9: ssi-9 {
1672 inter 1674 interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
1673 dmas 1675 dmas = <&audma0 0x13>, <&audma0 0x14>,
1674 1676 <&audma0 0x7d>, <&audma0 0x7e>;
1675 dma-n 1677 dma-names = "rx", "tx", "rxu", "txu";
1676 }; 1678 };
1677 }; 1679 };
1678 }; 1680 };
1679 1681
1680 mlp: mlp@ec520000 { <<
1681 compatible = "renesas <<
1682 "renesas <<
1683 reg = <0 0xec520000 0 <<
1684 interrupts = <GIC_SPI <<
1685 <GIC_SPI 385 <<
1686 clocks = <&cpg CPG_MO <<
1687 power-domains = <&sys <<
1688 resets = <&cpg 802>; <<
1689 status = "disabled"; <<
1690 }; <<
1691 <<
1692 audma0: dma-controller@ec7000 1682 audma0: dma-controller@ec700000 {
1693 compatible = "renesas 1683 compatible = "renesas,dmac-r8a77990",
1694 "renesas 1684 "renesas,rcar-dmac";
1695 reg = <0 0xec700000 0 1685 reg = <0 0xec700000 0 0x10000>;
1696 interrupts = <GIC_SPI 1686 interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>,
1697 <GIC_SPI 1687 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
1698 <GIC_SPI 1688 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
1699 <GIC_SPI 1689 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
1700 <GIC_SPI 1690 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
1701 <GIC_SPI 1691 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
1702 <GIC_SPI 1692 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
1703 <GIC_SPI 1693 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
1704 <GIC_SPI 1694 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
1705 <GIC_SPI 1695 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
1706 <GIC_SPI 1696 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
1707 <GIC_SPI 1697 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
1708 <GIC_SPI 1698 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
1709 <GIC_SPI 1699 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
1710 <GIC_SPI 1700 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
1711 <GIC_SPI 1701 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
1712 <GIC_SPI 1702 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>;
1713 interrupt-names = "er 1703 interrupt-names = "error",
1714 "ch0" 1704 "ch0", "ch1", "ch2", "ch3",
1715 "ch4" 1705 "ch4", "ch5", "ch6", "ch7",
1716 "ch8" 1706 "ch8", "ch9", "ch10", "ch11",
1717 "ch12 1707 "ch12", "ch13", "ch14", "ch15";
1718 clocks = <&cpg CPG_MO 1708 clocks = <&cpg CPG_MOD 502>;
1719 clock-names = "fck"; 1709 clock-names = "fck";
1720 power-domains = <&sys 1710 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1721 resets = <&cpg 502>; 1711 resets = <&cpg 502>;
1722 #dma-cells = <1>; 1712 #dma-cells = <1>;
1723 dma-channels = <16>; 1713 dma-channels = <16>;
1724 iommus = <&ipmmu_mp 0 1714 iommus = <&ipmmu_mp 0>, <&ipmmu_mp 1>,
1725 <&ipmmu_mp 2 1715 <&ipmmu_mp 2>, <&ipmmu_mp 3>,
1726 <&ipmmu_mp 4 1716 <&ipmmu_mp 4>, <&ipmmu_mp 5>,
1727 <&ipmmu_mp 6 1717 <&ipmmu_mp 6>, <&ipmmu_mp 7>,
1728 <&ipmmu_mp 8 1718 <&ipmmu_mp 8>, <&ipmmu_mp 9>,
1729 <&ipmmu_mp 1 1719 <&ipmmu_mp 10>, <&ipmmu_mp 11>,
1730 <&ipmmu_mp 1 1720 <&ipmmu_mp 12>, <&ipmmu_mp 13>,
1731 <&ipmmu_mp 1 1721 <&ipmmu_mp 14>, <&ipmmu_mp 15>;
1732 }; 1722 };
1733 1723
1734 xhci0: usb@ee000000 { 1724 xhci0: usb@ee000000 {
1735 compatible = "renesas 1725 compatible = "renesas,xhci-r8a77990",
1736 "renesas 1726 "renesas,rcar-gen3-xhci";
1737 reg = <0 0xee000000 0 1727 reg = <0 0xee000000 0 0xc00>;
1738 interrupts = <GIC_SPI 1728 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
1739 clocks = <&cpg CPG_MO 1729 clocks = <&cpg CPG_MOD 328>;
1740 power-domains = <&sys 1730 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1741 resets = <&cpg 328>; 1731 resets = <&cpg 328>;
1742 status = "disabled"; 1732 status = "disabled";
1743 }; 1733 };
1744 1734
1745 usb3_peri0: usb@ee020000 { 1735 usb3_peri0: usb@ee020000 {
1746 compatible = "renesas 1736 compatible = "renesas,r8a77990-usb3-peri",
1747 "renesas 1737 "renesas,rcar-gen3-usb3-peri";
1748 reg = <0 0xee020000 0 1738 reg = <0 0xee020000 0 0x400>;
1749 interrupts = <GIC_SPI 1739 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
1750 clocks = <&cpg CPG_MO 1740 clocks = <&cpg CPG_MOD 328>;
1751 power-domains = <&sys 1741 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1752 resets = <&cpg 328>; 1742 resets = <&cpg 328>;
1753 status = "disabled"; 1743 status = "disabled";
1754 }; 1744 };
1755 1745
1756 ohci0: usb@ee080000 { 1746 ohci0: usb@ee080000 {
1757 compatible = "generic 1747 compatible = "generic-ohci";
1758 reg = <0 0xee080000 0 1748 reg = <0 0xee080000 0 0x100>;
1759 interrupts = <GIC_SPI 1749 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
1760 clocks = <&cpg CPG_MO 1750 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
1761 phys = <&usb2_phy0 1> 1751 phys = <&usb2_phy0 1>;
1762 phy-names = "usb"; 1752 phy-names = "usb";
1763 power-domains = <&sys 1753 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1764 resets = <&cpg 703>, 1754 resets = <&cpg 703>, <&cpg 704>;
1765 status = "disabled"; 1755 status = "disabled";
1766 }; 1756 };
1767 1757
1768 ehci0: usb@ee080100 { 1758 ehci0: usb@ee080100 {
1769 compatible = "generic 1759 compatible = "generic-ehci";
1770 reg = <0 0xee080100 0 1760 reg = <0 0xee080100 0 0x100>;
1771 interrupts = <GIC_SPI 1761 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
1772 clocks = <&cpg CPG_MO 1762 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
1773 phys = <&usb2_phy0 2> 1763 phys = <&usb2_phy0 2>;
1774 phy-names = "usb"; 1764 phy-names = "usb";
1775 companion = <&ohci0>; 1765 companion = <&ohci0>;
1776 power-domains = <&sys 1766 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1777 resets = <&cpg 703>, 1767 resets = <&cpg 703>, <&cpg 704>;
1778 status = "disabled"; 1768 status = "disabled";
1779 }; 1769 };
1780 1770
1781 usb2_phy0: usb-phy@ee080200 { 1771 usb2_phy0: usb-phy@ee080200 {
1782 compatible = "renesas 1772 compatible = "renesas,usb2-phy-r8a77990",
1783 "renesas 1773 "renesas,rcar-gen3-usb2-phy";
1784 reg = <0 0xee080200 0 1774 reg = <0 0xee080200 0 0x700>;
1785 interrupts = <GIC_SPI 1775 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
1786 clocks = <&cpg CPG_MO 1776 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
1787 power-domains = <&sys 1777 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1788 resets = <&cpg 703>, 1778 resets = <&cpg 703>, <&cpg 704>;
1789 #phy-cells = <1>; 1779 #phy-cells = <1>;
1790 status = "disabled"; 1780 status = "disabled";
1791 }; 1781 };
1792 1782
1793 sdhi0: mmc@ee100000 { 1783 sdhi0: mmc@ee100000 {
1794 compatible = "renesas 1784 compatible = "renesas,sdhi-r8a77990",
1795 "renesas 1785 "renesas,rcar-gen3-sdhi";
1796 reg = <0 0xee100000 0 1786 reg = <0 0xee100000 0 0x2000>;
1797 interrupts = <GIC_SPI 1787 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
1798 clocks = <&cpg CPG_MO !! 1788 clocks = <&cpg CPG_MOD 314>;
1799 clock-names = "core", <<
1800 max-frequency = <2000 1789 max-frequency = <200000000>;
1801 power-domains = <&sys 1790 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1802 resets = <&cpg 314>; 1791 resets = <&cpg 314>;
1803 iommus = <&ipmmu_ds1 1792 iommus = <&ipmmu_ds1 32>;
1804 status = "disabled"; 1793 status = "disabled";
1805 }; 1794 };
1806 1795
1807 sdhi1: mmc@ee120000 { 1796 sdhi1: mmc@ee120000 {
1808 compatible = "renesas 1797 compatible = "renesas,sdhi-r8a77990",
1809 "renesas 1798 "renesas,rcar-gen3-sdhi";
1810 reg = <0 0xee120000 0 1799 reg = <0 0xee120000 0 0x2000>;
1811 interrupts = <GIC_SPI 1800 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
1812 clocks = <&cpg CPG_MO !! 1801 clocks = <&cpg CPG_MOD 313>;
1813 clock-names = "core", <<
1814 max-frequency = <2000 1802 max-frequency = <200000000>;
1815 power-domains = <&sys 1803 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1816 resets = <&cpg 313>; 1804 resets = <&cpg 313>;
1817 iommus = <&ipmmu_ds1 1805 iommus = <&ipmmu_ds1 33>;
1818 status = "disabled"; 1806 status = "disabled";
1819 }; 1807 };
1820 1808
1821 sdhi3: mmc@ee160000 { 1809 sdhi3: mmc@ee160000 {
1822 compatible = "renesas 1810 compatible = "renesas,sdhi-r8a77990",
1823 "renesas 1811 "renesas,rcar-gen3-sdhi";
1824 reg = <0 0xee160000 0 1812 reg = <0 0xee160000 0 0x2000>;
1825 interrupts = <GIC_SPI 1813 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
1826 clocks = <&cpg CPG_MO !! 1814 clocks = <&cpg CPG_MOD 311>;
1827 clock-names = "core", <<
1828 max-frequency = <2000 1815 max-frequency = <200000000>;
1829 power-domains = <&sys 1816 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1830 resets = <&cpg 311>; 1817 resets = <&cpg 311>;
1831 iommus = <&ipmmu_ds1 1818 iommus = <&ipmmu_ds1 35>;
1832 status = "disabled"; 1819 status = "disabled";
1833 }; 1820 };
1834 1821
1835 rpc: spi@ee200000 { <<
1836 compatible = "renesas <<
1837 "renesas <<
1838 reg = <0 0xee200000 0 <<
1839 <0 0x08000000 0 <<
1840 <0 0xee208000 0 <<
1841 reg-names = "regs", " <<
1842 interrupts = <GIC_SPI <<
1843 clocks = <&cpg CPG_MO <<
1844 power-domains = <&sys <<
1845 resets = <&cpg 917>; <<
1846 #address-cells = <1>; <<
1847 #size-cells = <0>; <<
1848 status = "disabled"; <<
1849 }; <<
1850 <<
1851 gic: interrupt-controller@f10 1822 gic: interrupt-controller@f1010000 {
1852 compatible = "arm,gic 1823 compatible = "arm,gic-400";
1853 #interrupt-cells = <3 1824 #interrupt-cells = <3>;
1854 #address-cells = <0>; 1825 #address-cells = <0>;
1855 interrupt-controller; 1826 interrupt-controller;
1856 reg = <0x0 0xf1010000 1827 reg = <0x0 0xf1010000 0 0x1000>,
1857 <0x0 0xf1020000 1828 <0x0 0xf1020000 0 0x20000>,
1858 <0x0 0xf1040000 1829 <0x0 0xf1040000 0 0x20000>,
1859 <0x0 0xf1060000 1830 <0x0 0xf1060000 0 0x20000>;
1860 interrupts = <GIC_PPI 1831 interrupts = <GIC_PPI 9
1861 (GIC_ 1832 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
1862 clocks = <&cpg CPG_MO 1833 clocks = <&cpg CPG_MOD 408>;
1863 clock-names = "clk"; 1834 clock-names = "clk";
1864 power-domains = <&sys 1835 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1865 resets = <&cpg 408>; 1836 resets = <&cpg 408>;
1866 }; 1837 };
1867 1838
1868 pciec0: pcie@fe000000 { 1839 pciec0: pcie@fe000000 {
1869 compatible = "renesas 1840 compatible = "renesas,pcie-r8a77990",
1870 "renesas 1841 "renesas,pcie-rcar-gen3";
1871 reg = <0 0xfe000000 0 1842 reg = <0 0xfe000000 0 0x80000>;
1872 #address-cells = <3>; 1843 #address-cells = <3>;
1873 #size-cells = <2>; 1844 #size-cells = <2>;
1874 bus-range = <0x00 0xf 1845 bus-range = <0x00 0xff>;
1875 device_type = "pci"; 1846 device_type = "pci";
1876 ranges = <0x01000000 1847 ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>,
1877 <0x02000000 1848 <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>,
1878 <0x02000000 1849 <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>,
1879 <0x42000000 1850 <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
1880 /* Map all possible D !! 1851 /* Map all possible DDR as inbound ranges */
1881 dma-ranges = <0x42000 !! 1852 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x40000000>;
1882 interrupts = <GIC_SPI 1853 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
1883 <GIC_SPI 1854 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
1884 <GIC_SPI 1855 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
1885 #interrupt-cells = <1 1856 #interrupt-cells = <1>;
1886 interrupt-map-mask = 1857 interrupt-map-mask = <0 0 0 0>;
1887 interrupt-map = <0 0 1858 interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
1888 clocks = <&cpg CPG_MO 1859 clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>;
1889 clock-names = "pcie", 1860 clock-names = "pcie", "pcie_bus";
1890 power-domains = <&sys 1861 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1891 resets = <&cpg 319>; 1862 resets = <&cpg 319>;
1892 iommu-map = <0 &ipmmu <<
1893 iommu-map-mask = <0>; <<
1894 status = "disabled"; 1863 status = "disabled";
1895 }; 1864 };
1896 1865
1897 vspb0: vsp@fe960000 { 1866 vspb0: vsp@fe960000 {
1898 compatible = "renesas 1867 compatible = "renesas,vsp2";
1899 reg = <0 0xfe960000 0 1868 reg = <0 0xfe960000 0 0x8000>;
1900 interrupts = <GIC_SPI 1869 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
1901 clocks = <&cpg CPG_MO 1870 clocks = <&cpg CPG_MOD 626>;
1902 power-domains = <&sys 1871 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1903 resets = <&cpg 626>; 1872 resets = <&cpg 626>;
1904 renesas,fcp = <&fcpvb 1873 renesas,fcp = <&fcpvb0>;
1905 }; 1874 };
1906 1875
1907 fcpvb0: fcp@fe96f000 { 1876 fcpvb0: fcp@fe96f000 {
1908 compatible = "renesas 1877 compatible = "renesas,fcpv";
1909 reg = <0 0xfe96f000 0 1878 reg = <0 0xfe96f000 0 0x200>;
1910 clocks = <&cpg CPG_MO 1879 clocks = <&cpg CPG_MOD 607>;
1911 power-domains = <&sys 1880 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1912 resets = <&cpg 607>; 1881 resets = <&cpg 607>;
1913 iommus = <&ipmmu_vp0 1882 iommus = <&ipmmu_vp0 5>;
1914 }; 1883 };
1915 1884
1916 vspi0: vsp@fe9a0000 { 1885 vspi0: vsp@fe9a0000 {
1917 compatible = "renesas 1886 compatible = "renesas,vsp2";
1918 reg = <0 0xfe9a0000 0 1887 reg = <0 0xfe9a0000 0 0x8000>;
1919 interrupts = <GIC_SPI 1888 interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>;
1920 clocks = <&cpg CPG_MO 1889 clocks = <&cpg CPG_MOD 631>;
1921 power-domains = <&sys 1890 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1922 resets = <&cpg 631>; 1891 resets = <&cpg 631>;
1923 renesas,fcp = <&fcpvi 1892 renesas,fcp = <&fcpvi0>;
1924 }; 1893 };
1925 1894
1926 fcpvi0: fcp@fe9af000 { 1895 fcpvi0: fcp@fe9af000 {
1927 compatible = "renesas 1896 compatible = "renesas,fcpv";
1928 reg = <0 0xfe9af000 0 1897 reg = <0 0xfe9af000 0 0x200>;
1929 clocks = <&cpg CPG_MO 1898 clocks = <&cpg CPG_MOD 611>;
1930 power-domains = <&sys 1899 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1931 resets = <&cpg 611>; 1900 resets = <&cpg 611>;
1932 iommus = <&ipmmu_vp0 1901 iommus = <&ipmmu_vp0 8>;
1933 }; 1902 };
1934 1903
1935 vspd0: vsp@fea20000 { 1904 vspd0: vsp@fea20000 {
1936 compatible = "renesas 1905 compatible = "renesas,vsp2";
1937 reg = <0 0xfea20000 0 1906 reg = <0 0xfea20000 0 0x7000>;
1938 interrupts = <GIC_SPI 1907 interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>;
1939 clocks = <&cpg CPG_MO 1908 clocks = <&cpg CPG_MOD 623>;
1940 power-domains = <&sys 1909 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1941 resets = <&cpg 623>; 1910 resets = <&cpg 623>;
1942 renesas,fcp = <&fcpvd 1911 renesas,fcp = <&fcpvd0>;
1943 }; 1912 };
1944 1913
1945 fcpvd0: fcp@fea27000 { 1914 fcpvd0: fcp@fea27000 {
1946 compatible = "renesas 1915 compatible = "renesas,fcpv";
1947 reg = <0 0xfea27000 0 1916 reg = <0 0xfea27000 0 0x200>;
1948 clocks = <&cpg CPG_MO 1917 clocks = <&cpg CPG_MOD 603>;
1949 power-domains = <&sys 1918 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1950 resets = <&cpg 603>; 1919 resets = <&cpg 603>;
1951 iommus = <&ipmmu_vi0 1920 iommus = <&ipmmu_vi0 8>;
1952 }; 1921 };
1953 1922
1954 vspd1: vsp@fea28000 { 1923 vspd1: vsp@fea28000 {
1955 compatible = "renesas 1924 compatible = "renesas,vsp2";
1956 reg = <0 0xfea28000 0 1925 reg = <0 0xfea28000 0 0x7000>;
1957 interrupts = <GIC_SPI 1926 interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>;
1958 clocks = <&cpg CPG_MO 1927 clocks = <&cpg CPG_MOD 622>;
1959 power-domains = <&sys 1928 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1960 resets = <&cpg 622>; 1929 resets = <&cpg 622>;
1961 renesas,fcp = <&fcpvd 1930 renesas,fcp = <&fcpvd1>;
1962 }; 1931 };
1963 1932
1964 fcpvd1: fcp@fea2f000 { 1933 fcpvd1: fcp@fea2f000 {
1965 compatible = "renesas 1934 compatible = "renesas,fcpv";
1966 reg = <0 0xfea2f000 0 1935 reg = <0 0xfea2f000 0 0x200>;
1967 clocks = <&cpg CPG_MO 1936 clocks = <&cpg CPG_MOD 602>;
1968 power-domains = <&sys 1937 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1969 resets = <&cpg 602>; 1938 resets = <&cpg 602>;
1970 iommus = <&ipmmu_vi0 1939 iommus = <&ipmmu_vi0 9>;
1971 }; 1940 };
1972 1941
1973 cmm0: cmm@fea40000 { 1942 cmm0: cmm@fea40000 {
1974 compatible = "renesas 1943 compatible = "renesas,r8a77990-cmm",
1975 "renesas 1944 "renesas,rcar-gen3-cmm";
1976 reg = <0 0xfea40000 0 1945 reg = <0 0xfea40000 0 0x1000>;
1977 power-domains = <&sys 1946 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1978 clocks = <&cpg CPG_MO 1947 clocks = <&cpg CPG_MOD 711>;
1979 resets = <&cpg 711>; 1948 resets = <&cpg 711>;
1980 }; 1949 };
1981 1950
1982 cmm1: cmm@fea50000 { 1951 cmm1: cmm@fea50000 {
1983 compatible = "renesas 1952 compatible = "renesas,r8a77990-cmm",
1984 "renesas 1953 "renesas,rcar-gen3-cmm";
1985 reg = <0 0xfea50000 0 1954 reg = <0 0xfea50000 0 0x1000>;
1986 power-domains = <&sys 1955 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1987 clocks = <&cpg CPG_MO 1956 clocks = <&cpg CPG_MOD 710>;
1988 resets = <&cpg 710>; 1957 resets = <&cpg 710>;
1989 }; 1958 };
1990 1959
1991 csi40: csi2@feaa0000 { 1960 csi40: csi2@feaa0000 {
1992 compatible = "renesas 1961 compatible = "renesas,r8a77990-csi2";
1993 reg = <0 0xfeaa0000 0 1962 reg = <0 0xfeaa0000 0 0x10000>;
1994 interrupts = <GIC_SPI 1963 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
1995 clocks = <&cpg CPG_MO 1964 clocks = <&cpg CPG_MOD 716>;
1996 power-domains = <&sys 1965 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1997 resets = <&cpg 716>; 1966 resets = <&cpg 716>;
1998 status = "disabled"; 1967 status = "disabled";
1999 1968
2000 ports { 1969 ports {
2001 #address-cell 1970 #address-cells = <1>;
2002 #size-cells = 1971 #size-cells = <0>;
2003 1972
2004 port@0 { 1973 port@0 {
2005 reg = 1974 reg = <0>;
2006 }; 1975 };
2007 1976
2008 port@1 { 1977 port@1 {
2009 #addr 1978 #address-cells = <1>;
2010 #size 1979 #size-cells = <0>;
2011 1980
2012 reg = 1981 reg = <1>;
2013 1982
2014 csi40 1983 csi40vin4: endpoint@0 {
2015 1984 reg = <0>;
2016 1985 remote-endpoint = <&vin4csi40>;
2017 }; 1986 };
2018 csi40 1987 csi40vin5: endpoint@1 {
2019 1988 reg = <1>;
2020 1989 remote-endpoint = <&vin5csi40>;
2021 }; 1990 };
2022 }; 1991 };
2023 }; 1992 };
2024 }; 1993 };
2025 1994
2026 du: display@feb00000 { 1995 du: display@feb00000 {
2027 compatible = "renesas 1996 compatible = "renesas,du-r8a77990";
2028 reg = <0 0xfeb00000 0 1997 reg = <0 0xfeb00000 0 0x40000>;
2029 interrupts = <GIC_SPI 1998 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
2030 <GIC_SPI 1999 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
2031 clocks = <&cpg CPG_MO 2000 clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>;
2032 clock-names = "du.0", 2001 clock-names = "du.0", "du.1";
2033 resets = <&cpg 724>; 2002 resets = <&cpg 724>;
2034 reset-names = "du.0"; 2003 reset-names = "du.0";
2035 2004
2036 renesas,cmms = <&cmm0 2005 renesas,cmms = <&cmm0>, <&cmm1>;
2037 renesas,vsps = <&vspd 2006 renesas,vsps = <&vspd0 0>, <&vspd1 0>;
2038 2007
2039 status = "disabled"; 2008 status = "disabled";
2040 2009
2041 ports { 2010 ports {
2042 #address-cell 2011 #address-cells = <1>;
2043 #size-cells = 2012 #size-cells = <0>;
2044 2013
2045 port@0 { 2014 port@0 {
2046 reg = 2015 reg = <0>;
>> 2016 du_out_rgb: endpoint {
>> 2017 };
2047 }; 2018 };
2048 2019
2049 port@1 { 2020 port@1 {
2050 reg = 2021 reg = <1>;
2051 du_ou 2022 du_out_lvds0: endpoint {
2052 2023 remote-endpoint = <&lvds0_in>;
2053 }; 2024 };
2054 }; 2025 };
2055 2026
2056 port@2 { 2027 port@2 {
2057 reg = 2028 reg = <2>;
2058 du_ou 2029 du_out_lvds1: endpoint {
2059 2030 remote-endpoint = <&lvds1_in>;
2060 }; 2031 };
2061 }; 2032 };
2062 }; 2033 };
2063 }; 2034 };
2064 2035
2065 lvds0: lvds-encoder@feb90000 2036 lvds0: lvds-encoder@feb90000 {
2066 compatible = "renesas 2037 compatible = "renesas,r8a77990-lvds";
2067 reg = <0 0xfeb90000 0 2038 reg = <0 0xfeb90000 0 0x20>;
2068 clocks = <&cpg CPG_MO 2039 clocks = <&cpg CPG_MOD 727>;
2069 power-domains = <&sys 2040 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
2070 resets = <&cpg 727>; 2041 resets = <&cpg 727>;
2071 status = "disabled"; 2042 status = "disabled";
2072 2043
2073 renesas,companion = < 2044 renesas,companion = <&lvds1>;
2074 2045
2075 ports { 2046 ports {
2076 #address-cell 2047 #address-cells = <1>;
2077 #size-cells = 2048 #size-cells = <0>;
2078 2049
2079 port@0 { 2050 port@0 {
2080 reg = 2051 reg = <0>;
2081 lvds0 2052 lvds0_in: endpoint {
2082 2053 remote-endpoint = <&du_out_lvds0>;
2083 }; 2054 };
2084 }; 2055 };
2085 2056
2086 port@1 { 2057 port@1 {
2087 reg = 2058 reg = <1>;
>> 2059 lvds0_out: endpoint {
>> 2060 };
2088 }; 2061 };
2089 }; 2062 };
2090 }; 2063 };
2091 2064
2092 lvds1: lvds-encoder@feb90100 2065 lvds1: lvds-encoder@feb90100 {
2093 compatible = "renesas 2066 compatible = "renesas,r8a77990-lvds";
2094 reg = <0 0xfeb90100 0 2067 reg = <0 0xfeb90100 0 0x20>;
2095 clocks = <&cpg CPG_MO 2068 clocks = <&cpg CPG_MOD 727>;
2096 power-domains = <&sys 2069 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
2097 resets = <&cpg 726>; 2070 resets = <&cpg 726>;
2098 status = "disabled"; 2071 status = "disabled";
2099 2072
2100 ports { 2073 ports {
2101 #address-cell 2074 #address-cells = <1>;
2102 #size-cells = 2075 #size-cells = <0>;
2103 2076
2104 port@0 { 2077 port@0 {
2105 reg = 2078 reg = <0>;
2106 lvds1 2079 lvds1_in: endpoint {
2107 2080 remote-endpoint = <&du_out_lvds1>;
2108 }; 2081 };
2109 }; 2082 };
2110 2083
2111 port@1 { 2084 port@1 {
2112 reg = 2085 reg = <1>;
>> 2086 lvds1_out: endpoint {
>> 2087 };
2113 }; 2088 };
2114 }; 2089 };
2115 }; 2090 };
2116 2091
2117 prr: chipid@fff00044 { 2092 prr: chipid@fff00044 {
2118 compatible = "renesas 2093 compatible = "renesas,prr";
2119 reg = <0 0xfff00044 0 2094 reg = <0 0xfff00044 0 4>;
2120 }; 2095 };
2121 }; 2096 };
2122 2097
2123 thermal-zones { 2098 thermal-zones {
2124 cpu-thermal { 2099 cpu-thermal {
2125 polling-delay-passive 2100 polling-delay-passive = <250>;
2126 polling-delay = <0>; 2101 polling-delay = <0>;
2127 thermal-sensors = <&t 2102 thermal-sensors = <&thermal>;
2128 sustainable-power = < 2103 sustainable-power = <717>;
2129 2104
2130 cooling-maps { 2105 cooling-maps {
2131 map0 { 2106 map0 {
2132 trip 2107 trip = <&target>;
2133 cooli 2108 cooling-device = <&a53_0 0 2>;
2134 contr 2109 contribution = <1024>;
2135 }; 2110 };
2136 }; 2111 };
2137 2112
2138 trips { 2113 trips {
2139 sensor1_crit: 2114 sensor1_crit: sensor1-crit {
2140 tempe 2115 temperature = <120000>;
2141 hyste 2116 hysteresis = <2000>;
2142 type 2117 type = "critical";
2143 }; 2118 };
2144 2119
2145 target: trip- 2120 target: trip-point1 {
2146 tempe 2121 temperature = <100000>;
2147 hyste 2122 hysteresis = <2000>;
2148 type 2123 type = "passive";
2149 }; 2124 };
2150 }; 2125 };
2151 }; 2126 };
2152 }; 2127 };
2153 2128
2154 timer { 2129 timer {
2155 compatible = "arm,armv8-timer 2130 compatible = "arm,armv8-timer";
2156 interrupts-extended = <&gic G 2131 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
2157 <&gic G 2132 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
2158 <&gic G 2133 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
2159 <&gic G 2134 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
2160 interrupt-names = "sec-phys", <<
2161 }; 2135 };
2162 }; 2136 };
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