1 // SPDX-License-Identifier: GPL-2.0 1 // SPDX-License-Identifier: GPL-2.0
2 /* 2 /*
3 * Device Tree Source for the R-Car E3 (R8A779 3 * Device Tree Source for the R-Car E3 (R8A77990) SoC
4 * 4 *
5 * Copyright (C) 2018-2019 Renesas Electronics 5 * Copyright (C) 2018-2019 Renesas Electronics Corp.
6 */ 6 */
7 7
8 #include <dt-bindings/clock/r8a77990-cpg-mssr. 8 #include <dt-bindings/clock/r8a77990-cpg-mssr.h>
9 #include <dt-bindings/interrupt-controller/arm 9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/power/r8a77990-sysc.h> 10 #include <dt-bindings/power/r8a77990-sysc.h>
11 11
12 / { 12 / {
13 compatible = "renesas,r8a77990"; 13 compatible = "renesas,r8a77990";
14 #address-cells = <2>; 14 #address-cells = <2>;
15 #size-cells = <2>; 15 #size-cells = <2>;
16 16
>> 17 aliases {
>> 18 i2c0 = &i2c0;
>> 19 i2c1 = &i2c1;
>> 20 i2c2 = &i2c2;
>> 21 i2c3 = &i2c3;
>> 22 i2c4 = &i2c4;
>> 23 i2c5 = &i2c5;
>> 24 i2c6 = &i2c6;
>> 25 i2c7 = &i2c7;
>> 26 };
>> 27
17 /* 28 /*
18 * The external audio clocks are confi 29 * The external audio clocks are configured as 0 Hz fixed frequency
19 * clocks by default. 30 * clocks by default.
20 * Boards that provide audio clocks sh 31 * Boards that provide audio clocks should override them.
21 */ 32 */
22 audio_clk_a: audio_clk_a { 33 audio_clk_a: audio_clk_a {
23 compatible = "fixed-clock"; 34 compatible = "fixed-clock";
24 #clock-cells = <0>; 35 #clock-cells = <0>;
25 clock-frequency = <0>; 36 clock-frequency = <0>;
26 }; 37 };
27 38
28 audio_clk_b: audio_clk_b { 39 audio_clk_b: audio_clk_b {
29 compatible = "fixed-clock"; 40 compatible = "fixed-clock";
30 #clock-cells = <0>; 41 #clock-cells = <0>;
31 clock-frequency = <0>; 42 clock-frequency = <0>;
32 }; 43 };
33 44
34 audio_clk_c: audio_clk_c { 45 audio_clk_c: audio_clk_c {
35 compatible = "fixed-clock"; 46 compatible = "fixed-clock";
36 #clock-cells = <0>; 47 #clock-cells = <0>;
37 clock-frequency = <0>; 48 clock-frequency = <0>;
38 }; 49 };
39 50
40 /* External CAN clock - to be overridd 51 /* External CAN clock - to be overridden by boards that provide it */
41 can_clk: can { 52 can_clk: can {
42 compatible = "fixed-clock"; 53 compatible = "fixed-clock";
43 #clock-cells = <0>; 54 #clock-cells = <0>;
44 clock-frequency = <0>; 55 clock-frequency = <0>;
45 }; 56 };
46 57
47 cluster1_opp: opp-table-1 { !! 58 cluster1_opp: opp_table10 {
48 compatible = "operating-points 59 compatible = "operating-points-v2";
49 opp-shared; 60 opp-shared;
50 opp-800000000 { 61 opp-800000000 {
51 opp-hz = /bits/ 64 <80 62 opp-hz = /bits/ 64 <800000000>;
>> 63 opp-microvolt = <820000>;
52 clock-latency-ns = <30 64 clock-latency-ns = <300000>;
53 }; 65 };
54 opp-1000000000 { 66 opp-1000000000 {
55 opp-hz = /bits/ 64 <10 67 opp-hz = /bits/ 64 <1000000000>;
>> 68 opp-microvolt = <820000>;
56 clock-latency-ns = <30 69 clock-latency-ns = <300000>;
57 }; 70 };
58 opp-1200000000 { 71 opp-1200000000 {
59 opp-hz = /bits/ 64 <12 72 opp-hz = /bits/ 64 <1200000000>;
>> 73 opp-microvolt = <820000>;
60 clock-latency-ns = <30 74 clock-latency-ns = <300000>;
61 opp-suspend; 75 opp-suspend;
62 }; 76 };
63 }; 77 };
64 78
65 cpus { 79 cpus {
66 #address-cells = <1>; 80 #address-cells = <1>;
67 #size-cells = <0>; 81 #size-cells = <0>;
68 82
69 a53_0: cpu@0 { 83 a53_0: cpu@0 {
70 compatible = "arm,cort 84 compatible = "arm,cortex-a53";
71 reg = <0>; 85 reg = <0>;
72 device_type = "cpu"; 86 device_type = "cpu";
73 #cooling-cells = <2>; 87 #cooling-cells = <2>;
74 power-domains = <&sysc 88 power-domains = <&sysc R8A77990_PD_CA53_CPU0>;
75 next-level-cache = <&L 89 next-level-cache = <&L2_CA53>;
76 enable-method = "psci" 90 enable-method = "psci";
77 cpu-idle-states = <&CP <<
78 dynamic-power-coeffici 91 dynamic-power-coefficient = <277>;
79 clocks = <&cpg CPG_COR !! 92 clocks =<&cpg CPG_CORE R8A77990_CLK_Z2>;
80 operating-points-v2 = 93 operating-points-v2 = <&cluster1_opp>;
81 }; 94 };
82 95
83 a53_1: cpu@1 { 96 a53_1: cpu@1 {
84 compatible = "arm,cort 97 compatible = "arm,cortex-a53";
85 reg = <1>; 98 reg = <1>;
86 device_type = "cpu"; 99 device_type = "cpu";
87 power-domains = <&sysc 100 power-domains = <&sysc R8A77990_PD_CA53_CPU1>;
88 next-level-cache = <&L 101 next-level-cache = <&L2_CA53>;
89 enable-method = "psci" 102 enable-method = "psci";
90 cpu-idle-states = <&CP !! 103 clocks =<&cpg CPG_CORE R8A77990_CLK_Z2>;
91 clocks = <&cpg CPG_COR <<
92 operating-points-v2 = 104 operating-points-v2 = <&cluster1_opp>;
93 }; 105 };
94 106
95 L2_CA53: cache-controller-0 { 107 L2_CA53: cache-controller-0 {
96 compatible = "cache"; 108 compatible = "cache";
97 power-domains = <&sysc 109 power-domains = <&sysc R8A77990_PD_CA53_SCU>;
98 cache-unified; 110 cache-unified;
99 cache-level = <2>; 111 cache-level = <2>;
100 }; 112 };
101 <<
102 idle-states { <<
103 entry-method = "psci"; <<
104 <<
105 CPU_SLEEP_0: cpu-sleep <<
106 compatible = " <<
107 arm,psci-suspe <<
108 local-timer-st <<
109 entry-latency- <<
110 exit-latency-u <<
111 min-residency- <<
112 }; <<
113 }; <<
114 }; 113 };
115 114
116 extal_clk: extal { 115 extal_clk: extal {
117 compatible = "fixed-clock"; 116 compatible = "fixed-clock";
118 #clock-cells = <0>; 117 #clock-cells = <0>;
119 /* This value must be overridd 118 /* This value must be overridden by the board */
120 clock-frequency = <0>; 119 clock-frequency = <0>;
121 }; 120 };
122 121
123 /* External PCIe clock - can be overri 122 /* External PCIe clock - can be overridden by the board */
124 pcie_bus_clk: pcie_bus { 123 pcie_bus_clk: pcie_bus {
125 compatible = "fixed-clock"; 124 compatible = "fixed-clock";
126 #clock-cells = <0>; 125 #clock-cells = <0>;
127 clock-frequency = <0>; 126 clock-frequency = <0>;
128 }; 127 };
129 128
130 pmu_a53 { 129 pmu_a53 {
131 compatible = "arm,cortex-a53-p 130 compatible = "arm,cortex-a53-pmu";
132 interrupts-extended = <&gic GI 131 interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
133 <&gic GI 132 <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
134 interrupt-affinity = <&a53_0>, 133 interrupt-affinity = <&a53_0>, <&a53_1>;
135 }; 134 };
136 135
137 psci { 136 psci {
138 compatible = "arm,psci-1.0", " 137 compatible = "arm,psci-1.0", "arm,psci-0.2";
139 method = "smc"; 138 method = "smc";
140 }; 139 };
141 140
142 /* External SCIF clock - to be overrid 141 /* External SCIF clock - to be overridden by boards that provide it */
143 scif_clk: scif { 142 scif_clk: scif {
144 compatible = "fixed-clock"; 143 compatible = "fixed-clock";
145 #clock-cells = <0>; 144 #clock-cells = <0>;
146 clock-frequency = <0>; 145 clock-frequency = <0>;
147 }; 146 };
148 147
149 soc: soc { 148 soc: soc {
150 compatible = "simple-bus"; 149 compatible = "simple-bus";
151 interrupt-parent = <&gic>; 150 interrupt-parent = <&gic>;
152 #address-cells = <2>; 151 #address-cells = <2>;
153 #size-cells = <2>; 152 #size-cells = <2>;
154 ranges; 153 ranges;
155 154
156 rwdt: watchdog@e6020000 { 155 rwdt: watchdog@e6020000 {
157 compatible = "renesas, 156 compatible = "renesas,r8a77990-wdt",
158 "renesas, 157 "renesas,rcar-gen3-wdt";
159 reg = <0 0xe6020000 0 158 reg = <0 0xe6020000 0 0x0c>;
160 interrupts = <GIC_SPI <<
161 clocks = <&cpg CPG_MOD 159 clocks = <&cpg CPG_MOD 402>;
162 power-domains = <&sysc 160 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
163 resets = <&cpg 402>; 161 resets = <&cpg 402>;
164 status = "disabled"; 162 status = "disabled";
165 }; 163 };
166 164
167 gpio0: gpio@e6050000 { 165 gpio0: gpio@e6050000 {
168 compatible = "renesas, 166 compatible = "renesas,gpio-r8a77990",
169 "renesas, 167 "renesas,rcar-gen3-gpio";
170 reg = <0 0xe6050000 0 168 reg = <0 0xe6050000 0 0x50>;
171 interrupts = <GIC_SPI 169 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
172 #gpio-cells = <2>; 170 #gpio-cells = <2>;
173 gpio-controller; 171 gpio-controller;
174 gpio-ranges = <&pfc 0 172 gpio-ranges = <&pfc 0 0 18>;
175 #interrupt-cells = <2> 173 #interrupt-cells = <2>;
176 interrupt-controller; 174 interrupt-controller;
177 clocks = <&cpg CPG_MOD 175 clocks = <&cpg CPG_MOD 912>;
178 power-domains = <&sysc 176 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
179 resets = <&cpg 912>; 177 resets = <&cpg 912>;
180 }; 178 };
181 179
182 gpio1: gpio@e6051000 { 180 gpio1: gpio@e6051000 {
183 compatible = "renesas, 181 compatible = "renesas,gpio-r8a77990",
184 "renesas, 182 "renesas,rcar-gen3-gpio";
185 reg = <0 0xe6051000 0 183 reg = <0 0xe6051000 0 0x50>;
186 interrupts = <GIC_SPI 184 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
187 #gpio-cells = <2>; 185 #gpio-cells = <2>;
188 gpio-controller; 186 gpio-controller;
189 gpio-ranges = <&pfc 0 187 gpio-ranges = <&pfc 0 32 23>;
190 #interrupt-cells = <2> 188 #interrupt-cells = <2>;
191 interrupt-controller; 189 interrupt-controller;
192 clocks = <&cpg CPG_MOD 190 clocks = <&cpg CPG_MOD 911>;
193 power-domains = <&sysc 191 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
194 resets = <&cpg 911>; 192 resets = <&cpg 911>;
195 }; 193 };
196 194
197 gpio2: gpio@e6052000 { 195 gpio2: gpio@e6052000 {
198 compatible = "renesas, 196 compatible = "renesas,gpio-r8a77990",
199 "renesas, 197 "renesas,rcar-gen3-gpio";
200 reg = <0 0xe6052000 0 198 reg = <0 0xe6052000 0 0x50>;
201 interrupts = <GIC_SPI 199 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
202 #gpio-cells = <2>; 200 #gpio-cells = <2>;
203 gpio-controller; 201 gpio-controller;
204 gpio-ranges = <&pfc 0 202 gpio-ranges = <&pfc 0 64 26>;
205 #interrupt-cells = <2> 203 #interrupt-cells = <2>;
206 interrupt-controller; 204 interrupt-controller;
207 clocks = <&cpg CPG_MOD 205 clocks = <&cpg CPG_MOD 910>;
208 power-domains = <&sysc 206 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
209 resets = <&cpg 910>; 207 resets = <&cpg 910>;
210 }; 208 };
211 209
212 gpio3: gpio@e6053000 { 210 gpio3: gpio@e6053000 {
213 compatible = "renesas, 211 compatible = "renesas,gpio-r8a77990",
214 "renesas, 212 "renesas,rcar-gen3-gpio";
215 reg = <0 0xe6053000 0 213 reg = <0 0xe6053000 0 0x50>;
216 interrupts = <GIC_SPI 214 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
217 #gpio-cells = <2>; 215 #gpio-cells = <2>;
218 gpio-controller; 216 gpio-controller;
219 gpio-ranges = <&pfc 0 217 gpio-ranges = <&pfc 0 96 16>;
220 #interrupt-cells = <2> 218 #interrupt-cells = <2>;
221 interrupt-controller; 219 interrupt-controller;
222 clocks = <&cpg CPG_MOD 220 clocks = <&cpg CPG_MOD 909>;
223 power-domains = <&sysc 221 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
224 resets = <&cpg 909>; 222 resets = <&cpg 909>;
225 }; 223 };
226 224
227 gpio4: gpio@e6054000 { 225 gpio4: gpio@e6054000 {
228 compatible = "renesas, 226 compatible = "renesas,gpio-r8a77990",
229 "renesas, 227 "renesas,rcar-gen3-gpio";
230 reg = <0 0xe6054000 0 228 reg = <0 0xe6054000 0 0x50>;
231 interrupts = <GIC_SPI 229 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
232 #gpio-cells = <2>; 230 #gpio-cells = <2>;
233 gpio-controller; 231 gpio-controller;
234 gpio-ranges = <&pfc 0 232 gpio-ranges = <&pfc 0 128 11>;
235 #interrupt-cells = <2> 233 #interrupt-cells = <2>;
236 interrupt-controller; 234 interrupt-controller;
237 clocks = <&cpg CPG_MOD 235 clocks = <&cpg CPG_MOD 908>;
238 power-domains = <&sysc 236 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
239 resets = <&cpg 908>; 237 resets = <&cpg 908>;
240 }; 238 };
241 239
242 gpio5: gpio@e6055000 { 240 gpio5: gpio@e6055000 {
243 compatible = "renesas, 241 compatible = "renesas,gpio-r8a77990",
244 "renesas, 242 "renesas,rcar-gen3-gpio";
245 reg = <0 0xe6055000 0 243 reg = <0 0xe6055000 0 0x50>;
246 interrupts = <GIC_SPI 244 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
247 #gpio-cells = <2>; 245 #gpio-cells = <2>;
248 gpio-controller; 246 gpio-controller;
249 gpio-ranges = <&pfc 0 247 gpio-ranges = <&pfc 0 160 20>;
250 #interrupt-cells = <2> 248 #interrupt-cells = <2>;
251 interrupt-controller; 249 interrupt-controller;
252 clocks = <&cpg CPG_MOD 250 clocks = <&cpg CPG_MOD 907>;
253 power-domains = <&sysc 251 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
254 resets = <&cpg 907>; 252 resets = <&cpg 907>;
255 }; 253 };
256 254
257 gpio6: gpio@e6055400 { 255 gpio6: gpio@e6055400 {
258 compatible = "renesas, 256 compatible = "renesas,gpio-r8a77990",
259 "renesas, 257 "renesas,rcar-gen3-gpio";
260 reg = <0 0xe6055400 0 258 reg = <0 0xe6055400 0 0x50>;
261 interrupts = <GIC_SPI 259 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
262 #gpio-cells = <2>; 260 #gpio-cells = <2>;
263 gpio-controller; 261 gpio-controller;
264 gpio-ranges = <&pfc 0 262 gpio-ranges = <&pfc 0 192 18>;
265 #interrupt-cells = <2> 263 #interrupt-cells = <2>;
266 interrupt-controller; 264 interrupt-controller;
267 clocks = <&cpg CPG_MOD 265 clocks = <&cpg CPG_MOD 906>;
268 power-domains = <&sysc 266 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
269 resets = <&cpg 906>; 267 resets = <&cpg 906>;
270 }; 268 };
271 269
272 pfc: pinctrl@e6060000 { !! 270 pfc: pin-controller@e6060000 {
273 compatible = "renesas, 271 compatible = "renesas,pfc-r8a77990";
274 reg = <0 0xe6060000 0 272 reg = <0 0xe6060000 0 0x508>;
275 }; 273 };
276 274
277 i2c_dvfs: i2c@e60b0000 { 275 i2c_dvfs: i2c@e60b0000 {
278 #address-cells = <1>; 276 #address-cells = <1>;
279 #size-cells = <0>; 277 #size-cells = <0>;
280 compatible = "renesas, !! 278 compatible = "renesas,iic-r8a77990";
281 "renesas, !! 279 reg = <0 0xe60b0000 0 0x15>;
282 "renesas, <<
283 reg = <0 0xe60b0000 0 <<
284 interrupts = <GIC_SPI 280 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
285 clocks = <&cpg CPG_MOD 281 clocks = <&cpg CPG_MOD 926>;
286 power-domains = <&sysc 282 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
287 resets = <&cpg 926>; 283 resets = <&cpg 926>;
288 dmas = <&dmac0 0x11>, 284 dmas = <&dmac0 0x11>, <&dmac0 0x10>;
289 dma-names = "tx", "rx" 285 dma-names = "tx", "rx";
290 status = "disabled"; 286 status = "disabled";
291 }; 287 };
292 288
293 cmt0: timer@e60f0000 { 289 cmt0: timer@e60f0000 {
294 compatible = "renesas, 290 compatible = "renesas,r8a77990-cmt0",
295 "renesas, 291 "renesas,rcar-gen3-cmt0";
296 reg = <0 0xe60f0000 0 292 reg = <0 0xe60f0000 0 0x1004>;
297 interrupts = <GIC_SPI 293 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
298 <GIC_SPI 294 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
299 clocks = <&cpg CPG_MOD 295 clocks = <&cpg CPG_MOD 303>;
300 clock-names = "fck"; 296 clock-names = "fck";
301 power-domains = <&sysc 297 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
302 resets = <&cpg 303>; 298 resets = <&cpg 303>;
303 status = "disabled"; 299 status = "disabled";
304 }; 300 };
305 301
306 cmt1: timer@e6130000 { 302 cmt1: timer@e6130000 {
307 compatible = "renesas, 303 compatible = "renesas,r8a77990-cmt1",
308 "renesas, 304 "renesas,rcar-gen3-cmt1";
309 reg = <0 0xe6130000 0 305 reg = <0 0xe6130000 0 0x1004>;
310 interrupts = <GIC_SPI 306 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
311 <GIC_SPI 307 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
312 <GIC_SPI 308 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
313 <GIC_SPI 309 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
314 <GIC_SPI 310 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
315 <GIC_SPI 311 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
316 <GIC_SPI 312 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
317 <GIC_SPI 313 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
318 clocks = <&cpg CPG_MOD 314 clocks = <&cpg CPG_MOD 302>;
319 clock-names = "fck"; 315 clock-names = "fck";
320 power-domains = <&sysc 316 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
321 resets = <&cpg 302>; 317 resets = <&cpg 302>;
322 status = "disabled"; 318 status = "disabled";
323 }; 319 };
324 320
325 cmt2: timer@e6140000 { 321 cmt2: timer@e6140000 {
326 compatible = "renesas, 322 compatible = "renesas,r8a77990-cmt1",
327 "renesas, 323 "renesas,rcar-gen3-cmt1";
328 reg = <0 0xe6140000 0 324 reg = <0 0xe6140000 0 0x1004>;
329 interrupts = <GIC_SPI 325 interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
330 <GIC_SPI 326 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
331 <GIC_SPI 327 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
332 <GIC_SPI 328 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
333 <GIC_SPI 329 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
334 <GIC_SPI 330 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
335 <GIC_SPI 331 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
336 <GIC_SPI 332 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>;
337 clocks = <&cpg CPG_MOD 333 clocks = <&cpg CPG_MOD 301>;
338 clock-names = "fck"; 334 clock-names = "fck";
339 power-domains = <&sysc 335 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
340 resets = <&cpg 301>; 336 resets = <&cpg 301>;
341 status = "disabled"; 337 status = "disabled";
342 }; 338 };
343 339
344 cmt3: timer@e6148000 { 340 cmt3: timer@e6148000 {
345 compatible = "renesas, 341 compatible = "renesas,r8a77990-cmt1",
346 "renesas, 342 "renesas,rcar-gen3-cmt1";
347 reg = <0 0xe6148000 0 343 reg = <0 0xe6148000 0 0x1004>;
348 interrupts = <GIC_SPI 344 interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>,
349 <GIC_SPI 345 <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>,
350 <GIC_SPI 346 <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>,
351 <GIC_SPI 347 <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>,
352 <GIC_SPI 348 <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>,
353 <GIC_SPI 349 <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>,
354 <GIC_SPI 350 <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>,
355 <GIC_SPI 351 <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>;
356 clocks = <&cpg CPG_MOD 352 clocks = <&cpg CPG_MOD 300>;
357 clock-names = "fck"; 353 clock-names = "fck";
358 power-domains = <&sysc 354 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
359 resets = <&cpg 300>; 355 resets = <&cpg 300>;
360 status = "disabled"; 356 status = "disabled";
361 }; 357 };
362 358
363 cpg: clock-controller@e6150000 359 cpg: clock-controller@e6150000 {
364 compatible = "renesas, 360 compatible = "renesas,r8a77990-cpg-mssr";
365 reg = <0 0xe6150000 0 361 reg = <0 0xe6150000 0 0x1000>;
366 clocks = <&extal_clk>; 362 clocks = <&extal_clk>;
367 clock-names = "extal"; 363 clock-names = "extal";
368 #clock-cells = <2>; 364 #clock-cells = <2>;
369 #power-domain-cells = 365 #power-domain-cells = <0>;
370 #reset-cells = <1>; 366 #reset-cells = <1>;
371 }; 367 };
372 368
373 rst: reset-controller@e6160000 369 rst: reset-controller@e6160000 {
374 compatible = "renesas, 370 compatible = "renesas,r8a77990-rst";
375 reg = <0 0xe6160000 0 371 reg = <0 0xe6160000 0 0x0200>;
376 }; 372 };
377 373
378 sysc: system-controller@e61800 374 sysc: system-controller@e6180000 {
379 compatible = "renesas, 375 compatible = "renesas,r8a77990-sysc";
380 reg = <0 0xe6180000 0 376 reg = <0 0xe6180000 0 0x0400>;
381 #power-domain-cells = 377 #power-domain-cells = <1>;
382 }; 378 };
383 379
384 thermal: thermal@e6190000 { 380 thermal: thermal@e6190000 {
385 compatible = "renesas, 381 compatible = "renesas,thermal-r8a77990";
386 reg = <0 0xe6190000 0 382 reg = <0 0xe6190000 0 0x10>, <0 0xe6190100 0 0x38>;
387 interrupts = <GIC_SPI 383 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
388 <GIC_SPI 384 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
389 <GIC_SPI 385 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
390 clocks = <&cpg CPG_MOD 386 clocks = <&cpg CPG_MOD 522>;
391 power-domains = <&sysc 387 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
392 resets = <&cpg 522>; 388 resets = <&cpg 522>;
393 #thermal-sensor-cells 389 #thermal-sensor-cells = <0>;
394 }; 390 };
395 391
396 intc_ex: interrupt-controller@ 392 intc_ex: interrupt-controller@e61c0000 {
397 compatible = "renesas, 393 compatible = "renesas,intc-ex-r8a77990", "renesas,irqc";
398 #interrupt-cells = <2> 394 #interrupt-cells = <2>;
399 interrupt-controller; 395 interrupt-controller;
400 reg = <0 0xe61c0000 0 396 reg = <0 0xe61c0000 0 0x200>;
401 interrupts = <GIC_SPI !! 397 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH
402 <GIC_SPI !! 398 GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH
403 <GIC_SPI !! 399 GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH
404 <GIC_SPI !! 400 GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH
405 <GIC_SPI !! 401 GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH
406 <GIC_SPI !! 402 GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
407 clocks = <&cpg CPG_MOD 403 clocks = <&cpg CPG_MOD 407>;
408 power-domains = <&sysc 404 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
409 resets = <&cpg 407>; 405 resets = <&cpg 407>;
410 }; 406 };
411 407
412 tmu0: timer@e61e0000 { <<
413 compatible = "renesas, <<
414 reg = <0 0xe61e0000 0 <<
415 interrupts = <GIC_SPI <<
416 <GIC_SPI <<
417 <GIC_SPI <<
418 interrupt-names = "tun <<
419 clocks = <&cpg CPG_MOD <<
420 clock-names = "fck"; <<
421 power-domains = <&sysc <<
422 resets = <&cpg 125>; <<
423 status = "disabled"; <<
424 }; <<
425 <<
426 tmu1: timer@e6fc0000 { <<
427 compatible = "renesas, <<
428 reg = <0 0xe6fc0000 0 <<
429 interrupts = <GIC_SPI <<
430 <GIC_SPI <<
431 <GIC_SPI <<
432 <GIC_SPI <<
433 interrupt-names = "tun <<
434 clocks = <&cpg CPG_MOD <<
435 clock-names = "fck"; <<
436 power-domains = <&sysc <<
437 resets = <&cpg 124>; <<
438 status = "disabled"; <<
439 }; <<
440 <<
441 tmu2: timer@e6fd0000 { <<
442 compatible = "renesas, <<
443 reg = <0 0xe6fd0000 0 <<
444 interrupts = <GIC_SPI <<
445 <GIC_SPI <<
446 <GIC_SPI <<
447 <GIC_SPI <<
448 interrupt-names = "tun <<
449 clocks = <&cpg CPG_MOD <<
450 clock-names = "fck"; <<
451 power-domains = <&sysc <<
452 resets = <&cpg 123>; <<
453 status = "disabled"; <<
454 }; <<
455 <<
456 tmu3: timer@e6fe0000 { <<
457 compatible = "renesas, <<
458 reg = <0 0xe6fe0000 0 <<
459 interrupts = <GIC_SPI <<
460 <GIC_SPI <<
461 <GIC_SPI <<
462 interrupt-names = "tun <<
463 clocks = <&cpg CPG_MOD <<
464 clock-names = "fck"; <<
465 power-domains = <&sysc <<
466 resets = <&cpg 122>; <<
467 status = "disabled"; <<
468 }; <<
469 <<
470 tmu4: timer@ffc00000 { <<
471 compatible = "renesas, <<
472 reg = <0 0xffc00000 0 <<
473 interrupts = <GIC_SPI <<
474 <GIC_SPI <<
475 <GIC_SPI <<
476 interrupt-names = "tun <<
477 clocks = <&cpg CPG_MOD <<
478 clock-names = "fck"; <<
479 power-domains = <&sysc <<
480 resets = <&cpg 121>; <<
481 status = "disabled"; <<
482 }; <<
483 <<
484 i2c0: i2c@e6500000 { 408 i2c0: i2c@e6500000 {
485 #address-cells = <1>; 409 #address-cells = <1>;
486 #size-cells = <0>; 410 #size-cells = <0>;
487 compatible = "renesas, 411 compatible = "renesas,i2c-r8a77990",
488 "renesas, 412 "renesas,rcar-gen3-i2c";
489 reg = <0 0xe6500000 0 413 reg = <0 0xe6500000 0 0x40>;
490 interrupts = <GIC_SPI 414 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
491 clocks = <&cpg CPG_MOD 415 clocks = <&cpg CPG_MOD 931>;
492 power-domains = <&sysc 416 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
493 resets = <&cpg 931>; 417 resets = <&cpg 931>;
494 dmas = <&dmac1 0x91>, 418 dmas = <&dmac1 0x91>, <&dmac1 0x90>,
495 <&dmac2 0x91>, 419 <&dmac2 0x91>, <&dmac2 0x90>;
496 dma-names = "tx", "rx" 420 dma-names = "tx", "rx", "tx", "rx";
497 i2c-scl-internal-delay 421 i2c-scl-internal-delay-ns = <110>;
498 status = "disabled"; 422 status = "disabled";
499 }; 423 };
500 424
501 i2c1: i2c@e6508000 { 425 i2c1: i2c@e6508000 {
502 #address-cells = <1>; 426 #address-cells = <1>;
503 #size-cells = <0>; 427 #size-cells = <0>;
504 compatible = "renesas, 428 compatible = "renesas,i2c-r8a77990",
505 "renesas, 429 "renesas,rcar-gen3-i2c";
506 reg = <0 0xe6508000 0 430 reg = <0 0xe6508000 0 0x40>;
507 interrupts = <GIC_SPI 431 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
508 clocks = <&cpg CPG_MOD 432 clocks = <&cpg CPG_MOD 930>;
509 power-domains = <&sysc 433 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
510 resets = <&cpg 930>; 434 resets = <&cpg 930>;
511 dmas = <&dmac1 0x93>, 435 dmas = <&dmac1 0x93>, <&dmac1 0x92>,
512 <&dmac2 0x93>, 436 <&dmac2 0x93>, <&dmac2 0x92>;
513 dma-names = "tx", "rx" 437 dma-names = "tx", "rx", "tx", "rx";
514 i2c-scl-internal-delay 438 i2c-scl-internal-delay-ns = <6>;
515 status = "disabled"; 439 status = "disabled";
516 }; 440 };
517 441
518 i2c2: i2c@e6510000 { 442 i2c2: i2c@e6510000 {
519 #address-cells = <1>; 443 #address-cells = <1>;
520 #size-cells = <0>; 444 #size-cells = <0>;
521 compatible = "renesas, 445 compatible = "renesas,i2c-r8a77990",
522 "renesas, 446 "renesas,rcar-gen3-i2c";
523 reg = <0 0xe6510000 0 447 reg = <0 0xe6510000 0 0x40>;
524 interrupts = <GIC_SPI 448 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
525 clocks = <&cpg CPG_MOD 449 clocks = <&cpg CPG_MOD 929>;
526 power-domains = <&sysc 450 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
527 resets = <&cpg 929>; 451 resets = <&cpg 929>;
528 dmas = <&dmac1 0x95>, 452 dmas = <&dmac1 0x95>, <&dmac1 0x94>,
529 <&dmac2 0x95>, 453 <&dmac2 0x95>, <&dmac2 0x94>;
530 dma-names = "tx", "rx" 454 dma-names = "tx", "rx", "tx", "rx";
531 i2c-scl-internal-delay 455 i2c-scl-internal-delay-ns = <6>;
532 status = "disabled"; 456 status = "disabled";
533 }; 457 };
534 458
535 i2c3: i2c@e66d0000 { 459 i2c3: i2c@e66d0000 {
536 #address-cells = <1>; 460 #address-cells = <1>;
537 #size-cells = <0>; 461 #size-cells = <0>;
538 compatible = "renesas, 462 compatible = "renesas,i2c-r8a77990",
539 "renesas, 463 "renesas,rcar-gen3-i2c";
540 reg = <0 0xe66d0000 0 464 reg = <0 0xe66d0000 0 0x40>;
541 interrupts = <GIC_SPI 465 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
542 clocks = <&cpg CPG_MOD 466 clocks = <&cpg CPG_MOD 928>;
543 power-domains = <&sysc 467 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
544 resets = <&cpg 928>; 468 resets = <&cpg 928>;
545 dmas = <&dmac0 0x97>, 469 dmas = <&dmac0 0x97>, <&dmac0 0x96>;
546 dma-names = "tx", "rx" 470 dma-names = "tx", "rx";
547 i2c-scl-internal-delay 471 i2c-scl-internal-delay-ns = <110>;
548 status = "disabled"; 472 status = "disabled";
549 }; 473 };
550 474
551 i2c4: i2c@e66d8000 { 475 i2c4: i2c@e66d8000 {
552 #address-cells = <1>; 476 #address-cells = <1>;
553 #size-cells = <0>; 477 #size-cells = <0>;
554 compatible = "renesas, 478 compatible = "renesas,i2c-r8a77990",
555 "renesas, 479 "renesas,rcar-gen3-i2c";
556 reg = <0 0xe66d8000 0 480 reg = <0 0xe66d8000 0 0x40>;
557 interrupts = <GIC_SPI 481 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
558 clocks = <&cpg CPG_MOD 482 clocks = <&cpg CPG_MOD 927>;
559 power-domains = <&sysc 483 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
560 resets = <&cpg 927>; 484 resets = <&cpg 927>;
561 dmas = <&dmac0 0x99>, 485 dmas = <&dmac0 0x99>, <&dmac0 0x98>;
562 dma-names = "tx", "rx" 486 dma-names = "tx", "rx";
563 i2c-scl-internal-delay 487 i2c-scl-internal-delay-ns = <6>;
564 status = "disabled"; 488 status = "disabled";
565 }; 489 };
566 490
567 i2c5: i2c@e66e0000 { 491 i2c5: i2c@e66e0000 {
568 #address-cells = <1>; 492 #address-cells = <1>;
569 #size-cells = <0>; 493 #size-cells = <0>;
570 compatible = "renesas, 494 compatible = "renesas,i2c-r8a77990",
571 "renesas, 495 "renesas,rcar-gen3-i2c";
572 reg = <0 0xe66e0000 0 496 reg = <0 0xe66e0000 0 0x40>;
573 interrupts = <GIC_SPI 497 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
574 clocks = <&cpg CPG_MOD 498 clocks = <&cpg CPG_MOD 919>;
575 power-domains = <&sysc 499 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
576 resets = <&cpg 919>; 500 resets = <&cpg 919>;
577 dmas = <&dmac0 0x9b>, 501 dmas = <&dmac0 0x9b>, <&dmac0 0x9a>;
578 dma-names = "tx", "rx" 502 dma-names = "tx", "rx";
579 i2c-scl-internal-delay 503 i2c-scl-internal-delay-ns = <6>;
580 status = "disabled"; 504 status = "disabled";
581 }; 505 };
582 506
583 i2c6: i2c@e66e8000 { 507 i2c6: i2c@e66e8000 {
584 #address-cells = <1>; 508 #address-cells = <1>;
585 #size-cells = <0>; 509 #size-cells = <0>;
586 compatible = "renesas, 510 compatible = "renesas,i2c-r8a77990",
587 "renesas, 511 "renesas,rcar-gen3-i2c";
588 reg = <0 0xe66e8000 0 512 reg = <0 0xe66e8000 0 0x40>;
589 interrupts = <GIC_SPI 513 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
590 clocks = <&cpg CPG_MOD 514 clocks = <&cpg CPG_MOD 918>;
591 power-domains = <&sysc 515 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
592 resets = <&cpg 918>; 516 resets = <&cpg 918>;
593 dmas = <&dmac0 0x9d>, 517 dmas = <&dmac0 0x9d>, <&dmac0 0x9c>;
594 dma-names = "tx", "rx" 518 dma-names = "tx", "rx";
595 i2c-scl-internal-delay 519 i2c-scl-internal-delay-ns = <6>;
596 status = "disabled"; 520 status = "disabled";
597 }; 521 };
598 522
599 i2c7: i2c@e6690000 { 523 i2c7: i2c@e6690000 {
600 #address-cells = <1>; 524 #address-cells = <1>;
601 #size-cells = <0>; 525 #size-cells = <0>;
602 compatible = "renesas, 526 compatible = "renesas,i2c-r8a77990",
603 "renesas, 527 "renesas,rcar-gen3-i2c";
604 reg = <0 0xe6690000 0 528 reg = <0 0xe6690000 0 0x40>;
605 interrupts = <GIC_SPI 529 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
606 clocks = <&cpg CPG_MOD 530 clocks = <&cpg CPG_MOD 1003>;
607 power-domains = <&sysc 531 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
608 resets = <&cpg 1003>; 532 resets = <&cpg 1003>;
609 i2c-scl-internal-delay 533 i2c-scl-internal-delay-ns = <6>;
610 status = "disabled"; 534 status = "disabled";
611 }; 535 };
612 536
613 hscif0: serial@e6540000 { 537 hscif0: serial@e6540000 {
614 compatible = "renesas, 538 compatible = "renesas,hscif-r8a77990",
615 "renesas, 539 "renesas,rcar-gen3-hscif",
616 "renesas, 540 "renesas,hscif";
617 reg = <0 0xe6540000 0 541 reg = <0 0xe6540000 0 0x60>;
618 interrupts = <GIC_SPI 542 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
619 clocks = <&cpg CPG_MOD 543 clocks = <&cpg CPG_MOD 520>,
620 <&cpg CPG_COR 544 <&cpg CPG_CORE R8A77990_CLK_S3D1C>,
621 <&scif_clk>; 545 <&scif_clk>;
622 clock-names = "fck", " 546 clock-names = "fck", "brg_int", "scif_clk";
623 dmas = <&dmac1 0x31>, 547 dmas = <&dmac1 0x31>, <&dmac1 0x30>,
624 <&dmac2 0x31>, 548 <&dmac2 0x31>, <&dmac2 0x30>;
625 dma-names = "tx", "rx" 549 dma-names = "tx", "rx", "tx", "rx";
626 power-domains = <&sysc 550 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
627 resets = <&cpg 520>; 551 resets = <&cpg 520>;
628 status = "disabled"; 552 status = "disabled";
629 }; 553 };
630 554
631 hscif1: serial@e6550000 { 555 hscif1: serial@e6550000 {
632 compatible = "renesas, 556 compatible = "renesas,hscif-r8a77990",
633 "renesas, 557 "renesas,rcar-gen3-hscif",
634 "renesas, 558 "renesas,hscif";
635 reg = <0 0xe6550000 0 559 reg = <0 0xe6550000 0 0x60>;
636 interrupts = <GIC_SPI 560 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
637 clocks = <&cpg CPG_MOD 561 clocks = <&cpg CPG_MOD 519>,
638 <&cpg CPG_COR 562 <&cpg CPG_CORE R8A77990_CLK_S3D1C>,
639 <&scif_clk>; 563 <&scif_clk>;
640 clock-names = "fck", " 564 clock-names = "fck", "brg_int", "scif_clk";
641 dmas = <&dmac1 0x33>, 565 dmas = <&dmac1 0x33>, <&dmac1 0x32>,
642 <&dmac2 0x33>, 566 <&dmac2 0x33>, <&dmac2 0x32>;
643 dma-names = "tx", "rx" 567 dma-names = "tx", "rx", "tx", "rx";
644 power-domains = <&sysc 568 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
645 resets = <&cpg 519>; 569 resets = <&cpg 519>;
646 status = "disabled"; 570 status = "disabled";
647 }; 571 };
648 572
649 hscif2: serial@e6560000 { 573 hscif2: serial@e6560000 {
650 compatible = "renesas, 574 compatible = "renesas,hscif-r8a77990",
651 "renesas, 575 "renesas,rcar-gen3-hscif",
652 "renesas, 576 "renesas,hscif";
653 reg = <0 0xe6560000 0 577 reg = <0 0xe6560000 0 0x60>;
654 interrupts = <GIC_SPI 578 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
655 clocks = <&cpg CPG_MOD 579 clocks = <&cpg CPG_MOD 518>,
656 <&cpg CPG_COR 580 <&cpg CPG_CORE R8A77990_CLK_S3D1C>,
657 <&scif_clk>; 581 <&scif_clk>;
658 clock-names = "fck", " 582 clock-names = "fck", "brg_int", "scif_clk";
659 dmas = <&dmac1 0x35>, 583 dmas = <&dmac1 0x35>, <&dmac1 0x34>,
660 <&dmac2 0x35>, 584 <&dmac2 0x35>, <&dmac2 0x34>;
661 dma-names = "tx", "rx" 585 dma-names = "tx", "rx", "tx", "rx";
662 power-domains = <&sysc 586 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
663 resets = <&cpg 518>; 587 resets = <&cpg 518>;
664 status = "disabled"; 588 status = "disabled";
665 }; 589 };
666 590
667 hscif3: serial@e66a0000 { 591 hscif3: serial@e66a0000 {
668 compatible = "renesas, 592 compatible = "renesas,hscif-r8a77990",
669 "renesas, 593 "renesas,rcar-gen3-hscif",
670 "renesas, 594 "renesas,hscif";
671 reg = <0 0xe66a0000 0 595 reg = <0 0xe66a0000 0 0x60>;
672 interrupts = <GIC_SPI 596 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
673 clocks = <&cpg CPG_MOD 597 clocks = <&cpg CPG_MOD 517>,
674 <&cpg CPG_COR 598 <&cpg CPG_CORE R8A77990_CLK_S3D1C>,
675 <&scif_clk>; 599 <&scif_clk>;
676 clock-names = "fck", " 600 clock-names = "fck", "brg_int", "scif_clk";
677 dmas = <&dmac0 0x37>, 601 dmas = <&dmac0 0x37>, <&dmac0 0x36>;
678 dma-names = "tx", "rx" 602 dma-names = "tx", "rx";
679 power-domains = <&sysc 603 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
680 resets = <&cpg 517>; 604 resets = <&cpg 517>;
681 status = "disabled"; 605 status = "disabled";
682 }; 606 };
683 607
684 hscif4: serial@e66b0000 { 608 hscif4: serial@e66b0000 {
685 compatible = "renesas, 609 compatible = "renesas,hscif-r8a77990",
686 "renesas, 610 "renesas,rcar-gen3-hscif",
687 "renesas, 611 "renesas,hscif";
688 reg = <0 0xe66b0000 0 612 reg = <0 0xe66b0000 0 0x60>;
689 interrupts = <GIC_SPI 613 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
690 clocks = <&cpg CPG_MOD 614 clocks = <&cpg CPG_MOD 516>,
691 <&cpg CPG_COR 615 <&cpg CPG_CORE R8A77990_CLK_S3D1C>,
692 <&scif_clk>; 616 <&scif_clk>;
693 clock-names = "fck", " 617 clock-names = "fck", "brg_int", "scif_clk";
694 dmas = <&dmac0 0x39>, 618 dmas = <&dmac0 0x39>, <&dmac0 0x38>;
695 dma-names = "tx", "rx" 619 dma-names = "tx", "rx";
696 power-domains = <&sysc 620 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
697 resets = <&cpg 516>; 621 resets = <&cpg 516>;
698 status = "disabled"; 622 status = "disabled";
699 }; 623 };
700 624
701 hsusb: usb@e6590000 { 625 hsusb: usb@e6590000 {
702 compatible = "renesas, 626 compatible = "renesas,usbhs-r8a77990",
703 "renesas, 627 "renesas,rcar-gen3-usbhs";
704 reg = <0 0xe6590000 0 628 reg = <0 0xe6590000 0 0x200>;
705 interrupts = <GIC_SPI 629 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
706 clocks = <&cpg CPG_MOD 630 clocks = <&cpg CPG_MOD 704>, <&cpg CPG_MOD 703>;
707 dmas = <&usb_dmac0 0>, 631 dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
708 <&usb_dmac1 0>, 632 <&usb_dmac1 0>, <&usb_dmac1 1>;
709 dma-names = "ch0", "ch 633 dma-names = "ch0", "ch1", "ch2", "ch3";
710 renesas,buswait = <11> 634 renesas,buswait = <11>;
711 phys = <&usb2_phy0 3>; 635 phys = <&usb2_phy0 3>;
712 phy-names = "usb"; 636 phy-names = "usb";
713 power-domains = <&sysc 637 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
714 resets = <&cpg 704>, < 638 resets = <&cpg 704>, <&cpg 703>;
715 status = "disabled"; 639 status = "disabled";
716 }; 640 };
717 641
718 usb_dmac0: dma-controller@e65a 642 usb_dmac0: dma-controller@e65a0000 {
719 compatible = "renesas, 643 compatible = "renesas,r8a77990-usb-dmac",
720 "renesas, 644 "renesas,usb-dmac";
721 reg = <0 0xe65a0000 0 645 reg = <0 0xe65a0000 0 0x100>;
722 interrupts = <GIC_SPI !! 646 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH
723 <GIC_SPI !! 647 GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
724 interrupt-names = "ch0 648 interrupt-names = "ch0", "ch1";
725 clocks = <&cpg CPG_MOD 649 clocks = <&cpg CPG_MOD 330>;
726 power-domains = <&sysc 650 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
727 resets = <&cpg 330>; 651 resets = <&cpg 330>;
728 #dma-cells = <1>; 652 #dma-cells = <1>;
729 dma-channels = <2>; 653 dma-channels = <2>;
730 }; 654 };
731 655
732 usb_dmac1: dma-controller@e65b 656 usb_dmac1: dma-controller@e65b0000 {
733 compatible = "renesas, 657 compatible = "renesas,r8a77990-usb-dmac",
734 "renesas, 658 "renesas,usb-dmac";
735 reg = <0 0xe65b0000 0 659 reg = <0 0xe65b0000 0 0x100>;
736 interrupts = <GIC_SPI !! 660 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH
737 <GIC_SPI !! 661 GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
738 interrupt-names = "ch0 662 interrupt-names = "ch0", "ch1";
739 clocks = <&cpg CPG_MOD 663 clocks = <&cpg CPG_MOD 331>;
740 power-domains = <&sysc 664 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
741 resets = <&cpg 331>; 665 resets = <&cpg 331>;
742 #dma-cells = <1>; 666 #dma-cells = <1>;
743 dma-channels = <2>; 667 dma-channels = <2>;
744 }; 668 };
745 669
746 arm_cc630p: crypto@e6601000 { <<
747 compatible = "arm,cryp <<
748 interrupts = <GIC_SPI <<
749 reg = <0x0 0xe6601000 <<
750 clocks = <&cpg CPG_MOD <<
751 resets = <&cpg 229>; <<
752 power-domains = <&sysc <<
753 }; <<
754 <<
755 dmac0: dma-controller@e6700000 670 dmac0: dma-controller@e6700000 {
756 compatible = "renesas, 671 compatible = "renesas,dmac-r8a77990",
757 "renesas, 672 "renesas,rcar-dmac";
758 reg = <0 0xe6700000 0 673 reg = <0 0xe6700000 0 0x10000>;
759 interrupts = <GIC_SPI !! 674 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH
760 <GIC_SPI !! 675 GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
761 <GIC_SPI !! 676 GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
762 <GIC_SPI !! 677 GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
763 <GIC_SPI !! 678 GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
764 <GIC_SPI !! 679 GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
765 <GIC_SPI !! 680 GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
766 <GIC_SPI !! 681 GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
767 <GIC_SPI !! 682 GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
768 <GIC_SPI !! 683 GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
769 <GIC_SPI !! 684 GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
770 <GIC_SPI !! 685 GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
771 <GIC_SPI !! 686 GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
772 <GIC_SPI !! 687 GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
773 <GIC_SPI !! 688 GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
774 <GIC_SPI !! 689 GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH
775 <GIC_SPI !! 690 GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>;
776 interrupt-names = "err 691 interrupt-names = "error",
777 "ch0", 692 "ch0", "ch1", "ch2", "ch3",
778 "ch4", 693 "ch4", "ch5", "ch6", "ch7",
779 "ch8", 694 "ch8", "ch9", "ch10", "ch11",
780 "ch12" 695 "ch12", "ch13", "ch14", "ch15";
781 clocks = <&cpg CPG_MOD 696 clocks = <&cpg CPG_MOD 219>;
782 clock-names = "fck"; 697 clock-names = "fck";
783 power-domains = <&sysc 698 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
784 resets = <&cpg 219>; 699 resets = <&cpg 219>;
785 #dma-cells = <1>; 700 #dma-cells = <1>;
786 dma-channels = <16>; 701 dma-channels = <16>;
787 iommus = <&ipmmu_ds0 0 702 iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>,
788 <&ipmmu_ds0 2>, 703 <&ipmmu_ds0 2>, <&ipmmu_ds0 3>,
789 <&ipmmu_ds0 4>, 704 <&ipmmu_ds0 4>, <&ipmmu_ds0 5>,
790 <&ipmmu_ds0 6>, 705 <&ipmmu_ds0 6>, <&ipmmu_ds0 7>,
791 <&ipmmu_ds0 8>, 706 <&ipmmu_ds0 8>, <&ipmmu_ds0 9>,
792 <&ipmmu_ds0 10> 707 <&ipmmu_ds0 10>, <&ipmmu_ds0 11>,
793 <&ipmmu_ds0 12> 708 <&ipmmu_ds0 12>, <&ipmmu_ds0 13>,
794 <&ipmmu_ds0 14> 709 <&ipmmu_ds0 14>, <&ipmmu_ds0 15>;
795 }; 710 };
796 711
797 dmac1: dma-controller@e7300000 712 dmac1: dma-controller@e7300000 {
798 compatible = "renesas, 713 compatible = "renesas,dmac-r8a77990",
799 "renesas, 714 "renesas,rcar-dmac";
800 reg = <0 0xe7300000 0 715 reg = <0 0xe7300000 0 0x10000>;
801 interrupts = <GIC_SPI !! 716 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
802 <GIC_SPI !! 717 GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
803 <GIC_SPI !! 718 GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
804 <GIC_SPI !! 719 GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
805 <GIC_SPI !! 720 GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
806 <GIC_SPI !! 721 GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
807 <GIC_SPI !! 722 GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
808 <GIC_SPI !! 723 GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
809 <GIC_SPI !! 724 GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
810 <GIC_SPI !! 725 GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
811 <GIC_SPI !! 726 GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
812 <GIC_SPI !! 727 GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
813 <GIC_SPI !! 728 GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
814 <GIC_SPI !! 729 GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
815 <GIC_SPI !! 730 GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
816 <GIC_SPI !! 731 GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH
817 <GIC_SPI !! 732 GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>;
818 interrupt-names = "err 733 interrupt-names = "error",
819 "ch0", 734 "ch0", "ch1", "ch2", "ch3",
820 "ch4", 735 "ch4", "ch5", "ch6", "ch7",
821 "ch8", 736 "ch8", "ch9", "ch10", "ch11",
822 "ch12" 737 "ch12", "ch13", "ch14", "ch15";
823 clocks = <&cpg CPG_MOD 738 clocks = <&cpg CPG_MOD 218>;
824 clock-names = "fck"; 739 clock-names = "fck";
825 power-domains = <&sysc 740 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
826 resets = <&cpg 218>; 741 resets = <&cpg 218>;
827 #dma-cells = <1>; 742 #dma-cells = <1>;
828 dma-channels = <16>; 743 dma-channels = <16>;
829 iommus = <&ipmmu_ds1 0 744 iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>,
830 <&ipmmu_ds1 2>, 745 <&ipmmu_ds1 2>, <&ipmmu_ds1 3>,
831 <&ipmmu_ds1 4>, 746 <&ipmmu_ds1 4>, <&ipmmu_ds1 5>,
832 <&ipmmu_ds1 6>, 747 <&ipmmu_ds1 6>, <&ipmmu_ds1 7>,
833 <&ipmmu_ds1 8>, 748 <&ipmmu_ds1 8>, <&ipmmu_ds1 9>,
834 <&ipmmu_ds1 10> 749 <&ipmmu_ds1 10>, <&ipmmu_ds1 11>,
835 <&ipmmu_ds1 12> 750 <&ipmmu_ds1 12>, <&ipmmu_ds1 13>,
836 <&ipmmu_ds1 14> 751 <&ipmmu_ds1 14>, <&ipmmu_ds1 15>;
837 }; 752 };
838 753
839 dmac2: dma-controller@e7310000 754 dmac2: dma-controller@e7310000 {
840 compatible = "renesas, 755 compatible = "renesas,dmac-r8a77990",
841 "renesas, 756 "renesas,rcar-dmac";
842 reg = <0 0xe7310000 0 757 reg = <0 0xe7310000 0 0x10000>;
843 interrupts = <GIC_SPI !! 758 interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH
844 <GIC_SPI !! 759 GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH
845 <GIC_SPI !! 760 GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH
846 <GIC_SPI !! 761 GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH
847 <GIC_SPI !! 762 GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH
848 <GIC_SPI !! 763 GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH
849 <GIC_SPI !! 764 GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH
850 <GIC_SPI !! 765 GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH
851 <GIC_SPI !! 766 GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH
852 <GIC_SPI !! 767 GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH
853 <GIC_SPI !! 768 GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH
854 <GIC_SPI !! 769 GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH
855 <GIC_SPI !! 770 GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH
856 <GIC_SPI !! 771 GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH
857 <GIC_SPI !! 772 GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH
858 <GIC_SPI !! 773 GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH
859 <GIC_SPI !! 774 GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>;
860 interrupt-names = "err 775 interrupt-names = "error",
861 "ch0", 776 "ch0", "ch1", "ch2", "ch3",
862 "ch4", 777 "ch4", "ch5", "ch6", "ch7",
863 "ch8", 778 "ch8", "ch9", "ch10", "ch11",
864 "ch12" 779 "ch12", "ch13", "ch14", "ch15";
865 clocks = <&cpg CPG_MOD 780 clocks = <&cpg CPG_MOD 217>;
866 clock-names = "fck"; 781 clock-names = "fck";
867 power-domains = <&sysc 782 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
868 resets = <&cpg 217>; 783 resets = <&cpg 217>;
869 #dma-cells = <1>; 784 #dma-cells = <1>;
870 dma-channels = <16>; 785 dma-channels = <16>;
871 iommus = <&ipmmu_ds1 1 786 iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>,
872 <&ipmmu_ds1 18> 787 <&ipmmu_ds1 18>, <&ipmmu_ds1 19>,
873 <&ipmmu_ds1 20> 788 <&ipmmu_ds1 20>, <&ipmmu_ds1 21>,
874 <&ipmmu_ds1 22> 789 <&ipmmu_ds1 22>, <&ipmmu_ds1 23>,
875 <&ipmmu_ds1 24> 790 <&ipmmu_ds1 24>, <&ipmmu_ds1 25>,
876 <&ipmmu_ds1 26> 791 <&ipmmu_ds1 26>, <&ipmmu_ds1 27>,
877 <&ipmmu_ds1 28> 792 <&ipmmu_ds1 28>, <&ipmmu_ds1 29>,
878 <&ipmmu_ds1 30> 793 <&ipmmu_ds1 30>, <&ipmmu_ds1 31>;
879 }; 794 };
880 795
881 ipmmu_ds0: iommu@e6740000 { !! 796 ipmmu_ds0: mmu@e6740000 {
882 compatible = "renesas, 797 compatible = "renesas,ipmmu-r8a77990";
883 reg = <0 0xe6740000 0 798 reg = <0 0xe6740000 0 0x1000>;
884 renesas,ipmmu-main = < 799 renesas,ipmmu-main = <&ipmmu_mm 0>;
885 power-domains = <&sysc 800 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
886 #iommu-cells = <1>; 801 #iommu-cells = <1>;
887 }; 802 };
888 803
889 ipmmu_ds1: iommu@e7740000 { !! 804 ipmmu_ds1: mmu@e7740000 {
890 compatible = "renesas, 805 compatible = "renesas,ipmmu-r8a77990";
891 reg = <0 0xe7740000 0 806 reg = <0 0xe7740000 0 0x1000>;
892 renesas,ipmmu-main = < 807 renesas,ipmmu-main = <&ipmmu_mm 1>;
893 power-domains = <&sysc 808 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
894 #iommu-cells = <1>; 809 #iommu-cells = <1>;
895 }; 810 };
896 811
897 ipmmu_hc: iommu@e6570000 { !! 812 ipmmu_hc: mmu@e6570000 {
898 compatible = "renesas, 813 compatible = "renesas,ipmmu-r8a77990";
899 reg = <0 0xe6570000 0 814 reg = <0 0xe6570000 0 0x1000>;
900 renesas,ipmmu-main = < 815 renesas,ipmmu-main = <&ipmmu_mm 2>;
901 power-domains = <&sysc 816 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
902 #iommu-cells = <1>; 817 #iommu-cells = <1>;
903 }; 818 };
904 819
905 ipmmu_mm: iommu@e67b0000 { !! 820 ipmmu_mm: mmu@e67b0000 {
906 compatible = "renesas, 821 compatible = "renesas,ipmmu-r8a77990";
907 reg = <0 0xe67b0000 0 822 reg = <0 0xe67b0000 0 0x1000>;
908 interrupts = <GIC_SPI 823 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
909 <GIC_SPI 824 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
910 power-domains = <&sysc 825 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
911 #iommu-cells = <1>; 826 #iommu-cells = <1>;
912 }; 827 };
913 828
914 ipmmu_mp: iommu@ec670000 { !! 829 ipmmu_mp: mmu@ec670000 {
915 compatible = "renesas, 830 compatible = "renesas,ipmmu-r8a77990";
916 reg = <0 0xec670000 0 831 reg = <0 0xec670000 0 0x1000>;
917 renesas,ipmmu-main = < 832 renesas,ipmmu-main = <&ipmmu_mm 4>;
918 power-domains = <&sysc 833 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
919 #iommu-cells = <1>; 834 #iommu-cells = <1>;
920 }; 835 };
921 836
922 ipmmu_pv0: iommu@fd800000 { !! 837 ipmmu_pv0: mmu@fd800000 {
923 compatible = "renesas, 838 compatible = "renesas,ipmmu-r8a77990";
924 reg = <0 0xfd800000 0 839 reg = <0 0xfd800000 0 0x1000>;
925 renesas,ipmmu-main = < 840 renesas,ipmmu-main = <&ipmmu_mm 6>;
926 power-domains = <&sysc 841 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
927 #iommu-cells = <1>; 842 #iommu-cells = <1>;
928 }; 843 };
929 844
930 ipmmu_rt: iommu@ffc80000 { !! 845 ipmmu_rt: mmu@ffc80000 {
931 compatible = "renesas, 846 compatible = "renesas,ipmmu-r8a77990";
932 reg = <0 0xffc80000 0 847 reg = <0 0xffc80000 0 0x1000>;
933 renesas,ipmmu-main = < 848 renesas,ipmmu-main = <&ipmmu_mm 10>;
934 power-domains = <&sysc 849 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
935 #iommu-cells = <1>; 850 #iommu-cells = <1>;
936 }; 851 };
937 852
938 ipmmu_vc0: iommu@fe6b0000 { !! 853 ipmmu_vc0: mmu@fe6b0000 {
939 compatible = "renesas, 854 compatible = "renesas,ipmmu-r8a77990";
940 reg = <0 0xfe6b0000 0 855 reg = <0 0xfe6b0000 0 0x1000>;
941 renesas,ipmmu-main = < 856 renesas,ipmmu-main = <&ipmmu_mm 12>;
942 power-domains = <&sysc 857 power-domains = <&sysc R8A77990_PD_A3VC>;
943 #iommu-cells = <1>; 858 #iommu-cells = <1>;
944 }; 859 };
945 860
946 ipmmu_vi0: iommu@febd0000 { !! 861 ipmmu_vi0: mmu@febd0000 {
947 compatible = "renesas, 862 compatible = "renesas,ipmmu-r8a77990";
948 reg = <0 0xfebd0000 0 863 reg = <0 0xfebd0000 0 0x1000>;
949 renesas,ipmmu-main = < 864 renesas,ipmmu-main = <&ipmmu_mm 14>;
950 power-domains = <&sysc 865 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
951 #iommu-cells = <1>; 866 #iommu-cells = <1>;
952 }; 867 };
953 868
954 ipmmu_vp0: iommu@fe990000 { !! 869 ipmmu_vp0: mmu@fe990000 {
955 compatible = "renesas, 870 compatible = "renesas,ipmmu-r8a77990";
956 reg = <0 0xfe990000 0 871 reg = <0 0xfe990000 0 0x1000>;
957 renesas,ipmmu-main = < 872 renesas,ipmmu-main = <&ipmmu_mm 16>;
958 power-domains = <&sysc 873 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
959 #iommu-cells = <1>; 874 #iommu-cells = <1>;
960 }; 875 };
961 876
962 avb: ethernet@e6800000 { 877 avb: ethernet@e6800000 {
963 compatible = "renesas, 878 compatible = "renesas,etheravb-r8a77990",
964 "renesas, 879 "renesas,etheravb-rcar-gen3";
965 reg = <0 0xe6800000 0 880 reg = <0 0xe6800000 0 0x800>;
966 interrupts = <GIC_SPI 881 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
967 <GIC_SPI 882 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
968 <GIC_SPI 883 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
969 <GIC_SPI 884 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
970 <GIC_SPI 885 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
971 <GIC_SPI 886 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
972 <GIC_SPI 887 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
973 <GIC_SPI 888 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
974 <GIC_SPI 889 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
975 <GIC_SPI 890 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
976 <GIC_SPI 891 <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
977 <GIC_SPI 892 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
978 <GIC_SPI 893 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
979 <GIC_SPI 894 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
980 <GIC_SPI 895 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
981 <GIC_SPI 896 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
982 <GIC_SPI 897 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
983 <GIC_SPI 898 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
984 <GIC_SPI 899 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
985 <GIC_SPI 900 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
986 <GIC_SPI 901 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
987 <GIC_SPI 902 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
988 <GIC_SPI 903 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
989 <GIC_SPI 904 <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
990 <GIC_SPI 905 <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
991 interrupt-names = "ch0 906 interrupt-names = "ch0", "ch1", "ch2", "ch3",
992 "ch4 907 "ch4", "ch5", "ch6", "ch7",
993 "ch8 908 "ch8", "ch9", "ch10", "ch11",
994 "ch1 909 "ch12", "ch13", "ch14", "ch15",
995 "ch1 910 "ch16", "ch17", "ch18", "ch19",
996 "ch2 911 "ch20", "ch21", "ch22", "ch23",
997 "ch2 912 "ch24";
998 clocks = <&cpg CPG_MOD 913 clocks = <&cpg CPG_MOD 812>;
999 clock-names = "fck"; <<
1000 power-domains = <&sys 914 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1001 resets = <&cpg 812>; 915 resets = <&cpg 812>;
1002 phy-mode = "rgmii"; 916 phy-mode = "rgmii";
1003 rx-internal-delay-ps <<
1004 iommus = <&ipmmu_ds0 917 iommus = <&ipmmu_ds0 16>;
1005 #address-cells = <1>; 918 #address-cells = <1>;
1006 #size-cells = <0>; 919 #size-cells = <0>;
1007 status = "disabled"; 920 status = "disabled";
1008 }; 921 };
1009 922
1010 can0: can@e6c30000 { 923 can0: can@e6c30000 {
1011 compatible = "renesas 924 compatible = "renesas,can-r8a77990",
1012 "renesas 925 "renesas,rcar-gen3-can";
1013 reg = <0 0xe6c30000 0 926 reg = <0 0xe6c30000 0 0x1000>;
1014 interrupts = <GIC_SPI 927 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
1015 clocks = <&cpg CPG_MO 928 clocks = <&cpg CPG_MOD 916>,
1016 <&cpg CPG_CORE 929 <&cpg CPG_CORE R8A77990_CLK_CANFD>,
1017 <&can_clk>; 930 <&can_clk>;
1018 clock-names = "clkp1" 931 clock-names = "clkp1", "clkp2", "can_clk";
1019 assigned-clocks = <&c 932 assigned-clocks = <&cpg CPG_CORE R8A77990_CLK_CANFD>;
1020 assigned-clock-rates 933 assigned-clock-rates = <40000000>;
1021 power-domains = <&sys 934 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1022 resets = <&cpg 916>; 935 resets = <&cpg 916>;
1023 status = "disabled"; 936 status = "disabled";
1024 }; 937 };
1025 938
1026 can1: can@e6c38000 { 939 can1: can@e6c38000 {
1027 compatible = "renesas 940 compatible = "renesas,can-r8a77990",
1028 "renesas 941 "renesas,rcar-gen3-can";
1029 reg = <0 0xe6c38000 0 942 reg = <0 0xe6c38000 0 0x1000>;
1030 interrupts = <GIC_SPI 943 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
1031 clocks = <&cpg CPG_MO 944 clocks = <&cpg CPG_MOD 915>,
1032 <&cpg CPG_CORE 945 <&cpg CPG_CORE R8A77990_CLK_CANFD>,
1033 <&can_clk>; 946 <&can_clk>;
1034 clock-names = "clkp1" 947 clock-names = "clkp1", "clkp2", "can_clk";
1035 assigned-clocks = <&c 948 assigned-clocks = <&cpg CPG_CORE R8A77990_CLK_CANFD>;
1036 assigned-clock-rates 949 assigned-clock-rates = <40000000>;
1037 power-domains = <&sys 950 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1038 resets = <&cpg 915>; 951 resets = <&cpg 915>;
1039 status = "disabled"; 952 status = "disabled";
1040 }; 953 };
1041 954
1042 canfd: can@e66c0000 { 955 canfd: can@e66c0000 {
1043 compatible = "renesas 956 compatible = "renesas,r8a77990-canfd",
1044 "renesas 957 "renesas,rcar-gen3-canfd";
1045 reg = <0 0xe66c0000 0 958 reg = <0 0xe66c0000 0 0x8000>;
1046 interrupts = <GIC_SPI 959 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
1047 <GIC_SPI 3 960 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
1048 interrupt-names = "ch <<
1049 clocks = <&cpg CPG_MO 961 clocks = <&cpg CPG_MOD 914>,
1050 <&cpg CPG_CORE 962 <&cpg CPG_CORE R8A77990_CLK_CANFD>,
1051 <&can_clk>; 963 <&can_clk>;
1052 clock-names = "fck", 964 clock-names = "fck", "canfd", "can_clk";
1053 assigned-clocks = <&c 965 assigned-clocks = <&cpg CPG_CORE R8A77990_CLK_CANFD>;
1054 assigned-clock-rates 966 assigned-clock-rates = <40000000>;
1055 power-domains = <&sys 967 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1056 resets = <&cpg 914>; 968 resets = <&cpg 914>;
1057 status = "disabled"; 969 status = "disabled";
1058 970
1059 channel0 { 971 channel0 {
1060 status = "dis 972 status = "disabled";
1061 }; 973 };
1062 974
1063 channel1 { 975 channel1 {
1064 status = "dis 976 status = "disabled";
1065 }; 977 };
1066 }; 978 };
1067 979
1068 pwm0: pwm@e6e30000 { 980 pwm0: pwm@e6e30000 {
1069 compatible = "renesas 981 compatible = "renesas,pwm-r8a77990", "renesas,pwm-rcar";
1070 reg = <0 0xe6e30000 0 982 reg = <0 0xe6e30000 0 0x8>;
1071 clocks = <&cpg CPG_MO 983 clocks = <&cpg CPG_MOD 523>;
1072 power-domains = <&sys 984 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1073 resets = <&cpg 523>; 985 resets = <&cpg 523>;
1074 #pwm-cells = <2>; 986 #pwm-cells = <2>;
1075 status = "disabled"; 987 status = "disabled";
1076 }; 988 };
1077 989
1078 pwm1: pwm@e6e31000 { 990 pwm1: pwm@e6e31000 {
1079 compatible = "renesas 991 compatible = "renesas,pwm-r8a77990", "renesas,pwm-rcar";
1080 reg = <0 0xe6e31000 0 992 reg = <0 0xe6e31000 0 0x8>;
1081 clocks = <&cpg CPG_MO 993 clocks = <&cpg CPG_MOD 523>;
1082 power-domains = <&sys 994 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1083 resets = <&cpg 523>; 995 resets = <&cpg 523>;
1084 #pwm-cells = <2>; 996 #pwm-cells = <2>;
1085 status = "disabled"; 997 status = "disabled";
1086 }; 998 };
1087 999
1088 pwm2: pwm@e6e32000 { 1000 pwm2: pwm@e6e32000 {
1089 compatible = "renesas 1001 compatible = "renesas,pwm-r8a77990", "renesas,pwm-rcar";
1090 reg = <0 0xe6e32000 0 1002 reg = <0 0xe6e32000 0 0x8>;
1091 clocks = <&cpg CPG_MO 1003 clocks = <&cpg CPG_MOD 523>;
1092 power-domains = <&sys 1004 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1093 resets = <&cpg 523>; 1005 resets = <&cpg 523>;
1094 #pwm-cells = <2>; 1006 #pwm-cells = <2>;
1095 status = "disabled"; 1007 status = "disabled";
1096 }; 1008 };
1097 1009
1098 pwm3: pwm@e6e33000 { 1010 pwm3: pwm@e6e33000 {
1099 compatible = "renesas 1011 compatible = "renesas,pwm-r8a77990", "renesas,pwm-rcar";
1100 reg = <0 0xe6e33000 0 1012 reg = <0 0xe6e33000 0 0x8>;
1101 clocks = <&cpg CPG_MO 1013 clocks = <&cpg CPG_MOD 523>;
1102 power-domains = <&sys 1014 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1103 resets = <&cpg 523>; 1015 resets = <&cpg 523>;
1104 #pwm-cells = <2>; 1016 #pwm-cells = <2>;
1105 status = "disabled"; 1017 status = "disabled";
1106 }; 1018 };
1107 1019
1108 pwm4: pwm@e6e34000 { 1020 pwm4: pwm@e6e34000 {
1109 compatible = "renesas 1021 compatible = "renesas,pwm-r8a77990", "renesas,pwm-rcar";
1110 reg = <0 0xe6e34000 0 1022 reg = <0 0xe6e34000 0 0x8>;
1111 clocks = <&cpg CPG_MO 1023 clocks = <&cpg CPG_MOD 523>;
1112 power-domains = <&sys 1024 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1113 resets = <&cpg 523>; 1025 resets = <&cpg 523>;
1114 #pwm-cells = <2>; 1026 #pwm-cells = <2>;
1115 status = "disabled"; 1027 status = "disabled";
1116 }; 1028 };
1117 1029
1118 pwm5: pwm@e6e35000 { 1030 pwm5: pwm@e6e35000 {
1119 compatible = "renesas 1031 compatible = "renesas,pwm-r8a77990", "renesas,pwm-rcar";
1120 reg = <0 0xe6e35000 0 1032 reg = <0 0xe6e35000 0 0x8>;
1121 clocks = <&cpg CPG_MO 1033 clocks = <&cpg CPG_MOD 523>;
1122 power-domains = <&sys 1034 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1123 resets = <&cpg 523>; 1035 resets = <&cpg 523>;
1124 #pwm-cells = <2>; 1036 #pwm-cells = <2>;
1125 status = "disabled"; 1037 status = "disabled";
1126 }; 1038 };
1127 1039
1128 pwm6: pwm@e6e36000 { 1040 pwm6: pwm@e6e36000 {
1129 compatible = "renesas 1041 compatible = "renesas,pwm-r8a77990", "renesas,pwm-rcar";
1130 reg = <0 0xe6e36000 0 1042 reg = <0 0xe6e36000 0 0x8>;
1131 clocks = <&cpg CPG_MO 1043 clocks = <&cpg CPG_MOD 523>;
1132 power-domains = <&sys 1044 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1133 resets = <&cpg 523>; 1045 resets = <&cpg 523>;
1134 #pwm-cells = <2>; 1046 #pwm-cells = <2>;
1135 status = "disabled"; 1047 status = "disabled";
1136 }; 1048 };
1137 1049
1138 scif0: serial@e6e60000 { 1050 scif0: serial@e6e60000 {
1139 compatible = "renesas 1051 compatible = "renesas,scif-r8a77990",
1140 "renesas 1052 "renesas,rcar-gen3-scif", "renesas,scif";
1141 reg = <0 0xe6e60000 0 1053 reg = <0 0xe6e60000 0 64>;
1142 interrupts = <GIC_SPI 1054 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
1143 clocks = <&cpg CPG_MO 1055 clocks = <&cpg CPG_MOD 207>,
1144 <&cpg CPG_CO 1056 <&cpg CPG_CORE R8A77990_CLK_S3D1C>,
1145 <&scif_clk>; 1057 <&scif_clk>;
1146 clock-names = "fck", 1058 clock-names = "fck", "brg_int", "scif_clk";
1147 dmas = <&dmac1 0x51>, 1059 dmas = <&dmac1 0x51>, <&dmac1 0x50>,
1148 <&dmac2 0x51>, 1060 <&dmac2 0x51>, <&dmac2 0x50>;
1149 dma-names = "tx", "rx 1061 dma-names = "tx", "rx", "tx", "rx";
1150 power-domains = <&sys 1062 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1151 resets = <&cpg 207>; 1063 resets = <&cpg 207>;
1152 status = "disabled"; 1064 status = "disabled";
1153 }; 1065 };
1154 1066
1155 scif1: serial@e6e68000 { 1067 scif1: serial@e6e68000 {
1156 compatible = "renesas 1068 compatible = "renesas,scif-r8a77990",
1157 "renesas 1069 "renesas,rcar-gen3-scif", "renesas,scif";
1158 reg = <0 0xe6e68000 0 1070 reg = <0 0xe6e68000 0 64>;
1159 interrupts = <GIC_SPI 1071 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
1160 clocks = <&cpg CPG_MO 1072 clocks = <&cpg CPG_MOD 206>,
1161 <&cpg CPG_CO 1073 <&cpg CPG_CORE R8A77990_CLK_S3D1C>,
1162 <&scif_clk>; 1074 <&scif_clk>;
1163 clock-names = "fck", 1075 clock-names = "fck", "brg_int", "scif_clk";
1164 dmas = <&dmac1 0x53>, 1076 dmas = <&dmac1 0x53>, <&dmac1 0x52>,
1165 <&dmac2 0x53>, 1077 <&dmac2 0x53>, <&dmac2 0x52>;
1166 dma-names = "tx", "rx 1078 dma-names = "tx", "rx", "tx", "rx";
1167 power-domains = <&sys 1079 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1168 resets = <&cpg 206>; 1080 resets = <&cpg 206>;
1169 status = "disabled"; 1081 status = "disabled";
1170 }; 1082 };
1171 1083
1172 scif2: serial@e6e88000 { 1084 scif2: serial@e6e88000 {
1173 compatible = "renesas 1085 compatible = "renesas,scif-r8a77990",
1174 "renesas 1086 "renesas,rcar-gen3-scif", "renesas,scif";
1175 reg = <0 0xe6e88000 0 1087 reg = <0 0xe6e88000 0 64>;
1176 interrupts = <GIC_SPI 1088 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
1177 clocks = <&cpg CPG_MO 1089 clocks = <&cpg CPG_MOD 310>,
1178 <&cpg CPG_CO 1090 <&cpg CPG_CORE R8A77990_CLK_S3D1C>,
1179 <&scif_clk>; 1091 <&scif_clk>;
1180 clock-names = "fck", 1092 clock-names = "fck", "brg_int", "scif_clk";
1181 dmas = <&dmac1 0x13>, 1093 dmas = <&dmac1 0x13>, <&dmac1 0x12>,
1182 <&dmac2 0x13>, 1094 <&dmac2 0x13>, <&dmac2 0x12>;
1183 dma-names = "tx", "rx 1095 dma-names = "tx", "rx", "tx", "rx";
1184 power-domains = <&sys 1096 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1185 resets = <&cpg 310>; 1097 resets = <&cpg 310>;
1186 status = "disabled"; 1098 status = "disabled";
1187 }; 1099 };
1188 1100
1189 scif3: serial@e6c50000 { 1101 scif3: serial@e6c50000 {
1190 compatible = "renesas 1102 compatible = "renesas,scif-r8a77990",
1191 "renesas 1103 "renesas,rcar-gen3-scif", "renesas,scif";
1192 reg = <0 0xe6c50000 0 1104 reg = <0 0xe6c50000 0 64>;
1193 interrupts = <GIC_SPI 1105 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
1194 clocks = <&cpg CPG_MO 1106 clocks = <&cpg CPG_MOD 204>,
1195 <&cpg CPG_CO 1107 <&cpg CPG_CORE R8A77990_CLK_S3D1C>,
1196 <&scif_clk>; 1108 <&scif_clk>;
1197 clock-names = "fck", 1109 clock-names = "fck", "brg_int", "scif_clk";
1198 dmas = <&dmac0 0x57>, 1110 dmas = <&dmac0 0x57>, <&dmac0 0x56>;
1199 dma-names = "tx", "rx 1111 dma-names = "tx", "rx";
1200 power-domains = <&sys 1112 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1201 resets = <&cpg 204>; 1113 resets = <&cpg 204>;
1202 status = "disabled"; 1114 status = "disabled";
1203 }; 1115 };
1204 1116
1205 scif4: serial@e6c40000 { 1117 scif4: serial@e6c40000 {
1206 compatible = "renesas 1118 compatible = "renesas,scif-r8a77990",
1207 "renesas 1119 "renesas,rcar-gen3-scif", "renesas,scif";
1208 reg = <0 0xe6c40000 0 1120 reg = <0 0xe6c40000 0 64>;
1209 interrupts = <GIC_SPI 1121 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1210 clocks = <&cpg CPG_MO 1122 clocks = <&cpg CPG_MOD 203>,
1211 <&cpg CPG_CO 1123 <&cpg CPG_CORE R8A77990_CLK_S3D1C>,
1212 <&scif_clk>; 1124 <&scif_clk>;
1213 clock-names = "fck", 1125 clock-names = "fck", "brg_int", "scif_clk";
1214 dmas = <&dmac0 0x59>, 1126 dmas = <&dmac0 0x59>, <&dmac0 0x58>;
1215 dma-names = "tx", "rx 1127 dma-names = "tx", "rx";
1216 power-domains = <&sys 1128 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1217 resets = <&cpg 203>; 1129 resets = <&cpg 203>;
1218 status = "disabled"; 1130 status = "disabled";
1219 }; 1131 };
1220 1132
1221 scif5: serial@e6f30000 { 1133 scif5: serial@e6f30000 {
1222 compatible = "renesas 1134 compatible = "renesas,scif-r8a77990",
1223 "renesas 1135 "renesas,rcar-gen3-scif", "renesas,scif";
1224 reg = <0 0xe6f30000 0 1136 reg = <0 0xe6f30000 0 64>;
1225 interrupts = <GIC_SPI 1137 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1226 clocks = <&cpg CPG_MO 1138 clocks = <&cpg CPG_MOD 202>,
1227 <&cpg CPG_CO 1139 <&cpg CPG_CORE R8A77990_CLK_S3D1C>,
1228 <&scif_clk>; 1140 <&scif_clk>;
1229 clock-names = "fck", 1141 clock-names = "fck", "brg_int", "scif_clk";
1230 dmas = <&dmac0 0x5b>, 1142 dmas = <&dmac0 0x5b>, <&dmac0 0x5a>;
1231 dma-names = "tx", "rx 1143 dma-names = "tx", "rx";
1232 power-domains = <&sys 1144 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1233 resets = <&cpg 202>; 1145 resets = <&cpg 202>;
1234 status = "disabled"; 1146 status = "disabled";
1235 }; 1147 };
1236 1148
1237 msiof0: spi@e6e90000 { 1149 msiof0: spi@e6e90000 {
1238 compatible = "renesas 1150 compatible = "renesas,msiof-r8a77990",
1239 "renesas 1151 "renesas,rcar-gen3-msiof";
1240 reg = <0 0xe6e90000 0 1152 reg = <0 0xe6e90000 0 0x0064>;
1241 interrupts = <GIC_SPI 1153 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
1242 clocks = <&cpg CPG_MO 1154 clocks = <&cpg CPG_MOD 211>;
1243 dmas = <&dmac1 0x41>, 1155 dmas = <&dmac1 0x41>, <&dmac1 0x40>,
1244 <&dmac2 0x41>, 1156 <&dmac2 0x41>, <&dmac2 0x40>;
1245 dma-names = "tx", "rx 1157 dma-names = "tx", "rx", "tx", "rx";
1246 power-domains = <&sys 1158 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1247 resets = <&cpg 211>; 1159 resets = <&cpg 211>;
1248 #address-cells = <1>; 1160 #address-cells = <1>;
1249 #size-cells = <0>; 1161 #size-cells = <0>;
1250 status = "disabled"; 1162 status = "disabled";
1251 }; 1163 };
1252 1164
1253 msiof1: spi@e6ea0000 { 1165 msiof1: spi@e6ea0000 {
1254 compatible = "renesas 1166 compatible = "renesas,msiof-r8a77990",
1255 "renesas 1167 "renesas,rcar-gen3-msiof";
1256 reg = <0 0xe6ea0000 0 1168 reg = <0 0xe6ea0000 0 0x0064>;
1257 interrupts = <GIC_SPI 1169 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
1258 clocks = <&cpg CPG_MO 1170 clocks = <&cpg CPG_MOD 210>;
1259 dmas = <&dmac0 0x43>, !! 1171 dmas = <&dmac1 0x43>, <&dmac1 0x42>,
1260 dma-names = "tx", "rx !! 1172 <&dmac2 0x43>, <&dmac2 0x42>;
>> 1173 dma-names = "tx", "rx", "tx", "rx";
1261 power-domains = <&sys 1174 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1262 resets = <&cpg 210>; 1175 resets = <&cpg 210>;
1263 #address-cells = <1>; 1176 #address-cells = <1>;
1264 #size-cells = <0>; 1177 #size-cells = <0>;
1265 status = "disabled"; 1178 status = "disabled";
1266 }; 1179 };
1267 1180
1268 msiof2: spi@e6c00000 { 1181 msiof2: spi@e6c00000 {
1269 compatible = "renesas 1182 compatible = "renesas,msiof-r8a77990",
1270 "renesas 1183 "renesas,rcar-gen3-msiof";
1271 reg = <0 0xe6c00000 0 1184 reg = <0 0xe6c00000 0 0x0064>;
1272 interrupts = <GIC_SPI 1185 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
1273 clocks = <&cpg CPG_MO 1186 clocks = <&cpg CPG_MOD 209>;
1274 dmas = <&dmac0 0x45>, 1187 dmas = <&dmac0 0x45>, <&dmac0 0x44>;
1275 dma-names = "tx", "rx 1188 dma-names = "tx", "rx";
1276 power-domains = <&sys 1189 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1277 resets = <&cpg 209>; 1190 resets = <&cpg 209>;
1278 #address-cells = <1>; 1191 #address-cells = <1>;
1279 #size-cells = <0>; 1192 #size-cells = <0>;
1280 status = "disabled"; 1193 status = "disabled";
1281 }; 1194 };
1282 1195
1283 msiof3: spi@e6c10000 { 1196 msiof3: spi@e6c10000 {
1284 compatible = "renesas 1197 compatible = "renesas,msiof-r8a77990",
1285 "renesas 1198 "renesas,rcar-gen3-msiof";
1286 reg = <0 0xe6c10000 0 1199 reg = <0 0xe6c10000 0 0x0064>;
1287 interrupts = <GIC_SPI 1200 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
1288 clocks = <&cpg CPG_MO 1201 clocks = <&cpg CPG_MOD 208>;
1289 dmas = <&dmac0 0x47>, 1202 dmas = <&dmac0 0x47>, <&dmac0 0x46>;
1290 dma-names = "tx", "rx 1203 dma-names = "tx", "rx";
1291 power-domains = <&sys 1204 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1292 resets = <&cpg 208>; 1205 resets = <&cpg 208>;
1293 #address-cells = <1>; 1206 #address-cells = <1>;
1294 #size-cells = <0>; 1207 #size-cells = <0>;
1295 status = "disabled"; 1208 status = "disabled";
1296 }; 1209 };
1297 1210
1298 vin4: video@e6ef4000 { 1211 vin4: video@e6ef4000 {
1299 compatible = "renesas 1212 compatible = "renesas,vin-r8a77990";
1300 reg = <0 0xe6ef4000 0 1213 reg = <0 0xe6ef4000 0 0x1000>;
1301 interrupts = <GIC_SPI 1214 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
1302 clocks = <&cpg CPG_MO 1215 clocks = <&cpg CPG_MOD 807>;
1303 power-domains = <&sys 1216 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1304 resets = <&cpg 807>; 1217 resets = <&cpg 807>;
1305 renesas,id = <4>; 1218 renesas,id = <4>;
1306 status = "disabled"; 1219 status = "disabled";
1307 1220
1308 ports { 1221 ports {
1309 #address-cell 1222 #address-cells = <1>;
1310 #size-cells = 1223 #size-cells = <0>;
1311 1224
1312 port@1 { 1225 port@1 {
1313 #addr 1226 #address-cells = <1>;
1314 #size 1227 #size-cells = <0>;
1315 1228
1316 reg = 1229 reg = <1>;
1317 1230
1318 vin4c 1231 vin4csi40: endpoint@2 {
1319 1232 reg = <2>;
1320 !! 1233 remote-endpoint= <&csi40vin4>;
1321 }; 1234 };
1322 }; 1235 };
1323 }; 1236 };
1324 }; 1237 };
1325 1238
1326 vin5: video@e6ef5000 { 1239 vin5: video@e6ef5000 {
1327 compatible = "renesas 1240 compatible = "renesas,vin-r8a77990";
1328 reg = <0 0xe6ef5000 0 1241 reg = <0 0xe6ef5000 0 0x1000>;
1329 interrupts = <GIC_SPI 1242 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
1330 clocks = <&cpg CPG_MO 1243 clocks = <&cpg CPG_MOD 806>;
1331 power-domains = <&sys 1244 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1332 resets = <&cpg 806>; 1245 resets = <&cpg 806>;
1333 renesas,id = <5>; 1246 renesas,id = <5>;
1334 status = "disabled"; 1247 status = "disabled";
1335 1248
1336 ports { 1249 ports {
1337 #address-cell 1250 #address-cells = <1>;
1338 #size-cells = 1251 #size-cells = <0>;
1339 1252
1340 port@1 { 1253 port@1 {
1341 #addr 1254 #address-cells = <1>;
1342 #size 1255 #size-cells = <0>;
1343 1256
1344 reg = 1257 reg = <1>;
1345 1258
1346 vin5c 1259 vin5csi40: endpoint@2 {
1347 1260 reg = <2>;
1348 !! 1261 remote-endpoint= <&csi40vin5>;
1349 }; 1262 };
1350 }; 1263 };
1351 }; 1264 };
1352 }; 1265 };
1353 1266
1354 drif00: rif@e6f40000 { <<
1355 compatible = "renesas <<
1356 "renesas <<
1357 reg = <0 0xe6f40000 0 <<
1358 interrupts = <GIC_SPI <<
1359 clocks = <&cpg CPG_MO <<
1360 clock-names = "fck"; <<
1361 dmas = <&dmac1 0x20>, <<
1362 dma-names = "rx", "rx <<
1363 power-domains = <&sys <<
1364 resets = <&cpg 515>; <<
1365 renesas,bonding = <&d <<
1366 status = "disabled"; <<
1367 }; <<
1368 <<
1369 drif01: rif@e6f50000 { <<
1370 compatible = "renesas <<
1371 "renesas <<
1372 reg = <0 0xe6f50000 0 <<
1373 interrupts = <GIC_SPI <<
1374 clocks = <&cpg CPG_MO <<
1375 clock-names = "fck"; <<
1376 dmas = <&dmac1 0x22>, <<
1377 dma-names = "rx", "rx <<
1378 power-domains = <&sys <<
1379 resets = <&cpg 514>; <<
1380 renesas,bonding = <&d <<
1381 status = "disabled"; <<
1382 }; <<
1383 <<
1384 drif10: rif@e6f60000 { <<
1385 compatible = "renesas <<
1386 "renesas <<
1387 reg = <0 0xe6f60000 0 <<
1388 interrupts = <GIC_SPI <<
1389 clocks = <&cpg CPG_MO <<
1390 clock-names = "fck"; <<
1391 dmas = <&dmac1 0x24>, <<
1392 dma-names = "rx", "rx <<
1393 power-domains = <&sys <<
1394 resets = <&cpg 513>; <<
1395 renesas,bonding = <&d <<
1396 status = "disabled"; <<
1397 }; <<
1398 <<
1399 drif11: rif@e6f70000 { <<
1400 compatible = "renesas <<
1401 "renesas <<
1402 reg = <0 0xe6f70000 0 <<
1403 interrupts = <GIC_SPI <<
1404 clocks = <&cpg CPG_MO <<
1405 clock-names = "fck"; <<
1406 dmas = <&dmac1 0x26>, <<
1407 dma-names = "rx", "rx <<
1408 power-domains = <&sys <<
1409 resets = <&cpg 512>; <<
1410 renesas,bonding = <&d <<
1411 status = "disabled"; <<
1412 }; <<
1413 <<
1414 drif20: rif@e6f80000 { <<
1415 compatible = "renesas <<
1416 "renesas <<
1417 reg = <0 0xe6f80000 0 <<
1418 interrupts = <GIC_SPI <<
1419 clocks = <&cpg CPG_MO <<
1420 clock-names = "fck"; <<
1421 dmas = <&dmac0 0x28>; <<
1422 dma-names = "rx"; <<
1423 power-domains = <&sys <<
1424 resets = <&cpg 511>; <<
1425 renesas,bonding = <&d <<
1426 status = "disabled"; <<
1427 }; <<
1428 <<
1429 drif21: rif@e6f90000 { <<
1430 compatible = "renesas <<
1431 "renesas <<
1432 reg = <0 0xe6f90000 0 <<
1433 interrupts = <GIC_SPI <<
1434 clocks = <&cpg CPG_MO <<
1435 clock-names = "fck"; <<
1436 dmas = <&dmac0 0x2a>; <<
1437 dma-names = "rx"; <<
1438 power-domains = <&sys <<
1439 resets = <&cpg 510>; <<
1440 renesas,bonding = <&d <<
1441 status = "disabled"; <<
1442 }; <<
1443 <<
1444 drif30: rif@e6fa0000 { <<
1445 compatible = "renesas <<
1446 "renesas <<
1447 reg = <0 0xe6fa0000 0 <<
1448 interrupts = <GIC_SPI <<
1449 clocks = <&cpg CPG_MO <<
1450 clock-names = "fck"; <<
1451 dmas = <&dmac0 0x2c>; <<
1452 dma-names = "rx"; <<
1453 power-domains = <&sys <<
1454 resets = <&cpg 509>; <<
1455 renesas,bonding = <&d <<
1456 status = "disabled"; <<
1457 }; <<
1458 <<
1459 drif31: rif@e6fb0000 { <<
1460 compatible = "renesas <<
1461 "renesas <<
1462 reg = <0 0xe6fb0000 0 <<
1463 interrupts = <GIC_SPI <<
1464 clocks = <&cpg CPG_MO <<
1465 clock-names = "fck"; <<
1466 dmas = <&dmac0 0x2e>; <<
1467 dma-names = "rx"; <<
1468 power-domains = <&sys <<
1469 resets = <&cpg 508>; <<
1470 renesas,bonding = <&d <<
1471 status = "disabled"; <<
1472 }; <<
1473 <<
1474 rcar_sound: sound@ec500000 { 1267 rcar_sound: sound@ec500000 {
1475 /* 1268 /*
1476 * #sound-dai-cells i !! 1269 * #sound-dai-cells is required
1477 * 1270 *
1478 * Single DAI : #soun 1271 * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
1479 * Multi DAI : #soun 1272 * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>;
1480 */ 1273 */
1481 /* 1274 /*
1482 * #clock-cells is re 1275 * #clock-cells is required for audio_clkout0/1/2/3
1483 * 1276 *
1484 * clkout : #cl 1277 * clkout : #clock-cells = <0>; <&rcar_sound>;
1485 * clkout0/1/2/3: #cl 1278 * clkout0/1/2/3: #clock-cells = <1>; <&rcar_sound N>;
1486 */ 1279 */
1487 compatible = "renesas !! 1280 compatible = "renesas,rcar_sound-r8a77990", "renesas,rcar_sound-gen3";
1488 reg = <0 0xec500000 0 !! 1281 reg = <0 0xec500000 0 0x1000>, /* SCU */
1489 <0 0xec5a0000 0 !! 1282 <0 0xec5a0000 0 0x100>, /* ADG */
1490 <0 0xec540000 0 !! 1283 <0 0xec540000 0 0x1000>, /* SSIU */
1491 <0 0xec541000 0 !! 1284 <0 0xec541000 0 0x280>, /* SSI */
1492 <0 0xec760000 0 !! 1285 <0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/
1493 reg-names = "scu", "a 1286 reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
1494 1287
1495 clocks = <&cpg CPG_MO 1288 clocks = <&cpg CPG_MOD 1005>,
1496 <&cpg CPG_MO 1289 <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
1497 <&cpg CPG_MO 1290 <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
1498 <&cpg CPG_MO 1291 <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
1499 <&cpg CPG_MO 1292 <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
1500 <&cpg CPG_MO 1293 <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
1501 <&cpg CPG_MO 1294 <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
1502 <&cpg CPG_MO 1295 <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
1503 <&cpg CPG_MO 1296 <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
1504 <&cpg CPG_MO 1297 <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
1505 <&cpg CPG_MO 1298 <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
1506 <&cpg CPG_MO 1299 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
1507 <&cpg CPG_MO 1300 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
1508 <&cpg CPG_MO 1301 <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
1509 <&audio_clk_ 1302 <&audio_clk_a>, <&audio_clk_b>,
1510 <&audio_clk_ 1303 <&audio_clk_c>,
1511 <&cpg CPG_MO !! 1304 <&cpg CPG_CORE R8A77990_CLK_ZA2>;
1512 clock-names = "ssi-al 1305 clock-names = "ssi-all",
1513 "ssi.9" 1306 "ssi.9", "ssi.8", "ssi.7", "ssi.6",
1514 "ssi.5" 1307 "ssi.5", "ssi.4", "ssi.3", "ssi.2",
1515 "ssi.1" 1308 "ssi.1", "ssi.0",
1516 "src.9" 1309 "src.9", "src.8", "src.7", "src.6",
1517 "src.5" 1310 "src.5", "src.4", "src.3", "src.2",
1518 "src.1" 1311 "src.1", "src.0",
1519 "mix.1" 1312 "mix.1", "mix.0",
1520 "ctu.1" 1313 "ctu.1", "ctu.0",
1521 "dvc.0" 1314 "dvc.0", "dvc.1",
1522 "clk_a" 1315 "clk_a", "clk_b", "clk_c", "clk_i";
1523 power-domains = <&sys 1316 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1524 resets = <&cpg 1005>, 1317 resets = <&cpg 1005>,
1525 <&cpg 1006>, 1318 <&cpg 1006>, <&cpg 1007>,
1526 <&cpg 1008>, 1319 <&cpg 1008>, <&cpg 1009>,
1527 <&cpg 1010>, 1320 <&cpg 1010>, <&cpg 1011>,
1528 <&cpg 1012>, 1321 <&cpg 1012>, <&cpg 1013>,
1529 <&cpg 1014>, 1322 <&cpg 1014>, <&cpg 1015>;
1530 reset-names = "ssi-al 1323 reset-names = "ssi-all",
1531 "ssi.9" 1324 "ssi.9", "ssi.8", "ssi.7", "ssi.6",
1532 "ssi.5" 1325 "ssi.5", "ssi.4", "ssi.3", "ssi.2",
1533 "ssi.1" 1326 "ssi.1", "ssi.0";
1534 status = "disabled"; 1327 status = "disabled";
1535 1328
1536 rcar_sound,ctu { <<
1537 ctu00: ctu-0 <<
1538 ctu01: ctu-1 <<
1539 ctu02: ctu-2 <<
1540 ctu03: ctu-3 <<
1541 ctu10: ctu-4 <<
1542 ctu11: ctu-5 <<
1543 ctu12: ctu-6 <<
1544 ctu13: ctu-7 <<
1545 }; <<
1546 <<
1547 rcar_sound,dvc { 1329 rcar_sound,dvc {
1548 dvc0: dvc-0 { 1330 dvc0: dvc-0 {
1549 dmas 1331 dmas = <&audma0 0xbc>;
1550 dma-n 1332 dma-names = "tx";
1551 }; 1333 };
1552 dvc1: dvc-1 { 1334 dvc1: dvc-1 {
1553 dmas 1335 dmas = <&audma0 0xbe>;
1554 dma-n 1336 dma-names = "tx";
1555 }; 1337 };
1556 }; 1338 };
1557 1339
1558 rcar_sound,mix { 1340 rcar_sound,mix {
1559 mix0: mix-0 { 1341 mix0: mix-0 { };
1560 mix1: mix-1 { 1342 mix1: mix-1 { };
1561 }; 1343 };
1562 1344
>> 1345 rcar_sound,ctu {
>> 1346 ctu00: ctu-0 { };
>> 1347 ctu01: ctu-1 { };
>> 1348 ctu02: ctu-2 { };
>> 1349 ctu03: ctu-3 { };
>> 1350 ctu10: ctu-4 { };
>> 1351 ctu11: ctu-5 { };
>> 1352 ctu12: ctu-6 { };
>> 1353 ctu13: ctu-7 { };
>> 1354 };
>> 1355
1563 rcar_sound,src { 1356 rcar_sound,src {
1564 src0: src-0 { 1357 src0: src-0 {
1565 inter 1358 interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
1566 dmas 1359 dmas = <&audma0 0x85>, <&audma0 0x9a>;
1567 dma-n 1360 dma-names = "rx", "tx";
1568 }; 1361 };
1569 src1: src-1 { 1362 src1: src-1 {
1570 inter 1363 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1571 dmas 1364 dmas = <&audma0 0x87>, <&audma0 0x9c>;
1572 dma-n 1365 dma-names = "rx", "tx";
1573 }; 1366 };
1574 src2: src-2 { 1367 src2: src-2 {
1575 inter 1368 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1576 dmas 1369 dmas = <&audma0 0x89>, <&audma0 0x9e>;
1577 dma-n 1370 dma-names = "rx", "tx";
1578 }; 1371 };
1579 src3: src-3 { 1372 src3: src-3 {
1580 inter 1373 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1581 dmas 1374 dmas = <&audma0 0x8b>, <&audma0 0xa0>;
1582 dma-n 1375 dma-names = "rx", "tx";
1583 }; 1376 };
1584 src4: src-4 { 1377 src4: src-4 {
1585 inter 1378 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1586 dmas 1379 dmas = <&audma0 0x8d>, <&audma0 0xb0>;
1587 dma-n 1380 dma-names = "rx", "tx";
1588 }; 1381 };
1589 src5: src-5 { 1382 src5: src-5 {
1590 inter 1383 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1591 dmas 1384 dmas = <&audma0 0x8f>, <&audma0 0xb2>;
1592 dma-n 1385 dma-names = "rx", "tx";
1593 }; 1386 };
1594 src6: src-6 { 1387 src6: src-6 {
1595 inter 1388 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1596 dmas 1389 dmas = <&audma0 0x91>, <&audma0 0xb4>;
1597 dma-n 1390 dma-names = "rx", "tx";
1598 }; 1391 };
1599 src7: src-7 { 1392 src7: src-7 {
1600 inter 1393 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
1601 dmas 1394 dmas = <&audma0 0x93>, <&audma0 0xb6>;
1602 dma-n 1395 dma-names = "rx", "tx";
1603 }; 1396 };
1604 src8: src-8 { 1397 src8: src-8 {
1605 inter 1398 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
1606 dmas 1399 dmas = <&audma0 0x95>, <&audma0 0xb8>;
1607 dma-n 1400 dma-names = "rx", "tx";
1608 }; 1401 };
1609 src9: src-9 { 1402 src9: src-9 {
1610 inter 1403 interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>;
1611 dmas 1404 dmas = <&audma0 0x97>, <&audma0 0xba>;
1612 dma-n 1405 dma-names = "rx", "tx";
1613 }; 1406 };
1614 }; 1407 };
1615 1408
1616 rcar_sound,ssi { 1409 rcar_sound,ssi {
1617 ssi0: ssi-0 { 1410 ssi0: ssi-0 {
1618 inter 1411 interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
1619 dmas 1412 dmas = <&audma0 0x01>, <&audma0 0x02>,
1620 1413 <&audma0 0x15>, <&audma0 0x16>;
1621 dma-n 1414 dma-names = "rx", "tx", "rxu", "txu";
1622 }; 1415 };
1623 ssi1: ssi-1 { 1416 ssi1: ssi-1 {
1624 inter 1417 interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
1625 dmas 1418 dmas = <&audma0 0x03>, <&audma0 0x04>,
1626 1419 <&audma0 0x49>, <&audma0 0x4a>;
1627 dma-n 1420 dma-names = "rx", "tx", "rxu", "txu";
1628 }; 1421 };
1629 ssi2: ssi-2 { 1422 ssi2: ssi-2 {
1630 inter 1423 interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>;
1631 dmas 1424 dmas = <&audma0 0x05>, <&audma0 0x06>,
1632 1425 <&audma0 0x63>, <&audma0 0x64>;
1633 dma-n 1426 dma-names = "rx", "tx", "rxu", "txu";
1634 }; 1427 };
1635 ssi3: ssi-3 { 1428 ssi3: ssi-3 {
1636 inter 1429 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
1637 dmas 1430 dmas = <&audma0 0x07>, <&audma0 0x08>,
1638 1431 <&audma0 0x6f>, <&audma0 0x70>;
1639 dma-n 1432 dma-names = "rx", "tx", "rxu", "txu";
1640 }; 1433 };
1641 ssi4: ssi-4 { 1434 ssi4: ssi-4 {
1642 inter 1435 interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
1643 dmas 1436 dmas = <&audma0 0x09>, <&audma0 0x0a>,
1644 1437 <&audma0 0x71>, <&audma0 0x72>;
1645 dma-n 1438 dma-names = "rx", "tx", "rxu", "txu";
1646 }; 1439 };
1647 ssi5: ssi-5 { 1440 ssi5: ssi-5 {
1648 inter 1441 interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
1649 dmas 1442 dmas = <&audma0 0x0b>, <&audma0 0x0c>,
1650 1443 <&audma0 0x73>, <&audma0 0x74>;
1651 dma-n 1444 dma-names = "rx", "tx", "rxu", "txu";
1652 }; 1445 };
1653 ssi6: ssi-6 { 1446 ssi6: ssi-6 {
1654 inter 1447 interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>;
1655 dmas 1448 dmas = <&audma0 0x0d>, <&audma0 0x0e>,
1656 1449 <&audma0 0x75>, <&audma0 0x76>;
1657 dma-n 1450 dma-names = "rx", "tx", "rxu", "txu";
1658 }; 1451 };
1659 ssi7: ssi-7 { 1452 ssi7: ssi-7 {
1660 inter 1453 interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>;
1661 dmas 1454 dmas = <&audma0 0x0f>, <&audma0 0x10>,
1662 1455 <&audma0 0x79>, <&audma0 0x7a>;
1663 dma-n 1456 dma-names = "rx", "tx", "rxu", "txu";
1664 }; 1457 };
1665 ssi8: ssi-8 { 1458 ssi8: ssi-8 {
1666 inter 1459 interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>;
1667 dmas 1460 dmas = <&audma0 0x11>, <&audma0 0x12>,
1668 1461 <&audma0 0x7b>, <&audma0 0x7c>;
1669 dma-n 1462 dma-names = "rx", "tx", "rxu", "txu";
1670 }; 1463 };
1671 ssi9: ssi-9 { 1464 ssi9: ssi-9 {
1672 inter 1465 interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
1673 dmas 1466 dmas = <&audma0 0x13>, <&audma0 0x14>,
1674 1467 <&audma0 0x7d>, <&audma0 0x7e>;
1675 dma-n 1468 dma-names = "rx", "tx", "rxu", "txu";
1676 }; 1469 };
1677 }; 1470 };
1678 }; 1471 };
1679 1472
1680 mlp: mlp@ec520000 { <<
1681 compatible = "renesas <<
1682 "renesas <<
1683 reg = <0 0xec520000 0 <<
1684 interrupts = <GIC_SPI <<
1685 <GIC_SPI 385 <<
1686 clocks = <&cpg CPG_MO <<
1687 power-domains = <&sys <<
1688 resets = <&cpg 802>; <<
1689 status = "disabled"; <<
1690 }; <<
1691 <<
1692 audma0: dma-controller@ec7000 1473 audma0: dma-controller@ec700000 {
1693 compatible = "renesas 1474 compatible = "renesas,dmac-r8a77990",
1694 "renesas 1475 "renesas,rcar-dmac";
1695 reg = <0 0xec700000 0 1476 reg = <0 0xec700000 0 0x10000>;
1696 interrupts = <GIC_SPI !! 1477 interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH
1697 <GIC_SPI !! 1478 GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH
1698 <GIC_SPI !! 1479 GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH
1699 <GIC_SPI !! 1480 GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH
1700 <GIC_SPI !! 1481 GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH
1701 <GIC_SPI !! 1482 GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH
1702 <GIC_SPI !! 1483 GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH
1703 <GIC_SPI !! 1484 GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH
1704 <GIC_SPI !! 1485 GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH
1705 <GIC_SPI !! 1486 GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH
1706 <GIC_SPI !! 1487 GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH
1707 <GIC_SPI !! 1488 GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH
1708 <GIC_SPI !! 1489 GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH
1709 <GIC_SPI !! 1490 GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH
1710 <GIC_SPI !! 1491 GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH
1711 <GIC_SPI !! 1492 GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH
1712 <GIC_SPI !! 1493 GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>;
1713 interrupt-names = "er 1494 interrupt-names = "error",
1714 "ch0" 1495 "ch0", "ch1", "ch2", "ch3",
1715 "ch4" 1496 "ch4", "ch5", "ch6", "ch7",
1716 "ch8" 1497 "ch8", "ch9", "ch10", "ch11",
1717 "ch12 1498 "ch12", "ch13", "ch14", "ch15";
1718 clocks = <&cpg CPG_MO 1499 clocks = <&cpg CPG_MOD 502>;
1719 clock-names = "fck"; 1500 clock-names = "fck";
1720 power-domains = <&sys 1501 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1721 resets = <&cpg 502>; 1502 resets = <&cpg 502>;
1722 #dma-cells = <1>; 1503 #dma-cells = <1>;
1723 dma-channels = <16>; 1504 dma-channels = <16>;
1724 iommus = <&ipmmu_mp 0 1505 iommus = <&ipmmu_mp 0>, <&ipmmu_mp 1>,
1725 <&ipmmu_mp 2 1506 <&ipmmu_mp 2>, <&ipmmu_mp 3>,
1726 <&ipmmu_mp 4 1507 <&ipmmu_mp 4>, <&ipmmu_mp 5>,
1727 <&ipmmu_mp 6 1508 <&ipmmu_mp 6>, <&ipmmu_mp 7>,
1728 <&ipmmu_mp 8 1509 <&ipmmu_mp 8>, <&ipmmu_mp 9>,
1729 <&ipmmu_mp 1 1510 <&ipmmu_mp 10>, <&ipmmu_mp 11>,
1730 <&ipmmu_mp 1 1511 <&ipmmu_mp 12>, <&ipmmu_mp 13>,
1731 <&ipmmu_mp 1 1512 <&ipmmu_mp 14>, <&ipmmu_mp 15>;
1732 }; 1513 };
1733 1514
1734 xhci0: usb@ee000000 { 1515 xhci0: usb@ee000000 {
1735 compatible = "renesas 1516 compatible = "renesas,xhci-r8a77990",
1736 "renesas 1517 "renesas,rcar-gen3-xhci";
1737 reg = <0 0xee000000 0 1518 reg = <0 0xee000000 0 0xc00>;
1738 interrupts = <GIC_SPI 1519 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
1739 clocks = <&cpg CPG_MO 1520 clocks = <&cpg CPG_MOD 328>;
1740 power-domains = <&sys 1521 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1741 resets = <&cpg 328>; 1522 resets = <&cpg 328>;
1742 status = "disabled"; 1523 status = "disabled";
1743 }; 1524 };
1744 1525
1745 usb3_peri0: usb@ee020000 { 1526 usb3_peri0: usb@ee020000 {
1746 compatible = "renesas 1527 compatible = "renesas,r8a77990-usb3-peri",
1747 "renesas 1528 "renesas,rcar-gen3-usb3-peri";
1748 reg = <0 0xee020000 0 1529 reg = <0 0xee020000 0 0x400>;
1749 interrupts = <GIC_SPI 1530 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
1750 clocks = <&cpg CPG_MO 1531 clocks = <&cpg CPG_MOD 328>;
1751 power-domains = <&sys 1532 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1752 resets = <&cpg 328>; 1533 resets = <&cpg 328>;
1753 status = "disabled"; 1534 status = "disabled";
1754 }; 1535 };
1755 1536
1756 ohci0: usb@ee080000 { 1537 ohci0: usb@ee080000 {
1757 compatible = "generic 1538 compatible = "generic-ohci";
1758 reg = <0 0xee080000 0 1539 reg = <0 0xee080000 0 0x100>;
1759 interrupts = <GIC_SPI 1540 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
1760 clocks = <&cpg CPG_MO 1541 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
1761 phys = <&usb2_phy0 1> 1542 phys = <&usb2_phy0 1>;
1762 phy-names = "usb"; 1543 phy-names = "usb";
1763 power-domains = <&sys 1544 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1764 resets = <&cpg 703>, 1545 resets = <&cpg 703>, <&cpg 704>;
1765 status = "disabled"; 1546 status = "disabled";
1766 }; 1547 };
1767 1548
1768 ehci0: usb@ee080100 { 1549 ehci0: usb@ee080100 {
1769 compatible = "generic 1550 compatible = "generic-ehci";
1770 reg = <0 0xee080100 0 1551 reg = <0 0xee080100 0 0x100>;
1771 interrupts = <GIC_SPI 1552 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
1772 clocks = <&cpg CPG_MO 1553 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
1773 phys = <&usb2_phy0 2> 1554 phys = <&usb2_phy0 2>;
1774 phy-names = "usb"; 1555 phy-names = "usb";
1775 companion = <&ohci0>; 1556 companion = <&ohci0>;
1776 power-domains = <&sys 1557 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1777 resets = <&cpg 703>, 1558 resets = <&cpg 703>, <&cpg 704>;
1778 status = "disabled"; 1559 status = "disabled";
1779 }; 1560 };
1780 1561
1781 usb2_phy0: usb-phy@ee080200 { 1562 usb2_phy0: usb-phy@ee080200 {
1782 compatible = "renesas 1563 compatible = "renesas,usb2-phy-r8a77990",
1783 "renesas 1564 "renesas,rcar-gen3-usb2-phy";
1784 reg = <0 0xee080200 0 1565 reg = <0 0xee080200 0 0x700>;
1785 interrupts = <GIC_SPI 1566 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
1786 clocks = <&cpg CPG_MO 1567 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
1787 power-domains = <&sys 1568 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1788 resets = <&cpg 703>, 1569 resets = <&cpg 703>, <&cpg 704>;
1789 #phy-cells = <1>; 1570 #phy-cells = <1>;
1790 status = "disabled"; 1571 status = "disabled";
1791 }; 1572 };
1792 1573
1793 sdhi0: mmc@ee100000 { !! 1574 sdhi0: sd@ee100000 {
1794 compatible = "renesas 1575 compatible = "renesas,sdhi-r8a77990",
1795 "renesas 1576 "renesas,rcar-gen3-sdhi";
1796 reg = <0 0xee100000 0 1577 reg = <0 0xee100000 0 0x2000>;
1797 interrupts = <GIC_SPI 1578 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
1798 clocks = <&cpg CPG_MO !! 1579 clocks = <&cpg CPG_MOD 314>;
1799 clock-names = "core", <<
1800 max-frequency = <2000 1580 max-frequency = <200000000>;
1801 power-domains = <&sys 1581 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1802 resets = <&cpg 314>; 1582 resets = <&cpg 314>;
1803 iommus = <&ipmmu_ds1 <<
1804 status = "disabled"; 1583 status = "disabled";
1805 }; 1584 };
1806 1585
1807 sdhi1: mmc@ee120000 { !! 1586 sdhi1: sd@ee120000 {
1808 compatible = "renesas 1587 compatible = "renesas,sdhi-r8a77990",
1809 "renesas 1588 "renesas,rcar-gen3-sdhi";
1810 reg = <0 0xee120000 0 1589 reg = <0 0xee120000 0 0x2000>;
1811 interrupts = <GIC_SPI 1590 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
1812 clocks = <&cpg CPG_MO !! 1591 clocks = <&cpg CPG_MOD 313>;
1813 clock-names = "core", <<
1814 max-frequency = <2000 1592 max-frequency = <200000000>;
1815 power-domains = <&sys 1593 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1816 resets = <&cpg 313>; 1594 resets = <&cpg 313>;
1817 iommus = <&ipmmu_ds1 <<
1818 status = "disabled"; 1595 status = "disabled";
1819 }; 1596 };
1820 1597
1821 sdhi3: mmc@ee160000 { !! 1598 sdhi3: sd@ee160000 {
1822 compatible = "renesas 1599 compatible = "renesas,sdhi-r8a77990",
1823 "renesas 1600 "renesas,rcar-gen3-sdhi";
1824 reg = <0 0xee160000 0 1601 reg = <0 0xee160000 0 0x2000>;
1825 interrupts = <GIC_SPI 1602 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
1826 clocks = <&cpg CPG_MO !! 1603 clocks = <&cpg CPG_MOD 311>;
1827 clock-names = "core", <<
1828 max-frequency = <2000 1604 max-frequency = <200000000>;
1829 power-domains = <&sys 1605 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1830 resets = <&cpg 311>; 1606 resets = <&cpg 311>;
1831 iommus = <&ipmmu_ds1 <<
1832 status = "disabled"; <<
1833 }; <<
1834 <<
1835 rpc: spi@ee200000 { <<
1836 compatible = "renesas <<
1837 "renesas <<
1838 reg = <0 0xee200000 0 <<
1839 <0 0x08000000 0 <<
1840 <0 0xee208000 0 <<
1841 reg-names = "regs", " <<
1842 interrupts = <GIC_SPI <<
1843 clocks = <&cpg CPG_MO <<
1844 power-domains = <&sys <<
1845 resets = <&cpg 917>; <<
1846 #address-cells = <1>; <<
1847 #size-cells = <0>; <<
1848 status = "disabled"; 1607 status = "disabled";
1849 }; 1608 };
1850 1609
1851 gic: interrupt-controller@f10 1610 gic: interrupt-controller@f1010000 {
1852 compatible = "arm,gic 1611 compatible = "arm,gic-400";
1853 #interrupt-cells = <3 1612 #interrupt-cells = <3>;
1854 #address-cells = <0>; 1613 #address-cells = <0>;
1855 interrupt-controller; 1614 interrupt-controller;
1856 reg = <0x0 0xf1010000 1615 reg = <0x0 0xf1010000 0 0x1000>,
1857 <0x0 0xf1020000 1616 <0x0 0xf1020000 0 0x20000>,
1858 <0x0 0xf1040000 1617 <0x0 0xf1040000 0 0x20000>,
1859 <0x0 0xf1060000 1618 <0x0 0xf1060000 0 0x20000>;
1860 interrupts = <GIC_PPI 1619 interrupts = <GIC_PPI 9
1861 (GIC_ 1620 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
1862 clocks = <&cpg CPG_MO 1621 clocks = <&cpg CPG_MOD 408>;
1863 clock-names = "clk"; 1622 clock-names = "clk";
1864 power-domains = <&sys 1623 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1865 resets = <&cpg 408>; 1624 resets = <&cpg 408>;
1866 }; 1625 };
1867 1626
1868 pciec0: pcie@fe000000 { 1627 pciec0: pcie@fe000000 {
1869 compatible = "renesas 1628 compatible = "renesas,pcie-r8a77990",
1870 "renesas 1629 "renesas,pcie-rcar-gen3";
1871 reg = <0 0xfe000000 0 1630 reg = <0 0xfe000000 0 0x80000>;
1872 #address-cells = <3>; 1631 #address-cells = <3>;
1873 #size-cells = <2>; 1632 #size-cells = <2>;
1874 bus-range = <0x00 0xf 1633 bus-range = <0x00 0xff>;
1875 device_type = "pci"; 1634 device_type = "pci";
1876 ranges = <0x01000000 !! 1635 ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000
1877 <0x02000000 !! 1636 0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000
1878 <0x02000000 !! 1637 0x02000000 0 0x30000000 0 0x30000000 0 0x08000000
1879 <0x42000000 !! 1638 0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
1880 /* Map all possible D !! 1639 /* Map all possible DDR as inbound ranges */
1881 dma-ranges = <0x42000 !! 1640 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x40000000>;
1882 interrupts = <GIC_SPI 1641 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
1883 <GIC_SPI 1642 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
1884 <GIC_SPI 1643 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
1885 #interrupt-cells = <1 1644 #interrupt-cells = <1>;
1886 interrupt-map-mask = 1645 interrupt-map-mask = <0 0 0 0>;
1887 interrupt-map = <0 0 1646 interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
1888 clocks = <&cpg CPG_MO 1647 clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>;
1889 clock-names = "pcie", 1648 clock-names = "pcie", "pcie_bus";
1890 power-domains = <&sys 1649 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1891 resets = <&cpg 319>; 1650 resets = <&cpg 319>;
1892 iommu-map = <0 &ipmmu <<
1893 iommu-map-mask = <0>; <<
1894 status = "disabled"; 1651 status = "disabled";
1895 }; 1652 };
1896 1653
1897 vspb0: vsp@fe960000 { 1654 vspb0: vsp@fe960000 {
1898 compatible = "renesas 1655 compatible = "renesas,vsp2";
1899 reg = <0 0xfe960000 0 1656 reg = <0 0xfe960000 0 0x8000>;
1900 interrupts = <GIC_SPI 1657 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
1901 clocks = <&cpg CPG_MO 1658 clocks = <&cpg CPG_MOD 626>;
1902 power-domains = <&sys 1659 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1903 resets = <&cpg 626>; 1660 resets = <&cpg 626>;
1904 renesas,fcp = <&fcpvb 1661 renesas,fcp = <&fcpvb0>;
1905 }; 1662 };
1906 1663
1907 fcpvb0: fcp@fe96f000 { 1664 fcpvb0: fcp@fe96f000 {
1908 compatible = "renesas 1665 compatible = "renesas,fcpv";
1909 reg = <0 0xfe96f000 0 1666 reg = <0 0xfe96f000 0 0x200>;
1910 clocks = <&cpg CPG_MO 1667 clocks = <&cpg CPG_MOD 607>;
1911 power-domains = <&sys 1668 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1912 resets = <&cpg 607>; 1669 resets = <&cpg 607>;
1913 iommus = <&ipmmu_vp0 1670 iommus = <&ipmmu_vp0 5>;
1914 }; 1671 };
1915 1672
1916 vspi0: vsp@fe9a0000 { 1673 vspi0: vsp@fe9a0000 {
1917 compatible = "renesas 1674 compatible = "renesas,vsp2";
1918 reg = <0 0xfe9a0000 0 1675 reg = <0 0xfe9a0000 0 0x8000>;
1919 interrupts = <GIC_SPI 1676 interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>;
1920 clocks = <&cpg CPG_MO 1677 clocks = <&cpg CPG_MOD 631>;
1921 power-domains = <&sys 1678 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1922 resets = <&cpg 631>; 1679 resets = <&cpg 631>;
1923 renesas,fcp = <&fcpvi 1680 renesas,fcp = <&fcpvi0>;
1924 }; 1681 };
1925 1682
1926 fcpvi0: fcp@fe9af000 { 1683 fcpvi0: fcp@fe9af000 {
1927 compatible = "renesas 1684 compatible = "renesas,fcpv";
1928 reg = <0 0xfe9af000 0 1685 reg = <0 0xfe9af000 0 0x200>;
1929 clocks = <&cpg CPG_MO 1686 clocks = <&cpg CPG_MOD 611>;
1930 power-domains = <&sys 1687 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1931 resets = <&cpg 611>; 1688 resets = <&cpg 611>;
1932 iommus = <&ipmmu_vp0 1689 iommus = <&ipmmu_vp0 8>;
1933 }; 1690 };
1934 1691
1935 vspd0: vsp@fea20000 { 1692 vspd0: vsp@fea20000 {
1936 compatible = "renesas 1693 compatible = "renesas,vsp2";
1937 reg = <0 0xfea20000 0 1694 reg = <0 0xfea20000 0 0x7000>;
1938 interrupts = <GIC_SPI 1695 interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>;
1939 clocks = <&cpg CPG_MO 1696 clocks = <&cpg CPG_MOD 623>;
1940 power-domains = <&sys 1697 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1941 resets = <&cpg 623>; 1698 resets = <&cpg 623>;
1942 renesas,fcp = <&fcpvd 1699 renesas,fcp = <&fcpvd0>;
1943 }; 1700 };
1944 1701
1945 fcpvd0: fcp@fea27000 { 1702 fcpvd0: fcp@fea27000 {
1946 compatible = "renesas 1703 compatible = "renesas,fcpv";
1947 reg = <0 0xfea27000 0 1704 reg = <0 0xfea27000 0 0x200>;
1948 clocks = <&cpg CPG_MO 1705 clocks = <&cpg CPG_MOD 603>;
1949 power-domains = <&sys 1706 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1950 resets = <&cpg 603>; 1707 resets = <&cpg 603>;
1951 iommus = <&ipmmu_vi0 1708 iommus = <&ipmmu_vi0 8>;
1952 }; 1709 };
1953 1710
1954 vspd1: vsp@fea28000 { 1711 vspd1: vsp@fea28000 {
1955 compatible = "renesas 1712 compatible = "renesas,vsp2";
1956 reg = <0 0xfea28000 0 1713 reg = <0 0xfea28000 0 0x7000>;
1957 interrupts = <GIC_SPI 1714 interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>;
1958 clocks = <&cpg CPG_MO 1715 clocks = <&cpg CPG_MOD 622>;
1959 power-domains = <&sys 1716 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1960 resets = <&cpg 622>; 1717 resets = <&cpg 622>;
1961 renesas,fcp = <&fcpvd 1718 renesas,fcp = <&fcpvd1>;
1962 }; 1719 };
1963 1720
1964 fcpvd1: fcp@fea2f000 { 1721 fcpvd1: fcp@fea2f000 {
1965 compatible = "renesas 1722 compatible = "renesas,fcpv";
1966 reg = <0 0xfea2f000 0 1723 reg = <0 0xfea2f000 0 0x200>;
1967 clocks = <&cpg CPG_MO 1724 clocks = <&cpg CPG_MOD 602>;
1968 power-domains = <&sys 1725 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1969 resets = <&cpg 602>; 1726 resets = <&cpg 602>;
1970 iommus = <&ipmmu_vi0 1727 iommus = <&ipmmu_vi0 9>;
1971 }; 1728 };
1972 1729
1973 cmm0: cmm@fea40000 { <<
1974 compatible = "renesas <<
1975 "renesas <<
1976 reg = <0 0xfea40000 0 <<
1977 power-domains = <&sys <<
1978 clocks = <&cpg CPG_MO <<
1979 resets = <&cpg 711>; <<
1980 }; <<
1981 <<
1982 cmm1: cmm@fea50000 { <<
1983 compatible = "renesas <<
1984 "renesas <<
1985 reg = <0 0xfea50000 0 <<
1986 power-domains = <&sys <<
1987 clocks = <&cpg CPG_MO <<
1988 resets = <&cpg 710>; <<
1989 }; <<
1990 <<
1991 csi40: csi2@feaa0000 { 1730 csi40: csi2@feaa0000 {
1992 compatible = "renesas 1731 compatible = "renesas,r8a77990-csi2";
1993 reg = <0 0xfeaa0000 0 1732 reg = <0 0xfeaa0000 0 0x10000>;
1994 interrupts = <GIC_SPI 1733 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
1995 clocks = <&cpg CPG_MO 1734 clocks = <&cpg CPG_MOD 716>;
1996 power-domains = <&sys 1735 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1997 resets = <&cpg 716>; 1736 resets = <&cpg 716>;
1998 status = "disabled"; 1737 status = "disabled";
1999 1738
2000 ports { 1739 ports {
2001 #address-cell 1740 #address-cells = <1>;
2002 #size-cells = 1741 #size-cells = <0>;
2003 1742
2004 port@0 { <<
2005 reg = <<
2006 }; <<
2007 <<
2008 port@1 { 1743 port@1 {
2009 #addr 1744 #address-cells = <1>;
2010 #size 1745 #size-cells = <0>;
2011 1746
2012 reg = 1747 reg = <1>;
2013 1748
2014 csi40 1749 csi40vin4: endpoint@0 {
2015 1750 reg = <0>;
2016 1751 remote-endpoint = <&vin4csi40>;
2017 }; 1752 };
2018 csi40 1753 csi40vin5: endpoint@1 {
2019 1754 reg = <1>;
2020 1755 remote-endpoint = <&vin5csi40>;
2021 }; 1756 };
2022 }; 1757 };
2023 }; 1758 };
2024 }; 1759 };
2025 1760
2026 du: display@feb00000 { 1761 du: display@feb00000 {
2027 compatible = "renesas 1762 compatible = "renesas,du-r8a77990";
2028 reg = <0 0xfeb00000 0 1763 reg = <0 0xfeb00000 0 0x40000>;
2029 interrupts = <GIC_SPI 1764 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
2030 <GIC_SPI 1765 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
2031 clocks = <&cpg CPG_MO !! 1766 clocks = <&cpg CPG_MOD 724>,
>> 1767 <&cpg CPG_MOD 723>;
2032 clock-names = "du.0", 1768 clock-names = "du.0", "du.1";
2033 resets = <&cpg 724>; !! 1769 vsps = <&vspd0 0 &vspd1 0>;
2034 reset-names = "du.0"; <<
2035 <<
2036 renesas,cmms = <&cmm0 <<
2037 renesas,vsps = <&vspd <<
2038 <<
2039 status = "disabled"; 1770 status = "disabled";
2040 1771
2041 ports { 1772 ports {
2042 #address-cell 1773 #address-cells = <1>;
2043 #size-cells = 1774 #size-cells = <0>;
2044 1775
2045 port@0 { 1776 port@0 {
2046 reg = 1777 reg = <0>;
>> 1778 du_out_rgb: endpoint {
>> 1779 };
2047 }; 1780 };
2048 1781
2049 port@1 { 1782 port@1 {
2050 reg = 1783 reg = <1>;
2051 du_ou 1784 du_out_lvds0: endpoint {
2052 1785 remote-endpoint = <&lvds0_in>;
2053 }; 1786 };
2054 }; 1787 };
2055 1788
2056 port@2 { 1789 port@2 {
2057 reg = 1790 reg = <2>;
2058 du_ou 1791 du_out_lvds1: endpoint {
2059 1792 remote-endpoint = <&lvds1_in>;
2060 }; 1793 };
2061 }; 1794 };
2062 }; 1795 };
2063 }; 1796 };
2064 1797
2065 lvds0: lvds-encoder@feb90000 1798 lvds0: lvds-encoder@feb90000 {
2066 compatible = "renesas 1799 compatible = "renesas,r8a77990-lvds";
2067 reg = <0 0xfeb90000 0 1800 reg = <0 0xfeb90000 0 0x20>;
2068 clocks = <&cpg CPG_MO 1801 clocks = <&cpg CPG_MOD 727>;
2069 power-domains = <&sys 1802 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
2070 resets = <&cpg 727>; 1803 resets = <&cpg 727>;
2071 status = "disabled"; 1804 status = "disabled";
2072 1805
2073 renesas,companion = < 1806 renesas,companion = <&lvds1>;
2074 1807
2075 ports { 1808 ports {
2076 #address-cell 1809 #address-cells = <1>;
2077 #size-cells = 1810 #size-cells = <0>;
2078 1811
2079 port@0 { 1812 port@0 {
2080 reg = 1813 reg = <0>;
2081 lvds0 1814 lvds0_in: endpoint {
2082 1815 remote-endpoint = <&du_out_lvds0>;
2083 }; 1816 };
2084 }; 1817 };
2085 1818
2086 port@1 { 1819 port@1 {
2087 reg = 1820 reg = <1>;
>> 1821 lvds0_out: endpoint {
>> 1822 };
2088 }; 1823 };
2089 }; 1824 };
2090 }; 1825 };
2091 1826
2092 lvds1: lvds-encoder@feb90100 1827 lvds1: lvds-encoder@feb90100 {
2093 compatible = "renesas 1828 compatible = "renesas,r8a77990-lvds";
2094 reg = <0 0xfeb90100 0 1829 reg = <0 0xfeb90100 0 0x20>;
2095 clocks = <&cpg CPG_MO 1830 clocks = <&cpg CPG_MOD 727>;
2096 power-domains = <&sys 1831 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
2097 resets = <&cpg 726>; 1832 resets = <&cpg 726>;
2098 status = "disabled"; 1833 status = "disabled";
2099 1834
2100 ports { 1835 ports {
2101 #address-cell 1836 #address-cells = <1>;
2102 #size-cells = 1837 #size-cells = <0>;
2103 1838
2104 port@0 { 1839 port@0 {
2105 reg = 1840 reg = <0>;
2106 lvds1 1841 lvds1_in: endpoint {
2107 1842 remote-endpoint = <&du_out_lvds1>;
2108 }; 1843 };
2109 }; 1844 };
2110 1845
2111 port@1 { 1846 port@1 {
2112 reg = 1847 reg = <1>;
>> 1848 lvds1_out: endpoint {
>> 1849 };
2113 }; 1850 };
2114 }; 1851 };
2115 }; 1852 };
2116 1853
2117 prr: chipid@fff00044 { 1854 prr: chipid@fff00044 {
2118 compatible = "renesas 1855 compatible = "renesas,prr";
2119 reg = <0 0xfff00044 0 1856 reg = <0 0xfff00044 0 4>;
2120 }; 1857 };
2121 }; 1858 };
2122 1859
2123 thermal-zones { 1860 thermal-zones {
2124 cpu-thermal { 1861 cpu-thermal {
2125 polling-delay-passive 1862 polling-delay-passive = <250>;
2126 polling-delay = <0>; 1863 polling-delay = <0>;
2127 thermal-sensors = <&t !! 1864 thermal-sensors = <&thermal 0>;
2128 sustainable-power = < 1865 sustainable-power = <717>;
2129 1866
2130 cooling-maps { !! 1867 trips {
2131 map0 { !! 1868 target: trip-point1 {
2132 trip !! 1869 temperature = <100000>;
2133 cooli !! 1870 hysteresis = <2000>;
2134 contr !! 1871 type = "passive";
2135 }; 1872 };
2136 }; <<
2137 1873
2138 trips { <<
2139 sensor1_crit: 1874 sensor1_crit: sensor1-crit {
2140 tempe 1875 temperature = <120000>;
2141 hyste 1876 hysteresis = <2000>;
2142 type 1877 type = "critical";
2143 }; 1878 };
>> 1879 };
2144 1880
2145 target: trip- !! 1881 cooling-maps {
2146 tempe !! 1882 map0 {
2147 hyste !! 1883 trip = <&target>;
2148 type !! 1884 cooling-device = <&a53_0 0 2>;
>> 1885 contribution = <1024>;
2149 }; 1886 };
2150 }; 1887 };
2151 }; 1888 };
2152 }; 1889 };
2153 1890
2154 timer { 1891 timer {
2155 compatible = "arm,armv8-timer 1892 compatible = "arm,armv8-timer";
2156 interrupts-extended = <&gic G 1893 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
2157 <&gic G 1894 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
2158 <&gic G 1895 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
2159 <&gic G 1896 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
2160 interrupt-names = "sec-phys", <<
2161 }; 1897 };
2162 }; 1898 };
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