1 // SPDX-License-Identifier: GPL-2.0 1 // SPDX-License-Identifier: GPL-2.0
2 /* 2 /*
3 * Device Tree Source for the R-Car E3 (R8A779 3 * Device Tree Source for the R-Car E3 (R8A77990) SoC
4 * 4 *
5 * Copyright (C) 2018-2019 Renesas Electronics 5 * Copyright (C) 2018-2019 Renesas Electronics Corp.
6 */ 6 */
7 7
8 #include <dt-bindings/clock/r8a77990-cpg-mssr. 8 #include <dt-bindings/clock/r8a77990-cpg-mssr.h>
9 #include <dt-bindings/interrupt-controller/arm 9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/power/r8a77990-sysc.h> 10 #include <dt-bindings/power/r8a77990-sysc.h>
11 11
12 / { 12 / {
13 compatible = "renesas,r8a77990"; 13 compatible = "renesas,r8a77990";
14 #address-cells = <2>; 14 #address-cells = <2>;
15 #size-cells = <2>; 15 #size-cells = <2>;
16 16
>> 17 aliases {
>> 18 i2c0 = &i2c0;
>> 19 i2c1 = &i2c1;
>> 20 i2c2 = &i2c2;
>> 21 i2c3 = &i2c3;
>> 22 i2c4 = &i2c4;
>> 23 i2c5 = &i2c5;
>> 24 i2c6 = &i2c6;
>> 25 i2c7 = &i2c7;
>> 26 };
>> 27
17 /* 28 /*
18 * The external audio clocks are confi 29 * The external audio clocks are configured as 0 Hz fixed frequency
19 * clocks by default. 30 * clocks by default.
20 * Boards that provide audio clocks sh 31 * Boards that provide audio clocks should override them.
21 */ 32 */
22 audio_clk_a: audio_clk_a { 33 audio_clk_a: audio_clk_a {
23 compatible = "fixed-clock"; 34 compatible = "fixed-clock";
24 #clock-cells = <0>; 35 #clock-cells = <0>;
25 clock-frequency = <0>; 36 clock-frequency = <0>;
26 }; 37 };
27 38
28 audio_clk_b: audio_clk_b { 39 audio_clk_b: audio_clk_b {
29 compatible = "fixed-clock"; 40 compatible = "fixed-clock";
30 #clock-cells = <0>; 41 #clock-cells = <0>;
31 clock-frequency = <0>; 42 clock-frequency = <0>;
32 }; 43 };
33 44
34 audio_clk_c: audio_clk_c { 45 audio_clk_c: audio_clk_c {
35 compatible = "fixed-clock"; 46 compatible = "fixed-clock";
36 #clock-cells = <0>; 47 #clock-cells = <0>;
37 clock-frequency = <0>; 48 clock-frequency = <0>;
38 }; 49 };
39 50
40 /* External CAN clock - to be overridd 51 /* External CAN clock - to be overridden by boards that provide it */
41 can_clk: can { 52 can_clk: can {
42 compatible = "fixed-clock"; 53 compatible = "fixed-clock";
43 #clock-cells = <0>; 54 #clock-cells = <0>;
44 clock-frequency = <0>; 55 clock-frequency = <0>;
45 }; 56 };
46 57
47 cluster1_opp: opp-table-1 { 58 cluster1_opp: opp-table-1 {
48 compatible = "operating-points 59 compatible = "operating-points-v2";
49 opp-shared; 60 opp-shared;
50 opp-800000000 { 61 opp-800000000 {
51 opp-hz = /bits/ 64 <80 62 opp-hz = /bits/ 64 <800000000>;
>> 63 opp-microvolt = <820000>;
52 clock-latency-ns = <30 64 clock-latency-ns = <300000>;
53 }; 65 };
54 opp-1000000000 { 66 opp-1000000000 {
55 opp-hz = /bits/ 64 <10 67 opp-hz = /bits/ 64 <1000000000>;
>> 68 opp-microvolt = <820000>;
56 clock-latency-ns = <30 69 clock-latency-ns = <300000>;
57 }; 70 };
58 opp-1200000000 { 71 opp-1200000000 {
59 opp-hz = /bits/ 64 <12 72 opp-hz = /bits/ 64 <1200000000>;
>> 73 opp-microvolt = <820000>;
60 clock-latency-ns = <30 74 clock-latency-ns = <300000>;
61 opp-suspend; 75 opp-suspend;
62 }; 76 };
63 }; 77 };
64 78
65 cpus { 79 cpus {
66 #address-cells = <1>; 80 #address-cells = <1>;
67 #size-cells = <0>; 81 #size-cells = <0>;
68 82
69 a53_0: cpu@0 { 83 a53_0: cpu@0 {
70 compatible = "arm,cort 84 compatible = "arm,cortex-a53";
71 reg = <0>; 85 reg = <0>;
72 device_type = "cpu"; 86 device_type = "cpu";
73 #cooling-cells = <2>; 87 #cooling-cells = <2>;
74 power-domains = <&sysc 88 power-domains = <&sysc R8A77990_PD_CA53_CPU0>;
75 next-level-cache = <&L 89 next-level-cache = <&L2_CA53>;
76 enable-method = "psci" 90 enable-method = "psci";
77 cpu-idle-states = <&CP 91 cpu-idle-states = <&CPU_SLEEP_0>;
78 dynamic-power-coeffici 92 dynamic-power-coefficient = <277>;
79 clocks = <&cpg CPG_COR !! 93 clocks =<&cpg CPG_CORE R8A77990_CLK_Z2>;
80 operating-points-v2 = 94 operating-points-v2 = <&cluster1_opp>;
81 }; 95 };
82 96
83 a53_1: cpu@1 { 97 a53_1: cpu@1 {
84 compatible = "arm,cort 98 compatible = "arm,cortex-a53";
85 reg = <1>; 99 reg = <1>;
86 device_type = "cpu"; 100 device_type = "cpu";
87 power-domains = <&sysc 101 power-domains = <&sysc R8A77990_PD_CA53_CPU1>;
88 next-level-cache = <&L 102 next-level-cache = <&L2_CA53>;
89 enable-method = "psci" 103 enable-method = "psci";
90 cpu-idle-states = <&CP 104 cpu-idle-states = <&CPU_SLEEP_0>;
91 clocks = <&cpg CPG_COR !! 105 clocks =<&cpg CPG_CORE R8A77990_CLK_Z2>;
92 operating-points-v2 = 106 operating-points-v2 = <&cluster1_opp>;
93 }; 107 };
94 108
95 L2_CA53: cache-controller-0 { 109 L2_CA53: cache-controller-0 {
96 compatible = "cache"; 110 compatible = "cache";
97 power-domains = <&sysc 111 power-domains = <&sysc R8A77990_PD_CA53_SCU>;
98 cache-unified; 112 cache-unified;
99 cache-level = <2>; 113 cache-level = <2>;
100 }; 114 };
101 115
102 idle-states { 116 idle-states {
103 entry-method = "psci"; 117 entry-method = "psci";
104 118
105 CPU_SLEEP_0: cpu-sleep 119 CPU_SLEEP_0: cpu-sleep-0 {
106 compatible = " 120 compatible = "arm,idle-state";
107 arm,psci-suspe 121 arm,psci-suspend-param = <0x0010000>;
108 local-timer-st 122 local-timer-stop;
109 entry-latency- 123 entry-latency-us = <700>;
110 exit-latency-u 124 exit-latency-us = <700>;
111 min-residency- 125 min-residency-us = <5000>;
112 }; 126 };
113 }; 127 };
114 }; 128 };
115 129
116 extal_clk: extal { 130 extal_clk: extal {
117 compatible = "fixed-clock"; 131 compatible = "fixed-clock";
118 #clock-cells = <0>; 132 #clock-cells = <0>;
119 /* This value must be overridd 133 /* This value must be overridden by the board */
120 clock-frequency = <0>; 134 clock-frequency = <0>;
121 }; 135 };
122 136
123 /* External PCIe clock - can be overri 137 /* External PCIe clock - can be overridden by the board */
124 pcie_bus_clk: pcie_bus { 138 pcie_bus_clk: pcie_bus {
125 compatible = "fixed-clock"; 139 compatible = "fixed-clock";
126 #clock-cells = <0>; 140 #clock-cells = <0>;
127 clock-frequency = <0>; 141 clock-frequency = <0>;
128 }; 142 };
129 143
130 pmu_a53 { 144 pmu_a53 {
131 compatible = "arm,cortex-a53-p 145 compatible = "arm,cortex-a53-pmu";
132 interrupts-extended = <&gic GI 146 interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
133 <&gic GI 147 <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
134 interrupt-affinity = <&a53_0>, 148 interrupt-affinity = <&a53_0>, <&a53_1>;
135 }; 149 };
136 150
137 psci { 151 psci {
138 compatible = "arm,psci-1.0", " 152 compatible = "arm,psci-1.0", "arm,psci-0.2";
139 method = "smc"; 153 method = "smc";
140 }; 154 };
141 155
142 /* External SCIF clock - to be overrid 156 /* External SCIF clock - to be overridden by boards that provide it */
143 scif_clk: scif { 157 scif_clk: scif {
144 compatible = "fixed-clock"; 158 compatible = "fixed-clock";
145 #clock-cells = <0>; 159 #clock-cells = <0>;
146 clock-frequency = <0>; 160 clock-frequency = <0>;
147 }; 161 };
148 162
149 soc: soc { 163 soc: soc {
150 compatible = "simple-bus"; 164 compatible = "simple-bus";
151 interrupt-parent = <&gic>; 165 interrupt-parent = <&gic>;
152 #address-cells = <2>; 166 #address-cells = <2>;
153 #size-cells = <2>; 167 #size-cells = <2>;
154 ranges; 168 ranges;
155 169
156 rwdt: watchdog@e6020000 { 170 rwdt: watchdog@e6020000 {
157 compatible = "renesas, 171 compatible = "renesas,r8a77990-wdt",
158 "renesas, 172 "renesas,rcar-gen3-wdt";
159 reg = <0 0xe6020000 0 173 reg = <0 0xe6020000 0 0x0c>;
160 interrupts = <GIC_SPI 174 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
161 clocks = <&cpg CPG_MOD 175 clocks = <&cpg CPG_MOD 402>;
162 power-domains = <&sysc 176 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
163 resets = <&cpg 402>; 177 resets = <&cpg 402>;
164 status = "disabled"; 178 status = "disabled";
165 }; 179 };
166 180
167 gpio0: gpio@e6050000 { 181 gpio0: gpio@e6050000 {
168 compatible = "renesas, 182 compatible = "renesas,gpio-r8a77990",
169 "renesas, 183 "renesas,rcar-gen3-gpio";
170 reg = <0 0xe6050000 0 184 reg = <0 0xe6050000 0 0x50>;
171 interrupts = <GIC_SPI 185 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
172 #gpio-cells = <2>; 186 #gpio-cells = <2>;
173 gpio-controller; 187 gpio-controller;
174 gpio-ranges = <&pfc 0 188 gpio-ranges = <&pfc 0 0 18>;
175 #interrupt-cells = <2> 189 #interrupt-cells = <2>;
176 interrupt-controller; 190 interrupt-controller;
177 clocks = <&cpg CPG_MOD 191 clocks = <&cpg CPG_MOD 912>;
178 power-domains = <&sysc 192 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
179 resets = <&cpg 912>; 193 resets = <&cpg 912>;
180 }; 194 };
181 195
182 gpio1: gpio@e6051000 { 196 gpio1: gpio@e6051000 {
183 compatible = "renesas, 197 compatible = "renesas,gpio-r8a77990",
184 "renesas, 198 "renesas,rcar-gen3-gpio";
185 reg = <0 0xe6051000 0 199 reg = <0 0xe6051000 0 0x50>;
186 interrupts = <GIC_SPI 200 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
187 #gpio-cells = <2>; 201 #gpio-cells = <2>;
188 gpio-controller; 202 gpio-controller;
189 gpio-ranges = <&pfc 0 203 gpio-ranges = <&pfc 0 32 23>;
190 #interrupt-cells = <2> 204 #interrupt-cells = <2>;
191 interrupt-controller; 205 interrupt-controller;
192 clocks = <&cpg CPG_MOD 206 clocks = <&cpg CPG_MOD 911>;
193 power-domains = <&sysc 207 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
194 resets = <&cpg 911>; 208 resets = <&cpg 911>;
195 }; 209 };
196 210
197 gpio2: gpio@e6052000 { 211 gpio2: gpio@e6052000 {
198 compatible = "renesas, 212 compatible = "renesas,gpio-r8a77990",
199 "renesas, 213 "renesas,rcar-gen3-gpio";
200 reg = <0 0xe6052000 0 214 reg = <0 0xe6052000 0 0x50>;
201 interrupts = <GIC_SPI 215 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
202 #gpio-cells = <2>; 216 #gpio-cells = <2>;
203 gpio-controller; 217 gpio-controller;
204 gpio-ranges = <&pfc 0 218 gpio-ranges = <&pfc 0 64 26>;
205 #interrupt-cells = <2> 219 #interrupt-cells = <2>;
206 interrupt-controller; 220 interrupt-controller;
207 clocks = <&cpg CPG_MOD 221 clocks = <&cpg CPG_MOD 910>;
208 power-domains = <&sysc 222 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
209 resets = <&cpg 910>; 223 resets = <&cpg 910>;
210 }; 224 };
211 225
212 gpio3: gpio@e6053000 { 226 gpio3: gpio@e6053000 {
213 compatible = "renesas, 227 compatible = "renesas,gpio-r8a77990",
214 "renesas, 228 "renesas,rcar-gen3-gpio";
215 reg = <0 0xe6053000 0 229 reg = <0 0xe6053000 0 0x50>;
216 interrupts = <GIC_SPI 230 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
217 #gpio-cells = <2>; 231 #gpio-cells = <2>;
218 gpio-controller; 232 gpio-controller;
219 gpio-ranges = <&pfc 0 233 gpio-ranges = <&pfc 0 96 16>;
220 #interrupt-cells = <2> 234 #interrupt-cells = <2>;
221 interrupt-controller; 235 interrupt-controller;
222 clocks = <&cpg CPG_MOD 236 clocks = <&cpg CPG_MOD 909>;
223 power-domains = <&sysc 237 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
224 resets = <&cpg 909>; 238 resets = <&cpg 909>;
225 }; 239 };
226 240
227 gpio4: gpio@e6054000 { 241 gpio4: gpio@e6054000 {
228 compatible = "renesas, 242 compatible = "renesas,gpio-r8a77990",
229 "renesas, 243 "renesas,rcar-gen3-gpio";
230 reg = <0 0xe6054000 0 244 reg = <0 0xe6054000 0 0x50>;
231 interrupts = <GIC_SPI 245 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
232 #gpio-cells = <2>; 246 #gpio-cells = <2>;
233 gpio-controller; 247 gpio-controller;
234 gpio-ranges = <&pfc 0 248 gpio-ranges = <&pfc 0 128 11>;
235 #interrupt-cells = <2> 249 #interrupt-cells = <2>;
236 interrupt-controller; 250 interrupt-controller;
237 clocks = <&cpg CPG_MOD 251 clocks = <&cpg CPG_MOD 908>;
238 power-domains = <&sysc 252 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
239 resets = <&cpg 908>; 253 resets = <&cpg 908>;
240 }; 254 };
241 255
242 gpio5: gpio@e6055000 { 256 gpio5: gpio@e6055000 {
243 compatible = "renesas, 257 compatible = "renesas,gpio-r8a77990",
244 "renesas, 258 "renesas,rcar-gen3-gpio";
245 reg = <0 0xe6055000 0 259 reg = <0 0xe6055000 0 0x50>;
246 interrupts = <GIC_SPI 260 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
247 #gpio-cells = <2>; 261 #gpio-cells = <2>;
248 gpio-controller; 262 gpio-controller;
249 gpio-ranges = <&pfc 0 263 gpio-ranges = <&pfc 0 160 20>;
250 #interrupt-cells = <2> 264 #interrupt-cells = <2>;
251 interrupt-controller; 265 interrupt-controller;
252 clocks = <&cpg CPG_MOD 266 clocks = <&cpg CPG_MOD 907>;
253 power-domains = <&sysc 267 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
254 resets = <&cpg 907>; 268 resets = <&cpg 907>;
255 }; 269 };
256 270
257 gpio6: gpio@e6055400 { 271 gpio6: gpio@e6055400 {
258 compatible = "renesas, 272 compatible = "renesas,gpio-r8a77990",
259 "renesas, 273 "renesas,rcar-gen3-gpio";
260 reg = <0 0xe6055400 0 274 reg = <0 0xe6055400 0 0x50>;
261 interrupts = <GIC_SPI 275 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
262 #gpio-cells = <2>; 276 #gpio-cells = <2>;
263 gpio-controller; 277 gpio-controller;
264 gpio-ranges = <&pfc 0 278 gpio-ranges = <&pfc 0 192 18>;
265 #interrupt-cells = <2> 279 #interrupt-cells = <2>;
266 interrupt-controller; 280 interrupt-controller;
267 clocks = <&cpg CPG_MOD 281 clocks = <&cpg CPG_MOD 906>;
268 power-domains = <&sysc 282 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
269 resets = <&cpg 906>; 283 resets = <&cpg 906>;
270 }; 284 };
271 285
272 pfc: pinctrl@e6060000 { 286 pfc: pinctrl@e6060000 {
273 compatible = "renesas, 287 compatible = "renesas,pfc-r8a77990";
274 reg = <0 0xe6060000 0 288 reg = <0 0xe6060000 0 0x508>;
275 }; 289 };
276 290
277 i2c_dvfs: i2c@e60b0000 { 291 i2c_dvfs: i2c@e60b0000 {
278 #address-cells = <1>; 292 #address-cells = <1>;
279 #size-cells = <0>; 293 #size-cells = <0>;
280 compatible = "renesas, 294 compatible = "renesas,iic-r8a77990",
281 "renesas, 295 "renesas,rcar-gen3-iic",
282 "renesas, 296 "renesas,rmobile-iic";
283 reg = <0 0xe60b0000 0 297 reg = <0 0xe60b0000 0 0x425>;
284 interrupts = <GIC_SPI 298 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
285 clocks = <&cpg CPG_MOD 299 clocks = <&cpg CPG_MOD 926>;
286 power-domains = <&sysc 300 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
287 resets = <&cpg 926>; 301 resets = <&cpg 926>;
288 dmas = <&dmac0 0x11>, 302 dmas = <&dmac0 0x11>, <&dmac0 0x10>;
289 dma-names = "tx", "rx" 303 dma-names = "tx", "rx";
290 status = "disabled"; 304 status = "disabled";
291 }; 305 };
292 306
293 cmt0: timer@e60f0000 { 307 cmt0: timer@e60f0000 {
294 compatible = "renesas, 308 compatible = "renesas,r8a77990-cmt0",
295 "renesas, 309 "renesas,rcar-gen3-cmt0";
296 reg = <0 0xe60f0000 0 310 reg = <0 0xe60f0000 0 0x1004>;
297 interrupts = <GIC_SPI 311 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
298 <GIC_SPI 312 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
299 clocks = <&cpg CPG_MOD 313 clocks = <&cpg CPG_MOD 303>;
300 clock-names = "fck"; 314 clock-names = "fck";
301 power-domains = <&sysc 315 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
302 resets = <&cpg 303>; 316 resets = <&cpg 303>;
303 status = "disabled"; 317 status = "disabled";
304 }; 318 };
305 319
306 cmt1: timer@e6130000 { 320 cmt1: timer@e6130000 {
307 compatible = "renesas, 321 compatible = "renesas,r8a77990-cmt1",
308 "renesas, 322 "renesas,rcar-gen3-cmt1";
309 reg = <0 0xe6130000 0 323 reg = <0 0xe6130000 0 0x1004>;
310 interrupts = <GIC_SPI 324 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
311 <GIC_SPI 325 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
312 <GIC_SPI 326 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
313 <GIC_SPI 327 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
314 <GIC_SPI 328 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
315 <GIC_SPI 329 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
316 <GIC_SPI 330 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
317 <GIC_SPI 331 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
318 clocks = <&cpg CPG_MOD 332 clocks = <&cpg CPG_MOD 302>;
319 clock-names = "fck"; 333 clock-names = "fck";
320 power-domains = <&sysc 334 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
321 resets = <&cpg 302>; 335 resets = <&cpg 302>;
322 status = "disabled"; 336 status = "disabled";
323 }; 337 };
324 338
325 cmt2: timer@e6140000 { 339 cmt2: timer@e6140000 {
326 compatible = "renesas, 340 compatible = "renesas,r8a77990-cmt1",
327 "renesas, 341 "renesas,rcar-gen3-cmt1";
328 reg = <0 0xe6140000 0 342 reg = <0 0xe6140000 0 0x1004>;
329 interrupts = <GIC_SPI 343 interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
330 <GIC_SPI 344 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
331 <GIC_SPI 345 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
332 <GIC_SPI 346 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
333 <GIC_SPI 347 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
334 <GIC_SPI 348 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
335 <GIC_SPI 349 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
336 <GIC_SPI 350 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>;
337 clocks = <&cpg CPG_MOD 351 clocks = <&cpg CPG_MOD 301>;
338 clock-names = "fck"; 352 clock-names = "fck";
339 power-domains = <&sysc 353 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
340 resets = <&cpg 301>; 354 resets = <&cpg 301>;
341 status = "disabled"; 355 status = "disabled";
342 }; 356 };
343 357
344 cmt3: timer@e6148000 { 358 cmt3: timer@e6148000 {
345 compatible = "renesas, 359 compatible = "renesas,r8a77990-cmt1",
346 "renesas, 360 "renesas,rcar-gen3-cmt1";
347 reg = <0 0xe6148000 0 361 reg = <0 0xe6148000 0 0x1004>;
348 interrupts = <GIC_SPI 362 interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>,
349 <GIC_SPI 363 <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>,
350 <GIC_SPI 364 <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>,
351 <GIC_SPI 365 <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>,
352 <GIC_SPI 366 <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>,
353 <GIC_SPI 367 <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>,
354 <GIC_SPI 368 <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>,
355 <GIC_SPI 369 <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>;
356 clocks = <&cpg CPG_MOD 370 clocks = <&cpg CPG_MOD 300>;
357 clock-names = "fck"; 371 clock-names = "fck";
358 power-domains = <&sysc 372 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
359 resets = <&cpg 300>; 373 resets = <&cpg 300>;
360 status = "disabled"; 374 status = "disabled";
361 }; 375 };
362 376
363 cpg: clock-controller@e6150000 377 cpg: clock-controller@e6150000 {
364 compatible = "renesas, 378 compatible = "renesas,r8a77990-cpg-mssr";
365 reg = <0 0xe6150000 0 379 reg = <0 0xe6150000 0 0x1000>;
366 clocks = <&extal_clk>; 380 clocks = <&extal_clk>;
367 clock-names = "extal"; 381 clock-names = "extal";
368 #clock-cells = <2>; 382 #clock-cells = <2>;
369 #power-domain-cells = 383 #power-domain-cells = <0>;
370 #reset-cells = <1>; 384 #reset-cells = <1>;
371 }; 385 };
372 386
373 rst: reset-controller@e6160000 387 rst: reset-controller@e6160000 {
374 compatible = "renesas, 388 compatible = "renesas,r8a77990-rst";
375 reg = <0 0xe6160000 0 389 reg = <0 0xe6160000 0 0x0200>;
376 }; 390 };
377 391
378 sysc: system-controller@e61800 392 sysc: system-controller@e6180000 {
379 compatible = "renesas, 393 compatible = "renesas,r8a77990-sysc";
380 reg = <0 0xe6180000 0 394 reg = <0 0xe6180000 0 0x0400>;
381 #power-domain-cells = 395 #power-domain-cells = <1>;
382 }; 396 };
383 397
384 thermal: thermal@e6190000 { 398 thermal: thermal@e6190000 {
385 compatible = "renesas, 399 compatible = "renesas,thermal-r8a77990";
386 reg = <0 0xe6190000 0 400 reg = <0 0xe6190000 0 0x10>, <0 0xe6190100 0 0x38>;
387 interrupts = <GIC_SPI 401 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
388 <GIC_SPI 402 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
389 <GIC_SPI 403 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
390 clocks = <&cpg CPG_MOD 404 clocks = <&cpg CPG_MOD 522>;
391 power-domains = <&sysc 405 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
392 resets = <&cpg 522>; 406 resets = <&cpg 522>;
393 #thermal-sensor-cells 407 #thermal-sensor-cells = <0>;
394 }; 408 };
395 409
396 intc_ex: interrupt-controller@ 410 intc_ex: interrupt-controller@e61c0000 {
397 compatible = "renesas, 411 compatible = "renesas,intc-ex-r8a77990", "renesas,irqc";
398 #interrupt-cells = <2> 412 #interrupt-cells = <2>;
399 interrupt-controller; 413 interrupt-controller;
400 reg = <0 0xe61c0000 0 414 reg = <0 0xe61c0000 0 0x200>;
401 interrupts = <GIC_SPI 415 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
402 <GIC_SPI 416 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
403 <GIC_SPI 417 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
404 <GIC_SPI 418 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
405 <GIC_SPI 419 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
406 <GIC_SPI 420 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
407 clocks = <&cpg CPG_MOD 421 clocks = <&cpg CPG_MOD 407>;
408 power-domains = <&sysc 422 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
409 resets = <&cpg 407>; 423 resets = <&cpg 407>;
410 }; 424 };
411 425
412 tmu0: timer@e61e0000 { 426 tmu0: timer@e61e0000 {
413 compatible = "renesas, 427 compatible = "renesas,tmu-r8a77990", "renesas,tmu";
414 reg = <0 0xe61e0000 0 428 reg = <0 0xe61e0000 0 0x30>;
415 interrupts = <GIC_SPI 429 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
416 <GIC_SPI 430 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
417 <GIC_SPI 431 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
418 interrupt-names = "tun <<
419 clocks = <&cpg CPG_MOD 432 clocks = <&cpg CPG_MOD 125>;
420 clock-names = "fck"; 433 clock-names = "fck";
421 power-domains = <&sysc 434 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
422 resets = <&cpg 125>; 435 resets = <&cpg 125>;
423 status = "disabled"; 436 status = "disabled";
424 }; 437 };
425 438
426 tmu1: timer@e6fc0000 { 439 tmu1: timer@e6fc0000 {
427 compatible = "renesas, 440 compatible = "renesas,tmu-r8a77990", "renesas,tmu";
428 reg = <0 0xe6fc0000 0 441 reg = <0 0xe6fc0000 0 0x30>;
429 interrupts = <GIC_SPI 442 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
430 <GIC_SPI 443 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
431 <GIC_SPI !! 444 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
432 <GIC_SPI <<
433 interrupt-names = "tun <<
434 clocks = <&cpg CPG_MOD 445 clocks = <&cpg CPG_MOD 124>;
435 clock-names = "fck"; 446 clock-names = "fck";
436 power-domains = <&sysc 447 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
437 resets = <&cpg 124>; 448 resets = <&cpg 124>;
438 status = "disabled"; 449 status = "disabled";
439 }; 450 };
440 451
441 tmu2: timer@e6fd0000 { 452 tmu2: timer@e6fd0000 {
442 compatible = "renesas, 453 compatible = "renesas,tmu-r8a77990", "renesas,tmu";
443 reg = <0 0xe6fd0000 0 454 reg = <0 0xe6fd0000 0 0x30>;
444 interrupts = <GIC_SPI 455 interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>,
445 <GIC_SPI 456 <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
446 <GIC_SPI !! 457 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
447 <GIC_SPI <<
448 interrupt-names = "tun <<
449 clocks = <&cpg CPG_MOD 458 clocks = <&cpg CPG_MOD 123>;
450 clock-names = "fck"; 459 clock-names = "fck";
451 power-domains = <&sysc 460 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
452 resets = <&cpg 123>; 461 resets = <&cpg 123>;
453 status = "disabled"; 462 status = "disabled";
454 }; 463 };
455 464
456 tmu3: timer@e6fe0000 { 465 tmu3: timer@e6fe0000 {
457 compatible = "renesas, 466 compatible = "renesas,tmu-r8a77990", "renesas,tmu";
458 reg = <0 0xe6fe0000 0 467 reg = <0 0xe6fe0000 0 0x30>;
459 interrupts = <GIC_SPI 468 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
460 <GIC_SPI 469 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
461 <GIC_SPI 470 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
462 interrupt-names = "tun <<
463 clocks = <&cpg CPG_MOD 471 clocks = <&cpg CPG_MOD 122>;
464 clock-names = "fck"; 472 clock-names = "fck";
465 power-domains = <&sysc 473 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
466 resets = <&cpg 122>; 474 resets = <&cpg 122>;
467 status = "disabled"; 475 status = "disabled";
468 }; 476 };
469 477
470 tmu4: timer@ffc00000 { 478 tmu4: timer@ffc00000 {
471 compatible = "renesas, 479 compatible = "renesas,tmu-r8a77990", "renesas,tmu";
472 reg = <0 0xffc00000 0 480 reg = <0 0xffc00000 0 0x30>;
473 interrupts = <GIC_SPI 481 interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
474 <GIC_SPI 482 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
475 <GIC_SPI 483 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>;
476 interrupt-names = "tun <<
477 clocks = <&cpg CPG_MOD 484 clocks = <&cpg CPG_MOD 121>;
478 clock-names = "fck"; 485 clock-names = "fck";
479 power-domains = <&sysc 486 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
480 resets = <&cpg 121>; 487 resets = <&cpg 121>;
481 status = "disabled"; 488 status = "disabled";
482 }; 489 };
483 490
484 i2c0: i2c@e6500000 { 491 i2c0: i2c@e6500000 {
485 #address-cells = <1>; 492 #address-cells = <1>;
486 #size-cells = <0>; 493 #size-cells = <0>;
487 compatible = "renesas, 494 compatible = "renesas,i2c-r8a77990",
488 "renesas, 495 "renesas,rcar-gen3-i2c";
489 reg = <0 0xe6500000 0 496 reg = <0 0xe6500000 0 0x40>;
490 interrupts = <GIC_SPI 497 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
491 clocks = <&cpg CPG_MOD 498 clocks = <&cpg CPG_MOD 931>;
492 power-domains = <&sysc 499 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
493 resets = <&cpg 931>; 500 resets = <&cpg 931>;
494 dmas = <&dmac1 0x91>, 501 dmas = <&dmac1 0x91>, <&dmac1 0x90>,
495 <&dmac2 0x91>, 502 <&dmac2 0x91>, <&dmac2 0x90>;
496 dma-names = "tx", "rx" 503 dma-names = "tx", "rx", "tx", "rx";
497 i2c-scl-internal-delay 504 i2c-scl-internal-delay-ns = <110>;
498 status = "disabled"; 505 status = "disabled";
499 }; 506 };
500 507
501 i2c1: i2c@e6508000 { 508 i2c1: i2c@e6508000 {
502 #address-cells = <1>; 509 #address-cells = <1>;
503 #size-cells = <0>; 510 #size-cells = <0>;
504 compatible = "renesas, 511 compatible = "renesas,i2c-r8a77990",
505 "renesas, 512 "renesas,rcar-gen3-i2c";
506 reg = <0 0xe6508000 0 513 reg = <0 0xe6508000 0 0x40>;
507 interrupts = <GIC_SPI 514 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
508 clocks = <&cpg CPG_MOD 515 clocks = <&cpg CPG_MOD 930>;
509 power-domains = <&sysc 516 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
510 resets = <&cpg 930>; 517 resets = <&cpg 930>;
511 dmas = <&dmac1 0x93>, 518 dmas = <&dmac1 0x93>, <&dmac1 0x92>,
512 <&dmac2 0x93>, 519 <&dmac2 0x93>, <&dmac2 0x92>;
513 dma-names = "tx", "rx" 520 dma-names = "tx", "rx", "tx", "rx";
514 i2c-scl-internal-delay 521 i2c-scl-internal-delay-ns = <6>;
515 status = "disabled"; 522 status = "disabled";
516 }; 523 };
517 524
518 i2c2: i2c@e6510000 { 525 i2c2: i2c@e6510000 {
519 #address-cells = <1>; 526 #address-cells = <1>;
520 #size-cells = <0>; 527 #size-cells = <0>;
521 compatible = "renesas, 528 compatible = "renesas,i2c-r8a77990",
522 "renesas, 529 "renesas,rcar-gen3-i2c";
523 reg = <0 0xe6510000 0 530 reg = <0 0xe6510000 0 0x40>;
524 interrupts = <GIC_SPI 531 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
525 clocks = <&cpg CPG_MOD 532 clocks = <&cpg CPG_MOD 929>;
526 power-domains = <&sysc 533 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
527 resets = <&cpg 929>; 534 resets = <&cpg 929>;
528 dmas = <&dmac1 0x95>, 535 dmas = <&dmac1 0x95>, <&dmac1 0x94>,
529 <&dmac2 0x95>, 536 <&dmac2 0x95>, <&dmac2 0x94>;
530 dma-names = "tx", "rx" 537 dma-names = "tx", "rx", "tx", "rx";
531 i2c-scl-internal-delay 538 i2c-scl-internal-delay-ns = <6>;
532 status = "disabled"; 539 status = "disabled";
533 }; 540 };
534 541
535 i2c3: i2c@e66d0000 { 542 i2c3: i2c@e66d0000 {
536 #address-cells = <1>; 543 #address-cells = <1>;
537 #size-cells = <0>; 544 #size-cells = <0>;
538 compatible = "renesas, 545 compatible = "renesas,i2c-r8a77990",
539 "renesas, 546 "renesas,rcar-gen3-i2c";
540 reg = <0 0xe66d0000 0 547 reg = <0 0xe66d0000 0 0x40>;
541 interrupts = <GIC_SPI 548 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
542 clocks = <&cpg CPG_MOD 549 clocks = <&cpg CPG_MOD 928>;
543 power-domains = <&sysc 550 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
544 resets = <&cpg 928>; 551 resets = <&cpg 928>;
545 dmas = <&dmac0 0x97>, 552 dmas = <&dmac0 0x97>, <&dmac0 0x96>;
546 dma-names = "tx", "rx" 553 dma-names = "tx", "rx";
547 i2c-scl-internal-delay 554 i2c-scl-internal-delay-ns = <110>;
548 status = "disabled"; 555 status = "disabled";
549 }; 556 };
550 557
551 i2c4: i2c@e66d8000 { 558 i2c4: i2c@e66d8000 {
552 #address-cells = <1>; 559 #address-cells = <1>;
553 #size-cells = <0>; 560 #size-cells = <0>;
554 compatible = "renesas, 561 compatible = "renesas,i2c-r8a77990",
555 "renesas, 562 "renesas,rcar-gen3-i2c";
556 reg = <0 0xe66d8000 0 563 reg = <0 0xe66d8000 0 0x40>;
557 interrupts = <GIC_SPI 564 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
558 clocks = <&cpg CPG_MOD 565 clocks = <&cpg CPG_MOD 927>;
559 power-domains = <&sysc 566 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
560 resets = <&cpg 927>; 567 resets = <&cpg 927>;
561 dmas = <&dmac0 0x99>, 568 dmas = <&dmac0 0x99>, <&dmac0 0x98>;
562 dma-names = "tx", "rx" 569 dma-names = "tx", "rx";
563 i2c-scl-internal-delay 570 i2c-scl-internal-delay-ns = <6>;
564 status = "disabled"; 571 status = "disabled";
565 }; 572 };
566 573
567 i2c5: i2c@e66e0000 { 574 i2c5: i2c@e66e0000 {
568 #address-cells = <1>; 575 #address-cells = <1>;
569 #size-cells = <0>; 576 #size-cells = <0>;
570 compatible = "renesas, 577 compatible = "renesas,i2c-r8a77990",
571 "renesas, 578 "renesas,rcar-gen3-i2c";
572 reg = <0 0xe66e0000 0 579 reg = <0 0xe66e0000 0 0x40>;
573 interrupts = <GIC_SPI 580 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
574 clocks = <&cpg CPG_MOD 581 clocks = <&cpg CPG_MOD 919>;
575 power-domains = <&sysc 582 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
576 resets = <&cpg 919>; 583 resets = <&cpg 919>;
577 dmas = <&dmac0 0x9b>, 584 dmas = <&dmac0 0x9b>, <&dmac0 0x9a>;
578 dma-names = "tx", "rx" 585 dma-names = "tx", "rx";
579 i2c-scl-internal-delay 586 i2c-scl-internal-delay-ns = <6>;
580 status = "disabled"; 587 status = "disabled";
581 }; 588 };
582 589
583 i2c6: i2c@e66e8000 { 590 i2c6: i2c@e66e8000 {
584 #address-cells = <1>; 591 #address-cells = <1>;
585 #size-cells = <0>; 592 #size-cells = <0>;
586 compatible = "renesas, 593 compatible = "renesas,i2c-r8a77990",
587 "renesas, 594 "renesas,rcar-gen3-i2c";
588 reg = <0 0xe66e8000 0 595 reg = <0 0xe66e8000 0 0x40>;
589 interrupts = <GIC_SPI 596 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
590 clocks = <&cpg CPG_MOD 597 clocks = <&cpg CPG_MOD 918>;
591 power-domains = <&sysc 598 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
592 resets = <&cpg 918>; 599 resets = <&cpg 918>;
593 dmas = <&dmac0 0x9d>, 600 dmas = <&dmac0 0x9d>, <&dmac0 0x9c>;
594 dma-names = "tx", "rx" 601 dma-names = "tx", "rx";
595 i2c-scl-internal-delay 602 i2c-scl-internal-delay-ns = <6>;
596 status = "disabled"; 603 status = "disabled";
597 }; 604 };
598 605
599 i2c7: i2c@e6690000 { 606 i2c7: i2c@e6690000 {
600 #address-cells = <1>; 607 #address-cells = <1>;
601 #size-cells = <0>; 608 #size-cells = <0>;
602 compatible = "renesas, 609 compatible = "renesas,i2c-r8a77990",
603 "renesas, 610 "renesas,rcar-gen3-i2c";
604 reg = <0 0xe6690000 0 611 reg = <0 0xe6690000 0 0x40>;
605 interrupts = <GIC_SPI 612 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
606 clocks = <&cpg CPG_MOD 613 clocks = <&cpg CPG_MOD 1003>;
607 power-domains = <&sysc 614 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
608 resets = <&cpg 1003>; 615 resets = <&cpg 1003>;
609 i2c-scl-internal-delay 616 i2c-scl-internal-delay-ns = <6>;
610 status = "disabled"; 617 status = "disabled";
611 }; 618 };
612 619
613 hscif0: serial@e6540000 { 620 hscif0: serial@e6540000 {
614 compatible = "renesas, 621 compatible = "renesas,hscif-r8a77990",
615 "renesas, 622 "renesas,rcar-gen3-hscif",
616 "renesas, 623 "renesas,hscif";
617 reg = <0 0xe6540000 0 624 reg = <0 0xe6540000 0 0x60>;
618 interrupts = <GIC_SPI 625 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
619 clocks = <&cpg CPG_MOD 626 clocks = <&cpg CPG_MOD 520>,
620 <&cpg CPG_COR 627 <&cpg CPG_CORE R8A77990_CLK_S3D1C>,
621 <&scif_clk>; 628 <&scif_clk>;
622 clock-names = "fck", " 629 clock-names = "fck", "brg_int", "scif_clk";
623 dmas = <&dmac1 0x31>, 630 dmas = <&dmac1 0x31>, <&dmac1 0x30>,
624 <&dmac2 0x31>, 631 <&dmac2 0x31>, <&dmac2 0x30>;
625 dma-names = "tx", "rx" 632 dma-names = "tx", "rx", "tx", "rx";
626 power-domains = <&sysc 633 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
627 resets = <&cpg 520>; 634 resets = <&cpg 520>;
628 status = "disabled"; 635 status = "disabled";
629 }; 636 };
630 637
631 hscif1: serial@e6550000 { 638 hscif1: serial@e6550000 {
632 compatible = "renesas, 639 compatible = "renesas,hscif-r8a77990",
633 "renesas, 640 "renesas,rcar-gen3-hscif",
634 "renesas, 641 "renesas,hscif";
635 reg = <0 0xe6550000 0 642 reg = <0 0xe6550000 0 0x60>;
636 interrupts = <GIC_SPI 643 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
637 clocks = <&cpg CPG_MOD 644 clocks = <&cpg CPG_MOD 519>,
638 <&cpg CPG_COR 645 <&cpg CPG_CORE R8A77990_CLK_S3D1C>,
639 <&scif_clk>; 646 <&scif_clk>;
640 clock-names = "fck", " 647 clock-names = "fck", "brg_int", "scif_clk";
641 dmas = <&dmac1 0x33>, 648 dmas = <&dmac1 0x33>, <&dmac1 0x32>,
642 <&dmac2 0x33>, 649 <&dmac2 0x33>, <&dmac2 0x32>;
643 dma-names = "tx", "rx" 650 dma-names = "tx", "rx", "tx", "rx";
644 power-domains = <&sysc 651 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
645 resets = <&cpg 519>; 652 resets = <&cpg 519>;
646 status = "disabled"; 653 status = "disabled";
647 }; 654 };
648 655
649 hscif2: serial@e6560000 { 656 hscif2: serial@e6560000 {
650 compatible = "renesas, 657 compatible = "renesas,hscif-r8a77990",
651 "renesas, 658 "renesas,rcar-gen3-hscif",
652 "renesas, 659 "renesas,hscif";
653 reg = <0 0xe6560000 0 660 reg = <0 0xe6560000 0 0x60>;
654 interrupts = <GIC_SPI 661 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
655 clocks = <&cpg CPG_MOD 662 clocks = <&cpg CPG_MOD 518>,
656 <&cpg CPG_COR 663 <&cpg CPG_CORE R8A77990_CLK_S3D1C>,
657 <&scif_clk>; 664 <&scif_clk>;
658 clock-names = "fck", " 665 clock-names = "fck", "brg_int", "scif_clk";
659 dmas = <&dmac1 0x35>, 666 dmas = <&dmac1 0x35>, <&dmac1 0x34>,
660 <&dmac2 0x35>, 667 <&dmac2 0x35>, <&dmac2 0x34>;
661 dma-names = "tx", "rx" 668 dma-names = "tx", "rx", "tx", "rx";
662 power-domains = <&sysc 669 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
663 resets = <&cpg 518>; 670 resets = <&cpg 518>;
664 status = "disabled"; 671 status = "disabled";
665 }; 672 };
666 673
667 hscif3: serial@e66a0000 { 674 hscif3: serial@e66a0000 {
668 compatible = "renesas, 675 compatible = "renesas,hscif-r8a77990",
669 "renesas, 676 "renesas,rcar-gen3-hscif",
670 "renesas, 677 "renesas,hscif";
671 reg = <0 0xe66a0000 0 678 reg = <0 0xe66a0000 0 0x60>;
672 interrupts = <GIC_SPI 679 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
673 clocks = <&cpg CPG_MOD 680 clocks = <&cpg CPG_MOD 517>,
674 <&cpg CPG_COR 681 <&cpg CPG_CORE R8A77990_CLK_S3D1C>,
675 <&scif_clk>; 682 <&scif_clk>;
676 clock-names = "fck", " 683 clock-names = "fck", "brg_int", "scif_clk";
677 dmas = <&dmac0 0x37>, 684 dmas = <&dmac0 0x37>, <&dmac0 0x36>;
678 dma-names = "tx", "rx" 685 dma-names = "tx", "rx";
679 power-domains = <&sysc 686 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
680 resets = <&cpg 517>; 687 resets = <&cpg 517>;
681 status = "disabled"; 688 status = "disabled";
682 }; 689 };
683 690
684 hscif4: serial@e66b0000 { 691 hscif4: serial@e66b0000 {
685 compatible = "renesas, 692 compatible = "renesas,hscif-r8a77990",
686 "renesas, 693 "renesas,rcar-gen3-hscif",
687 "renesas, 694 "renesas,hscif";
688 reg = <0 0xe66b0000 0 695 reg = <0 0xe66b0000 0 0x60>;
689 interrupts = <GIC_SPI 696 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
690 clocks = <&cpg CPG_MOD 697 clocks = <&cpg CPG_MOD 516>,
691 <&cpg CPG_COR 698 <&cpg CPG_CORE R8A77990_CLK_S3D1C>,
692 <&scif_clk>; 699 <&scif_clk>;
693 clock-names = "fck", " 700 clock-names = "fck", "brg_int", "scif_clk";
694 dmas = <&dmac0 0x39>, 701 dmas = <&dmac0 0x39>, <&dmac0 0x38>;
695 dma-names = "tx", "rx" 702 dma-names = "tx", "rx";
696 power-domains = <&sysc 703 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
697 resets = <&cpg 516>; 704 resets = <&cpg 516>;
698 status = "disabled"; 705 status = "disabled";
699 }; 706 };
700 707
701 hsusb: usb@e6590000 { 708 hsusb: usb@e6590000 {
702 compatible = "renesas, 709 compatible = "renesas,usbhs-r8a77990",
703 "renesas, 710 "renesas,rcar-gen3-usbhs";
704 reg = <0 0xe6590000 0 711 reg = <0 0xe6590000 0 0x200>;
705 interrupts = <GIC_SPI 712 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
706 clocks = <&cpg CPG_MOD 713 clocks = <&cpg CPG_MOD 704>, <&cpg CPG_MOD 703>;
707 dmas = <&usb_dmac0 0>, 714 dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
708 <&usb_dmac1 0>, 715 <&usb_dmac1 0>, <&usb_dmac1 1>;
709 dma-names = "ch0", "ch 716 dma-names = "ch0", "ch1", "ch2", "ch3";
710 renesas,buswait = <11> 717 renesas,buswait = <11>;
711 phys = <&usb2_phy0 3>; 718 phys = <&usb2_phy0 3>;
712 phy-names = "usb"; 719 phy-names = "usb";
713 power-domains = <&sysc 720 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
714 resets = <&cpg 704>, < 721 resets = <&cpg 704>, <&cpg 703>;
715 status = "disabled"; 722 status = "disabled";
716 }; 723 };
717 724
718 usb_dmac0: dma-controller@e65a 725 usb_dmac0: dma-controller@e65a0000 {
719 compatible = "renesas, 726 compatible = "renesas,r8a77990-usb-dmac",
720 "renesas, 727 "renesas,usb-dmac";
721 reg = <0 0xe65a0000 0 728 reg = <0 0xe65a0000 0 0x100>;
722 interrupts = <GIC_SPI 729 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
723 <GIC_SPI 730 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
724 interrupt-names = "ch0 731 interrupt-names = "ch0", "ch1";
725 clocks = <&cpg CPG_MOD 732 clocks = <&cpg CPG_MOD 330>;
726 power-domains = <&sysc 733 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
727 resets = <&cpg 330>; 734 resets = <&cpg 330>;
728 #dma-cells = <1>; 735 #dma-cells = <1>;
729 dma-channels = <2>; 736 dma-channels = <2>;
730 }; 737 };
731 738
732 usb_dmac1: dma-controller@e65b 739 usb_dmac1: dma-controller@e65b0000 {
733 compatible = "renesas, 740 compatible = "renesas,r8a77990-usb-dmac",
734 "renesas, 741 "renesas,usb-dmac";
735 reg = <0 0xe65b0000 0 742 reg = <0 0xe65b0000 0 0x100>;
736 interrupts = <GIC_SPI 743 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
737 <GIC_SPI 744 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
738 interrupt-names = "ch0 745 interrupt-names = "ch0", "ch1";
739 clocks = <&cpg CPG_MOD 746 clocks = <&cpg CPG_MOD 331>;
740 power-domains = <&sysc 747 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
741 resets = <&cpg 331>; 748 resets = <&cpg 331>;
742 #dma-cells = <1>; 749 #dma-cells = <1>;
743 dma-channels = <2>; 750 dma-channels = <2>;
744 }; 751 };
745 752
746 arm_cc630p: crypto@e6601000 { 753 arm_cc630p: crypto@e6601000 {
747 compatible = "arm,cryp 754 compatible = "arm,cryptocell-630p-ree";
748 interrupts = <GIC_SPI 755 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
749 reg = <0x0 0xe6601000 756 reg = <0x0 0xe6601000 0 0x1000>;
750 clocks = <&cpg CPG_MOD 757 clocks = <&cpg CPG_MOD 229>;
751 resets = <&cpg 229>; 758 resets = <&cpg 229>;
752 power-domains = <&sysc 759 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
753 }; 760 };
754 761
755 dmac0: dma-controller@e6700000 762 dmac0: dma-controller@e6700000 {
756 compatible = "renesas, 763 compatible = "renesas,dmac-r8a77990",
757 "renesas, 764 "renesas,rcar-dmac";
758 reg = <0 0xe6700000 0 765 reg = <0 0xe6700000 0 0x10000>;
759 interrupts = <GIC_SPI 766 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
760 <GIC_SPI 767 <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
761 <GIC_SPI 768 <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
762 <GIC_SPI 769 <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
763 <GIC_SPI 770 <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
764 <GIC_SPI 771 <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
765 <GIC_SPI 772 <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
766 <GIC_SPI 773 <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
767 <GIC_SPI 774 <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
768 <GIC_SPI 775 <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
769 <GIC_SPI 776 <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>,
770 <GIC_SPI 777 <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
771 <GIC_SPI 778 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
772 <GIC_SPI 779 <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
773 <GIC_SPI 780 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
774 <GIC_SPI 781 <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
775 <GIC_SPI 782 <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>;
776 interrupt-names = "err 783 interrupt-names = "error",
777 "ch0", 784 "ch0", "ch1", "ch2", "ch3",
778 "ch4", 785 "ch4", "ch5", "ch6", "ch7",
779 "ch8", 786 "ch8", "ch9", "ch10", "ch11",
780 "ch12" 787 "ch12", "ch13", "ch14", "ch15";
781 clocks = <&cpg CPG_MOD 788 clocks = <&cpg CPG_MOD 219>;
782 clock-names = "fck"; 789 clock-names = "fck";
783 power-domains = <&sysc 790 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
784 resets = <&cpg 219>; 791 resets = <&cpg 219>;
785 #dma-cells = <1>; 792 #dma-cells = <1>;
786 dma-channels = <16>; 793 dma-channels = <16>;
787 iommus = <&ipmmu_ds0 0 794 iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>,
788 <&ipmmu_ds0 2>, 795 <&ipmmu_ds0 2>, <&ipmmu_ds0 3>,
789 <&ipmmu_ds0 4>, 796 <&ipmmu_ds0 4>, <&ipmmu_ds0 5>,
790 <&ipmmu_ds0 6>, 797 <&ipmmu_ds0 6>, <&ipmmu_ds0 7>,
791 <&ipmmu_ds0 8>, 798 <&ipmmu_ds0 8>, <&ipmmu_ds0 9>,
792 <&ipmmu_ds0 10> 799 <&ipmmu_ds0 10>, <&ipmmu_ds0 11>,
793 <&ipmmu_ds0 12> 800 <&ipmmu_ds0 12>, <&ipmmu_ds0 13>,
794 <&ipmmu_ds0 14> 801 <&ipmmu_ds0 14>, <&ipmmu_ds0 15>;
795 }; 802 };
796 803
797 dmac1: dma-controller@e7300000 804 dmac1: dma-controller@e7300000 {
798 compatible = "renesas, 805 compatible = "renesas,dmac-r8a77990",
799 "renesas, 806 "renesas,rcar-dmac";
800 reg = <0 0xe7300000 0 807 reg = <0 0xe7300000 0 0x10000>;
801 interrupts = <GIC_SPI 808 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
802 <GIC_SPI 809 <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
803 <GIC_SPI 810 <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
804 <GIC_SPI 811 <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
805 <GIC_SPI 812 <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
806 <GIC_SPI 813 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
807 <GIC_SPI 814 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
808 <GIC_SPI 815 <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
809 <GIC_SPI 816 <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>,
810 <GIC_SPI 817 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
811 <GIC_SPI 818 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
812 <GIC_SPI 819 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
813 <GIC_SPI 820 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
814 <GIC_SPI 821 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
815 <GIC_SPI 822 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
816 <GIC_SPI 823 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
817 <GIC_SPI 824 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>;
818 interrupt-names = "err 825 interrupt-names = "error",
819 "ch0", 826 "ch0", "ch1", "ch2", "ch3",
820 "ch4", 827 "ch4", "ch5", "ch6", "ch7",
821 "ch8", 828 "ch8", "ch9", "ch10", "ch11",
822 "ch12" 829 "ch12", "ch13", "ch14", "ch15";
823 clocks = <&cpg CPG_MOD 830 clocks = <&cpg CPG_MOD 218>;
824 clock-names = "fck"; 831 clock-names = "fck";
825 power-domains = <&sysc 832 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
826 resets = <&cpg 218>; 833 resets = <&cpg 218>;
827 #dma-cells = <1>; 834 #dma-cells = <1>;
828 dma-channels = <16>; 835 dma-channels = <16>;
829 iommus = <&ipmmu_ds1 0 836 iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>,
830 <&ipmmu_ds1 2>, 837 <&ipmmu_ds1 2>, <&ipmmu_ds1 3>,
831 <&ipmmu_ds1 4>, 838 <&ipmmu_ds1 4>, <&ipmmu_ds1 5>,
832 <&ipmmu_ds1 6>, 839 <&ipmmu_ds1 6>, <&ipmmu_ds1 7>,
833 <&ipmmu_ds1 8>, 840 <&ipmmu_ds1 8>, <&ipmmu_ds1 9>,
834 <&ipmmu_ds1 10> 841 <&ipmmu_ds1 10>, <&ipmmu_ds1 11>,
835 <&ipmmu_ds1 12> 842 <&ipmmu_ds1 12>, <&ipmmu_ds1 13>,
836 <&ipmmu_ds1 14> 843 <&ipmmu_ds1 14>, <&ipmmu_ds1 15>;
837 }; 844 };
838 845
839 dmac2: dma-controller@e7310000 846 dmac2: dma-controller@e7310000 {
840 compatible = "renesas, 847 compatible = "renesas,dmac-r8a77990",
841 "renesas, 848 "renesas,rcar-dmac";
842 reg = <0 0xe7310000 0 849 reg = <0 0xe7310000 0 0x10000>;
843 interrupts = <GIC_SPI 850 interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
844 <GIC_SPI 851 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
845 <GIC_SPI 852 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
846 <GIC_SPI 853 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
847 <GIC_SPI 854 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
848 <GIC_SPI 855 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
849 <GIC_SPI 856 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
850 <GIC_SPI 857 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
851 <GIC_SPI 858 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
852 <GIC_SPI 859 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
853 <GIC_SPI 860 <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>,
854 <GIC_SPI 861 <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>,
855 <GIC_SPI 862 <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>,
856 <GIC_SPI 863 <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>,
857 <GIC_SPI 864 <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>,
858 <GIC_SPI 865 <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH>,
859 <GIC_SPI 866 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>;
860 interrupt-names = "err 867 interrupt-names = "error",
861 "ch0", 868 "ch0", "ch1", "ch2", "ch3",
862 "ch4", 869 "ch4", "ch5", "ch6", "ch7",
863 "ch8", 870 "ch8", "ch9", "ch10", "ch11",
864 "ch12" 871 "ch12", "ch13", "ch14", "ch15";
865 clocks = <&cpg CPG_MOD 872 clocks = <&cpg CPG_MOD 217>;
866 clock-names = "fck"; 873 clock-names = "fck";
867 power-domains = <&sysc 874 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
868 resets = <&cpg 217>; 875 resets = <&cpg 217>;
869 #dma-cells = <1>; 876 #dma-cells = <1>;
870 dma-channels = <16>; 877 dma-channels = <16>;
871 iommus = <&ipmmu_ds1 1 878 iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>,
872 <&ipmmu_ds1 18> 879 <&ipmmu_ds1 18>, <&ipmmu_ds1 19>,
873 <&ipmmu_ds1 20> 880 <&ipmmu_ds1 20>, <&ipmmu_ds1 21>,
874 <&ipmmu_ds1 22> 881 <&ipmmu_ds1 22>, <&ipmmu_ds1 23>,
875 <&ipmmu_ds1 24> 882 <&ipmmu_ds1 24>, <&ipmmu_ds1 25>,
876 <&ipmmu_ds1 26> 883 <&ipmmu_ds1 26>, <&ipmmu_ds1 27>,
877 <&ipmmu_ds1 28> 884 <&ipmmu_ds1 28>, <&ipmmu_ds1 29>,
878 <&ipmmu_ds1 30> 885 <&ipmmu_ds1 30>, <&ipmmu_ds1 31>;
879 }; 886 };
880 887
881 ipmmu_ds0: iommu@e6740000 { 888 ipmmu_ds0: iommu@e6740000 {
882 compatible = "renesas, 889 compatible = "renesas,ipmmu-r8a77990";
883 reg = <0 0xe6740000 0 890 reg = <0 0xe6740000 0 0x1000>;
884 renesas,ipmmu-main = < 891 renesas,ipmmu-main = <&ipmmu_mm 0>;
885 power-domains = <&sysc 892 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
886 #iommu-cells = <1>; 893 #iommu-cells = <1>;
887 }; 894 };
888 895
889 ipmmu_ds1: iommu@e7740000 { 896 ipmmu_ds1: iommu@e7740000 {
890 compatible = "renesas, 897 compatible = "renesas,ipmmu-r8a77990";
891 reg = <0 0xe7740000 0 898 reg = <0 0xe7740000 0 0x1000>;
892 renesas,ipmmu-main = < 899 renesas,ipmmu-main = <&ipmmu_mm 1>;
893 power-domains = <&sysc 900 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
894 #iommu-cells = <1>; 901 #iommu-cells = <1>;
895 }; 902 };
896 903
897 ipmmu_hc: iommu@e6570000 { 904 ipmmu_hc: iommu@e6570000 {
898 compatible = "renesas, 905 compatible = "renesas,ipmmu-r8a77990";
899 reg = <0 0xe6570000 0 906 reg = <0 0xe6570000 0 0x1000>;
900 renesas,ipmmu-main = < 907 renesas,ipmmu-main = <&ipmmu_mm 2>;
901 power-domains = <&sysc 908 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
902 #iommu-cells = <1>; 909 #iommu-cells = <1>;
903 }; 910 };
904 911
905 ipmmu_mm: iommu@e67b0000 { 912 ipmmu_mm: iommu@e67b0000 {
906 compatible = "renesas, 913 compatible = "renesas,ipmmu-r8a77990";
907 reg = <0 0xe67b0000 0 914 reg = <0 0xe67b0000 0 0x1000>;
908 interrupts = <GIC_SPI 915 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
909 <GIC_SPI 916 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
910 power-domains = <&sysc 917 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
911 #iommu-cells = <1>; 918 #iommu-cells = <1>;
912 }; 919 };
913 920
914 ipmmu_mp: iommu@ec670000 { 921 ipmmu_mp: iommu@ec670000 {
915 compatible = "renesas, 922 compatible = "renesas,ipmmu-r8a77990";
916 reg = <0 0xec670000 0 923 reg = <0 0xec670000 0 0x1000>;
917 renesas,ipmmu-main = < 924 renesas,ipmmu-main = <&ipmmu_mm 4>;
918 power-domains = <&sysc 925 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
919 #iommu-cells = <1>; 926 #iommu-cells = <1>;
920 }; 927 };
921 928
922 ipmmu_pv0: iommu@fd800000 { 929 ipmmu_pv0: iommu@fd800000 {
923 compatible = "renesas, 930 compatible = "renesas,ipmmu-r8a77990";
924 reg = <0 0xfd800000 0 931 reg = <0 0xfd800000 0 0x1000>;
925 renesas,ipmmu-main = < 932 renesas,ipmmu-main = <&ipmmu_mm 6>;
926 power-domains = <&sysc 933 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
927 #iommu-cells = <1>; 934 #iommu-cells = <1>;
928 }; 935 };
929 936
930 ipmmu_rt: iommu@ffc80000 { 937 ipmmu_rt: iommu@ffc80000 {
931 compatible = "renesas, 938 compatible = "renesas,ipmmu-r8a77990";
932 reg = <0 0xffc80000 0 939 reg = <0 0xffc80000 0 0x1000>;
933 renesas,ipmmu-main = < 940 renesas,ipmmu-main = <&ipmmu_mm 10>;
934 power-domains = <&sysc 941 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
935 #iommu-cells = <1>; 942 #iommu-cells = <1>;
936 }; 943 };
937 944
938 ipmmu_vc0: iommu@fe6b0000 { 945 ipmmu_vc0: iommu@fe6b0000 {
939 compatible = "renesas, 946 compatible = "renesas,ipmmu-r8a77990";
940 reg = <0 0xfe6b0000 0 947 reg = <0 0xfe6b0000 0 0x1000>;
941 renesas,ipmmu-main = < 948 renesas,ipmmu-main = <&ipmmu_mm 12>;
942 power-domains = <&sysc 949 power-domains = <&sysc R8A77990_PD_A3VC>;
943 #iommu-cells = <1>; 950 #iommu-cells = <1>;
944 }; 951 };
945 952
946 ipmmu_vi0: iommu@febd0000 { 953 ipmmu_vi0: iommu@febd0000 {
947 compatible = "renesas, 954 compatible = "renesas,ipmmu-r8a77990";
948 reg = <0 0xfebd0000 0 955 reg = <0 0xfebd0000 0 0x1000>;
949 renesas,ipmmu-main = < 956 renesas,ipmmu-main = <&ipmmu_mm 14>;
950 power-domains = <&sysc 957 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
951 #iommu-cells = <1>; 958 #iommu-cells = <1>;
952 }; 959 };
953 960
954 ipmmu_vp0: iommu@fe990000 { 961 ipmmu_vp0: iommu@fe990000 {
955 compatible = "renesas, 962 compatible = "renesas,ipmmu-r8a77990";
956 reg = <0 0xfe990000 0 963 reg = <0 0xfe990000 0 0x1000>;
957 renesas,ipmmu-main = < 964 renesas,ipmmu-main = <&ipmmu_mm 16>;
958 power-domains = <&sysc 965 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
959 #iommu-cells = <1>; 966 #iommu-cells = <1>;
960 }; 967 };
961 968
962 avb: ethernet@e6800000 { 969 avb: ethernet@e6800000 {
963 compatible = "renesas, 970 compatible = "renesas,etheravb-r8a77990",
964 "renesas, 971 "renesas,etheravb-rcar-gen3";
965 reg = <0 0xe6800000 0 972 reg = <0 0xe6800000 0 0x800>;
966 interrupts = <GIC_SPI 973 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
967 <GIC_SPI 974 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
968 <GIC_SPI 975 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
969 <GIC_SPI 976 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
970 <GIC_SPI 977 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
971 <GIC_SPI 978 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
972 <GIC_SPI 979 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
973 <GIC_SPI 980 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
974 <GIC_SPI 981 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
975 <GIC_SPI 982 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
976 <GIC_SPI 983 <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
977 <GIC_SPI 984 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
978 <GIC_SPI 985 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
979 <GIC_SPI 986 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
980 <GIC_SPI 987 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
981 <GIC_SPI 988 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
982 <GIC_SPI 989 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
983 <GIC_SPI 990 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
984 <GIC_SPI 991 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
985 <GIC_SPI 992 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
986 <GIC_SPI 993 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
987 <GIC_SPI 994 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
988 <GIC_SPI 995 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
989 <GIC_SPI 996 <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
990 <GIC_SPI 997 <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
991 interrupt-names = "ch0 998 interrupt-names = "ch0", "ch1", "ch2", "ch3",
992 "ch4 999 "ch4", "ch5", "ch6", "ch7",
993 "ch8 1000 "ch8", "ch9", "ch10", "ch11",
994 "ch1 1001 "ch12", "ch13", "ch14", "ch15",
995 "ch1 1002 "ch16", "ch17", "ch18", "ch19",
996 "ch2 1003 "ch20", "ch21", "ch22", "ch23",
997 "ch2 1004 "ch24";
998 clocks = <&cpg CPG_MOD 1005 clocks = <&cpg CPG_MOD 812>;
999 clock-names = "fck"; 1006 clock-names = "fck";
1000 power-domains = <&sys 1007 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1001 resets = <&cpg 812>; 1008 resets = <&cpg 812>;
1002 phy-mode = "rgmii"; 1009 phy-mode = "rgmii";
1003 rx-internal-delay-ps 1010 rx-internal-delay-ps = <0>;
1004 iommus = <&ipmmu_ds0 1011 iommus = <&ipmmu_ds0 16>;
1005 #address-cells = <1>; 1012 #address-cells = <1>;
1006 #size-cells = <0>; 1013 #size-cells = <0>;
1007 status = "disabled"; 1014 status = "disabled";
1008 }; 1015 };
1009 1016
1010 can0: can@e6c30000 { 1017 can0: can@e6c30000 {
1011 compatible = "renesas 1018 compatible = "renesas,can-r8a77990",
1012 "renesas 1019 "renesas,rcar-gen3-can";
1013 reg = <0 0xe6c30000 0 1020 reg = <0 0xe6c30000 0 0x1000>;
1014 interrupts = <GIC_SPI 1021 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
1015 clocks = <&cpg CPG_MO 1022 clocks = <&cpg CPG_MOD 916>,
1016 <&cpg CPG_CORE 1023 <&cpg CPG_CORE R8A77990_CLK_CANFD>,
1017 <&can_clk>; 1024 <&can_clk>;
1018 clock-names = "clkp1" 1025 clock-names = "clkp1", "clkp2", "can_clk";
1019 assigned-clocks = <&c 1026 assigned-clocks = <&cpg CPG_CORE R8A77990_CLK_CANFD>;
1020 assigned-clock-rates 1027 assigned-clock-rates = <40000000>;
1021 power-domains = <&sys 1028 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1022 resets = <&cpg 916>; 1029 resets = <&cpg 916>;
1023 status = "disabled"; 1030 status = "disabled";
1024 }; 1031 };
1025 1032
1026 can1: can@e6c38000 { 1033 can1: can@e6c38000 {
1027 compatible = "renesas 1034 compatible = "renesas,can-r8a77990",
1028 "renesas 1035 "renesas,rcar-gen3-can";
1029 reg = <0 0xe6c38000 0 1036 reg = <0 0xe6c38000 0 0x1000>;
1030 interrupts = <GIC_SPI 1037 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
1031 clocks = <&cpg CPG_MO 1038 clocks = <&cpg CPG_MOD 915>,
1032 <&cpg CPG_CORE 1039 <&cpg CPG_CORE R8A77990_CLK_CANFD>,
1033 <&can_clk>; 1040 <&can_clk>;
1034 clock-names = "clkp1" 1041 clock-names = "clkp1", "clkp2", "can_clk";
1035 assigned-clocks = <&c 1042 assigned-clocks = <&cpg CPG_CORE R8A77990_CLK_CANFD>;
1036 assigned-clock-rates 1043 assigned-clock-rates = <40000000>;
1037 power-domains = <&sys 1044 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1038 resets = <&cpg 915>; 1045 resets = <&cpg 915>;
1039 status = "disabled"; 1046 status = "disabled";
1040 }; 1047 };
1041 1048
1042 canfd: can@e66c0000 { 1049 canfd: can@e66c0000 {
1043 compatible = "renesas 1050 compatible = "renesas,r8a77990-canfd",
1044 "renesas 1051 "renesas,rcar-gen3-canfd";
1045 reg = <0 0xe66c0000 0 1052 reg = <0 0xe66c0000 0 0x8000>;
1046 interrupts = <GIC_SPI 1053 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
1047 <GIC_SPI 3 1054 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
1048 interrupt-names = "ch 1055 interrupt-names = "ch_int", "g_int";
1049 clocks = <&cpg CPG_MO 1056 clocks = <&cpg CPG_MOD 914>,
1050 <&cpg CPG_CORE 1057 <&cpg CPG_CORE R8A77990_CLK_CANFD>,
1051 <&can_clk>; 1058 <&can_clk>;
1052 clock-names = "fck", 1059 clock-names = "fck", "canfd", "can_clk";
1053 assigned-clocks = <&c 1060 assigned-clocks = <&cpg CPG_CORE R8A77990_CLK_CANFD>;
1054 assigned-clock-rates 1061 assigned-clock-rates = <40000000>;
1055 power-domains = <&sys 1062 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1056 resets = <&cpg 914>; 1063 resets = <&cpg 914>;
1057 status = "disabled"; 1064 status = "disabled";
1058 1065
1059 channel0 { 1066 channel0 {
1060 status = "dis 1067 status = "disabled";
1061 }; 1068 };
1062 1069
1063 channel1 { 1070 channel1 {
1064 status = "dis 1071 status = "disabled";
1065 }; 1072 };
1066 }; 1073 };
1067 1074
1068 pwm0: pwm@e6e30000 { 1075 pwm0: pwm@e6e30000 {
1069 compatible = "renesas 1076 compatible = "renesas,pwm-r8a77990", "renesas,pwm-rcar";
1070 reg = <0 0xe6e30000 0 1077 reg = <0 0xe6e30000 0 0x8>;
1071 clocks = <&cpg CPG_MO 1078 clocks = <&cpg CPG_MOD 523>;
1072 power-domains = <&sys 1079 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1073 resets = <&cpg 523>; 1080 resets = <&cpg 523>;
1074 #pwm-cells = <2>; 1081 #pwm-cells = <2>;
1075 status = "disabled"; 1082 status = "disabled";
1076 }; 1083 };
1077 1084
1078 pwm1: pwm@e6e31000 { 1085 pwm1: pwm@e6e31000 {
1079 compatible = "renesas 1086 compatible = "renesas,pwm-r8a77990", "renesas,pwm-rcar";
1080 reg = <0 0xe6e31000 0 1087 reg = <0 0xe6e31000 0 0x8>;
1081 clocks = <&cpg CPG_MO 1088 clocks = <&cpg CPG_MOD 523>;
1082 power-domains = <&sys 1089 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1083 resets = <&cpg 523>; 1090 resets = <&cpg 523>;
1084 #pwm-cells = <2>; 1091 #pwm-cells = <2>;
1085 status = "disabled"; 1092 status = "disabled";
1086 }; 1093 };
1087 1094
1088 pwm2: pwm@e6e32000 { 1095 pwm2: pwm@e6e32000 {
1089 compatible = "renesas 1096 compatible = "renesas,pwm-r8a77990", "renesas,pwm-rcar";
1090 reg = <0 0xe6e32000 0 1097 reg = <0 0xe6e32000 0 0x8>;
1091 clocks = <&cpg CPG_MO 1098 clocks = <&cpg CPG_MOD 523>;
1092 power-domains = <&sys 1099 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1093 resets = <&cpg 523>; 1100 resets = <&cpg 523>;
1094 #pwm-cells = <2>; 1101 #pwm-cells = <2>;
1095 status = "disabled"; 1102 status = "disabled";
1096 }; 1103 };
1097 1104
1098 pwm3: pwm@e6e33000 { 1105 pwm3: pwm@e6e33000 {
1099 compatible = "renesas 1106 compatible = "renesas,pwm-r8a77990", "renesas,pwm-rcar";
1100 reg = <0 0xe6e33000 0 1107 reg = <0 0xe6e33000 0 0x8>;
1101 clocks = <&cpg CPG_MO 1108 clocks = <&cpg CPG_MOD 523>;
1102 power-domains = <&sys 1109 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1103 resets = <&cpg 523>; 1110 resets = <&cpg 523>;
1104 #pwm-cells = <2>; 1111 #pwm-cells = <2>;
1105 status = "disabled"; 1112 status = "disabled";
1106 }; 1113 };
1107 1114
1108 pwm4: pwm@e6e34000 { 1115 pwm4: pwm@e6e34000 {
1109 compatible = "renesas 1116 compatible = "renesas,pwm-r8a77990", "renesas,pwm-rcar";
1110 reg = <0 0xe6e34000 0 1117 reg = <0 0xe6e34000 0 0x8>;
1111 clocks = <&cpg CPG_MO 1118 clocks = <&cpg CPG_MOD 523>;
1112 power-domains = <&sys 1119 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1113 resets = <&cpg 523>; 1120 resets = <&cpg 523>;
1114 #pwm-cells = <2>; 1121 #pwm-cells = <2>;
1115 status = "disabled"; 1122 status = "disabled";
1116 }; 1123 };
1117 1124
1118 pwm5: pwm@e6e35000 { 1125 pwm5: pwm@e6e35000 {
1119 compatible = "renesas 1126 compatible = "renesas,pwm-r8a77990", "renesas,pwm-rcar";
1120 reg = <0 0xe6e35000 0 1127 reg = <0 0xe6e35000 0 0x8>;
1121 clocks = <&cpg CPG_MO 1128 clocks = <&cpg CPG_MOD 523>;
1122 power-domains = <&sys 1129 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1123 resets = <&cpg 523>; 1130 resets = <&cpg 523>;
1124 #pwm-cells = <2>; 1131 #pwm-cells = <2>;
1125 status = "disabled"; 1132 status = "disabled";
1126 }; 1133 };
1127 1134
1128 pwm6: pwm@e6e36000 { 1135 pwm6: pwm@e6e36000 {
1129 compatible = "renesas 1136 compatible = "renesas,pwm-r8a77990", "renesas,pwm-rcar";
1130 reg = <0 0xe6e36000 0 1137 reg = <0 0xe6e36000 0 0x8>;
1131 clocks = <&cpg CPG_MO 1138 clocks = <&cpg CPG_MOD 523>;
1132 power-domains = <&sys 1139 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1133 resets = <&cpg 523>; 1140 resets = <&cpg 523>;
1134 #pwm-cells = <2>; 1141 #pwm-cells = <2>;
1135 status = "disabled"; 1142 status = "disabled";
1136 }; 1143 };
1137 1144
1138 scif0: serial@e6e60000 { 1145 scif0: serial@e6e60000 {
1139 compatible = "renesas 1146 compatible = "renesas,scif-r8a77990",
1140 "renesas 1147 "renesas,rcar-gen3-scif", "renesas,scif";
1141 reg = <0 0xe6e60000 0 1148 reg = <0 0xe6e60000 0 64>;
1142 interrupts = <GIC_SPI 1149 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
1143 clocks = <&cpg CPG_MO 1150 clocks = <&cpg CPG_MOD 207>,
1144 <&cpg CPG_CO 1151 <&cpg CPG_CORE R8A77990_CLK_S3D1C>,
1145 <&scif_clk>; 1152 <&scif_clk>;
1146 clock-names = "fck", 1153 clock-names = "fck", "brg_int", "scif_clk";
1147 dmas = <&dmac1 0x51>, 1154 dmas = <&dmac1 0x51>, <&dmac1 0x50>,
1148 <&dmac2 0x51>, 1155 <&dmac2 0x51>, <&dmac2 0x50>;
1149 dma-names = "tx", "rx 1156 dma-names = "tx", "rx", "tx", "rx";
1150 power-domains = <&sys 1157 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1151 resets = <&cpg 207>; 1158 resets = <&cpg 207>;
1152 status = "disabled"; 1159 status = "disabled";
1153 }; 1160 };
1154 1161
1155 scif1: serial@e6e68000 { 1162 scif1: serial@e6e68000 {
1156 compatible = "renesas 1163 compatible = "renesas,scif-r8a77990",
1157 "renesas 1164 "renesas,rcar-gen3-scif", "renesas,scif";
1158 reg = <0 0xe6e68000 0 1165 reg = <0 0xe6e68000 0 64>;
1159 interrupts = <GIC_SPI 1166 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
1160 clocks = <&cpg CPG_MO 1167 clocks = <&cpg CPG_MOD 206>,
1161 <&cpg CPG_CO 1168 <&cpg CPG_CORE R8A77990_CLK_S3D1C>,
1162 <&scif_clk>; 1169 <&scif_clk>;
1163 clock-names = "fck", 1170 clock-names = "fck", "brg_int", "scif_clk";
1164 dmas = <&dmac1 0x53>, 1171 dmas = <&dmac1 0x53>, <&dmac1 0x52>,
1165 <&dmac2 0x53>, 1172 <&dmac2 0x53>, <&dmac2 0x52>;
1166 dma-names = "tx", "rx 1173 dma-names = "tx", "rx", "tx", "rx";
1167 power-domains = <&sys 1174 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1168 resets = <&cpg 206>; 1175 resets = <&cpg 206>;
1169 status = "disabled"; 1176 status = "disabled";
1170 }; 1177 };
1171 1178
1172 scif2: serial@e6e88000 { 1179 scif2: serial@e6e88000 {
1173 compatible = "renesas 1180 compatible = "renesas,scif-r8a77990",
1174 "renesas 1181 "renesas,rcar-gen3-scif", "renesas,scif";
1175 reg = <0 0xe6e88000 0 1182 reg = <0 0xe6e88000 0 64>;
1176 interrupts = <GIC_SPI 1183 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
1177 clocks = <&cpg CPG_MO 1184 clocks = <&cpg CPG_MOD 310>,
1178 <&cpg CPG_CO 1185 <&cpg CPG_CORE R8A77990_CLK_S3D1C>,
1179 <&scif_clk>; 1186 <&scif_clk>;
1180 clock-names = "fck", 1187 clock-names = "fck", "brg_int", "scif_clk";
1181 dmas = <&dmac1 0x13>, 1188 dmas = <&dmac1 0x13>, <&dmac1 0x12>,
1182 <&dmac2 0x13>, 1189 <&dmac2 0x13>, <&dmac2 0x12>;
1183 dma-names = "tx", "rx 1190 dma-names = "tx", "rx", "tx", "rx";
1184 power-domains = <&sys 1191 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1185 resets = <&cpg 310>; 1192 resets = <&cpg 310>;
1186 status = "disabled"; 1193 status = "disabled";
1187 }; 1194 };
1188 1195
1189 scif3: serial@e6c50000 { 1196 scif3: serial@e6c50000 {
1190 compatible = "renesas 1197 compatible = "renesas,scif-r8a77990",
1191 "renesas 1198 "renesas,rcar-gen3-scif", "renesas,scif";
1192 reg = <0 0xe6c50000 0 1199 reg = <0 0xe6c50000 0 64>;
1193 interrupts = <GIC_SPI 1200 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
1194 clocks = <&cpg CPG_MO 1201 clocks = <&cpg CPG_MOD 204>,
1195 <&cpg CPG_CO 1202 <&cpg CPG_CORE R8A77990_CLK_S3D1C>,
1196 <&scif_clk>; 1203 <&scif_clk>;
1197 clock-names = "fck", 1204 clock-names = "fck", "brg_int", "scif_clk";
1198 dmas = <&dmac0 0x57>, 1205 dmas = <&dmac0 0x57>, <&dmac0 0x56>;
1199 dma-names = "tx", "rx 1206 dma-names = "tx", "rx";
1200 power-domains = <&sys 1207 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1201 resets = <&cpg 204>; 1208 resets = <&cpg 204>;
1202 status = "disabled"; 1209 status = "disabled";
1203 }; 1210 };
1204 1211
1205 scif4: serial@e6c40000 { 1212 scif4: serial@e6c40000 {
1206 compatible = "renesas 1213 compatible = "renesas,scif-r8a77990",
1207 "renesas 1214 "renesas,rcar-gen3-scif", "renesas,scif";
1208 reg = <0 0xe6c40000 0 1215 reg = <0 0xe6c40000 0 64>;
1209 interrupts = <GIC_SPI 1216 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1210 clocks = <&cpg CPG_MO 1217 clocks = <&cpg CPG_MOD 203>,
1211 <&cpg CPG_CO 1218 <&cpg CPG_CORE R8A77990_CLK_S3D1C>,
1212 <&scif_clk>; 1219 <&scif_clk>;
1213 clock-names = "fck", 1220 clock-names = "fck", "brg_int", "scif_clk";
1214 dmas = <&dmac0 0x59>, 1221 dmas = <&dmac0 0x59>, <&dmac0 0x58>;
1215 dma-names = "tx", "rx 1222 dma-names = "tx", "rx";
1216 power-domains = <&sys 1223 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1217 resets = <&cpg 203>; 1224 resets = <&cpg 203>;
1218 status = "disabled"; 1225 status = "disabled";
1219 }; 1226 };
1220 1227
1221 scif5: serial@e6f30000 { 1228 scif5: serial@e6f30000 {
1222 compatible = "renesas 1229 compatible = "renesas,scif-r8a77990",
1223 "renesas 1230 "renesas,rcar-gen3-scif", "renesas,scif";
1224 reg = <0 0xe6f30000 0 1231 reg = <0 0xe6f30000 0 64>;
1225 interrupts = <GIC_SPI 1232 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1226 clocks = <&cpg CPG_MO 1233 clocks = <&cpg CPG_MOD 202>,
1227 <&cpg CPG_CO 1234 <&cpg CPG_CORE R8A77990_CLK_S3D1C>,
1228 <&scif_clk>; 1235 <&scif_clk>;
1229 clock-names = "fck", 1236 clock-names = "fck", "brg_int", "scif_clk";
1230 dmas = <&dmac0 0x5b>, 1237 dmas = <&dmac0 0x5b>, <&dmac0 0x5a>;
1231 dma-names = "tx", "rx 1238 dma-names = "tx", "rx";
1232 power-domains = <&sys 1239 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1233 resets = <&cpg 202>; 1240 resets = <&cpg 202>;
1234 status = "disabled"; 1241 status = "disabled";
1235 }; 1242 };
1236 1243
1237 msiof0: spi@e6e90000 { 1244 msiof0: spi@e6e90000 {
1238 compatible = "renesas 1245 compatible = "renesas,msiof-r8a77990",
1239 "renesas 1246 "renesas,rcar-gen3-msiof";
1240 reg = <0 0xe6e90000 0 1247 reg = <0 0xe6e90000 0 0x0064>;
1241 interrupts = <GIC_SPI 1248 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
1242 clocks = <&cpg CPG_MO 1249 clocks = <&cpg CPG_MOD 211>;
1243 dmas = <&dmac1 0x41>, 1250 dmas = <&dmac1 0x41>, <&dmac1 0x40>,
1244 <&dmac2 0x41>, 1251 <&dmac2 0x41>, <&dmac2 0x40>;
1245 dma-names = "tx", "rx 1252 dma-names = "tx", "rx", "tx", "rx";
1246 power-domains = <&sys 1253 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1247 resets = <&cpg 211>; 1254 resets = <&cpg 211>;
1248 #address-cells = <1>; 1255 #address-cells = <1>;
1249 #size-cells = <0>; 1256 #size-cells = <0>;
1250 status = "disabled"; 1257 status = "disabled";
1251 }; 1258 };
1252 1259
1253 msiof1: spi@e6ea0000 { 1260 msiof1: spi@e6ea0000 {
1254 compatible = "renesas 1261 compatible = "renesas,msiof-r8a77990",
1255 "renesas 1262 "renesas,rcar-gen3-msiof";
1256 reg = <0 0xe6ea0000 0 1263 reg = <0 0xe6ea0000 0 0x0064>;
1257 interrupts = <GIC_SPI 1264 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
1258 clocks = <&cpg CPG_MO 1265 clocks = <&cpg CPG_MOD 210>;
1259 dmas = <&dmac0 0x43>, 1266 dmas = <&dmac0 0x43>, <&dmac0 0x42>;
1260 dma-names = "tx", "rx 1267 dma-names = "tx", "rx";
1261 power-domains = <&sys 1268 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1262 resets = <&cpg 210>; 1269 resets = <&cpg 210>;
1263 #address-cells = <1>; 1270 #address-cells = <1>;
1264 #size-cells = <0>; 1271 #size-cells = <0>;
1265 status = "disabled"; 1272 status = "disabled";
1266 }; 1273 };
1267 1274
1268 msiof2: spi@e6c00000 { 1275 msiof2: spi@e6c00000 {
1269 compatible = "renesas 1276 compatible = "renesas,msiof-r8a77990",
1270 "renesas 1277 "renesas,rcar-gen3-msiof";
1271 reg = <0 0xe6c00000 0 1278 reg = <0 0xe6c00000 0 0x0064>;
1272 interrupts = <GIC_SPI 1279 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
1273 clocks = <&cpg CPG_MO 1280 clocks = <&cpg CPG_MOD 209>;
1274 dmas = <&dmac0 0x45>, 1281 dmas = <&dmac0 0x45>, <&dmac0 0x44>;
1275 dma-names = "tx", "rx 1282 dma-names = "tx", "rx";
1276 power-domains = <&sys 1283 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1277 resets = <&cpg 209>; 1284 resets = <&cpg 209>;
1278 #address-cells = <1>; 1285 #address-cells = <1>;
1279 #size-cells = <0>; 1286 #size-cells = <0>;
1280 status = "disabled"; 1287 status = "disabled";
1281 }; 1288 };
1282 1289
1283 msiof3: spi@e6c10000 { 1290 msiof3: spi@e6c10000 {
1284 compatible = "renesas 1291 compatible = "renesas,msiof-r8a77990",
1285 "renesas 1292 "renesas,rcar-gen3-msiof";
1286 reg = <0 0xe6c10000 0 1293 reg = <0 0xe6c10000 0 0x0064>;
1287 interrupts = <GIC_SPI 1294 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
1288 clocks = <&cpg CPG_MO 1295 clocks = <&cpg CPG_MOD 208>;
1289 dmas = <&dmac0 0x47>, 1296 dmas = <&dmac0 0x47>, <&dmac0 0x46>;
1290 dma-names = "tx", "rx 1297 dma-names = "tx", "rx";
1291 power-domains = <&sys 1298 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1292 resets = <&cpg 208>; 1299 resets = <&cpg 208>;
1293 #address-cells = <1>; 1300 #address-cells = <1>;
1294 #size-cells = <0>; 1301 #size-cells = <0>;
1295 status = "disabled"; 1302 status = "disabled";
1296 }; 1303 };
1297 1304
1298 vin4: video@e6ef4000 { 1305 vin4: video@e6ef4000 {
1299 compatible = "renesas 1306 compatible = "renesas,vin-r8a77990";
1300 reg = <0 0xe6ef4000 0 1307 reg = <0 0xe6ef4000 0 0x1000>;
1301 interrupts = <GIC_SPI 1308 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
1302 clocks = <&cpg CPG_MO 1309 clocks = <&cpg CPG_MOD 807>;
1303 power-domains = <&sys 1310 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1304 resets = <&cpg 807>; 1311 resets = <&cpg 807>;
1305 renesas,id = <4>; 1312 renesas,id = <4>;
1306 status = "disabled"; 1313 status = "disabled";
1307 1314
1308 ports { 1315 ports {
1309 #address-cell 1316 #address-cells = <1>;
1310 #size-cells = 1317 #size-cells = <0>;
1311 1318
1312 port@1 { 1319 port@1 {
1313 #addr 1320 #address-cells = <1>;
1314 #size 1321 #size-cells = <0>;
1315 1322
1316 reg = 1323 reg = <1>;
1317 1324
1318 vin4c 1325 vin4csi40: endpoint@2 {
1319 1326 reg = <2>;
1320 1327 remote-endpoint = <&csi40vin4>;
1321 }; 1328 };
1322 }; 1329 };
1323 }; 1330 };
1324 }; 1331 };
1325 1332
1326 vin5: video@e6ef5000 { 1333 vin5: video@e6ef5000 {
1327 compatible = "renesas 1334 compatible = "renesas,vin-r8a77990";
1328 reg = <0 0xe6ef5000 0 1335 reg = <0 0xe6ef5000 0 0x1000>;
1329 interrupts = <GIC_SPI 1336 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
1330 clocks = <&cpg CPG_MO 1337 clocks = <&cpg CPG_MOD 806>;
1331 power-domains = <&sys 1338 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1332 resets = <&cpg 806>; 1339 resets = <&cpg 806>;
1333 renesas,id = <5>; 1340 renesas,id = <5>;
1334 status = "disabled"; 1341 status = "disabled";
1335 1342
1336 ports { 1343 ports {
1337 #address-cell 1344 #address-cells = <1>;
1338 #size-cells = 1345 #size-cells = <0>;
1339 1346
1340 port@1 { 1347 port@1 {
1341 #addr 1348 #address-cells = <1>;
1342 #size 1349 #size-cells = <0>;
1343 1350
1344 reg = 1351 reg = <1>;
1345 1352
1346 vin5c 1353 vin5csi40: endpoint@2 {
1347 1354 reg = <2>;
1348 1355 remote-endpoint = <&csi40vin5>;
1349 }; 1356 };
1350 }; 1357 };
1351 }; 1358 };
1352 }; 1359 };
1353 1360
1354 drif00: rif@e6f40000 { 1361 drif00: rif@e6f40000 {
1355 compatible = "renesas 1362 compatible = "renesas,r8a77990-drif",
1356 "renesas 1363 "renesas,rcar-gen3-drif";
1357 reg = <0 0xe6f40000 0 1364 reg = <0 0xe6f40000 0 0x84>;
1358 interrupts = <GIC_SPI 1365 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1359 clocks = <&cpg CPG_MO 1366 clocks = <&cpg CPG_MOD 515>;
1360 clock-names = "fck"; 1367 clock-names = "fck";
1361 dmas = <&dmac1 0x20>, 1368 dmas = <&dmac1 0x20>, <&dmac2 0x20>;
1362 dma-names = "rx", "rx 1369 dma-names = "rx", "rx";
1363 power-domains = <&sys 1370 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1364 resets = <&cpg 515>; 1371 resets = <&cpg 515>;
1365 renesas,bonding = <&d 1372 renesas,bonding = <&drif01>;
1366 status = "disabled"; 1373 status = "disabled";
1367 }; 1374 };
1368 1375
1369 drif01: rif@e6f50000 { 1376 drif01: rif@e6f50000 {
1370 compatible = "renesas 1377 compatible = "renesas,r8a77990-drif",
1371 "renesas 1378 "renesas,rcar-gen3-drif";
1372 reg = <0 0xe6f50000 0 1379 reg = <0 0xe6f50000 0 0x84>;
1373 interrupts = <GIC_SPI 1380 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
1374 clocks = <&cpg CPG_MO 1381 clocks = <&cpg CPG_MOD 514>;
1375 clock-names = "fck"; 1382 clock-names = "fck";
1376 dmas = <&dmac1 0x22>, 1383 dmas = <&dmac1 0x22>, <&dmac2 0x22>;
1377 dma-names = "rx", "rx 1384 dma-names = "rx", "rx";
1378 power-domains = <&sys 1385 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1379 resets = <&cpg 514>; 1386 resets = <&cpg 514>;
1380 renesas,bonding = <&d 1387 renesas,bonding = <&drif00>;
1381 status = "disabled"; 1388 status = "disabled";
1382 }; 1389 };
1383 1390
1384 drif10: rif@e6f60000 { 1391 drif10: rif@e6f60000 {
1385 compatible = "renesas 1392 compatible = "renesas,r8a77990-drif",
1386 "renesas 1393 "renesas,rcar-gen3-drif";
1387 reg = <0 0xe6f60000 0 1394 reg = <0 0xe6f60000 0 0x84>;
1388 interrupts = <GIC_SPI 1395 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1389 clocks = <&cpg CPG_MO 1396 clocks = <&cpg CPG_MOD 513>;
1390 clock-names = "fck"; 1397 clock-names = "fck";
1391 dmas = <&dmac1 0x24>, 1398 dmas = <&dmac1 0x24>, <&dmac2 0x24>;
1392 dma-names = "rx", "rx 1399 dma-names = "rx", "rx";
1393 power-domains = <&sys 1400 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1394 resets = <&cpg 513>; 1401 resets = <&cpg 513>;
1395 renesas,bonding = <&d 1402 renesas,bonding = <&drif11>;
1396 status = "disabled"; 1403 status = "disabled";
1397 }; 1404 };
1398 1405
1399 drif11: rif@e6f70000 { 1406 drif11: rif@e6f70000 {
1400 compatible = "renesas 1407 compatible = "renesas,r8a77990-drif",
1401 "renesas 1408 "renesas,rcar-gen3-drif";
1402 reg = <0 0xe6f70000 0 1409 reg = <0 0xe6f70000 0 0x84>;
1403 interrupts = <GIC_SPI 1410 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1404 clocks = <&cpg CPG_MO 1411 clocks = <&cpg CPG_MOD 512>;
1405 clock-names = "fck"; 1412 clock-names = "fck";
1406 dmas = <&dmac1 0x26>, 1413 dmas = <&dmac1 0x26>, <&dmac2 0x26>;
1407 dma-names = "rx", "rx 1414 dma-names = "rx", "rx";
1408 power-domains = <&sys 1415 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1409 resets = <&cpg 512>; 1416 resets = <&cpg 512>;
1410 renesas,bonding = <&d 1417 renesas,bonding = <&drif10>;
1411 status = "disabled"; 1418 status = "disabled";
1412 }; 1419 };
1413 1420
1414 drif20: rif@e6f80000 { 1421 drif20: rif@e6f80000 {
1415 compatible = "renesas 1422 compatible = "renesas,r8a77990-drif",
1416 "renesas 1423 "renesas,rcar-gen3-drif";
1417 reg = <0 0xe6f80000 0 1424 reg = <0 0xe6f80000 0 0x84>;
1418 interrupts = <GIC_SPI 1425 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
1419 clocks = <&cpg CPG_MO 1426 clocks = <&cpg CPG_MOD 511>;
1420 clock-names = "fck"; 1427 clock-names = "fck";
1421 dmas = <&dmac0 0x28>; 1428 dmas = <&dmac0 0x28>;
1422 dma-names = "rx"; 1429 dma-names = "rx";
1423 power-domains = <&sys 1430 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1424 resets = <&cpg 511>; 1431 resets = <&cpg 511>;
1425 renesas,bonding = <&d 1432 renesas,bonding = <&drif21>;
1426 status = "disabled"; 1433 status = "disabled";
1427 }; 1434 };
1428 1435
1429 drif21: rif@e6f90000 { 1436 drif21: rif@e6f90000 {
1430 compatible = "renesas 1437 compatible = "renesas,r8a77990-drif",
1431 "renesas 1438 "renesas,rcar-gen3-drif";
1432 reg = <0 0xe6f90000 0 1439 reg = <0 0xe6f90000 0 0x84>;
1433 interrupts = <GIC_SPI 1440 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
1434 clocks = <&cpg CPG_MO 1441 clocks = <&cpg CPG_MOD 510>;
1435 clock-names = "fck"; 1442 clock-names = "fck";
1436 dmas = <&dmac0 0x2a>; 1443 dmas = <&dmac0 0x2a>;
1437 dma-names = "rx"; 1444 dma-names = "rx";
1438 power-domains = <&sys 1445 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1439 resets = <&cpg 510>; 1446 resets = <&cpg 510>;
1440 renesas,bonding = <&d 1447 renesas,bonding = <&drif20>;
1441 status = "disabled"; 1448 status = "disabled";
1442 }; 1449 };
1443 1450
1444 drif30: rif@e6fa0000 { 1451 drif30: rif@e6fa0000 {
1445 compatible = "renesas 1452 compatible = "renesas,r8a77990-drif",
1446 "renesas 1453 "renesas,rcar-gen3-drif";
1447 reg = <0 0xe6fa0000 0 1454 reg = <0 0xe6fa0000 0 0x84>;
1448 interrupts = <GIC_SPI 1455 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
1449 clocks = <&cpg CPG_MO 1456 clocks = <&cpg CPG_MOD 509>;
1450 clock-names = "fck"; 1457 clock-names = "fck";
1451 dmas = <&dmac0 0x2c>; 1458 dmas = <&dmac0 0x2c>;
1452 dma-names = "rx"; 1459 dma-names = "rx";
1453 power-domains = <&sys 1460 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1454 resets = <&cpg 509>; 1461 resets = <&cpg 509>;
1455 renesas,bonding = <&d 1462 renesas,bonding = <&drif31>;
1456 status = "disabled"; 1463 status = "disabled";
1457 }; 1464 };
1458 1465
1459 drif31: rif@e6fb0000 { 1466 drif31: rif@e6fb0000 {
1460 compatible = "renesas 1467 compatible = "renesas,r8a77990-drif",
1461 "renesas 1468 "renesas,rcar-gen3-drif";
1462 reg = <0 0xe6fb0000 0 1469 reg = <0 0xe6fb0000 0 0x84>;
1463 interrupts = <GIC_SPI 1470 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
1464 clocks = <&cpg CPG_MO 1471 clocks = <&cpg CPG_MOD 508>;
1465 clock-names = "fck"; 1472 clock-names = "fck";
1466 dmas = <&dmac0 0x2e>; 1473 dmas = <&dmac0 0x2e>;
1467 dma-names = "rx"; 1474 dma-names = "rx";
1468 power-domains = <&sys 1475 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1469 resets = <&cpg 508>; 1476 resets = <&cpg 508>;
1470 renesas,bonding = <&d 1477 renesas,bonding = <&drif30>;
1471 status = "disabled"; 1478 status = "disabled";
1472 }; 1479 };
1473 1480
1474 rcar_sound: sound@ec500000 { 1481 rcar_sound: sound@ec500000 {
1475 /* 1482 /*
1476 * #sound-dai-cells i !! 1483 * #sound-dai-cells is required
1477 * 1484 *
1478 * Single DAI : #soun 1485 * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
1479 * Multi DAI : #soun 1486 * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>;
1480 */ 1487 */
1481 /* 1488 /*
1482 * #clock-cells is re 1489 * #clock-cells is required for audio_clkout0/1/2/3
1483 * 1490 *
1484 * clkout : #cl 1491 * clkout : #clock-cells = <0>; <&rcar_sound>;
1485 * clkout0/1/2/3: #cl 1492 * clkout0/1/2/3: #clock-cells = <1>; <&rcar_sound N>;
1486 */ 1493 */
1487 compatible = "renesas 1494 compatible = "renesas,rcar_sound-r8a77990", "renesas,rcar_sound-gen3";
1488 reg = <0 0xec500000 0 1495 reg = <0 0xec500000 0 0x1000>, /* SCU */
1489 <0 0xec5a0000 0 1496 <0 0xec5a0000 0 0x100>, /* ADG */
1490 <0 0xec540000 0 1497 <0 0xec540000 0 0x1000>, /* SSIU */
1491 <0 0xec541000 0 1498 <0 0xec541000 0 0x280>, /* SSI */
1492 <0 0xec760000 0 1499 <0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/
1493 reg-names = "scu", "a 1500 reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
1494 1501
1495 clocks = <&cpg CPG_MO 1502 clocks = <&cpg CPG_MOD 1005>,
1496 <&cpg CPG_MO 1503 <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
1497 <&cpg CPG_MO 1504 <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
1498 <&cpg CPG_MO 1505 <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
1499 <&cpg CPG_MO 1506 <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
1500 <&cpg CPG_MO 1507 <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
1501 <&cpg CPG_MO 1508 <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,
1502 <&cpg CPG_MO 1509 <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,
1503 <&cpg CPG_MO 1510 <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,
1504 <&cpg CPG_MO 1511 <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,
1505 <&cpg CPG_MO 1512 <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,
1506 <&cpg CPG_MO 1513 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
1507 <&cpg CPG_MO 1514 <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
1508 <&cpg CPG_MO 1515 <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
1509 <&audio_clk_ 1516 <&audio_clk_a>, <&audio_clk_b>,
1510 <&audio_clk_ 1517 <&audio_clk_c>,
1511 <&cpg CPG_MO !! 1518 <&cpg CPG_CORE R8A77990_CLK_ZA2>;
1512 clock-names = "ssi-al 1519 clock-names = "ssi-all",
1513 "ssi.9" 1520 "ssi.9", "ssi.8", "ssi.7", "ssi.6",
1514 "ssi.5" 1521 "ssi.5", "ssi.4", "ssi.3", "ssi.2",
1515 "ssi.1" 1522 "ssi.1", "ssi.0",
1516 "src.9" 1523 "src.9", "src.8", "src.7", "src.6",
1517 "src.5" 1524 "src.5", "src.4", "src.3", "src.2",
1518 "src.1" 1525 "src.1", "src.0",
1519 "mix.1" 1526 "mix.1", "mix.0",
1520 "ctu.1" 1527 "ctu.1", "ctu.0",
1521 "dvc.0" 1528 "dvc.0", "dvc.1",
1522 "clk_a" 1529 "clk_a", "clk_b", "clk_c", "clk_i";
1523 power-domains = <&sys 1530 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1524 resets = <&cpg 1005>, 1531 resets = <&cpg 1005>,
1525 <&cpg 1006>, 1532 <&cpg 1006>, <&cpg 1007>,
1526 <&cpg 1008>, 1533 <&cpg 1008>, <&cpg 1009>,
1527 <&cpg 1010>, 1534 <&cpg 1010>, <&cpg 1011>,
1528 <&cpg 1012>, 1535 <&cpg 1012>, <&cpg 1013>,
1529 <&cpg 1014>, 1536 <&cpg 1014>, <&cpg 1015>;
1530 reset-names = "ssi-al 1537 reset-names = "ssi-all",
1531 "ssi.9" 1538 "ssi.9", "ssi.8", "ssi.7", "ssi.6",
1532 "ssi.5" 1539 "ssi.5", "ssi.4", "ssi.3", "ssi.2",
1533 "ssi.1" 1540 "ssi.1", "ssi.0";
1534 status = "disabled"; 1541 status = "disabled";
1535 1542
1536 rcar_sound,ctu { 1543 rcar_sound,ctu {
1537 ctu00: ctu-0 1544 ctu00: ctu-0 { };
1538 ctu01: ctu-1 1545 ctu01: ctu-1 { };
1539 ctu02: ctu-2 1546 ctu02: ctu-2 { };
1540 ctu03: ctu-3 1547 ctu03: ctu-3 { };
1541 ctu10: ctu-4 1548 ctu10: ctu-4 { };
1542 ctu11: ctu-5 1549 ctu11: ctu-5 { };
1543 ctu12: ctu-6 1550 ctu12: ctu-6 { };
1544 ctu13: ctu-7 1551 ctu13: ctu-7 { };
1545 }; 1552 };
1546 1553
1547 rcar_sound,dvc { 1554 rcar_sound,dvc {
1548 dvc0: dvc-0 { 1555 dvc0: dvc-0 {
1549 dmas 1556 dmas = <&audma0 0xbc>;
1550 dma-n 1557 dma-names = "tx";
1551 }; 1558 };
1552 dvc1: dvc-1 { 1559 dvc1: dvc-1 {
1553 dmas 1560 dmas = <&audma0 0xbe>;
1554 dma-n 1561 dma-names = "tx";
1555 }; 1562 };
1556 }; 1563 };
1557 1564
1558 rcar_sound,mix { 1565 rcar_sound,mix {
1559 mix0: mix-0 { 1566 mix0: mix-0 { };
1560 mix1: mix-1 { 1567 mix1: mix-1 { };
1561 }; 1568 };
1562 1569
1563 rcar_sound,src { 1570 rcar_sound,src {
1564 src0: src-0 { 1571 src0: src-0 {
1565 inter 1572 interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
1566 dmas 1573 dmas = <&audma0 0x85>, <&audma0 0x9a>;
1567 dma-n 1574 dma-names = "rx", "tx";
1568 }; 1575 };
1569 src1: src-1 { 1576 src1: src-1 {
1570 inter 1577 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1571 dmas 1578 dmas = <&audma0 0x87>, <&audma0 0x9c>;
1572 dma-n 1579 dma-names = "rx", "tx";
1573 }; 1580 };
1574 src2: src-2 { 1581 src2: src-2 {
1575 inter 1582 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1576 dmas 1583 dmas = <&audma0 0x89>, <&audma0 0x9e>;
1577 dma-n 1584 dma-names = "rx", "tx";
1578 }; 1585 };
1579 src3: src-3 { 1586 src3: src-3 {
1580 inter 1587 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1581 dmas 1588 dmas = <&audma0 0x8b>, <&audma0 0xa0>;
1582 dma-n 1589 dma-names = "rx", "tx";
1583 }; 1590 };
1584 src4: src-4 { 1591 src4: src-4 {
1585 inter 1592 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1586 dmas 1593 dmas = <&audma0 0x8d>, <&audma0 0xb0>;
1587 dma-n 1594 dma-names = "rx", "tx";
1588 }; 1595 };
1589 src5: src-5 { 1596 src5: src-5 {
1590 inter 1597 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1591 dmas 1598 dmas = <&audma0 0x8f>, <&audma0 0xb2>;
1592 dma-n 1599 dma-names = "rx", "tx";
1593 }; 1600 };
1594 src6: src-6 { 1601 src6: src-6 {
1595 inter 1602 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1596 dmas 1603 dmas = <&audma0 0x91>, <&audma0 0xb4>;
1597 dma-n 1604 dma-names = "rx", "tx";
1598 }; 1605 };
1599 src7: src-7 { 1606 src7: src-7 {
1600 inter 1607 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
1601 dmas 1608 dmas = <&audma0 0x93>, <&audma0 0xb6>;
1602 dma-n 1609 dma-names = "rx", "tx";
1603 }; 1610 };
1604 src8: src-8 { 1611 src8: src-8 {
1605 inter 1612 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
1606 dmas 1613 dmas = <&audma0 0x95>, <&audma0 0xb8>;
1607 dma-n 1614 dma-names = "rx", "tx";
1608 }; 1615 };
1609 src9: src-9 { 1616 src9: src-9 {
1610 inter 1617 interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>;
1611 dmas 1618 dmas = <&audma0 0x97>, <&audma0 0xba>;
1612 dma-n 1619 dma-names = "rx", "tx";
1613 }; 1620 };
1614 }; 1621 };
1615 1622
1616 rcar_sound,ssi { 1623 rcar_sound,ssi {
1617 ssi0: ssi-0 { 1624 ssi0: ssi-0 {
1618 inter 1625 interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
1619 dmas 1626 dmas = <&audma0 0x01>, <&audma0 0x02>,
1620 1627 <&audma0 0x15>, <&audma0 0x16>;
1621 dma-n 1628 dma-names = "rx", "tx", "rxu", "txu";
1622 }; 1629 };
1623 ssi1: ssi-1 { 1630 ssi1: ssi-1 {
1624 inter 1631 interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
1625 dmas 1632 dmas = <&audma0 0x03>, <&audma0 0x04>,
1626 1633 <&audma0 0x49>, <&audma0 0x4a>;
1627 dma-n 1634 dma-names = "rx", "tx", "rxu", "txu";
1628 }; 1635 };
1629 ssi2: ssi-2 { 1636 ssi2: ssi-2 {
1630 inter 1637 interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>;
1631 dmas 1638 dmas = <&audma0 0x05>, <&audma0 0x06>,
1632 1639 <&audma0 0x63>, <&audma0 0x64>;
1633 dma-n 1640 dma-names = "rx", "tx", "rxu", "txu";
1634 }; 1641 };
1635 ssi3: ssi-3 { 1642 ssi3: ssi-3 {
1636 inter 1643 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
1637 dmas 1644 dmas = <&audma0 0x07>, <&audma0 0x08>,
1638 1645 <&audma0 0x6f>, <&audma0 0x70>;
1639 dma-n 1646 dma-names = "rx", "tx", "rxu", "txu";
1640 }; 1647 };
1641 ssi4: ssi-4 { 1648 ssi4: ssi-4 {
1642 inter 1649 interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
1643 dmas 1650 dmas = <&audma0 0x09>, <&audma0 0x0a>,
1644 1651 <&audma0 0x71>, <&audma0 0x72>;
1645 dma-n 1652 dma-names = "rx", "tx", "rxu", "txu";
1646 }; 1653 };
1647 ssi5: ssi-5 { 1654 ssi5: ssi-5 {
1648 inter 1655 interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
1649 dmas 1656 dmas = <&audma0 0x0b>, <&audma0 0x0c>,
1650 1657 <&audma0 0x73>, <&audma0 0x74>;
1651 dma-n 1658 dma-names = "rx", "tx", "rxu", "txu";
1652 }; 1659 };
1653 ssi6: ssi-6 { 1660 ssi6: ssi-6 {
1654 inter 1661 interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>;
1655 dmas 1662 dmas = <&audma0 0x0d>, <&audma0 0x0e>,
1656 1663 <&audma0 0x75>, <&audma0 0x76>;
1657 dma-n 1664 dma-names = "rx", "tx", "rxu", "txu";
1658 }; 1665 };
1659 ssi7: ssi-7 { 1666 ssi7: ssi-7 {
1660 inter 1667 interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>;
1661 dmas 1668 dmas = <&audma0 0x0f>, <&audma0 0x10>,
1662 1669 <&audma0 0x79>, <&audma0 0x7a>;
1663 dma-n 1670 dma-names = "rx", "tx", "rxu", "txu";
1664 }; 1671 };
1665 ssi8: ssi-8 { 1672 ssi8: ssi-8 {
1666 inter 1673 interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>;
1667 dmas 1674 dmas = <&audma0 0x11>, <&audma0 0x12>,
1668 1675 <&audma0 0x7b>, <&audma0 0x7c>;
1669 dma-n 1676 dma-names = "rx", "tx", "rxu", "txu";
1670 }; 1677 };
1671 ssi9: ssi-9 { 1678 ssi9: ssi-9 {
1672 inter 1679 interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
1673 dmas 1680 dmas = <&audma0 0x13>, <&audma0 0x14>,
1674 1681 <&audma0 0x7d>, <&audma0 0x7e>;
1675 dma-n 1682 dma-names = "rx", "tx", "rxu", "txu";
1676 }; 1683 };
1677 }; 1684 };
1678 }; 1685 };
1679 1686
1680 mlp: mlp@ec520000 { 1687 mlp: mlp@ec520000 {
1681 compatible = "renesas 1688 compatible = "renesas,r8a77990-mlp",
1682 "renesas 1689 "renesas,rcar-gen3-mlp";
1683 reg = <0 0xec520000 0 1690 reg = <0 0xec520000 0 0x800>;
1684 interrupts = <GIC_SPI 1691 interrupts = <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>,
1685 <GIC_SPI 385 1692 <GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>;
1686 clocks = <&cpg CPG_MO 1693 clocks = <&cpg CPG_MOD 802>;
1687 power-domains = <&sys 1694 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1688 resets = <&cpg 802>; 1695 resets = <&cpg 802>;
1689 status = "disabled"; 1696 status = "disabled";
1690 }; 1697 };
1691 1698
1692 audma0: dma-controller@ec7000 1699 audma0: dma-controller@ec700000 {
1693 compatible = "renesas 1700 compatible = "renesas,dmac-r8a77990",
1694 "renesas 1701 "renesas,rcar-dmac";
1695 reg = <0 0xec700000 0 1702 reg = <0 0xec700000 0 0x10000>;
1696 interrupts = <GIC_SPI 1703 interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>,
1697 <GIC_SPI 1704 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
1698 <GIC_SPI 1705 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
1699 <GIC_SPI 1706 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
1700 <GIC_SPI 1707 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
1701 <GIC_SPI 1708 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
1702 <GIC_SPI 1709 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
1703 <GIC_SPI 1710 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
1704 <GIC_SPI 1711 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
1705 <GIC_SPI 1712 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
1706 <GIC_SPI 1713 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
1707 <GIC_SPI 1714 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
1708 <GIC_SPI 1715 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
1709 <GIC_SPI 1716 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
1710 <GIC_SPI 1717 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
1711 <GIC_SPI 1718 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
1712 <GIC_SPI 1719 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>;
1713 interrupt-names = "er 1720 interrupt-names = "error",
1714 "ch0" 1721 "ch0", "ch1", "ch2", "ch3",
1715 "ch4" 1722 "ch4", "ch5", "ch6", "ch7",
1716 "ch8" 1723 "ch8", "ch9", "ch10", "ch11",
1717 "ch12 1724 "ch12", "ch13", "ch14", "ch15";
1718 clocks = <&cpg CPG_MO 1725 clocks = <&cpg CPG_MOD 502>;
1719 clock-names = "fck"; 1726 clock-names = "fck";
1720 power-domains = <&sys 1727 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1721 resets = <&cpg 502>; 1728 resets = <&cpg 502>;
1722 #dma-cells = <1>; 1729 #dma-cells = <1>;
1723 dma-channels = <16>; 1730 dma-channels = <16>;
1724 iommus = <&ipmmu_mp 0 1731 iommus = <&ipmmu_mp 0>, <&ipmmu_mp 1>,
1725 <&ipmmu_mp 2 1732 <&ipmmu_mp 2>, <&ipmmu_mp 3>,
1726 <&ipmmu_mp 4 1733 <&ipmmu_mp 4>, <&ipmmu_mp 5>,
1727 <&ipmmu_mp 6 1734 <&ipmmu_mp 6>, <&ipmmu_mp 7>,
1728 <&ipmmu_mp 8 1735 <&ipmmu_mp 8>, <&ipmmu_mp 9>,
1729 <&ipmmu_mp 1 1736 <&ipmmu_mp 10>, <&ipmmu_mp 11>,
1730 <&ipmmu_mp 1 1737 <&ipmmu_mp 12>, <&ipmmu_mp 13>,
1731 <&ipmmu_mp 1 1738 <&ipmmu_mp 14>, <&ipmmu_mp 15>;
1732 }; 1739 };
1733 1740
1734 xhci0: usb@ee000000 { 1741 xhci0: usb@ee000000 {
1735 compatible = "renesas 1742 compatible = "renesas,xhci-r8a77990",
1736 "renesas 1743 "renesas,rcar-gen3-xhci";
1737 reg = <0 0xee000000 0 1744 reg = <0 0xee000000 0 0xc00>;
1738 interrupts = <GIC_SPI 1745 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
1739 clocks = <&cpg CPG_MO 1746 clocks = <&cpg CPG_MOD 328>;
1740 power-domains = <&sys 1747 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1741 resets = <&cpg 328>; 1748 resets = <&cpg 328>;
1742 status = "disabled"; 1749 status = "disabled";
1743 }; 1750 };
1744 1751
1745 usb3_peri0: usb@ee020000 { 1752 usb3_peri0: usb@ee020000 {
1746 compatible = "renesas 1753 compatible = "renesas,r8a77990-usb3-peri",
1747 "renesas 1754 "renesas,rcar-gen3-usb3-peri";
1748 reg = <0 0xee020000 0 1755 reg = <0 0xee020000 0 0x400>;
1749 interrupts = <GIC_SPI 1756 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
1750 clocks = <&cpg CPG_MO 1757 clocks = <&cpg CPG_MOD 328>;
1751 power-domains = <&sys 1758 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1752 resets = <&cpg 328>; 1759 resets = <&cpg 328>;
1753 status = "disabled"; 1760 status = "disabled";
1754 }; 1761 };
1755 1762
1756 ohci0: usb@ee080000 { 1763 ohci0: usb@ee080000 {
1757 compatible = "generic 1764 compatible = "generic-ohci";
1758 reg = <0 0xee080000 0 1765 reg = <0 0xee080000 0 0x100>;
1759 interrupts = <GIC_SPI 1766 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
1760 clocks = <&cpg CPG_MO 1767 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
1761 phys = <&usb2_phy0 1> 1768 phys = <&usb2_phy0 1>;
1762 phy-names = "usb"; 1769 phy-names = "usb";
1763 power-domains = <&sys 1770 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1764 resets = <&cpg 703>, 1771 resets = <&cpg 703>, <&cpg 704>;
1765 status = "disabled"; 1772 status = "disabled";
1766 }; 1773 };
1767 1774
1768 ehci0: usb@ee080100 { 1775 ehci0: usb@ee080100 {
1769 compatible = "generic 1776 compatible = "generic-ehci";
1770 reg = <0 0xee080100 0 1777 reg = <0 0xee080100 0 0x100>;
1771 interrupts = <GIC_SPI 1778 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
1772 clocks = <&cpg CPG_MO 1779 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
1773 phys = <&usb2_phy0 2> 1780 phys = <&usb2_phy0 2>;
1774 phy-names = "usb"; 1781 phy-names = "usb";
1775 companion = <&ohci0>; 1782 companion = <&ohci0>;
1776 power-domains = <&sys 1783 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1777 resets = <&cpg 703>, 1784 resets = <&cpg 703>, <&cpg 704>;
1778 status = "disabled"; 1785 status = "disabled";
1779 }; 1786 };
1780 1787
1781 usb2_phy0: usb-phy@ee080200 { 1788 usb2_phy0: usb-phy@ee080200 {
1782 compatible = "renesas 1789 compatible = "renesas,usb2-phy-r8a77990",
1783 "renesas 1790 "renesas,rcar-gen3-usb2-phy";
1784 reg = <0 0xee080200 0 1791 reg = <0 0xee080200 0 0x700>;
1785 interrupts = <GIC_SPI 1792 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
1786 clocks = <&cpg CPG_MO 1793 clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
1787 power-domains = <&sys 1794 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1788 resets = <&cpg 703>, 1795 resets = <&cpg 703>, <&cpg 704>;
1789 #phy-cells = <1>; 1796 #phy-cells = <1>;
1790 status = "disabled"; 1797 status = "disabled";
1791 }; 1798 };
1792 1799
1793 sdhi0: mmc@ee100000 { 1800 sdhi0: mmc@ee100000 {
1794 compatible = "renesas 1801 compatible = "renesas,sdhi-r8a77990",
1795 "renesas 1802 "renesas,rcar-gen3-sdhi";
1796 reg = <0 0xee100000 0 1803 reg = <0 0xee100000 0 0x2000>;
1797 interrupts = <GIC_SPI 1804 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
1798 clocks = <&cpg CPG_MO 1805 clocks = <&cpg CPG_MOD 314>, <&cpg CPG_CORE R8A77990_CLK_SD0H>;
1799 clock-names = "core", 1806 clock-names = "core", "clkh";
1800 max-frequency = <2000 1807 max-frequency = <200000000>;
1801 power-domains = <&sys 1808 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1802 resets = <&cpg 314>; 1809 resets = <&cpg 314>;
1803 iommus = <&ipmmu_ds1 1810 iommus = <&ipmmu_ds1 32>;
1804 status = "disabled"; 1811 status = "disabled";
1805 }; 1812 };
1806 1813
1807 sdhi1: mmc@ee120000 { 1814 sdhi1: mmc@ee120000 {
1808 compatible = "renesas 1815 compatible = "renesas,sdhi-r8a77990",
1809 "renesas 1816 "renesas,rcar-gen3-sdhi";
1810 reg = <0 0xee120000 0 1817 reg = <0 0xee120000 0 0x2000>;
1811 interrupts = <GIC_SPI 1818 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
1812 clocks = <&cpg CPG_MO 1819 clocks = <&cpg CPG_MOD 313>, <&cpg CPG_CORE R8A77990_CLK_SD1H>;
1813 clock-names = "core", 1820 clock-names = "core", "clkh";
1814 max-frequency = <2000 1821 max-frequency = <200000000>;
1815 power-domains = <&sys 1822 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1816 resets = <&cpg 313>; 1823 resets = <&cpg 313>;
1817 iommus = <&ipmmu_ds1 1824 iommus = <&ipmmu_ds1 33>;
1818 status = "disabled"; 1825 status = "disabled";
1819 }; 1826 };
1820 1827
1821 sdhi3: mmc@ee160000 { 1828 sdhi3: mmc@ee160000 {
1822 compatible = "renesas 1829 compatible = "renesas,sdhi-r8a77990",
1823 "renesas 1830 "renesas,rcar-gen3-sdhi";
1824 reg = <0 0xee160000 0 1831 reg = <0 0xee160000 0 0x2000>;
1825 interrupts = <GIC_SPI 1832 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
1826 clocks = <&cpg CPG_MO 1833 clocks = <&cpg CPG_MOD 311>, <&cpg CPG_CORE R8A77990_CLK_SD3H>;
1827 clock-names = "core", 1834 clock-names = "core", "clkh";
1828 max-frequency = <2000 1835 max-frequency = <200000000>;
1829 power-domains = <&sys 1836 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1830 resets = <&cpg 311>; 1837 resets = <&cpg 311>;
1831 iommus = <&ipmmu_ds1 1838 iommus = <&ipmmu_ds1 35>;
1832 status = "disabled"; 1839 status = "disabled";
1833 }; 1840 };
1834 1841
1835 rpc: spi@ee200000 { 1842 rpc: spi@ee200000 {
1836 compatible = "renesas 1843 compatible = "renesas,r8a77990-rpc-if",
1837 "renesas 1844 "renesas,rcar-gen3-rpc-if";
1838 reg = <0 0xee200000 0 1845 reg = <0 0xee200000 0 0x200>,
1839 <0 0x08000000 0 1846 <0 0x08000000 0 0x04000000>,
1840 <0 0xee208000 0 1847 <0 0xee208000 0 0x100>;
1841 reg-names = "regs", " 1848 reg-names = "regs", "dirmap", "wbuf";
1842 interrupts = <GIC_SPI 1849 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
1843 clocks = <&cpg CPG_MO 1850 clocks = <&cpg CPG_MOD 917>;
1844 power-domains = <&sys 1851 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1845 resets = <&cpg 917>; 1852 resets = <&cpg 917>;
1846 #address-cells = <1>; 1853 #address-cells = <1>;
1847 #size-cells = <0>; 1854 #size-cells = <0>;
1848 status = "disabled"; 1855 status = "disabled";
1849 }; 1856 };
1850 1857
1851 gic: interrupt-controller@f10 1858 gic: interrupt-controller@f1010000 {
1852 compatible = "arm,gic 1859 compatible = "arm,gic-400";
1853 #interrupt-cells = <3 1860 #interrupt-cells = <3>;
1854 #address-cells = <0>; 1861 #address-cells = <0>;
1855 interrupt-controller; 1862 interrupt-controller;
1856 reg = <0x0 0xf1010000 1863 reg = <0x0 0xf1010000 0 0x1000>,
1857 <0x0 0xf1020000 1864 <0x0 0xf1020000 0 0x20000>,
1858 <0x0 0xf1040000 1865 <0x0 0xf1040000 0 0x20000>,
1859 <0x0 0xf1060000 1866 <0x0 0xf1060000 0 0x20000>;
1860 interrupts = <GIC_PPI 1867 interrupts = <GIC_PPI 9
1861 (GIC_ 1868 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
1862 clocks = <&cpg CPG_MO 1869 clocks = <&cpg CPG_MOD 408>;
1863 clock-names = "clk"; 1870 clock-names = "clk";
1864 power-domains = <&sys 1871 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1865 resets = <&cpg 408>; 1872 resets = <&cpg 408>;
1866 }; 1873 };
1867 1874
1868 pciec0: pcie@fe000000 { 1875 pciec0: pcie@fe000000 {
1869 compatible = "renesas 1876 compatible = "renesas,pcie-r8a77990",
1870 "renesas 1877 "renesas,pcie-rcar-gen3";
1871 reg = <0 0xfe000000 0 1878 reg = <0 0xfe000000 0 0x80000>;
1872 #address-cells = <3>; 1879 #address-cells = <3>;
1873 #size-cells = <2>; 1880 #size-cells = <2>;
1874 bus-range = <0x00 0xf 1881 bus-range = <0x00 0xff>;
1875 device_type = "pci"; 1882 device_type = "pci";
1876 ranges = <0x01000000 1883 ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>,
1877 <0x02000000 1884 <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>,
1878 <0x02000000 1885 <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>,
1879 <0x42000000 1886 <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
1880 /* Map all possible D !! 1887 /* Map all possible DDR as inbound ranges */
1881 dma-ranges = <0x42000 !! 1888 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x40000000>;
1882 interrupts = <GIC_SPI 1889 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
1883 <GIC_SPI 1890 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
1884 <GIC_SPI 1891 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
1885 #interrupt-cells = <1 1892 #interrupt-cells = <1>;
1886 interrupt-map-mask = 1893 interrupt-map-mask = <0 0 0 0>;
1887 interrupt-map = <0 0 1894 interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
1888 clocks = <&cpg CPG_MO 1895 clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>;
1889 clock-names = "pcie", 1896 clock-names = "pcie", "pcie_bus";
1890 power-domains = <&sys 1897 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1891 resets = <&cpg 319>; 1898 resets = <&cpg 319>;
1892 iommu-map = <0 &ipmmu <<
1893 iommu-map-mask = <0>; <<
1894 status = "disabled"; 1899 status = "disabled";
1895 }; 1900 };
1896 1901
1897 vspb0: vsp@fe960000 { 1902 vspb0: vsp@fe960000 {
1898 compatible = "renesas 1903 compatible = "renesas,vsp2";
1899 reg = <0 0xfe960000 0 1904 reg = <0 0xfe960000 0 0x8000>;
1900 interrupts = <GIC_SPI 1905 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
1901 clocks = <&cpg CPG_MO 1906 clocks = <&cpg CPG_MOD 626>;
1902 power-domains = <&sys 1907 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1903 resets = <&cpg 626>; 1908 resets = <&cpg 626>;
1904 renesas,fcp = <&fcpvb 1909 renesas,fcp = <&fcpvb0>;
1905 }; 1910 };
1906 1911
1907 fcpvb0: fcp@fe96f000 { 1912 fcpvb0: fcp@fe96f000 {
1908 compatible = "renesas 1913 compatible = "renesas,fcpv";
1909 reg = <0 0xfe96f000 0 1914 reg = <0 0xfe96f000 0 0x200>;
1910 clocks = <&cpg CPG_MO 1915 clocks = <&cpg CPG_MOD 607>;
1911 power-domains = <&sys 1916 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1912 resets = <&cpg 607>; 1917 resets = <&cpg 607>;
1913 iommus = <&ipmmu_vp0 1918 iommus = <&ipmmu_vp0 5>;
1914 }; 1919 };
1915 1920
1916 vspi0: vsp@fe9a0000 { 1921 vspi0: vsp@fe9a0000 {
1917 compatible = "renesas 1922 compatible = "renesas,vsp2";
1918 reg = <0 0xfe9a0000 0 1923 reg = <0 0xfe9a0000 0 0x8000>;
1919 interrupts = <GIC_SPI 1924 interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>;
1920 clocks = <&cpg CPG_MO 1925 clocks = <&cpg CPG_MOD 631>;
1921 power-domains = <&sys 1926 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1922 resets = <&cpg 631>; 1927 resets = <&cpg 631>;
1923 renesas,fcp = <&fcpvi 1928 renesas,fcp = <&fcpvi0>;
1924 }; 1929 };
1925 1930
1926 fcpvi0: fcp@fe9af000 { 1931 fcpvi0: fcp@fe9af000 {
1927 compatible = "renesas 1932 compatible = "renesas,fcpv";
1928 reg = <0 0xfe9af000 0 1933 reg = <0 0xfe9af000 0 0x200>;
1929 clocks = <&cpg CPG_MO 1934 clocks = <&cpg CPG_MOD 611>;
1930 power-domains = <&sys 1935 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1931 resets = <&cpg 611>; 1936 resets = <&cpg 611>;
1932 iommus = <&ipmmu_vp0 1937 iommus = <&ipmmu_vp0 8>;
1933 }; 1938 };
1934 1939
1935 vspd0: vsp@fea20000 { 1940 vspd0: vsp@fea20000 {
1936 compatible = "renesas 1941 compatible = "renesas,vsp2";
1937 reg = <0 0xfea20000 0 1942 reg = <0 0xfea20000 0 0x7000>;
1938 interrupts = <GIC_SPI 1943 interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>;
1939 clocks = <&cpg CPG_MO 1944 clocks = <&cpg CPG_MOD 623>;
1940 power-domains = <&sys 1945 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1941 resets = <&cpg 623>; 1946 resets = <&cpg 623>;
1942 renesas,fcp = <&fcpvd 1947 renesas,fcp = <&fcpvd0>;
1943 }; 1948 };
1944 1949
1945 fcpvd0: fcp@fea27000 { 1950 fcpvd0: fcp@fea27000 {
1946 compatible = "renesas 1951 compatible = "renesas,fcpv";
1947 reg = <0 0xfea27000 0 1952 reg = <0 0xfea27000 0 0x200>;
1948 clocks = <&cpg CPG_MO 1953 clocks = <&cpg CPG_MOD 603>;
1949 power-domains = <&sys 1954 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1950 resets = <&cpg 603>; 1955 resets = <&cpg 603>;
1951 iommus = <&ipmmu_vi0 1956 iommus = <&ipmmu_vi0 8>;
1952 }; 1957 };
1953 1958
1954 vspd1: vsp@fea28000 { 1959 vspd1: vsp@fea28000 {
1955 compatible = "renesas 1960 compatible = "renesas,vsp2";
1956 reg = <0 0xfea28000 0 1961 reg = <0 0xfea28000 0 0x7000>;
1957 interrupts = <GIC_SPI 1962 interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>;
1958 clocks = <&cpg CPG_MO 1963 clocks = <&cpg CPG_MOD 622>;
1959 power-domains = <&sys 1964 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1960 resets = <&cpg 622>; 1965 resets = <&cpg 622>;
1961 renesas,fcp = <&fcpvd 1966 renesas,fcp = <&fcpvd1>;
1962 }; 1967 };
1963 1968
1964 fcpvd1: fcp@fea2f000 { 1969 fcpvd1: fcp@fea2f000 {
1965 compatible = "renesas 1970 compatible = "renesas,fcpv";
1966 reg = <0 0xfea2f000 0 1971 reg = <0 0xfea2f000 0 0x200>;
1967 clocks = <&cpg CPG_MO 1972 clocks = <&cpg CPG_MOD 602>;
1968 power-domains = <&sys 1973 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1969 resets = <&cpg 602>; 1974 resets = <&cpg 602>;
1970 iommus = <&ipmmu_vi0 1975 iommus = <&ipmmu_vi0 9>;
1971 }; 1976 };
1972 1977
1973 cmm0: cmm@fea40000 { 1978 cmm0: cmm@fea40000 {
1974 compatible = "renesas 1979 compatible = "renesas,r8a77990-cmm",
1975 "renesas 1980 "renesas,rcar-gen3-cmm";
1976 reg = <0 0xfea40000 0 1981 reg = <0 0xfea40000 0 0x1000>;
1977 power-domains = <&sys 1982 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1978 clocks = <&cpg CPG_MO 1983 clocks = <&cpg CPG_MOD 711>;
1979 resets = <&cpg 711>; 1984 resets = <&cpg 711>;
1980 }; 1985 };
1981 1986
1982 cmm1: cmm@fea50000 { 1987 cmm1: cmm@fea50000 {
1983 compatible = "renesas 1988 compatible = "renesas,r8a77990-cmm",
1984 "renesas 1989 "renesas,rcar-gen3-cmm";
1985 reg = <0 0xfea50000 0 1990 reg = <0 0xfea50000 0 0x1000>;
1986 power-domains = <&sys 1991 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1987 clocks = <&cpg CPG_MO 1992 clocks = <&cpg CPG_MOD 710>;
1988 resets = <&cpg 710>; 1993 resets = <&cpg 710>;
1989 }; 1994 };
1990 1995
1991 csi40: csi2@feaa0000 { 1996 csi40: csi2@feaa0000 {
1992 compatible = "renesas 1997 compatible = "renesas,r8a77990-csi2";
1993 reg = <0 0xfeaa0000 0 1998 reg = <0 0xfeaa0000 0 0x10000>;
1994 interrupts = <GIC_SPI 1999 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
1995 clocks = <&cpg CPG_MO 2000 clocks = <&cpg CPG_MOD 716>;
1996 power-domains = <&sys 2001 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1997 resets = <&cpg 716>; 2002 resets = <&cpg 716>;
1998 status = "disabled"; 2003 status = "disabled";
1999 2004
2000 ports { 2005 ports {
2001 #address-cell 2006 #address-cells = <1>;
2002 #size-cells = 2007 #size-cells = <0>;
2003 2008
2004 port@0 { 2009 port@0 {
2005 reg = 2010 reg = <0>;
2006 }; 2011 };
2007 2012
2008 port@1 { 2013 port@1 {
2009 #addr 2014 #address-cells = <1>;
2010 #size 2015 #size-cells = <0>;
2011 2016
2012 reg = 2017 reg = <1>;
2013 2018
2014 csi40 2019 csi40vin4: endpoint@0 {
2015 2020 reg = <0>;
2016 2021 remote-endpoint = <&vin4csi40>;
2017 }; 2022 };
2018 csi40 2023 csi40vin5: endpoint@1 {
2019 2024 reg = <1>;
2020 2025 remote-endpoint = <&vin5csi40>;
2021 }; 2026 };
2022 }; 2027 };
2023 }; 2028 };
2024 }; 2029 };
2025 2030
2026 du: display@feb00000 { 2031 du: display@feb00000 {
2027 compatible = "renesas 2032 compatible = "renesas,du-r8a77990";
2028 reg = <0 0xfeb00000 0 2033 reg = <0 0xfeb00000 0 0x40000>;
2029 interrupts = <GIC_SPI 2034 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
2030 <GIC_SPI 2035 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
2031 clocks = <&cpg CPG_MO 2036 clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>;
2032 clock-names = "du.0", 2037 clock-names = "du.0", "du.1";
2033 resets = <&cpg 724>; 2038 resets = <&cpg 724>;
2034 reset-names = "du.0"; 2039 reset-names = "du.0";
2035 2040
2036 renesas,cmms = <&cmm0 2041 renesas,cmms = <&cmm0>, <&cmm1>;
2037 renesas,vsps = <&vspd 2042 renesas,vsps = <&vspd0 0>, <&vspd1 0>;
2038 2043
2039 status = "disabled"; 2044 status = "disabled";
2040 2045
2041 ports { 2046 ports {
2042 #address-cell 2047 #address-cells = <1>;
2043 #size-cells = 2048 #size-cells = <0>;
2044 2049
2045 port@0 { 2050 port@0 {
2046 reg = 2051 reg = <0>;
2047 }; 2052 };
2048 2053
2049 port@1 { 2054 port@1 {
2050 reg = 2055 reg = <1>;
2051 du_ou 2056 du_out_lvds0: endpoint {
2052 2057 remote-endpoint = <&lvds0_in>;
2053 }; 2058 };
2054 }; 2059 };
2055 2060
2056 port@2 { 2061 port@2 {
2057 reg = 2062 reg = <2>;
2058 du_ou 2063 du_out_lvds1: endpoint {
2059 2064 remote-endpoint = <&lvds1_in>;
2060 }; 2065 };
2061 }; 2066 };
2062 }; 2067 };
2063 }; 2068 };
2064 2069
2065 lvds0: lvds-encoder@feb90000 2070 lvds0: lvds-encoder@feb90000 {
2066 compatible = "renesas 2071 compatible = "renesas,r8a77990-lvds";
2067 reg = <0 0xfeb90000 0 2072 reg = <0 0xfeb90000 0 0x20>;
2068 clocks = <&cpg CPG_MO 2073 clocks = <&cpg CPG_MOD 727>;
2069 power-domains = <&sys 2074 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
2070 resets = <&cpg 727>; 2075 resets = <&cpg 727>;
2071 status = "disabled"; 2076 status = "disabled";
2072 2077
2073 renesas,companion = < 2078 renesas,companion = <&lvds1>;
2074 2079
2075 ports { 2080 ports {
2076 #address-cell 2081 #address-cells = <1>;
2077 #size-cells = 2082 #size-cells = <0>;
2078 2083
2079 port@0 { 2084 port@0 {
2080 reg = 2085 reg = <0>;
2081 lvds0 2086 lvds0_in: endpoint {
2082 2087 remote-endpoint = <&du_out_lvds0>;
2083 }; 2088 };
2084 }; 2089 };
2085 2090
2086 port@1 { 2091 port@1 {
2087 reg = 2092 reg = <1>;
2088 }; 2093 };
2089 }; 2094 };
2090 }; 2095 };
2091 2096
2092 lvds1: lvds-encoder@feb90100 2097 lvds1: lvds-encoder@feb90100 {
2093 compatible = "renesas 2098 compatible = "renesas,r8a77990-lvds";
2094 reg = <0 0xfeb90100 0 2099 reg = <0 0xfeb90100 0 0x20>;
2095 clocks = <&cpg CPG_MO 2100 clocks = <&cpg CPG_MOD 727>;
2096 power-domains = <&sys 2101 power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
2097 resets = <&cpg 726>; 2102 resets = <&cpg 726>;
2098 status = "disabled"; 2103 status = "disabled";
2099 2104
2100 ports { 2105 ports {
2101 #address-cell 2106 #address-cells = <1>;
2102 #size-cells = 2107 #size-cells = <0>;
2103 2108
2104 port@0 { 2109 port@0 {
2105 reg = 2110 reg = <0>;
2106 lvds1 2111 lvds1_in: endpoint {
2107 2112 remote-endpoint = <&du_out_lvds1>;
2108 }; 2113 };
2109 }; 2114 };
2110 2115
2111 port@1 { 2116 port@1 {
2112 reg = 2117 reg = <1>;
2113 }; 2118 };
2114 }; 2119 };
2115 }; 2120 };
2116 2121
2117 prr: chipid@fff00044 { 2122 prr: chipid@fff00044 {
2118 compatible = "renesas 2123 compatible = "renesas,prr";
2119 reg = <0 0xfff00044 0 2124 reg = <0 0xfff00044 0 4>;
2120 }; 2125 };
2121 }; 2126 };
2122 2127
2123 thermal-zones { 2128 thermal-zones {
2124 cpu-thermal { 2129 cpu-thermal {
2125 polling-delay-passive 2130 polling-delay-passive = <250>;
2126 polling-delay = <0>; 2131 polling-delay = <0>;
2127 thermal-sensors = <&t 2132 thermal-sensors = <&thermal>;
2128 sustainable-power = < 2133 sustainable-power = <717>;
2129 2134
2130 cooling-maps { 2135 cooling-maps {
2131 map0 { 2136 map0 {
2132 trip 2137 trip = <&target>;
2133 cooli 2138 cooling-device = <&a53_0 0 2>;
2134 contr 2139 contribution = <1024>;
2135 }; 2140 };
2136 }; 2141 };
2137 2142
2138 trips { 2143 trips {
2139 sensor1_crit: 2144 sensor1_crit: sensor1-crit {
2140 tempe 2145 temperature = <120000>;
2141 hyste 2146 hysteresis = <2000>;
2142 type 2147 type = "critical";
2143 }; 2148 };
2144 2149
2145 target: trip- 2150 target: trip-point1 {
2146 tempe 2151 temperature = <100000>;
2147 hyste 2152 hysteresis = <2000>;
2148 type 2153 type = "passive";
2149 }; 2154 };
2150 }; 2155 };
2151 }; 2156 };
2152 }; 2157 };
2153 2158
2154 timer { 2159 timer {
2155 compatible = "arm,armv8-timer 2160 compatible = "arm,armv8-timer";
2156 interrupts-extended = <&gic G 2161 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
2157 <&gic G 2162 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
2158 <&gic G 2163 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
2159 <&gic G 2164 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
2160 interrupt-names = "sec-phys", <<
2161 }; 2165 };
2162 }; 2166 };
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