1 // SPDX-License-Identifier: GPL-2.0 1 // SPDX-License-Identifier: GPL-2.0
2 /* 2 /*
3 * Device Tree Source for the Falcon CPU and B 3 * Device Tree Source for the Falcon CPU and BreakOut boards with R-Car V3U
4 * 4 *
5 * Copyright (C) 2020 Renesas Electronics Corp 5 * Copyright (C) 2020 Renesas Electronics Corp.
6 */ 6 */
7 7
8 /dts-v1/; 8 /dts-v1/;
9 #include "r8a779a0-falcon-cpu.dtsi" 9 #include "r8a779a0-falcon-cpu.dtsi"
10 #include "r8a779a0-falcon-csi-dsi.dtsi" 10 #include "r8a779a0-falcon-csi-dsi.dtsi"
11 #include "r8a779a0-falcon-ethernet.dtsi" 11 #include "r8a779a0-falcon-ethernet.dtsi"
12 12
13 / { 13 / {
14 model = "Renesas Falcon CPU and Breako 14 model = "Renesas Falcon CPU and Breakout boards based on r8a779a0";
15 compatible = "renesas,falcon-breakout" 15 compatible = "renesas,falcon-breakout", "renesas,falcon-cpu", "renesas,r8a779a0";
16 16
17 aliases { 17 aliases {
18 ethernet0 = &avb0; 18 ethernet0 = &avb0;
19 }; 19 };
20 }; 20 };
21 21
22 &avb0 { 22 &avb0 {
23 pinctrl-0 = <&avb0_pins>; 23 pinctrl-0 = <&avb0_pins>;
24 pinctrl-names = "default"; 24 pinctrl-names = "default";
25 phy-handle = <&phy0>; 25 phy-handle = <&phy0>;
26 tx-internal-delay-ps = <2000>; 26 tx-internal-delay-ps = <2000>;
27 status = "okay"; 27 status = "okay";
28 28
29 phy0: ethernet-phy@0 { 29 phy0: ethernet-phy@0 {
30 compatible = "ethernet-phy-id0 30 compatible = "ethernet-phy-id0022.1622",
31 "ethernet-phy-iee 31 "ethernet-phy-ieee802.3-c22";
32 rxc-skew-ps = <1500>; 32 rxc-skew-ps = <1500>;
33 reg = <0>; 33 reg = <0>;
34 interrupt-parent = <&gpio4>; 34 interrupt-parent = <&gpio4>;
35 interrupts = <16 IRQ_TYPE_LEVE 35 interrupts = <16 IRQ_TYPE_LEVEL_LOW>;
36 reset-gpios = <&gpio4 15 GPIO_ 36 reset-gpios = <&gpio4 15 GPIO_ACTIVE_LOW>;
37 }; 37 };
38 }; 38 };
39 39
40 &can_clk { <<
41 clock-frequency = <40000000>; <<
42 }; <<
43 <<
44 &canfd { 40 &canfd {
45 pinctrl-0 = <&canfd0_pins>, <&canfd1_p !! 41 pinctrl-0 = <&canfd0_pins>, <&canfd1_pins>;
46 pinctrl-names = "default"; 42 pinctrl-names = "default";
47 status = "okay"; 43 status = "okay";
48 44
49 channel0 { 45 channel0 {
50 status = "okay"; 46 status = "okay";
51 }; 47 };
52 48
53 channel1 { 49 channel1 {
54 status = "okay"; 50 status = "okay";
55 }; 51 };
56 }; 52 };
57 53
58 &i2c0 { 54 &i2c0 {
59 eeprom@51 { 55 eeprom@51 {
60 compatible = "rohm,br24g01", " 56 compatible = "rohm,br24g01", "atmel,24c01";
61 label = "breakout-board"; 57 label = "breakout-board";
62 reg = <0x51>; 58 reg = <0x51>;
63 pagesize = <8>; 59 pagesize = <8>;
64 }; 60 };
65 }; 61 };
66 62
67 &pfc { 63 &pfc {
68 avb0_pins: avb0 { 64 avb0_pins: avb0 {
69 mux { 65 mux {
70 groups = "avb0_link", 66 groups = "avb0_link", "avb0_mdio", "avb0_rgmii",
71 "avb0_txcrefc 67 "avb0_txcrefclk";
72 function = "avb0"; 68 function = "avb0";
73 }; 69 };
74 70
75 pins_mdio { 71 pins_mdio {
76 groups = "avb0_mdio"; 72 groups = "avb0_mdio";
77 drive-strength = <21>; 73 drive-strength = <21>;
78 }; 74 };
79 75
80 pins_mii { 76 pins_mii {
81 groups = "avb0_rgmii"; 77 groups = "avb0_rgmii";
82 drive-strength = <21>; 78 drive-strength = <21>;
83 }; 79 };
84 80
85 }; <<
86 <<
87 can_clk_pins: can-clk { <<
88 groups = "can_clk"; <<
89 function = "can_clk"; <<
90 }; 81 };
91 82
92 canfd0_pins: canfd0 { 83 canfd0_pins: canfd0 {
93 groups = "canfd0_data"; 84 groups = "canfd0_data";
94 function = "canfd0"; 85 function = "canfd0";
95 }; 86 };
96 87
97 canfd1_pins: canfd1 { 88 canfd1_pins: canfd1 {
98 groups = "canfd1_data"; 89 groups = "canfd1_data";
99 function = "canfd1"; 90 function = "canfd1";
100 }; 91 };
101 }; 92 };
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