1 // SPDX-License-Identifier: GPL-2.0 1 // SPDX-License-Identifier: GPL-2.0
2 /* 2 /*
3 * Device Tree Source for the R-Car V3U (R8A77 3 * Device Tree Source for the R-Car V3U (R8A779A0) SoC
4 * 4 *
5 * Copyright (C) 2020 Renesas Electronics Corp 5 * Copyright (C) 2020 Renesas Electronics Corp.
6 */ 6 */
7 7
8 #include <dt-bindings/clock/r8a779a0-cpg-mssr. 8 #include <dt-bindings/clock/r8a779a0-cpg-mssr.h>
9 #include <dt-bindings/interrupt-controller/arm 9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/power/r8a779a0-sysc.h> 10 #include <dt-bindings/power/r8a779a0-sysc.h>
11 11
12 / { 12 / {
13 compatible = "renesas,r8a779a0"; 13 compatible = "renesas,r8a779a0";
14 #address-cells = <2>; 14 #address-cells = <2>;
15 #size-cells = <2>; 15 #size-cells = <2>;
16 16
17 /* External CAN clock - to be overridd !! 17 aliases {
18 can_clk: can { !! 18 i2c0 = &i2c0;
19 compatible = "fixed-clock"; !! 19 i2c1 = &i2c1;
20 #clock-cells = <0>; !! 20 i2c2 = &i2c2;
21 clock-frequency = <0>; !! 21 i2c3 = &i2c3;
>> 22 i2c4 = &i2c4;
>> 23 i2c5 = &i2c5;
>> 24 i2c6 = &i2c6;
22 }; 25 };
23 26
24 cpus { 27 cpus {
25 #address-cells = <1>; 28 #address-cells = <1>;
26 #size-cells = <0>; 29 #size-cells = <0>;
27 30
28 a76_0: cpu@0 { 31 a76_0: cpu@0 {
29 compatible = "arm,cort 32 compatible = "arm,cortex-a76";
30 reg = <0>; 33 reg = <0>;
31 device_type = "cpu"; 34 device_type = "cpu";
32 power-domains = <&sysc 35 power-domains = <&sysc R8A779A0_PD_A1E0D0C0>;
33 next-level-cache = <&L 36 next-level-cache = <&L3_CA76_0>;
34 clocks = <&cpg CPG_COR <<
35 }; 37 };
36 38
37 L3_CA76_0: cache-controller-0 39 L3_CA76_0: cache-controller-0 {
38 compatible = "cache"; 40 compatible = "cache";
39 power-domains = <&sysc 41 power-domains = <&sysc R8A779A0_PD_A2E0D0>;
40 cache-unified; 42 cache-unified;
41 cache-level = <3>; 43 cache-level = <3>;
42 }; 44 };
43 }; 45 };
44 46
45 extal_clk: extal { 47 extal_clk: extal {
46 compatible = "fixed-clock"; 48 compatible = "fixed-clock";
47 #clock-cells = <0>; 49 #clock-cells = <0>;
48 /* This value must be overridd 50 /* This value must be overridden by the board */
49 clock-frequency = <0>; 51 clock-frequency = <0>;
50 }; 52 };
51 53
52 extalr_clk: extalr { 54 extalr_clk: extalr {
53 compatible = "fixed-clock"; 55 compatible = "fixed-clock";
54 #clock-cells = <0>; 56 #clock-cells = <0>;
55 /* This value must be overridd 57 /* This value must be overridden by the board */
56 clock-frequency = <0>; 58 clock-frequency = <0>;
57 }; 59 };
58 60
59 pmu_a76 { 61 pmu_a76 {
60 compatible = "arm,cortex-a76-p 62 compatible = "arm,cortex-a76-pmu";
61 interrupts-extended = <&gic GI 63 interrupts-extended = <&gic GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
62 }; 64 };
63 65
64 /* External SCIF clock - to be overrid 66 /* External SCIF clock - to be overridden by boards that provide it */
65 scif_clk: scif { 67 scif_clk: scif {
66 compatible = "fixed-clock"; 68 compatible = "fixed-clock";
67 #clock-cells = <0>; 69 #clock-cells = <0>;
68 clock-frequency = <0>; 70 clock-frequency = <0>;
69 }; 71 };
70 72
71 soc: soc { 73 soc: soc {
72 compatible = "simple-bus"; 74 compatible = "simple-bus";
73 interrupt-parent = <&gic>; 75 interrupt-parent = <&gic>;
74 #address-cells = <2>; 76 #address-cells = <2>;
75 #size-cells = <2>; 77 #size-cells = <2>;
76 ranges; 78 ranges;
77 79
78 rwdt: watchdog@e6020000 { 80 rwdt: watchdog@e6020000 {
79 compatible = "renesas, 81 compatible = "renesas,r8a779a0-wdt",
80 "renesas, !! 82 "renesas,rcar-gen3-wdt";
81 reg = <0 0xe6020000 0 83 reg = <0 0xe6020000 0 0x0c>;
82 interrupts = <GIC_SPI <<
83 clocks = <&cpg CPG_MOD 84 clocks = <&cpg CPG_MOD 907>;
84 power-domains = <&sysc 85 power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
85 resets = <&cpg 907>; 86 resets = <&cpg 907>;
86 status = "disabled"; 87 status = "disabled";
87 }; 88 };
88 89
89 pfc: pinctrl@e6050000 { !! 90 pfc: pin-controller@e6050000 {
90 compatible = "renesas, 91 compatible = "renesas,pfc-r8a779a0";
91 reg = <0 0xe6050000 0 92 reg = <0 0xe6050000 0 0x16c>, <0 0xe6050800 0 0x16c>,
92 <0 0xe6058000 0 93 <0 0xe6058000 0 0x16c>, <0 0xe6058800 0 0x16c>,
93 <0 0xe6060000 0 94 <0 0xe6060000 0 0x16c>, <0 0xe6060800 0 0x16c>,
94 <0 0xe6068000 0 95 <0 0xe6068000 0 0x16c>, <0 0xe6068800 0 0x16c>,
95 <0 0xe6069000 0 96 <0 0xe6069000 0 0x16c>, <0 0xe6069800 0 0x16c>;
96 }; 97 };
97 98
98 gpio0: gpio@e6058180 { 99 gpio0: gpio@e6058180 {
99 compatible = "renesas, !! 100 compatible = "renesas,gpio-r8a779a0";
100 "renesas, <<
101 reg = <0 0xe6058180 0 101 reg = <0 0xe6058180 0 0x54>;
102 interrupts = <GIC_SPI 102 interrupts = <GIC_SPI 832 IRQ_TYPE_LEVEL_HIGH>;
103 clocks = <&cpg CPG_MOD 103 clocks = <&cpg CPG_MOD 916>;
104 power-domains = <&sysc 104 power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
105 resets = <&cpg 916>; !! 105 resets = <&cpg 916>;
106 gpio-controller; 106 gpio-controller;
107 #gpio-cells = <2>; 107 #gpio-cells = <2>;
108 gpio-ranges = <&pfc 0 108 gpio-ranges = <&pfc 0 0 28>;
109 interrupt-controller; 109 interrupt-controller;
110 #interrupt-cells = <2> 110 #interrupt-cells = <2>;
111 }; 111 };
112 112
113 gpio1: gpio@e6050180 { 113 gpio1: gpio@e6050180 {
114 compatible = "renesas, !! 114 compatible = "renesas,gpio-r8a779a0";
115 "renesas, <<
116 reg = <0 0xe6050180 0 115 reg = <0 0xe6050180 0 0x54>;
117 interrupts = <GIC_SPI 116 interrupts = <GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>;
118 clocks = <&cpg CPG_MOD 117 clocks = <&cpg CPG_MOD 915>;
119 power-domains = <&sysc 118 power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
120 resets = <&cpg 915>; !! 119 resets = <&cpg 915>;
121 gpio-controller; 120 gpio-controller;
122 #gpio-cells = <2>; 121 #gpio-cells = <2>;
123 gpio-ranges = <&pfc 0 122 gpio-ranges = <&pfc 0 32 31>;
124 interrupt-controller; 123 interrupt-controller;
125 #interrupt-cells = <2> 124 #interrupt-cells = <2>;
126 }; 125 };
127 126
128 gpio2: gpio@e6050980 { 127 gpio2: gpio@e6050980 {
129 compatible = "renesas, !! 128 compatible = "renesas,gpio-r8a779a0";
130 "renesas, <<
131 reg = <0 0xe6050980 0 129 reg = <0 0xe6050980 0 0x54>;
132 interrupts = <GIC_SPI 130 interrupts = <GIC_SPI 840 IRQ_TYPE_LEVEL_HIGH>;
133 clocks = <&cpg CPG_MOD 131 clocks = <&cpg CPG_MOD 915>;
134 power-domains = <&sysc 132 power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
135 resets = <&cpg 915>; !! 133 resets = <&cpg 915>;
136 gpio-controller; 134 gpio-controller;
137 #gpio-cells = <2>; 135 #gpio-cells = <2>;
138 gpio-ranges = <&pfc 0 136 gpio-ranges = <&pfc 0 64 25>;
139 interrupt-controller; 137 interrupt-controller;
140 #interrupt-cells = <2> 138 #interrupt-cells = <2>;
141 }; 139 };
142 140
143 gpio3: gpio@e6058980 { 141 gpio3: gpio@e6058980 {
144 compatible = "renesas, !! 142 compatible = "renesas,gpio-r8a779a0";
145 "renesas, <<
146 reg = <0 0xe6058980 0 143 reg = <0 0xe6058980 0 0x54>;
147 interrupts = <GIC_SPI 144 interrupts = <GIC_SPI 844 IRQ_TYPE_LEVEL_HIGH>;
148 clocks = <&cpg CPG_MOD 145 clocks = <&cpg CPG_MOD 916>;
149 power-domains = <&sysc 146 power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
150 resets = <&cpg 916>; !! 147 resets = <&cpg 916>;
151 gpio-controller; 148 gpio-controller;
152 #gpio-cells = <2>; 149 #gpio-cells = <2>;
153 gpio-ranges = <&pfc 0 150 gpio-ranges = <&pfc 0 96 17>;
154 interrupt-controller; 151 interrupt-controller;
155 #interrupt-cells = <2> 152 #interrupt-cells = <2>;
156 }; 153 };
157 154
158 gpio4: gpio@e6060180 { 155 gpio4: gpio@e6060180 {
159 compatible = "renesas, !! 156 compatible = "renesas,gpio-r8a779a0";
160 "renesas, <<
161 reg = <0 0xe6060180 0 157 reg = <0 0xe6060180 0 0x54>;
162 interrupts = <GIC_SPI 158 interrupts = <GIC_SPI 848 IRQ_TYPE_LEVEL_HIGH>;
163 clocks = <&cpg CPG_MOD 159 clocks = <&cpg CPG_MOD 917>;
164 power-domains = <&sysc 160 power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
165 resets = <&cpg 917>; !! 161 resets = <&cpg 917>;
166 gpio-controller; 162 gpio-controller;
167 #gpio-cells = <2>; 163 #gpio-cells = <2>;
168 gpio-ranges = <&pfc 0 164 gpio-ranges = <&pfc 0 128 27>;
169 interrupt-controller; 165 interrupt-controller;
170 #interrupt-cells = <2> 166 #interrupt-cells = <2>;
171 }; 167 };
172 168
173 gpio5: gpio@e6060980 { 169 gpio5: gpio@e6060980 {
174 compatible = "renesas, !! 170 compatible = "renesas,gpio-r8a779a0";
175 "renesas, <<
176 reg = <0 0xe6060980 0 171 reg = <0 0xe6060980 0 0x54>;
177 interrupts = <GIC_SPI 172 interrupts = <GIC_SPI 852 IRQ_TYPE_LEVEL_HIGH>;
178 clocks = <&cpg CPG_MOD 173 clocks = <&cpg CPG_MOD 917>;
179 power-domains = <&sysc 174 power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
180 resets = <&cpg 917>; !! 175 resets = <&cpg 917>;
181 gpio-controller; 176 gpio-controller;
182 #gpio-cells = <2>; 177 #gpio-cells = <2>;
183 gpio-ranges = <&pfc 0 178 gpio-ranges = <&pfc 0 160 21>;
184 interrupt-controller; 179 interrupt-controller;
185 #interrupt-cells = <2> 180 #interrupt-cells = <2>;
186 }; 181 };
187 182
188 gpio6: gpio@e6068180 { 183 gpio6: gpio@e6068180 {
189 compatible = "renesas, !! 184 compatible = "renesas,gpio-r8a779a0";
190 "renesas, <<
191 reg = <0 0xe6068180 0 185 reg = <0 0xe6068180 0 0x54>;
192 interrupts = <GIC_SPI 186 interrupts = <GIC_SPI 856 IRQ_TYPE_LEVEL_HIGH>;
193 clocks = <&cpg CPG_MOD 187 clocks = <&cpg CPG_MOD 918>;
194 power-domains = <&sysc 188 power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
195 resets = <&cpg 918>; !! 189 resets = <&cpg 918>;
196 gpio-controller; 190 gpio-controller;
197 #gpio-cells = <2>; 191 #gpio-cells = <2>;
198 gpio-ranges = <&pfc 0 192 gpio-ranges = <&pfc 0 192 21>;
199 interrupt-controller; 193 interrupt-controller;
200 #interrupt-cells = <2> 194 #interrupt-cells = <2>;
201 }; 195 };
202 196
203 gpio7: gpio@e6068980 { 197 gpio7: gpio@e6068980 {
204 compatible = "renesas, !! 198 compatible = "renesas,gpio-r8a779a0";
205 "renesas, <<
206 reg = <0 0xe6068980 0 199 reg = <0 0xe6068980 0 0x54>;
207 interrupts = <GIC_SPI 200 interrupts = <GIC_SPI 860 IRQ_TYPE_LEVEL_HIGH>;
208 clocks = <&cpg CPG_MOD 201 clocks = <&cpg CPG_MOD 918>;
209 power-domains = <&sysc 202 power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
210 resets = <&cpg 918>; !! 203 resets = <&cpg 918>;
211 gpio-controller; 204 gpio-controller;
212 #gpio-cells = <2>; 205 #gpio-cells = <2>;
213 gpio-ranges = <&pfc 0 206 gpio-ranges = <&pfc 0 224 21>;
214 interrupt-controller; 207 interrupt-controller;
215 #interrupt-cells = <2> 208 #interrupt-cells = <2>;
216 }; 209 };
217 210
218 gpio8: gpio@e6069180 { 211 gpio8: gpio@e6069180 {
219 compatible = "renesas, !! 212 compatible = "renesas,gpio-r8a779a0";
220 "renesas, <<
221 reg = <0 0xe6069180 0 213 reg = <0 0xe6069180 0 0x54>;
222 interrupts = <GIC_SPI 214 interrupts = <GIC_SPI 864 IRQ_TYPE_LEVEL_HIGH>;
223 clocks = <&cpg CPG_MOD 215 clocks = <&cpg CPG_MOD 918>;
224 power-domains = <&sysc 216 power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
225 resets = <&cpg 918>; !! 217 resets = <&cpg 918>;
226 gpio-controller; 218 gpio-controller;
227 #gpio-cells = <2>; 219 #gpio-cells = <2>;
228 gpio-ranges = <&pfc 0 220 gpio-ranges = <&pfc 0 256 21>;
229 interrupt-controller; 221 interrupt-controller;
230 #interrupt-cells = <2> 222 #interrupt-cells = <2>;
231 }; 223 };
232 224
233 gpio9: gpio@e6069980 { 225 gpio9: gpio@e6069980 {
234 compatible = "renesas, !! 226 compatible = "renesas,gpio-r8a779a0";
235 "renesas, <<
236 reg = <0 0xe6069980 0 227 reg = <0 0xe6069980 0 0x54>;
237 interrupts = <GIC_SPI 228 interrupts = <GIC_SPI 868 IRQ_TYPE_LEVEL_HIGH>;
238 clocks = <&cpg CPG_MOD 229 clocks = <&cpg CPG_MOD 918>;
239 power-domains = <&sysc 230 power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
240 resets = <&cpg 918>; !! 231 resets = <&cpg 918>;
241 gpio-controller; 232 gpio-controller;
242 #gpio-cells = <2>; 233 #gpio-cells = <2>;
243 gpio-ranges = <&pfc 0 234 gpio-ranges = <&pfc 0 288 21>;
244 interrupt-controller; 235 interrupt-controller;
245 #interrupt-cells = <2> 236 #interrupt-cells = <2>;
246 }; 237 };
247 238
248 cmt0: timer@e60f0000 { <<
249 compatible = "renesas, <<
250 "renesas, <<
251 reg = <0 0xe60f0000 0 <<
252 interrupts = <GIC_SPI <<
253 <GIC_SPI <<
254 clocks = <&cpg CPG_MOD <<
255 clock-names = "fck"; <<
256 power-domains = <&sysc <<
257 resets = <&cpg 910>; <<
258 status = "disabled"; <<
259 }; <<
260 <<
261 cmt1: timer@e6130000 { <<
262 compatible = "renesas, <<
263 "renesas, <<
264 reg = <0 0xe6130000 0 <<
265 interrupts = <GIC_SPI <<
266 <GIC_SPI <<
267 <GIC_SPI <<
268 <GIC_SPI <<
269 <GIC_SPI <<
270 <GIC_SPI <<
271 <GIC_SPI <<
272 <GIC_SPI <<
273 clocks = <&cpg CPG_MOD <<
274 clock-names = "fck"; <<
275 power-domains = <&sysc <<
276 resets = <&cpg 911>; <<
277 status = "disabled"; <<
278 }; <<
279 <<
280 cmt2: timer@e6140000 { <<
281 compatible = "renesas, <<
282 "renesas, <<
283 reg = <0 0xe6140000 0 <<
284 interrupts = <GIC_SPI <<
285 <GIC_SPI <<
286 <GIC_SPI <<
287 <GIC_SPI <<
288 <GIC_SPI <<
289 <GIC_SPI <<
290 <GIC_SPI <<
291 <GIC_SPI <<
292 clocks = <&cpg CPG_MOD <<
293 clock-names = "fck"; <<
294 power-domains = <&sysc <<
295 resets = <&cpg 912>; <<
296 status = "disabled"; <<
297 }; <<
298 <<
299 cmt3: timer@e6148000 { <<
300 compatible = "renesas, <<
301 "renesas, <<
302 reg = <0 0xe6148000 0 <<
303 interrupts = <GIC_SPI <<
304 <GIC_SPI <<
305 <GIC_SPI <<
306 <GIC_SPI <<
307 <GIC_SPI <<
308 <GIC_SPI <<
309 <GIC_SPI <<
310 <GIC_SPI <<
311 clocks = <&cpg CPG_MOD <<
312 clock-names = "fck"; <<
313 power-domains = <&sysc <<
314 resets = <&cpg 913>; <<
315 status = "disabled"; <<
316 }; <<
317 <<
318 cpg: clock-controller@e6150000 239 cpg: clock-controller@e6150000 {
319 compatible = "renesas, 240 compatible = "renesas,r8a779a0-cpg-mssr";
320 reg = <0 0xe6150000 0 241 reg = <0 0xe6150000 0 0x4000>;
321 clocks = <&extal_clk>, 242 clocks = <&extal_clk>, <&extalr_clk>;
322 clock-names = "extal", 243 clock-names = "extal", "extalr";
323 #clock-cells = <2>; 244 #clock-cells = <2>;
324 #power-domain-cells = 245 #power-domain-cells = <0>;
325 #reset-cells = <1>; 246 #reset-cells = <1>;
326 }; 247 };
327 248
328 rst: reset-controller@e6160000 249 rst: reset-controller@e6160000 {
329 compatible = "renesas, 250 compatible = "renesas,r8a779a0-rst";
330 reg = <0 0xe6160000 0 251 reg = <0 0xe6160000 0 0x4000>;
331 }; 252 };
332 253
333 sysc: system-controller@e61800 254 sysc: system-controller@e6180000 {
334 compatible = "renesas, 255 compatible = "renesas,r8a779a0-sysc";
335 reg = <0 0xe6180000 0 256 reg = <0 0xe6180000 0 0x4000>;
336 #power-domain-cells = 257 #power-domain-cells = <1>;
337 }; 258 };
338 259
339 tsc: thermal@e6190000 { <<
340 compatible = "renesas, <<
341 reg = <0 0xe6190000 0 <<
342 <0 0xe6198000 0 <<
343 <0 0xe61a0000 0 <<
344 <0 0xe61a8000 0 <<
345 <0 0xe61b0000 0 <<
346 clocks = <&cpg CPG_MOD <<
347 power-domains = <&sysc <<
348 resets = <&cpg 919>; <<
349 #thermal-sensor-cells <<
350 }; <<
351 <<
352 intc_ex: interrupt-controller@ <<
353 compatible = "renesas, <<
354 #interrupt-cells = <2> <<
355 interrupt-controller; <<
356 reg = <0 0xe61c0000 0 <<
357 interrupts = <GIC_SPI <<
358 <GIC_SPI <<
359 <GIC_SPI <<
360 <GIC_SPI <<
361 <GIC_SPI <<
362 <GIC_SPI <<
363 clocks = <&cpg CPG_COR <<
364 power-domains = <&sysc <<
365 }; <<
366 <<
367 tmu0: timer@e61e0000 { <<
368 compatible = "renesas, <<
369 reg = <0 0xe61e0000 0 <<
370 interrupts = <GIC_SPI <<
371 <GIC_SPI <<
372 <GIC_SPI <<
373 interrupt-names = "tun <<
374 clocks = <&cpg CPG_MOD <<
375 clock-names = "fck"; <<
376 power-domains = <&sysc <<
377 resets = <&cpg 713>; <<
378 status = "disabled"; <<
379 }; <<
380 <<
381 tmu1: timer@e6fc0000 { <<
382 compatible = "renesas, <<
383 reg = <0 0xe6fc0000 0 <<
384 interrupts = <GIC_SPI <<
385 <GIC_SPI <<
386 <GIC_SPI <<
387 <GIC_SPI <<
388 interrupt-names = "tun <<
389 clocks = <&cpg CPG_MOD <<
390 clock-names = "fck"; <<
391 power-domains = <&sysc <<
392 resets = <&cpg 714>; <<
393 status = "disabled"; <<
394 }; <<
395 <<
396 tmu2: timer@e6fd0000 { <<
397 compatible = "renesas, <<
398 reg = <0 0xe6fd0000 0 <<
399 interrupts = <GIC_SPI <<
400 <GIC_SPI <<
401 <GIC_SPI <<
402 <GIC_SPI <<
403 interrupt-names = "tun <<
404 clocks = <&cpg CPG_MOD <<
405 clock-names = "fck"; <<
406 power-domains = <&sysc <<
407 resets = <&cpg 715>; <<
408 status = "disabled"; <<
409 }; <<
410 <<
411 tmu3: timer@e6fe0000 { <<
412 compatible = "renesas, <<
413 reg = <0 0xe6fe0000 0 <<
414 interrupts = <GIC_SPI <<
415 <GIC_SPI <<
416 <GIC_SPI <<
417 <GIC_SPI <<
418 interrupt-names = "tun <<
419 clocks = <&cpg CPG_MOD <<
420 clock-names = "fck"; <<
421 power-domains = <&sysc <<
422 resets = <&cpg 716>; <<
423 status = "disabled"; <<
424 }; <<
425 <<
426 tmu4: timer@ffc00000 { <<
427 compatible = "renesas, <<
428 reg = <0 0xffc00000 0 <<
429 interrupts = <GIC_SPI <<
430 <GIC_SPI <<
431 <GIC_SPI <<
432 <GIC_SPI <<
433 interrupt-names = "tun <<
434 clocks = <&cpg CPG_MOD <<
435 clock-names = "fck"; <<
436 power-domains = <&sysc <<
437 resets = <&cpg 717>; <<
438 status = "disabled"; <<
439 }; <<
440 <<
441 i2c0: i2c@e6500000 { 260 i2c0: i2c@e6500000 {
442 compatible = "renesas, 261 compatible = "renesas,i2c-r8a779a0",
443 "renesas, !! 262 "renesas,rcar-gen3-i2c";
444 reg = <0 0xe6500000 0 263 reg = <0 0xe6500000 0 0x40>;
445 interrupts = <GIC_SPI 264 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
446 clocks = <&cpg CPG_MOD 265 clocks = <&cpg CPG_MOD 518>;
447 power-domains = <&sysc 266 power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
448 resets = <&cpg 518>; 267 resets = <&cpg 518>;
449 dmas = <&dmac1 0x91>, 268 dmas = <&dmac1 0x91>, <&dmac1 0x90>;
450 dma-names = "tx", "rx" 269 dma-names = "tx", "rx";
451 i2c-scl-internal-delay 270 i2c-scl-internal-delay-ns = <110>;
452 #address-cells = <1>; 271 #address-cells = <1>;
453 #size-cells = <0>; 272 #size-cells = <0>;
454 status = "disabled"; 273 status = "disabled";
455 }; 274 };
456 275
457 i2c1: i2c@e6508000 { 276 i2c1: i2c@e6508000 {
458 compatible = "renesas, 277 compatible = "renesas,i2c-r8a779a0",
459 "renesas, !! 278 "renesas,rcar-gen3-i2c";
460 reg = <0 0xe6508000 0 279 reg = <0 0xe6508000 0 0x40>;
461 interrupts = <GIC_SPI 280 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
462 clocks = <&cpg CPG_MOD 281 clocks = <&cpg CPG_MOD 519>;
463 power-domains = <&sysc 282 power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
464 resets = <&cpg 519>; 283 resets = <&cpg 519>;
465 dmas = <&dmac1 0x93>, 284 dmas = <&dmac1 0x93>, <&dmac1 0x92>;
466 dma-names = "tx", "rx" 285 dma-names = "tx", "rx";
467 i2c-scl-internal-delay 286 i2c-scl-internal-delay-ns = <110>;
468 #address-cells = <1>; 287 #address-cells = <1>;
469 #size-cells = <0>; 288 #size-cells = <0>;
470 status = "disabled"; 289 status = "disabled";
471 }; 290 };
472 291
473 i2c2: i2c@e6510000 { 292 i2c2: i2c@e6510000 {
474 compatible = "renesas, 293 compatible = "renesas,i2c-r8a779a0",
475 "renesas, !! 294 "renesas,rcar-gen3-i2c";
476 reg = <0 0xe6510000 0 295 reg = <0 0xe6510000 0 0x40>;
477 interrupts = <GIC_SPI 296 interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
478 clocks = <&cpg CPG_MOD 297 clocks = <&cpg CPG_MOD 520>;
479 power-domains = <&sysc 298 power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
480 resets = <&cpg 520>; 299 resets = <&cpg 520>;
481 dmas = <&dmac1 0x95>, 300 dmas = <&dmac1 0x95>, <&dmac1 0x94>;
482 dma-names = "tx", "rx" 301 dma-names = "tx", "rx";
483 i2c-scl-internal-delay 302 i2c-scl-internal-delay-ns = <110>;
484 #address-cells = <1>; 303 #address-cells = <1>;
485 #size-cells = <0>; 304 #size-cells = <0>;
486 status = "disabled"; 305 status = "disabled";
487 }; 306 };
488 307
489 i2c3: i2c@e66d0000 { 308 i2c3: i2c@e66d0000 {
490 compatible = "renesas, 309 compatible = "renesas,i2c-r8a779a0",
491 "renesas, !! 310 "renesas,rcar-gen3-i2c";
492 reg = <0 0xe66d0000 0 311 reg = <0 0xe66d0000 0 0x40>;
493 interrupts = <GIC_SPI 312 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>;
494 clocks = <&cpg CPG_MOD 313 clocks = <&cpg CPG_MOD 521>;
495 power-domains = <&sysc 314 power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
496 resets = <&cpg 521>; 315 resets = <&cpg 521>;
497 dmas = <&dmac1 0x97>, 316 dmas = <&dmac1 0x97>, <&dmac1 0x96>;
498 dma-names = "tx", "rx" 317 dma-names = "tx", "rx";
499 i2c-scl-internal-delay 318 i2c-scl-internal-delay-ns = <110>;
500 #address-cells = <1>; 319 #address-cells = <1>;
501 #size-cells = <0>; 320 #size-cells = <0>;
502 status = "disabled"; 321 status = "disabled";
503 }; 322 };
504 323
505 i2c4: i2c@e66d8000 { 324 i2c4: i2c@e66d8000 {
506 compatible = "renesas, 325 compatible = "renesas,i2c-r8a779a0",
507 "renesas, !! 326 "renesas,rcar-gen3-i2c";
508 reg = <0 0xe66d8000 0 327 reg = <0 0xe66d8000 0 0x40>;
509 interrupts = <GIC_SPI 328 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>;
510 clocks = <&cpg CPG_MOD 329 clocks = <&cpg CPG_MOD 522>;
511 power-domains = <&sysc 330 power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
512 resets = <&cpg 522>; 331 resets = <&cpg 522>;
513 dmas = <&dmac1 0x99>, 332 dmas = <&dmac1 0x99>, <&dmac1 0x98>;
514 dma-names = "tx", "rx" 333 dma-names = "tx", "rx";
515 i2c-scl-internal-delay 334 i2c-scl-internal-delay-ns = <110>;
516 #address-cells = <1>; 335 #address-cells = <1>;
517 #size-cells = <0>; 336 #size-cells = <0>;
518 status = "disabled"; 337 status = "disabled";
519 }; 338 };
520 339
521 i2c5: i2c@e66e0000 { 340 i2c5: i2c@e66e0000 {
522 compatible = "renesas, 341 compatible = "renesas,i2c-r8a779a0",
523 "renesas, !! 342 "renesas,rcar-gen3-i2c";
524 reg = <0 0xe66e0000 0 343 reg = <0 0xe66e0000 0 0x40>;
525 interrupts = <GIC_SPI 344 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
526 clocks = <&cpg CPG_MOD 345 clocks = <&cpg CPG_MOD 523>;
527 power-domains = <&sysc 346 power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
528 resets = <&cpg 523>; 347 resets = <&cpg 523>;
529 dmas = <&dmac1 0x9b>, 348 dmas = <&dmac1 0x9b>, <&dmac1 0x9a>;
530 dma-names = "tx", "rx" 349 dma-names = "tx", "rx";
531 i2c-scl-internal-delay 350 i2c-scl-internal-delay-ns = <110>;
532 #address-cells = <1>; 351 #address-cells = <1>;
533 #size-cells = <0>; 352 #size-cells = <0>;
534 status = "disabled"; 353 status = "disabled";
535 }; 354 };
536 355
537 i2c6: i2c@e66e8000 { 356 i2c6: i2c@e66e8000 {
538 compatible = "renesas, 357 compatible = "renesas,i2c-r8a779a0",
539 "renesas, !! 358 "renesas,rcar-gen3-i2c";
540 reg = <0 0xe66e8000 0 359 reg = <0 0xe66e8000 0 0x40>;
541 interrupts = <GIC_SPI 360 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>;
542 clocks = <&cpg CPG_MOD 361 clocks = <&cpg CPG_MOD 524>;
543 power-domains = <&sysc 362 power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
544 resets = <&cpg 524>; 363 resets = <&cpg 524>;
545 dmas = <&dmac1 0x9d>, 364 dmas = <&dmac1 0x9d>, <&dmac1 0x9c>;
546 dma-names = "tx", "rx" 365 dma-names = "tx", "rx";
547 i2c-scl-internal-delay 366 i2c-scl-internal-delay-ns = <110>;
548 #address-cells = <1>; 367 #address-cells = <1>;
549 #size-cells = <0>; 368 #size-cells = <0>;
550 status = "disabled"; 369 status = "disabled";
551 }; 370 };
552 371
553 hscif0: serial@e6540000 { 372 hscif0: serial@e6540000 {
554 compatible = "renesas, 373 compatible = "renesas,hscif-r8a779a0",
555 "renesas, !! 374 "renesas,rcar-gen3-hscif", "renesas,hscif";
556 reg = <0 0xe6540000 0 375 reg = <0 0xe6540000 0 0x60>;
557 interrupts = <GIC_SPI 376 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
558 clocks = <&cpg CPG_MOD 377 clocks = <&cpg CPG_MOD 514>,
559 <&cpg CPG_COR 378 <&cpg CPG_CORE R8A779A0_CLK_S1D2>,
560 <&scif_clk>; 379 <&scif_clk>;
561 clock-names = "fck", " 380 clock-names = "fck", "brg_int", "scif_clk";
562 dmas = <&dmac1 0x31>, 381 dmas = <&dmac1 0x31>, <&dmac1 0x30>;
563 dma-names = "tx", "rx" 382 dma-names = "tx", "rx";
564 power-domains = <&sysc 383 power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
565 resets = <&cpg 514>; 384 resets = <&cpg 514>;
566 status = "disabled"; 385 status = "disabled";
567 }; 386 };
568 387
569 hscif1: serial@e6550000 { 388 hscif1: serial@e6550000 {
570 compatible = "renesas, 389 compatible = "renesas,hscif-r8a779a0",
571 "renesas, !! 390 "renesas,rcar-gen3-hscif", "renesas,hscif";
572 reg = <0 0xe6550000 0 391 reg = <0 0xe6550000 0 0x60>;
573 interrupts = <GIC_SPI 392 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
574 clocks = <&cpg CPG_MOD 393 clocks = <&cpg CPG_MOD 515>,
575 <&cpg CPG_COR 394 <&cpg CPG_CORE R8A779A0_CLK_S1D2>,
576 <&scif_clk>; 395 <&scif_clk>;
577 clock-names = "fck", " 396 clock-names = "fck", "brg_int", "scif_clk";
578 dmas = <&dmac1 0x33>, 397 dmas = <&dmac1 0x33>, <&dmac1 0x32>;
579 dma-names = "tx", "rx" 398 dma-names = "tx", "rx";
580 power-domains = <&sysc 399 power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
581 resets = <&cpg 515>; 400 resets = <&cpg 515>;
582 status = "disabled"; 401 status = "disabled";
583 }; 402 };
584 403
585 hscif2: serial@e6560000 { 404 hscif2: serial@e6560000 {
586 compatible = "renesas, 405 compatible = "renesas,hscif-r8a779a0",
587 "renesas, !! 406 "renesas,rcar-gen3-hscif", "renesas,hscif";
588 reg = <0 0xe6560000 0 407 reg = <0 0xe6560000 0 0x60>;
589 interrupts = <GIC_SPI 408 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
590 clocks = <&cpg CPG_MOD 409 clocks = <&cpg CPG_MOD 516>,
591 <&cpg CPG_COR 410 <&cpg CPG_CORE R8A779A0_CLK_S1D2>,
592 <&scif_clk>; 411 <&scif_clk>;
593 clock-names = "fck", " 412 clock-names = "fck", "brg_int", "scif_clk";
594 dmas = <&dmac1 0x35>, 413 dmas = <&dmac1 0x35>, <&dmac1 0x34>;
595 dma-names = "tx", "rx" 414 dma-names = "tx", "rx";
596 power-domains = <&sysc 415 power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
597 resets = <&cpg 516>; 416 resets = <&cpg 516>;
598 status = "disabled"; 417 status = "disabled";
599 }; 418 };
600 419
601 hscif3: serial@e66a0000 { 420 hscif3: serial@e66a0000 {
602 compatible = "renesas, 421 compatible = "renesas,hscif-r8a779a0",
603 "renesas, !! 422 "renesas,rcar-gen3-hscif", "renesas,hscif";
604 reg = <0 0xe66a0000 0 423 reg = <0 0xe66a0000 0 0x60>;
605 interrupts = <GIC_SPI 424 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
606 clocks = <&cpg CPG_MOD 425 clocks = <&cpg CPG_MOD 517>,
607 <&cpg CPG_COR 426 <&cpg CPG_CORE R8A779A0_CLK_S1D2>,
608 <&scif_clk>; 427 <&scif_clk>;
609 clock-names = "fck", " 428 clock-names = "fck", "brg_int", "scif_clk";
610 dmas = <&dmac1 0x37>, 429 dmas = <&dmac1 0x37>, <&dmac1 0x36>;
611 dma-names = "tx", "rx" 430 dma-names = "tx", "rx";
612 power-domains = <&sysc 431 power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
613 resets = <&cpg 517>; 432 resets = <&cpg 517>;
614 status = "disabled"; 433 status = "disabled";
615 }; 434 };
616 435
617 canfd: can@e6660000 { <<
618 compatible = "renesas, <<
619 "renesas, <<
620 reg = <0 0xe6660000 0 <<
621 interrupts = <GIC_SPI <<
622 <GIC_S <<
623 interrupt-names = "ch_ <<
624 clocks = <&cpg CPG_MOD <<
625 <&cpg CPG_COR <<
626 <&can_clk>; <<
627 clock-names = "fck", " <<
628 assigned-clocks = <&cp <<
629 assigned-clock-rates = <<
630 power-domains = <&sysc <<
631 resets = <&cpg 328>; <<
632 status = "disabled"; <<
633 <<
634 channel0 { <<
635 status = "disa <<
636 }; <<
637 <<
638 channel1 { <<
639 status = "disa <<
640 }; <<
641 <<
642 channel2 { <<
643 status = "disa <<
644 }; <<
645 <<
646 channel3 { <<
647 status = "disa <<
648 }; <<
649 <<
650 channel4 { <<
651 status = "disa <<
652 }; <<
653 <<
654 channel5 { <<
655 status = "disa <<
656 }; <<
657 <<
658 channel6 { <<
659 status = "disa <<
660 }; <<
661 <<
662 channel7 { <<
663 status = "disa <<
664 }; <<
665 }; <<
666 <<
667 avb0: ethernet@e6800000 { 436 avb0: ethernet@e6800000 {
668 compatible = "renesas, 437 compatible = "renesas,etheravb-r8a779a0",
669 "renesas, !! 438 "renesas,etheravb-rcar-gen3";
670 reg = <0 0xe6800000 0 !! 439 reg = <0 0xe6800000 0 0x800>;
671 interrupts = <GIC_SPI 440 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
672 <GIC_SPI 441 <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
673 <GIC_SPI 442 <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
674 <GIC_SPI 443 <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>,
675 <GIC_SPI 444 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
676 <GIC_SPI 445 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
677 <GIC_SPI 446 <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
678 <GIC_SPI 447 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>,
679 <GIC_SPI 448 <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>,
680 <GIC_SPI 449 <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
681 <GIC_SPI 450 <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>,
682 <GIC_SPI 451 <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>,
683 <GIC_SPI 452 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
684 <GIC_SPI 453 <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>,
685 <GIC_SPI 454 <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>,
686 <GIC_SPI 455 <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>,
687 <GIC_SPI 456 <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>,
688 <GIC_SPI 457 <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>,
689 <GIC_SPI 458 <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>,
690 <GIC_SPI 459 <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>,
691 <GIC_SPI 460 <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>,
692 <GIC_SPI 461 <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>,
693 <GIC_SPI 462 <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>,
694 <GIC_SPI 463 <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
695 <GIC_SPI 464 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>;
696 interrupt-names = "ch0 465 interrupt-names = "ch0", "ch1", "ch2", "ch3",
697 "ch4 466 "ch4", "ch5", "ch6", "ch7",
698 "ch8 467 "ch8", "ch9", "ch10", "ch11",
699 "ch1 468 "ch12", "ch13", "ch14", "ch15",
700 "ch1 469 "ch16", "ch17", "ch18", "ch19",
701 "ch2 470 "ch20", "ch21", "ch22", "ch23",
702 "ch2 471 "ch24";
703 clocks = <&cpg CPG_MOD 472 clocks = <&cpg CPG_MOD 211>;
704 clock-names = "fck"; <<
705 power-domains = <&sysc 473 power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
706 resets = <&cpg 211>; 474 resets = <&cpg 211>;
707 phy-mode = "rgmii"; 475 phy-mode = "rgmii";
708 rx-internal-delay-ps = 476 rx-internal-delay-ps = <0>;
709 tx-internal-delay-ps = 477 tx-internal-delay-ps = <0>;
710 iommus = <&ipmmu_ds1 0 <<
711 #address-cells = <1>; 478 #address-cells = <1>;
712 #size-cells = <0>; 479 #size-cells = <0>;
713 status = "disabled"; 480 status = "disabled";
714 }; 481 };
715 482
716 avb1: ethernet@e6810000 { 483 avb1: ethernet@e6810000 {
717 compatible = "renesas, 484 compatible = "renesas,etheravb-r8a779a0",
718 "renesas, !! 485 "renesas,etheravb-rcar-gen3";
719 reg = <0 0xe6810000 0 !! 486 reg = <0 0xe6810000 0 0x800>;
720 interrupts = <GIC_SPI 487 interrupts = <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
721 <GIC_SPI 488 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
722 <GIC_SPI 489 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
723 <GIC_SPI 490 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
724 <GIC_SPI 491 <GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>,
725 <GIC_SPI 492 <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>,
726 <GIC_SPI 493 <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>,
727 <GIC_SPI 494 <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>,
728 <GIC_SPI 495 <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>,
729 <GIC_SPI 496 <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>,
730 <GIC_SPI 497 <GIC_SPI 291 IRQ_TYPE_LEVEL_HIGH>,
731 <GIC_SPI 498 <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>,
732 <GIC_SPI 499 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
733 <GIC_SPI 500 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
734 <GIC_SPI 501 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
735 <GIC_SPI 502 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
736 <GIC_SPI 503 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
737 <GIC_SPI 504 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>,
738 <GIC_SPI 505 <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>,
739 <GIC_SPI 506 <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>,
740 <GIC_SPI 507 <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>,
741 <GIC_SPI 508 <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>,
742 <GIC_SPI 509 <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>,
743 <GIC_SPI 510 <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
744 <GIC_SPI 511 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
745 interrupt-names = "ch0 512 interrupt-names = "ch0", "ch1", "ch2", "ch3",
746 "ch4 513 "ch4", "ch5", "ch6", "ch7",
747 "ch8 514 "ch8", "ch9", "ch10", "ch11",
748 "ch1 515 "ch12", "ch13", "ch14", "ch15",
749 "ch1 516 "ch16", "ch17", "ch18", "ch19",
750 "ch2 517 "ch20", "ch21", "ch22", "ch23",
751 "ch2 518 "ch24";
752 clocks = <&cpg CPG_MOD 519 clocks = <&cpg CPG_MOD 212>;
753 clock-names = "fck"; <<
754 power-domains = <&sysc 520 power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
755 resets = <&cpg 212>; 521 resets = <&cpg 212>;
756 phy-mode = "rgmii"; 522 phy-mode = "rgmii";
757 rx-internal-delay-ps = 523 rx-internal-delay-ps = <0>;
758 tx-internal-delay-ps = 524 tx-internal-delay-ps = <0>;
759 iommus = <&ipmmu_ds1 1 <<
760 #address-cells = <1>; 525 #address-cells = <1>;
761 #size-cells = <0>; 526 #size-cells = <0>;
762 status = "disabled"; 527 status = "disabled";
763 }; 528 };
764 529
765 avb2: ethernet@e6820000 { 530 avb2: ethernet@e6820000 {
766 compatible = "renesas, 531 compatible = "renesas,etheravb-r8a779a0",
767 "renesas, !! 532 "renesas,etheravb-rcar-gen3";
768 reg = <0 0xe6820000 0 533 reg = <0 0xe6820000 0 0x1000>;
769 interrupts = <GIC_SPI 534 interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>,
770 <GIC_S 535 <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,
771 <GIC_S 536 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
772 <GIC_S 537 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
773 <GIC_S 538 <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
774 <GIC_S 539 <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>,
775 <GIC_S 540 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
776 <GIC_S 541 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
777 <GIC_S 542 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
778 <GIC_S 543 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
779 <GIC_S 544 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
780 <GIC_S 545 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
781 <GIC_S 546 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
782 <GIC_S 547 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
783 <GIC_S 548 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
784 <GIC_S 549 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
785 <GIC_S 550 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
786 <GIC_S 551 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
787 <GIC_S 552 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
788 <GIC_S 553 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
789 <GIC_S 554 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
790 <GIC_S 555 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
791 <GIC_S 556 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
792 <GIC_S 557 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
793 <GIC_S 558 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>;
794 interrupt-names = "ch0 559 interrupt-names = "ch0", "ch1", "ch2", "ch3",
795 "ch4", 560 "ch4", "ch5", "ch6", "ch7",
796 "ch8", 561 "ch8", "ch9", "ch10", "ch11",
797 "ch12" 562 "ch12", "ch13", "ch14", "ch15",
798 "ch16" 563 "ch16", "ch17", "ch18", "ch19",
799 "ch20" 564 "ch20", "ch21", "ch22", "ch23",
800 "ch24" 565 "ch24";
801 clocks = <&cpg CPG_MOD 566 clocks = <&cpg CPG_MOD 213>;
802 clock-names = "fck"; <<
803 power-domains = <&sysc 567 power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
804 resets = <&cpg 213>; 568 resets = <&cpg 213>;
805 phy-mode = "rgmii"; 569 phy-mode = "rgmii";
806 rx-internal-delay-ps = 570 rx-internal-delay-ps = <0>;
807 tx-internal-delay-ps = 571 tx-internal-delay-ps = <0>;
808 iommus = <&ipmmu_ds1 2 <<
809 #address-cells = <1>; 572 #address-cells = <1>;
810 #size-cells = <0>; 573 #size-cells = <0>;
811 status = "disabled"; 574 status = "disabled";
812 }; 575 };
813 576
814 avb3: ethernet@e6830000 { 577 avb3: ethernet@e6830000 {
815 compatible = "renesas, 578 compatible = "renesas,etheravb-r8a779a0",
816 "renesas, !! 579 "renesas,etheravb-rcar-gen3";
817 reg = <0 0xe6830000 0 580 reg = <0 0xe6830000 0 0x1000>;
818 interrupts = <GIC_SPI 581 interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
819 <GIC_S 582 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
820 <GIC_S 583 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
821 <GIC_S 584 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
822 <GIC_S 585 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
823 <GIC_S 586 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
824 <GIC_S 587 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
825 <GIC_S 588 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
826 <GIC_S 589 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
827 <GIC_S 590 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
828 <GIC_S 591 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
829 <GIC_S 592 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
830 <GIC_S 593 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
831 <GIC_S 594 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
832 <GIC_S 595 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
833 <GIC_S 596 <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>,
834 <GIC_S 597 <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
835 <GIC_S 598 <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>,
836 <GIC_S 599 <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>,
837 <GIC_S 600 <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>,
838 <GIC_S 601 <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>,
839 <GIC_S 602 <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>,
840 <GIC_S 603 <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>,
841 <GIC_S 604 <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>,
842 <GIC_S 605 <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
843 interrupt-names = "ch0 606 interrupt-names = "ch0", "ch1", "ch2", "ch3",
844 "ch4", 607 "ch4", "ch5", "ch6", "ch7",
845 "ch8", 608 "ch8", "ch9", "ch10", "ch11",
846 "ch12" 609 "ch12", "ch13", "ch14", "ch15",
847 "ch16" 610 "ch16", "ch17", "ch18", "ch19",
848 "ch20" 611 "ch20", "ch21", "ch22", "ch23",
849 "ch24" 612 "ch24";
850 clocks = <&cpg CPG_MOD 613 clocks = <&cpg CPG_MOD 214>;
851 clock-names = "fck"; <<
852 power-domains = <&sysc 614 power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
853 resets = <&cpg 214>; 615 resets = <&cpg 214>;
854 phy-mode = "rgmii"; 616 phy-mode = "rgmii";
855 rx-internal-delay-ps = 617 rx-internal-delay-ps = <0>;
856 tx-internal-delay-ps = 618 tx-internal-delay-ps = <0>;
857 iommus = <&ipmmu_ds1 3 <<
858 #address-cells = <1>; 619 #address-cells = <1>;
859 #size-cells = <0>; 620 #size-cells = <0>;
860 status = "disabled"; 621 status = "disabled";
861 }; 622 };
862 623
863 avb4: ethernet@e6840000 { 624 avb4: ethernet@e6840000 {
864 compatible = "renesas, 625 compatible = "renesas,etheravb-r8a779a0",
865 "renesas, !! 626 "renesas,etheravb-rcar-gen3";
866 reg = <0 0xe6840000 0 627 reg = <0 0xe6840000 0 0x1000>;
867 interrupts = <GIC_SPI 628 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>,
868 <GIC_S 629 <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>,
869 <GIC_S 630 <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>,
870 <GIC_S 631 <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>,
871 <GIC_S 632 <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>,
872 <GIC_S 633 <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>,
873 <GIC_S 634 <GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH>,
874 <GIC_S 635 <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>,
875 <GIC_S 636 <GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH>,
876 <GIC_S 637 <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH>,
877 <GIC_S 638 <GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>,
878 <GIC_S 639 <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>,
879 <GIC_S 640 <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>,
880 <GIC_S 641 <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>,
881 <GIC_S 642 <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>,
882 <GIC_S 643 <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>,
883 <GIC_S 644 <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>,
884 <GIC_S 645 <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>,
885 <GIC_S 646 <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>,
886 <GIC_S 647 <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>,
887 <GIC_S 648 <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>,
888 <GIC_S 649 <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>,
889 <GIC_S 650 <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>,
890 <GIC_S 651 <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>,
891 <GIC_S 652 <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>;
892 interrupt-names = "ch0 653 interrupt-names = "ch0", "ch1", "ch2", "ch3",
893 "ch4", 654 "ch4", "ch5", "ch6", "ch7",
894 "ch8", 655 "ch8", "ch9", "ch10", "ch11",
895 "ch12" 656 "ch12", "ch13", "ch14", "ch15",
896 "ch16" 657 "ch16", "ch17", "ch18", "ch19",
897 "ch20" 658 "ch20", "ch21", "ch22", "ch23",
898 "ch24" 659 "ch24";
899 clocks = <&cpg CPG_MOD 660 clocks = <&cpg CPG_MOD 215>;
900 clock-names = "fck"; <<
901 power-domains = <&sysc 661 power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
902 resets = <&cpg 215>; 662 resets = <&cpg 215>;
903 phy-mode = "rgmii"; 663 phy-mode = "rgmii";
904 rx-internal-delay-ps = 664 rx-internal-delay-ps = <0>;
905 tx-internal-delay-ps = 665 tx-internal-delay-ps = <0>;
906 iommus = <&ipmmu_ds1 4 <<
907 #address-cells = <1>; 666 #address-cells = <1>;
908 #size-cells = <0>; 667 #size-cells = <0>;
909 status = "disabled"; 668 status = "disabled";
910 }; 669 };
911 670
912 avb5: ethernet@e6850000 { 671 avb5: ethernet@e6850000 {
913 compatible = "renesas, 672 compatible = "renesas,etheravb-r8a779a0",
914 "renesas, !! 673 "renesas,etheravb-rcar-gen3";
915 reg = <0 0xe6850000 0 674 reg = <0 0xe6850000 0 0x1000>;
916 interrupts = <GIC_SPI 675 interrupts = <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>,
917 <GIC_S 676 <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>,
918 <GIC_S 677 <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>,
919 <GIC_S 678 <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>,
920 <GIC_S 679 <GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>,
921 <GIC_S 680 <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>,
922 <GIC_S 681 <GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>,
923 <GIC_S 682 <GIC_SPI 388 IRQ_TYPE_LEVEL_HIGH>,
924 <GIC_S 683 <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>,
925 <GIC_S 684 <GIC_SPI 390 IRQ_TYPE_LEVEL_HIGH>,
926 <GIC_S 685 <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH>,
927 <GIC_S 686 <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH>,
928 <GIC_S 687 <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>,
929 <GIC_S 688 <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>,
930 <GIC_S 689 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
931 <GIC_S 690 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
932 <GIC_S 691 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
933 <GIC_S 692 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
934 <GIC_S 693 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
935 <GIC_S 694 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
936 <GIC_S 695 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
937 <GIC_S 696 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
938 <GIC_S 697 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
939 <GIC_S 698 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
940 <GIC_S 699 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>;
941 interrupt-names = "ch0 700 interrupt-names = "ch0", "ch1", "ch2", "ch3",
942 "ch4", 701 "ch4", "ch5", "ch6", "ch7",
943 "ch8", 702 "ch8", "ch9", "ch10", "ch11",
944 "ch12" 703 "ch12", "ch13", "ch14", "ch15",
945 "ch16" 704 "ch16", "ch17", "ch18", "ch19",
946 "ch20" 705 "ch20", "ch21", "ch22", "ch23",
947 "ch24" 706 "ch24";
948 clocks = <&cpg CPG_MOD 707 clocks = <&cpg CPG_MOD 216>;
949 clock-names = "fck"; <<
950 power-domains = <&sysc 708 power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
951 resets = <&cpg 216>; 709 resets = <&cpg 216>;
952 phy-mode = "rgmii"; 710 phy-mode = "rgmii";
953 rx-internal-delay-ps = 711 rx-internal-delay-ps = <0>;
954 tx-internal-delay-ps = 712 tx-internal-delay-ps = <0>;
955 iommus = <&ipmmu_ds1 1 <<
956 #address-cells = <1>; 713 #address-cells = <1>;
957 #size-cells = <0>; 714 #size-cells = <0>;
958 status = "disabled"; 715 status = "disabled";
959 }; 716 };
960 717
961 pwm0: pwm@e6e30000 { <<
962 compatible = "renesas, <<
963 reg = <0 0xe6e30000 0 <<
964 #pwm-cells = <2>; <<
965 clocks = <&cpg CPG_MOD <<
966 power-domains = <&sysc <<
967 resets = <&cpg 628>; <<
968 status = "disabled"; <<
969 }; <<
970 <<
971 pwm1: pwm@e6e31000 { <<
972 compatible = "renesas, <<
973 reg = <0 0xe6e31000 0 <<
974 #pwm-cells = <2>; <<
975 clocks = <&cpg CPG_MOD <<
976 power-domains = <&sysc <<
977 resets = <&cpg 628>; <<
978 status = "disabled"; <<
979 }; <<
980 <<
981 pwm2: pwm@e6e32000 { <<
982 compatible = "renesas, <<
983 reg = <0 0xe6e32000 0 <<
984 #pwm-cells = <2>; <<
985 clocks = <&cpg CPG_MOD <<
986 power-domains = <&sysc <<
987 resets = <&cpg 628>; <<
988 status = "disabled"; <<
989 }; <<
990 <<
991 pwm3: pwm@e6e33000 { <<
992 compatible = "renesas, <<
993 reg = <0 0xe6e33000 0 <<
994 #pwm-cells = <2>; <<
995 clocks = <&cpg CPG_MOD <<
996 power-domains = <&sysc <<
997 resets = <&cpg 628>; <<
998 status = "disabled"; <<
999 }; <<
1000 <<
1001 pwm4: pwm@e6e34000 { <<
1002 compatible = "renesas <<
1003 reg = <0 0xe6e34000 0 <<
1004 #pwm-cells = <2>; <<
1005 clocks = <&cpg CPG_MO <<
1006 power-domains = <&sys <<
1007 resets = <&cpg 628>; <<
1008 status = "disabled"; <<
1009 }; <<
1010 <<
1011 scif0: serial@e6e60000 { 718 scif0: serial@e6e60000 {
1012 compatible = "renesas 719 compatible = "renesas,scif-r8a779a0",
1013 "renesas !! 720 "renesas,rcar-gen3-scif", "renesas,scif";
1014 reg = <0 0xe6e60000 0 721 reg = <0 0xe6e60000 0 64>;
1015 interrupts = <GIC_SPI 722 interrupts = <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>;
1016 clocks = <&cpg CPG_MO 723 clocks = <&cpg CPG_MOD 702>,
1017 <&cpg CPG_CO 724 <&cpg CPG_CORE R8A779A0_CLK_S1D2>,
1018 <&scif_clk>; 725 <&scif_clk>;
1019 clock-names = "fck", 726 clock-names = "fck", "brg_int", "scif_clk";
1020 dmas = <&dmac1 0x51>, 727 dmas = <&dmac1 0x51>, <&dmac1 0x50>;
1021 dma-names = "tx", "rx 728 dma-names = "tx", "rx";
1022 power-domains = <&sys 729 power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
1023 resets = <&cpg 702>; 730 resets = <&cpg 702>;
1024 status = "disabled"; 731 status = "disabled";
1025 }; 732 };
1026 733
1027 scif1: serial@e6e68000 { 734 scif1: serial@e6e68000 {
1028 compatible = "renesas 735 compatible = "renesas,scif-r8a779a0",
1029 "renesas !! 736 "renesas,rcar-gen3-scif", "renesas,scif";
1030 reg = <0 0xe6e68000 0 737 reg = <0 0xe6e68000 0 64>;
1031 interrupts = <GIC_SPI 738 interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>;
1032 clocks = <&cpg CPG_MO 739 clocks = <&cpg CPG_MOD 703>,
1033 <&cpg CPG_CO 740 <&cpg CPG_CORE R8A779A0_CLK_S1D2>,
1034 <&scif_clk>; 741 <&scif_clk>;
1035 clock-names = "fck", 742 clock-names = "fck", "brg_int", "scif_clk";
1036 dmas = <&dmac1 0x53>, 743 dmas = <&dmac1 0x53>, <&dmac1 0x52>;
1037 dma-names = "tx", "rx 744 dma-names = "tx", "rx";
1038 power-domains = <&sys 745 power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
1039 resets = <&cpg 703>; 746 resets = <&cpg 703>;
1040 status = "disabled"; 747 status = "disabled";
1041 }; 748 };
1042 749
1043 scif3: serial@e6c50000 { 750 scif3: serial@e6c50000 {
1044 compatible = "renesas 751 compatible = "renesas,scif-r8a779a0",
1045 "renesas !! 752 "renesas,rcar-gen3-scif", "renesas,scif";
1046 reg = <0 0xe6c50000 0 753 reg = <0 0xe6c50000 0 64>;
1047 interrupts = <GIC_SPI 754 interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>;
1048 clocks = <&cpg CPG_MO 755 clocks = <&cpg CPG_MOD 704>,
1049 <&cpg CPG_CO 756 <&cpg CPG_CORE R8A779A0_CLK_S1D2>,
1050 <&scif_clk>; 757 <&scif_clk>;
1051 clock-names = "fck", 758 clock-names = "fck", "brg_int", "scif_clk";
1052 dmas = <&dmac1 0x57>, 759 dmas = <&dmac1 0x57>, <&dmac1 0x56>;
1053 dma-names = "tx", "rx 760 dma-names = "tx", "rx";
1054 power-domains = <&sys 761 power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
1055 resets = <&cpg 704>; 762 resets = <&cpg 704>;
1056 status = "disabled"; 763 status = "disabled";
1057 }; 764 };
1058 765
1059 scif4: serial@e6c40000 { 766 scif4: serial@e6c40000 {
1060 compatible = "renesas 767 compatible = "renesas,scif-r8a779a0",
1061 "renesas !! 768 "renesas,rcar-gen3-scif", "renesas,scif";
1062 reg = <0 0xe6c40000 0 769 reg = <0 0xe6c40000 0 64>;
1063 interrupts = <GIC_SPI 770 interrupts = <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>;
1064 clocks = <&cpg CPG_MO 771 clocks = <&cpg CPG_MOD 705>,
1065 <&cpg CPG_CO 772 <&cpg CPG_CORE R8A779A0_CLK_S1D2>,
1066 <&scif_clk>; 773 <&scif_clk>;
1067 clock-names = "fck", 774 clock-names = "fck", "brg_int", "scif_clk";
1068 dmas = <&dmac1 0x59>, 775 dmas = <&dmac1 0x59>, <&dmac1 0x58>;
1069 dma-names = "tx", "rx 776 dma-names = "tx", "rx";
1070 power-domains = <&sys 777 power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
1071 resets = <&cpg 705>; 778 resets = <&cpg 705>;
1072 status = "disabled"; 779 status = "disabled";
1073 }; 780 };
1074 781
1075 tpu: pwm@e6e80000 { <<
1076 compatible = "renesas <<
1077 reg = <0 0xe6e80000 0 <<
1078 interrupts = <GIC_SPI <<
1079 clocks = <&cpg CPG_MO <<
1080 power-domains = <&sys <<
1081 resets = <&cpg 718>; <<
1082 #pwm-cells = <3>; <<
1083 status = "disabled"; <<
1084 }; <<
1085 <<
1086 msiof0: spi@e6e90000 { 782 msiof0: spi@e6e90000 {
1087 compatible = "renesas 783 compatible = "renesas,msiof-r8a779a0",
1088 "renesas !! 784 "renesas,rcar-gen3-msiof";
1089 reg = <0 0xe6e90000 0 785 reg = <0 0xe6e90000 0 0x0064>;
1090 interrupts = <GIC_SPI 786 interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>;
1091 clocks = <&cpg CPG_MO 787 clocks = <&cpg CPG_MOD 618>;
1092 power-domains = <&sys 788 power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
1093 resets = <&cpg 618>; 789 resets = <&cpg 618>;
1094 dmas = <&dmac1 0x41>, 790 dmas = <&dmac1 0x41>, <&dmac1 0x40>;
1095 dma-names = "tx", "rx 791 dma-names = "tx", "rx";
1096 #address-cells = <1>; 792 #address-cells = <1>;
1097 #size-cells = <0>; 793 #size-cells = <0>;
1098 status = "disabled"; 794 status = "disabled";
1099 }; 795 };
1100 796
1101 msiof1: spi@e6ea0000 { 797 msiof1: spi@e6ea0000 {
1102 compatible = "renesas 798 compatible = "renesas,msiof-r8a779a0",
1103 "renesas !! 799 "renesas,rcar-gen3-msiof";
1104 reg = <0 0xe6ea0000 0 800 reg = <0 0xe6ea0000 0 0x0064>;
1105 interrupts = <GIC_SPI 801 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
1106 clocks = <&cpg CPG_MO 802 clocks = <&cpg CPG_MOD 619>;
1107 power-domains = <&sys 803 power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
1108 resets = <&cpg 619>; 804 resets = <&cpg 619>;
1109 dmas = <&dmac1 0x43>, 805 dmas = <&dmac1 0x43>, <&dmac1 0x42>;
1110 dma-names = "tx", "rx 806 dma-names = "tx", "rx";
1111 #address-cells = <1>; 807 #address-cells = <1>;
1112 #size-cells = <0>; 808 #size-cells = <0>;
1113 status = "disabled"; 809 status = "disabled";
1114 }; 810 };
1115 811
1116 msiof2: spi@e6c00000 { 812 msiof2: spi@e6c00000 {
1117 compatible = "renesas 813 compatible = "renesas,msiof-r8a779a0",
1118 "renesas !! 814 "renesas,rcar-gen3-msiof";
1119 reg = <0 0xe6c00000 0 815 reg = <0 0xe6c00000 0 0x0064>;
1120 interrupts = <GIC_SPI 816 interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
1121 clocks = <&cpg CPG_MO 817 clocks = <&cpg CPG_MOD 620>;
1122 power-domains = <&sys 818 power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
1123 resets = <&cpg 620>; 819 resets = <&cpg 620>;
1124 dmas = <&dmac1 0x45>, 820 dmas = <&dmac1 0x45>, <&dmac1 0x44>;
1125 dma-names = "tx", "rx 821 dma-names = "tx", "rx";
1126 #address-cells = <1>; 822 #address-cells = <1>;
1127 #size-cells = <0>; 823 #size-cells = <0>;
1128 status = "disabled"; 824 status = "disabled";
1129 }; 825 };
1130 826
1131 msiof3: spi@e6c10000 { 827 msiof3: spi@e6c10000 {
1132 compatible = "renesas 828 compatible = "renesas,msiof-r8a779a0",
1133 "renesas !! 829 "renesas,rcar-gen3-msiof";
1134 reg = <0 0xe6c10000 0 830 reg = <0 0xe6c10000 0 0x0064>;
1135 interrupts = <GIC_SPI 831 interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>;
1136 clocks = <&cpg CPG_MO 832 clocks = <&cpg CPG_MOD 621>;
1137 power-domains = <&sys 833 power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
1138 resets = <&cpg 621>; 834 resets = <&cpg 621>;
1139 dmas = <&dmac1 0x47>, 835 dmas = <&dmac1 0x47>, <&dmac1 0x46>;
1140 dma-names = "tx", "rx 836 dma-names = "tx", "rx";
1141 #address-cells = <1>; 837 #address-cells = <1>;
1142 #size-cells = <0>; 838 #size-cells = <0>;
1143 status = "disabled"; 839 status = "disabled";
1144 }; 840 };
1145 841
1146 msiof4: spi@e6c20000 { 842 msiof4: spi@e6c20000 {
1147 compatible = "renesas 843 compatible = "renesas,msiof-r8a779a0",
1148 "renesas !! 844 "renesas,rcar-gen3-msiof";
1149 reg = <0 0xe6c20000 0 845 reg = <0 0xe6c20000 0 0x0064>;
1150 interrupts = <GIC_SPI 846 interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>;
1151 clocks = <&cpg CPG_MO 847 clocks = <&cpg CPG_MOD 622>;
1152 power-domains = <&sys 848 power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
1153 resets = <&cpg 622>; 849 resets = <&cpg 622>;
1154 dmas = <&dmac1 0x49>, 850 dmas = <&dmac1 0x49>, <&dmac1 0x48>;
1155 dma-names = "tx", "rx 851 dma-names = "tx", "rx";
1156 #address-cells = <1>; 852 #address-cells = <1>;
1157 #size-cells = <0>; 853 #size-cells = <0>;
1158 status = "disabled"; 854 status = "disabled";
1159 }; 855 };
1160 856
1161 msiof5: spi@e6c28000 { 857 msiof5: spi@e6c28000 {
1162 compatible = "renesas 858 compatible = "renesas,msiof-r8a779a0",
1163 "renesas !! 859 "renesas,rcar-gen3-msiof";
1164 reg = <0 0xe6c28000 0 860 reg = <0 0xe6c28000 0 0x0064>;
1165 interrupts = <GIC_SPI 861 interrupts = <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>;
1166 clocks = <&cpg CPG_MO 862 clocks = <&cpg CPG_MOD 623>;
1167 power-domains = <&sys 863 power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
1168 resets = <&cpg 623>; 864 resets = <&cpg 623>;
1169 dmas = <&dmac1 0x4b>, 865 dmas = <&dmac1 0x4b>, <&dmac1 0x4a>;
1170 dma-names = "tx", "rx 866 dma-names = "tx", "rx";
1171 #address-cells = <1>; 867 #address-cells = <1>;
1172 #size-cells = <0>; 868 #size-cells = <0>;
1173 status = "disabled"; 869 status = "disabled";
1174 }; 870 };
1175 871
1176 vin00: video@e6ef0000 { <<
1177 compatible = "renesas <<
1178 "renesas <<
1179 reg = <0 0xe6ef0000 0 <<
1180 interrupts = <GIC_SPI <<
1181 clocks = <&cpg CPG_MO <<
1182 power-domains = <&sys <<
1183 resets = <&cpg 730>; <<
1184 renesas,id = <0>; <<
1185 status = "disabled"; <<
1186 <<
1187 ports { <<
1188 #address-cell <<
1189 #size-cells = <<
1190 <<
1191 port@2 { <<
1192 #addr <<
1193 #size <<
1194 <<
1195 reg = <<
1196 <<
1197 vin00 <<
1198 <<
1199 <<
1200 }; <<
1201 }; <<
1202 }; <<
1203 }; <<
1204 <<
1205 vin01: video@e6ef1000 { <<
1206 compatible = "renesas <<
1207 "renesas <<
1208 reg = <0 0xe6ef1000 0 <<
1209 interrupts = <GIC_SPI <<
1210 clocks = <&cpg CPG_MO <<
1211 power-domains = <&sys <<
1212 resets = <&cpg 731>; <<
1213 renesas,id = <1>; <<
1214 status = "disabled"; <<
1215 <<
1216 ports { <<
1217 #address-cell <<
1218 #size-cells = <<
1219 <<
1220 port@2 { <<
1221 #addr <<
1222 #size <<
1223 <<
1224 reg = <<
1225 <<
1226 vin01 <<
1227 <<
1228 <<
1229 }; <<
1230 }; <<
1231 }; <<
1232 }; <<
1233 <<
1234 vin02: video@e6ef2000 { <<
1235 compatible = "renesas <<
1236 "renesas <<
1237 reg = <0 0xe6ef2000 0 <<
1238 interrupts = <GIC_SPI <<
1239 clocks = <&cpg CPG_MO <<
1240 power-domains = <&sys <<
1241 resets = <&cpg 800>; <<
1242 renesas,id = <2>; <<
1243 status = "disabled"; <<
1244 <<
1245 ports { <<
1246 #address-cell <<
1247 #size-cells = <<
1248 <<
1249 port@2 { <<
1250 #addr <<
1251 #size <<
1252 <<
1253 reg = <<
1254 <<
1255 vin02 <<
1256 <<
1257 <<
1258 }; <<
1259 }; <<
1260 }; <<
1261 }; <<
1262 <<
1263 vin03: video@e6ef3000 { <<
1264 compatible = "renesas <<
1265 "renesas <<
1266 reg = <0 0xe6ef3000 0 <<
1267 interrupts = <GIC_SPI <<
1268 clocks = <&cpg CPG_MO <<
1269 power-domains = <&sys <<
1270 resets = <&cpg 801>; <<
1271 renesas,id = <3>; <<
1272 status = "disabled"; <<
1273 <<
1274 ports { <<
1275 #address-cell <<
1276 #size-cells = <<
1277 <<
1278 port@2 { <<
1279 #addr <<
1280 #size <<
1281 <<
1282 reg = <<
1283 <<
1284 vin03 <<
1285 <<
1286 <<
1287 }; <<
1288 }; <<
1289 }; <<
1290 }; <<
1291 <<
1292 vin04: video@e6ef4000 { <<
1293 compatible = "renesas <<
1294 "renesas <<
1295 reg = <0 0xe6ef4000 0 <<
1296 interrupts = <GIC_SPI <<
1297 clocks = <&cpg CPG_MO <<
1298 power-domains = <&sys <<
1299 resets = <&cpg 802>; <<
1300 renesas,id = <4>; <<
1301 status = "disabled"; <<
1302 <<
1303 ports { <<
1304 #address-cell <<
1305 #size-cells = <<
1306 <<
1307 port@2 { <<
1308 #addr <<
1309 #size <<
1310 <<
1311 reg = <<
1312 <<
1313 vin04 <<
1314 <<
1315 <<
1316 }; <<
1317 }; <<
1318 }; <<
1319 }; <<
1320 <<
1321 vin05: video@e6ef5000 { <<
1322 compatible = "renesas <<
1323 "renesas <<
1324 reg = <0 0xe6ef5000 0 <<
1325 interrupts = <GIC_SPI <<
1326 clocks = <&cpg CPG_MO <<
1327 power-domains = <&sys <<
1328 resets = <&cpg 803>; <<
1329 renesas,id = <5>; <<
1330 status = "disabled"; <<
1331 <<
1332 ports { <<
1333 #address-cell <<
1334 #size-cells = <<
1335 <<
1336 port@2 { <<
1337 #addr <<
1338 #size <<
1339 <<
1340 reg = <<
1341 <<
1342 vin05 <<
1343 <<
1344 <<
1345 }; <<
1346 }; <<
1347 }; <<
1348 }; <<
1349 <<
1350 vin06: video@e6ef6000 { <<
1351 compatible = "renesas <<
1352 "renesas <<
1353 reg = <0 0xe6ef6000 0 <<
1354 interrupts = <GIC_SPI <<
1355 clocks = <&cpg CPG_MO <<
1356 power-domains = <&sys <<
1357 resets = <&cpg 804>; <<
1358 renesas,id = <6>; <<
1359 status = "disabled"; <<
1360 <<
1361 ports { <<
1362 #address-cell <<
1363 #size-cells = <<
1364 <<
1365 port@2 { <<
1366 #addr <<
1367 #size <<
1368 <<
1369 reg = <<
1370 <<
1371 vin06 <<
1372 <<
1373 <<
1374 }; <<
1375 }; <<
1376 }; <<
1377 }; <<
1378 <<
1379 vin07: video@e6ef7000 { <<
1380 compatible = "renesas <<
1381 "renesas <<
1382 reg = <0 0xe6ef7000 0 <<
1383 interrupts = <GIC_SPI <<
1384 clocks = <&cpg CPG_MO <<
1385 power-domains = <&sys <<
1386 resets = <&cpg 805>; <<
1387 renesas,id = <7>; <<
1388 status = "disabled"; <<
1389 <<
1390 ports { <<
1391 #address-cell <<
1392 #size-cells = <<
1393 <<
1394 port@2 { <<
1395 #addr <<
1396 #size <<
1397 <<
1398 reg = <<
1399 <<
1400 vin07 <<
1401 <<
1402 <<
1403 }; <<
1404 }; <<
1405 }; <<
1406 }; <<
1407 <<
1408 vin08: video@e6ef8000 { <<
1409 compatible = "renesas <<
1410 "renesas <<
1411 reg = <0 0xe6ef8000 0 <<
1412 interrupts = <GIC_SPI <<
1413 clocks = <&cpg CPG_MO <<
1414 power-domains = <&sys <<
1415 resets = <&cpg 806>; <<
1416 renesas,id = <8>; <<
1417 status = "disabled"; <<
1418 <<
1419 ports { <<
1420 #address-cell <<
1421 #size-cells = <<
1422 <<
1423 port@2 { <<
1424 #addr <<
1425 #size <<
1426 <<
1427 reg = <<
1428 <<
1429 vin08 <<
1430 <<
1431 <<
1432 }; <<
1433 }; <<
1434 }; <<
1435 }; <<
1436 <<
1437 vin09: video@e6ef9000 { <<
1438 compatible = "renesas <<
1439 "renesas <<
1440 reg = <0 0xe6ef9000 0 <<
1441 interrupts = <GIC_SPI <<
1442 clocks = <&cpg CPG_MO <<
1443 power-domains = <&sys <<
1444 resets = <&cpg 807>; <<
1445 renesas,id = <9>; <<
1446 status = "disabled"; <<
1447 <<
1448 ports { <<
1449 #address-cell <<
1450 #size-cells = <<
1451 <<
1452 port@2 { <<
1453 #addr <<
1454 #size <<
1455 <<
1456 reg = <<
1457 <<
1458 vin09 <<
1459 <<
1460 <<
1461 }; <<
1462 }; <<
1463 }; <<
1464 }; <<
1465 <<
1466 vin10: video@e6efa000 { <<
1467 compatible = "renesas <<
1468 "renesas <<
1469 reg = <0 0xe6efa000 0 <<
1470 interrupts = <GIC_SPI <<
1471 clocks = <&cpg CPG_MO <<
1472 power-domains = <&sys <<
1473 resets = <&cpg 808>; <<
1474 renesas,id = <10>; <<
1475 status = "disabled"; <<
1476 <<
1477 ports { <<
1478 #address-cell <<
1479 #size-cells = <<
1480 <<
1481 port@2 { <<
1482 #addr <<
1483 #size <<
1484 <<
1485 reg = <<
1486 <<
1487 vin10 <<
1488 <<
1489 <<
1490 }; <<
1491 }; <<
1492 }; <<
1493 }; <<
1494 <<
1495 vin11: video@e6efb000 { <<
1496 compatible = "renesas <<
1497 "renesas <<
1498 reg = <0 0xe6efb000 0 <<
1499 interrupts = <GIC_SPI <<
1500 clocks = <&cpg CPG_MO <<
1501 power-domains = <&sys <<
1502 resets = <&cpg 809>; <<
1503 renesas,id = <11>; <<
1504 status = "disabled"; <<
1505 <<
1506 ports { <<
1507 #address-cell <<
1508 #size-cells = <<
1509 <<
1510 port@2 { <<
1511 #addr <<
1512 #size <<
1513 <<
1514 reg = <<
1515 <<
1516 vin11 <<
1517 <<
1518 <<
1519 }; <<
1520 }; <<
1521 }; <<
1522 }; <<
1523 <<
1524 vin12: video@e6efc000 { <<
1525 compatible = "renesas <<
1526 "renesas <<
1527 reg = <0 0xe6efc000 0 <<
1528 interrupts = <GIC_SPI <<
1529 clocks = <&cpg CPG_MO <<
1530 power-domains = <&sys <<
1531 resets = <&cpg 810>; <<
1532 renesas,id = <12>; <<
1533 status = "disabled"; <<
1534 <<
1535 ports { <<
1536 #address-cell <<
1537 #size-cells = <<
1538 <<
1539 port@2 { <<
1540 #addr <<
1541 #size <<
1542 <<
1543 reg = <<
1544 <<
1545 vin12 <<
1546 <<
1547 <<
1548 }; <<
1549 }; <<
1550 }; <<
1551 }; <<
1552 <<
1553 vin13: video@e6efd000 { <<
1554 compatible = "renesas <<
1555 "renesas <<
1556 reg = <0 0xe6efd000 0 <<
1557 interrupts = <GIC_SPI <<
1558 clocks = <&cpg CPG_MO <<
1559 power-domains = <&sys <<
1560 resets = <&cpg 811>; <<
1561 renesas,id = <13>; <<
1562 status = "disabled"; <<
1563 <<
1564 ports { <<
1565 #address-cell <<
1566 #size-cells = <<
1567 <<
1568 port@2 { <<
1569 #addr <<
1570 #size <<
1571 <<
1572 reg = <<
1573 <<
1574 vin13 <<
1575 <<
1576 <<
1577 }; <<
1578 }; <<
1579 }; <<
1580 }; <<
1581 <<
1582 vin14: video@e6efe000 { <<
1583 compatible = "renesas <<
1584 "renesas <<
1585 reg = <0 0xe6efe000 0 <<
1586 interrupts = <GIC_SPI <<
1587 clocks = <&cpg CPG_MO <<
1588 power-domains = <&sys <<
1589 resets = <&cpg 812>; <<
1590 renesas,id = <14>; <<
1591 status = "disabled"; <<
1592 <<
1593 ports { <<
1594 #address-cell <<
1595 #size-cells = <<
1596 <<
1597 port@2 { <<
1598 #addr <<
1599 #size <<
1600 <<
1601 reg = <<
1602 <<
1603 vin14 <<
1604 <<
1605 <<
1606 }; <<
1607 }; <<
1608 }; <<
1609 }; <<
1610 <<
1611 vin15: video@e6eff000 { <<
1612 compatible = "renesas <<
1613 "renesas <<
1614 reg = <0 0xe6eff000 0 <<
1615 interrupts = <GIC_SPI <<
1616 clocks = <&cpg CPG_MO <<
1617 power-domains = <&sys <<
1618 resets = <&cpg 813>; <<
1619 renesas,id = <15>; <<
1620 status = "disabled"; <<
1621 <<
1622 ports { <<
1623 #address-cell <<
1624 #size-cells = <<
1625 <<
1626 port@2 { <<
1627 #addr <<
1628 #size <<
1629 <<
1630 reg = <<
1631 <<
1632 vin15 <<
1633 <<
1634 <<
1635 }; <<
1636 }; <<
1637 }; <<
1638 }; <<
1639 <<
1640 vin16: video@e6ed0000 { <<
1641 compatible = "renesas <<
1642 "renesas <<
1643 reg = <0 0xe6ed0000 0 <<
1644 interrupts = <GIC_SPI <<
1645 clocks = <&cpg CPG_MO <<
1646 power-domains = <&sys <<
1647 resets = <&cpg 814>; <<
1648 renesas,id = <16>; <<
1649 status = "disabled"; <<
1650 <<
1651 ports { <<
1652 #address-cell <<
1653 #size-cells = <<
1654 <<
1655 port@2 { <<
1656 #addr <<
1657 #size <<
1658 <<
1659 reg = <<
1660 <<
1661 vin16 <<
1662 <<
1663 <<
1664 }; <<
1665 }; <<
1666 }; <<
1667 }; <<
1668 <<
1669 vin17: video@e6ed1000 { <<
1670 compatible = "renesas <<
1671 "renesas <<
1672 reg = <0 0xe6ed1000 0 <<
1673 interrupts = <GIC_SPI <<
1674 clocks = <&cpg CPG_MO <<
1675 power-domains = <&sys <<
1676 resets = <&cpg 815>; <<
1677 renesas,id = <17>; <<
1678 status = "disabled"; <<
1679 <<
1680 ports { <<
1681 #address-cell <<
1682 #size-cells = <<
1683 <<
1684 port@2 { <<
1685 #addr <<
1686 #size <<
1687 <<
1688 reg = <<
1689 <<
1690 vin17 <<
1691 <<
1692 <<
1693 }; <<
1694 }; <<
1695 }; <<
1696 }; <<
1697 <<
1698 vin18: video@e6ed2000 { <<
1699 compatible = "renesas <<
1700 "renesas <<
1701 reg = <0 0xe6ed2000 0 <<
1702 interrupts = <GIC_SPI <<
1703 clocks = <&cpg CPG_MO <<
1704 power-domains = <&sys <<
1705 resets = <&cpg 816>; <<
1706 renesas,id = <18>; <<
1707 status = "disabled"; <<
1708 <<
1709 ports { <<
1710 #address-cell <<
1711 #size-cells = <<
1712 <<
1713 port@2 { <<
1714 #addr <<
1715 #size <<
1716 <<
1717 reg = <<
1718 <<
1719 vin18 <<
1720 <<
1721 <<
1722 }; <<
1723 }; <<
1724 }; <<
1725 }; <<
1726 <<
1727 vin19: video@e6ed3000 { <<
1728 compatible = "renesas <<
1729 "renesas <<
1730 reg = <0 0xe6ed3000 0 <<
1731 interrupts = <GIC_SPI <<
1732 clocks = <&cpg CPG_MO <<
1733 power-domains = <&sys <<
1734 resets = <&cpg 817>; <<
1735 renesas,id = <19>; <<
1736 status = "disabled"; <<
1737 <<
1738 ports { <<
1739 #address-cell <<
1740 #size-cells = <<
1741 <<
1742 port@2 { <<
1743 #addr <<
1744 #size <<
1745 <<
1746 reg = <<
1747 <<
1748 vin19 <<
1749 <<
1750 <<
1751 }; <<
1752 }; <<
1753 }; <<
1754 }; <<
1755 <<
1756 vin20: video@e6ed4000 { <<
1757 compatible = "renesas <<
1758 "renesas <<
1759 reg = <0 0xe6ed4000 0 <<
1760 interrupts = <GIC_SPI <<
1761 clocks = <&cpg CPG_MO <<
1762 power-domains = <&sys <<
1763 resets = <&cpg 818>; <<
1764 renesas,id = <20>; <<
1765 status = "disabled"; <<
1766 <<
1767 ports { <<
1768 #address-cell <<
1769 #size-cells = <<
1770 <<
1771 port@2 { <<
1772 #addr <<
1773 #size <<
1774 <<
1775 reg = <<
1776 <<
1777 vin20 <<
1778 <<
1779 <<
1780 }; <<
1781 }; <<
1782 }; <<
1783 }; <<
1784 <<
1785 vin21: video@e6ed5000 { <<
1786 compatible = "renesas <<
1787 "renesas <<
1788 reg = <0 0xe6ed5000 0 <<
1789 interrupts = <GIC_SPI <<
1790 clocks = <&cpg CPG_MO <<
1791 power-domains = <&sys <<
1792 resets = <&cpg 819>; <<
1793 renesas,id = <21>; <<
1794 status = "disabled"; <<
1795 <<
1796 ports { <<
1797 #address-cell <<
1798 #size-cells = <<
1799 <<
1800 port@2 { <<
1801 #addr <<
1802 #size <<
1803 <<
1804 reg = <<
1805 <<
1806 vin21 <<
1807 <<
1808 <<
1809 }; <<
1810 }; <<
1811 }; <<
1812 }; <<
1813 <<
1814 vin22: video@e6ed6000 { <<
1815 compatible = "renesas <<
1816 "renesas <<
1817 reg = <0 0xe6ed6000 0 <<
1818 interrupts = <GIC_SPI <<
1819 clocks = <&cpg CPG_MO <<
1820 power-domains = <&sys <<
1821 resets = <&cpg 820>; <<
1822 renesas,id = <22>; <<
1823 status = "disabled"; <<
1824 <<
1825 ports { <<
1826 #address-cell <<
1827 #size-cells = <<
1828 <<
1829 port@2 { <<
1830 #addr <<
1831 #size <<
1832 <<
1833 reg = <<
1834 <<
1835 vin22 <<
1836 <<
1837 <<
1838 }; <<
1839 }; <<
1840 }; <<
1841 }; <<
1842 <<
1843 vin23: video@e6ed7000 { <<
1844 compatible = "renesas <<
1845 "renesas <<
1846 reg = <0 0xe6ed7000 0 <<
1847 interrupts = <GIC_SPI <<
1848 clocks = <&cpg CPG_MO <<
1849 power-domains = <&sys <<
1850 resets = <&cpg 821>; <<
1851 renesas,id = <23>; <<
1852 status = "disabled"; <<
1853 <<
1854 ports { <<
1855 #address-cell <<
1856 #size-cells = <<
1857 <<
1858 port@2 { <<
1859 #addr <<
1860 #size <<
1861 <<
1862 reg = <<
1863 <<
1864 vin23 <<
1865 <<
1866 <<
1867 }; <<
1868 }; <<
1869 }; <<
1870 }; <<
1871 <<
1872 vin24: video@e6ed8000 { <<
1873 compatible = "renesas <<
1874 "renesas <<
1875 reg = <0 0xe6ed8000 0 <<
1876 interrupts = <GIC_SPI <<
1877 clocks = <&cpg CPG_MO <<
1878 power-domains = <&sys <<
1879 resets = <&cpg 822>; <<
1880 renesas,id = <24>; <<
1881 status = "disabled"; <<
1882 <<
1883 ports { <<
1884 #address-cell <<
1885 #size-cells = <<
1886 <<
1887 port@2 { <<
1888 #addr <<
1889 #size <<
1890 <<
1891 reg = <<
1892 <<
1893 vin24 <<
1894 <<
1895 <<
1896 }; <<
1897 }; <<
1898 }; <<
1899 }; <<
1900 <<
1901 vin25: video@e6ed9000 { <<
1902 compatible = "renesas <<
1903 "renesas <<
1904 reg = <0 0xe6ed9000 0 <<
1905 interrupts = <GIC_SPI <<
1906 clocks = <&cpg CPG_MO <<
1907 power-domains = <&sys <<
1908 resets = <&cpg 823>; <<
1909 renesas,id = <25>; <<
1910 status = "disabled"; <<
1911 <<
1912 ports { <<
1913 #address-cell <<
1914 #size-cells = <<
1915 <<
1916 port@2 { <<
1917 #addr <<
1918 #size <<
1919 <<
1920 reg = <<
1921 <<
1922 vin25 <<
1923 <<
1924 <<
1925 }; <<
1926 }; <<
1927 }; <<
1928 }; <<
1929 <<
1930 vin26: video@e6eda000 { <<
1931 compatible = "renesas <<
1932 "renesas <<
1933 reg = <0 0xe6eda000 0 <<
1934 interrupts = <GIC_SPI <<
1935 clocks = <&cpg CPG_MO <<
1936 power-domains = <&sys <<
1937 resets = <&cpg 824>; <<
1938 renesas,id = <26>; <<
1939 status = "disabled"; <<
1940 <<
1941 ports { <<
1942 #address-cell <<
1943 #size-cells = <<
1944 <<
1945 port@2 { <<
1946 #addr <<
1947 #size <<
1948 <<
1949 reg = <<
1950 <<
1951 vin26 <<
1952 <<
1953 <<
1954 }; <<
1955 }; <<
1956 }; <<
1957 }; <<
1958 <<
1959 vin27: video@e6edb000 { <<
1960 compatible = "renesas <<
1961 "renesas <<
1962 reg = <0 0xe6edb000 0 <<
1963 interrupts = <GIC_SPI <<
1964 clocks = <&cpg CPG_MO <<
1965 power-domains = <&sys <<
1966 resets = <&cpg 825>; <<
1967 renesas,id = <27>; <<
1968 status = "disabled"; <<
1969 <<
1970 ports { <<
1971 #address-cell <<
1972 #size-cells = <<
1973 <<
1974 port@2 { <<
1975 #addr <<
1976 #size <<
1977 <<
1978 reg = <<
1979 <<
1980 vin27 <<
1981 <<
1982 <<
1983 }; <<
1984 }; <<
1985 }; <<
1986 }; <<
1987 <<
1988 vin28: video@e6edc000 { <<
1989 compatible = "renesas <<
1990 "renesas <<
1991 reg = <0 0xe6edc000 0 <<
1992 interrupts = <GIC_SPI <<
1993 clocks = <&cpg CPG_MO <<
1994 power-domains = <&sys <<
1995 resets = <&cpg 826>; <<
1996 renesas,id = <28>; <<
1997 status = "disabled"; <<
1998 <<
1999 ports { <<
2000 #address-cell <<
2001 #size-cells = <<
2002 <<
2003 port@2 { <<
2004 #addr <<
2005 #size <<
2006 <<
2007 reg = <<
2008 <<
2009 vin28 <<
2010 <<
2011 <<
2012 }; <<
2013 }; <<
2014 }; <<
2015 }; <<
2016 <<
2017 vin29: video@e6edd000 { <<
2018 compatible = "renesas <<
2019 "renesas <<
2020 reg = <0 0xe6edd000 0 <<
2021 interrupts = <GIC_SPI <<
2022 clocks = <&cpg CPG_MO <<
2023 power-domains = <&sys <<
2024 resets = <&cpg 827>; <<
2025 renesas,id = <29>; <<
2026 status = "disabled"; <<
2027 <<
2028 ports { <<
2029 #address-cell <<
2030 #size-cells = <<
2031 <<
2032 port@2 { <<
2033 #addr <<
2034 #size <<
2035 <<
2036 reg = <<
2037 <<
2038 vin29 <<
2039 <<
2040 <<
2041 }; <<
2042 }; <<
2043 }; <<
2044 }; <<
2045 <<
2046 vin30: video@e6ede000 { <<
2047 compatible = "renesas <<
2048 "renesas <<
2049 reg = <0 0xe6ede000 0 <<
2050 interrupts = <GIC_SPI <<
2051 clocks = <&cpg CPG_MO <<
2052 power-domains = <&sys <<
2053 resets = <&cpg 828>; <<
2054 renesas,id = <30>; <<
2055 status = "disabled"; <<
2056 <<
2057 ports { <<
2058 #address-cell <<
2059 #size-cells = <<
2060 <<
2061 port@2 { <<
2062 #addr <<
2063 #size <<
2064 <<
2065 reg = <<
2066 <<
2067 vin30 <<
2068 <<
2069 <<
2070 }; <<
2071 }; <<
2072 }; <<
2073 }; <<
2074 <<
2075 vin31: video@e6edf000 { <<
2076 compatible = "renesas <<
2077 "renesas <<
2078 reg = <0 0xe6edf000 0 <<
2079 interrupts = <GIC_SPI <<
2080 clocks = <&cpg CPG_MO <<
2081 power-domains = <&sys <<
2082 resets = <&cpg 829>; <<
2083 renesas,id = <31>; <<
2084 status = "disabled"; <<
2085 <<
2086 ports { <<
2087 #address-cell <<
2088 #size-cells = <<
2089 <<
2090 port@2 { <<
2091 #addr <<
2092 #size <<
2093 <<
2094 reg = <<
2095 <<
2096 vin31 <<
2097 <<
2098 <<
2099 }; <<
2100 }; <<
2101 }; <<
2102 }; <<
2103 <<
2104 dmac1: dma-controller@e735000 872 dmac1: dma-controller@e7350000 {
2105 compatible = "renesas !! 873 compatible = "renesas,dmac-r8a779a0";
2106 "renesas <<
2107 reg = <0 0xe7350000 0 874 reg = <0 0xe7350000 0 0x1000>,
2108 <0 0xe7300000 0 875 <0 0xe7300000 0 0x10000>;
2109 interrupts = <GIC_SPI 876 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
2110 <GIC_SPI 877 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
2111 <GIC_SPI 878 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
2112 <GIC_SPI 879 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
2113 <GIC_SPI 880 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
2114 <GIC_SPI 881 <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
2115 <GIC_SPI 882 <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
2116 <GIC_SPI 883 <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
2117 <GIC_SPI 884 <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
2118 <GIC_SPI 885 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
2119 <GIC_SPI 886 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
2120 <GIC_SPI 887 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
2121 <GIC_SPI 888 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
2122 <GIC_SPI 889 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
2123 <GIC_SPI 890 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
2124 <GIC_SPI 891 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
2125 <GIC_SPI 892 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
2126 interrupt-names = "er 893 interrupt-names = "error",
2127 "ch 894 "ch0", "ch1", "ch2", "ch3", "ch4",
2128 "ch 895 "ch5", "ch6", "ch7", "ch8", "ch9",
2129 "ch 896 "ch10", "ch11", "ch12", "ch13",
2130 "ch 897 "ch14", "ch15";
2131 clocks = <&cpg CPG_MO 898 clocks = <&cpg CPG_MOD 709>;
2132 clock-names = "fck"; 899 clock-names = "fck";
2133 power-domains = <&sys 900 power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
2134 resets = <&cpg 709>; 901 resets = <&cpg 709>;
2135 #dma-cells = <1>; 902 #dma-cells = <1>;
2136 dma-channels = <16>; 903 dma-channels = <16>;
2137 iommus = <&ipmmu_ds0 <<
2138 <&ipmmu_ds0 <<
2139 <&ipmmu_ds0 <<
2140 <&ipmmu_ds0 <<
2141 <&ipmmu_ds0 <<
2142 <&ipmmu_ds0 <<
2143 <&ipmmu_ds0 <<
2144 <&ipmmu_ds0 <<
2145 }; 904 };
2146 905
2147 dmac2: dma-controller@e735100 906 dmac2: dma-controller@e7351000 {
2148 compatible = "renesas !! 907 compatible = "renesas,dmac-r8a779a0";
2149 "renesas <<
2150 reg = <0 0xe7351000 0 908 reg = <0 0xe7351000 0 0x1000>,
2151 <0 0xe7310000 0 909 <0 0xe7310000 0 0x10000>;
2152 interrupts = <GIC_SPI 910 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
2153 <GIC_SPI 911 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
2154 <GIC_SPI 912 <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
2155 <GIC_SPI 913 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
2156 <GIC_SPI 914 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
2157 <GIC_SPI 915 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
2158 <GIC_SPI 916 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
2159 <GIC_SPI 917 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
2160 <GIC_SPI 918 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
2161 interrupt-names = "er 919 interrupt-names = "error",
2162 "ch 920 "ch0", "ch1", "ch2", "ch3", "ch4",
2163 "ch 921 "ch5", "ch6", "ch7";
2164 clocks = <&cpg CPG_MO 922 clocks = <&cpg CPG_MOD 710>;
2165 clock-names = "fck"; 923 clock-names = "fck";
2166 power-domains = <&sys 924 power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
2167 resets = <&cpg 710>; 925 resets = <&cpg 710>;
2168 #dma-cells = <1>; 926 #dma-cells = <1>;
2169 dma-channels = <8>; 927 dma-channels = <8>;
2170 iommus = <&ipmmu_ds0 <<
2171 <&ipmmu_ds0 <<
2172 <&ipmmu_ds0 <<
2173 <&ipmmu_ds0 <<
2174 }; 928 };
2175 929
2176 mmc0: mmc@ee140000 { 930 mmc0: mmc@ee140000 {
2177 compatible = "renesas 931 compatible = "renesas,sdhi-r8a779a0",
2178 "renesas !! 932 "renesas,rcar-gen3-sdhi";
2179 reg = <0 0xee140000 0 933 reg = <0 0xee140000 0 0x2000>;
2180 interrupts = <GIC_SPI 934 interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>;
2181 clocks = <&cpg CPG_MO !! 935 clocks = <&cpg CPG_MOD 706>;
2182 clock-names = "core", <<
2183 power-domains = <&sys 936 power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
2184 resets = <&cpg 706>; 937 resets = <&cpg 706>;
2185 max-frequency = <2000 938 max-frequency = <200000000>;
2186 iommus = <&ipmmu_ds0 <<
2187 status = "disabled"; <<
2188 }; <<
2189 <<
2190 rpc: spi@ee200000 { <<
2191 compatible = "renesas <<
2192 "renesas <<
2193 reg = <0 0xee200000 0 <<
2194 <0 0x08000000 0 <<
2195 <0 0xee208000 0 <<
2196 reg-names = "regs", " <<
2197 interrupts = <GIC_SPI <<
2198 clocks = <&cpg CPG_MO <<
2199 power-domains = <&sys <<
2200 resets = <&cpg 629>; <<
2201 #address-cells = <1>; <<
2202 #size-cells = <0>; <<
2203 status = "disabled"; 939 status = "disabled";
2204 }; 940 };
2205 941
2206 ipmmu_rt0: iommu@ee480000 { <<
2207 compatible = "renesas <<
2208 "renesas <<
2209 reg = <0 0xee480000 0 <<
2210 renesas,ipmmu-main = <<
2211 power-domains = <&sys <<
2212 #iommu-cells = <1>; <<
2213 }; <<
2214 <<
2215 ipmmu_rt1: iommu@ee4c0000 { <<
2216 compatible = "renesas <<
2217 "renesas <<
2218 reg = <0 0xee4c0000 0 <<
2219 renesas,ipmmu-main = <<
2220 power-domains = <&sys <<
2221 #iommu-cells = <1>; <<
2222 }; <<
2223 <<
2224 ipmmu_ds0: iommu@eed00000 { <<
2225 compatible = "renesas <<
2226 "renesas <<
2227 reg = <0 0xeed00000 0 <<
2228 renesas,ipmmu-main = <<
2229 power-domains = <&sys <<
2230 #iommu-cells = <1>; <<
2231 }; <<
2232 <<
2233 ipmmu_ds1: iommu@eed40000 { <<
2234 compatible = "renesas <<
2235 "renesas <<
2236 reg = <0 0xeed40000 0 <<
2237 renesas,ipmmu-main = <<
2238 power-domains = <&sys <<
2239 #iommu-cells = <1>; <<
2240 }; <<
2241 <<
2242 ipmmu_ir: iommu@eed80000 { <<
2243 compatible = "renesas <<
2244 "renesas <<
2245 reg = <0 0xeed80000 0 <<
2246 renesas,ipmmu-main = <<
2247 power-domains = <&sys <<
2248 #iommu-cells = <1>; <<
2249 }; <<
2250 <<
2251 ipmmu_vc0: iommu@eedc0000 { <<
2252 compatible = "renesas <<
2253 "renesas <<
2254 reg = <0 0xeedc0000 0 <<
2255 renesas,ipmmu-main = <<
2256 power-domains = <&sys <<
2257 #iommu-cells = <1>; <<
2258 }; <<
2259 <<
2260 ipmmu_vi0: iommu@eee80000 { <<
2261 compatible = "renesas <<
2262 "renesas <<
2263 reg = <0 0xeee80000 0 <<
2264 renesas,ipmmu-main = <<
2265 power-domains = <&sys <<
2266 #iommu-cells = <1>; <<
2267 }; <<
2268 <<
2269 ipmmu_vi1: iommu@eeec0000 { <<
2270 compatible = "renesas <<
2271 "renesas <<
2272 reg = <0 0xeeec0000 0 <<
2273 renesas,ipmmu-main = <<
2274 power-domains = <&sys <<
2275 #iommu-cells = <1>; <<
2276 }; <<
2277 <<
2278 ipmmu_3dg: iommu@eee00000 { <<
2279 compatible = "renesas <<
2280 "renesas <<
2281 reg = <0 0xeee00000 0 <<
2282 renesas,ipmmu-main = <<
2283 power-domains = <&sys <<
2284 #iommu-cells = <1>; <<
2285 }; <<
2286 <<
2287 ipmmu_vip0: iommu@eef00000 { <<
2288 compatible = "renesas <<
2289 "renesas <<
2290 reg = <0 0xeef00000 0 <<
2291 renesas,ipmmu-main = <<
2292 power-domains = <&sys <<
2293 #iommu-cells = <1>; <<
2294 }; <<
2295 <<
2296 ipmmu_vip1: iommu@eef40000 { <<
2297 compatible = "renesas <<
2298 "renesas <<
2299 reg = <0 0xeef40000 0 <<
2300 renesas,ipmmu-main = <<
2301 power-domains = <&sys <<
2302 #iommu-cells = <1>; <<
2303 }; <<
2304 <<
2305 ipmmu_mm: iommu@eefc0000 { <<
2306 compatible = "renesas <<
2307 "renesas <<
2308 reg = <0 0xeefc0000 0 <<
2309 interrupts = <GIC_SPI <<
2310 <GIC_SPI <<
2311 power-domains = <&sys <<
2312 #iommu-cells = <1>; <<
2313 }; <<
2314 <<
2315 gic: interrupt-controller@f10 942 gic: interrupt-controller@f1000000 {
2316 compatible = "arm,gic 943 compatible = "arm,gic-v3";
2317 #interrupt-cells = <3 944 #interrupt-cells = <3>;
2318 #address-cells = <0>; 945 #address-cells = <0>;
2319 interrupt-controller; 946 interrupt-controller;
2320 reg = <0x0 0xf1000000 947 reg = <0x0 0xf1000000 0 0x20000>,
2321 <0x0 0xf1060000 948 <0x0 0xf1060000 0 0x110000>;
2322 interrupts = <GIC_PPI !! 949 interrupts = <GIC_PPI 9
2323 }; !! 950 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
2324 <<
2325 fcpvd0: fcp@fea10000 { <<
2326 compatible = "renesas <<
2327 reg = <0 0xfea10000 0 <<
2328 clocks = <&cpg CPG_MO <<
2329 power-domains = <&sys <<
2330 resets = <&cpg 508>; <<
2331 iommus = <&ipmmu_vi1 <<
2332 }; <<
2333 <<
2334 fcpvd1: fcp@fea11000 { <<
2335 compatible = "renesas <<
2336 reg = <0 0xfea11000 0 <<
2337 clocks = <&cpg CPG_MO <<
2338 power-domains = <&sys <<
2339 resets = <&cpg 509>; <<
2340 iommus = <&ipmmu_vi1 <<
2341 }; <<
2342 <<
2343 vspd0: vsp@fea20000 { <<
2344 compatible = "renesas <<
2345 reg = <0 0xfea20000 0 <<
2346 interrupts = <GIC_SPI <<
2347 clocks = <&cpg CPG_MO <<
2348 power-domains = <&sys <<
2349 resets = <&cpg 830>; <<
2350 <<
2351 renesas,fcp = <&fcpvd <<
2352 }; <<
2353 <<
2354 vspd1: vsp@fea28000 { <<
2355 compatible = "renesas <<
2356 reg = <0 0xfea28000 0 <<
2357 interrupts = <GIC_SPI <<
2358 clocks = <&cpg CPG_MO <<
2359 power-domains = <&sys <<
2360 resets = <&cpg 831>; <<
2361 <<
2362 renesas,fcp = <&fcpvd <<
2363 }; <<
2364 <<
2365 csi40: csi2@feaa0000 { <<
2366 compatible = "renesas <<
2367 reg = <0 0xfeaa0000 0 <<
2368 interrupts = <GIC_SPI <<
2369 clocks = <&cpg CPG_MO <<
2370 power-domains = <&sys <<
2371 resets = <&cpg 331>; <<
2372 status = "disabled"; <<
2373 <<
2374 ports { <<
2375 #address-cell <<
2376 #size-cells = <<
2377 <<
2378 port@0 { <<
2379 reg = <<
2380 }; <<
2381 <<
2382 port@1 { <<
2383 reg = <<
2384 csi40 <<
2385 <<
2386 }; <<
2387 }; <<
2388 }; <<
2389 }; <<
2390 <<
2391 csi41: csi2@feab0000 { <<
2392 compatible = "renesas <<
2393 reg = <0 0xfeab0000 0 <<
2394 interrupts = <GIC_SPI <<
2395 clocks = <&cpg CPG_MO <<
2396 power-domains = <&sys <<
2397 resets = <&cpg 400>; <<
2398 status = "disabled"; <<
2399 <<
2400 ports { <<
2401 #address-cell <<
2402 #size-cells = <<
2403 <<
2404 port@0 { <<
2405 reg = <<
2406 }; <<
2407 <<
2408 port@1 { <<
2409 reg = <<
2410 csi41 <<
2411 <<
2412 }; <<
2413 }; <<
2414 }; <<
2415 }; <<
2416 <<
2417 csi42: csi2@fed60000 { <<
2418 compatible = "renesas <<
2419 reg = <0 0xfed60000 0 <<
2420 interrupts = <GIC_SPI <<
2421 clocks = <&cpg CPG_MO <<
2422 power-domains = <&sys <<
2423 resets = <&cpg 401>; <<
2424 status = "disabled"; <<
2425 <<
2426 ports { <<
2427 #address-cell <<
2428 #size-cells = <<
2429 <<
2430 port@0 { <<
2431 reg = <<
2432 }; <<
2433 <<
2434 port@1 { <<
2435 reg = <<
2436 csi42 <<
2437 <<
2438 }; <<
2439 }; <<
2440 }; <<
2441 }; <<
2442 <<
2443 csi43: csi2@fed70000 { <<
2444 compatible = "renesas <<
2445 reg = <0 0xfed70000 0 <<
2446 interrupts = <GIC_SPI <<
2447 clocks = <&cpg CPG_MO <<
2448 power-domains = <&sys <<
2449 resets = <&cpg 402>; <<
2450 status = "disabled"; <<
2451 <<
2452 ports { <<
2453 #address-cell <<
2454 #size-cells = <<
2455 <<
2456 port@0 { <<
2457 reg = <<
2458 }; <<
2459 <<
2460 port@1 { <<
2461 reg = <<
2462 csi43 <<
2463 <<
2464 }; <<
2465 }; <<
2466 }; <<
2467 }; <<
2468 <<
2469 du: display@feb00000 { <<
2470 compatible = "renesas <<
2471 reg = <0 0xfeb00000 0 <<
2472 interrupts = <GIC_SPI <<
2473 <GIC_SPI <<
2474 clocks = <&cpg CPG_MO <<
2475 clock-names = "du.0"; <<
2476 power-domains = <&sys <<
2477 resets = <&cpg 411>; <<
2478 reset-names = "du.0"; <<
2479 renesas,vsps = <&vspd <<
2480 <<
2481 status = "disabled"; <<
2482 <<
2483 ports { <<
2484 #address-cell <<
2485 #size-cells = <<
2486 <<
2487 port@0 { <<
2488 reg = <<
2489 du_ou <<
2490 <<
2491 }; <<
2492 }; <<
2493 <<
2494 port@1 { <<
2495 reg = <<
2496 du_ou <<
2497 <<
2498 }; <<
2499 }; <<
2500 }; <<
2501 }; <<
2502 <<
2503 isp0: isp@fed00000 { <<
2504 compatible = "renesas <<
2505 "renesas <<
2506 reg = <0 0xfed00000 0 <<
2507 interrupts = <GIC_SPI <<
2508 clocks = <&cpg CPG_MO <<
2509 power-domains = <&sys <<
2510 resets = <&cpg 612>; <<
2511 status = "disabled"; <<
2512 <<
2513 ports { <<
2514 #address-cell <<
2515 #size-cells = <<
2516 <<
2517 port@0 { <<
2518 #addr <<
2519 #size <<
2520 <<
2521 reg = <<
2522 <<
2523 isp0c <<
2524 <<
2525 <<
2526 }; <<
2527 }; <<
2528 <<
2529 port@1 { <<
2530 reg = <<
2531 isp0v <<
2532 <<
2533 }; <<
2534 }; <<
2535 <<
2536 port@2 { <<
2537 reg = <<
2538 isp0v <<
2539 <<
2540 }; <<
2541 }; <<
2542 <<
2543 port@3 { <<
2544 reg = <<
2545 isp0v <<
2546 <<
2547 }; <<
2548 }; <<
2549 <<
2550 port@4 { <<
2551 reg = <<
2552 isp0v <<
2553 <<
2554 }; <<
2555 }; <<
2556 <<
2557 port@5 { <<
2558 reg = <<
2559 isp0v <<
2560 <<
2561 }; <<
2562 }; <<
2563 <<
2564 port@6 { <<
2565 reg = <<
2566 isp0v <<
2567 <<
2568 }; <<
2569 }; <<
2570 <<
2571 port@7 { <<
2572 reg = <<
2573 isp0v <<
2574 <<
2575 }; <<
2576 }; <<
2577 <<
2578 port@8 { <<
2579 reg = <<
2580 isp0v <<
2581 <<
2582 }; <<
2583 }; <<
2584 }; <<
2585 }; <<
2586 <<
2587 isp1: isp@fed20000 { <<
2588 compatible = "renesas <<
2589 "renesas <<
2590 reg = <0 0xfed20000 0 <<
2591 interrupts = <GIC_SPI <<
2592 clocks = <&cpg CPG_MO <<
2593 power-domains = <&sys <<
2594 resets = <&cpg 613>; <<
2595 status = "disabled"; <<
2596 <<
2597 ports { <<
2598 #address-cell <<
2599 #size-cells = <<
2600 <<
2601 port@0 { <<
2602 #addr <<
2603 #size <<
2604 <<
2605 reg = <<
2606 <<
2607 isp1c <<
2608 <<
2609 <<
2610 }; <<
2611 }; <<
2612 <<
2613 port@1 { <<
2614 reg = <<
2615 isp1v <<
2616 <<
2617 }; <<
2618 }; <<
2619 <<
2620 port@2 { <<
2621 reg = <<
2622 isp1v <<
2623 <<
2624 }; <<
2625 }; <<
2626 <<
2627 port@3 { <<
2628 reg = <<
2629 isp1v <<
2630 <<
2631 }; <<
2632 }; <<
2633 <<
2634 port@4 { <<
2635 reg = <<
2636 isp1v <<
2637 <<
2638 }; <<
2639 }; <<
2640 <<
2641 port@5 { <<
2642 reg = <<
2643 isp1v <<
2644 <<
2645 }; <<
2646 }; <<
2647 <<
2648 port@6 { <<
2649 reg = <<
2650 isp1v <<
2651 <<
2652 }; <<
2653 }; <<
2654 <<
2655 port@7 { <<
2656 reg = <<
2657 isp1v <<
2658 <<
2659 }; <<
2660 }; <<
2661 <<
2662 port@8 { <<
2663 reg = <<
2664 isp1v <<
2665 <<
2666 }; <<
2667 }; <<
2668 }; <<
2669 }; <<
2670 <<
2671 isp2: isp@fed30000 { <<
2672 compatible = "renesas <<
2673 "renesas <<
2674 reg = <0 0xfed30000 0 <<
2675 interrupts = <GIC_SPI <<
2676 clocks = <&cpg CPG_MO <<
2677 power-domains = <&sys <<
2678 resets = <&cpg 614>; <<
2679 status = "disabled"; <<
2680 <<
2681 ports { <<
2682 #address-cell <<
2683 #size-cells = <<
2684 <<
2685 port@0 { <<
2686 #addr <<
2687 #size <<
2688 <<
2689 reg = <<
2690 <<
2691 isp2c <<
2692 <<
2693 <<
2694 }; <<
2695 }; <<
2696 <<
2697 port@1 { <<
2698 reg = <<
2699 isp2v <<
2700 <<
2701 }; <<
2702 }; <<
2703 <<
2704 port@2 { <<
2705 reg = <<
2706 isp2v <<
2707 <<
2708 }; <<
2709 }; <<
2710 <<
2711 port@3 { <<
2712 reg = <<
2713 isp2v <<
2714 <<
2715 }; <<
2716 }; <<
2717 <<
2718 port@4 { <<
2719 reg = <<
2720 isp2v <<
2721 <<
2722 }; <<
2723 }; <<
2724 <<
2725 port@5 { <<
2726 reg = <<
2727 isp2v <<
2728 <<
2729 }; <<
2730 }; <<
2731 <<
2732 port@6 { <<
2733 reg = <<
2734 isp2v <<
2735 <<
2736 }; <<
2737 }; <<
2738 <<
2739 port@7 { <<
2740 reg = <<
2741 isp2v <<
2742 <<
2743 }; <<
2744 }; <<
2745 <<
2746 port@8 { <<
2747 reg = <<
2748 isp2v <<
2749 <<
2750 }; <<
2751 }; <<
2752 }; <<
2753 }; <<
2754 <<
2755 isp3: isp@fed40000 { <<
2756 compatible = "renesas <<
2757 "renesas <<
2758 reg = <0 0xfed40000 0 <<
2759 interrupts = <GIC_SPI <<
2760 clocks = <&cpg CPG_MO <<
2761 power-domains = <&sys <<
2762 resets = <&cpg 615>; <<
2763 status = "disabled"; <<
2764 <<
2765 ports { <<
2766 #address-cell <<
2767 #size-cells = <<
2768 <<
2769 port@0 { <<
2770 #addr <<
2771 #size <<
2772 <<
2773 reg = <<
2774 <<
2775 isp3c <<
2776 <<
2777 <<
2778 }; <<
2779 }; <<
2780 <<
2781 port@1 { <<
2782 reg = <<
2783 isp3v <<
2784 <<
2785 }; <<
2786 }; <<
2787 <<
2788 port@2 { <<
2789 reg = <<
2790 isp3v <<
2791 <<
2792 }; <<
2793 }; <<
2794 <<
2795 port@3 { <<
2796 reg = <<
2797 isp3v <<
2798 <<
2799 }; <<
2800 }; <<
2801 <<
2802 port@4 { <<
2803 reg = <<
2804 isp3v <<
2805 <<
2806 }; <<
2807 }; <<
2808 <<
2809 port@5 { <<
2810 reg = <<
2811 isp3v <<
2812 <<
2813 }; <<
2814 }; <<
2815 <<
2816 port@6 { <<
2817 reg = <<
2818 isp3v <<
2819 <<
2820 }; <<
2821 }; <<
2822 <<
2823 port@7 { <<
2824 reg = <<
2825 isp3v <<
2826 <<
2827 }; <<
2828 }; <<
2829 <<
2830 port@8 { <<
2831 reg = <<
2832 isp3v <<
2833 <<
2834 }; <<
2835 }; <<
2836 }; <<
2837 }; <<
2838 <<
2839 dsi0: dsi-encoder@fed80000 { <<
2840 compatible = "renesas <<
2841 reg = <0 0xfed80000 0 <<
2842 power-domains = <&sys <<
2843 clocks = <&cpg CPG_MO <<
2844 <&cpg CPG_CO <<
2845 <&cpg CPG_CO <<
2846 clock-names = "fck", <<
2847 resets = <&cpg 415>; <<
2848 status = "disabled"; <<
2849 <<
2850 ports { <<
2851 #address-cell <<
2852 #size-cells = <<
2853 <<
2854 port@0 { <<
2855 reg = <<
2856 dsi0_ <<
2857 <<
2858 }; <<
2859 }; <<
2860 <<
2861 port@1 { <<
2862 reg = <<
2863 }; <<
2864 }; <<
2865 }; <<
2866 <<
2867 dsi1: dsi-encoder@fed90000 { <<
2868 compatible = "renesas <<
2869 reg = <0 0xfed90000 0 <<
2870 power-domains = <&sys <<
2871 clocks = <&cpg CPG_MO <<
2872 <&cpg CPG_CO <<
2873 <&cpg CPG_CO <<
2874 clock-names = "fck", <<
2875 resets = <&cpg 416>; <<
2876 status = "disabled"; <<
2877 <<
2878 ports { <<
2879 #address-cell <<
2880 #size-cells = <<
2881 <<
2882 port@0 { <<
2883 reg = <<
2884 dsi1_ <<
2885 <<
2886 }; <<
2887 }; <<
2888 <<
2889 port@1 { <<
2890 reg = <<
2891 }; <<
2892 }; <<
2893 }; 951 };
2894 952
2895 prr: chipid@fff00044 { 953 prr: chipid@fff00044 {
2896 compatible = "renesas 954 compatible = "renesas,prr";
2897 reg = <0 0xfff00044 0 955 reg = <0 0xfff00044 0 4>;
2898 }; 956 };
2899 }; 957 };
2900 958
2901 thermal-zones { <<
2902 sensor1_thermal: sensor1-ther <<
2903 polling-delay-passive <<
2904 polling-delay = <1000 <<
2905 thermal-sensors = <&t <<
2906 <<
2907 trips { <<
2908 sensor1_crit: <<
2909 tempe <<
2910 hyste <<
2911 type <<
2912 }; <<
2913 }; <<
2914 }; <<
2915 <<
2916 sensor2_thermal: sensor2-ther <<
2917 polling-delay-passive <<
2918 polling-delay = <1000 <<
2919 thermal-sensors = <&t <<
2920 <<
2921 trips { <<
2922 sensor2_crit: <<
2923 tempe <<
2924 hyste <<
2925 type <<
2926 }; <<
2927 }; <<
2928 }; <<
2929 <<
2930 sensor3_thermal: sensor3-ther <<
2931 polling-delay-passive <<
2932 polling-delay = <1000 <<
2933 thermal-sensors = <&t <<
2934 <<
2935 trips { <<
2936 sensor3_crit: <<
2937 tempe <<
2938 hyste <<
2939 type <<
2940 }; <<
2941 }; <<
2942 }; <<
2943 <<
2944 sensor4_thermal: sensor4-ther <<
2945 polling-delay-passive <<
2946 polling-delay = <1000 <<
2947 thermal-sensors = <&t <<
2948 <<
2949 trips { <<
2950 sensor4_crit: <<
2951 tempe <<
2952 hyste <<
2953 type <<
2954 }; <<
2955 }; <<
2956 }; <<
2957 <<
2958 sensor5_thermal: sensor5-ther <<
2959 polling-delay-passive <<
2960 polling-delay = <1000 <<
2961 thermal-sensors = <&t <<
2962 <<
2963 trips { <<
2964 sensor5_crit: <<
2965 tempe <<
2966 hyste <<
2967 type <<
2968 }; <<
2969 }; <<
2970 }; <<
2971 }; <<
2972 <<
2973 timer { 959 timer {
2974 compatible = "arm,armv8-timer 960 compatible = "arm,armv8-timer";
2975 interrupts-extended = <&gic G !! 961 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
2976 <&gic G !! 962 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
2977 <&gic G !! 963 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
2978 <&gic G !! 964 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
2979 <&gic G <<
2980 interrupt-names = "sec-phys", <<
2981 "hyp-virt"; <<
2982 }; 965 };
2983 }; 966 };
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