1 // SPDX-License-Identifier: (GPL-2.0 OR MIT) !! 1 // SPDX-License-Identifier: (GPL-2.0 or MIT)
2 /* 2 /*
3 * Device Tree Source for the R-Car S4-8 (R8A7 3 * Device Tree Source for the R-Car S4-8 (R8A779F0) SoC
4 * 4 *
5 * Copyright (C) 2021 Renesas Electronics Corp 5 * Copyright (C) 2021 Renesas Electronics Corp.
6 */ 6 */
7 7
8 #include <dt-bindings/clock/r8a779f0-cpg-mssr. 8 #include <dt-bindings/clock/r8a779f0-cpg-mssr.h>
9 #include <dt-bindings/interrupt-controller/arm 9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/power/r8a779f0-sysc.h> 10 #include <dt-bindings/power/r8a779f0-sysc.h>
11 11
12 / { 12 / {
13 compatible = "renesas,r8a779f0"; 13 compatible = "renesas,r8a779f0";
14 #address-cells = <2>; 14 #address-cells = <2>;
15 #size-cells = <2>; 15 #size-cells = <2>;
16 16
17 cluster01_opp: opp-table-0 { <<
18 compatible = "operating-points <<
19 opp-shared; <<
20 <<
21 opp-500000000 { <<
22 opp-hz = /bits/ 64 <50 <<
23 opp-microvolt = <88000 <<
24 clock-latency-ns = <50 <<
25 }; <<
26 opp-800000000 { <<
27 opp-hz = /bits/ 64 <80 <<
28 opp-microvolt = <88000 <<
29 clock-latency-ns = <50 <<
30 }; <<
31 opp-1000000000 { <<
32 opp-hz = /bits/ 64 <10 <<
33 opp-microvolt = <88000 <<
34 clock-latency-ns = <50 <<
35 }; <<
36 opp-1200000000 { <<
37 opp-hz = /bits/ 64 <12 <<
38 opp-microvolt = <88000 <<
39 clock-latency-ns = <50 <<
40 opp-suspend; <<
41 }; <<
42 }; <<
43 <<
44 cluster23_opp: opp-table-1 { <<
45 compatible = "operating-points <<
46 opp-shared; <<
47 <<
48 opp-500000000 { <<
49 opp-hz = /bits/ 64 <50 <<
50 opp-microvolt = <88000 <<
51 clock-latency-ns = <50 <<
52 }; <<
53 opp-800000000 { <<
54 opp-hz = /bits/ 64 <80 <<
55 opp-microvolt = <88000 <<
56 clock-latency-ns = <50 <<
57 }; <<
58 opp-1000000000 { <<
59 opp-hz = /bits/ 64 <10 <<
60 opp-microvolt = <88000 <<
61 clock-latency-ns = <50 <<
62 }; <<
63 opp-1200000000 { <<
64 opp-hz = /bits/ 64 <12 <<
65 opp-microvolt = <88000 <<
66 clock-latency-ns = <50 <<
67 opp-suspend; <<
68 }; <<
69 }; <<
70 <<
71 cpus { 17 cpus {
72 #address-cells = <1>; 18 #address-cells = <1>;
73 #size-cells = <0>; 19 #size-cells = <0>;
74 20
75 cpu-map { <<
76 cluster0 { <<
77 core0 { <<
78 cpu = <<
79 }; <<
80 core1 { <<
81 cpu = <<
82 }; <<
83 }; <<
84 <<
85 cluster1 { <<
86 core0 { <<
87 cpu = <<
88 }; <<
89 core1 { <<
90 cpu = <<
91 }; <<
92 }; <<
93 <<
94 cluster2 { <<
95 core0 { <<
96 cpu = <<
97 }; <<
98 core1 { <<
99 cpu = <<
100 }; <<
101 }; <<
102 <<
103 cluster3 { <<
104 core0 { <<
105 cpu = <<
106 }; <<
107 core1 { <<
108 cpu = <<
109 }; <<
110 }; <<
111 }; <<
112 <<
113 a55_0: cpu@0 { 21 a55_0: cpu@0 {
114 compatible = "arm,cort 22 compatible = "arm,cortex-a55";
115 reg = <0>; 23 reg = <0>;
116 device_type = "cpu"; 24 device_type = "cpu";
117 power-domains = <&sysc 25 power-domains = <&sysc R8A779F0_PD_A1E0D0C0>;
118 next-level-cache = <&L <<
119 enable-method = "psci" <<
120 cpu-idle-states = <&CP <<
121 clocks = <&cpg CPG_COR <<
122 operating-points-v2 = <<
123 }; <<
124 <<
125 a55_1: cpu@100 { <<
126 compatible = "arm,cort <<
127 reg = <0x100>; <<
128 device_type = "cpu"; <<
129 power-domains = <&sysc <<
130 next-level-cache = <&L <<
131 enable-method = "psci" <<
132 cpu-idle-states = <&CP <<
133 clocks = <&cpg CPG_COR <<
134 operating-points-v2 = <<
135 }; <<
136 <<
137 a55_2: cpu@10000 { <<
138 compatible = "arm,cort <<
139 reg = <0x10000>; <<
140 device_type = "cpu"; <<
141 power-domains = <&sysc <<
142 next-level-cache = <&L <<
143 enable-method = "psci" <<
144 cpu-idle-states = <&CP <<
145 clocks = <&cpg CPG_COR <<
146 operating-points-v2 = <<
147 }; <<
148 <<
149 a55_3: cpu@10100 { <<
150 compatible = "arm,cort <<
151 reg = <0x10100>; <<
152 device_type = "cpu"; <<
153 power-domains = <&sysc <<
154 next-level-cache = <&L <<
155 enable-method = "psci" <<
156 cpu-idle-states = <&CP <<
157 clocks = <&cpg CPG_COR <<
158 operating-points-v2 = <<
159 }; <<
160 <<
161 a55_4: cpu@20000 { <<
162 compatible = "arm,cort <<
163 reg = <0x20000>; <<
164 device_type = "cpu"; <<
165 power-domains = <&sysc <<
166 next-level-cache = <&L <<
167 enable-method = "psci" <<
168 cpu-idle-states = <&CP <<
169 clocks = <&cpg CPG_COR <<
170 operating-points-v2 = <<
171 }; <<
172 <<
173 a55_5: cpu@20100 { <<
174 compatible = "arm,cort <<
175 reg = <0x20100>; <<
176 device_type = "cpu"; <<
177 power-domains = <&sysc <<
178 next-level-cache = <&L <<
179 enable-method = "psci" <<
180 cpu-idle-states = <&CP <<
181 clocks = <&cpg CPG_COR <<
182 operating-points-v2 = <<
183 }; <<
184 <<
185 a55_6: cpu@30000 { <<
186 compatible = "arm,cort <<
187 reg = <0x30000>; <<
188 device_type = "cpu"; <<
189 power-domains = <&sysc <<
190 next-level-cache = <&L <<
191 enable-method = "psci" <<
192 cpu-idle-states = <&CP <<
193 clocks = <&cpg CPG_COR <<
194 operating-points-v2 = <<
195 }; <<
196 <<
197 a55_7: cpu@30100 { <<
198 compatible = "arm,cort <<
199 reg = <0x30100>; <<
200 device_type = "cpu"; <<
201 power-domains = <&sysc <<
202 next-level-cache = <&L <<
203 enable-method = "psci" <<
204 cpu-idle-states = <&CP <<
205 clocks = <&cpg CPG_COR <<
206 operating-points-v2 = <<
207 }; <<
208 <<
209 L3_CA55_0: cache-controller-0 <<
210 compatible = "cache"; <<
211 power-domains = <&sysc <<
212 cache-unified; <<
213 cache-level = <3>; <<
214 }; <<
215 <<
216 L3_CA55_1: cache-controller-1 <<
217 compatible = "cache"; <<
218 power-domains = <&sysc <<
219 cache-unified; <<
220 cache-level = <3>; <<
221 }; <<
222 <<
223 L3_CA55_2: cache-controller-2 <<
224 compatible = "cache"; <<
225 power-domains = <&sysc <<
226 cache-unified; <<
227 cache-level = <3>; <<
228 }; <<
229 <<
230 L3_CA55_3: cache-controller-3 <<
231 compatible = "cache"; <<
232 power-domains = <&sysc <<
233 cache-unified; <<
234 cache-level = <3>; <<
235 }; <<
236 <<
237 idle-states { <<
238 entry-method = "psci"; <<
239 <<
240 CPU_SLEEP_0: cpu-sleep <<
241 compatible = " <<
242 arm,psci-suspe <<
243 local-timer-st <<
244 entry-latency- <<
245 exit-latency-u <<
246 min-residency- <<
247 }; <<
248 }; 26 };
249 }; 27 };
250 28
251 extal_clk: extal { 29 extal_clk: extal {
252 compatible = "fixed-clock"; 30 compatible = "fixed-clock";
253 #clock-cells = <0>; 31 #clock-cells = <0>;
254 /* This value must be overridd 32 /* This value must be overridden by the board */
255 clock-frequency = <0>; 33 clock-frequency = <0>;
256 }; 34 };
257 35
258 extalr_clk: extalr { 36 extalr_clk: extalr {
259 compatible = "fixed-clock"; 37 compatible = "fixed-clock";
260 #clock-cells = <0>; 38 #clock-cells = <0>;
261 /* This value must be overridd 39 /* This value must be overridden by the board */
262 clock-frequency = <0>; 40 clock-frequency = <0>;
263 }; 41 };
264 42
265 pcie0_clkref: pcie0-clkref { <<
266 compatible = "fixed-clock"; <<
267 #clock-cells = <0>; <<
268 /* This value must be overridd <<
269 clock-frequency = <0>; <<
270 }; <<
271 <<
272 pcie1_clkref: pcie1-clkref { <<
273 compatible = "fixed-clock"; <<
274 #clock-cells = <0>; <<
275 /* This value must be overridd <<
276 clock-frequency = <0>; <<
277 }; <<
278 <<
279 pmu_a55 { 43 pmu_a55 {
280 compatible = "arm,cortex-a55-p 44 compatible = "arm,cortex-a55-pmu";
281 interrupts-extended = <&gic GI 45 interrupts-extended = <&gic GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
282 }; 46 };
283 47
284 psci { <<
285 compatible = "arm,psci-1.0", " <<
286 method = "smc"; <<
287 }; <<
288 <<
289 /* External SCIF clock - to be overrid 48 /* External SCIF clock - to be overridden by boards that provide it */
290 scif_clk: scif { 49 scif_clk: scif {
291 compatible = "fixed-clock"; 50 compatible = "fixed-clock";
292 #clock-cells = <0>; 51 #clock-cells = <0>;
293 clock-frequency = <0>; 52 clock-frequency = <0>;
294 }; 53 };
295 54
296 soc: soc { 55 soc: soc {
297 compatible = "simple-bus"; 56 compatible = "simple-bus";
298 interrupt-parent = <&gic>; 57 interrupt-parent = <&gic>;
299 #address-cells = <2>; 58 #address-cells = <2>;
300 #size-cells = <2>; 59 #size-cells = <2>;
301 ranges; 60 ranges;
302 61
303 rwdt: watchdog@e6020000 { <<
304 compatible = "renesas, <<
305 "renesas, <<
306 reg = <0 0xe6020000 0 <<
307 interrupts = <GIC_SPI <<
308 clocks = <&cpg CPG_MOD <<
309 power-domains = <&sysc <<
310 resets = <&cpg 907>; <<
311 status = "disabled"; <<
312 }; <<
313 <<
314 pfc: pinctrl@e6050000 { <<
315 compatible = "renesas, <<
316 reg = <0 0xe6050000 0 <<
317 <0 0xe6051000 0 <<
318 }; <<
319 <<
320 gpio0: gpio@e6050180 { <<
321 compatible = "renesas, <<
322 "renesas, <<
323 reg = <0 0xe6050180 0 <<
324 interrupts = <GIC_SPI <<
325 clocks = <&cpg CPG_MOD <<
326 power-domains = <&sysc <<
327 resets = <&cpg 915>; <<
328 gpio-controller; <<
329 #gpio-cells = <2>; <<
330 gpio-ranges = <&pfc 0 <<
331 interrupt-controller; <<
332 #interrupt-cells = <2> <<
333 }; <<
334 <<
335 gpio1: gpio@e6050980 { <<
336 compatible = "renesas, <<
337 "renesas, <<
338 reg = <0 0xe6050980 0 <<
339 interrupts = <GIC_SPI <<
340 clocks = <&cpg CPG_MOD <<
341 power-domains = <&sysc <<
342 resets = <&cpg 915>; <<
343 gpio-controller; <<
344 #gpio-cells = <2>; <<
345 gpio-ranges = <&pfc 0 <<
346 interrupt-controller; <<
347 #interrupt-cells = <2> <<
348 }; <<
349 <<
350 gpio2: gpio@e6051180 { <<
351 compatible = "renesas, <<
352 "renesas, <<
353 reg = <0 0xe6051180 0 <<
354 interrupts = <GIC_SPI <<
355 clocks = <&cpg CPG_MOD <<
356 power-domains = <&sysc <<
357 resets = <&cpg 915>; <<
358 gpio-controller; <<
359 #gpio-cells = <2>; <<
360 gpio-ranges = <&pfc 0 <<
361 interrupt-controller; <<
362 #interrupt-cells = <2> <<
363 }; <<
364 <<
365 gpio3: gpio@e6051980 { <<
366 compatible = "renesas, <<
367 "renesas, <<
368 reg = <0 0xe6051980 0 <<
369 interrupts = <GIC_SPI <<
370 clocks = <&cpg CPG_MOD <<
371 power-domains = <&sysc <<
372 resets = <&cpg 915>; <<
373 gpio-controller; <<
374 #gpio-cells = <2>; <<
375 gpio-ranges = <&pfc 0 <<
376 interrupt-controller; <<
377 #interrupt-cells = <2> <<
378 }; <<
379 <<
380 cmt0: timer@e60f0000 { <<
381 compatible = "renesas, <<
382 "renesas, <<
383 reg = <0 0xe60f0000 0 <<
384 interrupts = <GIC_SPI <<
385 <GIC_SPI <<
386 clocks = <&cpg CPG_MOD <<
387 clock-names = "fck"; <<
388 power-domains = <&sysc <<
389 resets = <&cpg 910>; <<
390 status = "disabled"; <<
391 }; <<
392 <<
393 cmt1: timer@e6130000 { <<
394 compatible = "renesas, <<
395 "renesas, <<
396 reg = <0 0xe6130000 0 <<
397 interrupts = <GIC_SPI <<
398 <GIC_SPI <<
399 <GIC_SPI <<
400 <GIC_SPI <<
401 <GIC_SPI <<
402 <GIC_SPI <<
403 <GIC_SPI <<
404 <GIC_SPI <<
405 clocks = <&cpg CPG_MOD <<
406 clock-names = "fck"; <<
407 power-domains = <&sysc <<
408 resets = <&cpg 911>; <<
409 status = "disabled"; <<
410 }; <<
411 <<
412 cmt2: timer@e6140000 { <<
413 compatible = "renesas, <<
414 "renesas, <<
415 reg = <0 0xe6140000 0 <<
416 interrupts = <GIC_SPI <<
417 <GIC_SPI <<
418 <GIC_SPI <<
419 <GIC_SPI <<
420 <GIC_SPI <<
421 <GIC_SPI <<
422 <GIC_SPI <<
423 <GIC_SPI <<
424 clocks = <&cpg CPG_MOD <<
425 clock-names = "fck"; <<
426 power-domains = <&sysc <<
427 resets = <&cpg 912>; <<
428 status = "disabled"; <<
429 }; <<
430 <<
431 cmt3: timer@e6148000 { <<
432 compatible = "renesas, <<
433 "renesas, <<
434 reg = <0 0xe6148000 0 <<
435 interrupts = <GIC_SPI <<
436 <GIC_SPI <<
437 <GIC_SPI <<
438 <GIC_SPI <<
439 <GIC_SPI <<
440 <GIC_SPI <<
441 <GIC_SPI <<
442 <GIC_SPI <<
443 clocks = <&cpg CPG_MOD <<
444 clock-names = "fck"; <<
445 power-domains = <&sysc <<
446 resets = <&cpg 913>; <<
447 status = "disabled"; <<
448 }; <<
449 <<
450 cpg: clock-controller@e6150000 62 cpg: clock-controller@e6150000 {
451 compatible = "renesas, 63 compatible = "renesas,r8a779f0-cpg-mssr";
452 reg = <0 0xe6150000 0 64 reg = <0 0xe6150000 0 0x4000>;
453 clocks = <&extal_clk>, 65 clocks = <&extal_clk>, <&extalr_clk>;
454 clock-names = "extal", 66 clock-names = "extal", "extalr";
455 #clock-cells = <2>; 67 #clock-cells = <2>;
456 #power-domain-cells = 68 #power-domain-cells = <0>;
457 #reset-cells = <1>; 69 #reset-cells = <1>;
458 }; 70 };
459 71
460 rst: reset-controller@e6160000 72 rst: reset-controller@e6160000 {
461 compatible = "renesas, 73 compatible = "renesas,r8a779f0-rst";
462 reg = <0 0xe6160000 0 74 reg = <0 0xe6160000 0 0x4000>;
463 }; 75 };
464 76
465 sysc: system-controller@e61800 77 sysc: system-controller@e6180000 {
466 compatible = "renesas, 78 compatible = "renesas,r8a779f0-sysc";
467 reg = <0 0xe6180000 0 79 reg = <0 0xe6180000 0 0x4000>;
468 #power-domain-cells = 80 #power-domain-cells = <1>;
469 }; 81 };
470 82
471 tsc: thermal@e6198000 { <<
472 compatible = "renesas, <<
473 /* The 4th sensor is i <<
474 reg = <0 0xe6198000 0 <<
475 <0 0xe61a0000 0 <<
476 <0 0xe61a8000 0 <<
477 clocks = <&cpg CPG_MOD <<
478 power-domains = <&sysc <<
479 resets = <&cpg 919>; <<
480 #thermal-sensor-cells <<
481 }; <<
482 <<
483 intc_ex: interrupt-controller@ <<
484 compatible = "renesas, <<
485 #interrupt-cells = <2> <<
486 interrupt-controller; <<
487 reg = <0 0xe61c0000 0 <<
488 interrupts = <GIC_SPI <<
489 <GIC_SPI <<
490 <GIC_SPI <<
491 <GIC_SPI <<
492 <GIC_SPI <<
493 <GIC_SPI <<
494 clocks = <&cpg CPG_COR <<
495 power-domains = <&sysc <<
496 }; <<
497 <<
498 tmu0: timer@e61e0000 { <<
499 compatible = "renesas, <<
500 reg = <0 0xe61e0000 0 <<
501 interrupts = <GIC_SPI <<
502 <GIC_SPI <<
503 <GIC_SPI <<
504 interrupt-names = "tun <<
505 clocks = <&cpg CPG_MOD <<
506 clock-names = "fck"; <<
507 power-domains = <&sysc <<
508 resets = <&cpg 713>; <<
509 status = "disabled"; <<
510 }; <<
511 <<
512 tmu1: timer@e6fc0000 { <<
513 compatible = "renesas, <<
514 reg = <0 0xe6fc0000 0 <<
515 interrupts = <GIC_SPI <<
516 <GIC_SPI <<
517 <GIC_SPI <<
518 <GIC_SPI <<
519 interrupt-names = "tun <<
520 clocks = <&cpg CPG_MOD <<
521 clock-names = "fck"; <<
522 power-domains = <&sysc <<
523 resets = <&cpg 714>; <<
524 status = "disabled"; <<
525 }; <<
526 <<
527 tmu2: timer@e6fd0000 { <<
528 compatible = "renesas, <<
529 reg = <0 0xe6fd0000 0 <<
530 interrupts = <GIC_SPI <<
531 <GIC_SPI <<
532 <GIC_SPI <<
533 <GIC_SPI <<
534 interrupt-names = "tun <<
535 clocks = <&cpg CPG_MOD <<
536 clock-names = "fck"; <<
537 power-domains = <&sysc <<
538 resets = <&cpg 715>; <<
539 status = "disabled"; <<
540 }; <<
541 <<
542 tmu3: timer@e6fe0000 { <<
543 compatible = "renesas, <<
544 reg = <0 0xe6fe0000 0 <<
545 interrupts = <GIC_SPI <<
546 <GIC_SPI <<
547 <GIC_SPI <<
548 <GIC_SPI <<
549 interrupt-names = "tun <<
550 clocks = <&cpg CPG_MOD <<
551 clock-names = "fck"; <<
552 power-domains = <&sysc <<
553 resets = <&cpg 716>; <<
554 status = "disabled"; <<
555 }; <<
556 <<
557 tmu4: timer@ffc00000 { <<
558 compatible = "renesas, <<
559 reg = <0 0xffc00000 0 <<
560 interrupts = <GIC_SPI <<
561 <GIC_SPI <<
562 <GIC_SPI <<
563 <GIC_SPI <<
564 interrupt-names = "tun <<
565 clocks = <&cpg CPG_MOD <<
566 clock-names = "fck"; <<
567 power-domains = <&sysc <<
568 resets = <&cpg 717>; <<
569 status = "disabled"; <<
570 }; <<
571 <<
572 eth_serdes: phy@e6444000 { <<
573 compatible = "renesas, <<
574 reg = <0 0xe6444000 0 <<
575 clocks = <&cpg CPG_MOD <<
576 power-domains = <&sysc <<
577 resets = <&cpg 1506>; <<
578 #phy-cells = <1>; <<
579 status = "disabled"; <<
580 }; <<
581 <<
582 i2c0: i2c@e6500000 { <<
583 compatible = "renesas, <<
584 "renesas, <<
585 reg = <0 0xe6500000 0 <<
586 interrupts = <GIC_SPI <<
587 clocks = <&cpg CPG_MOD <<
588 power-domains = <&sysc <<
589 resets = <&cpg 518>; <<
590 dmas = <&dmac0 0x91>, <<
591 <&dmac1 0x91>, <<
592 dma-names = "tx", "rx" <<
593 i2c-scl-internal-delay <<
594 #address-cells = <1>; <<
595 #size-cells = <0>; <<
596 status = "disabled"; <<
597 }; <<
598 <<
599 i2c1: i2c@e6508000 { <<
600 compatible = "renesas, <<
601 "renesas, <<
602 reg = <0 0xe6508000 0 <<
603 interrupts = <GIC_SPI <<
604 clocks = <&cpg CPG_MOD <<
605 power-domains = <&sysc <<
606 resets = <&cpg 519>; <<
607 dmas = <&dmac0 0x93>, <<
608 <&dmac1 0x93>, <<
609 dma-names = "tx", "rx" <<
610 i2c-scl-internal-delay <<
611 #address-cells = <1>; <<
612 #size-cells = <0>; <<
613 status = "disabled"; <<
614 }; <<
615 <<
616 i2c2: i2c@e6510000 { <<
617 compatible = "renesas, <<
618 "renesas, <<
619 reg = <0 0xe6510000 0 <<
620 interrupts = <0 240 IR <<
621 clocks = <&cpg CPG_MOD <<
622 power-domains = <&sysc <<
623 resets = <&cpg 520>; <<
624 dmas = <&dmac0 0x95>, <<
625 <&dmac1 0x95>, <<
626 dma-names = "tx", "rx" <<
627 i2c-scl-internal-delay <<
628 #address-cells = <1>; <<
629 #size-cells = <0>; <<
630 status = "disabled"; <<
631 }; <<
632 <<
633 i2c3: i2c@e66d0000 { <<
634 compatible = "renesas, <<
635 "renesas, <<
636 reg = <0 0xe66d0000 0 <<
637 interrupts = <GIC_SPI <<
638 clocks = <&cpg CPG_MOD <<
639 power-domains = <&sysc <<
640 resets = <&cpg 521>; <<
641 dmas = <&dmac0 0x97>, <<
642 <&dmac1 0x97>, <<
643 dma-names = "tx", "rx" <<
644 i2c-scl-internal-delay <<
645 #address-cells = <1>; <<
646 #size-cells = <0>; <<
647 status = "disabled"; <<
648 }; <<
649 <<
650 i2c4: i2c@e66d8000 { <<
651 compatible = "renesas, <<
652 "renesas, <<
653 reg = <0 0xe66d8000 0 <<
654 interrupts = <GIC_SPI <<
655 clocks = <&cpg CPG_MOD <<
656 power-domains = <&sysc <<
657 resets = <&cpg 522>; <<
658 dmas = <&dmac0 0x99>, <<
659 <&dmac1 0x99>, <<
660 dma-names = "tx", "rx" <<
661 i2c-scl-internal-delay <<
662 #address-cells = <1>; <<
663 #size-cells = <0>; <<
664 status = "disabled"; <<
665 }; <<
666 <<
667 i2c5: i2c@e66e0000 { <<
668 compatible = "renesas, <<
669 "renesas, <<
670 reg = <0 0xe66e0000 0 <<
671 interrupts = <GIC_SPI <<
672 clocks = <&cpg CPG_MOD <<
673 power-domains = <&sysc <<
674 resets = <&cpg 523>; <<
675 dmas = <&dmac0 0x9b>, <<
676 <&dmac1 0x9b>, <<
677 dma-names = "tx", "rx" <<
678 i2c-scl-internal-delay <<
679 #address-cells = <1>; <<
680 #size-cells = <0>; <<
681 status = "disabled"; <<
682 }; <<
683 <<
684 hscif0: serial@e6540000 { <<
685 compatible = "renesas, <<
686 "renesas, <<
687 reg = <0 0xe6540000 0 <<
688 interrupts = <GIC_SPI <<
689 clocks = <&cpg CPG_MOD <<
690 <&cpg CPG_COR <<
691 <&scif_clk>; <<
692 clock-names = "fck", " <<
693 dmas = <&dmac0 0x31>, <<
694 <&dmac1 0x31>, <<
695 dma-names = "tx", "rx" <<
696 power-domains = <&sysc <<
697 resets = <&cpg 514>; <<
698 status = "disabled"; <<
699 }; <<
700 <<
701 hscif1: serial@e6550000 { <<
702 compatible = "renesas, <<
703 "renesas, <<
704 reg = <0 0xe6550000 0 <<
705 interrupts = <GIC_SPI <<
706 clocks = <&cpg CPG_MOD <<
707 <&cpg CPG_COR <<
708 <&scif_clk>; <<
709 clock-names = "fck", " <<
710 dmas = <&dmac0 0x33>, <<
711 <&dmac1 0x33>, <<
712 dma-names = "tx", "rx" <<
713 power-domains = <&sysc <<
714 resets = <&cpg 515>; <<
715 status = "disabled"; <<
716 }; <<
717 <<
718 hscif2: serial@e6560000 { <<
719 compatible = "renesas, <<
720 "renesas, <<
721 reg = <0 0xe6560000 0 <<
722 interrupts = <GIC_SPI <<
723 clocks = <&cpg CPG_MOD <<
724 <&cpg CPG_COR <<
725 <&scif_clk>; <<
726 clock-names = "fck", " <<
727 dmas = <&dmac0 0x35>, <<
728 <&dmac1 0x35>, <<
729 dma-names = "tx", "rx" <<
730 power-domains = <&sysc <<
731 resets = <&cpg 516>; <<
732 status = "disabled"; <<
733 }; <<
734 <<
735 hscif3: serial@e66a0000 { <<
736 compatible = "renesas, <<
737 "renesas, <<
738 reg = <0 0xe66a0000 0 <<
739 interrupts = <GIC_SPI <<
740 clocks = <&cpg CPG_MOD <<
741 <&cpg CPG_COR <<
742 <&scif_clk>; <<
743 clock-names = "fck", " <<
744 dmas = <&dmac0 0x37>, <<
745 <&dmac1 0x37>, <<
746 dma-names = "tx", "rx" <<
747 power-domains = <&sysc <<
748 resets = <&cpg 517>; <<
749 status = "disabled"; <<
750 }; <<
751 <<
752 pciec0: pcie@e65d0000 { <<
753 compatible = "renesas, <<
754 "renesas, <<
755 reg = <0 0xe65d0000 0 <<
756 <0 0xe65d3000 0 <<
757 <0 0xe65d6200 0 <<
758 <0 0xfe000000 0 <<
759 reg-names = "dbi", "db <<
760 interrupts = <GIC_SPI <<
761 <GIC_SPI <<
762 <GIC_SPI <<
763 <GIC_SPI <<
764 interrupt-names = "msi <<
765 clocks = <&cpg CPG_MOD <<
766 clock-names = "core", <<
767 power-domains = <&sysc <<
768 resets = <&cpg 624>; <<
769 reset-names = "pwr"; <<
770 max-link-speed = <4>; <<
771 num-lanes = <2>; <<
772 #address-cells = <3>; <<
773 #size-cells = <2>; <<
774 bus-range = <0x00 0xff <<
775 device_type = "pci"; <<
776 ranges = <0x01000000 0 <<
777 <0x02000000 0 <<
778 dma-ranges = <0x420000 <<
779 #interrupt-cells = <1> <<
780 interrupt-map-mask = < <<
781 interrupt-map = <0 0 0 <<
782 <0 0 0 <<
783 <0 0 0 <<
784 <0 0 0 <<
785 snps,enable-cdm-check; <<
786 status = "disabled"; <<
787 }; <<
788 <<
789 pciec1: pcie@e65d8000 { <<
790 compatible = "renesas, <<
791 "renesas, <<
792 reg = <0 0xe65d8000 0 <<
793 <0 0xe65db000 0 <<
794 <0 0xe65de200 0 <<
795 <0 0xee900000 0 <<
796 reg-names = "dbi", "db <<
797 interrupts = <GIC_SPI <<
798 <GIC_SPI <<
799 <GIC_SPI <<
800 <GIC_SPI <<
801 interrupt-names = "msi <<
802 clocks = <&cpg CPG_MOD <<
803 clock-names = "core", <<
804 power-domains = <&sysc <<
805 resets = <&cpg 625>; <<
806 reset-names = "pwr"; <<
807 max-link-speed = <4>; <<
808 num-lanes = <2>; <<
809 #address-cells = <3>; <<
810 #size-cells = <2>; <<
811 bus-range = <0x00 0xff <<
812 device_type = "pci"; <<
813 ranges = <0x01000000 0 <<
814 <0x02000000 0 <<
815 dma-ranges = <0x420000 <<
816 #interrupt-cells = <1> <<
817 interrupt-map-mask = < <<
818 interrupt-map = <0 0 0 <<
819 <0 0 0 <<
820 <0 0 0 <<
821 <0 0 0 <<
822 snps,enable-cdm-check; <<
823 status = "disabled"; <<
824 }; <<
825 <<
826 pciec0_ep: pcie-ep@e65d0000 { <<
827 compatible = "renesas, <<
828 "renesas, <<
829 reg = <0 0xe65d0000 0 <<
830 <0 0xe65d3000 0 <<
831 <0 0xe65d6200 0 <<
832 <0 0xfe000000 0 <<
833 reg-names = "dbi", "db <<
834 interrupts = <GIC_SPI <<
835 <GIC_SPI <<
836 <GIC_SPI <<
837 interrupt-names = "dma <<
838 clocks = <&cpg CPG_MOD <<
839 clock-names = "core", <<
840 power-domains = <&sysc <<
841 resets = <&cpg 624>; <<
842 reset-names = "pwr"; <<
843 max-link-speed = <4>; <<
844 num-lanes = <2>; <<
845 max-functions = /bits/ <<
846 status = "disabled"; <<
847 }; <<
848 <<
849 pciec1_ep: pcie-ep@e65d8000 { <<
850 compatible = "renesas, <<
851 "renesas, <<
852 reg = <0 0xe65d8000 0 <<
853 <0 0xe65db000 0 <<
854 <0 0xe65de200 0 <<
855 <0 0xee900000 0 <<
856 reg-names = "dbi", "db <<
857 interrupts = <GIC_SPI <<
858 <GIC_SPI <<
859 <GIC_SPI <<
860 interrupt-names = "dma <<
861 clocks = <&cpg CPG_MOD <<
862 clock-names = "core", <<
863 power-domains = <&sysc <<
864 resets = <&cpg 625>; <<
865 reset-names = "pwr"; <<
866 max-link-speed = <4>; <<
867 num-lanes = <2>; <<
868 max-functions = /bits/ <<
869 status = "disabled"; <<
870 }; <<
871 <<
872 ufs: ufs@e6860000 { <<
873 compatible = "renesas, <<
874 reg = <0 0xe6860000 0 <<
875 interrupts = <GIC_SPI <<
876 clocks = <&cpg CPG_MOD <<
877 clock-names = "fck", " <<
878 freq-table-hz = <20000 <<
879 power-domains = <&sysc <<
880 resets = <&cpg 1514>; <<
881 status = "disabled"; <<
882 }; <<
883 <<
884 rswitch: ethernet@e6880000 { <<
885 compatible = "renesas, <<
886 reg = <0 0xe6880000 0 <<
887 reg-names = "base", "s <<
888 interrupts = <GIC_SPI <<
889 <GIC_SPI <<
890 <GIC_SPI <<
891 <GIC_SPI <<
892 <GIC_SPI <<
893 <GIC_SPI <<
894 <GIC_SPI <<
895 <GIC_SPI <<
896 <GIC_SPI <<
897 <GIC_SPI <<
898 <GIC_SPI <<
899 <GIC_SPI <<
900 <GIC_SPI <<
901 <GIC_SPI <<
902 <GIC_SPI <<
903 <GIC_SPI <<
904 <GIC_SPI <<
905 <GIC_SPI <<
906 <GIC_SPI <<
907 <GIC_SPI <<
908 <GIC_SPI <<
909 <GIC_SPI <<
910 <GIC_SPI <<
911 <GIC_SPI <<
912 <GIC_SPI <<
913 <GIC_SPI <<
914 <GIC_SPI <<
915 <GIC_SPI <<
916 <GIC_SPI <<
917 <GIC_SPI <<
918 <GIC_SPI <<
919 <GIC_SPI <<
920 <GIC_SPI <<
921 <GIC_SPI <<
922 <GIC_SPI <<
923 <GIC_SPI <<
924 <GIC_SPI <<
925 <GIC_SPI <<
926 <GIC_SPI <<
927 <GIC_SPI <<
928 <GIC_SPI <<
929 <GIC_SPI <<
930 <GIC_SPI <<
931 <GIC_SPI <<
932 <GIC_SPI <<
933 <GIC_SPI <<
934 <GIC_SPI <<
935 interrupt-names = "mfw <<
936 "com <<
937 "gwc <<
938 "eth <<
939 "gpt <<
940 "mfw <<
941 "com <<
942 "gwc <<
943 "eth <<
944 "rma <<
945 "rma <<
946 "gwc <<
947 "gwc <<
948 "gwc <<
949 "gwc <<
950 "gwc <<
951 "gwc <<
952 "gwc <<
953 "gwc <<
954 "gwc <<
955 "gwc <<
956 "rma <<
957 "rma <<
958 "rma <<
959 "rma <<
960 clocks = <&cpg CPG_MOD <<
961 power-domains = <&sysc <<
962 resets = <&cpg 1505>; <<
963 status = "disabled"; <<
964 <<
965 ethernet-ports { <<
966 #address-cells <<
967 #size-cells = <<
968 <<
969 port@0 { <<
970 reg = <<
971 phys = <<
972 }; <<
973 port@1 { <<
974 reg = <<
975 phys = <<
976 }; <<
977 port@2 { <<
978 reg = <<
979 phys = <<
980 }; <<
981 }; <<
982 }; <<
983 <<
984 scif0: serial@e6e60000 { <<
985 compatible = "renesas, <<
986 "renesas, <<
987 reg = <0 0xe6e60000 0 <<
988 interrupts = <GIC_SPI <<
989 clocks = <&cpg CPG_MOD <<
990 <&cpg CPG_COR <<
991 <&scif_clk>; <<
992 clock-names = "fck", " <<
993 dmas = <&dmac0 0x51>, <<
994 <&dmac1 0x51>, <<
995 dma-names = "tx", "rx" <<
996 power-domains = <&sysc <<
997 resets = <&cpg 702>; <<
998 status = "disabled"; <<
999 }; <<
1000 <<
1001 scif1: serial@e6e68000 { <<
1002 compatible = "renesas <<
1003 "renesas <<
1004 reg = <0 0xe6e68000 0 <<
1005 interrupts = <GIC_SPI <<
1006 clocks = <&cpg CPG_MO <<
1007 <&cpg CPG_CO <<
1008 <&scif_clk>; <<
1009 clock-names = "fck", <<
1010 dmas = <&dmac0 0x53>, <<
1011 <&dmac1 0x53>, <<
1012 dma-names = "tx", "rx <<
1013 power-domains = <&sys <<
1014 resets = <&cpg 703>; <<
1015 status = "disabled"; <<
1016 }; <<
1017 <<
1018 scif3: serial@e6c50000 { 83 scif3: serial@e6c50000 {
1019 compatible = "renesas 84 compatible = "renesas,scif-r8a779f0",
1020 "renesas 85 "renesas,rcar-gen4-scif", "renesas,scif";
1021 reg = <0 0xe6c50000 0 86 reg = <0 0xe6c50000 0 64>;
1022 interrupts = <GIC_SPI 87 interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>;
1023 clocks = <&cpg CPG_MO 88 clocks = <&cpg CPG_MOD 704>,
1024 <&cpg CPG_CO !! 89 <&cpg CPG_CORE R8A779F0_CLK_S0D3_PER>,
1025 <&scif_clk>; 90 <&scif_clk>;
1026 clock-names = "fck", 91 clock-names = "fck", "brg_int", "scif_clk";
1027 dmas = <&dmac0 0x57>, <<
1028 <&dmac1 0x57>, <<
1029 dma-names = "tx", "rx <<
1030 power-domains = <&sys 92 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
1031 resets = <&cpg 704>; 93 resets = <&cpg 704>;
1032 status = "disabled"; 94 status = "disabled";
1033 }; 95 };
1034 96
1035 scif4: serial@e6c40000 { <<
1036 compatible = "renesas <<
1037 "renesas <<
1038 reg = <0 0xe6c40000 0 <<
1039 interrupts = <GIC_SPI <<
1040 clocks = <&cpg CPG_MO <<
1041 <&cpg CPG_CO <<
1042 <&scif_clk>; <<
1043 clock-names = "fck", <<
1044 dmas = <&dmac0 0x59>, <<
1045 <&dmac1 0x59>, <<
1046 dma-names = "tx", "rx <<
1047 power-domains = <&sys <<
1048 resets = <&cpg 705>; <<
1049 status = "disabled"; <<
1050 }; <<
1051 <<
1052 msiof0: spi@e6e90000 { <<
1053 compatible = "renesas <<
1054 "renesas <<
1055 reg = <0 0xe6e90000 0 <<
1056 interrupts = <GIC_SPI <<
1057 clocks = <&cpg CPG_MO <<
1058 dmas = <&dmac0 0x41>, <<
1059 <&dmac1 0x41>, <<
1060 dma-names = "tx", "rx <<
1061 power-domains = <&sys <<
1062 resets = <&cpg 618>; <<
1063 #address-cells = <1>; <<
1064 #size-cells = <0>; <<
1065 status = "disabled"; <<
1066 }; <<
1067 <<
1068 msiof1: spi@e6ea0000 { <<
1069 compatible = "renesas <<
1070 "renesas <<
1071 reg = <0 0xe6ea0000 0 <<
1072 interrupts = <GIC_SPI <<
1073 clocks = <&cpg CPG_MO <<
1074 dmas = <&dmac0 0x43>, <<
1075 <&dmac1 0x43>, <<
1076 dma-names = "tx", "rx <<
1077 power-domains = <&sys <<
1078 resets = <&cpg 619>; <<
1079 #address-cells = <1>; <<
1080 #size-cells = <0>; <<
1081 status = "disabled"; <<
1082 }; <<
1083 <<
1084 msiof2: spi@e6c00000 { <<
1085 compatible = "renesas <<
1086 "renesas <<
1087 reg = <0 0xe6c00000 0 <<
1088 interrupts = <GIC_SPI <<
1089 clocks = <&cpg CPG_MO <<
1090 dmas = <&dmac0 0x45>, <<
1091 <&dmac1 0x45>, <<
1092 dma-names = "tx", "rx <<
1093 power-domains = <&sys <<
1094 resets = <&cpg 620>; <<
1095 #address-cells = <1>; <<
1096 #size-cells = <0>; <<
1097 status = "disabled"; <<
1098 }; <<
1099 <<
1100 msiof3: spi@e6c10000 { <<
1101 compatible = "renesas <<
1102 "renesas <<
1103 reg = <0 0xe6c10000 0 <<
1104 interrupts = <GIC_SPI <<
1105 clocks = <&cpg CPG_MO <<
1106 dmas = <&dmac0 0x47>, <<
1107 <&dmac1 0x47>, <<
1108 dma-names = "tx", "rx <<
1109 power-domains = <&sys <<
1110 resets = <&cpg 621>; <<
1111 #address-cells = <1>; <<
1112 #size-cells = <0>; <<
1113 status = "disabled"; <<
1114 }; <<
1115 <<
1116 dmac0: dma-controller@e735000 <<
1117 compatible = "renesas <<
1118 "renesas <<
1119 reg = <0 0xe7350000 0 <<
1120 <0 0xe7300000 0 <<
1121 interrupts = <GIC_SPI <<
1122 <GIC_SPI <<
1123 <GIC_SPI <<
1124 <GIC_SPI <<
1125 <GIC_SPI <<
1126 <GIC_SPI <<
1127 <GIC_SPI <<
1128 <GIC_SPI <<
1129 <GIC_SPI <<
1130 <GIC_SPI <<
1131 <GIC_SPI <<
1132 <GIC_SPI <<
1133 <GIC_SPI <<
1134 <GIC_SPI <<
1135 <GIC_SPI <<
1136 <GIC_SPI <<
1137 <GIC_SPI <<
1138 interrupt-names = "er <<
1139 "ch <<
1140 "ch <<
1141 "ch <<
1142 "ch <<
1143 clocks = <&cpg CPG_MO <<
1144 clock-names = "fck"; <<
1145 power-domains = <&sys <<
1146 resets = <&cpg 709>; <<
1147 #dma-cells = <1>; <<
1148 dma-channels = <16>; <<
1149 iommus = <&ipmmu_ds0 <<
1150 <&ipmmu_ds0 <<
1151 <&ipmmu_ds0 <<
1152 <&ipmmu_ds0 <<
1153 <&ipmmu_ds0 <<
1154 <&ipmmu_ds0 <<
1155 <&ipmmu_ds0 <<
1156 <&ipmmu_ds0 <<
1157 }; <<
1158 <<
1159 dmac1: dma-controller@e735100 <<
1160 compatible = "renesas <<
1161 "renesas <<
1162 reg = <0 0xe7351000 0 <<
1163 <0 0xe7310000 0 <<
1164 interrupts = <GIC_SPI <<
1165 <GIC_SPI <<
1166 <GIC_SPI <<
1167 <GIC_SPI <<
1168 <GIC_SPI <<
1169 <GIC_SPI <<
1170 <GIC_SPI <<
1171 <GIC_SPI <<
1172 <GIC_SPI <<
1173 <GIC_SPI <<
1174 <GIC_SPI <<
1175 <GIC_SPI <<
1176 <GIC_SPI <<
1177 <GIC_SPI <<
1178 <GIC_SPI <<
1179 <GIC_SPI <<
1180 <GIC_SPI <<
1181 interrupt-names = "er <<
1182 "ch <<
1183 "ch <<
1184 "ch <<
1185 "ch <<
1186 clocks = <&cpg CPG_MO <<
1187 clock-names = "fck"; <<
1188 power-domains = <&sys <<
1189 resets = <&cpg 710>; <<
1190 #dma-cells = <1>; <<
1191 dma-channels = <16>; <<
1192 iommus = <&ipmmu_ds0 <<
1193 <&ipmmu_ds0 <<
1194 <&ipmmu_ds0 <<
1195 <&ipmmu_ds0 <<
1196 <&ipmmu_ds0 <<
1197 <&ipmmu_ds0 <<
1198 <&ipmmu_ds0 <<
1199 <&ipmmu_ds0 <<
1200 }; <<
1201 <<
1202 mmc0: mmc@ee140000 { <<
1203 compatible = "renesas <<
1204 "renesas <<
1205 reg = <0 0xee140000 0 <<
1206 interrupts = <GIC_SPI <<
1207 clocks = <&cpg CPG_MO <<
1208 clock-names = "core", <<
1209 power-domains = <&sys <<
1210 resets = <&cpg 706>; <<
1211 max-frequency = <2000 <<
1212 iommus = <&ipmmu_ds0 <<
1213 status = "disabled"; <<
1214 }; <<
1215 <<
1216 ipmmu_rt0: iommu@ee480000 { <<
1217 compatible = "renesas <<
1218 "renesas <<
1219 reg = <0 0xee480000 0 <<
1220 renesas,ipmmu-main = <<
1221 power-domains = <&sys <<
1222 #iommu-cells = <1>; <<
1223 }; <<
1224 <<
1225 ipmmu_rt1: iommu@ee4c0000 { <<
1226 compatible = "renesas <<
1227 "renesas <<
1228 reg = <0 0xee4c0000 0 <<
1229 renesas,ipmmu-main = <<
1230 power-domains = <&sys <<
1231 #iommu-cells = <1>; <<
1232 }; <<
1233 <<
1234 ipmmu_ds0: iommu@eed00000 { <<
1235 compatible = "renesas <<
1236 "renesas <<
1237 reg = <0 0xeed00000 0 <<
1238 renesas,ipmmu-main = <<
1239 power-domains = <&sys <<
1240 #iommu-cells = <1>; <<
1241 }; <<
1242 <<
1243 ipmmu_hc: iommu@eed40000 { <<
1244 compatible = "renesas <<
1245 "renesas <<
1246 reg = <0 0xeed40000 0 <<
1247 renesas,ipmmu-main = <<
1248 power-domains = <&sys <<
1249 #iommu-cells = <1>; <<
1250 }; <<
1251 <<
1252 ipmmu_mm: iommu@eefc0000 { <<
1253 compatible = "renesas <<
1254 "renesas <<
1255 reg = <0 0xeefc0000 0 <<
1256 interrupts = <GIC_SPI <<
1257 <GIC_SPI <<
1258 power-domains = <&sys <<
1259 #iommu-cells = <1>; <<
1260 }; <<
1261 <<
1262 gic: interrupt-controller@f10 97 gic: interrupt-controller@f1000000 {
1263 compatible = "arm,gic 98 compatible = "arm,gic-v3";
1264 #interrupt-cells = <3 99 #interrupt-cells = <3>;
1265 #address-cells = <0>; 100 #address-cells = <0>;
1266 interrupt-controller; 101 interrupt-controller;
1267 reg = <0x0 0xf1000000 102 reg = <0x0 0xf1000000 0 0x20000>,
1268 <0x0 0xf1060000 103 <0x0 0xf1060000 0 0x110000>;
1269 interrupts = <GIC_PPI !! 104 interrupts = <GIC_PPI 9
>> 105 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
1270 }; 106 };
1271 107
1272 prr: chipid@fff00044 { 108 prr: chipid@fff00044 {
1273 compatible = "renesas 109 compatible = "renesas,prr";
1274 reg = <0 0xfff00044 0 110 reg = <0 0xfff00044 0 4>;
1275 }; 111 };
1276 }; 112 };
1277 113
1278 thermal-zones { <<
1279 sensor_thermal_rtcore: sensor <<
1280 polling-delay-passive <<
1281 polling-delay = <1000 <<
1282 thermal-sensors = <&t <<
1283 <<
1284 trips { <<
1285 sensor1_crit: <<
1286 tempe <<
1287 hyste <<
1288 type <<
1289 }; <<
1290 }; <<
1291 }; <<
1292 <<
1293 sensor_thermal_apcore0: senso <<
1294 polling-delay-passive <<
1295 polling-delay = <1000 <<
1296 thermal-sensors = <&t <<
1297 <<
1298 trips { <<
1299 sensor2_crit: <<
1300 tempe <<
1301 hyste <<
1302 type <<
1303 }; <<
1304 }; <<
1305 }; <<
1306 <<
1307 sensor_thermal_apcore4: senso <<
1308 polling-delay-passive <<
1309 polling-delay = <1000 <<
1310 thermal-sensors = <&t <<
1311 <<
1312 trips { <<
1313 sensor3_crit: <<
1314 tempe <<
1315 hyste <<
1316 type <<
1317 }; <<
1318 }; <<
1319 }; <<
1320 }; <<
1321 <<
1322 timer { 114 timer {
1323 compatible = "arm,armv8-timer 115 compatible = "arm,armv8-timer";
1324 interrupts-extended = <&gic G !! 116 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
1325 <&gic G !! 117 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
1326 <&gic G !! 118 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
1327 <&gic G !! 119 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
1328 <&gic G <<
1329 interrupt-names = "sec-phys", <<
1330 "hyp-virt"; <<
1331 }; <<
1332 <<
1333 ufs30_clk: ufs30-clk { <<
1334 compatible = "fixed-clock"; <<
1335 #clock-cells = <0>; <<
1336 /* This value must be overrid <<
1337 clock-frequency = <0>; <<
1338 }; 120 };
1339 }; 121 };
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