1 // SPDX-License-Identifier: (GPL-2.0 OR MIT) !! 1 // SPDX-License-Identifier: (GPL-2.0 or MIT)
2 /* 2 /*
3 * Device Tree Source for the R-Car S4-8 (R8A7 3 * Device Tree Source for the R-Car S4-8 (R8A779F0) SoC
4 * 4 *
5 * Copyright (C) 2021 Renesas Electronics Corp 5 * Copyright (C) 2021 Renesas Electronics Corp.
6 */ 6 */
7 7
8 #include <dt-bindings/clock/r8a779f0-cpg-mssr. 8 #include <dt-bindings/clock/r8a779f0-cpg-mssr.h>
9 #include <dt-bindings/interrupt-controller/arm 9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/power/r8a779f0-sysc.h> 10 #include <dt-bindings/power/r8a779f0-sysc.h>
11 11
12 / { 12 / {
13 compatible = "renesas,r8a779f0"; 13 compatible = "renesas,r8a779f0";
14 #address-cells = <2>; 14 #address-cells = <2>;
15 #size-cells = <2>; 15 #size-cells = <2>;
16 16
17 cluster01_opp: opp-table-0 { <<
18 compatible = "operating-points <<
19 opp-shared; <<
20 <<
21 opp-500000000 { <<
22 opp-hz = /bits/ 64 <50 <<
23 opp-microvolt = <88000 <<
24 clock-latency-ns = <50 <<
25 }; <<
26 opp-800000000 { <<
27 opp-hz = /bits/ 64 <80 <<
28 opp-microvolt = <88000 <<
29 clock-latency-ns = <50 <<
30 }; <<
31 opp-1000000000 { <<
32 opp-hz = /bits/ 64 <10 <<
33 opp-microvolt = <88000 <<
34 clock-latency-ns = <50 <<
35 }; <<
36 opp-1200000000 { <<
37 opp-hz = /bits/ 64 <12 <<
38 opp-microvolt = <88000 <<
39 clock-latency-ns = <50 <<
40 opp-suspend; <<
41 }; <<
42 }; <<
43 <<
44 cluster23_opp: opp-table-1 { <<
45 compatible = "operating-points <<
46 opp-shared; <<
47 <<
48 opp-500000000 { <<
49 opp-hz = /bits/ 64 <50 <<
50 opp-microvolt = <88000 <<
51 clock-latency-ns = <50 <<
52 }; <<
53 opp-800000000 { <<
54 opp-hz = /bits/ 64 <80 <<
55 opp-microvolt = <88000 <<
56 clock-latency-ns = <50 <<
57 }; <<
58 opp-1000000000 { <<
59 opp-hz = /bits/ 64 <10 <<
60 opp-microvolt = <88000 <<
61 clock-latency-ns = <50 <<
62 }; <<
63 opp-1200000000 { <<
64 opp-hz = /bits/ 64 <12 <<
65 opp-microvolt = <88000 <<
66 clock-latency-ns = <50 <<
67 opp-suspend; <<
68 }; <<
69 }; <<
70 <<
71 cpus { 17 cpus {
72 #address-cells = <1>; 18 #address-cells = <1>;
73 #size-cells = <0>; 19 #size-cells = <0>;
74 20
75 cpu-map { 21 cpu-map {
76 cluster0 { 22 cluster0 {
77 core0 { 23 core0 {
78 cpu = 24 cpu = <&a55_0>;
79 }; 25 };
80 core1 { 26 core1 {
81 cpu = 27 cpu = <&a55_1>;
82 }; 28 };
83 }; 29 };
84 30
85 cluster1 { 31 cluster1 {
86 core0 { 32 core0 {
87 cpu = 33 cpu = <&a55_2>;
88 }; 34 };
89 core1 { 35 core1 {
90 cpu = 36 cpu = <&a55_3>;
91 }; 37 };
92 }; 38 };
93 39
94 cluster2 { 40 cluster2 {
95 core0 { 41 core0 {
96 cpu = 42 cpu = <&a55_4>;
97 }; 43 };
98 core1 { 44 core1 {
99 cpu = 45 cpu = <&a55_5>;
100 }; 46 };
101 }; 47 };
102 48
103 cluster3 { 49 cluster3 {
104 core0 { 50 core0 {
105 cpu = 51 cpu = <&a55_6>;
106 }; 52 };
107 core1 { 53 core1 {
108 cpu = 54 cpu = <&a55_7>;
109 }; 55 };
110 }; 56 };
111 }; 57 };
112 58
113 a55_0: cpu@0 { 59 a55_0: cpu@0 {
114 compatible = "arm,cort 60 compatible = "arm,cortex-a55";
115 reg = <0>; 61 reg = <0>;
116 device_type = "cpu"; 62 device_type = "cpu";
117 power-domains = <&sysc 63 power-domains = <&sysc R8A779F0_PD_A1E0D0C0>;
118 next-level-cache = <&L 64 next-level-cache = <&L3_CA55_0>;
119 enable-method = "psci" 65 enable-method = "psci";
120 cpu-idle-states = <&CP 66 cpu-idle-states = <&CPU_SLEEP_0>;
121 clocks = <&cpg CPG_COR 67 clocks = <&cpg CPG_CORE R8A779F0_CLK_Z0>;
122 operating-points-v2 = <<
123 }; 68 };
124 69
125 a55_1: cpu@100 { 70 a55_1: cpu@100 {
126 compatible = "arm,cort 71 compatible = "arm,cortex-a55";
127 reg = <0x100>; 72 reg = <0x100>;
128 device_type = "cpu"; 73 device_type = "cpu";
129 power-domains = <&sysc 74 power-domains = <&sysc R8A779F0_PD_A1E0D0C1>;
130 next-level-cache = <&L 75 next-level-cache = <&L3_CA55_0>;
131 enable-method = "psci" 76 enable-method = "psci";
132 cpu-idle-states = <&CP 77 cpu-idle-states = <&CPU_SLEEP_0>;
133 clocks = <&cpg CPG_COR 78 clocks = <&cpg CPG_CORE R8A779F0_CLK_Z0>;
134 operating-points-v2 = <<
135 }; 79 };
136 80
137 a55_2: cpu@10000 { 81 a55_2: cpu@10000 {
138 compatible = "arm,cort 82 compatible = "arm,cortex-a55";
139 reg = <0x10000>; 83 reg = <0x10000>;
140 device_type = "cpu"; 84 device_type = "cpu";
141 power-domains = <&sysc 85 power-domains = <&sysc R8A779F0_PD_A1E0D1C0>;
142 next-level-cache = <&L 86 next-level-cache = <&L3_CA55_1>;
143 enable-method = "psci" 87 enable-method = "psci";
144 cpu-idle-states = <&CP 88 cpu-idle-states = <&CPU_SLEEP_0>;
145 clocks = <&cpg CPG_COR 89 clocks = <&cpg CPG_CORE R8A779F0_CLK_Z0>;
146 operating-points-v2 = <<
147 }; 90 };
148 91
149 a55_3: cpu@10100 { 92 a55_3: cpu@10100 {
150 compatible = "arm,cort 93 compatible = "arm,cortex-a55";
151 reg = <0x10100>; 94 reg = <0x10100>;
152 device_type = "cpu"; 95 device_type = "cpu";
153 power-domains = <&sysc 96 power-domains = <&sysc R8A779F0_PD_A1E0D1C1>;
154 next-level-cache = <&L 97 next-level-cache = <&L3_CA55_1>;
155 enable-method = "psci" 98 enable-method = "psci";
156 cpu-idle-states = <&CP 99 cpu-idle-states = <&CPU_SLEEP_0>;
157 clocks = <&cpg CPG_COR 100 clocks = <&cpg CPG_CORE R8A779F0_CLK_Z0>;
158 operating-points-v2 = <<
159 }; 101 };
160 102
161 a55_4: cpu@20000 { 103 a55_4: cpu@20000 {
162 compatible = "arm,cort 104 compatible = "arm,cortex-a55";
163 reg = <0x20000>; 105 reg = <0x20000>;
164 device_type = "cpu"; 106 device_type = "cpu";
165 power-domains = <&sysc 107 power-domains = <&sysc R8A779F0_PD_A1E1D0C0>;
166 next-level-cache = <&L 108 next-level-cache = <&L3_CA55_2>;
167 enable-method = "psci" 109 enable-method = "psci";
168 cpu-idle-states = <&CP 110 cpu-idle-states = <&CPU_SLEEP_0>;
169 clocks = <&cpg CPG_COR 111 clocks = <&cpg CPG_CORE R8A779F0_CLK_Z1>;
170 operating-points-v2 = <<
171 }; 112 };
172 113
173 a55_5: cpu@20100 { 114 a55_5: cpu@20100 {
174 compatible = "arm,cort 115 compatible = "arm,cortex-a55";
175 reg = <0x20100>; 116 reg = <0x20100>;
176 device_type = "cpu"; 117 device_type = "cpu";
177 power-domains = <&sysc 118 power-domains = <&sysc R8A779F0_PD_A1E1D0C1>;
178 next-level-cache = <&L 119 next-level-cache = <&L3_CA55_2>;
179 enable-method = "psci" 120 enable-method = "psci";
180 cpu-idle-states = <&CP 121 cpu-idle-states = <&CPU_SLEEP_0>;
181 clocks = <&cpg CPG_COR 122 clocks = <&cpg CPG_CORE R8A779F0_CLK_Z1>;
182 operating-points-v2 = <<
183 }; 123 };
184 124
185 a55_6: cpu@30000 { 125 a55_6: cpu@30000 {
186 compatible = "arm,cort 126 compatible = "arm,cortex-a55";
187 reg = <0x30000>; 127 reg = <0x30000>;
188 device_type = "cpu"; 128 device_type = "cpu";
189 power-domains = <&sysc 129 power-domains = <&sysc R8A779F0_PD_A1E1D1C0>;
190 next-level-cache = <&L 130 next-level-cache = <&L3_CA55_3>;
191 enable-method = "psci" 131 enable-method = "psci";
192 cpu-idle-states = <&CP 132 cpu-idle-states = <&CPU_SLEEP_0>;
193 clocks = <&cpg CPG_COR 133 clocks = <&cpg CPG_CORE R8A779F0_CLK_Z1>;
194 operating-points-v2 = <<
195 }; 134 };
196 135
197 a55_7: cpu@30100 { 136 a55_7: cpu@30100 {
198 compatible = "arm,cort 137 compatible = "arm,cortex-a55";
199 reg = <0x30100>; 138 reg = <0x30100>;
200 device_type = "cpu"; 139 device_type = "cpu";
201 power-domains = <&sysc 140 power-domains = <&sysc R8A779F0_PD_A1E1D1C1>;
202 next-level-cache = <&L 141 next-level-cache = <&L3_CA55_3>;
203 enable-method = "psci" 142 enable-method = "psci";
204 cpu-idle-states = <&CP 143 cpu-idle-states = <&CPU_SLEEP_0>;
205 clocks = <&cpg CPG_COR 144 clocks = <&cpg CPG_CORE R8A779F0_CLK_Z1>;
206 operating-points-v2 = <<
207 }; 145 };
208 146
209 L3_CA55_0: cache-controller-0 147 L3_CA55_0: cache-controller-0 {
210 compatible = "cache"; 148 compatible = "cache";
211 power-domains = <&sysc 149 power-domains = <&sysc R8A779F0_PD_A2E0D0>;
212 cache-unified; 150 cache-unified;
213 cache-level = <3>; 151 cache-level = <3>;
214 }; 152 };
215 153
216 L3_CA55_1: cache-controller-1 154 L3_CA55_1: cache-controller-1 {
217 compatible = "cache"; 155 compatible = "cache";
218 power-domains = <&sysc 156 power-domains = <&sysc R8A779F0_PD_A2E0D1>;
219 cache-unified; 157 cache-unified;
220 cache-level = <3>; 158 cache-level = <3>;
221 }; 159 };
222 160
223 L3_CA55_2: cache-controller-2 161 L3_CA55_2: cache-controller-2 {
224 compatible = "cache"; 162 compatible = "cache";
225 power-domains = <&sysc 163 power-domains = <&sysc R8A779F0_PD_A2E1D0>;
226 cache-unified; 164 cache-unified;
227 cache-level = <3>; 165 cache-level = <3>;
228 }; 166 };
229 167
230 L3_CA55_3: cache-controller-3 168 L3_CA55_3: cache-controller-3 {
231 compatible = "cache"; 169 compatible = "cache";
232 power-domains = <&sysc 170 power-domains = <&sysc R8A779F0_PD_A2E1D1>;
233 cache-unified; 171 cache-unified;
234 cache-level = <3>; 172 cache-level = <3>;
235 }; 173 };
236 174
237 idle-states { 175 idle-states {
238 entry-method = "psci"; 176 entry-method = "psci";
239 177
240 CPU_SLEEP_0: cpu-sleep 178 CPU_SLEEP_0: cpu-sleep-0 {
241 compatible = " 179 compatible = "arm,idle-state";
242 arm,psci-suspe 180 arm,psci-suspend-param = <0x0010000>;
243 local-timer-st 181 local-timer-stop;
244 entry-latency- 182 entry-latency-us = <400>;
245 exit-latency-u 183 exit-latency-us = <500>;
246 min-residency- 184 min-residency-us = <4000>;
247 }; 185 };
248 }; 186 };
249 }; 187 };
250 188
251 extal_clk: extal { 189 extal_clk: extal {
252 compatible = "fixed-clock"; 190 compatible = "fixed-clock";
253 #clock-cells = <0>; 191 #clock-cells = <0>;
254 /* This value must be overridd 192 /* This value must be overridden by the board */
255 clock-frequency = <0>; 193 clock-frequency = <0>;
256 }; 194 };
257 195
258 extalr_clk: extalr { 196 extalr_clk: extalr {
259 compatible = "fixed-clock"; 197 compatible = "fixed-clock";
260 #clock-cells = <0>; 198 #clock-cells = <0>;
261 /* This value must be overridd 199 /* This value must be overridden by the board */
262 clock-frequency = <0>; 200 clock-frequency = <0>;
263 }; 201 };
264 202
265 pcie0_clkref: pcie0-clkref { <<
266 compatible = "fixed-clock"; <<
267 #clock-cells = <0>; <<
268 /* This value must be overridd <<
269 clock-frequency = <0>; <<
270 }; <<
271 <<
272 pcie1_clkref: pcie1-clkref { <<
273 compatible = "fixed-clock"; <<
274 #clock-cells = <0>; <<
275 /* This value must be overridd <<
276 clock-frequency = <0>; <<
277 }; <<
278 <<
279 pmu_a55 { 203 pmu_a55 {
280 compatible = "arm,cortex-a55-p 204 compatible = "arm,cortex-a55-pmu";
281 interrupts-extended = <&gic GI 205 interrupts-extended = <&gic GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
282 }; 206 };
283 207
284 psci { 208 psci {
285 compatible = "arm,psci-1.0", " 209 compatible = "arm,psci-1.0", "arm,psci-0.2";
286 method = "smc"; 210 method = "smc";
287 }; 211 };
288 212
289 /* External SCIF clock - to be overrid 213 /* External SCIF clock - to be overridden by boards that provide it */
290 scif_clk: scif { 214 scif_clk: scif {
291 compatible = "fixed-clock"; 215 compatible = "fixed-clock";
292 #clock-cells = <0>; 216 #clock-cells = <0>;
293 clock-frequency = <0>; 217 clock-frequency = <0>;
294 }; 218 };
295 219
296 soc: soc { 220 soc: soc {
297 compatible = "simple-bus"; 221 compatible = "simple-bus";
298 interrupt-parent = <&gic>; 222 interrupt-parent = <&gic>;
299 #address-cells = <2>; 223 #address-cells = <2>;
300 #size-cells = <2>; 224 #size-cells = <2>;
301 ranges; 225 ranges;
302 226
303 rwdt: watchdog@e6020000 { 227 rwdt: watchdog@e6020000 {
304 compatible = "renesas, 228 compatible = "renesas,r8a779f0-wdt",
305 "renesas, 229 "renesas,rcar-gen4-wdt";
306 reg = <0 0xe6020000 0 230 reg = <0 0xe6020000 0 0x0c>;
307 interrupts = <GIC_SPI 231 interrupts = <GIC_SPI 515 IRQ_TYPE_LEVEL_HIGH>;
308 clocks = <&cpg CPG_MOD 232 clocks = <&cpg CPG_MOD 907>;
309 power-domains = <&sysc 233 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
310 resets = <&cpg 907>; 234 resets = <&cpg 907>;
311 status = "disabled"; 235 status = "disabled";
312 }; 236 };
313 237
314 pfc: pinctrl@e6050000 { 238 pfc: pinctrl@e6050000 {
315 compatible = "renesas, 239 compatible = "renesas,pfc-r8a779f0";
316 reg = <0 0xe6050000 0 240 reg = <0 0xe6050000 0 0x16c>, <0 0xe6050800 0 0x16c>,
317 <0 0xe6051000 0 241 <0 0xe6051000 0 0x16c>, <0 0xe6051800 0 0x16c>;
318 }; 242 };
319 243
320 gpio0: gpio@e6050180 { 244 gpio0: gpio@e6050180 {
321 compatible = "renesas, 245 compatible = "renesas,gpio-r8a779f0",
322 "renesas, 246 "renesas,rcar-gen4-gpio";
323 reg = <0 0xe6050180 0 247 reg = <0 0xe6050180 0 0x54>;
324 interrupts = <GIC_SPI 248 interrupts = <GIC_SPI 822 IRQ_TYPE_LEVEL_HIGH>;
325 clocks = <&cpg CPG_MOD 249 clocks = <&cpg CPG_MOD 915>;
326 power-domains = <&sysc 250 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
327 resets = <&cpg 915>; 251 resets = <&cpg 915>;
328 gpio-controller; 252 gpio-controller;
329 #gpio-cells = <2>; 253 #gpio-cells = <2>;
330 gpio-ranges = <&pfc 0 254 gpio-ranges = <&pfc 0 0 21>;
331 interrupt-controller; 255 interrupt-controller;
332 #interrupt-cells = <2> 256 #interrupt-cells = <2>;
333 }; 257 };
334 258
335 gpio1: gpio@e6050980 { 259 gpio1: gpio@e6050980 {
336 compatible = "renesas, 260 compatible = "renesas,gpio-r8a779f0",
337 "renesas, 261 "renesas,rcar-gen4-gpio";
338 reg = <0 0xe6050980 0 262 reg = <0 0xe6050980 0 0x54>;
339 interrupts = <GIC_SPI 263 interrupts = <GIC_SPI 823 IRQ_TYPE_LEVEL_HIGH>;
340 clocks = <&cpg CPG_MOD 264 clocks = <&cpg CPG_MOD 915>;
341 power-domains = <&sysc 265 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
342 resets = <&cpg 915>; 266 resets = <&cpg 915>;
343 gpio-controller; 267 gpio-controller;
344 #gpio-cells = <2>; 268 #gpio-cells = <2>;
345 gpio-ranges = <&pfc 0 269 gpio-ranges = <&pfc 0 32 25>;
346 interrupt-controller; 270 interrupt-controller;
347 #interrupt-cells = <2> 271 #interrupt-cells = <2>;
348 }; 272 };
349 273
350 gpio2: gpio@e6051180 { 274 gpio2: gpio@e6051180 {
351 compatible = "renesas, 275 compatible = "renesas,gpio-r8a779f0",
352 "renesas, 276 "renesas,rcar-gen4-gpio";
353 reg = <0 0xe6051180 0 277 reg = <0 0xe6051180 0 0x54>;
354 interrupts = <GIC_SPI 278 interrupts = <GIC_SPI 824 IRQ_TYPE_LEVEL_HIGH>;
355 clocks = <&cpg CPG_MOD 279 clocks = <&cpg CPG_MOD 915>;
356 power-domains = <&sysc 280 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
357 resets = <&cpg 915>; 281 resets = <&cpg 915>;
358 gpio-controller; 282 gpio-controller;
359 #gpio-cells = <2>; 283 #gpio-cells = <2>;
360 gpio-ranges = <&pfc 0 284 gpio-ranges = <&pfc 0 64 17>;
361 interrupt-controller; 285 interrupt-controller;
362 #interrupt-cells = <2> 286 #interrupt-cells = <2>;
363 }; 287 };
364 288
365 gpio3: gpio@e6051980 { 289 gpio3: gpio@e6051980 {
366 compatible = "renesas, 290 compatible = "renesas,gpio-r8a779f0",
367 "renesas, 291 "renesas,rcar-gen4-gpio";
368 reg = <0 0xe6051980 0 292 reg = <0 0xe6051980 0 0x54>;
369 interrupts = <GIC_SPI 293 interrupts = <GIC_SPI 825 IRQ_TYPE_LEVEL_HIGH>;
370 clocks = <&cpg CPG_MOD 294 clocks = <&cpg CPG_MOD 915>;
371 power-domains = <&sysc 295 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
372 resets = <&cpg 915>; 296 resets = <&cpg 915>;
373 gpio-controller; 297 gpio-controller;
374 #gpio-cells = <2>; 298 #gpio-cells = <2>;
375 gpio-ranges = <&pfc 0 299 gpio-ranges = <&pfc 0 96 19>;
376 interrupt-controller; 300 interrupt-controller;
377 #interrupt-cells = <2> 301 #interrupt-cells = <2>;
378 }; 302 };
379 303
380 cmt0: timer@e60f0000 { <<
381 compatible = "renesas, <<
382 "renesas, <<
383 reg = <0 0xe60f0000 0 <<
384 interrupts = <GIC_SPI <<
385 <GIC_SPI <<
386 clocks = <&cpg CPG_MOD <<
387 clock-names = "fck"; <<
388 power-domains = <&sysc <<
389 resets = <&cpg 910>; <<
390 status = "disabled"; <<
391 }; <<
392 <<
393 cmt1: timer@e6130000 { <<
394 compatible = "renesas, <<
395 "renesas, <<
396 reg = <0 0xe6130000 0 <<
397 interrupts = <GIC_SPI <<
398 <GIC_SPI <<
399 <GIC_SPI <<
400 <GIC_SPI <<
401 <GIC_SPI <<
402 <GIC_SPI <<
403 <GIC_SPI <<
404 <GIC_SPI <<
405 clocks = <&cpg CPG_MOD <<
406 clock-names = "fck"; <<
407 power-domains = <&sysc <<
408 resets = <&cpg 911>; <<
409 status = "disabled"; <<
410 }; <<
411 <<
412 cmt2: timer@e6140000 { <<
413 compatible = "renesas, <<
414 "renesas, <<
415 reg = <0 0xe6140000 0 <<
416 interrupts = <GIC_SPI <<
417 <GIC_SPI <<
418 <GIC_SPI <<
419 <GIC_SPI <<
420 <GIC_SPI <<
421 <GIC_SPI <<
422 <GIC_SPI <<
423 <GIC_SPI <<
424 clocks = <&cpg CPG_MOD <<
425 clock-names = "fck"; <<
426 power-domains = <&sysc <<
427 resets = <&cpg 912>; <<
428 status = "disabled"; <<
429 }; <<
430 <<
431 cmt3: timer@e6148000 { <<
432 compatible = "renesas, <<
433 "renesas, <<
434 reg = <0 0xe6148000 0 <<
435 interrupts = <GIC_SPI <<
436 <GIC_SPI <<
437 <GIC_SPI <<
438 <GIC_SPI <<
439 <GIC_SPI <<
440 <GIC_SPI <<
441 <GIC_SPI <<
442 <GIC_SPI <<
443 clocks = <&cpg CPG_MOD <<
444 clock-names = "fck"; <<
445 power-domains = <&sysc <<
446 resets = <&cpg 913>; <<
447 status = "disabled"; <<
448 }; <<
449 <<
450 cpg: clock-controller@e6150000 304 cpg: clock-controller@e6150000 {
451 compatible = "renesas, 305 compatible = "renesas,r8a779f0-cpg-mssr";
452 reg = <0 0xe6150000 0 306 reg = <0 0xe6150000 0 0x4000>;
453 clocks = <&extal_clk>, 307 clocks = <&extal_clk>, <&extalr_clk>;
454 clock-names = "extal", 308 clock-names = "extal", "extalr";
455 #clock-cells = <2>; 309 #clock-cells = <2>;
456 #power-domain-cells = 310 #power-domain-cells = <0>;
457 #reset-cells = <1>; 311 #reset-cells = <1>;
458 }; 312 };
459 313
460 rst: reset-controller@e6160000 314 rst: reset-controller@e6160000 {
461 compatible = "renesas, 315 compatible = "renesas,r8a779f0-rst";
462 reg = <0 0xe6160000 0 316 reg = <0 0xe6160000 0 0x4000>;
463 }; 317 };
464 318
465 sysc: system-controller@e61800 319 sysc: system-controller@e6180000 {
466 compatible = "renesas, 320 compatible = "renesas,r8a779f0-sysc";
467 reg = <0 0xe6180000 0 321 reg = <0 0xe6180000 0 0x4000>;
468 #power-domain-cells = 322 #power-domain-cells = <1>;
469 }; 323 };
470 324
471 tsc: thermal@e6198000 { 325 tsc: thermal@e6198000 {
472 compatible = "renesas, 326 compatible = "renesas,r8a779f0-thermal";
473 /* The 4th sensor is i 327 /* The 4th sensor is in control domain and not for Linux */
474 reg = <0 0xe6198000 0 328 reg = <0 0xe6198000 0 0x200>,
475 <0 0xe61a0000 0 329 <0 0xe61a0000 0 0x200>,
476 <0 0xe61a8000 0 330 <0 0xe61a8000 0 0x200>;
477 clocks = <&cpg CPG_MOD 331 clocks = <&cpg CPG_MOD 919>;
478 power-domains = <&sysc 332 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
479 resets = <&cpg 919>; 333 resets = <&cpg 919>;
480 #thermal-sensor-cells 334 #thermal-sensor-cells = <1>;
481 }; 335 };
482 336
483 intc_ex: interrupt-controller@ <<
484 compatible = "renesas, <<
485 #interrupt-cells = <2> <<
486 interrupt-controller; <<
487 reg = <0 0xe61c0000 0 <<
488 interrupts = <GIC_SPI <<
489 <GIC_SPI <<
490 <GIC_SPI <<
491 <GIC_SPI <<
492 <GIC_SPI <<
493 <GIC_SPI <<
494 clocks = <&cpg CPG_COR <<
495 power-domains = <&sysc <<
496 }; <<
497 <<
498 tmu0: timer@e61e0000 { <<
499 compatible = "renesas, <<
500 reg = <0 0xe61e0000 0 <<
501 interrupts = <GIC_SPI <<
502 <GIC_SPI <<
503 <GIC_SPI <<
504 interrupt-names = "tun <<
505 clocks = <&cpg CPG_MOD <<
506 clock-names = "fck"; <<
507 power-domains = <&sysc <<
508 resets = <&cpg 713>; <<
509 status = "disabled"; <<
510 }; <<
511 <<
512 tmu1: timer@e6fc0000 { <<
513 compatible = "renesas, <<
514 reg = <0 0xe6fc0000 0 <<
515 interrupts = <GIC_SPI <<
516 <GIC_SPI <<
517 <GIC_SPI <<
518 <GIC_SPI <<
519 interrupt-names = "tun <<
520 clocks = <&cpg CPG_MOD <<
521 clock-names = "fck"; <<
522 power-domains = <&sysc <<
523 resets = <&cpg 714>; <<
524 status = "disabled"; <<
525 }; <<
526 <<
527 tmu2: timer@e6fd0000 { <<
528 compatible = "renesas, <<
529 reg = <0 0xe6fd0000 0 <<
530 interrupts = <GIC_SPI <<
531 <GIC_SPI <<
532 <GIC_SPI <<
533 <GIC_SPI <<
534 interrupt-names = "tun <<
535 clocks = <&cpg CPG_MOD <<
536 clock-names = "fck"; <<
537 power-domains = <&sysc <<
538 resets = <&cpg 715>; <<
539 status = "disabled"; <<
540 }; <<
541 <<
542 tmu3: timer@e6fe0000 { <<
543 compatible = "renesas, <<
544 reg = <0 0xe6fe0000 0 <<
545 interrupts = <GIC_SPI <<
546 <GIC_SPI <<
547 <GIC_SPI <<
548 <GIC_SPI <<
549 interrupt-names = "tun <<
550 clocks = <&cpg CPG_MOD <<
551 clock-names = "fck"; <<
552 power-domains = <&sysc <<
553 resets = <&cpg 716>; <<
554 status = "disabled"; <<
555 }; <<
556 <<
557 tmu4: timer@ffc00000 { <<
558 compatible = "renesas, <<
559 reg = <0 0xffc00000 0 <<
560 interrupts = <GIC_SPI <<
561 <GIC_SPI <<
562 <GIC_SPI <<
563 <GIC_SPI <<
564 interrupt-names = "tun <<
565 clocks = <&cpg CPG_MOD <<
566 clock-names = "fck"; <<
567 power-domains = <&sysc <<
568 resets = <&cpg 717>; <<
569 status = "disabled"; <<
570 }; <<
571 <<
572 eth_serdes: phy@e6444000 { <<
573 compatible = "renesas, <<
574 reg = <0 0xe6444000 0 <<
575 clocks = <&cpg CPG_MOD <<
576 power-domains = <&sysc <<
577 resets = <&cpg 1506>; <<
578 #phy-cells = <1>; <<
579 status = "disabled"; <<
580 }; <<
581 <<
582 i2c0: i2c@e6500000 { 337 i2c0: i2c@e6500000 {
583 compatible = "renesas, 338 compatible = "renesas,i2c-r8a779f0",
584 "renesas, 339 "renesas,rcar-gen4-i2c";
585 reg = <0 0xe6500000 0 340 reg = <0 0xe6500000 0 0x40>;
586 interrupts = <GIC_SPI 341 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
587 clocks = <&cpg CPG_MOD 342 clocks = <&cpg CPG_MOD 518>;
588 power-domains = <&sysc 343 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
589 resets = <&cpg 518>; 344 resets = <&cpg 518>;
590 dmas = <&dmac0 0x91>, 345 dmas = <&dmac0 0x91>, <&dmac0 0x90>,
591 <&dmac1 0x91>, 346 <&dmac1 0x91>, <&dmac1 0x90>;
592 dma-names = "tx", "rx" 347 dma-names = "tx", "rx", "tx", "rx";
593 i2c-scl-internal-delay 348 i2c-scl-internal-delay-ns = <110>;
594 #address-cells = <1>; 349 #address-cells = <1>;
595 #size-cells = <0>; 350 #size-cells = <0>;
596 status = "disabled"; 351 status = "disabled";
597 }; 352 };
598 353
599 i2c1: i2c@e6508000 { 354 i2c1: i2c@e6508000 {
600 compatible = "renesas, 355 compatible = "renesas,i2c-r8a779f0",
601 "renesas, 356 "renesas,rcar-gen4-i2c";
602 reg = <0 0xe6508000 0 357 reg = <0 0xe6508000 0 0x40>;
603 interrupts = <GIC_SPI 358 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
604 clocks = <&cpg CPG_MOD 359 clocks = <&cpg CPG_MOD 519>;
605 power-domains = <&sysc 360 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
606 resets = <&cpg 519>; 361 resets = <&cpg 519>;
607 dmas = <&dmac0 0x93>, 362 dmas = <&dmac0 0x93>, <&dmac0 0x92>,
608 <&dmac1 0x93>, 363 <&dmac1 0x93>, <&dmac1 0x92>;
609 dma-names = "tx", "rx" 364 dma-names = "tx", "rx", "tx", "rx";
610 i2c-scl-internal-delay 365 i2c-scl-internal-delay-ns = <110>;
611 #address-cells = <1>; 366 #address-cells = <1>;
612 #size-cells = <0>; 367 #size-cells = <0>;
613 status = "disabled"; 368 status = "disabled";
614 }; 369 };
615 370
616 i2c2: i2c@e6510000 { 371 i2c2: i2c@e6510000 {
617 compatible = "renesas, 372 compatible = "renesas,i2c-r8a779f0",
618 "renesas, 373 "renesas,rcar-gen4-i2c";
619 reg = <0 0xe6510000 0 374 reg = <0 0xe6510000 0 0x40>;
620 interrupts = <0 240 IR 375 interrupts = <0 240 IRQ_TYPE_LEVEL_HIGH>;
621 clocks = <&cpg CPG_MOD 376 clocks = <&cpg CPG_MOD 520>;
622 power-domains = <&sysc 377 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
623 resets = <&cpg 520>; 378 resets = <&cpg 520>;
624 dmas = <&dmac0 0x95>, 379 dmas = <&dmac0 0x95>, <&dmac0 0x94>,
625 <&dmac1 0x95>, 380 <&dmac1 0x95>, <&dmac1 0x94>;
626 dma-names = "tx", "rx" 381 dma-names = "tx", "rx", "tx", "rx";
627 i2c-scl-internal-delay 382 i2c-scl-internal-delay-ns = <110>;
628 #address-cells = <1>; 383 #address-cells = <1>;
629 #size-cells = <0>; 384 #size-cells = <0>;
630 status = "disabled"; 385 status = "disabled";
631 }; 386 };
632 387
633 i2c3: i2c@e66d0000 { 388 i2c3: i2c@e66d0000 {
634 compatible = "renesas, 389 compatible = "renesas,i2c-r8a779f0",
635 "renesas, 390 "renesas,rcar-gen4-i2c";
636 reg = <0 0xe66d0000 0 391 reg = <0 0xe66d0000 0 0x40>;
637 interrupts = <GIC_SPI 392 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>;
638 clocks = <&cpg CPG_MOD 393 clocks = <&cpg CPG_MOD 521>;
639 power-domains = <&sysc 394 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
640 resets = <&cpg 521>; 395 resets = <&cpg 521>;
641 dmas = <&dmac0 0x97>, 396 dmas = <&dmac0 0x97>, <&dmac0 0x96>,
642 <&dmac1 0x97>, 397 <&dmac1 0x97>, <&dmac1 0x96>;
643 dma-names = "tx", "rx" 398 dma-names = "tx", "rx", "tx", "rx";
644 i2c-scl-internal-delay 399 i2c-scl-internal-delay-ns = <110>;
645 #address-cells = <1>; 400 #address-cells = <1>;
646 #size-cells = <0>; 401 #size-cells = <0>;
647 status = "disabled"; 402 status = "disabled";
648 }; 403 };
649 404
650 i2c4: i2c@e66d8000 { 405 i2c4: i2c@e66d8000 {
651 compatible = "renesas, 406 compatible = "renesas,i2c-r8a779f0",
652 "renesas, 407 "renesas,rcar-gen4-i2c";
653 reg = <0 0xe66d8000 0 408 reg = <0 0xe66d8000 0 0x40>;
654 interrupts = <GIC_SPI 409 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>;
655 clocks = <&cpg CPG_MOD 410 clocks = <&cpg CPG_MOD 522>;
656 power-domains = <&sysc 411 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
657 resets = <&cpg 522>; 412 resets = <&cpg 522>;
658 dmas = <&dmac0 0x99>, 413 dmas = <&dmac0 0x99>, <&dmac0 0x98>,
659 <&dmac1 0x99>, 414 <&dmac1 0x99>, <&dmac1 0x98>;
660 dma-names = "tx", "rx" 415 dma-names = "tx", "rx", "tx", "rx";
661 i2c-scl-internal-delay 416 i2c-scl-internal-delay-ns = <110>;
662 #address-cells = <1>; 417 #address-cells = <1>;
663 #size-cells = <0>; 418 #size-cells = <0>;
664 status = "disabled"; 419 status = "disabled";
665 }; 420 };
666 421
667 i2c5: i2c@e66e0000 { 422 i2c5: i2c@e66e0000 {
668 compatible = "renesas, 423 compatible = "renesas,i2c-r8a779f0",
669 "renesas, 424 "renesas,rcar-gen4-i2c";
670 reg = <0 0xe66e0000 0 425 reg = <0 0xe66e0000 0 0x40>;
671 interrupts = <GIC_SPI 426 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
672 clocks = <&cpg CPG_MOD 427 clocks = <&cpg CPG_MOD 523>;
673 power-domains = <&sysc 428 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
674 resets = <&cpg 523>; 429 resets = <&cpg 523>;
675 dmas = <&dmac0 0x9b>, 430 dmas = <&dmac0 0x9b>, <&dmac0 0x9a>,
676 <&dmac1 0x9b>, 431 <&dmac1 0x9b>, <&dmac1 0x9a>;
677 dma-names = "tx", "rx" 432 dma-names = "tx", "rx", "tx", "rx";
678 i2c-scl-internal-delay 433 i2c-scl-internal-delay-ns = <110>;
679 #address-cells = <1>; 434 #address-cells = <1>;
680 #size-cells = <0>; 435 #size-cells = <0>;
681 status = "disabled"; 436 status = "disabled";
682 }; 437 };
683 438
684 hscif0: serial@e6540000 { 439 hscif0: serial@e6540000 {
685 compatible = "renesas, 440 compatible = "renesas,hscif-r8a779f0",
686 "renesas, 441 "renesas,rcar-gen4-hscif", "renesas,hscif";
687 reg = <0 0xe6540000 0 442 reg = <0 0xe6540000 0 0x60>;
688 interrupts = <GIC_SPI 443 interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>;
689 clocks = <&cpg CPG_MOD 444 clocks = <&cpg CPG_MOD 514>,
690 <&cpg CPG_COR 445 <&cpg CPG_CORE R8A779F0_CLK_SASYNCPERD1>,
691 <&scif_clk>; 446 <&scif_clk>;
692 clock-names = "fck", " 447 clock-names = "fck", "brg_int", "scif_clk";
693 dmas = <&dmac0 0x31>, 448 dmas = <&dmac0 0x31>, <&dmac0 0x30>,
694 <&dmac1 0x31>, 449 <&dmac1 0x31>, <&dmac1 0x30>;
695 dma-names = "tx", "rx" 450 dma-names = "tx", "rx", "tx", "rx";
696 power-domains = <&sysc 451 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
697 resets = <&cpg 514>; 452 resets = <&cpg 514>;
698 status = "disabled"; 453 status = "disabled";
699 }; 454 };
700 455
701 hscif1: serial@e6550000 { 456 hscif1: serial@e6550000 {
702 compatible = "renesas, 457 compatible = "renesas,hscif-r8a779f0",
703 "renesas, 458 "renesas,rcar-gen4-hscif", "renesas,hscif";
704 reg = <0 0xe6550000 0 459 reg = <0 0xe6550000 0 0x60>;
705 interrupts = <GIC_SPI 460 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
706 clocks = <&cpg CPG_MOD 461 clocks = <&cpg CPG_MOD 515>,
707 <&cpg CPG_COR 462 <&cpg CPG_CORE R8A779F0_CLK_SASYNCPERD1>,
708 <&scif_clk>; 463 <&scif_clk>;
709 clock-names = "fck", " 464 clock-names = "fck", "brg_int", "scif_clk";
710 dmas = <&dmac0 0x33>, 465 dmas = <&dmac0 0x33>, <&dmac0 0x32>,
711 <&dmac1 0x33>, 466 <&dmac1 0x33>, <&dmac1 0x32>;
712 dma-names = "tx", "rx" 467 dma-names = "tx", "rx", "tx", "rx";
713 power-domains = <&sysc 468 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
714 resets = <&cpg 515>; 469 resets = <&cpg 515>;
715 status = "disabled"; 470 status = "disabled";
716 }; 471 };
717 472
718 hscif2: serial@e6560000 { 473 hscif2: serial@e6560000 {
719 compatible = "renesas, 474 compatible = "renesas,hscif-r8a779f0",
720 "renesas, 475 "renesas,rcar-gen4-hscif", "renesas,hscif";
721 reg = <0 0xe6560000 0 476 reg = <0 0xe6560000 0 0x60>;
722 interrupts = <GIC_SPI 477 interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
723 clocks = <&cpg CPG_MOD 478 clocks = <&cpg CPG_MOD 516>,
724 <&cpg CPG_COR 479 <&cpg CPG_CORE R8A779F0_CLK_SASYNCPERD1>,
725 <&scif_clk>; 480 <&scif_clk>;
726 clock-names = "fck", " 481 clock-names = "fck", "brg_int", "scif_clk";
727 dmas = <&dmac0 0x35>, 482 dmas = <&dmac0 0x35>, <&dmac0 0x34>,
728 <&dmac1 0x35>, 483 <&dmac1 0x35>, <&dmac1 0x34>;
729 dma-names = "tx", "rx" 484 dma-names = "tx", "rx", "tx", "rx";
730 power-domains = <&sysc 485 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
731 resets = <&cpg 516>; 486 resets = <&cpg 516>;
732 status = "disabled"; 487 status = "disabled";
733 }; 488 };
734 489
735 hscif3: serial@e66a0000 { 490 hscif3: serial@e66a0000 {
736 compatible = "renesas, 491 compatible = "renesas,hscif-r8a779f0",
737 "renesas, 492 "renesas,rcar-gen4-hscif", "renesas,hscif";
738 reg = <0 0xe66a0000 0 493 reg = <0 0xe66a0000 0 0x60>;
739 interrupts = <GIC_SPI 494 interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>;
740 clocks = <&cpg CPG_MOD 495 clocks = <&cpg CPG_MOD 517>,
741 <&cpg CPG_COR 496 <&cpg CPG_CORE R8A779F0_CLK_SASYNCPERD1>,
742 <&scif_clk>; 497 <&scif_clk>;
743 clock-names = "fck", " 498 clock-names = "fck", "brg_int", "scif_clk";
744 dmas = <&dmac0 0x37>, 499 dmas = <&dmac0 0x37>, <&dmac0 0x36>,
745 <&dmac1 0x37>, 500 <&dmac1 0x37>, <&dmac1 0x36>;
746 dma-names = "tx", "rx" 501 dma-names = "tx", "rx", "tx", "rx";
747 power-domains = <&sysc 502 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
748 resets = <&cpg 517>; 503 resets = <&cpg 517>;
749 status = "disabled"; 504 status = "disabled";
750 }; 505 };
751 506
752 pciec0: pcie@e65d0000 { <<
753 compatible = "renesas, <<
754 "renesas, <<
755 reg = <0 0xe65d0000 0 <<
756 <0 0xe65d3000 0 <<
757 <0 0xe65d6200 0 <<
758 <0 0xfe000000 0 <<
759 reg-names = "dbi", "db <<
760 interrupts = <GIC_SPI <<
761 <GIC_SPI <<
762 <GIC_SPI <<
763 <GIC_SPI <<
764 interrupt-names = "msi <<
765 clocks = <&cpg CPG_MOD <<
766 clock-names = "core", <<
767 power-domains = <&sysc <<
768 resets = <&cpg 624>; <<
769 reset-names = "pwr"; <<
770 max-link-speed = <4>; <<
771 num-lanes = <2>; <<
772 #address-cells = <3>; <<
773 #size-cells = <2>; <<
774 bus-range = <0x00 0xff <<
775 device_type = "pci"; <<
776 ranges = <0x01000000 0 <<
777 <0x02000000 0 <<
778 dma-ranges = <0x420000 <<
779 #interrupt-cells = <1> <<
780 interrupt-map-mask = < <<
781 interrupt-map = <0 0 0 <<
782 <0 0 0 <<
783 <0 0 0 <<
784 <0 0 0 <<
785 snps,enable-cdm-check; <<
786 status = "disabled"; <<
787 }; <<
788 <<
789 pciec1: pcie@e65d8000 { <<
790 compatible = "renesas, <<
791 "renesas, <<
792 reg = <0 0xe65d8000 0 <<
793 <0 0xe65db000 0 <<
794 <0 0xe65de200 0 <<
795 <0 0xee900000 0 <<
796 reg-names = "dbi", "db <<
797 interrupts = <GIC_SPI <<
798 <GIC_SPI <<
799 <GIC_SPI <<
800 <GIC_SPI <<
801 interrupt-names = "msi <<
802 clocks = <&cpg CPG_MOD <<
803 clock-names = "core", <<
804 power-domains = <&sysc <<
805 resets = <&cpg 625>; <<
806 reset-names = "pwr"; <<
807 max-link-speed = <4>; <<
808 num-lanes = <2>; <<
809 #address-cells = <3>; <<
810 #size-cells = <2>; <<
811 bus-range = <0x00 0xff <<
812 device_type = "pci"; <<
813 ranges = <0x01000000 0 <<
814 <0x02000000 0 <<
815 dma-ranges = <0x420000 <<
816 #interrupt-cells = <1> <<
817 interrupt-map-mask = < <<
818 interrupt-map = <0 0 0 <<
819 <0 0 0 <<
820 <0 0 0 <<
821 <0 0 0 <<
822 snps,enable-cdm-check; <<
823 status = "disabled"; <<
824 }; <<
825 <<
826 pciec0_ep: pcie-ep@e65d0000 { <<
827 compatible = "renesas, <<
828 "renesas, <<
829 reg = <0 0xe65d0000 0 <<
830 <0 0xe65d3000 0 <<
831 <0 0xe65d6200 0 <<
832 <0 0xfe000000 0 <<
833 reg-names = "dbi", "db <<
834 interrupts = <GIC_SPI <<
835 <GIC_SPI <<
836 <GIC_SPI <<
837 interrupt-names = "dma <<
838 clocks = <&cpg CPG_MOD <<
839 clock-names = "core", <<
840 power-domains = <&sysc <<
841 resets = <&cpg 624>; <<
842 reset-names = "pwr"; <<
843 max-link-speed = <4>; <<
844 num-lanes = <2>; <<
845 max-functions = /bits/ <<
846 status = "disabled"; <<
847 }; <<
848 <<
849 pciec1_ep: pcie-ep@e65d8000 { <<
850 compatible = "renesas, <<
851 "renesas, <<
852 reg = <0 0xe65d8000 0 <<
853 <0 0xe65db000 0 <<
854 <0 0xe65de200 0 <<
855 <0 0xee900000 0 <<
856 reg-names = "dbi", "db <<
857 interrupts = <GIC_SPI <<
858 <GIC_SPI <<
859 <GIC_SPI <<
860 interrupt-names = "dma <<
861 clocks = <&cpg CPG_MOD <<
862 clock-names = "core", <<
863 power-domains = <&sysc <<
864 resets = <&cpg 625>; <<
865 reset-names = "pwr"; <<
866 max-link-speed = <4>; <<
867 num-lanes = <2>; <<
868 max-functions = /bits/ <<
869 status = "disabled"; <<
870 }; <<
871 <<
872 ufs: ufs@e6860000 { 507 ufs: ufs@e6860000 {
873 compatible = "renesas, 508 compatible = "renesas,r8a779f0-ufs";
874 reg = <0 0xe6860000 0 509 reg = <0 0xe6860000 0 0x100>;
875 interrupts = <GIC_SPI 510 interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>;
876 clocks = <&cpg CPG_MOD 511 clocks = <&cpg CPG_MOD 1514>, <&ufs30_clk>;
877 clock-names = "fck", " 512 clock-names = "fck", "ref_clk";
878 freq-table-hz = <20000 513 freq-table-hz = <200000000 200000000>, <38400000 38400000>;
879 power-domains = <&sysc 514 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
880 resets = <&cpg 1514>; 515 resets = <&cpg 1514>;
881 status = "disabled"; 516 status = "disabled";
882 }; 517 };
883 518
884 rswitch: ethernet@e6880000 { <<
885 compatible = "renesas, <<
886 reg = <0 0xe6880000 0 <<
887 reg-names = "base", "s <<
888 interrupts = <GIC_SPI <<
889 <GIC_SPI <<
890 <GIC_SPI <<
891 <GIC_SPI <<
892 <GIC_SPI <<
893 <GIC_SPI <<
894 <GIC_SPI <<
895 <GIC_SPI <<
896 <GIC_SPI <<
897 <GIC_SPI <<
898 <GIC_SPI <<
899 <GIC_SPI <<
900 <GIC_SPI <<
901 <GIC_SPI <<
902 <GIC_SPI <<
903 <GIC_SPI <<
904 <GIC_SPI <<
905 <GIC_SPI <<
906 <GIC_SPI <<
907 <GIC_SPI <<
908 <GIC_SPI <<
909 <GIC_SPI <<
910 <GIC_SPI <<
911 <GIC_SPI <<
912 <GIC_SPI <<
913 <GIC_SPI <<
914 <GIC_SPI <<
915 <GIC_SPI <<
916 <GIC_SPI <<
917 <GIC_SPI <<
918 <GIC_SPI <<
919 <GIC_SPI <<
920 <GIC_SPI <<
921 <GIC_SPI <<
922 <GIC_SPI <<
923 <GIC_SPI <<
924 <GIC_SPI <<
925 <GIC_SPI <<
926 <GIC_SPI <<
927 <GIC_SPI <<
928 <GIC_SPI <<
929 <GIC_SPI <<
930 <GIC_SPI <<
931 <GIC_SPI <<
932 <GIC_SPI <<
933 <GIC_SPI <<
934 <GIC_SPI <<
935 interrupt-names = "mfw <<
936 "com <<
937 "gwc <<
938 "eth <<
939 "gpt <<
940 "mfw <<
941 "com <<
942 "gwc <<
943 "eth <<
944 "rma <<
945 "rma <<
946 "gwc <<
947 "gwc <<
948 "gwc <<
949 "gwc <<
950 "gwc <<
951 "gwc <<
952 "gwc <<
953 "gwc <<
954 "gwc <<
955 "gwc <<
956 "rma <<
957 "rma <<
958 "rma <<
959 "rma <<
960 clocks = <&cpg CPG_MOD <<
961 power-domains = <&sysc <<
962 resets = <&cpg 1505>; <<
963 status = "disabled"; <<
964 <<
965 ethernet-ports { <<
966 #address-cells <<
967 #size-cells = <<
968 <<
969 port@0 { <<
970 reg = <<
971 phys = <<
972 }; <<
973 port@1 { <<
974 reg = <<
975 phys = <<
976 }; <<
977 port@2 { <<
978 reg = <<
979 phys = <<
980 }; <<
981 }; <<
982 }; <<
983 <<
984 scif0: serial@e6e60000 { 519 scif0: serial@e6e60000 {
985 compatible = "renesas, 520 compatible = "renesas,scif-r8a779f0",
986 "renesas, 521 "renesas,rcar-gen4-scif", "renesas,scif";
987 reg = <0 0xe6e60000 0 522 reg = <0 0xe6e60000 0 64>;
988 interrupts = <GIC_SPI 523 interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>;
989 clocks = <&cpg CPG_MOD 524 clocks = <&cpg CPG_MOD 702>,
990 <&cpg CPG_COR 525 <&cpg CPG_CORE R8A779F0_CLK_SASYNCPERD1>,
991 <&scif_clk>; 526 <&scif_clk>;
992 clock-names = "fck", " 527 clock-names = "fck", "brg_int", "scif_clk";
993 dmas = <&dmac0 0x51>, 528 dmas = <&dmac0 0x51>, <&dmac0 0x50>,
994 <&dmac1 0x51>, 529 <&dmac1 0x51>, <&dmac1 0x50>;
995 dma-names = "tx", "rx" 530 dma-names = "tx", "rx", "tx", "rx";
996 power-domains = <&sysc 531 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
997 resets = <&cpg 702>; 532 resets = <&cpg 702>;
998 status = "disabled"; 533 status = "disabled";
999 }; 534 };
1000 535
1001 scif1: serial@e6e68000 { 536 scif1: serial@e6e68000 {
1002 compatible = "renesas 537 compatible = "renesas,scif-r8a779f0",
1003 "renesas 538 "renesas,rcar-gen4-scif", "renesas,scif";
1004 reg = <0 0xe6e68000 0 539 reg = <0 0xe6e68000 0 64>;
1005 interrupts = <GIC_SPI 540 interrupts = <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>;
1006 clocks = <&cpg CPG_MO 541 clocks = <&cpg CPG_MOD 703>,
1007 <&cpg CPG_CO 542 <&cpg CPG_CORE R8A779F0_CLK_SASYNCPERD1>,
1008 <&scif_clk>; 543 <&scif_clk>;
1009 clock-names = "fck", 544 clock-names = "fck", "brg_int", "scif_clk";
1010 dmas = <&dmac0 0x53>, 545 dmas = <&dmac0 0x53>, <&dmac0 0x52>,
1011 <&dmac1 0x53>, 546 <&dmac1 0x53>, <&dmac1 0x52>;
1012 dma-names = "tx", "rx 547 dma-names = "tx", "rx", "tx", "rx";
1013 power-domains = <&sys 548 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
1014 resets = <&cpg 703>; 549 resets = <&cpg 703>;
1015 status = "disabled"; 550 status = "disabled";
1016 }; 551 };
1017 552
1018 scif3: serial@e6c50000 { 553 scif3: serial@e6c50000 {
1019 compatible = "renesas 554 compatible = "renesas,scif-r8a779f0",
1020 "renesas 555 "renesas,rcar-gen4-scif", "renesas,scif";
1021 reg = <0 0xe6c50000 0 556 reg = <0 0xe6c50000 0 64>;
1022 interrupts = <GIC_SPI 557 interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>;
1023 clocks = <&cpg CPG_MO 558 clocks = <&cpg CPG_MOD 704>,
1024 <&cpg CPG_CO 559 <&cpg CPG_CORE R8A779F0_CLK_SASYNCPERD1>,
1025 <&scif_clk>; 560 <&scif_clk>;
1026 clock-names = "fck", 561 clock-names = "fck", "brg_int", "scif_clk";
1027 dmas = <&dmac0 0x57>, 562 dmas = <&dmac0 0x57>, <&dmac0 0x56>,
1028 <&dmac1 0x57>, 563 <&dmac1 0x57>, <&dmac1 0x56>;
1029 dma-names = "tx", "rx 564 dma-names = "tx", "rx", "tx", "rx";
1030 power-domains = <&sys 565 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
1031 resets = <&cpg 704>; 566 resets = <&cpg 704>;
1032 status = "disabled"; 567 status = "disabled";
1033 }; 568 };
1034 569
1035 scif4: serial@e6c40000 { 570 scif4: serial@e6c40000 {
1036 compatible = "renesas 571 compatible = "renesas,scif-r8a779f0",
1037 "renesas 572 "renesas,rcar-gen4-scif", "renesas,scif";
1038 reg = <0 0xe6c40000 0 573 reg = <0 0xe6c40000 0 64>;
1039 interrupts = <GIC_SPI 574 interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>;
1040 clocks = <&cpg CPG_MO 575 clocks = <&cpg CPG_MOD 705>,
1041 <&cpg CPG_CO 576 <&cpg CPG_CORE R8A779F0_CLK_SASYNCPERD1>,
1042 <&scif_clk>; 577 <&scif_clk>;
1043 clock-names = "fck", 578 clock-names = "fck", "brg_int", "scif_clk";
1044 dmas = <&dmac0 0x59>, 579 dmas = <&dmac0 0x59>, <&dmac0 0x58>,
1045 <&dmac1 0x59>, 580 <&dmac1 0x59>, <&dmac1 0x58>;
1046 dma-names = "tx", "rx 581 dma-names = "tx", "rx", "tx", "rx";
1047 power-domains = <&sys 582 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
1048 resets = <&cpg 705>; 583 resets = <&cpg 705>;
1049 status = "disabled"; 584 status = "disabled";
1050 }; 585 };
1051 586
1052 msiof0: spi@e6e90000 { <<
1053 compatible = "renesas <<
1054 "renesas <<
1055 reg = <0 0xe6e90000 0 <<
1056 interrupts = <GIC_SPI <<
1057 clocks = <&cpg CPG_MO <<
1058 dmas = <&dmac0 0x41>, <<
1059 <&dmac1 0x41>, <<
1060 dma-names = "tx", "rx <<
1061 power-domains = <&sys <<
1062 resets = <&cpg 618>; <<
1063 #address-cells = <1>; <<
1064 #size-cells = <0>; <<
1065 status = "disabled"; <<
1066 }; <<
1067 <<
1068 msiof1: spi@e6ea0000 { <<
1069 compatible = "renesas <<
1070 "renesas <<
1071 reg = <0 0xe6ea0000 0 <<
1072 interrupts = <GIC_SPI <<
1073 clocks = <&cpg CPG_MO <<
1074 dmas = <&dmac0 0x43>, <<
1075 <&dmac1 0x43>, <<
1076 dma-names = "tx", "rx <<
1077 power-domains = <&sys <<
1078 resets = <&cpg 619>; <<
1079 #address-cells = <1>; <<
1080 #size-cells = <0>; <<
1081 status = "disabled"; <<
1082 }; <<
1083 <<
1084 msiof2: spi@e6c00000 { <<
1085 compatible = "renesas <<
1086 "renesas <<
1087 reg = <0 0xe6c00000 0 <<
1088 interrupts = <GIC_SPI <<
1089 clocks = <&cpg CPG_MO <<
1090 dmas = <&dmac0 0x45>, <<
1091 <&dmac1 0x45>, <<
1092 dma-names = "tx", "rx <<
1093 power-domains = <&sys <<
1094 resets = <&cpg 620>; <<
1095 #address-cells = <1>; <<
1096 #size-cells = <0>; <<
1097 status = "disabled"; <<
1098 }; <<
1099 <<
1100 msiof3: spi@e6c10000 { <<
1101 compatible = "renesas <<
1102 "renesas <<
1103 reg = <0 0xe6c10000 0 <<
1104 interrupts = <GIC_SPI <<
1105 clocks = <&cpg CPG_MO <<
1106 dmas = <&dmac0 0x47>, <<
1107 <&dmac1 0x47>, <<
1108 dma-names = "tx", "rx <<
1109 power-domains = <&sys <<
1110 resets = <&cpg 621>; <<
1111 #address-cells = <1>; <<
1112 #size-cells = <0>; <<
1113 status = "disabled"; <<
1114 }; <<
1115 <<
1116 dmac0: dma-controller@e735000 587 dmac0: dma-controller@e7350000 {
1117 compatible = "renesas 588 compatible = "renesas,dmac-r8a779f0",
1118 "renesas 589 "renesas,rcar-gen4-dmac";
1119 reg = <0 0xe7350000 0 590 reg = <0 0xe7350000 0 0x1000>,
1120 <0 0xe7300000 0 591 <0 0xe7300000 0 0x10000>;
1121 interrupts = <GIC_SPI 592 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
1122 <GIC_SPI 593 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
1123 <GIC_SPI 594 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
1124 <GIC_SPI 595 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
1125 <GIC_SPI 596 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
1126 <GIC_SPI 597 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
1127 <GIC_SPI 598 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
1128 <GIC_SPI 599 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
1129 <GIC_SPI 600 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
1130 <GIC_SPI 601 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
1131 <GIC_SPI 602 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
1132 <GIC_SPI 603 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
1133 <GIC_SPI 604 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
1134 <GIC_SPI 605 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
1135 <GIC_SPI 606 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
1136 <GIC_SPI 607 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
1137 <GIC_SPI 608 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
1138 interrupt-names = "er 609 interrupt-names = "error",
1139 "ch 610 "ch0", "ch1", "ch2", "ch3", "ch4",
1140 "ch 611 "ch5", "ch6", "ch7", "ch8", "ch9",
1141 "ch 612 "ch10", "ch11", "ch12", "ch13",
1142 "ch 613 "ch14", "ch15";
1143 clocks = <&cpg CPG_MO 614 clocks = <&cpg CPG_MOD 709>;
1144 clock-names = "fck"; 615 clock-names = "fck";
1145 power-domains = <&sys 616 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
1146 resets = <&cpg 709>; 617 resets = <&cpg 709>;
1147 #dma-cells = <1>; 618 #dma-cells = <1>;
1148 dma-channels = <16>; 619 dma-channels = <16>;
1149 iommus = <&ipmmu_ds0 620 iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>,
1150 <&ipmmu_ds0 621 <&ipmmu_ds0 2>, <&ipmmu_ds0 3>,
1151 <&ipmmu_ds0 622 <&ipmmu_ds0 4>, <&ipmmu_ds0 5>,
1152 <&ipmmu_ds0 623 <&ipmmu_ds0 6>, <&ipmmu_ds0 7>,
1153 <&ipmmu_ds0 624 <&ipmmu_ds0 8>, <&ipmmu_ds0 9>,
1154 <&ipmmu_ds0 625 <&ipmmu_ds0 10>, <&ipmmu_ds0 11>,
1155 <&ipmmu_ds0 626 <&ipmmu_ds0 12>, <&ipmmu_ds0 13>,
1156 <&ipmmu_ds0 627 <&ipmmu_ds0 14>, <&ipmmu_ds0 15>;
1157 }; 628 };
1158 629
1159 dmac1: dma-controller@e735100 630 dmac1: dma-controller@e7351000 {
1160 compatible = "renesas 631 compatible = "renesas,dmac-r8a779f0",
1161 "renesas 632 "renesas,rcar-gen4-dmac";
1162 reg = <0 0xe7351000 0 633 reg = <0 0xe7351000 0 0x1000>,
1163 <0 0xe7310000 0 634 <0 0xe7310000 0 0x10000>;
1164 interrupts = <GIC_SPI 635 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
1165 <GIC_SPI 636 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
1166 <GIC_SPI 637 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
1167 <GIC_SPI 638 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
1168 <GIC_SPI 639 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
1169 <GIC_SPI 640 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
1170 <GIC_SPI 641 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
1171 <GIC_SPI 642 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
1172 <GIC_SPI 643 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
1173 <GIC_SPI 644 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
1174 <GIC_SPI 645 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
1175 <GIC_SPI 646 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
1176 <GIC_SPI 647 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
1177 <GIC_SPI 648 <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
1178 <GIC_SPI 649 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
1179 <GIC_SPI 650 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
1180 <GIC_SPI 651 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
1181 interrupt-names = "er 652 interrupt-names = "error",
1182 "ch 653 "ch0", "ch1", "ch2", "ch3", "ch4",
1183 "ch 654 "ch5", "ch6", "ch7", "ch8", "ch9",
1184 "ch 655 "ch10", "ch11", "ch12", "ch13",
1185 "ch 656 "ch14", "ch15";
1186 clocks = <&cpg CPG_MO 657 clocks = <&cpg CPG_MOD 710>;
1187 clock-names = "fck"; 658 clock-names = "fck";
1188 power-domains = <&sys 659 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
1189 resets = <&cpg 710>; 660 resets = <&cpg 710>;
1190 #dma-cells = <1>; 661 #dma-cells = <1>;
1191 dma-channels = <16>; 662 dma-channels = <16>;
1192 iommus = <&ipmmu_ds0 663 iommus = <&ipmmu_ds0 16>, <&ipmmu_ds0 17>,
1193 <&ipmmu_ds0 664 <&ipmmu_ds0 18>, <&ipmmu_ds0 19>,
1194 <&ipmmu_ds0 665 <&ipmmu_ds0 20>, <&ipmmu_ds0 21>,
1195 <&ipmmu_ds0 666 <&ipmmu_ds0 22>, <&ipmmu_ds0 23>,
1196 <&ipmmu_ds0 667 <&ipmmu_ds0 24>, <&ipmmu_ds0 25>,
1197 <&ipmmu_ds0 668 <&ipmmu_ds0 26>, <&ipmmu_ds0 27>,
1198 <&ipmmu_ds0 669 <&ipmmu_ds0 28>, <&ipmmu_ds0 29>,
1199 <&ipmmu_ds0 670 <&ipmmu_ds0 30>, <&ipmmu_ds0 31>;
1200 }; 671 };
1201 672
1202 mmc0: mmc@ee140000 { <<
1203 compatible = "renesas <<
1204 "renesas <<
1205 reg = <0 0xee140000 0 <<
1206 interrupts = <GIC_SPI <<
1207 clocks = <&cpg CPG_MO <<
1208 clock-names = "core", <<
1209 power-domains = <&sys <<
1210 resets = <&cpg 706>; <<
1211 max-frequency = <2000 <<
1212 iommus = <&ipmmu_ds0 <<
1213 status = "disabled"; <<
1214 }; <<
1215 <<
1216 ipmmu_rt0: iommu@ee480000 { 673 ipmmu_rt0: iommu@ee480000 {
1217 compatible = "renesas 674 compatible = "renesas,ipmmu-r8a779f0",
1218 "renesas 675 "renesas,rcar-gen4-ipmmu-vmsa";
1219 reg = <0 0xee480000 0 676 reg = <0 0xee480000 0 0x20000>;
1220 renesas,ipmmu-main = !! 677 renesas,ipmmu-main = <&ipmmu_mm 10>;
1221 power-domains = <&sys 678 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
1222 #iommu-cells = <1>; 679 #iommu-cells = <1>;
1223 }; 680 };
1224 681
1225 ipmmu_rt1: iommu@ee4c0000 { 682 ipmmu_rt1: iommu@ee4c0000 {
1226 compatible = "renesas 683 compatible = "renesas,ipmmu-r8a779f0",
1227 "renesas 684 "renesas,rcar-gen4-ipmmu-vmsa";
1228 reg = <0 0xee4c0000 0 685 reg = <0 0xee4c0000 0 0x20000>;
1229 renesas,ipmmu-main = !! 686 renesas,ipmmu-main = <&ipmmu_mm 19>;
1230 power-domains = <&sys 687 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
1231 #iommu-cells = <1>; 688 #iommu-cells = <1>;
1232 }; 689 };
1233 690
1234 ipmmu_ds0: iommu@eed00000 { 691 ipmmu_ds0: iommu@eed00000 {
1235 compatible = "renesas 692 compatible = "renesas,ipmmu-r8a779f0",
1236 "renesas 693 "renesas,rcar-gen4-ipmmu-vmsa";
1237 reg = <0 0xeed00000 0 694 reg = <0 0xeed00000 0 0x20000>;
1238 renesas,ipmmu-main = !! 695 renesas,ipmmu-main = <&ipmmu_mm 0>;
1239 power-domains = <&sys 696 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
1240 #iommu-cells = <1>; 697 #iommu-cells = <1>;
1241 }; 698 };
1242 699
1243 ipmmu_hc: iommu@eed40000 { 700 ipmmu_hc: iommu@eed40000 {
1244 compatible = "renesas 701 compatible = "renesas,ipmmu-r8a779f0",
1245 "renesas 702 "renesas,rcar-gen4-ipmmu-vmsa";
1246 reg = <0 0xeed40000 0 703 reg = <0 0xeed40000 0 0x20000>;
1247 renesas,ipmmu-main = !! 704 renesas,ipmmu-main = <&ipmmu_mm 2>;
1248 power-domains = <&sys 705 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
1249 #iommu-cells = <1>; 706 #iommu-cells = <1>;
1250 }; 707 };
1251 708
1252 ipmmu_mm: iommu@eefc0000 { 709 ipmmu_mm: iommu@eefc0000 {
1253 compatible = "renesas 710 compatible = "renesas,ipmmu-r8a779f0",
1254 "renesas 711 "renesas,rcar-gen4-ipmmu-vmsa";
1255 reg = <0 0xeefc0000 0 712 reg = <0 0xeefc0000 0 0x20000>;
1256 interrupts = <GIC_SPI 713 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
1257 <GIC_SPI 714 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
1258 power-domains = <&sys 715 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
1259 #iommu-cells = <1>; 716 #iommu-cells = <1>;
1260 }; 717 };
1261 718
1262 gic: interrupt-controller@f10 719 gic: interrupt-controller@f1000000 {
1263 compatible = "arm,gic 720 compatible = "arm,gic-v3";
1264 #interrupt-cells = <3 721 #interrupt-cells = <3>;
1265 #address-cells = <0>; 722 #address-cells = <0>;
1266 interrupt-controller; 723 interrupt-controller;
1267 reg = <0x0 0xf1000000 724 reg = <0x0 0xf1000000 0 0x20000>,
1268 <0x0 0xf1060000 725 <0x0 0xf1060000 0 0x110000>;
1269 interrupts = <GIC_PPI !! 726 interrupts = <GIC_PPI 9
>> 727 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
1270 }; 728 };
1271 729
1272 prr: chipid@fff00044 { 730 prr: chipid@fff00044 {
1273 compatible = "renesas 731 compatible = "renesas,prr";
1274 reg = <0 0xfff00044 0 732 reg = <0 0xfff00044 0 4>;
1275 }; 733 };
1276 }; 734 };
1277 735
1278 thermal-zones { 736 thermal-zones {
1279 sensor_thermal_rtcore: sensor !! 737 sensor_thermal1: sensor1-thermal {
1280 polling-delay-passive 738 polling-delay-passive = <250>;
1281 polling-delay = <1000 739 polling-delay = <1000>;
1282 thermal-sensors = <&t 740 thermal-sensors = <&tsc 0>;
1283 741
1284 trips { 742 trips {
1285 sensor1_crit: 743 sensor1_crit: sensor1-crit {
1286 tempe 744 temperature = <120000>;
1287 hyste 745 hysteresis = <1000>;
1288 type 746 type = "critical";
1289 }; 747 };
1290 }; 748 };
1291 }; 749 };
1292 750
1293 sensor_thermal_apcore0: senso !! 751 sensor_thermal2: sensor2-thermal {
1294 polling-delay-passive 752 polling-delay-passive = <250>;
1295 polling-delay = <1000 753 polling-delay = <1000>;
1296 thermal-sensors = <&t 754 thermal-sensors = <&tsc 1>;
1297 755
1298 trips { 756 trips {
1299 sensor2_crit: 757 sensor2_crit: sensor2-crit {
1300 tempe 758 temperature = <120000>;
1301 hyste 759 hysteresis = <1000>;
1302 type 760 type = "critical";
1303 }; 761 };
1304 }; 762 };
1305 }; 763 };
1306 764
1307 sensor_thermal_apcore4: senso !! 765 sensor_thermal3: sensor3-thermal {
1308 polling-delay-passive 766 polling-delay-passive = <250>;
1309 polling-delay = <1000 767 polling-delay = <1000>;
1310 thermal-sensors = <&t 768 thermal-sensors = <&tsc 2>;
1311 769
1312 trips { 770 trips {
1313 sensor3_crit: 771 sensor3_crit: sensor3-crit {
1314 tempe 772 temperature = <120000>;
1315 hyste 773 hysteresis = <1000>;
1316 type 774 type = "critical";
1317 }; 775 };
1318 }; 776 };
1319 }; 777 };
1320 }; 778 };
1321 779
1322 timer { 780 timer {
1323 compatible = "arm,armv8-timer 781 compatible = "arm,armv8-timer";
1324 interrupts-extended = <&gic G !! 782 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
1325 <&gic G !! 783 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
1326 <&gic G !! 784 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
1327 <&gic G !! 785 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
1328 <&gic G <<
1329 interrupt-names = "sec-phys", <<
1330 "hyp-virt"; <<
1331 }; 786 };
1332 787
1333 ufs30_clk: ufs30-clk { 788 ufs30_clk: ufs30-clk {
1334 compatible = "fixed-clock"; 789 compatible = "fixed-clock";
1335 #clock-cells = <0>; 790 #clock-cells = <0>;
1336 /* This value must be overrid 791 /* This value must be overridden by the board */
1337 clock-frequency = <0>; 792 clock-frequency = <0>;
1338 }; 793 };
1339 }; 794 };
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