1 // SPDX-License-Identifier: (GPL-2.0 OR MIT) !! 1 // SPDX-License-Identifier: (GPL-2.0 or MIT)
2 /* 2 /*
3 * Device Tree Source for the R-Car S4-8 (R8A7 3 * Device Tree Source for the R-Car S4-8 (R8A779F0) SoC
4 * 4 *
5 * Copyright (C) 2021 Renesas Electronics Corp 5 * Copyright (C) 2021 Renesas Electronics Corp.
6 */ 6 */
7 7
8 #include <dt-bindings/clock/r8a779f0-cpg-mssr. 8 #include <dt-bindings/clock/r8a779f0-cpg-mssr.h>
9 #include <dt-bindings/interrupt-controller/arm 9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/power/r8a779f0-sysc.h> 10 #include <dt-bindings/power/r8a779f0-sysc.h>
11 11
12 / { 12 / {
13 compatible = "renesas,r8a779f0"; 13 compatible = "renesas,r8a779f0";
14 #address-cells = <2>; 14 #address-cells = <2>;
15 #size-cells = <2>; 15 #size-cells = <2>;
16 16
17 cluster01_opp: opp-table-0 { <<
18 compatible = "operating-points <<
19 opp-shared; <<
20 <<
21 opp-500000000 { <<
22 opp-hz = /bits/ 64 <50 <<
23 opp-microvolt = <88000 <<
24 clock-latency-ns = <50 <<
25 }; <<
26 opp-800000000 { <<
27 opp-hz = /bits/ 64 <80 <<
28 opp-microvolt = <88000 <<
29 clock-latency-ns = <50 <<
30 }; <<
31 opp-1000000000 { <<
32 opp-hz = /bits/ 64 <10 <<
33 opp-microvolt = <88000 <<
34 clock-latency-ns = <50 <<
35 }; <<
36 opp-1200000000 { <<
37 opp-hz = /bits/ 64 <12 <<
38 opp-microvolt = <88000 <<
39 clock-latency-ns = <50 <<
40 opp-suspend; <<
41 }; <<
42 }; <<
43 <<
44 cluster23_opp: opp-table-1 { <<
45 compatible = "operating-points <<
46 opp-shared; <<
47 <<
48 opp-500000000 { <<
49 opp-hz = /bits/ 64 <50 <<
50 opp-microvolt = <88000 <<
51 clock-latency-ns = <50 <<
52 }; <<
53 opp-800000000 { <<
54 opp-hz = /bits/ 64 <80 <<
55 opp-microvolt = <88000 <<
56 clock-latency-ns = <50 <<
57 }; <<
58 opp-1000000000 { <<
59 opp-hz = /bits/ 64 <10 <<
60 opp-microvolt = <88000 <<
61 clock-latency-ns = <50 <<
62 }; <<
63 opp-1200000000 { <<
64 opp-hz = /bits/ 64 <12 <<
65 opp-microvolt = <88000 <<
66 clock-latency-ns = <50 <<
67 opp-suspend; <<
68 }; <<
69 }; <<
70 <<
71 cpus { 17 cpus {
72 #address-cells = <1>; 18 #address-cells = <1>;
73 #size-cells = <0>; 19 #size-cells = <0>;
74 20
75 cpu-map { 21 cpu-map {
76 cluster0 { 22 cluster0 {
77 core0 { 23 core0 {
78 cpu = 24 cpu = <&a55_0>;
79 }; 25 };
80 core1 { 26 core1 {
81 cpu = 27 cpu = <&a55_1>;
82 }; 28 };
83 }; 29 };
84 30
85 cluster1 { 31 cluster1 {
86 core0 { 32 core0 {
87 cpu = 33 cpu = <&a55_2>;
88 }; 34 };
89 core1 { 35 core1 {
90 cpu = 36 cpu = <&a55_3>;
91 }; 37 };
92 }; 38 };
93 39
94 cluster2 { 40 cluster2 {
95 core0 { 41 core0 {
96 cpu = 42 cpu = <&a55_4>;
97 }; 43 };
98 core1 { 44 core1 {
99 cpu = 45 cpu = <&a55_5>;
100 }; 46 };
101 }; 47 };
102 48
103 cluster3 { 49 cluster3 {
104 core0 { 50 core0 {
105 cpu = 51 cpu = <&a55_6>;
106 }; 52 };
107 core1 { 53 core1 {
108 cpu = 54 cpu = <&a55_7>;
109 }; 55 };
110 }; 56 };
111 }; 57 };
112 58
113 a55_0: cpu@0 { 59 a55_0: cpu@0 {
114 compatible = "arm,cort 60 compatible = "arm,cortex-a55";
115 reg = <0>; 61 reg = <0>;
116 device_type = "cpu"; 62 device_type = "cpu";
117 power-domains = <&sysc 63 power-domains = <&sysc R8A779F0_PD_A1E0D0C0>;
118 next-level-cache = <&L 64 next-level-cache = <&L3_CA55_0>;
119 enable-method = "psci" 65 enable-method = "psci";
120 cpu-idle-states = <&CP 66 cpu-idle-states = <&CPU_SLEEP_0>;
121 clocks = <&cpg CPG_COR 67 clocks = <&cpg CPG_CORE R8A779F0_CLK_Z0>;
122 operating-points-v2 = <<
123 }; 68 };
124 69
125 a55_1: cpu@100 { 70 a55_1: cpu@100 {
126 compatible = "arm,cort 71 compatible = "arm,cortex-a55";
127 reg = <0x100>; 72 reg = <0x100>;
128 device_type = "cpu"; 73 device_type = "cpu";
129 power-domains = <&sysc 74 power-domains = <&sysc R8A779F0_PD_A1E0D0C1>;
130 next-level-cache = <&L 75 next-level-cache = <&L3_CA55_0>;
131 enable-method = "psci" 76 enable-method = "psci";
132 cpu-idle-states = <&CP 77 cpu-idle-states = <&CPU_SLEEP_0>;
133 clocks = <&cpg CPG_COR 78 clocks = <&cpg CPG_CORE R8A779F0_CLK_Z0>;
134 operating-points-v2 = <<
135 }; 79 };
136 80
137 a55_2: cpu@10000 { 81 a55_2: cpu@10000 {
138 compatible = "arm,cort 82 compatible = "arm,cortex-a55";
139 reg = <0x10000>; 83 reg = <0x10000>;
140 device_type = "cpu"; 84 device_type = "cpu";
141 power-domains = <&sysc 85 power-domains = <&sysc R8A779F0_PD_A1E0D1C0>;
142 next-level-cache = <&L 86 next-level-cache = <&L3_CA55_1>;
143 enable-method = "psci" 87 enable-method = "psci";
144 cpu-idle-states = <&CP 88 cpu-idle-states = <&CPU_SLEEP_0>;
145 clocks = <&cpg CPG_COR 89 clocks = <&cpg CPG_CORE R8A779F0_CLK_Z0>;
146 operating-points-v2 = <<
147 }; 90 };
148 91
149 a55_3: cpu@10100 { 92 a55_3: cpu@10100 {
150 compatible = "arm,cort 93 compatible = "arm,cortex-a55";
151 reg = <0x10100>; 94 reg = <0x10100>;
152 device_type = "cpu"; 95 device_type = "cpu";
153 power-domains = <&sysc 96 power-domains = <&sysc R8A779F0_PD_A1E0D1C1>;
154 next-level-cache = <&L 97 next-level-cache = <&L3_CA55_1>;
155 enable-method = "psci" 98 enable-method = "psci";
156 cpu-idle-states = <&CP 99 cpu-idle-states = <&CPU_SLEEP_0>;
157 clocks = <&cpg CPG_COR 100 clocks = <&cpg CPG_CORE R8A779F0_CLK_Z0>;
158 operating-points-v2 = <<
159 }; 101 };
160 102
161 a55_4: cpu@20000 { 103 a55_4: cpu@20000 {
162 compatible = "arm,cort 104 compatible = "arm,cortex-a55";
163 reg = <0x20000>; 105 reg = <0x20000>;
164 device_type = "cpu"; 106 device_type = "cpu";
165 power-domains = <&sysc 107 power-domains = <&sysc R8A779F0_PD_A1E1D0C0>;
166 next-level-cache = <&L 108 next-level-cache = <&L3_CA55_2>;
167 enable-method = "psci" 109 enable-method = "psci";
168 cpu-idle-states = <&CP 110 cpu-idle-states = <&CPU_SLEEP_0>;
169 clocks = <&cpg CPG_COR 111 clocks = <&cpg CPG_CORE R8A779F0_CLK_Z1>;
170 operating-points-v2 = <<
171 }; 112 };
172 113
173 a55_5: cpu@20100 { 114 a55_5: cpu@20100 {
174 compatible = "arm,cort 115 compatible = "arm,cortex-a55";
175 reg = <0x20100>; 116 reg = <0x20100>;
176 device_type = "cpu"; 117 device_type = "cpu";
177 power-domains = <&sysc 118 power-domains = <&sysc R8A779F0_PD_A1E1D0C1>;
178 next-level-cache = <&L 119 next-level-cache = <&L3_CA55_2>;
179 enable-method = "psci" 120 enable-method = "psci";
180 cpu-idle-states = <&CP 121 cpu-idle-states = <&CPU_SLEEP_0>;
181 clocks = <&cpg CPG_COR 122 clocks = <&cpg CPG_CORE R8A779F0_CLK_Z1>;
182 operating-points-v2 = <<
183 }; 123 };
184 124
185 a55_6: cpu@30000 { 125 a55_6: cpu@30000 {
186 compatible = "arm,cort 126 compatible = "arm,cortex-a55";
187 reg = <0x30000>; 127 reg = <0x30000>;
188 device_type = "cpu"; 128 device_type = "cpu";
189 power-domains = <&sysc 129 power-domains = <&sysc R8A779F0_PD_A1E1D1C0>;
190 next-level-cache = <&L 130 next-level-cache = <&L3_CA55_3>;
191 enable-method = "psci" 131 enable-method = "psci";
192 cpu-idle-states = <&CP 132 cpu-idle-states = <&CPU_SLEEP_0>;
193 clocks = <&cpg CPG_COR 133 clocks = <&cpg CPG_CORE R8A779F0_CLK_Z1>;
194 operating-points-v2 = <<
195 }; 134 };
196 135
197 a55_7: cpu@30100 { 136 a55_7: cpu@30100 {
198 compatible = "arm,cort 137 compatible = "arm,cortex-a55";
199 reg = <0x30100>; 138 reg = <0x30100>;
200 device_type = "cpu"; 139 device_type = "cpu";
201 power-domains = <&sysc 140 power-domains = <&sysc R8A779F0_PD_A1E1D1C1>;
202 next-level-cache = <&L 141 next-level-cache = <&L3_CA55_3>;
203 enable-method = "psci" 142 enable-method = "psci";
204 cpu-idle-states = <&CP 143 cpu-idle-states = <&CPU_SLEEP_0>;
205 clocks = <&cpg CPG_COR 144 clocks = <&cpg CPG_CORE R8A779F0_CLK_Z1>;
206 operating-points-v2 = <<
207 }; 145 };
208 146
209 L3_CA55_0: cache-controller-0 147 L3_CA55_0: cache-controller-0 {
210 compatible = "cache"; 148 compatible = "cache";
211 power-domains = <&sysc 149 power-domains = <&sysc R8A779F0_PD_A2E0D0>;
212 cache-unified; 150 cache-unified;
213 cache-level = <3>; 151 cache-level = <3>;
214 }; 152 };
215 153
216 L3_CA55_1: cache-controller-1 154 L3_CA55_1: cache-controller-1 {
217 compatible = "cache"; 155 compatible = "cache";
218 power-domains = <&sysc 156 power-domains = <&sysc R8A779F0_PD_A2E0D1>;
219 cache-unified; 157 cache-unified;
220 cache-level = <3>; 158 cache-level = <3>;
221 }; 159 };
222 160
223 L3_CA55_2: cache-controller-2 161 L3_CA55_2: cache-controller-2 {
224 compatible = "cache"; 162 compatible = "cache";
225 power-domains = <&sysc 163 power-domains = <&sysc R8A779F0_PD_A2E1D0>;
226 cache-unified; 164 cache-unified;
227 cache-level = <3>; 165 cache-level = <3>;
228 }; 166 };
229 167
230 L3_CA55_3: cache-controller-3 168 L3_CA55_3: cache-controller-3 {
231 compatible = "cache"; 169 compatible = "cache";
232 power-domains = <&sysc 170 power-domains = <&sysc R8A779F0_PD_A2E1D1>;
233 cache-unified; 171 cache-unified;
234 cache-level = <3>; 172 cache-level = <3>;
235 }; 173 };
236 174
237 idle-states { 175 idle-states {
238 entry-method = "psci"; 176 entry-method = "psci";
239 177
240 CPU_SLEEP_0: cpu-sleep 178 CPU_SLEEP_0: cpu-sleep-0 {
241 compatible = " 179 compatible = "arm,idle-state";
242 arm,psci-suspe 180 arm,psci-suspend-param = <0x0010000>;
243 local-timer-st 181 local-timer-stop;
244 entry-latency- 182 entry-latency-us = <400>;
245 exit-latency-u 183 exit-latency-us = <500>;
246 min-residency- 184 min-residency-us = <4000>;
247 }; 185 };
248 }; 186 };
249 }; 187 };
250 188
251 extal_clk: extal { 189 extal_clk: extal {
252 compatible = "fixed-clock"; 190 compatible = "fixed-clock";
253 #clock-cells = <0>; 191 #clock-cells = <0>;
254 /* This value must be overridd 192 /* This value must be overridden by the board */
255 clock-frequency = <0>; 193 clock-frequency = <0>;
256 }; 194 };
257 195
258 extalr_clk: extalr { 196 extalr_clk: extalr {
259 compatible = "fixed-clock"; 197 compatible = "fixed-clock";
260 #clock-cells = <0>; 198 #clock-cells = <0>;
261 /* This value must be overridd 199 /* This value must be overridden by the board */
262 clock-frequency = <0>; 200 clock-frequency = <0>;
263 }; 201 };
264 202
265 pcie0_clkref: pcie0-clkref { <<
266 compatible = "fixed-clock"; <<
267 #clock-cells = <0>; <<
268 /* This value must be overridd <<
269 clock-frequency = <0>; <<
270 }; <<
271 <<
272 pcie1_clkref: pcie1-clkref { <<
273 compatible = "fixed-clock"; <<
274 #clock-cells = <0>; <<
275 /* This value must be overridd <<
276 clock-frequency = <0>; <<
277 }; <<
278 <<
279 pmu_a55 { 203 pmu_a55 {
280 compatible = "arm,cortex-a55-p 204 compatible = "arm,cortex-a55-pmu";
281 interrupts-extended = <&gic GI 205 interrupts-extended = <&gic GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
282 }; 206 };
283 207
284 psci { 208 psci {
285 compatible = "arm,psci-1.0", " 209 compatible = "arm,psci-1.0", "arm,psci-0.2";
286 method = "smc"; 210 method = "smc";
287 }; 211 };
288 212
289 /* External SCIF clock - to be overrid 213 /* External SCIF clock - to be overridden by boards that provide it */
290 scif_clk: scif { 214 scif_clk: scif {
291 compatible = "fixed-clock"; 215 compatible = "fixed-clock";
292 #clock-cells = <0>; 216 #clock-cells = <0>;
293 clock-frequency = <0>; 217 clock-frequency = <0>;
294 }; 218 };
295 219
296 soc: soc { 220 soc: soc {
297 compatible = "simple-bus"; 221 compatible = "simple-bus";
298 interrupt-parent = <&gic>; 222 interrupt-parent = <&gic>;
299 #address-cells = <2>; 223 #address-cells = <2>;
300 #size-cells = <2>; 224 #size-cells = <2>;
301 ranges; 225 ranges;
302 226
303 rwdt: watchdog@e6020000 { 227 rwdt: watchdog@e6020000 {
304 compatible = "renesas, 228 compatible = "renesas,r8a779f0-wdt",
305 "renesas, 229 "renesas,rcar-gen4-wdt";
306 reg = <0 0xe6020000 0 230 reg = <0 0xe6020000 0 0x0c>;
307 interrupts = <GIC_SPI 231 interrupts = <GIC_SPI 515 IRQ_TYPE_LEVEL_HIGH>;
308 clocks = <&cpg CPG_MOD 232 clocks = <&cpg CPG_MOD 907>;
309 power-domains = <&sysc 233 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
310 resets = <&cpg 907>; 234 resets = <&cpg 907>;
311 status = "disabled"; 235 status = "disabled";
312 }; 236 };
313 237
314 pfc: pinctrl@e6050000 { 238 pfc: pinctrl@e6050000 {
315 compatible = "renesas, 239 compatible = "renesas,pfc-r8a779f0";
316 reg = <0 0xe6050000 0 240 reg = <0 0xe6050000 0 0x16c>, <0 0xe6050800 0 0x16c>,
317 <0 0xe6051000 0 241 <0 0xe6051000 0 0x16c>, <0 0xe6051800 0 0x16c>;
318 }; 242 };
319 243
320 gpio0: gpio@e6050180 { 244 gpio0: gpio@e6050180 {
321 compatible = "renesas, 245 compatible = "renesas,gpio-r8a779f0",
322 "renesas, 246 "renesas,rcar-gen4-gpio";
323 reg = <0 0xe6050180 0 247 reg = <0 0xe6050180 0 0x54>;
324 interrupts = <GIC_SPI 248 interrupts = <GIC_SPI 822 IRQ_TYPE_LEVEL_HIGH>;
325 clocks = <&cpg CPG_MOD 249 clocks = <&cpg CPG_MOD 915>;
326 power-domains = <&sysc 250 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
327 resets = <&cpg 915>; 251 resets = <&cpg 915>;
328 gpio-controller; 252 gpio-controller;
329 #gpio-cells = <2>; 253 #gpio-cells = <2>;
330 gpio-ranges = <&pfc 0 254 gpio-ranges = <&pfc 0 0 21>;
331 interrupt-controller; 255 interrupt-controller;
332 #interrupt-cells = <2> 256 #interrupt-cells = <2>;
333 }; 257 };
334 258
335 gpio1: gpio@e6050980 { 259 gpio1: gpio@e6050980 {
336 compatible = "renesas, 260 compatible = "renesas,gpio-r8a779f0",
337 "renesas, 261 "renesas,rcar-gen4-gpio";
338 reg = <0 0xe6050980 0 262 reg = <0 0xe6050980 0 0x54>;
339 interrupts = <GIC_SPI 263 interrupts = <GIC_SPI 823 IRQ_TYPE_LEVEL_HIGH>;
340 clocks = <&cpg CPG_MOD 264 clocks = <&cpg CPG_MOD 915>;
341 power-domains = <&sysc 265 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
342 resets = <&cpg 915>; 266 resets = <&cpg 915>;
343 gpio-controller; 267 gpio-controller;
344 #gpio-cells = <2>; 268 #gpio-cells = <2>;
345 gpio-ranges = <&pfc 0 269 gpio-ranges = <&pfc 0 32 25>;
346 interrupt-controller; 270 interrupt-controller;
347 #interrupt-cells = <2> 271 #interrupt-cells = <2>;
348 }; 272 };
349 273
350 gpio2: gpio@e6051180 { 274 gpio2: gpio@e6051180 {
351 compatible = "renesas, 275 compatible = "renesas,gpio-r8a779f0",
352 "renesas, 276 "renesas,rcar-gen4-gpio";
353 reg = <0 0xe6051180 0 277 reg = <0 0xe6051180 0 0x54>;
354 interrupts = <GIC_SPI 278 interrupts = <GIC_SPI 824 IRQ_TYPE_LEVEL_HIGH>;
355 clocks = <&cpg CPG_MOD 279 clocks = <&cpg CPG_MOD 915>;
356 power-domains = <&sysc 280 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
357 resets = <&cpg 915>; 281 resets = <&cpg 915>;
358 gpio-controller; 282 gpio-controller;
359 #gpio-cells = <2>; 283 #gpio-cells = <2>;
360 gpio-ranges = <&pfc 0 284 gpio-ranges = <&pfc 0 64 17>;
361 interrupt-controller; 285 interrupt-controller;
362 #interrupt-cells = <2> 286 #interrupt-cells = <2>;
363 }; 287 };
364 288
365 gpio3: gpio@e6051980 { 289 gpio3: gpio@e6051980 {
366 compatible = "renesas, 290 compatible = "renesas,gpio-r8a779f0",
367 "renesas, 291 "renesas,rcar-gen4-gpio";
368 reg = <0 0xe6051980 0 292 reg = <0 0xe6051980 0 0x54>;
369 interrupts = <GIC_SPI 293 interrupts = <GIC_SPI 825 IRQ_TYPE_LEVEL_HIGH>;
370 clocks = <&cpg CPG_MOD 294 clocks = <&cpg CPG_MOD 915>;
371 power-domains = <&sysc 295 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
372 resets = <&cpg 915>; 296 resets = <&cpg 915>;
373 gpio-controller; 297 gpio-controller;
374 #gpio-cells = <2>; 298 #gpio-cells = <2>;
375 gpio-ranges = <&pfc 0 299 gpio-ranges = <&pfc 0 96 19>;
376 interrupt-controller; 300 interrupt-controller;
377 #interrupt-cells = <2> 301 #interrupt-cells = <2>;
378 }; 302 };
379 303
380 cmt0: timer@e60f0000 { 304 cmt0: timer@e60f0000 {
381 compatible = "renesas, 305 compatible = "renesas,r8a779f0-cmt0",
382 "renesas, 306 "renesas,rcar-gen4-cmt0";
383 reg = <0 0xe60f0000 0 307 reg = <0 0xe60f0000 0 0x1004>;
384 interrupts = <GIC_SPI 308 interrupts = <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>,
385 <GIC_SPI 309 <GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>;
386 clocks = <&cpg CPG_MOD 310 clocks = <&cpg CPG_MOD 910>;
387 clock-names = "fck"; 311 clock-names = "fck";
388 power-domains = <&sysc 312 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
389 resets = <&cpg 910>; 313 resets = <&cpg 910>;
390 status = "disabled"; 314 status = "disabled";
391 }; 315 };
392 316
393 cmt1: timer@e6130000 { 317 cmt1: timer@e6130000 {
394 compatible = "renesas, 318 compatible = "renesas,r8a779f0-cmt1",
395 "renesas, 319 "renesas,rcar-gen4-cmt1";
396 reg = <0 0xe6130000 0 320 reg = <0 0xe6130000 0 0x1004>;
397 interrupts = <GIC_SPI 321 interrupts = <GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH>,
398 <GIC_SPI 322 <GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>,
399 <GIC_SPI 323 <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>,
400 <GIC_SPI 324 <GIC_SPI 453 IRQ_TYPE_LEVEL_HIGH>,
401 <GIC_SPI 325 <GIC_SPI 454 IRQ_TYPE_LEVEL_HIGH>,
402 <GIC_SPI 326 <GIC_SPI 455 IRQ_TYPE_LEVEL_HIGH>,
403 <GIC_SPI 327 <GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>,
404 <GIC_SPI 328 <GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>;
405 clocks = <&cpg CPG_MOD 329 clocks = <&cpg CPG_MOD 911>;
406 clock-names = "fck"; 330 clock-names = "fck";
407 power-domains = <&sysc 331 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
408 resets = <&cpg 911>; 332 resets = <&cpg 911>;
409 status = "disabled"; 333 status = "disabled";
410 }; 334 };
411 335
412 cmt2: timer@e6140000 { 336 cmt2: timer@e6140000 {
413 compatible = "renesas, 337 compatible = "renesas,r8a779f0-cmt1",
414 "renesas, 338 "renesas,rcar-gen4-cmt1";
415 reg = <0 0xe6140000 0 339 reg = <0 0xe6140000 0 0x1004>;
416 interrupts = <GIC_SPI 340 interrupts = <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>,
417 <GIC_SPI 341 <GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>,
418 <GIC_SPI 342 <GIC_SPI 460 IRQ_TYPE_LEVEL_HIGH>,
419 <GIC_SPI 343 <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>,
420 <GIC_SPI 344 <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>,
421 <GIC_SPI 345 <GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH>,
422 <GIC_SPI 346 <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>,
423 <GIC_SPI 347 <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>;
424 clocks = <&cpg CPG_MOD 348 clocks = <&cpg CPG_MOD 912>;
425 clock-names = "fck"; 349 clock-names = "fck";
426 power-domains = <&sysc 350 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
427 resets = <&cpg 912>; 351 resets = <&cpg 912>;
428 status = "disabled"; 352 status = "disabled";
429 }; 353 };
430 354
431 cmt3: timer@e6148000 { 355 cmt3: timer@e6148000 {
432 compatible = "renesas, 356 compatible = "renesas,r8a779f0-cmt1",
433 "renesas, 357 "renesas,rcar-gen4-cmt1";
434 reg = <0 0xe6148000 0 358 reg = <0 0xe6148000 0 0x1004>;
435 interrupts = <GIC_SPI 359 interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>,
436 <GIC_SPI 360 <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>,
437 <GIC_SPI 361 <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>,
438 <GIC_SPI 362 <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>,
439 <GIC_SPI 363 <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>,
440 <GIC_SPI 364 <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>,
441 <GIC_SPI 365 <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>,
442 <GIC_SPI 366 <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>;
443 clocks = <&cpg CPG_MOD 367 clocks = <&cpg CPG_MOD 913>;
444 clock-names = "fck"; 368 clock-names = "fck";
445 power-domains = <&sysc 369 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
446 resets = <&cpg 913>; 370 resets = <&cpg 913>;
447 status = "disabled"; 371 status = "disabled";
448 }; 372 };
449 373
450 cpg: clock-controller@e6150000 374 cpg: clock-controller@e6150000 {
451 compatible = "renesas, 375 compatible = "renesas,r8a779f0-cpg-mssr";
452 reg = <0 0xe6150000 0 376 reg = <0 0xe6150000 0 0x4000>;
453 clocks = <&extal_clk>, 377 clocks = <&extal_clk>, <&extalr_clk>;
454 clock-names = "extal", 378 clock-names = "extal", "extalr";
455 #clock-cells = <2>; 379 #clock-cells = <2>;
456 #power-domain-cells = 380 #power-domain-cells = <0>;
457 #reset-cells = <1>; 381 #reset-cells = <1>;
458 }; 382 };
459 383
460 rst: reset-controller@e6160000 384 rst: reset-controller@e6160000 {
461 compatible = "renesas, 385 compatible = "renesas,r8a779f0-rst";
462 reg = <0 0xe6160000 0 386 reg = <0 0xe6160000 0 0x4000>;
463 }; 387 };
464 388
465 sysc: system-controller@e61800 389 sysc: system-controller@e6180000 {
466 compatible = "renesas, 390 compatible = "renesas,r8a779f0-sysc";
467 reg = <0 0xe6180000 0 391 reg = <0 0xe6180000 0 0x4000>;
468 #power-domain-cells = 392 #power-domain-cells = <1>;
469 }; 393 };
470 394
471 tsc: thermal@e6198000 { 395 tsc: thermal@e6198000 {
472 compatible = "renesas, 396 compatible = "renesas,r8a779f0-thermal";
473 /* The 4th sensor is i 397 /* The 4th sensor is in control domain and not for Linux */
474 reg = <0 0xe6198000 0 398 reg = <0 0xe6198000 0 0x200>,
475 <0 0xe61a0000 0 399 <0 0xe61a0000 0 0x200>,
476 <0 0xe61a8000 0 400 <0 0xe61a8000 0 0x200>;
477 clocks = <&cpg CPG_MOD 401 clocks = <&cpg CPG_MOD 919>;
478 power-domains = <&sysc 402 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
479 resets = <&cpg 919>; 403 resets = <&cpg 919>;
480 #thermal-sensor-cells 404 #thermal-sensor-cells = <1>;
481 }; 405 };
482 406
483 intc_ex: interrupt-controller@ <<
484 compatible = "renesas, <<
485 #interrupt-cells = <2> <<
486 interrupt-controller; <<
487 reg = <0 0xe61c0000 0 <<
488 interrupts = <GIC_SPI <<
489 <GIC_SPI <<
490 <GIC_SPI <<
491 <GIC_SPI <<
492 <GIC_SPI <<
493 <GIC_SPI <<
494 clocks = <&cpg CPG_COR <<
495 power-domains = <&sysc <<
496 }; <<
497 <<
498 tmu0: timer@e61e0000 { 407 tmu0: timer@e61e0000 {
499 compatible = "renesas, 408 compatible = "renesas,tmu-r8a779f0", "renesas,tmu";
500 reg = <0 0xe61e0000 0 409 reg = <0 0xe61e0000 0 0x30>;
501 interrupts = <GIC_SPI 410 interrupts = <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>,
502 <GIC_SPI 411 <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>,
503 <GIC_SPI 412 <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>;
504 interrupt-names = "tun <<
505 clocks = <&cpg CPG_MOD 413 clocks = <&cpg CPG_MOD 713>;
506 clock-names = "fck"; 414 clock-names = "fck";
507 power-domains = <&sysc 415 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
508 resets = <&cpg 713>; 416 resets = <&cpg 713>;
509 status = "disabled"; 417 status = "disabled";
510 }; 418 };
511 419
512 tmu1: timer@e6fc0000 { 420 tmu1: timer@e6fc0000 {
513 compatible = "renesas, 421 compatible = "renesas,tmu-r8a779f0", "renesas,tmu";
514 reg = <0 0xe6fc0000 0 422 reg = <0 0xe6fc0000 0 0x30>;
515 interrupts = <GIC_SPI 423 interrupts = <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>,
516 <GIC_SPI 424 <GIC_SPI 478 IRQ_TYPE_LEVEL_HIGH>,
517 <GIC_SPI !! 425 <GIC_SPI 479 IRQ_TYPE_LEVEL_HIGH>;
518 <GIC_SPI <<
519 interrupt-names = "tun <<
520 clocks = <&cpg CPG_MOD 426 clocks = <&cpg CPG_MOD 714>;
521 clock-names = "fck"; 427 clock-names = "fck";
522 power-domains = <&sysc 428 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
523 resets = <&cpg 714>; 429 resets = <&cpg 714>;
524 status = "disabled"; 430 status = "disabled";
525 }; 431 };
526 432
527 tmu2: timer@e6fd0000 { 433 tmu2: timer@e6fd0000 {
528 compatible = "renesas, 434 compatible = "renesas,tmu-r8a779f0", "renesas,tmu";
529 reg = <0 0xe6fd0000 0 435 reg = <0 0xe6fd0000 0 0x30>;
530 interrupts = <GIC_SPI 436 interrupts = <GIC_SPI 481 IRQ_TYPE_LEVEL_HIGH>,
531 <GIC_SPI 437 <GIC_SPI 482 IRQ_TYPE_LEVEL_HIGH>,
532 <GIC_SPI !! 438 <GIC_SPI 483 IRQ_TYPE_LEVEL_HIGH>;
533 <GIC_SPI <<
534 interrupt-names = "tun <<
535 clocks = <&cpg CPG_MOD 439 clocks = <&cpg CPG_MOD 715>;
536 clock-names = "fck"; 440 clock-names = "fck";
537 power-domains = <&sysc 441 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
538 resets = <&cpg 715>; 442 resets = <&cpg 715>;
539 status = "disabled"; 443 status = "disabled";
540 }; 444 };
541 445
542 tmu3: timer@e6fe0000 { 446 tmu3: timer@e6fe0000 {
543 compatible = "renesas, 447 compatible = "renesas,tmu-r8a779f0", "renesas,tmu";
544 reg = <0 0xe6fe0000 0 448 reg = <0 0xe6fe0000 0 0x30>;
545 interrupts = <GIC_SPI 449 interrupts = <GIC_SPI 485 IRQ_TYPE_LEVEL_HIGH>,
546 <GIC_SPI 450 <GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>,
547 <GIC_SPI !! 451 <GIC_SPI 487 IRQ_TYPE_LEVEL_HIGH>;
548 <GIC_SPI <<
549 interrupt-names = "tun <<
550 clocks = <&cpg CPG_MOD 452 clocks = <&cpg CPG_MOD 716>;
551 clock-names = "fck"; 453 clock-names = "fck";
552 power-domains = <&sysc 454 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
553 resets = <&cpg 716>; 455 resets = <&cpg 716>;
554 status = "disabled"; 456 status = "disabled";
555 }; 457 };
556 458
557 tmu4: timer@ffc00000 { 459 tmu4: timer@ffc00000 {
558 compatible = "renesas, 460 compatible = "renesas,tmu-r8a779f0", "renesas,tmu";
559 reg = <0 0xffc00000 0 461 reg = <0 0xffc00000 0 0x30>;
560 interrupts = <GIC_SPI 462 interrupts = <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>,
561 <GIC_SPI 463 <GIC_SPI 490 IRQ_TYPE_LEVEL_HIGH>,
562 <GIC_SPI !! 464 <GIC_SPI 491 IRQ_TYPE_LEVEL_HIGH>;
563 <GIC_SPI <<
564 interrupt-names = "tun <<
565 clocks = <&cpg CPG_MOD 465 clocks = <&cpg CPG_MOD 717>;
566 clock-names = "fck"; 466 clock-names = "fck";
567 power-domains = <&sysc 467 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
568 resets = <&cpg 717>; 468 resets = <&cpg 717>;
569 status = "disabled"; 469 status = "disabled";
570 }; 470 };
571 471
572 eth_serdes: phy@e6444000 { <<
573 compatible = "renesas, <<
574 reg = <0 0xe6444000 0 <<
575 clocks = <&cpg CPG_MOD <<
576 power-domains = <&sysc <<
577 resets = <&cpg 1506>; <<
578 #phy-cells = <1>; <<
579 status = "disabled"; <<
580 }; <<
581 <<
582 i2c0: i2c@e6500000 { 472 i2c0: i2c@e6500000 {
583 compatible = "renesas, 473 compatible = "renesas,i2c-r8a779f0",
584 "renesas, 474 "renesas,rcar-gen4-i2c";
585 reg = <0 0xe6500000 0 475 reg = <0 0xe6500000 0 0x40>;
586 interrupts = <GIC_SPI 476 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
587 clocks = <&cpg CPG_MOD 477 clocks = <&cpg CPG_MOD 518>;
588 power-domains = <&sysc 478 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
589 resets = <&cpg 518>; 479 resets = <&cpg 518>;
590 dmas = <&dmac0 0x91>, 480 dmas = <&dmac0 0x91>, <&dmac0 0x90>,
591 <&dmac1 0x91>, 481 <&dmac1 0x91>, <&dmac1 0x90>;
592 dma-names = "tx", "rx" 482 dma-names = "tx", "rx", "tx", "rx";
593 i2c-scl-internal-delay 483 i2c-scl-internal-delay-ns = <110>;
594 #address-cells = <1>; 484 #address-cells = <1>;
595 #size-cells = <0>; 485 #size-cells = <0>;
596 status = "disabled"; 486 status = "disabled";
597 }; 487 };
598 488
599 i2c1: i2c@e6508000 { 489 i2c1: i2c@e6508000 {
600 compatible = "renesas, 490 compatible = "renesas,i2c-r8a779f0",
601 "renesas, 491 "renesas,rcar-gen4-i2c";
602 reg = <0 0xe6508000 0 492 reg = <0 0xe6508000 0 0x40>;
603 interrupts = <GIC_SPI 493 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
604 clocks = <&cpg CPG_MOD 494 clocks = <&cpg CPG_MOD 519>;
605 power-domains = <&sysc 495 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
606 resets = <&cpg 519>; 496 resets = <&cpg 519>;
607 dmas = <&dmac0 0x93>, 497 dmas = <&dmac0 0x93>, <&dmac0 0x92>,
608 <&dmac1 0x93>, 498 <&dmac1 0x93>, <&dmac1 0x92>;
609 dma-names = "tx", "rx" 499 dma-names = "tx", "rx", "tx", "rx";
610 i2c-scl-internal-delay 500 i2c-scl-internal-delay-ns = <110>;
611 #address-cells = <1>; 501 #address-cells = <1>;
612 #size-cells = <0>; 502 #size-cells = <0>;
613 status = "disabled"; 503 status = "disabled";
614 }; 504 };
615 505
616 i2c2: i2c@e6510000 { 506 i2c2: i2c@e6510000 {
617 compatible = "renesas, 507 compatible = "renesas,i2c-r8a779f0",
618 "renesas, 508 "renesas,rcar-gen4-i2c";
619 reg = <0 0xe6510000 0 509 reg = <0 0xe6510000 0 0x40>;
620 interrupts = <0 240 IR 510 interrupts = <0 240 IRQ_TYPE_LEVEL_HIGH>;
621 clocks = <&cpg CPG_MOD 511 clocks = <&cpg CPG_MOD 520>;
622 power-domains = <&sysc 512 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
623 resets = <&cpg 520>; 513 resets = <&cpg 520>;
624 dmas = <&dmac0 0x95>, 514 dmas = <&dmac0 0x95>, <&dmac0 0x94>,
625 <&dmac1 0x95>, 515 <&dmac1 0x95>, <&dmac1 0x94>;
626 dma-names = "tx", "rx" 516 dma-names = "tx", "rx", "tx", "rx";
627 i2c-scl-internal-delay 517 i2c-scl-internal-delay-ns = <110>;
628 #address-cells = <1>; 518 #address-cells = <1>;
629 #size-cells = <0>; 519 #size-cells = <0>;
630 status = "disabled"; 520 status = "disabled";
631 }; 521 };
632 522
633 i2c3: i2c@e66d0000 { 523 i2c3: i2c@e66d0000 {
634 compatible = "renesas, 524 compatible = "renesas,i2c-r8a779f0",
635 "renesas, 525 "renesas,rcar-gen4-i2c";
636 reg = <0 0xe66d0000 0 526 reg = <0 0xe66d0000 0 0x40>;
637 interrupts = <GIC_SPI 527 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>;
638 clocks = <&cpg CPG_MOD 528 clocks = <&cpg CPG_MOD 521>;
639 power-domains = <&sysc 529 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
640 resets = <&cpg 521>; 530 resets = <&cpg 521>;
641 dmas = <&dmac0 0x97>, 531 dmas = <&dmac0 0x97>, <&dmac0 0x96>,
642 <&dmac1 0x97>, 532 <&dmac1 0x97>, <&dmac1 0x96>;
643 dma-names = "tx", "rx" 533 dma-names = "tx", "rx", "tx", "rx";
644 i2c-scl-internal-delay 534 i2c-scl-internal-delay-ns = <110>;
645 #address-cells = <1>; 535 #address-cells = <1>;
646 #size-cells = <0>; 536 #size-cells = <0>;
647 status = "disabled"; 537 status = "disabled";
648 }; 538 };
649 539
650 i2c4: i2c@e66d8000 { 540 i2c4: i2c@e66d8000 {
651 compatible = "renesas, 541 compatible = "renesas,i2c-r8a779f0",
652 "renesas, 542 "renesas,rcar-gen4-i2c";
653 reg = <0 0xe66d8000 0 543 reg = <0 0xe66d8000 0 0x40>;
654 interrupts = <GIC_SPI 544 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>;
655 clocks = <&cpg CPG_MOD 545 clocks = <&cpg CPG_MOD 522>;
656 power-domains = <&sysc 546 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
657 resets = <&cpg 522>; 547 resets = <&cpg 522>;
658 dmas = <&dmac0 0x99>, 548 dmas = <&dmac0 0x99>, <&dmac0 0x98>,
659 <&dmac1 0x99>, 549 <&dmac1 0x99>, <&dmac1 0x98>;
660 dma-names = "tx", "rx" 550 dma-names = "tx", "rx", "tx", "rx";
661 i2c-scl-internal-delay 551 i2c-scl-internal-delay-ns = <110>;
662 #address-cells = <1>; 552 #address-cells = <1>;
663 #size-cells = <0>; 553 #size-cells = <0>;
664 status = "disabled"; 554 status = "disabled";
665 }; 555 };
666 556
667 i2c5: i2c@e66e0000 { 557 i2c5: i2c@e66e0000 {
668 compatible = "renesas, 558 compatible = "renesas,i2c-r8a779f0",
669 "renesas, 559 "renesas,rcar-gen4-i2c";
670 reg = <0 0xe66e0000 0 560 reg = <0 0xe66e0000 0 0x40>;
671 interrupts = <GIC_SPI 561 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
672 clocks = <&cpg CPG_MOD 562 clocks = <&cpg CPG_MOD 523>;
673 power-domains = <&sysc 563 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
674 resets = <&cpg 523>; 564 resets = <&cpg 523>;
675 dmas = <&dmac0 0x9b>, 565 dmas = <&dmac0 0x9b>, <&dmac0 0x9a>,
676 <&dmac1 0x9b>, 566 <&dmac1 0x9b>, <&dmac1 0x9a>;
677 dma-names = "tx", "rx" 567 dma-names = "tx", "rx", "tx", "rx";
678 i2c-scl-internal-delay 568 i2c-scl-internal-delay-ns = <110>;
679 #address-cells = <1>; 569 #address-cells = <1>;
680 #size-cells = <0>; 570 #size-cells = <0>;
681 status = "disabled"; 571 status = "disabled";
682 }; 572 };
683 573
684 hscif0: serial@e6540000 { 574 hscif0: serial@e6540000 {
685 compatible = "renesas, 575 compatible = "renesas,hscif-r8a779f0",
686 "renesas, 576 "renesas,rcar-gen4-hscif", "renesas,hscif";
687 reg = <0 0xe6540000 0 577 reg = <0 0xe6540000 0 0x60>;
688 interrupts = <GIC_SPI 578 interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>;
689 clocks = <&cpg CPG_MOD 579 clocks = <&cpg CPG_MOD 514>,
690 <&cpg CPG_COR 580 <&cpg CPG_CORE R8A779F0_CLK_SASYNCPERD1>,
691 <&scif_clk>; 581 <&scif_clk>;
692 clock-names = "fck", " 582 clock-names = "fck", "brg_int", "scif_clk";
693 dmas = <&dmac0 0x31>, 583 dmas = <&dmac0 0x31>, <&dmac0 0x30>,
694 <&dmac1 0x31>, 584 <&dmac1 0x31>, <&dmac1 0x30>;
695 dma-names = "tx", "rx" 585 dma-names = "tx", "rx", "tx", "rx";
696 power-domains = <&sysc 586 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
697 resets = <&cpg 514>; 587 resets = <&cpg 514>;
698 status = "disabled"; 588 status = "disabled";
699 }; 589 };
700 590
701 hscif1: serial@e6550000 { 591 hscif1: serial@e6550000 {
702 compatible = "renesas, 592 compatible = "renesas,hscif-r8a779f0",
703 "renesas, 593 "renesas,rcar-gen4-hscif", "renesas,hscif";
704 reg = <0 0xe6550000 0 594 reg = <0 0xe6550000 0 0x60>;
705 interrupts = <GIC_SPI 595 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
706 clocks = <&cpg CPG_MOD 596 clocks = <&cpg CPG_MOD 515>,
707 <&cpg CPG_COR 597 <&cpg CPG_CORE R8A779F0_CLK_SASYNCPERD1>,
708 <&scif_clk>; 598 <&scif_clk>;
709 clock-names = "fck", " 599 clock-names = "fck", "brg_int", "scif_clk";
710 dmas = <&dmac0 0x33>, 600 dmas = <&dmac0 0x33>, <&dmac0 0x32>,
711 <&dmac1 0x33>, 601 <&dmac1 0x33>, <&dmac1 0x32>;
712 dma-names = "tx", "rx" 602 dma-names = "tx", "rx", "tx", "rx";
713 power-domains = <&sysc 603 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
714 resets = <&cpg 515>; 604 resets = <&cpg 515>;
715 status = "disabled"; 605 status = "disabled";
716 }; 606 };
717 607
718 hscif2: serial@e6560000 { 608 hscif2: serial@e6560000 {
719 compatible = "renesas, 609 compatible = "renesas,hscif-r8a779f0",
720 "renesas, 610 "renesas,rcar-gen4-hscif", "renesas,hscif";
721 reg = <0 0xe6560000 0 611 reg = <0 0xe6560000 0 0x60>;
722 interrupts = <GIC_SPI 612 interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
723 clocks = <&cpg CPG_MOD 613 clocks = <&cpg CPG_MOD 516>,
724 <&cpg CPG_COR 614 <&cpg CPG_CORE R8A779F0_CLK_SASYNCPERD1>,
725 <&scif_clk>; 615 <&scif_clk>;
726 clock-names = "fck", " 616 clock-names = "fck", "brg_int", "scif_clk";
727 dmas = <&dmac0 0x35>, 617 dmas = <&dmac0 0x35>, <&dmac0 0x34>,
728 <&dmac1 0x35>, 618 <&dmac1 0x35>, <&dmac1 0x34>;
729 dma-names = "tx", "rx" 619 dma-names = "tx", "rx", "tx", "rx";
730 power-domains = <&sysc 620 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
731 resets = <&cpg 516>; 621 resets = <&cpg 516>;
732 status = "disabled"; 622 status = "disabled";
733 }; 623 };
734 624
735 hscif3: serial@e66a0000 { 625 hscif3: serial@e66a0000 {
736 compatible = "renesas, 626 compatible = "renesas,hscif-r8a779f0",
737 "renesas, 627 "renesas,rcar-gen4-hscif", "renesas,hscif";
738 reg = <0 0xe66a0000 0 628 reg = <0 0xe66a0000 0 0x60>;
739 interrupts = <GIC_SPI 629 interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>;
740 clocks = <&cpg CPG_MOD 630 clocks = <&cpg CPG_MOD 517>,
741 <&cpg CPG_COR 631 <&cpg CPG_CORE R8A779F0_CLK_SASYNCPERD1>,
742 <&scif_clk>; 632 <&scif_clk>;
743 clock-names = "fck", " 633 clock-names = "fck", "brg_int", "scif_clk";
744 dmas = <&dmac0 0x37>, 634 dmas = <&dmac0 0x37>, <&dmac0 0x36>,
745 <&dmac1 0x37>, 635 <&dmac1 0x37>, <&dmac1 0x36>;
746 dma-names = "tx", "rx" 636 dma-names = "tx", "rx", "tx", "rx";
747 power-domains = <&sysc 637 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
748 resets = <&cpg 517>; 638 resets = <&cpg 517>;
749 status = "disabled"; 639 status = "disabled";
750 }; 640 };
751 641
752 pciec0: pcie@e65d0000 { <<
753 compatible = "renesas, <<
754 "renesas, <<
755 reg = <0 0xe65d0000 0 <<
756 <0 0xe65d3000 0 <<
757 <0 0xe65d6200 0 <<
758 <0 0xfe000000 0 <<
759 reg-names = "dbi", "db <<
760 interrupts = <GIC_SPI <<
761 <GIC_SPI <<
762 <GIC_SPI <<
763 <GIC_SPI <<
764 interrupt-names = "msi <<
765 clocks = <&cpg CPG_MOD <<
766 clock-names = "core", <<
767 power-domains = <&sysc <<
768 resets = <&cpg 624>; <<
769 reset-names = "pwr"; <<
770 max-link-speed = <4>; <<
771 num-lanes = <2>; <<
772 #address-cells = <3>; <<
773 #size-cells = <2>; <<
774 bus-range = <0x00 0xff <<
775 device_type = "pci"; <<
776 ranges = <0x01000000 0 <<
777 <0x02000000 0 <<
778 dma-ranges = <0x420000 <<
779 #interrupt-cells = <1> <<
780 interrupt-map-mask = < <<
781 interrupt-map = <0 0 0 <<
782 <0 0 0 <<
783 <0 0 0 <<
784 <0 0 0 <<
785 snps,enable-cdm-check; <<
786 status = "disabled"; <<
787 }; <<
788 <<
789 pciec1: pcie@e65d8000 { <<
790 compatible = "renesas, <<
791 "renesas, <<
792 reg = <0 0xe65d8000 0 <<
793 <0 0xe65db000 0 <<
794 <0 0xe65de200 0 <<
795 <0 0xee900000 0 <<
796 reg-names = "dbi", "db <<
797 interrupts = <GIC_SPI <<
798 <GIC_SPI <<
799 <GIC_SPI <<
800 <GIC_SPI <<
801 interrupt-names = "msi <<
802 clocks = <&cpg CPG_MOD <<
803 clock-names = "core", <<
804 power-domains = <&sysc <<
805 resets = <&cpg 625>; <<
806 reset-names = "pwr"; <<
807 max-link-speed = <4>; <<
808 num-lanes = <2>; <<
809 #address-cells = <3>; <<
810 #size-cells = <2>; <<
811 bus-range = <0x00 0xff <<
812 device_type = "pci"; <<
813 ranges = <0x01000000 0 <<
814 <0x02000000 0 <<
815 dma-ranges = <0x420000 <<
816 #interrupt-cells = <1> <<
817 interrupt-map-mask = < <<
818 interrupt-map = <0 0 0 <<
819 <0 0 0 <<
820 <0 0 0 <<
821 <0 0 0 <<
822 snps,enable-cdm-check; <<
823 status = "disabled"; <<
824 }; <<
825 <<
826 pciec0_ep: pcie-ep@e65d0000 { <<
827 compatible = "renesas, <<
828 "renesas, <<
829 reg = <0 0xe65d0000 0 <<
830 <0 0xe65d3000 0 <<
831 <0 0xe65d6200 0 <<
832 <0 0xfe000000 0 <<
833 reg-names = "dbi", "db <<
834 interrupts = <GIC_SPI <<
835 <GIC_SPI <<
836 <GIC_SPI <<
837 interrupt-names = "dma <<
838 clocks = <&cpg CPG_MOD <<
839 clock-names = "core", <<
840 power-domains = <&sysc <<
841 resets = <&cpg 624>; <<
842 reset-names = "pwr"; <<
843 max-link-speed = <4>; <<
844 num-lanes = <2>; <<
845 max-functions = /bits/ <<
846 status = "disabled"; <<
847 }; <<
848 <<
849 pciec1_ep: pcie-ep@e65d8000 { <<
850 compatible = "renesas, <<
851 "renesas, <<
852 reg = <0 0xe65d8000 0 <<
853 <0 0xe65db000 0 <<
854 <0 0xe65de200 0 <<
855 <0 0xee900000 0 <<
856 reg-names = "dbi", "db <<
857 interrupts = <GIC_SPI <<
858 <GIC_SPI <<
859 <GIC_SPI <<
860 interrupt-names = "dma <<
861 clocks = <&cpg CPG_MOD <<
862 clock-names = "core", <<
863 power-domains = <&sysc <<
864 resets = <&cpg 625>; <<
865 reset-names = "pwr"; <<
866 max-link-speed = <4>; <<
867 num-lanes = <2>; <<
868 max-functions = /bits/ <<
869 status = "disabled"; <<
870 }; <<
871 <<
872 ufs: ufs@e6860000 { 642 ufs: ufs@e6860000 {
873 compatible = "renesas, 643 compatible = "renesas,r8a779f0-ufs";
874 reg = <0 0xe6860000 0 644 reg = <0 0xe6860000 0 0x100>;
875 interrupts = <GIC_SPI 645 interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>;
876 clocks = <&cpg CPG_MOD 646 clocks = <&cpg CPG_MOD 1514>, <&ufs30_clk>;
877 clock-names = "fck", " 647 clock-names = "fck", "ref_clk";
878 freq-table-hz = <20000 648 freq-table-hz = <200000000 200000000>, <38400000 38400000>;
879 power-domains = <&sysc 649 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
880 resets = <&cpg 1514>; 650 resets = <&cpg 1514>;
881 status = "disabled"; 651 status = "disabled";
882 }; 652 };
883 653
884 rswitch: ethernet@e6880000 { <<
885 compatible = "renesas, <<
886 reg = <0 0xe6880000 0 <<
887 reg-names = "base", "s <<
888 interrupts = <GIC_SPI <<
889 <GIC_SPI <<
890 <GIC_SPI <<
891 <GIC_SPI <<
892 <GIC_SPI <<
893 <GIC_SPI <<
894 <GIC_SPI <<
895 <GIC_SPI <<
896 <GIC_SPI <<
897 <GIC_SPI <<
898 <GIC_SPI <<
899 <GIC_SPI <<
900 <GIC_SPI <<
901 <GIC_SPI <<
902 <GIC_SPI <<
903 <GIC_SPI <<
904 <GIC_SPI <<
905 <GIC_SPI <<
906 <GIC_SPI <<
907 <GIC_SPI <<
908 <GIC_SPI <<
909 <GIC_SPI <<
910 <GIC_SPI <<
911 <GIC_SPI <<
912 <GIC_SPI <<
913 <GIC_SPI <<
914 <GIC_SPI <<
915 <GIC_SPI <<
916 <GIC_SPI <<
917 <GIC_SPI <<
918 <GIC_SPI <<
919 <GIC_SPI <<
920 <GIC_SPI <<
921 <GIC_SPI <<
922 <GIC_SPI <<
923 <GIC_SPI <<
924 <GIC_SPI <<
925 <GIC_SPI <<
926 <GIC_SPI <<
927 <GIC_SPI <<
928 <GIC_SPI <<
929 <GIC_SPI <<
930 <GIC_SPI <<
931 <GIC_SPI <<
932 <GIC_SPI <<
933 <GIC_SPI <<
934 <GIC_SPI <<
935 interrupt-names = "mfw <<
936 "com <<
937 "gwc <<
938 "eth <<
939 "gpt <<
940 "mfw <<
941 "com <<
942 "gwc <<
943 "eth <<
944 "rma <<
945 "rma <<
946 "gwc <<
947 "gwc <<
948 "gwc <<
949 "gwc <<
950 "gwc <<
951 "gwc <<
952 "gwc <<
953 "gwc <<
954 "gwc <<
955 "gwc <<
956 "rma <<
957 "rma <<
958 "rma <<
959 "rma <<
960 clocks = <&cpg CPG_MOD <<
961 power-domains = <&sysc <<
962 resets = <&cpg 1505>; <<
963 status = "disabled"; <<
964 <<
965 ethernet-ports { <<
966 #address-cells <<
967 #size-cells = <<
968 <<
969 port@0 { <<
970 reg = <<
971 phys = <<
972 }; <<
973 port@1 { <<
974 reg = <<
975 phys = <<
976 }; <<
977 port@2 { <<
978 reg = <<
979 phys = <<
980 }; <<
981 }; <<
982 }; <<
983 <<
984 scif0: serial@e6e60000 { 654 scif0: serial@e6e60000 {
985 compatible = "renesas, 655 compatible = "renesas,scif-r8a779f0",
986 "renesas, 656 "renesas,rcar-gen4-scif", "renesas,scif";
987 reg = <0 0xe6e60000 0 657 reg = <0 0xe6e60000 0 64>;
988 interrupts = <GIC_SPI 658 interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>;
989 clocks = <&cpg CPG_MOD 659 clocks = <&cpg CPG_MOD 702>,
990 <&cpg CPG_COR 660 <&cpg CPG_CORE R8A779F0_CLK_SASYNCPERD1>,
991 <&scif_clk>; 661 <&scif_clk>;
992 clock-names = "fck", " 662 clock-names = "fck", "brg_int", "scif_clk";
993 dmas = <&dmac0 0x51>, 663 dmas = <&dmac0 0x51>, <&dmac0 0x50>,
994 <&dmac1 0x51>, 664 <&dmac1 0x51>, <&dmac1 0x50>;
995 dma-names = "tx", "rx" 665 dma-names = "tx", "rx", "tx", "rx";
996 power-domains = <&sysc 666 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
997 resets = <&cpg 702>; 667 resets = <&cpg 702>;
998 status = "disabled"; 668 status = "disabled";
999 }; 669 };
1000 670
1001 scif1: serial@e6e68000 { 671 scif1: serial@e6e68000 {
1002 compatible = "renesas 672 compatible = "renesas,scif-r8a779f0",
1003 "renesas 673 "renesas,rcar-gen4-scif", "renesas,scif";
1004 reg = <0 0xe6e68000 0 674 reg = <0 0xe6e68000 0 64>;
1005 interrupts = <GIC_SPI 675 interrupts = <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>;
1006 clocks = <&cpg CPG_MO 676 clocks = <&cpg CPG_MOD 703>,
1007 <&cpg CPG_CO 677 <&cpg CPG_CORE R8A779F0_CLK_SASYNCPERD1>,
1008 <&scif_clk>; 678 <&scif_clk>;
1009 clock-names = "fck", 679 clock-names = "fck", "brg_int", "scif_clk";
1010 dmas = <&dmac0 0x53>, 680 dmas = <&dmac0 0x53>, <&dmac0 0x52>,
1011 <&dmac1 0x53>, 681 <&dmac1 0x53>, <&dmac1 0x52>;
1012 dma-names = "tx", "rx 682 dma-names = "tx", "rx", "tx", "rx";
1013 power-domains = <&sys 683 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
1014 resets = <&cpg 703>; 684 resets = <&cpg 703>;
1015 status = "disabled"; 685 status = "disabled";
1016 }; 686 };
1017 687
1018 scif3: serial@e6c50000 { 688 scif3: serial@e6c50000 {
1019 compatible = "renesas 689 compatible = "renesas,scif-r8a779f0",
1020 "renesas 690 "renesas,rcar-gen4-scif", "renesas,scif";
1021 reg = <0 0xe6c50000 0 691 reg = <0 0xe6c50000 0 64>;
1022 interrupts = <GIC_SPI 692 interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>;
1023 clocks = <&cpg CPG_MO 693 clocks = <&cpg CPG_MOD 704>,
1024 <&cpg CPG_CO 694 <&cpg CPG_CORE R8A779F0_CLK_SASYNCPERD1>,
1025 <&scif_clk>; 695 <&scif_clk>;
1026 clock-names = "fck", 696 clock-names = "fck", "brg_int", "scif_clk";
1027 dmas = <&dmac0 0x57>, 697 dmas = <&dmac0 0x57>, <&dmac0 0x56>,
1028 <&dmac1 0x57>, 698 <&dmac1 0x57>, <&dmac1 0x56>;
1029 dma-names = "tx", "rx 699 dma-names = "tx", "rx", "tx", "rx";
1030 power-domains = <&sys 700 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
1031 resets = <&cpg 704>; 701 resets = <&cpg 704>;
1032 status = "disabled"; 702 status = "disabled";
1033 }; 703 };
1034 704
1035 scif4: serial@e6c40000 { 705 scif4: serial@e6c40000 {
1036 compatible = "renesas 706 compatible = "renesas,scif-r8a779f0",
1037 "renesas 707 "renesas,rcar-gen4-scif", "renesas,scif";
1038 reg = <0 0xe6c40000 0 708 reg = <0 0xe6c40000 0 64>;
1039 interrupts = <GIC_SPI 709 interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>;
1040 clocks = <&cpg CPG_MO 710 clocks = <&cpg CPG_MOD 705>,
1041 <&cpg CPG_CO 711 <&cpg CPG_CORE R8A779F0_CLK_SASYNCPERD1>,
1042 <&scif_clk>; 712 <&scif_clk>;
1043 clock-names = "fck", 713 clock-names = "fck", "brg_int", "scif_clk";
1044 dmas = <&dmac0 0x59>, 714 dmas = <&dmac0 0x59>, <&dmac0 0x58>,
1045 <&dmac1 0x59>, 715 <&dmac1 0x59>, <&dmac1 0x58>;
1046 dma-names = "tx", "rx 716 dma-names = "tx", "rx", "tx", "rx";
1047 power-domains = <&sys 717 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
1048 resets = <&cpg 705>; 718 resets = <&cpg 705>;
1049 status = "disabled"; 719 status = "disabled";
1050 }; 720 };
1051 721
1052 msiof0: spi@e6e90000 { 722 msiof0: spi@e6e90000 {
1053 compatible = "renesas 723 compatible = "renesas,msiof-r8a779f0",
1054 "renesas 724 "renesas,rcar-gen4-msiof";
1055 reg = <0 0xe6e90000 0 725 reg = <0 0xe6e90000 0 0x0064>;
1056 interrupts = <GIC_SPI 726 interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>;
1057 clocks = <&cpg CPG_MO 727 clocks = <&cpg CPG_MOD 618>;
1058 dmas = <&dmac0 0x41>, 728 dmas = <&dmac0 0x41>, <&dmac0 0x40>,
1059 <&dmac1 0x41>, 729 <&dmac1 0x41>, <&dmac1 0x40>;
1060 dma-names = "tx", "rx 730 dma-names = "tx", "rx", "tx", "rx";
1061 power-domains = <&sys 731 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
1062 resets = <&cpg 618>; 732 resets = <&cpg 618>;
1063 #address-cells = <1>; 733 #address-cells = <1>;
1064 #size-cells = <0>; 734 #size-cells = <0>;
1065 status = "disabled"; 735 status = "disabled";
1066 }; 736 };
1067 737
1068 msiof1: spi@e6ea0000 { 738 msiof1: spi@e6ea0000 {
1069 compatible = "renesas 739 compatible = "renesas,msiof-r8a779f0",
1070 "renesas 740 "renesas,rcar-gen4-msiof";
1071 reg = <0 0xe6ea0000 0 741 reg = <0 0xe6ea0000 0 0x0064>;
1072 interrupts = <GIC_SPI 742 interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>;
1073 clocks = <&cpg CPG_MO 743 clocks = <&cpg CPG_MOD 619>;
1074 dmas = <&dmac0 0x43>, 744 dmas = <&dmac0 0x43>, <&dmac0 0x42>,
1075 <&dmac1 0x43>, 745 <&dmac1 0x43>, <&dmac1 0x42>;
1076 dma-names = "tx", "rx 746 dma-names = "tx", "rx", "tx", "rx";
1077 power-domains = <&sys 747 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
1078 resets = <&cpg 619>; 748 resets = <&cpg 619>;
1079 #address-cells = <1>; 749 #address-cells = <1>;
1080 #size-cells = <0>; 750 #size-cells = <0>;
1081 status = "disabled"; 751 status = "disabled";
1082 }; 752 };
1083 753
1084 msiof2: spi@e6c00000 { 754 msiof2: spi@e6c00000 {
1085 compatible = "renesas 755 compatible = "renesas,msiof-r8a779f0",
1086 "renesas 756 "renesas,rcar-gen4-msiof";
1087 reg = <0 0xe6c00000 0 757 reg = <0 0xe6c00000 0 0x0064>;
1088 interrupts = <GIC_SPI 758 interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>;
1089 clocks = <&cpg CPG_MO 759 clocks = <&cpg CPG_MOD 620>;
1090 dmas = <&dmac0 0x45>, 760 dmas = <&dmac0 0x45>, <&dmac0 0x44>,
1091 <&dmac1 0x45>, 761 <&dmac1 0x45>, <&dmac1 0x44>;
1092 dma-names = "tx", "rx 762 dma-names = "tx", "rx", "tx", "rx";
1093 power-domains = <&sys 763 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
1094 resets = <&cpg 620>; 764 resets = <&cpg 620>;
1095 #address-cells = <1>; 765 #address-cells = <1>;
1096 #size-cells = <0>; 766 #size-cells = <0>;
1097 status = "disabled"; 767 status = "disabled";
1098 }; 768 };
1099 769
1100 msiof3: spi@e6c10000 { 770 msiof3: spi@e6c10000 {
1101 compatible = "renesas 771 compatible = "renesas,msiof-r8a779f0",
1102 "renesas 772 "renesas,rcar-gen4-msiof";
1103 reg = <0 0xe6c10000 0 773 reg = <0 0xe6c10000 0 0x0064>;
1104 interrupts = <GIC_SPI 774 interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>;
1105 clocks = <&cpg CPG_MO 775 clocks = <&cpg CPG_MOD 621>;
1106 dmas = <&dmac0 0x47>, 776 dmas = <&dmac0 0x47>, <&dmac0 0x46>,
1107 <&dmac1 0x47>, 777 <&dmac1 0x47>, <&dmac1 0x46>;
1108 dma-names = "tx", "rx 778 dma-names = "tx", "rx", "tx", "rx";
1109 power-domains = <&sys 779 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
1110 resets = <&cpg 621>; 780 resets = <&cpg 621>;
1111 #address-cells = <1>; 781 #address-cells = <1>;
1112 #size-cells = <0>; 782 #size-cells = <0>;
1113 status = "disabled"; 783 status = "disabled";
1114 }; 784 };
1115 785
1116 dmac0: dma-controller@e735000 786 dmac0: dma-controller@e7350000 {
1117 compatible = "renesas 787 compatible = "renesas,dmac-r8a779f0",
1118 "renesas 788 "renesas,rcar-gen4-dmac";
1119 reg = <0 0xe7350000 0 789 reg = <0 0xe7350000 0 0x1000>,
1120 <0 0xe7300000 0 790 <0 0xe7300000 0 0x10000>;
1121 interrupts = <GIC_SPI 791 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
1122 <GIC_SPI 792 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
1123 <GIC_SPI 793 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
1124 <GIC_SPI 794 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
1125 <GIC_SPI 795 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
1126 <GIC_SPI 796 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
1127 <GIC_SPI 797 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
1128 <GIC_SPI 798 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
1129 <GIC_SPI 799 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
1130 <GIC_SPI 800 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
1131 <GIC_SPI 801 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
1132 <GIC_SPI 802 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
1133 <GIC_SPI 803 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
1134 <GIC_SPI 804 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
1135 <GIC_SPI 805 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
1136 <GIC_SPI 806 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
1137 <GIC_SPI 807 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
1138 interrupt-names = "er 808 interrupt-names = "error",
1139 "ch 809 "ch0", "ch1", "ch2", "ch3", "ch4",
1140 "ch 810 "ch5", "ch6", "ch7", "ch8", "ch9",
1141 "ch 811 "ch10", "ch11", "ch12", "ch13",
1142 "ch 812 "ch14", "ch15";
1143 clocks = <&cpg CPG_MO 813 clocks = <&cpg CPG_MOD 709>;
1144 clock-names = "fck"; 814 clock-names = "fck";
1145 power-domains = <&sys 815 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
1146 resets = <&cpg 709>; 816 resets = <&cpg 709>;
1147 #dma-cells = <1>; 817 #dma-cells = <1>;
1148 dma-channels = <16>; 818 dma-channels = <16>;
1149 iommus = <&ipmmu_ds0 819 iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>,
1150 <&ipmmu_ds0 820 <&ipmmu_ds0 2>, <&ipmmu_ds0 3>,
1151 <&ipmmu_ds0 821 <&ipmmu_ds0 4>, <&ipmmu_ds0 5>,
1152 <&ipmmu_ds0 822 <&ipmmu_ds0 6>, <&ipmmu_ds0 7>,
1153 <&ipmmu_ds0 823 <&ipmmu_ds0 8>, <&ipmmu_ds0 9>,
1154 <&ipmmu_ds0 824 <&ipmmu_ds0 10>, <&ipmmu_ds0 11>,
1155 <&ipmmu_ds0 825 <&ipmmu_ds0 12>, <&ipmmu_ds0 13>,
1156 <&ipmmu_ds0 826 <&ipmmu_ds0 14>, <&ipmmu_ds0 15>;
1157 }; 827 };
1158 828
1159 dmac1: dma-controller@e735100 829 dmac1: dma-controller@e7351000 {
1160 compatible = "renesas 830 compatible = "renesas,dmac-r8a779f0",
1161 "renesas 831 "renesas,rcar-gen4-dmac";
1162 reg = <0 0xe7351000 0 832 reg = <0 0xe7351000 0 0x1000>,
1163 <0 0xe7310000 0 833 <0 0xe7310000 0 0x10000>;
1164 interrupts = <GIC_SPI 834 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
1165 <GIC_SPI 835 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
1166 <GIC_SPI 836 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
1167 <GIC_SPI 837 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
1168 <GIC_SPI 838 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
1169 <GIC_SPI 839 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
1170 <GIC_SPI 840 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
1171 <GIC_SPI 841 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
1172 <GIC_SPI 842 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
1173 <GIC_SPI 843 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
1174 <GIC_SPI 844 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
1175 <GIC_SPI 845 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
1176 <GIC_SPI 846 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
1177 <GIC_SPI 847 <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
1178 <GIC_SPI 848 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
1179 <GIC_SPI 849 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
1180 <GIC_SPI 850 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
1181 interrupt-names = "er 851 interrupt-names = "error",
1182 "ch 852 "ch0", "ch1", "ch2", "ch3", "ch4",
1183 "ch 853 "ch5", "ch6", "ch7", "ch8", "ch9",
1184 "ch 854 "ch10", "ch11", "ch12", "ch13",
1185 "ch 855 "ch14", "ch15";
1186 clocks = <&cpg CPG_MO 856 clocks = <&cpg CPG_MOD 710>;
1187 clock-names = "fck"; 857 clock-names = "fck";
1188 power-domains = <&sys 858 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
1189 resets = <&cpg 710>; 859 resets = <&cpg 710>;
1190 #dma-cells = <1>; 860 #dma-cells = <1>;
1191 dma-channels = <16>; 861 dma-channels = <16>;
1192 iommus = <&ipmmu_ds0 862 iommus = <&ipmmu_ds0 16>, <&ipmmu_ds0 17>,
1193 <&ipmmu_ds0 863 <&ipmmu_ds0 18>, <&ipmmu_ds0 19>,
1194 <&ipmmu_ds0 864 <&ipmmu_ds0 20>, <&ipmmu_ds0 21>,
1195 <&ipmmu_ds0 865 <&ipmmu_ds0 22>, <&ipmmu_ds0 23>,
1196 <&ipmmu_ds0 866 <&ipmmu_ds0 24>, <&ipmmu_ds0 25>,
1197 <&ipmmu_ds0 867 <&ipmmu_ds0 26>, <&ipmmu_ds0 27>,
1198 <&ipmmu_ds0 868 <&ipmmu_ds0 28>, <&ipmmu_ds0 29>,
1199 <&ipmmu_ds0 869 <&ipmmu_ds0 30>, <&ipmmu_ds0 31>;
1200 }; 870 };
1201 871
1202 mmc0: mmc@ee140000 { 872 mmc0: mmc@ee140000 {
1203 compatible = "renesas 873 compatible = "renesas,sdhi-r8a779f0",
1204 "renesas 874 "renesas,rcar-gen4-sdhi";
1205 reg = <0 0xee140000 0 875 reg = <0 0xee140000 0 0x2000>;
1206 interrupts = <GIC_SPI 876 interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>;
1207 clocks = <&cpg CPG_MO 877 clocks = <&cpg CPG_MOD 706>, <&cpg CPG_CORE R8A779F0_CLK_SD0H>;
1208 clock-names = "core", 878 clock-names = "core", "clkh";
1209 power-domains = <&sys 879 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
1210 resets = <&cpg 706>; 880 resets = <&cpg 706>;
1211 max-frequency = <2000 881 max-frequency = <200000000>;
1212 iommus = <&ipmmu_ds0 <<
1213 status = "disabled"; 882 status = "disabled";
1214 }; 883 };
1215 884
1216 ipmmu_rt0: iommu@ee480000 { 885 ipmmu_rt0: iommu@ee480000 {
1217 compatible = "renesas 886 compatible = "renesas,ipmmu-r8a779f0",
1218 "renesas 887 "renesas,rcar-gen4-ipmmu-vmsa";
1219 reg = <0 0xee480000 0 888 reg = <0 0xee480000 0 0x20000>;
1220 renesas,ipmmu-main = !! 889 renesas,ipmmu-main = <&ipmmu_mm 10>;
1221 power-domains = <&sys 890 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
1222 #iommu-cells = <1>; 891 #iommu-cells = <1>;
1223 }; 892 };
1224 893
1225 ipmmu_rt1: iommu@ee4c0000 { 894 ipmmu_rt1: iommu@ee4c0000 {
1226 compatible = "renesas 895 compatible = "renesas,ipmmu-r8a779f0",
1227 "renesas 896 "renesas,rcar-gen4-ipmmu-vmsa";
1228 reg = <0 0xee4c0000 0 897 reg = <0 0xee4c0000 0 0x20000>;
1229 renesas,ipmmu-main = !! 898 renesas,ipmmu-main = <&ipmmu_mm 19>;
1230 power-domains = <&sys 899 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
1231 #iommu-cells = <1>; 900 #iommu-cells = <1>;
1232 }; 901 };
1233 902
1234 ipmmu_ds0: iommu@eed00000 { 903 ipmmu_ds0: iommu@eed00000 {
1235 compatible = "renesas 904 compatible = "renesas,ipmmu-r8a779f0",
1236 "renesas 905 "renesas,rcar-gen4-ipmmu-vmsa";
1237 reg = <0 0xeed00000 0 906 reg = <0 0xeed00000 0 0x20000>;
1238 renesas,ipmmu-main = !! 907 renesas,ipmmu-main = <&ipmmu_mm 0>;
1239 power-domains = <&sys 908 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
1240 #iommu-cells = <1>; 909 #iommu-cells = <1>;
1241 }; 910 };
1242 911
1243 ipmmu_hc: iommu@eed40000 { 912 ipmmu_hc: iommu@eed40000 {
1244 compatible = "renesas 913 compatible = "renesas,ipmmu-r8a779f0",
1245 "renesas 914 "renesas,rcar-gen4-ipmmu-vmsa";
1246 reg = <0 0xeed40000 0 915 reg = <0 0xeed40000 0 0x20000>;
1247 renesas,ipmmu-main = !! 916 renesas,ipmmu-main = <&ipmmu_mm 2>;
1248 power-domains = <&sys 917 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
1249 #iommu-cells = <1>; 918 #iommu-cells = <1>;
1250 }; 919 };
1251 920
1252 ipmmu_mm: iommu@eefc0000 { 921 ipmmu_mm: iommu@eefc0000 {
1253 compatible = "renesas 922 compatible = "renesas,ipmmu-r8a779f0",
1254 "renesas 923 "renesas,rcar-gen4-ipmmu-vmsa";
1255 reg = <0 0xeefc0000 0 924 reg = <0 0xeefc0000 0 0x20000>;
1256 interrupts = <GIC_SPI 925 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
1257 <GIC_SPI 926 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
1258 power-domains = <&sys 927 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
1259 #iommu-cells = <1>; 928 #iommu-cells = <1>;
1260 }; 929 };
1261 930
1262 gic: interrupt-controller@f10 931 gic: interrupt-controller@f1000000 {
1263 compatible = "arm,gic 932 compatible = "arm,gic-v3";
1264 #interrupt-cells = <3 933 #interrupt-cells = <3>;
1265 #address-cells = <0>; 934 #address-cells = <0>;
1266 interrupt-controller; 935 interrupt-controller;
1267 reg = <0x0 0xf1000000 936 reg = <0x0 0xf1000000 0 0x20000>,
1268 <0x0 0xf1060000 937 <0x0 0xf1060000 0 0x110000>;
1269 interrupts = <GIC_PPI 938 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
1270 }; 939 };
1271 940
1272 prr: chipid@fff00044 { 941 prr: chipid@fff00044 {
1273 compatible = "renesas 942 compatible = "renesas,prr";
1274 reg = <0 0xfff00044 0 943 reg = <0 0xfff00044 0 4>;
1275 }; 944 };
1276 }; 945 };
1277 946
1278 thermal-zones { 947 thermal-zones {
1279 sensor_thermal_rtcore: sensor !! 948 sensor_thermal1: sensor1-thermal {
1280 polling-delay-passive 949 polling-delay-passive = <250>;
1281 polling-delay = <1000 950 polling-delay = <1000>;
1282 thermal-sensors = <&t 951 thermal-sensors = <&tsc 0>;
1283 952
1284 trips { 953 trips {
1285 sensor1_crit: 954 sensor1_crit: sensor1-crit {
1286 tempe 955 temperature = <120000>;
1287 hyste 956 hysteresis = <1000>;
1288 type 957 type = "critical";
1289 }; 958 };
1290 }; 959 };
1291 }; 960 };
1292 961
1293 sensor_thermal_apcore0: senso !! 962 sensor_thermal2: sensor2-thermal {
1294 polling-delay-passive 963 polling-delay-passive = <250>;
1295 polling-delay = <1000 964 polling-delay = <1000>;
1296 thermal-sensors = <&t 965 thermal-sensors = <&tsc 1>;
1297 966
1298 trips { 967 trips {
1299 sensor2_crit: 968 sensor2_crit: sensor2-crit {
1300 tempe 969 temperature = <120000>;
1301 hyste 970 hysteresis = <1000>;
1302 type 971 type = "critical";
1303 }; 972 };
1304 }; 973 };
1305 }; 974 };
1306 975
1307 sensor_thermal_apcore4: senso !! 976 sensor_thermal3: sensor3-thermal {
1308 polling-delay-passive 977 polling-delay-passive = <250>;
1309 polling-delay = <1000 978 polling-delay = <1000>;
1310 thermal-sensors = <&t 979 thermal-sensors = <&tsc 2>;
1311 980
1312 trips { 981 trips {
1313 sensor3_crit: 982 sensor3_crit: sensor3-crit {
1314 tempe 983 temperature = <120000>;
1315 hyste 984 hysteresis = <1000>;
1316 type 985 type = "critical";
1317 }; 986 };
1318 }; 987 };
1319 }; 988 };
1320 }; 989 };
1321 990
1322 timer { 991 timer {
1323 compatible = "arm,armv8-timer 992 compatible = "arm,armv8-timer";
1324 interrupts-extended = <&gic G 993 interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
1325 <&gic G 994 <&gic GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
1326 <&gic G 995 <&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
1327 <&gic G 996 <&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>,
1328 <&gic G 997 <&gic GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>;
1329 interrupt-names = "sec-phys", 998 interrupt-names = "sec-phys", "phys", "virt", "hyp-phys",
1330 "hyp-virt"; 999 "hyp-virt";
1331 }; 1000 };
1332 1001
1333 ufs30_clk: ufs30-clk { 1002 ufs30_clk: ufs30-clk {
1334 compatible = "fixed-clock"; 1003 compatible = "fixed-clock";
1335 #clock-cells = <0>; 1004 #clock-cells = <0>;
1336 /* This value must be overrid 1005 /* This value must be overridden by the board */
1337 clock-frequency = <0>; 1006 clock-frequency = <0>;
1338 }; 1007 };
1339 }; 1008 };
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