1 // SPDX-License-Identifier: (GPL-2.0-only OR B 1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 /* 2 /*
3 * Device Tree Source for the R-Car V4M (R8A77 3 * Device Tree Source for the R-Car V4M (R8A779H0) SoC
4 * 4 *
5 * Copyright (C) 2023 Renesas Electronics Corp 5 * Copyright (C) 2023 Renesas Electronics Corp.
6 */ 6 */
7 7
8 #include <dt-bindings/clock/renesas,r8a779h0-c 8 #include <dt-bindings/clock/renesas,r8a779h0-cpg-mssr.h>
9 #include <dt-bindings/interrupt-controller/arm 9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/power/renesas,r8a779h0-s 10 #include <dt-bindings/power/renesas,r8a779h0-sysc.h>
11 11
12 / { 12 / {
13 compatible = "renesas,r8a779h0"; 13 compatible = "renesas,r8a779h0";
14 #address-cells = <2>; 14 #address-cells = <2>;
15 #size-cells = <2>; 15 #size-cells = <2>;
16 16
17 /* External Audio clock - to be overri <<
18 audio_clkin: audio_clkin { <<
19 compatible = "fixed-clock"; <<
20 #clock-cells = <0>; <<
21 clock-frequency = <0>; <<
22 }; <<
23 <<
24 /* External CAN clock - to be overridd <<
25 can_clk: can-clk { <<
26 compatible = "fixed-clock"; <<
27 #clock-cells = <0>; <<
28 clock-frequency = <0>; <<
29 }; <<
30 <<
31 cluster0_opp: opp-table-0 { 17 cluster0_opp: opp-table-0 {
32 compatible = "operating-points 18 compatible = "operating-points-v2";
33 19
34 opp-500000000 { 20 opp-500000000 {
35 opp-hz = /bits/ 64 <50 21 opp-hz = /bits/ 64 <500000000>;
36 opp-microvolt = <82500 22 opp-microvolt = <825000>;
37 clock-latency-ns = <50 23 clock-latency-ns = <500000>;
38 }; 24 };
39 opp-1000000000 { 25 opp-1000000000 {
40 opp-hz = /bits/ 64 <10 26 opp-hz = /bits/ 64 <1000000000>;
41 opp-microvolt = <82500 27 opp-microvolt = <825000>;
42 clock-latency-ns = <50 28 clock-latency-ns = <500000>;
43 }; 29 };
44 }; 30 };
45 31
46 cpus { 32 cpus {
47 #address-cells = <1>; 33 #address-cells = <1>;
48 #size-cells = <0>; 34 #size-cells = <0>;
49 35
50 cpu-map { 36 cpu-map {
51 cluster0 { 37 cluster0 {
52 core0 { 38 core0 {
53 cpu = 39 cpu = <&a76_0>;
54 }; 40 };
55 core1 { 41 core1 {
56 cpu = 42 cpu = <&a76_1>;
57 }; 43 };
58 core2 { 44 core2 {
59 cpu = 45 cpu = <&a76_2>;
60 }; 46 };
61 core3 { 47 core3 {
62 cpu = 48 cpu = <&a76_3>;
63 }; 49 };
64 }; 50 };
65 }; 51 };
66 52
67 a76_0: cpu@0 { 53 a76_0: cpu@0 {
68 compatible = "arm,cort 54 compatible = "arm,cortex-a76";
69 reg = <0>; 55 reg = <0>;
70 device_type = "cpu"; 56 device_type = "cpu";
71 power-domains = <&sysc 57 power-domains = <&sysc R8A779H0_PD_A1E0D0C0>;
72 next-level-cache = <&L 58 next-level-cache = <&L3_CA76>;
73 enable-method = "psci" 59 enable-method = "psci";
74 cpu-idle-states = <&CP 60 cpu-idle-states = <&CPU_SLEEP_0>;
75 clocks = <&cpg CPG_COR 61 clocks = <&cpg CPG_CORE R8A779H0_CLK_ZC0>;
76 operating-points-v2 = 62 operating-points-v2 = <&cluster0_opp>;
77 }; 63 };
78 64
79 a76_1: cpu@100 { 65 a76_1: cpu@100 {
80 compatible = "arm,cort 66 compatible = "arm,cortex-a76";
81 reg = <0x100>; 67 reg = <0x100>;
82 device_type = "cpu"; 68 device_type = "cpu";
83 power-domains = <&sysc 69 power-domains = <&sysc R8A779H0_PD_A1E0D0C1>;
84 next-level-cache = <&L 70 next-level-cache = <&L3_CA76>;
85 enable-method = "psci" 71 enable-method = "psci";
86 cpu-idle-states = <&CP 72 cpu-idle-states = <&CPU_SLEEP_0>;
87 clocks = <&cpg CPG_COR 73 clocks = <&cpg CPG_CORE R8A779H0_CLK_ZC1>;
88 operating-points-v2 = 74 operating-points-v2 = <&cluster0_opp>;
89 }; 75 };
90 76
91 a76_2: cpu@200 { 77 a76_2: cpu@200 {
92 compatible = "arm,cort 78 compatible = "arm,cortex-a76";
93 reg = <0x200>; 79 reg = <0x200>;
94 device_type = "cpu"; 80 device_type = "cpu";
95 power-domains = <&sysc 81 power-domains = <&sysc R8A779H0_PD_A1E0D0C2>;
96 next-level-cache = <&L 82 next-level-cache = <&L3_CA76>;
97 enable-method = "psci" 83 enable-method = "psci";
98 cpu-idle-states = <&CP 84 cpu-idle-states = <&CPU_SLEEP_0>;
99 clocks = <&cpg CPG_COR 85 clocks = <&cpg CPG_CORE R8A779H0_CLK_ZC2>;
100 operating-points-v2 = 86 operating-points-v2 = <&cluster0_opp>;
101 }; 87 };
102 88
103 a76_3: cpu@300 { 89 a76_3: cpu@300 {
104 compatible = "arm,cort 90 compatible = "arm,cortex-a76";
105 reg = <0x300>; 91 reg = <0x300>;
106 device_type = "cpu"; 92 device_type = "cpu";
107 power-domains = <&sysc 93 power-domains = <&sysc R8A779H0_PD_A1E0D0C3>;
108 next-level-cache = <&L 94 next-level-cache = <&L3_CA76>;
109 enable-method = "psci" 95 enable-method = "psci";
110 cpu-idle-states = <&CP 96 cpu-idle-states = <&CPU_SLEEP_0>;
111 clocks = <&cpg CPG_COR 97 clocks = <&cpg CPG_CORE R8A779H0_CLK_ZC3>;
112 operating-points-v2 = 98 operating-points-v2 = <&cluster0_opp>;
113 }; 99 };
114 100
115 idle-states { 101 idle-states {
116 entry-method = "psci"; 102 entry-method = "psci";
117 103
118 CPU_SLEEP_0: cpu-sleep 104 CPU_SLEEP_0: cpu-sleep-0 {
119 compatible = " 105 compatible = "arm,idle-state";
120 arm,psci-suspe 106 arm,psci-suspend-param = <0x0010000>;
121 local-timer-st 107 local-timer-stop;
122 entry-latency- 108 entry-latency-us = <400>;
123 exit-latency-u 109 exit-latency-us = <500>;
124 min-residency- 110 min-residency-us = <4000>;
125 }; 111 };
126 }; 112 };
127 113
128 L3_CA76: cache-controller { 114 L3_CA76: cache-controller {
129 compatible = "cache"; 115 compatible = "cache";
130 power-domains = <&sysc 116 power-domains = <&sysc R8A779H0_PD_A2E0D0>;
131 cache-unified; 117 cache-unified;
132 cache-level = <3>; 118 cache-level = <3>;
133 }; 119 };
134 }; 120 };
135 121
136 extal_clk: extal-clk { 122 extal_clk: extal-clk {
137 compatible = "fixed-clock"; 123 compatible = "fixed-clock";
138 #clock-cells = <0>; 124 #clock-cells = <0>;
139 /* This value must be overridd 125 /* This value must be overridden by the board */
140 clock-frequency = <0>; 126 clock-frequency = <0>;
141 }; 127 };
142 128
143 extalr_clk: extalr-clk { 129 extalr_clk: extalr-clk {
144 compatible = "fixed-clock"; 130 compatible = "fixed-clock";
145 #clock-cells = <0>; 131 #clock-cells = <0>;
146 /* This value must be overridd 132 /* This value must be overridden by the board */
147 clock-frequency = <0>; 133 clock-frequency = <0>;
148 }; 134 };
149 135
150 pmu-a76 { 136 pmu-a76 {
151 compatible = "arm,cortex-a76-p 137 compatible = "arm,cortex-a76-pmu";
152 interrupts-extended = <&gic GI 138 interrupts-extended = <&gic GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
153 }; 139 };
154 140
155 psci { 141 psci {
156 compatible = "arm,psci-1.0", " 142 compatible = "arm,psci-1.0", "arm,psci-0.2";
157 method = "smc"; 143 method = "smc";
158 }; 144 };
159 145
160 /* External SCIF clocks - to be overri 146 /* External SCIF clocks - to be overridden by boards that provide them */
161 scif_clk: scif-clk { 147 scif_clk: scif-clk {
162 compatible = "fixed-clock"; 148 compatible = "fixed-clock";
163 #clock-cells = <0>; 149 #clock-cells = <0>;
164 clock-frequency = <0>; 150 clock-frequency = <0>;
165 }; 151 };
166 152
167 scif_clk2: scif-clk2 { 153 scif_clk2: scif-clk2 {
168 compatible = "fixed-clock"; 154 compatible = "fixed-clock";
169 #clock-cells = <0>; 155 #clock-cells = <0>;
170 clock-frequency = <0>; 156 clock-frequency = <0>;
171 }; 157 };
172 158
173 soc: soc { 159 soc: soc {
174 compatible = "simple-bus"; 160 compatible = "simple-bus";
175 interrupt-parent = <&gic>; 161 interrupt-parent = <&gic>;
176 #address-cells = <2>; 162 #address-cells = <2>;
177 #size-cells = <2>; 163 #size-cells = <2>;
178 ranges; 164 ranges;
179 165
180 rwdt: watchdog@e6020000 { 166 rwdt: watchdog@e6020000 {
181 compatible = "renesas, 167 compatible = "renesas,r8a779h0-wdt",
182 "renesas, 168 "renesas,rcar-gen4-wdt";
183 reg = <0 0xe6020000 0 169 reg = <0 0xe6020000 0 0x0c>;
184 interrupts = <GIC_SPI 170 interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>;
185 clocks = <&cpg CPG_MOD 171 clocks = <&cpg CPG_MOD 907>;
186 power-domains = <&sysc 172 power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
187 resets = <&cpg 907>; 173 resets = <&cpg 907>;
188 status = "disabled"; 174 status = "disabled";
189 }; 175 };
190 176
191 pfc: pinctrl@e6050000 { 177 pfc: pinctrl@e6050000 {
192 compatible = "renesas, 178 compatible = "renesas,pfc-r8a779h0";
193 reg = <0 0xe6050000 0 179 reg = <0 0xe6050000 0 0x16c>, <0 0xe6050800 0 0x16c>,
194 <0 0xe6058000 0 180 <0 0xe6058000 0 0x16c>, <0 0xe6058800 0 0x16c>,
195 <0 0xe6060000 0 181 <0 0xe6060000 0 0x16c>, <0 0xe6060800 0 0x16c>,
196 <0 0xe6061000 0 182 <0 0xe6061000 0 0x16c>, <0 0xe6061800 0 0x16c>;
197 }; 183 };
198 184
199 gpio0: gpio@e6050180 { 185 gpio0: gpio@e6050180 {
200 compatible = "renesas, 186 compatible = "renesas,gpio-r8a779h0",
201 "renesas, 187 "renesas,rcar-gen4-gpio";
202 reg = <0 0xe6050180 0 188 reg = <0 0xe6050180 0 0x54>;
203 interrupts = <GIC_SPI 189 interrupts = <GIC_SPI 619 IRQ_TYPE_LEVEL_HIGH>;
204 #gpio-cells = <2>; 190 #gpio-cells = <2>;
205 gpio-controller; 191 gpio-controller;
206 gpio-ranges = <&pfc 0 192 gpio-ranges = <&pfc 0 0 19>;
207 #interrupt-cells = <2> 193 #interrupt-cells = <2>;
208 interrupt-controller; 194 interrupt-controller;
209 clocks = <&cpg CPG_MOD 195 clocks = <&cpg CPG_MOD 915>;
210 power-domains = <&sysc 196 power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
211 resets = <&cpg 915>; 197 resets = <&cpg 915>;
212 }; 198 };
213 199
214 gpio1: gpio@e6050980 { 200 gpio1: gpio@e6050980 {
215 compatible = "renesas, 201 compatible = "renesas,gpio-r8a779h0",
216 "renesas, 202 "renesas,rcar-gen4-gpio";
217 reg = <0 0xe6050980 0 203 reg = <0 0xe6050980 0 0x54>;
218 interrupts = <GIC_SPI 204 interrupts = <GIC_SPI 623 IRQ_TYPE_LEVEL_HIGH>;
219 #gpio-cells = <2>; 205 #gpio-cells = <2>;
220 gpio-controller; 206 gpio-controller;
221 gpio-ranges = <&pfc 0 207 gpio-ranges = <&pfc 0 32 30>;
222 #interrupt-cells = <2> 208 #interrupt-cells = <2>;
223 interrupt-controller; 209 interrupt-controller;
224 clocks = <&cpg CPG_MOD 210 clocks = <&cpg CPG_MOD 915>;
225 power-domains = <&sysc 211 power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
226 resets = <&cpg 915>; 212 resets = <&cpg 915>;
227 }; 213 };
228 214
229 gpio2: gpio@e6058180 { 215 gpio2: gpio@e6058180 {
230 compatible = "renesas, 216 compatible = "renesas,gpio-r8a779h0",
231 "renesas, 217 "renesas,rcar-gen4-gpio";
232 reg = <0 0xe6058180 0 218 reg = <0 0xe6058180 0 0x54>;
233 interrupts = <GIC_SPI 219 interrupts = <GIC_SPI 627 IRQ_TYPE_LEVEL_HIGH>;
234 #gpio-cells = <2>; 220 #gpio-cells = <2>;
235 gpio-controller; 221 gpio-controller;
236 gpio-ranges = <&pfc 0 222 gpio-ranges = <&pfc 0 64 20>;
237 #interrupt-cells = <2> 223 #interrupt-cells = <2>;
238 interrupt-controller; 224 interrupt-controller;
239 clocks = <&cpg CPG_MOD 225 clocks = <&cpg CPG_MOD 916>;
240 power-domains = <&sysc 226 power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
241 resets = <&cpg 916>; 227 resets = <&cpg 916>;
242 }; 228 };
243 229
244 gpio3: gpio@e6058980 { 230 gpio3: gpio@e6058980 {
245 compatible = "renesas, 231 compatible = "renesas,gpio-r8a779h0",
246 "renesas, 232 "renesas,rcar-gen4-gpio";
247 reg = <0 0xe6058980 0 233 reg = <0 0xe6058980 0 0x54>;
248 interrupts = <GIC_SPI 234 interrupts = <GIC_SPI 631 IRQ_TYPE_LEVEL_HIGH>;
249 #gpio-cells = <2>; 235 #gpio-cells = <2>;
250 gpio-controller; 236 gpio-controller;
251 gpio-ranges = <&pfc 0 237 gpio-ranges = <&pfc 0 96 32>;
252 #interrupt-cells = <2> 238 #interrupt-cells = <2>;
253 interrupt-controller; 239 interrupt-controller;
254 clocks = <&cpg CPG_MOD 240 clocks = <&cpg CPG_MOD 916>;
255 power-domains = <&sysc 241 power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
256 resets = <&cpg 916>; 242 resets = <&cpg 916>;
257 }; 243 };
258 244
259 gpio4: gpio@e6060180 { 245 gpio4: gpio@e6060180 {
260 compatible = "renesas, 246 compatible = "renesas,gpio-r8a779h0",
261 "renesas, 247 "renesas,rcar-gen4-gpio";
262 reg = <0 0xe6060180 0 248 reg = <0 0xe6060180 0 0x54>;
263 interrupts = <GIC_SPI 249 interrupts = <GIC_SPI 635 IRQ_TYPE_LEVEL_HIGH>;
264 #gpio-cells = <2>; 250 #gpio-cells = <2>;
265 gpio-controller; 251 gpio-controller;
266 gpio-ranges = <&pfc 0 252 gpio-ranges = <&pfc 0 128 25>;
267 #interrupt-cells = <2> 253 #interrupt-cells = <2>;
268 interrupt-controller; 254 interrupt-controller;
269 clocks = <&cpg CPG_MOD 255 clocks = <&cpg CPG_MOD 917>;
270 power-domains = <&sysc 256 power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
271 resets = <&cpg 917>; 257 resets = <&cpg 917>;
272 }; 258 };
273 259
274 gpio5: gpio@e6060980 { 260 gpio5: gpio@e6060980 {
275 compatible = "renesas, 261 compatible = "renesas,gpio-r8a779h0",
276 "renesas, 262 "renesas,rcar-gen4-gpio";
277 reg = <0 0xe6060980 0 263 reg = <0 0xe6060980 0 0x54>;
278 interrupts = <GIC_SPI 264 interrupts = <GIC_SPI 639 IRQ_TYPE_LEVEL_HIGH>;
279 #gpio-cells = <2>; 265 #gpio-cells = <2>;
280 gpio-controller; 266 gpio-controller;
281 gpio-ranges = <&pfc 0 267 gpio-ranges = <&pfc 0 160 21>;
282 #interrupt-cells = <2> 268 #interrupt-cells = <2>;
283 interrupt-controller; 269 interrupt-controller;
284 clocks = <&cpg CPG_MOD 270 clocks = <&cpg CPG_MOD 917>;
285 power-domains = <&sysc 271 power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
286 resets = <&cpg 917>; 272 resets = <&cpg 917>;
287 }; 273 };
288 274
289 gpio6: gpio@e6061180 { 275 gpio6: gpio@e6061180 {
290 compatible = "renesas, 276 compatible = "renesas,gpio-r8a779h0",
291 "renesas, 277 "renesas,rcar-gen4-gpio";
292 reg = <0 0xe6061180 0 278 reg = <0 0xe6061180 0 0x54>;
293 interrupts = <GIC_SPI 279 interrupts = <GIC_SPI 643 IRQ_TYPE_LEVEL_HIGH>;
294 #gpio-cells = <2>; 280 #gpio-cells = <2>;
295 gpio-controller; 281 gpio-controller;
296 gpio-ranges = <&pfc 0 282 gpio-ranges = <&pfc 0 192 21>;
297 #interrupt-cells = <2> 283 #interrupt-cells = <2>;
298 interrupt-controller; 284 interrupt-controller;
299 clocks = <&cpg CPG_MOD 285 clocks = <&cpg CPG_MOD 917>;
300 power-domains = <&sysc 286 power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
301 resets = <&cpg 917>; 287 resets = <&cpg 917>;
302 }; 288 };
303 289
304 gpio7: gpio@e6061980 { 290 gpio7: gpio@e6061980 {
305 compatible = "renesas, 291 compatible = "renesas,gpio-r8a779h0",
306 "renesas, 292 "renesas,rcar-gen4-gpio";
307 reg = <0 0xe6061980 0 293 reg = <0 0xe6061980 0 0x54>;
308 interrupts = <GIC_SPI 294 interrupts = <GIC_SPI 647 IRQ_TYPE_LEVEL_HIGH>;
309 #gpio-cells = <2>; 295 #gpio-cells = <2>;
310 gpio-controller; 296 gpio-controller;
311 gpio-ranges = <&pfc 0 297 gpio-ranges = <&pfc 0 224 21>;
312 #interrupt-cells = <2> 298 #interrupt-cells = <2>;
313 interrupt-controller; 299 interrupt-controller;
314 clocks = <&cpg CPG_MOD 300 clocks = <&cpg CPG_MOD 917>;
315 power-domains = <&sysc 301 power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
316 resets = <&cpg 917>; 302 resets = <&cpg 917>;
317 }; 303 };
318 304
319 cmt0: timer@e60f0000 { 305 cmt0: timer@e60f0000 {
320 compatible = "renesas, 306 compatible = "renesas,r8a779h0-cmt0",
321 "renesas, 307 "renesas,rcar-gen4-cmt0";
322 reg = <0 0xe60f0000 0 308 reg = <0 0xe60f0000 0 0x1004>;
323 interrupts = <GIC_SPI 309 interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
324 <GIC_SPI 310 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>;
325 clocks = <&cpg CPG_MOD 311 clocks = <&cpg CPG_MOD 910>;
326 clock-names = "fck"; 312 clock-names = "fck";
327 power-domains = <&sysc 313 power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
328 resets = <&cpg 910>; 314 resets = <&cpg 910>;
329 status = "disabled"; 315 status = "disabled";
330 }; 316 };
331 317
332 cmt1: timer@e6130000 { 318 cmt1: timer@e6130000 {
333 compatible = "renesas, 319 compatible = "renesas,r8a779h0-cmt1",
334 "renesas, 320 "renesas,rcar-gen4-cmt1";
335 reg = <0 0xe6130000 0 321 reg = <0 0xe6130000 0 0x1004>;
336 interrupts = <GIC_SPI 322 interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
337 <GIC_SPI 323 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>,
338 <GIC_SPI 324 <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>,
339 <GIC_SPI 325 <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
340 <GIC_SPI 326 <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>,
341 <GIC_SPI 327 <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>,
342 <GIC_SPI 328 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
343 <GIC_SPI 329 <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>;
344 clocks = <&cpg CPG_MOD 330 clocks = <&cpg CPG_MOD 911>;
345 clock-names = "fck"; 331 clock-names = "fck";
346 power-domains = <&sysc 332 power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
347 resets = <&cpg 911>; 333 resets = <&cpg 911>;
348 status = "disabled"; 334 status = "disabled";
349 }; 335 };
350 336
351 cmt2: timer@e6140000 { 337 cmt2: timer@e6140000 {
352 compatible = "renesas, 338 compatible = "renesas,r8a779h0-cmt1",
353 "renesas, 339 "renesas,rcar-gen4-cmt1";
354 reg = <0 0xe6140000 0 340 reg = <0 0xe6140000 0 0x1004>;
355 interrupts = <GIC_SPI 341 interrupts = <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>,
356 <GIC_SPI 342 <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>,
357 <GIC_SPI 343 <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>,
358 <GIC_SPI 344 <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>,
359 <GIC_SPI 345 <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>,
360 <GIC_SPI 346 <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>,
361 <GIC_SPI 347 <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>,
362 <GIC_SPI 348 <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>;
363 clocks = <&cpg CPG_MOD 349 clocks = <&cpg CPG_MOD 912>;
364 clock-names = "fck"; 350 clock-names = "fck";
365 power-domains = <&sysc 351 power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
366 resets = <&cpg 912>; 352 resets = <&cpg 912>;
367 status = "disabled"; 353 status = "disabled";
368 }; 354 };
369 355
370 cmt3: timer@e6148000 { 356 cmt3: timer@e6148000 {
371 compatible = "renesas, 357 compatible = "renesas,r8a779h0-cmt1",
372 "renesas, 358 "renesas,rcar-gen4-cmt1";
373 reg = <0 0xe6148000 0 359 reg = <0 0xe6148000 0 0x1004>;
374 interrupts = <GIC_SPI 360 interrupts = <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>,
375 <GIC_SPI 361 <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
376 <GIC_SPI 362 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
377 <GIC_SPI 363 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
378 <GIC_SPI 364 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
379 <GIC_SPI 365 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
380 <GIC_SPI 366 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
381 <GIC_SPI 367 <GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>;
382 clocks = <&cpg CPG_MOD 368 clocks = <&cpg CPG_MOD 913>;
383 clock-names = "fck"; 369 clock-names = "fck";
384 power-domains = <&sysc 370 power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
385 resets = <&cpg 913>; 371 resets = <&cpg 913>;
386 status = "disabled"; 372 status = "disabled";
387 }; 373 };
388 374
389 cpg: clock-controller@e6150000 375 cpg: clock-controller@e6150000 {
390 compatible = "renesas, 376 compatible = "renesas,r8a779h0-cpg-mssr";
391 reg = <0 0xe6150000 0 377 reg = <0 0xe6150000 0 0x4000>;
392 clocks = <&extal_clk>, 378 clocks = <&extal_clk>, <&extalr_clk>;
393 clock-names = "extal", 379 clock-names = "extal", "extalr";
394 #clock-cells = <2>; 380 #clock-cells = <2>;
395 #power-domain-cells = 381 #power-domain-cells = <0>;
396 #reset-cells = <1>; 382 #reset-cells = <1>;
397 }; 383 };
398 384
399 rst: reset-controller@e6160000 385 rst: reset-controller@e6160000 {
400 compatible = "renesas, 386 compatible = "renesas,r8a779h0-rst";
401 reg = <0 0xe6160000 0 387 reg = <0 0xe6160000 0 0x4000>;
402 }; 388 };
403 389
404 sysc: system-controller@e61800 390 sysc: system-controller@e6180000 {
405 compatible = "renesas, 391 compatible = "renesas,r8a779h0-sysc";
406 reg = <0 0xe6180000 0 392 reg = <0 0xe6180000 0 0x4000>;
407 #power-domain-cells = 393 #power-domain-cells = <1>;
408 }; 394 };
409 395
410 tsc: thermal@e6198000 { 396 tsc: thermal@e6198000 {
411 compatible = "renesas, 397 compatible = "renesas,r8a779h0-thermal";
412 reg = <0 0xe6198000 0 398 reg = <0 0xe6198000 0 0x200>,
413 <0 0xe61a0000 0 399 <0 0xe61a0000 0 0x200>;
414 clocks = <&cpg CPG_MOD 400 clocks = <&cpg CPG_MOD 919>;
415 power-domains = <&sysc 401 power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
416 resets = <&cpg 919>; 402 resets = <&cpg 919>;
417 #thermal-sensor-cells 403 #thermal-sensor-cells = <1>;
418 }; 404 };
419 405
420 intc_ex: interrupt-controller@ 406 intc_ex: interrupt-controller@e61c0000 {
421 compatible = "renesas, 407 compatible = "renesas,intc-ex-r8a779h0", "renesas,irqc";
422 #interrupt-cells = <2> 408 #interrupt-cells = <2>;
423 interrupt-controller; 409 interrupt-controller;
424 reg = <0 0xe61c0000 0 410 reg = <0 0xe61c0000 0 0x200>;
425 interrupts = <GIC_SPI 411 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
426 <GIC_SPI 412 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
427 <GIC_SPI 413 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
428 <GIC_SPI 414 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
429 <GIC_SPI 415 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
430 <GIC_SPI 416 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
431 clocks = <&cpg CPG_MOD 417 clocks = <&cpg CPG_MOD 611>;
432 power-domains = <&sysc 418 power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
433 resets = <&cpg 611>; 419 resets = <&cpg 611>;
434 }; 420 };
435 421
436 tmu0: timer@e61e0000 { 422 tmu0: timer@e61e0000 {
437 compatible = "renesas, 423 compatible = "renesas,tmu-r8a779h0", "renesas,tmu";
438 reg = <0 0xe61e0000 0 424 reg = <0 0xe61e0000 0 0x30>;
439 interrupts = <GIC_SPI 425 interrupts = <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>,
440 <GIC_SPI 426 <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>,
441 <GIC_SPI 427 <GIC_SPI 291 IRQ_TYPE_LEVEL_HIGH>;
442 interrupt-names = "tun 428 interrupt-names = "tuni0", "tuni1", "tuni2";
443 clocks = <&cpg CPG_MOD 429 clocks = <&cpg CPG_MOD 713>;
444 clock-names = "fck"; 430 clock-names = "fck";
445 power-domains = <&sysc 431 power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
446 resets = <&cpg 713>; 432 resets = <&cpg 713>;
447 status = "disabled"; 433 status = "disabled";
448 }; 434 };
449 435
450 tmu1: timer@e6fc0000 { 436 tmu1: timer@e6fc0000 {
451 compatible = "renesas, 437 compatible = "renesas,tmu-r8a779h0", "renesas,tmu";
452 reg = <0 0xe6fc0000 0 438 reg = <0 0xe6fc0000 0 0x30>;
453 interrupts = <GIC_SPI 439 interrupts = <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>,
454 <GIC_SPI 440 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
455 <GIC_SPI 441 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
456 <GIC_SPI 442 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>;
457 interrupt-names = "tun 443 interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2";
458 clocks = <&cpg CPG_MOD 444 clocks = <&cpg CPG_MOD 714>;
459 clock-names = "fck"; 445 clock-names = "fck";
460 power-domains = <&sysc 446 power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
461 resets = <&cpg 714>; 447 resets = <&cpg 714>;
462 status = "disabled"; 448 status = "disabled";
463 }; 449 };
464 450
465 tmu2: timer@e6fd0000 { 451 tmu2: timer@e6fd0000 {
466 compatible = "renesas, 452 compatible = "renesas,tmu-r8a779h0", "renesas,tmu";
467 reg = <0 0xe6fd0000 0 453 reg = <0 0xe6fd0000 0 0x30>;
468 interrupts = <GIC_SPI 454 interrupts = <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
469 <GIC_SPI 455 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
470 <GIC_SPI 456 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>,
471 <GIC_SPI 457 <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
472 interrupt-names = "tun 458 interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2";
473 clocks = <&cpg CPG_MOD 459 clocks = <&cpg CPG_MOD 715>;
474 clock-names = "fck"; 460 clock-names = "fck";
475 power-domains = <&sysc 461 power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
476 resets = <&cpg 715>; 462 resets = <&cpg 715>;
477 status = "disabled"; 463 status = "disabled";
478 }; 464 };
479 465
480 tmu3: timer@e6fe0000 { 466 tmu3: timer@e6fe0000 {
481 compatible = "renesas, 467 compatible = "renesas,tmu-r8a779h0", "renesas,tmu";
482 reg = <0 0xe6fe0000 0 468 reg = <0 0xe6fe0000 0 0x30>;
483 interrupts = <GIC_SPI 469 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>,
484 <GIC_SPI 470 <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>,
485 <GIC_SPI 471 <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>,
486 <GIC_SPI 472 <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>;
487 interrupt-names = "tun 473 interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2";
488 clocks = <&cpg CPG_MOD 474 clocks = <&cpg CPG_MOD 716>;
489 clock-names = "fck"; 475 clock-names = "fck";
490 power-domains = <&sysc 476 power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
491 resets = <&cpg 716>; 477 resets = <&cpg 716>;
492 status = "disabled"; 478 status = "disabled";
493 }; 479 };
494 480
495 tmu4: timer@ffc00000 { 481 tmu4: timer@ffc00000 {
496 compatible = "renesas, 482 compatible = "renesas,tmu-r8a779h0", "renesas,tmu";
497 reg = <0 0xffc00000 0 483 reg = <0 0xffc00000 0 0x30>;
498 interrupts = <GIC_SPI 484 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
499 <GIC_SPI 485 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>,
500 <GIC_SPI 486 <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>,
501 <GIC_SPI 487 <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
502 interrupt-names = "tun 488 interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2";
503 clocks = <&cpg CPG_MOD 489 clocks = <&cpg CPG_MOD 717>;
504 clock-names = "fck"; 490 clock-names = "fck";
505 power-domains = <&sysc 491 power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
506 resets = <&cpg 717>; 492 resets = <&cpg 717>;
507 status = "disabled"; 493 status = "disabled";
508 }; 494 };
509 495
510 i2c0: i2c@e6500000 { 496 i2c0: i2c@e6500000 {
511 compatible = "renesas, 497 compatible = "renesas,i2c-r8a779h0",
512 "renesas, 498 "renesas,rcar-gen4-i2c";
513 reg = <0 0xe6500000 0 499 reg = <0 0xe6500000 0 0x40>;
514 interrupts = <GIC_SPI 500 interrupts = <GIC_SPI 610 IRQ_TYPE_LEVEL_HIGH>;
515 clocks = <&cpg CPG_MOD 501 clocks = <&cpg CPG_MOD 518>;
516 power-domains = <&sysc 502 power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
517 resets = <&cpg 518>; 503 resets = <&cpg 518>;
518 dmas = <&dmac1 0x91>, 504 dmas = <&dmac1 0x91>, <&dmac1 0x90>,
519 <&dmac2 0x91>, 505 <&dmac2 0x91>, <&dmac2 0x90>;
520 dma-names = "tx", "rx" 506 dma-names = "tx", "rx", "tx", "rx";
521 i2c-scl-internal-delay 507 i2c-scl-internal-delay-ns = <110>;
522 #address-cells = <1>; 508 #address-cells = <1>;
523 #size-cells = <0>; 509 #size-cells = <0>;
524 status = "disabled"; 510 status = "disabled";
525 }; 511 };
526 512
527 i2c1: i2c@e6508000 { 513 i2c1: i2c@e6508000 {
528 compatible = "renesas, 514 compatible = "renesas,i2c-r8a779h0",
529 "renesas, 515 "renesas,rcar-gen4-i2c";
530 reg = <0 0xe6508000 0 516 reg = <0 0xe6508000 0 0x40>;
531 interrupts = <GIC_SPI 517 interrupts = <GIC_SPI 611 IRQ_TYPE_LEVEL_HIGH>;
532 clocks = <&cpg CPG_MOD 518 clocks = <&cpg CPG_MOD 519>;
533 power-domains = <&sysc 519 power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
534 resets = <&cpg 519>; 520 resets = <&cpg 519>;
535 dmas = <&dmac1 0x93>, 521 dmas = <&dmac1 0x93>, <&dmac1 0x92>,
536 <&dmac2 0x93>, 522 <&dmac2 0x93>, <&dmac2 0x92>;
537 dma-names = "tx", "rx" 523 dma-names = "tx", "rx", "tx", "rx";
538 i2c-scl-internal-delay 524 i2c-scl-internal-delay-ns = <110>;
539 #address-cells = <1>; 525 #address-cells = <1>;
540 #size-cells = <0>; 526 #size-cells = <0>;
541 status = "disabled"; 527 status = "disabled";
542 }; 528 };
543 529
544 i2c2: i2c@e6510000 { 530 i2c2: i2c@e6510000 {
545 compatible = "renesas, 531 compatible = "renesas,i2c-r8a779h0",
546 "renesas, 532 "renesas,rcar-gen4-i2c";
547 reg = <0 0xe6510000 0 533 reg = <0 0xe6510000 0 0x40>;
548 interrupts = <GIC_SPI 534 interrupts = <GIC_SPI 612 IRQ_TYPE_LEVEL_HIGH>;
549 clocks = <&cpg CPG_MOD 535 clocks = <&cpg CPG_MOD 520>;
550 power-domains = <&sysc 536 power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
551 resets = <&cpg 520>; 537 resets = <&cpg 520>;
552 dmas = <&dmac1 0x95>, 538 dmas = <&dmac1 0x95>, <&dmac1 0x94>,
553 <&dmac2 0x95>, 539 <&dmac2 0x95>, <&dmac2 0x94>;
554 dma-names = "tx", "rx" 540 dma-names = "tx", "rx", "tx", "rx";
555 i2c-scl-internal-delay 541 i2c-scl-internal-delay-ns = <110>;
556 #address-cells = <1>; 542 #address-cells = <1>;
557 #size-cells = <0>; 543 #size-cells = <0>;
558 status = "disabled"; 544 status = "disabled";
559 }; 545 };
560 546
561 i2c3: i2c@e66d0000 { 547 i2c3: i2c@e66d0000 {
562 compatible = "renesas, 548 compatible = "renesas,i2c-r8a779h0",
563 "renesas, 549 "renesas,rcar-gen4-i2c";
564 reg = <0 0xe66d0000 0 550 reg = <0 0xe66d0000 0 0x40>;
565 interrupts = <GIC_SPI 551 interrupts = <GIC_SPI 613 IRQ_TYPE_LEVEL_HIGH>;
566 clocks = <&cpg CPG_MOD 552 clocks = <&cpg CPG_MOD 521>;
567 power-domains = <&sysc 553 power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
568 resets = <&cpg 521>; 554 resets = <&cpg 521>;
569 dmas = <&dmac1 0x97>, 555 dmas = <&dmac1 0x97>, <&dmac1 0x96>,
570 <&dmac2 0x97>, 556 <&dmac2 0x97>, <&dmac2 0x96>;
571 dma-names = "tx", "rx" 557 dma-names = "tx", "rx", "tx", "rx";
572 i2c-scl-internal-delay 558 i2c-scl-internal-delay-ns = <110>;
573 #address-cells = <1>; 559 #address-cells = <1>;
574 #size-cells = <0>; 560 #size-cells = <0>;
575 status = "disabled"; 561 status = "disabled";
576 }; 562 };
577 563
578 hscif0: serial@e6540000 { 564 hscif0: serial@e6540000 {
579 compatible = "renesas, 565 compatible = "renesas,hscif-r8a779h0",
580 "renesas, 566 "renesas,rcar-gen4-hscif", "renesas,hscif";
581 reg = <0 0xe6540000 0 567 reg = <0 0xe6540000 0 0x60>;
582 interrupts = <GIC_SPI 568 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
583 clocks = <&cpg CPG_MOD 569 clocks = <&cpg CPG_MOD 514>,
584 <&cpg CPG_COR 570 <&cpg CPG_CORE R8A779H0_CLK_SASYNCPERD1>,
585 <&scif_clk>; 571 <&scif_clk>;
586 clock-names = "fck", " 572 clock-names = "fck", "brg_int", "scif_clk";
587 power-domains = <&sysc 573 power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
588 resets = <&cpg 514>; 574 resets = <&cpg 514>;
589 dmas = <&dmac1 0x31>, 575 dmas = <&dmac1 0x31>, <&dmac1 0x30>,
590 <&dmac2 0x31>, 576 <&dmac2 0x31>, <&dmac2 0x30>;
591 dma-names = "tx", "rx" 577 dma-names = "tx", "rx", "tx", "rx";
592 status = "disabled"; 578 status = "disabled";
593 }; 579 };
594 580
595 hscif1: serial@e6550000 { 581 hscif1: serial@e6550000 {
596 compatible = "renesas, 582 compatible = "renesas,hscif-r8a779h0",
597 "renesas, 583 "renesas,rcar-gen4-hscif", "renesas,hscif";
598 reg = <0 0xe6550000 0 584 reg = <0 0xe6550000 0 0x60>;
599 interrupts = <GIC_SPI 585 interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
600 clocks = <&cpg CPG_MOD 586 clocks = <&cpg CPG_MOD 515>,
601 <&cpg CPG_COR 587 <&cpg CPG_CORE R8A779H0_CLK_SASYNCPERD1>,
602 <&scif_clk>; 588 <&scif_clk>;
603 clock-names = "fck", " 589 clock-names = "fck", "brg_int", "scif_clk";
604 power-domains = <&sysc 590 power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
605 resets = <&cpg 515>; 591 resets = <&cpg 515>;
606 dmas = <&dmac1 0x33>, 592 dmas = <&dmac1 0x33>, <&dmac1 0x32>,
607 <&dmac2 0x33>, 593 <&dmac2 0x33>, <&dmac2 0x32>;
608 dma-names = "tx", "rx" 594 dma-names = "tx", "rx", "tx", "rx";
609 status = "disabled"; 595 status = "disabled";
610 }; 596 };
611 597
612 hscif2: serial@e6560000 { 598 hscif2: serial@e6560000 {
613 compatible = "renesas, 599 compatible = "renesas,hscif-r8a779h0",
614 "renesas, 600 "renesas,rcar-gen4-hscif", "renesas,hscif";
615 reg = <0 0xe6560000 0 601 reg = <0 0xe6560000 0 0x60>;
616 interrupts = <GIC_SPI 602 interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>;
617 clocks = <&cpg CPG_MOD 603 clocks = <&cpg CPG_MOD 516>,
618 <&cpg CPG_COR 604 <&cpg CPG_CORE R8A779H0_CLK_SASYNCPERD1>,
619 <&scif_clk2>; 605 <&scif_clk2>;
620 clock-names = "fck", " 606 clock-names = "fck", "brg_int", "scif_clk";
621 power-domains = <&sysc 607 power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
622 resets = <&cpg 516>; 608 resets = <&cpg 516>;
623 dmas = <&dmac1 0x35>, 609 dmas = <&dmac1 0x35>, <&dmac1 0x34>,
624 <&dmac2 0x35>, 610 <&dmac2 0x35>, <&dmac2 0x34>;
625 dma-names = "tx", "rx" 611 dma-names = "tx", "rx", "tx", "rx";
626 status = "disabled"; 612 status = "disabled";
627 }; 613 };
628 614
629 hscif3: serial@e66a0000 { 615 hscif3: serial@e66a0000 {
630 compatible = "renesas, 616 compatible = "renesas,hscif-r8a779h0",
631 "renesas, 617 "renesas,rcar-gen4-hscif", "renesas,hscif";
632 reg = <0 0xe66a0000 0 618 reg = <0 0xe66a0000 0 0x60>;
633 interrupts = <GIC_SPI 619 interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>;
634 clocks = <&cpg CPG_MOD 620 clocks = <&cpg CPG_MOD 517>,
635 <&cpg CPG_COR 621 <&cpg CPG_CORE R8A779H0_CLK_SASYNCPERD1>,
636 <&scif_clk>; 622 <&scif_clk>;
637 clock-names = "fck", " 623 clock-names = "fck", "brg_int", "scif_clk";
638 power-domains = <&sysc 624 power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
639 resets = <&cpg 517>; 625 resets = <&cpg 517>;
640 dmas = <&dmac1 0x37>, 626 dmas = <&dmac1 0x37>, <&dmac1 0x36>,
641 <&dmac2 0x37>, 627 <&dmac2 0x37>, <&dmac2 0x36>;
642 dma-names = "tx", "rx" 628 dma-names = "tx", "rx", "tx", "rx";
643 status = "disabled"; 629 status = "disabled";
644 }; 630 };
645 631
646 canfd: can@e6660000 { <<
647 compatible = "renesas, <<
648 "renesas, <<
649 reg = <0 0xe6660000 0 <<
650 interrupts = <GIC_SPI <<
651 <GIC_SPI <<
652 interrupt-names = "ch_ <<
653 clocks = <&cpg CPG_MOD <<
654 <&cpg CPG_COR <<
655 <&can_clk>; <<
656 clock-names = "fck", " <<
657 assigned-clocks = <&cp <<
658 assigned-clock-rates = <<
659 power-domains = <&sysc <<
660 resets = <&cpg 328>; <<
661 status = "disabled"; <<
662 <<
663 channel0 { <<
664 status = "disa <<
665 }; <<
666 <<
667 channel1 { <<
668 status = "disa <<
669 }; <<
670 <<
671 channel2 { <<
672 status = "disa <<
673 }; <<
674 <<
675 channel3 { <<
676 status = "disa <<
677 }; <<
678 }; <<
679 <<
680 avb0: ethernet@e6800000 { 632 avb0: ethernet@e6800000 {
681 compatible = "renesas, 633 compatible = "renesas,etheravb-r8a779h0",
682 "renesas, 634 "renesas,etheravb-rcar-gen4";
683 reg = <0 0xe6800000 0 635 reg = <0 0xe6800000 0 0x1000>;
684 interrupts = <GIC_SPI 636 interrupts = <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
685 <GIC_SPI 637 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
686 <GIC_SPI 638 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
687 <GIC_SPI 639 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
688 <GIC_SPI 640 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
689 <GIC_SPI 641 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
690 <GIC_SPI 642 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
691 <GIC_SPI 643 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
692 <GIC_SPI 644 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
693 <GIC_SPI 645 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
694 <GIC_SPI 646 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
695 <GIC_SPI 647 <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>,
696 <GIC_SPI 648 <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
697 <GIC_SPI 649 <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>,
698 <GIC_SPI 650 <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>,
699 <GIC_SPI 651 <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>,
700 <GIC_SPI 652 <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>,
701 <GIC_SPI 653 <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>,
702 <GIC_SPI 654 <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>,
703 <GIC_SPI 655 <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>,
704 <GIC_SPI 656 <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>,
705 <GIC_SPI 657 <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>,
706 <GIC_SPI 658 <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>,
707 <GIC_SPI 659 <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>,
708 <GIC_SPI 660 <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
709 interrupt-names = "ch0 661 interrupt-names = "ch0", "ch1", "ch2", "ch3",
710 "ch4 662 "ch4", "ch5", "ch6", "ch7",
711 "ch8 663 "ch8", "ch9", "ch10", "ch11",
712 "ch1 664 "ch12", "ch13", "ch14", "ch15",
713 "ch1 665 "ch16", "ch17", "ch18", "ch19",
714 "ch2 666 "ch20", "ch21", "ch22", "ch23",
715 "ch2 667 "ch24";
716 clocks = <&cpg CPG_MOD 668 clocks = <&cpg CPG_MOD 211>;
717 clock-names = "fck"; 669 clock-names = "fck";
718 power-domains = <&sysc 670 power-domains = <&sysc R8A779H0_PD_C4>;
719 resets = <&cpg 211>; 671 resets = <&cpg 211>;
720 phy-mode = "rgmii"; 672 phy-mode = "rgmii";
721 rx-internal-delay-ps = 673 rx-internal-delay-ps = <0>;
722 tx-internal-delay-ps = 674 tx-internal-delay-ps = <0>;
723 iommus = <&ipmmu_hc 0> 675 iommus = <&ipmmu_hc 0>;
724 #address-cells = <1>; 676 #address-cells = <1>;
725 #size-cells = <0>; 677 #size-cells = <0>;
726 status = "disabled"; 678 status = "disabled";
727 }; 679 };
728 680
729 avb1: ethernet@e6810000 { 681 avb1: ethernet@e6810000 {
730 compatible = "renesas, 682 compatible = "renesas,etheravb-r8a779h0",
731 "renesas, 683 "renesas,etheravb-rcar-gen4";
732 reg = <0 0xe6810000 0 684 reg = <0 0xe6810000 0 0x1000>;
733 interrupts = <GIC_SPI 685 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>,
734 <GIC_SPI 686 <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>,
735 <GIC_SPI 687 <GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH>,
736 <GIC_SPI 688 <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>,
737 <GIC_SPI 689 <GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH>,
738 <GIC_SPI 690 <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH>,
739 <GIC_SPI 691 <GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>,
740 <GIC_SPI 692 <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>,
741 <GIC_SPI 693 <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>,
742 <GIC_SPI 694 <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>,
743 <GIC_SPI 695 <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>,
744 <GIC_SPI 696 <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>,
745 <GIC_SPI 697 <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>,
746 <GIC_SPI 698 <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>,
747 <GIC_SPI 699 <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>,
748 <GIC_SPI 700 <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>,
749 <GIC_SPI 701 <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>,
750 <GIC_SPI 702 <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>,
751 <GIC_SPI 703 <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>,
752 <GIC_SPI 704 <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>,
753 <GIC_SPI 705 <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>,
754 <GIC_SPI 706 <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>,
755 <GIC_SPI 707 <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>,
756 <GIC_SPI 708 <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>,
757 <GIC_SPI 709 <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>;
758 interrupt-names = "ch0 710 interrupt-names = "ch0", "ch1", "ch2", "ch3",
759 "ch4 711 "ch4", "ch5", "ch6", "ch7",
760 "ch8 712 "ch8", "ch9", "ch10", "ch11",
761 "ch1 713 "ch12", "ch13", "ch14", "ch15",
762 "ch1 714 "ch16", "ch17", "ch18", "ch19",
763 "ch2 715 "ch20", "ch21", "ch22", "ch23",
764 "ch2 716 "ch24";
765 clocks = <&cpg CPG_MOD 717 clocks = <&cpg CPG_MOD 212>;
766 clock-names = "fck"; 718 clock-names = "fck";
767 power-domains = <&sysc 719 power-domains = <&sysc R8A779H0_PD_C4>;
768 resets = <&cpg 212>; 720 resets = <&cpg 212>;
769 phy-mode = "rgmii"; 721 phy-mode = "rgmii";
770 rx-internal-delay-ps = 722 rx-internal-delay-ps = <0>;
771 tx-internal-delay-ps = 723 tx-internal-delay-ps = <0>;
772 iommus = <&ipmmu_hc 1> <<
773 #address-cells = <1>; 724 #address-cells = <1>;
774 #size-cells = <0>; 725 #size-cells = <0>;
775 status = "disabled"; 726 status = "disabled";
776 }; 727 };
777 728
778 avb2: ethernet@e6820000 { 729 avb2: ethernet@e6820000 {
779 compatible = "renesas, 730 compatible = "renesas,etheravb-r8a779h0",
780 "renesas, 731 "renesas,etheravb-rcar-gen4";
781 reg = <0 0xe6820000 0 732 reg = <0 0xe6820000 0 0x1000>;
782 interrupts = <GIC_SPI 733 interrupts = <GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>,
783 <GIC_SPI 734 <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>,
784 <GIC_SPI 735 <GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>,
785 <GIC_SPI 736 <GIC_SPI 388 IRQ_TYPE_LEVEL_HIGH>,
786 <GIC_SPI 737 <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>,
787 <GIC_SPI 738 <GIC_SPI 390 IRQ_TYPE_LEVEL_HIGH>,
788 <GIC_SPI 739 <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH>,
789 <GIC_SPI 740 <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH>,
790 <GIC_SPI 741 <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>,
791 <GIC_SPI 742 <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>,
792 <GIC_SPI 743 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
793 <GIC_SPI 744 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
794 <GIC_SPI 745 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
795 <GIC_SPI 746 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
796 <GIC_SPI 747 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
797 <GIC_SPI 748 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
798 <GIC_SPI 749 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
799 <GIC_SPI 750 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
800 <GIC_SPI 751 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
801 <GIC_SPI 752 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
802 <GIC_SPI 753 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
803 <GIC_SPI 754 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
804 <GIC_SPI 755 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
805 <GIC_SPI 756 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
806 <GIC_SPI 757 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>;
807 interrupt-names = "ch0 758 interrupt-names = "ch0", "ch1", "ch2", "ch3",
808 "ch4 759 "ch4", "ch5", "ch6", "ch7",
809 "ch8 760 "ch8", "ch9", "ch10", "ch11",
810 "ch1 761 "ch12", "ch13", "ch14", "ch15",
811 "ch1 762 "ch16", "ch17", "ch18", "ch19",
812 "ch2 763 "ch20", "ch21", "ch22", "ch23",
813 "ch2 764 "ch24";
814 clocks = <&cpg CPG_MOD 765 clocks = <&cpg CPG_MOD 213>;
815 clock-names = "fck"; 766 clock-names = "fck";
816 power-domains = <&sysc 767 power-domains = <&sysc R8A779H0_PD_C4>;
817 resets = <&cpg 213>; 768 resets = <&cpg 213>;
818 phy-mode = "rgmii"; 769 phy-mode = "rgmii";
819 rx-internal-delay-ps = 770 rx-internal-delay-ps = <0>;
820 tx-internal-delay-ps = 771 tx-internal-delay-ps = <0>;
821 iommus = <&ipmmu_hc 2> <<
822 #address-cells = <1>; 772 #address-cells = <1>;
823 #size-cells = <0>; 773 #size-cells = <0>;
824 status = "disabled"; 774 status = "disabled";
825 }; 775 };
826 776
827 pwm0: pwm@e6e30000 { <<
828 compatible = "renesas, <<
829 reg = <0 0xe6e30000 0 <<
830 #pwm-cells = <2>; <<
831 clocks = <&cpg CPG_MOD <<
832 power-domains = <&sysc <<
833 resets = <&cpg 628>; <<
834 status = "disabled"; <<
835 }; <<
836 <<
837 pwm1: pwm@e6e31000 { <<
838 compatible = "renesas, <<
839 reg = <0 0xe6e31000 0 <<
840 #pwm-cells = <2>; <<
841 clocks = <&cpg CPG_MOD <<
842 power-domains = <&sysc <<
843 resets = <&cpg 628>; <<
844 status = "disabled"; <<
845 }; <<
846 <<
847 pwm2: pwm@e6e32000 { <<
848 compatible = "renesas, <<
849 reg = <0 0xe6e32000 0 <<
850 #pwm-cells = <2>; <<
851 clocks = <&cpg CPG_MOD <<
852 power-domains = <&sysc <<
853 resets = <&cpg 628>; <<
854 status = "disabled"; <<
855 }; <<
856 <<
857 pwm3: pwm@e6e33000 { <<
858 compatible = "renesas, <<
859 reg = <0 0xe6e33000 0 <<
860 #pwm-cells = <2>; <<
861 clocks = <&cpg CPG_MOD <<
862 power-domains = <&sysc <<
863 resets = <&cpg 628>; <<
864 status = "disabled"; <<
865 }; <<
866 <<
867 pwm4: pwm@e6e34000 { <<
868 compatible = "renesas, <<
869 reg = <0 0xe6e34000 0 <<
870 #pwm-cells = <2>; <<
871 clocks = <&cpg CPG_MOD <<
872 power-domains = <&sysc <<
873 resets = <&cpg 628>; <<
874 status = "disabled"; <<
875 }; <<
876 <<
877 scif0: serial@e6e60000 { 777 scif0: serial@e6e60000 {
878 compatible = "renesas, 778 compatible = "renesas,scif-r8a779h0",
879 "renesas, 779 "renesas,rcar-gen4-scif", "renesas,scif";
880 reg = <0 0xe6e60000 0 780 reg = <0 0xe6e60000 0 64>;
881 interrupts = <GIC_SPI 781 interrupts = <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>;
882 clocks = <&cpg CPG_MOD 782 clocks = <&cpg CPG_MOD 702>,
883 <&cpg CPG_COR 783 <&cpg CPG_CORE R8A779H0_CLK_SASYNCPERD1>,
884 <&scif_clk>; 784 <&scif_clk>;
885 clock-names = "fck", " 785 clock-names = "fck", "brg_int", "scif_clk";
886 power-domains = <&sysc 786 power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
887 resets = <&cpg 702>; 787 resets = <&cpg 702>;
888 dmas = <&dmac1 0x51>, 788 dmas = <&dmac1 0x51>, <&dmac1 0x50>,
889 <&dmac2 0x51>, 789 <&dmac2 0x51>, <&dmac2 0x50>;
890 dma-names = "tx", "rx" 790 dma-names = "tx", "rx", "tx", "rx";
891 status = "disabled"; 791 status = "disabled";
892 }; 792 };
893 793
894 scif1: serial@e6e68000 { 794 scif1: serial@e6e68000 {
895 compatible = "renesas, 795 compatible = "renesas,scif-r8a779h0",
896 "renesas, 796 "renesas,rcar-gen4-scif", "renesas,scif";
897 reg = <0 0xe6e68000 0 797 reg = <0 0xe6e68000 0 64>;
898 interrupts = <GIC_SPI 798 interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>;
899 clocks = <&cpg CPG_MOD 799 clocks = <&cpg CPG_MOD 703>,
900 <&cpg CPG_COR 800 <&cpg CPG_CORE R8A779H0_CLK_SASYNCPERD1>,
901 <&scif_clk>; 801 <&scif_clk>;
902 clock-names = "fck", " 802 clock-names = "fck", "brg_int", "scif_clk";
903 power-domains = <&sysc 803 power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
904 resets = <&cpg 703>; 804 resets = <&cpg 703>;
905 dmas = <&dmac1 0x53>, 805 dmas = <&dmac1 0x53>, <&dmac1 0x52>,
906 <&dmac2 0x53>, 806 <&dmac2 0x53>, <&dmac2 0x52>;
907 dma-names = "tx", "rx" 807 dma-names = "tx", "rx", "tx", "rx";
908 status = "disabled"; 808 status = "disabled";
909 }; 809 };
910 810
911 scif3: serial@e6c50000 { 811 scif3: serial@e6c50000 {
912 compatible = "renesas, 812 compatible = "renesas,scif-r8a779h0",
913 "renesas, 813 "renesas,rcar-gen4-scif", "renesas,scif";
914 reg = <0 0xe6c50000 0 814 reg = <0 0xe6c50000 0 64>;
915 interrupts = <GIC_SPI 815 interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>;
916 clocks = <&cpg CPG_MOD 816 clocks = <&cpg CPG_MOD 704>,
917 <&cpg CPG_COR 817 <&cpg CPG_CORE R8A779H0_CLK_SASYNCPERD1>,
918 <&scif_clk>; 818 <&scif_clk>;
919 clock-names = "fck", " 819 clock-names = "fck", "brg_int", "scif_clk";
920 power-domains = <&sysc 820 power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
921 resets = <&cpg 704>; 821 resets = <&cpg 704>;
922 dmas = <&dmac1 0x57>, 822 dmas = <&dmac1 0x57>, <&dmac1 0x56>,
923 <&dmac2 0x57>, 823 <&dmac2 0x57>, <&dmac2 0x56>;
924 dma-names = "tx", "rx" 824 dma-names = "tx", "rx", "tx", "rx";
925 status = "disabled"; 825 status = "disabled";
926 }; 826 };
927 827
928 scif4: serial@e6c40000 { 828 scif4: serial@e6c40000 {
929 compatible = "renesas, 829 compatible = "renesas,scif-r8a779h0",
930 "renesas, 830 "renesas,rcar-gen4-scif", "renesas,scif";
931 reg = <0 0xe6c40000 0 831 reg = <0 0xe6c40000 0 64>;
932 interrupts = <GIC_SPI 832 interrupts = <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>;
933 clocks = <&cpg CPG_MOD 833 clocks = <&cpg CPG_MOD 705>,
934 <&cpg CPG_COR 834 <&cpg CPG_CORE R8A779H0_CLK_SASYNCPERD1>,
935 <&scif_clk2>; 835 <&scif_clk2>;
936 clock-names = "fck", " 836 clock-names = "fck", "brg_int", "scif_clk";
937 power-domains = <&sysc 837 power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
938 resets = <&cpg 705>; 838 resets = <&cpg 705>;
939 dmas = <&dmac1 0x59>, 839 dmas = <&dmac1 0x59>, <&dmac1 0x58>,
940 <&dmac2 0x59>, 840 <&dmac2 0x59>, <&dmac2 0x58>;
941 dma-names = "tx", "rx" 841 dma-names = "tx", "rx", "tx", "rx";
942 status = "disabled"; 842 status = "disabled";
943 }; 843 };
944 844
945 msiof0: spi@e6e90000 { 845 msiof0: spi@e6e90000 {
946 compatible = "renesas, 846 compatible = "renesas,msiof-r8a779h0",
947 "renesas, 847 "renesas,rcar-gen4-msiof";
948 reg = <0 0xe6e90000 0 848 reg = <0 0xe6e90000 0 0x0064>;
949 interrupts = <GIC_SPI 849 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
950 clocks = <&cpg CPG_MOD 850 clocks = <&cpg CPG_MOD 618>;
951 dmas = <&dmac1 0x41>, 851 dmas = <&dmac1 0x41>, <&dmac1 0x40>,
952 <&dmac2 0x41>, 852 <&dmac2 0x41>, <&dmac2 0x40>;
953 dma-names = "tx", "rx" 853 dma-names = "tx", "rx", "tx", "rx";
954 power-domains = <&sysc 854 power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
955 resets = <&cpg 618>; 855 resets = <&cpg 618>;
956 #address-cells = <1>; 856 #address-cells = <1>;
957 #size-cells = <0>; 857 #size-cells = <0>;
958 status = "disabled"; 858 status = "disabled";
959 }; 859 };
960 860
961 msiof1: spi@e6ea0000 { 861 msiof1: spi@e6ea0000 {
962 compatible = "renesas, 862 compatible = "renesas,msiof-r8a779h0",
963 "renesas, 863 "renesas,rcar-gen4-msiof";
964 reg = <0 0xe6ea0000 0 864 reg = <0 0xe6ea0000 0 0x0064>;
965 interrupts = <GIC_SPI 865 interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
966 clocks = <&cpg CPG_MOD 866 clocks = <&cpg CPG_MOD 619>;
967 dmas = <&dmac1 0x43>, 867 dmas = <&dmac1 0x43>, <&dmac1 0x42>,
968 <&dmac2 0x43>, 868 <&dmac2 0x43>, <&dmac2 0x42>;
969 dma-names = "tx", "rx" 869 dma-names = "tx", "rx", "tx", "rx";
970 power-domains = <&sysc 870 power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
971 resets = <&cpg 619>; 871 resets = <&cpg 619>;
972 #address-cells = <1>; 872 #address-cells = <1>;
973 #size-cells = <0>; 873 #size-cells = <0>;
974 status = "disabled"; 874 status = "disabled";
975 }; 875 };
976 876
977 msiof2: spi@e6c00000 { 877 msiof2: spi@e6c00000 {
978 compatible = "renesas, 878 compatible = "renesas,msiof-r8a779h0",
979 "renesas, 879 "renesas,rcar-gen4-msiof";
980 reg = <0 0xe6c00000 0 880 reg = <0 0xe6c00000 0 0x0064>;
981 interrupts = <GIC_SPI 881 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>;
982 clocks = <&cpg CPG_MOD 882 clocks = <&cpg CPG_MOD 620>;
983 dmas = <&dmac1 0x45>, 883 dmas = <&dmac1 0x45>, <&dmac1 0x44>,
984 <&dmac2 0x45>, 884 <&dmac2 0x45>, <&dmac2 0x44>;
985 dma-names = "tx", "rx" 885 dma-names = "tx", "rx", "tx", "rx";
986 power-domains = <&sysc 886 power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
987 resets = <&cpg 620>; 887 resets = <&cpg 620>;
988 #address-cells = <1>; 888 #address-cells = <1>;
989 #size-cells = <0>; 889 #size-cells = <0>;
990 status = "disabled"; 890 status = "disabled";
991 }; 891 };
992 892
993 msiof3: spi@e6c10000 { 893 msiof3: spi@e6c10000 {
994 compatible = "renesas, 894 compatible = "renesas,msiof-r8a779h0",
995 "renesas, 895 "renesas,rcar-gen4-msiof";
996 reg = <0 0xe6c10000 0 896 reg = <0 0xe6c10000 0 0x0064>;
997 interrupts = <GIC_SPI 897 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>;
998 clocks = <&cpg CPG_MOD 898 clocks = <&cpg CPG_MOD 621>;
999 dmas = <&dmac1 0x47>, 899 dmas = <&dmac1 0x47>, <&dmac1 0x46>,
1000 <&dmac2 0x47>, 900 <&dmac2 0x47>, <&dmac2 0x46>;
1001 dma-names = "tx", "rx 901 dma-names = "tx", "rx", "tx", "rx";
1002 power-domains = <&sys 902 power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
1003 resets = <&cpg 621>; 903 resets = <&cpg 621>;
1004 #address-cells = <1>; 904 #address-cells = <1>;
1005 #size-cells = <0>; 905 #size-cells = <0>;
1006 status = "disabled"; 906 status = "disabled";
1007 }; 907 };
1008 908
1009 msiof4: spi@e6c20000 { 909 msiof4: spi@e6c20000 {
1010 compatible = "renesas 910 compatible = "renesas,msiof-r8a779h0",
1011 "renesas 911 "renesas,rcar-gen4-msiof";
1012 reg = <0 0xe6c20000 0 912 reg = <0 0xe6c20000 0 0x0064>;
1013 interrupts = <GIC_SPI 913 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
1014 clocks = <&cpg CPG_MO 914 clocks = <&cpg CPG_MOD 622>;
1015 dmas = <&dmac1 0x49>, 915 dmas = <&dmac1 0x49>, <&dmac1 0x48>,
1016 <&dmac2 0x49>, 916 <&dmac2 0x49>, <&dmac2 0x48>;
1017 dma-names = "tx", "rx 917 dma-names = "tx", "rx", "tx", "rx";
1018 power-domains = <&sys 918 power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
1019 resets = <&cpg 622>; 919 resets = <&cpg 622>;
1020 #address-cells = <1>; 920 #address-cells = <1>;
1021 #size-cells = <0>; 921 #size-cells = <0>;
1022 status = "disabled"; 922 status = "disabled";
1023 }; 923 };
1024 924
1025 msiof5: spi@e6c28000 { 925 msiof5: spi@e6c28000 {
1026 compatible = "renesas 926 compatible = "renesas,msiof-r8a779h0",
1027 "renesas 927 "renesas,rcar-gen4-msiof";
1028 reg = <0 0xe6c28000 0 928 reg = <0 0xe6c28000 0 0x0064>;
1029 interrupts = <GIC_SPI 929 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>;
1030 clocks = <&cpg CPG_MO 930 clocks = <&cpg CPG_MOD 623>;
1031 dmas = <&dmac1 0x4b>, 931 dmas = <&dmac1 0x4b>, <&dmac1 0x4a>,
1032 <&dmac2 0x4b>, 932 <&dmac2 0x4b>, <&dmac2 0x4a>;
1033 dma-names = "tx", "rx 933 dma-names = "tx", "rx", "tx", "rx";
1034 power-domains = <&sys 934 power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
1035 resets = <&cpg 623>; 935 resets = <&cpg 623>;
1036 #address-cells = <1>; 936 #address-cells = <1>;
1037 #size-cells = <0>; 937 #size-cells = <0>;
1038 status = "disabled"; 938 status = "disabled";
1039 }; 939 };
1040 940
1041 vin00: video@e6ef0000 { <<
1042 compatible = "renesas <<
1043 "renesas <<
1044 reg = <0 0xe6ef0000 0 <<
1045 interrupts = <GIC_SPI <<
1046 clocks = <&cpg CPG_MO <<
1047 power-domains = <&sys <<
1048 resets = <&cpg 730>; <<
1049 renesas,id = <0>; <<
1050 status = "disabled"; <<
1051 <<
1052 ports { <<
1053 #address-cell <<
1054 #size-cells = <<
1055 <<
1056 port@2 { <<
1057 #addr <<
1058 #size <<
1059 <<
1060 reg = <<
1061 <<
1062 vin00 <<
1063 <<
1064 <<
1065 }; <<
1066 }; <<
1067 }; <<
1068 }; <<
1069 <<
1070 vin01: video@e6ef1000 { <<
1071 compatible = "renesas <<
1072 "renesas <<
1073 reg = <0 0xe6ef1000 0 <<
1074 interrupts = <GIC_SPI <<
1075 clocks = <&cpg CPG_MO <<
1076 power-domains = <&sys <<
1077 resets = <&cpg 731>; <<
1078 renesas,id = <1>; <<
1079 status = "disabled"; <<
1080 <<
1081 ports { <<
1082 #address-cell <<
1083 #size-cells = <<
1084 <<
1085 port@2 { <<
1086 #addr <<
1087 #size <<
1088 <<
1089 reg = <<
1090 <<
1091 vin01 <<
1092 <<
1093 <<
1094 }; <<
1095 }; <<
1096 }; <<
1097 }; <<
1098 <<
1099 vin02: video@e6ef2000 { <<
1100 compatible = "renesas <<
1101 "renesas <<
1102 reg = <0 0xe6ef2000 0 <<
1103 interrupts = <GIC_SPI <<
1104 clocks = <&cpg CPG_MO <<
1105 power-domains = <&sys <<
1106 resets = <&cpg 800>; <<
1107 renesas,id = <2>; <<
1108 status = "disabled"; <<
1109 <<
1110 ports { <<
1111 #address-cell <<
1112 #size-cells = <<
1113 <<
1114 port@2 { <<
1115 #addr <<
1116 #size <<
1117 <<
1118 reg = <<
1119 <<
1120 vin02 <<
1121 <<
1122 <<
1123 }; <<
1124 }; <<
1125 }; <<
1126 }; <<
1127 <<
1128 vin03: video@e6ef3000 { <<
1129 compatible = "renesas <<
1130 "renesas <<
1131 reg = <0 0xe6ef3000 0 <<
1132 interrupts = <GIC_SPI <<
1133 clocks = <&cpg CPG_MO <<
1134 power-domains = <&sys <<
1135 resets = <&cpg 801>; <<
1136 renesas,id = <3>; <<
1137 status = "disabled"; <<
1138 <<
1139 ports { <<
1140 #address-cell <<
1141 #size-cells = <<
1142 <<
1143 port@2 { <<
1144 #addr <<
1145 #size <<
1146 <<
1147 reg = <<
1148 <<
1149 vin03 <<
1150 <<
1151 <<
1152 }; <<
1153 }; <<
1154 }; <<
1155 }; <<
1156 <<
1157 vin04: video@e6ef4000 { <<
1158 compatible = "renesas <<
1159 "renesas <<
1160 reg = <0 0xe6ef4000 0 <<
1161 interrupts = <GIC_SPI <<
1162 clocks = <&cpg CPG_MO <<
1163 power-domains = <&sys <<
1164 resets = <&cpg 802>; <<
1165 renesas,id = <4>; <<
1166 status = "disabled"; <<
1167 <<
1168 ports { <<
1169 #address-cell <<
1170 #size-cells = <<
1171 <<
1172 port@2 { <<
1173 #addr <<
1174 #size <<
1175 <<
1176 reg = <<
1177 <<
1178 vin04 <<
1179 <<
1180 <<
1181 }; <<
1182 }; <<
1183 }; <<
1184 }; <<
1185 <<
1186 vin05: video@e6ef5000 { <<
1187 compatible = "renesas <<
1188 "renesas <<
1189 reg = <0 0xe6ef5000 0 <<
1190 interrupts = <GIC_SPI <<
1191 clocks = <&cpg CPG_MO <<
1192 power-domains = <&sys <<
1193 resets = <&cpg 803>; <<
1194 renesas,id = <5>; <<
1195 status = "disabled"; <<
1196 <<
1197 ports { <<
1198 #address-cell <<
1199 #size-cells = <<
1200 <<
1201 port@2 { <<
1202 #addr <<
1203 #size <<
1204 <<
1205 reg = <<
1206 <<
1207 vin05 <<
1208 <<
1209 <<
1210 }; <<
1211 }; <<
1212 }; <<
1213 }; <<
1214 <<
1215 vin06: video@e6ef6000 { <<
1216 compatible = "renesas <<
1217 "renesas <<
1218 reg = <0 0xe6ef6000 0 <<
1219 interrupts = <GIC_SPI <<
1220 clocks = <&cpg CPG_MO <<
1221 power-domains = <&sys <<
1222 resets = <&cpg 804>; <<
1223 renesas,id = <6>; <<
1224 status = "disabled"; <<
1225 <<
1226 ports { <<
1227 #address-cell <<
1228 #size-cells = <<
1229 <<
1230 port@2 { <<
1231 #addr <<
1232 #size <<
1233 <<
1234 reg = <<
1235 <<
1236 vin06 <<
1237 <<
1238 <<
1239 }; <<
1240 }; <<
1241 }; <<
1242 }; <<
1243 <<
1244 vin07: video@e6ef7000 { <<
1245 compatible = "renesas <<
1246 "renesas <<
1247 reg = <0 0xe6ef7000 0 <<
1248 interrupts = <GIC_SPI <<
1249 clocks = <&cpg CPG_MO <<
1250 power-domains = <&sys <<
1251 resets = <&cpg 805>; <<
1252 renesas,id = <7>; <<
1253 status = "disabled"; <<
1254 <<
1255 ports { <<
1256 #address-cell <<
1257 #size-cells = <<
1258 <<
1259 port@2 { <<
1260 #addr <<
1261 #size <<
1262 <<
1263 reg = <<
1264 <<
1265 vin07 <<
1266 <<
1267 <<
1268 }; <<
1269 }; <<
1270 }; <<
1271 }; <<
1272 <<
1273 vin08: video@e6ef8000 { <<
1274 compatible = "renesas <<
1275 "renesas <<
1276 reg = <0 0xe6ef8000 0 <<
1277 interrupts = <GIC_SPI <<
1278 clocks = <&cpg CPG_MO <<
1279 power-domains = <&sys <<
1280 resets = <&cpg 806>; <<
1281 renesas,id = <8>; <<
1282 status = "disabled"; <<
1283 <<
1284 ports { <<
1285 #address-cell <<
1286 #size-cells = <<
1287 <<
1288 port@2 { <<
1289 #addr <<
1290 #size <<
1291 <<
1292 reg = <<
1293 <<
1294 vin08 <<
1295 <<
1296 <<
1297 }; <<
1298 }; <<
1299 }; <<
1300 }; <<
1301 <<
1302 vin09: video@e6ef9000 { <<
1303 compatible = "renesas <<
1304 "renesas <<
1305 reg = <0 0xe6ef9000 0 <<
1306 interrupts = <GIC_SPI <<
1307 clocks = <&cpg CPG_MO <<
1308 power-domains = <&sys <<
1309 resets = <&cpg 807>; <<
1310 renesas,id = <9>; <<
1311 status = "disabled"; <<
1312 <<
1313 ports { <<
1314 #address-cell <<
1315 #size-cells = <<
1316 <<
1317 port@2 { <<
1318 #addr <<
1319 #size <<
1320 <<
1321 reg = <<
1322 <<
1323 vin09 <<
1324 <<
1325 <<
1326 }; <<
1327 }; <<
1328 }; <<
1329 }; <<
1330 <<
1331 vin10: video@e6efa000 { <<
1332 compatible = "renesas <<
1333 "renesas <<
1334 reg = <0 0xe6efa000 0 <<
1335 interrupts = <GIC_SPI <<
1336 clocks = <&cpg CPG_MO <<
1337 power-domains = <&sys <<
1338 resets = <&cpg 808>; <<
1339 renesas,id = <10>; <<
1340 status = "disabled"; <<
1341 <<
1342 ports { <<
1343 #address-cell <<
1344 #size-cells = <<
1345 <<
1346 port@2 { <<
1347 #addr <<
1348 #size <<
1349 <<
1350 reg = <<
1351 <<
1352 vin10 <<
1353 <<
1354 <<
1355 }; <<
1356 }; <<
1357 }; <<
1358 }; <<
1359 <<
1360 vin11: video@e6efb000 { <<
1361 compatible = "renesas <<
1362 "renesas <<
1363 reg = <0 0xe6efb000 0 <<
1364 interrupts = <GIC_SPI <<
1365 clocks = <&cpg CPG_MO <<
1366 power-domains = <&sys <<
1367 resets = <&cpg 809>; <<
1368 renesas,id = <11>; <<
1369 status = "disabled"; <<
1370 <<
1371 ports { <<
1372 #address-cell <<
1373 #size-cells = <<
1374 <<
1375 port@2 { <<
1376 #addr <<
1377 #size <<
1378 <<
1379 reg = <<
1380 <<
1381 vin11 <<
1382 <<
1383 <<
1384 }; <<
1385 }; <<
1386 }; <<
1387 }; <<
1388 <<
1389 vin12: video@e6efc000 { <<
1390 compatible = "renesas <<
1391 "renesas <<
1392 reg = <0 0xe6efc000 0 <<
1393 interrupts = <GIC_SPI <<
1394 clocks = <&cpg CPG_MO <<
1395 power-domains = <&sys <<
1396 resets = <&cpg 810>; <<
1397 renesas,id = <12>; <<
1398 status = "disabled"; <<
1399 <<
1400 ports { <<
1401 #address-cell <<
1402 #size-cells = <<
1403 <<
1404 port@2 { <<
1405 #addr <<
1406 #size <<
1407 <<
1408 reg = <<
1409 <<
1410 vin12 <<
1411 <<
1412 <<
1413 }; <<
1414 }; <<
1415 }; <<
1416 }; <<
1417 <<
1418 vin13: video@e6efd000 { <<
1419 compatible = "renesas <<
1420 "renesas <<
1421 reg = <0 0xe6efd000 0 <<
1422 interrupts = <GIC_SPI <<
1423 clocks = <&cpg CPG_MO <<
1424 power-domains = <&sys <<
1425 resets = <&cpg 811>; <<
1426 renesas,id = <13>; <<
1427 status = "disabled"; <<
1428 <<
1429 ports { <<
1430 #address-cell <<
1431 #size-cells = <<
1432 <<
1433 port@2 { <<
1434 #addr <<
1435 #size <<
1436 <<
1437 reg = <<
1438 <<
1439 vin13 <<
1440 <<
1441 <<
1442 }; <<
1443 }; <<
1444 }; <<
1445 }; <<
1446 <<
1447 vin14: video@e6efe000 { <<
1448 compatible = "renesas <<
1449 "renesas <<
1450 reg = <0 0xe6efe000 0 <<
1451 interrupts = <GIC_SPI <<
1452 clocks = <&cpg CPG_MO <<
1453 power-domains = <&sys <<
1454 resets = <&cpg 812>; <<
1455 renesas,id = <14>; <<
1456 status = "disabled"; <<
1457 <<
1458 ports { <<
1459 #address-cell <<
1460 #size-cells = <<
1461 <<
1462 port@2 { <<
1463 #addr <<
1464 #size <<
1465 <<
1466 reg = <<
1467 <<
1468 vin14 <<
1469 <<
1470 <<
1471 }; <<
1472 }; <<
1473 }; <<
1474 }; <<
1475 <<
1476 vin15: video@e6eff000 { <<
1477 compatible = "renesas <<
1478 "renesas <<
1479 reg = <0 0xe6eff000 0 <<
1480 interrupts = <GIC_SPI <<
1481 clocks = <&cpg CPG_MO <<
1482 power-domains = <&sys <<
1483 resets = <&cpg 813>; <<
1484 renesas,id = <15>; <<
1485 status = "disabled"; <<
1486 <<
1487 ports { <<
1488 #address-cell <<
1489 #size-cells = <<
1490 <<
1491 port@2 { <<
1492 #addr <<
1493 #size <<
1494 <<
1495 reg = <<
1496 <<
1497 vin15 <<
1498 <<
1499 <<
1500 }; <<
1501 }; <<
1502 }; <<
1503 }; <<
1504 <<
1505 dmac1: dma-controller@e735000 941 dmac1: dma-controller@e7350000 {
1506 compatible = "renesas 942 compatible = "renesas,dmac-r8a779h0",
1507 "renesas 943 "renesas,rcar-gen4-dmac";
1508 reg = <0 0xe7350000 0 944 reg = <0 0xe7350000 0 0x1000>,
1509 <0 0xe7300000 0 945 <0 0xe7300000 0 0x10000>;
1510 interrupts = <GIC_SPI 946 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
1511 <GIC_SPI 947 <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
1512 <GIC_SPI 948 <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
1513 <GIC_SPI 949 <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
1514 <GIC_SPI 950 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
1515 <GIC_SPI 951 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
1516 <GIC_SPI 952 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
1517 <GIC_SPI 953 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
1518 <GIC_SPI 954 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
1519 <GIC_SPI 955 <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
1520 <GIC_SPI 956 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
1521 <GIC_SPI 957 <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
1522 <GIC_SPI 958 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
1523 <GIC_SPI 959 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
1524 <GIC_SPI 960 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
1525 <GIC_SPI 961 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
1526 <GIC_SPI 962 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
1527 interrupt-names = "er 963 interrupt-names = "error",
1528 "ch 964 "ch0", "ch1", "ch2", "ch3", "ch4",
1529 "ch 965 "ch5", "ch6", "ch7", "ch8", "ch9",
1530 "ch 966 "ch10", "ch11", "ch12", "ch13",
1531 "ch 967 "ch14", "ch15";
1532 clocks = <&cpg CPG_MO 968 clocks = <&cpg CPG_MOD 709>;
1533 clock-names = "fck"; 969 clock-names = "fck";
1534 power-domains = <&sys 970 power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
1535 resets = <&cpg 709>; 971 resets = <&cpg 709>;
1536 #dma-cells = <1>; 972 #dma-cells = <1>;
1537 dma-channels = <16>; 973 dma-channels = <16>;
1538 iommus = <&ipmmu_ds0 974 iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>,
1539 <&ipmmu_ds0 975 <&ipmmu_ds0 2>, <&ipmmu_ds0 3>,
1540 <&ipmmu_ds0 976 <&ipmmu_ds0 4>, <&ipmmu_ds0 5>,
1541 <&ipmmu_ds0 977 <&ipmmu_ds0 6>, <&ipmmu_ds0 7>,
1542 <&ipmmu_ds0 978 <&ipmmu_ds0 8>, <&ipmmu_ds0 9>,
1543 <&ipmmu_ds0 979 <&ipmmu_ds0 10>, <&ipmmu_ds0 11>,
1544 <&ipmmu_ds0 980 <&ipmmu_ds0 12>, <&ipmmu_ds0 13>,
1545 <&ipmmu_ds0 981 <&ipmmu_ds0 14>, <&ipmmu_ds0 15>;
1546 }; 982 };
1547 983
1548 dmac2: dma-controller@e735100 984 dmac2: dma-controller@e7351000 {
1549 compatible = "renesas 985 compatible = "renesas,dmac-r8a779h0",
1550 "renesas 986 "renesas,rcar-gen4-dmac";
1551 reg = <0 0xe7351000 0 987 reg = <0 0xe7351000 0 0x1000>,
1552 <0 0xe7310000 0 988 <0 0xe7310000 0 0x10000>;
1553 interrupts = <GIC_SPI 989 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
1554 <GIC_SPI 990 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
1555 <GIC_SPI 991 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
1556 <GIC_SPI 992 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
1557 <GIC_SPI 993 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
1558 <GIC_SPI 994 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
1559 <GIC_SPI 995 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
1560 <GIC_SPI 996 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
1561 <GIC_SPI 997 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
1562 interrupt-names = "er 998 interrupt-names = "error",
1563 "ch 999 "ch0", "ch1", "ch2", "ch3", "ch4",
1564 "ch 1000 "ch5", "ch6", "ch7";
1565 clocks = <&cpg CPG_MO 1001 clocks = <&cpg CPG_MOD 710>;
1566 clock-names = "fck"; 1002 clock-names = "fck";
1567 power-domains = <&sys 1003 power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
1568 resets = <&cpg 710>; 1004 resets = <&cpg 710>;
1569 #dma-cells = <1>; 1005 #dma-cells = <1>;
1570 dma-channels = <8>; 1006 dma-channels = <8>;
1571 iommus = <&ipmmu_ds0 1007 iommus = <&ipmmu_ds0 16>, <&ipmmu_ds0 17>,
1572 <&ipmmu_ds0 1008 <&ipmmu_ds0 18>, <&ipmmu_ds0 19>,
1573 <&ipmmu_ds0 1009 <&ipmmu_ds0 20>, <&ipmmu_ds0 21>,
1574 <&ipmmu_ds0 1010 <&ipmmu_ds0 22>, <&ipmmu_ds0 23>;
1575 }; 1011 };
1576 1012
1577 rcar_sound: sound@ec400000 { <<
1578 compatible = "renesas <<
1579 reg = <0 0xec400000 0 <<
1580 <0 0xec540000 0 <<
1581 <0 0xec541000 0 <<
1582 <0 0xec5a0000 0 <<
1583 reg-names = "sdmc", " <<
1584 clocks = <&cpg CPG_MO <<
1585 clock-names = "ssiu.0 <<
1586 /* #clock-cells is fi <<
1587 #clock-cells = <0>; <<
1588 /* #sound-dai-cells i <<
1589 #sound-dai-cells = <0 <<
1590 <<
1591 power-domains = <&sys <<
1592 resets = <&cpg 2926>, <<
1593 reset-names = "ssiu.0 <<
1594 status = "disabled"; <<
1595 <<
1596 rcar_sound,ssiu { <<
1597 ssiu00: ssiu- <<
1598 dmas <<
1599 dma-n <<
1600 }; <<
1601 ssiu01: ssiu- <<
1602 dmas <<
1603 dma-n <<
1604 }; <<
1605 ssiu02: ssiu- <<
1606 dmas <<
1607 dma-n <<
1608 }; <<
1609 ssiu03: ssiu- <<
1610 dmas <<
1611 dma-n <<
1612 }; <<
1613 ssiu04: ssiu- <<
1614 dmas <<
1615 dma-n <<
1616 }; <<
1617 ssiu05: ssiu- <<
1618 dmas <<
1619 dma-n <<
1620 }; <<
1621 ssiu06: ssiu- <<
1622 dmas <<
1623 dma-n <<
1624 }; <<
1625 ssiu07: ssiu- <<
1626 dmas <<
1627 dma-n <<
1628 }; <<
1629 }; <<
1630 <<
1631 rcar_sound,ssi { <<
1632 ssi0: ssi-0 { <<
1633 inter <<
1634 }; <<
1635 }; <<
1636 }; <<
1637 <<
1638 mmc0: mmc@ee140000 { 1013 mmc0: mmc@ee140000 {
1639 compatible = "renesas 1014 compatible = "renesas,sdhi-r8a779h0",
1640 "renesas 1015 "renesas,rcar-gen4-sdhi";
1641 reg = <0 0xee140000 0 1016 reg = <0 0xee140000 0 0x2000>;
1642 interrupts = <GIC_SPI 1017 interrupts = <GIC_SPI 440 IRQ_TYPE_LEVEL_HIGH>;
1643 clocks = <&cpg CPG_MO 1018 clocks = <&cpg CPG_MOD 706>,
1644 <&cpg CPG_CO 1019 <&cpg CPG_CORE R8A779H0_CLK_SD0H>;
1645 clock-names = "core", 1020 clock-names = "core", "clkh";
1646 power-domains = <&sys 1021 power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
1647 resets = <&cpg 706>; 1022 resets = <&cpg 706>;
1648 max-frequency = <2000 1023 max-frequency = <200000000>;
1649 iommus = <&ipmmu_ds0 1024 iommus = <&ipmmu_ds0 32>;
1650 status = "disabled"; 1025 status = "disabled";
1651 }; 1026 };
1652 1027
1653 rpc: spi@ee200000 { 1028 rpc: spi@ee200000 {
1654 compatible = "renesas 1029 compatible = "renesas,r8a779h0-rpc-if",
1655 "renesas 1030 "renesas,rcar-gen4-rpc-if";
1656 reg = <0 0xee200000 0 1031 reg = <0 0xee200000 0 0x200>,
1657 <0 0x08000000 0 1032 <0 0x08000000 0 0x04000000>,
1658 <0 0xee208000 0 1033 <0 0xee208000 0 0x100>;
1659 reg-names = "regs", " 1034 reg-names = "regs", "dirmap", "wbuf";
1660 interrupts = <GIC_SPI 1035 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
1661 clocks = <&cpg CPG_MO 1036 clocks = <&cpg CPG_MOD 629>;
1662 power-domains = <&sys 1037 power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
1663 resets = <&cpg 629>; 1038 resets = <&cpg 629>;
1664 #address-cells = <1>; 1039 #address-cells = <1>;
1665 #size-cells = <0>; 1040 #size-cells = <0>;
1666 status = "disabled"; 1041 status = "disabled";
1667 }; 1042 };
1668 1043
1669 ipmmu_rt0: iommu@ee480000 { 1044 ipmmu_rt0: iommu@ee480000 {
1670 compatible = "renesas 1045 compatible = "renesas,ipmmu-r8a779h0",
1671 "renesas 1046 "renesas,rcar-gen4-ipmmu-vmsa";
1672 reg = <0 0xee480000 0 1047 reg = <0 0xee480000 0 0x20000>;
1673 renesas,ipmmu-main = 1048 renesas,ipmmu-main = <&ipmmu_mm>;
1674 power-domains = <&sys 1049 power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
1675 #iommu-cells = <1>; 1050 #iommu-cells = <1>;
1676 }; 1051 };
1677 1052
1678 ipmmu_rt1: iommu@ee4c0000 { 1053 ipmmu_rt1: iommu@ee4c0000 {
1679 compatible = "renesas 1054 compatible = "renesas,ipmmu-r8a779h0",
1680 "renesas 1055 "renesas,rcar-gen4-ipmmu-vmsa";
1681 reg = <0 0xee4c0000 0 1056 reg = <0 0xee4c0000 0 0x20000>;
1682 renesas,ipmmu-main = 1057 renesas,ipmmu-main = <&ipmmu_mm>;
1683 power-domains = <&sys 1058 power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
1684 #iommu-cells = <1>; 1059 #iommu-cells = <1>;
1685 }; 1060 };
1686 1061
1687 ipmmu_ds0: iommu@eed00000 { 1062 ipmmu_ds0: iommu@eed00000 {
1688 compatible = "renesas 1063 compatible = "renesas,ipmmu-r8a779h0",
1689 "renesas 1064 "renesas,rcar-gen4-ipmmu-vmsa";
1690 reg = <0 0xeed00000 0 1065 reg = <0 0xeed00000 0 0x20000>;
1691 renesas,ipmmu-main = 1066 renesas,ipmmu-main = <&ipmmu_mm>;
1692 power-domains = <&sys 1067 power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
1693 #iommu-cells = <1>; 1068 #iommu-cells = <1>;
1694 }; 1069 };
1695 1070
1696 ipmmu_hc: iommu@eed40000 { 1071 ipmmu_hc: iommu@eed40000 {
1697 compatible = "renesas 1072 compatible = "renesas,ipmmu-r8a779h0",
1698 "renesas 1073 "renesas,rcar-gen4-ipmmu-vmsa";
1699 reg = <0 0xeed40000 0 1074 reg = <0 0xeed40000 0 0x20000>;
1700 renesas,ipmmu-main = 1075 renesas,ipmmu-main = <&ipmmu_mm>;
1701 power-domains = <&sys 1076 power-domains = <&sysc R8A779H0_PD_C4>;
1702 #iommu-cells = <1>; 1077 #iommu-cells = <1>;
1703 }; 1078 };
1704 1079
1705 ipmmu_ir: iommu@eed80000 { 1080 ipmmu_ir: iommu@eed80000 {
1706 compatible = "renesas 1081 compatible = "renesas,ipmmu-r8a779h0",
1707 "renesas 1082 "renesas,rcar-gen4-ipmmu-vmsa";
1708 reg = <0 0xeed80000 0 1083 reg = <0 0xeed80000 0 0x20000>;
1709 renesas,ipmmu-main = 1084 renesas,ipmmu-main = <&ipmmu_mm>;
1710 power-domains = <&sys 1085 power-domains = <&sysc R8A779H0_PD_C4>;
1711 #iommu-cells = <1>; 1086 #iommu-cells = <1>;
1712 }; 1087 };
1713 1088
1714 ipmmu_vc: iommu@eedc0000 { 1089 ipmmu_vc: iommu@eedc0000 {
1715 compatible = "renesas 1090 compatible = "renesas,ipmmu-r8a779h0",
1716 "renesas 1091 "renesas,rcar-gen4-ipmmu-vmsa";
1717 reg = <0 0xeedc0000 0 1092 reg = <0 0xeedc0000 0 0x20000>;
1718 renesas,ipmmu-main = 1093 renesas,ipmmu-main = <&ipmmu_mm>;
1719 power-domains = <&sys 1094 power-domains = <&sysc R8A779H0_PD_C4>;
1720 #iommu-cells = <1>; 1095 #iommu-cells = <1>;
1721 }; 1096 };
1722 1097
1723 ipmmu_3dg: iommu@eee00000 { 1098 ipmmu_3dg: iommu@eee00000 {
1724 compatible = "renesas 1099 compatible = "renesas,ipmmu-r8a779h0",
1725 "renesas 1100 "renesas,rcar-gen4-ipmmu-vmsa";
1726 reg = <0 0xeee00000 0 1101 reg = <0 0xeee00000 0 0x20000>;
1727 renesas,ipmmu-main = 1102 renesas,ipmmu-main = <&ipmmu_mm>;
1728 power-domains = <&sys 1103 power-domains = <&sysc R8A779H0_PD_C4>;
1729 #iommu-cells = <1>; 1104 #iommu-cells = <1>;
1730 }; 1105 };
1731 1106
1732 ipmmu_vi0: iommu@eee80000 { 1107 ipmmu_vi0: iommu@eee80000 {
1733 compatible = "renesas 1108 compatible = "renesas,ipmmu-r8a779h0",
1734 "renesas 1109 "renesas,rcar-gen4-ipmmu-vmsa";
1735 reg = <0 0xeee80000 0 1110 reg = <0 0xeee80000 0 0x20000>;
1736 renesas,ipmmu-main = 1111 renesas,ipmmu-main = <&ipmmu_mm>;
1737 power-domains = <&sys 1112 power-domains = <&sysc R8A779H0_PD_C4>;
1738 #iommu-cells = <1>; 1113 #iommu-cells = <1>;
1739 }; 1114 };
1740 1115
1741 ipmmu_vi1: iommu@eeec0000 { 1116 ipmmu_vi1: iommu@eeec0000 {
1742 compatible = "renesas 1117 compatible = "renesas,ipmmu-r8a779h0",
1743 "renesas 1118 "renesas,rcar-gen4-ipmmu-vmsa";
1744 reg = <0 0xeeec0000 0 1119 reg = <0 0xeeec0000 0 0x20000>;
1745 renesas,ipmmu-main = 1120 renesas,ipmmu-main = <&ipmmu_mm>;
1746 power-domains = <&sys 1121 power-domains = <&sysc R8A779H0_PD_C4>;
1747 #iommu-cells = <1>; 1122 #iommu-cells = <1>;
1748 }; 1123 };
1749 1124
1750 ipmmu_vip0: iommu@eef00000 { 1125 ipmmu_vip0: iommu@eef00000 {
1751 compatible = "renesas 1126 compatible = "renesas,ipmmu-r8a779h0",
1752 "renesas 1127 "renesas,rcar-gen4-ipmmu-vmsa";
1753 reg = <0 0xeef00000 0 1128 reg = <0 0xeef00000 0 0x20000>;
1754 renesas,ipmmu-main = 1129 renesas,ipmmu-main = <&ipmmu_mm>;
1755 power-domains = <&sys 1130 power-domains = <&sysc R8A779H0_PD_C4>;
1756 #iommu-cells = <1>; 1131 #iommu-cells = <1>;
1757 }; 1132 };
1758 1133
1759 ipmmu_mm: iommu@eefc0000 { 1134 ipmmu_mm: iommu@eefc0000 {
1760 compatible = "renesas 1135 compatible = "renesas,ipmmu-r8a779h0",
1761 "renesas 1136 "renesas,rcar-gen4-ipmmu-vmsa";
1762 reg = <0 0xeefc0000 0 1137 reg = <0 0xeefc0000 0 0x20000>;
1763 interrupts = <GIC_SPI 1138 interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
1764 <GIC_SPI 1139 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>;
1765 power-domains = <&sys 1140 power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
1766 #iommu-cells = <1>; 1141 #iommu-cells = <1>;
1767 }; 1142 };
1768 1143
1769 gic: interrupt-controller@f10 1144 gic: interrupt-controller@f1000000 {
1770 compatible = "arm,gic 1145 compatible = "arm,gic-v3";
1771 #interrupt-cells = <3 1146 #interrupt-cells = <3>;
1772 #address-cells = <0>; 1147 #address-cells = <0>;
1773 interrupt-controller; 1148 interrupt-controller;
1774 reg = <0x0 0xf1000000 1149 reg = <0x0 0xf1000000 0 0x20000>,
1775 <0x0 0xf1060000 1150 <0x0 0xf1060000 0 0x110000>;
1776 interrupts = <GIC_PPI 1151 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
1777 }; 1152 };
1778 1153
1779 csi40: csi2@fe500000 { <<
1780 compatible = "renesas <<
1781 reg = <0 0xfe500000 0 <<
1782 interrupts = <GIC_SPI <<
1783 clocks = <&cpg CPG_MO <<
1784 power-domains = <&sys <<
1785 resets = <&cpg 331>; <<
1786 status = "disabled"; <<
1787 <<
1788 ports { <<
1789 #address-cell <<
1790 #size-cells = <<
1791 <<
1792 port@0 { <<
1793 reg = <<
1794 }; <<
1795 <<
1796 port@1 { <<
1797 reg = <<
1798 csi40 <<
1799 <<
1800 }; <<
1801 }; <<
1802 }; <<
1803 }; <<
1804 <<
1805 csi41: csi2@fe540000 { <<
1806 compatible = "renesas <<
1807 reg = <0 0xfe540000 0 <<
1808 interrupts = <GIC_SPI <<
1809 clocks = <&cpg CPG_MO <<
1810 power-domains = <&sys <<
1811 resets = <&cpg 400>; <<
1812 status = "disabled"; <<
1813 <<
1814 ports { <<
1815 #address-cell <<
1816 #size-cells = <<
1817 <<
1818 port@0 { <<
1819 reg = <<
1820 }; <<
1821 <<
1822 port@1 { <<
1823 reg = <<
1824 csi41 <<
1825 <<
1826 }; <<
1827 }; <<
1828 }; <<
1829 }; <<
1830 <<
1831 isp0: isp@fed00000 { <<
1832 compatible = "renesas <<
1833 "renesas <<
1834 reg = <0 0xfed00000 0 <<
1835 interrupts = <GIC_SPI <<
1836 clocks = <&cpg CPG_MO <<
1837 power-domains = <&sys <<
1838 resets = <&cpg 612>; <<
1839 status = "disabled"; <<
1840 <<
1841 ports { <<
1842 #address-cell <<
1843 #size-cells = <<
1844 <<
1845 port@0 { <<
1846 #addr <<
1847 #size <<
1848 <<
1849 reg = <<
1850 <<
1851 isp0c <<
1852 <<
1853 <<
1854 }; <<
1855 }; <<
1856 <<
1857 port@1 { <<
1858 reg = <<
1859 isp0v <<
1860 <<
1861 }; <<
1862 }; <<
1863 <<
1864 port@2 { <<
1865 reg = <<
1866 isp0v <<
1867 <<
1868 }; <<
1869 }; <<
1870 <<
1871 port@3 { <<
1872 reg = <<
1873 isp0v <<
1874 <<
1875 }; <<
1876 }; <<
1877 <<
1878 port@4 { <<
1879 reg = <<
1880 isp0v <<
1881 <<
1882 }; <<
1883 }; <<
1884 <<
1885 port@5 { <<
1886 reg = <<
1887 isp0v <<
1888 <<
1889 }; <<
1890 }; <<
1891 <<
1892 port@6 { <<
1893 reg = <<
1894 isp0v <<
1895 <<
1896 }; <<
1897 }; <<
1898 <<
1899 port@7 { <<
1900 reg = <<
1901 isp0v <<
1902 <<
1903 }; <<
1904 }; <<
1905 <<
1906 port@8 { <<
1907 reg = <<
1908 isp0v <<
1909 <<
1910 }; <<
1911 }; <<
1912 }; <<
1913 }; <<
1914 <<
1915 isp1: isp@fed20000 { <<
1916 compatible = "renesas <<
1917 "renesas <<
1918 reg = <0 0xfed20000 0 <<
1919 interrupts = <GIC_SPI <<
1920 clocks = <&cpg CPG_MO <<
1921 power-domains = <&sys <<
1922 resets = <&cpg 613>; <<
1923 status = "disabled"; <<
1924 <<
1925 ports { <<
1926 #address-cell <<
1927 #size-cells = <<
1928 <<
1929 port@0 { <<
1930 #addr <<
1931 #size <<
1932 <<
1933 reg = <<
1934 <<
1935 isp1c <<
1936 <<
1937 <<
1938 }; <<
1939 }; <<
1940 <<
1941 port@1 { <<
1942 reg = <<
1943 isp1v <<
1944 <<
1945 }; <<
1946 }; <<
1947 <<
1948 port@2 { <<
1949 reg = <<
1950 isp1v <<
1951 <<
1952 }; <<
1953 }; <<
1954 <<
1955 port@3 { <<
1956 reg = <<
1957 isp1v <<
1958 <<
1959 }; <<
1960 }; <<
1961 <<
1962 port@4 { <<
1963 reg = <<
1964 isp1v <<
1965 <<
1966 }; <<
1967 }; <<
1968 <<
1969 port@5 { <<
1970 reg = <<
1971 isp1v <<
1972 <<
1973 }; <<
1974 }; <<
1975 <<
1976 port@6 { <<
1977 reg = <<
1978 isp1v <<
1979 <<
1980 }; <<
1981 }; <<
1982 <<
1983 port@7 { <<
1984 reg = <<
1985 isp1v <<
1986 <<
1987 }; <<
1988 }; <<
1989 <<
1990 port@8 { <<
1991 reg = <<
1992 isp1v <<
1993 <<
1994 }; <<
1995 }; <<
1996 }; <<
1997 }; <<
1998 <<
1999 prr: chipid@fff00044 { 1154 prr: chipid@fff00044 {
2000 compatible = "renesas 1155 compatible = "renesas,prr";
2001 reg = <0 0xfff00044 0 1156 reg = <0 0xfff00044 0 4>;
2002 }; 1157 };
2003 }; 1158 };
2004 1159
2005 thermal-zones { 1160 thermal-zones {
2006 sensor_thermal_cr52: sensor1- 1161 sensor_thermal_cr52: sensor1-thermal {
2007 polling-delay-passive 1162 polling-delay-passive = <250>;
2008 polling-delay = <1000 1163 polling-delay = <1000>;
2009 thermal-sensors = <&t 1164 thermal-sensors = <&tsc 0>;
2010 1165
2011 trips { 1166 trips {
2012 sensor1_crit: 1167 sensor1_crit: sensor1-crit {
2013 tempe 1168 temperature = <120000>;
2014 hyste 1169 hysteresis = <1000>;
2015 type 1170 type = "critical";
2016 }; 1171 };
2017 }; 1172 };
2018 }; 1173 };
2019 1174
2020 sensor_thermal_ca76: sensor2- 1175 sensor_thermal_ca76: sensor2-thermal {
2021 polling-delay-passive 1176 polling-delay-passive = <250>;
2022 polling-delay = <1000 1177 polling-delay = <1000>;
2023 thermal-sensors = <&t 1178 thermal-sensors = <&tsc 1>;
2024 1179
2025 trips { 1180 trips {
2026 sensor2_crit: 1181 sensor2_crit: sensor2-crit {
2027 tempe 1182 temperature = <120000>;
2028 hyste 1183 hysteresis = <1000>;
2029 type 1184 type = "critical";
2030 }; 1185 };
2031 }; 1186 };
2032 }; 1187 };
2033 }; 1188 };
2034 1189
2035 timer { 1190 timer {
2036 compatible = "arm,armv8-timer 1191 compatible = "arm,armv8-timer";
2037 interrupts-extended = <&gic G 1192 interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
2038 <&gic G 1193 <&gic GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
2039 <&gic G 1194 <&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
2040 <&gic G 1195 <&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>,
2041 <&gic G 1196 <&gic GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>;
2042 interrupt-names = "sec-phys", <<
2043 "hyp-virt"; <<
2044 }; 1197 };
2045 }; 1198 };
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