1 // SPDX-License-Identifier: (GPL-2.0-only OR B 1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 /* 2 /*
3 * Device Tree Source for the R-Car V4M (R8A77 3 * Device Tree Source for the R-Car V4M (R8A779H0) SoC
4 * 4 *
5 * Copyright (C) 2023 Renesas Electronics Corp 5 * Copyright (C) 2023 Renesas Electronics Corp.
6 */ 6 */
7 7
8 #include <dt-bindings/clock/renesas,r8a779h0-c 8 #include <dt-bindings/clock/renesas,r8a779h0-cpg-mssr.h>
9 #include <dt-bindings/interrupt-controller/arm 9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/power/renesas,r8a779h0-s 10 #include <dt-bindings/power/renesas,r8a779h0-sysc.h>
11 11
12 / { 12 / {
13 compatible = "renesas,r8a779h0"; 13 compatible = "renesas,r8a779h0";
14 #address-cells = <2>; 14 #address-cells = <2>;
15 #size-cells = <2>; 15 #size-cells = <2>;
16 16
17 /* External Audio clock - to be overri <<
18 audio_clkin: audio_clkin { <<
19 compatible = "fixed-clock"; <<
20 #clock-cells = <0>; <<
21 clock-frequency = <0>; <<
22 }; <<
23 <<
24 /* External CAN clock - to be overridd <<
25 can_clk: can-clk { <<
26 compatible = "fixed-clock"; <<
27 #clock-cells = <0>; <<
28 clock-frequency = <0>; <<
29 }; <<
30 <<
31 cluster0_opp: opp-table-0 { 17 cluster0_opp: opp-table-0 {
32 compatible = "operating-points 18 compatible = "operating-points-v2";
>> 19 opp-shared;
33 20
34 opp-500000000 { 21 opp-500000000 {
35 opp-hz = /bits/ 64 <50 22 opp-hz = /bits/ 64 <500000000>;
36 opp-microvolt = <82500 23 opp-microvolt = <825000>;
37 clock-latency-ns = <50 24 clock-latency-ns = <500000>;
38 }; 25 };
39 opp-1000000000 { 26 opp-1000000000 {
40 opp-hz = /bits/ 64 <10 27 opp-hz = /bits/ 64 <1000000000>;
41 opp-microvolt = <82500 28 opp-microvolt = <825000>;
42 clock-latency-ns = <50 29 clock-latency-ns = <500000>;
43 }; 30 };
44 }; 31 };
45 32
46 cpus { 33 cpus {
47 #address-cells = <1>; 34 #address-cells = <1>;
48 #size-cells = <0>; 35 #size-cells = <0>;
49 36
50 cpu-map { 37 cpu-map {
51 cluster0 { 38 cluster0 {
52 core0 { 39 core0 {
53 cpu = 40 cpu = <&a76_0>;
54 }; 41 };
55 core1 { 42 core1 {
56 cpu = 43 cpu = <&a76_1>;
57 }; 44 };
58 core2 { 45 core2 {
59 cpu = 46 cpu = <&a76_2>;
60 }; 47 };
61 core3 { 48 core3 {
62 cpu = 49 cpu = <&a76_3>;
63 }; 50 };
64 }; 51 };
65 }; 52 };
66 53
67 a76_0: cpu@0 { 54 a76_0: cpu@0 {
68 compatible = "arm,cort 55 compatible = "arm,cortex-a76";
69 reg = <0>; 56 reg = <0>;
70 device_type = "cpu"; 57 device_type = "cpu";
71 power-domains = <&sysc 58 power-domains = <&sysc R8A779H0_PD_A1E0D0C0>;
72 next-level-cache = <&L 59 next-level-cache = <&L3_CA76>;
73 enable-method = "psci" 60 enable-method = "psci";
74 cpu-idle-states = <&CP 61 cpu-idle-states = <&CPU_SLEEP_0>;
75 clocks = <&cpg CPG_COR 62 clocks = <&cpg CPG_CORE R8A779H0_CLK_ZC0>;
76 operating-points-v2 = 63 operating-points-v2 = <&cluster0_opp>;
77 }; 64 };
78 65
79 a76_1: cpu@100 { 66 a76_1: cpu@100 {
80 compatible = "arm,cort 67 compatible = "arm,cortex-a76";
81 reg = <0x100>; 68 reg = <0x100>;
82 device_type = "cpu"; 69 device_type = "cpu";
83 power-domains = <&sysc 70 power-domains = <&sysc R8A779H0_PD_A1E0D0C1>;
84 next-level-cache = <&L 71 next-level-cache = <&L3_CA76>;
85 enable-method = "psci" 72 enable-method = "psci";
86 cpu-idle-states = <&CP 73 cpu-idle-states = <&CPU_SLEEP_0>;
87 clocks = <&cpg CPG_COR 74 clocks = <&cpg CPG_CORE R8A779H0_CLK_ZC1>;
88 operating-points-v2 = 75 operating-points-v2 = <&cluster0_opp>;
89 }; 76 };
90 77
91 a76_2: cpu@200 { 78 a76_2: cpu@200 {
92 compatible = "arm,cort 79 compatible = "arm,cortex-a76";
93 reg = <0x200>; 80 reg = <0x200>;
94 device_type = "cpu"; 81 device_type = "cpu";
95 power-domains = <&sysc 82 power-domains = <&sysc R8A779H0_PD_A1E0D0C2>;
96 next-level-cache = <&L 83 next-level-cache = <&L3_CA76>;
97 enable-method = "psci" 84 enable-method = "psci";
98 cpu-idle-states = <&CP 85 cpu-idle-states = <&CPU_SLEEP_0>;
99 clocks = <&cpg CPG_COR 86 clocks = <&cpg CPG_CORE R8A779H0_CLK_ZC2>;
100 operating-points-v2 = 87 operating-points-v2 = <&cluster0_opp>;
101 }; 88 };
102 89
103 a76_3: cpu@300 { 90 a76_3: cpu@300 {
104 compatible = "arm,cort 91 compatible = "arm,cortex-a76";
105 reg = <0x300>; 92 reg = <0x300>;
106 device_type = "cpu"; 93 device_type = "cpu";
107 power-domains = <&sysc 94 power-domains = <&sysc R8A779H0_PD_A1E0D0C3>;
108 next-level-cache = <&L 95 next-level-cache = <&L3_CA76>;
109 enable-method = "psci" 96 enable-method = "psci";
110 cpu-idle-states = <&CP 97 cpu-idle-states = <&CPU_SLEEP_0>;
111 clocks = <&cpg CPG_COR 98 clocks = <&cpg CPG_CORE R8A779H0_CLK_ZC3>;
112 operating-points-v2 = 99 operating-points-v2 = <&cluster0_opp>;
113 }; 100 };
114 101
115 idle-states { 102 idle-states {
116 entry-method = "psci"; 103 entry-method = "psci";
117 104
118 CPU_SLEEP_0: cpu-sleep 105 CPU_SLEEP_0: cpu-sleep-0 {
119 compatible = " 106 compatible = "arm,idle-state";
120 arm,psci-suspe 107 arm,psci-suspend-param = <0x0010000>;
121 local-timer-st 108 local-timer-stop;
122 entry-latency- 109 entry-latency-us = <400>;
123 exit-latency-u 110 exit-latency-us = <500>;
124 min-residency- 111 min-residency-us = <4000>;
125 }; 112 };
126 }; 113 };
127 114
128 L3_CA76: cache-controller { 115 L3_CA76: cache-controller {
129 compatible = "cache"; 116 compatible = "cache";
130 power-domains = <&sysc 117 power-domains = <&sysc R8A779H0_PD_A2E0D0>;
131 cache-unified; 118 cache-unified;
132 cache-level = <3>; 119 cache-level = <3>;
133 }; 120 };
134 }; 121 };
135 122
136 extal_clk: extal-clk { 123 extal_clk: extal-clk {
137 compatible = "fixed-clock"; 124 compatible = "fixed-clock";
138 #clock-cells = <0>; 125 #clock-cells = <0>;
139 /* This value must be overridd 126 /* This value must be overridden by the board */
140 clock-frequency = <0>; 127 clock-frequency = <0>;
141 }; 128 };
142 129
143 extalr_clk: extalr-clk { 130 extalr_clk: extalr-clk {
144 compatible = "fixed-clock"; 131 compatible = "fixed-clock";
145 #clock-cells = <0>; 132 #clock-cells = <0>;
146 /* This value must be overridd 133 /* This value must be overridden by the board */
147 clock-frequency = <0>; 134 clock-frequency = <0>;
148 }; 135 };
149 136
150 pmu-a76 { 137 pmu-a76 {
151 compatible = "arm,cortex-a76-p 138 compatible = "arm,cortex-a76-pmu";
152 interrupts-extended = <&gic GI 139 interrupts-extended = <&gic GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
153 }; 140 };
154 141
155 psci { 142 psci {
156 compatible = "arm,psci-1.0", " 143 compatible = "arm,psci-1.0", "arm,psci-0.2";
157 method = "smc"; 144 method = "smc";
158 }; 145 };
159 146
160 /* External SCIF clocks - to be overri !! 147 /* External SCIF clock - to be overridden by boards that provide it */
161 scif_clk: scif-clk { 148 scif_clk: scif-clk {
162 compatible = "fixed-clock"; 149 compatible = "fixed-clock";
163 #clock-cells = <0>; 150 #clock-cells = <0>;
164 clock-frequency = <0>; 151 clock-frequency = <0>;
165 }; 152 };
166 153
167 scif_clk2: scif-clk2 { <<
168 compatible = "fixed-clock"; <<
169 #clock-cells = <0>; <<
170 clock-frequency = <0>; <<
171 }; <<
172 <<
173 soc: soc { 154 soc: soc {
174 compatible = "simple-bus"; 155 compatible = "simple-bus";
175 interrupt-parent = <&gic>; 156 interrupt-parent = <&gic>;
176 #address-cells = <2>; 157 #address-cells = <2>;
177 #size-cells = <2>; 158 #size-cells = <2>;
178 ranges; 159 ranges;
179 160
180 rwdt: watchdog@e6020000 { 161 rwdt: watchdog@e6020000 {
181 compatible = "renesas, 162 compatible = "renesas,r8a779h0-wdt",
182 "renesas, 163 "renesas,rcar-gen4-wdt";
183 reg = <0 0xe6020000 0 164 reg = <0 0xe6020000 0 0x0c>;
184 interrupts = <GIC_SPI 165 interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>;
185 clocks = <&cpg CPG_MOD 166 clocks = <&cpg CPG_MOD 907>;
186 power-domains = <&sysc 167 power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
187 resets = <&cpg 907>; 168 resets = <&cpg 907>;
188 status = "disabled"; 169 status = "disabled";
189 }; 170 };
190 171
191 pfc: pinctrl@e6050000 { 172 pfc: pinctrl@e6050000 {
192 compatible = "renesas, 173 compatible = "renesas,pfc-r8a779h0";
193 reg = <0 0xe6050000 0 174 reg = <0 0xe6050000 0 0x16c>, <0 0xe6050800 0 0x16c>,
194 <0 0xe6058000 0 175 <0 0xe6058000 0 0x16c>, <0 0xe6058800 0 0x16c>,
195 <0 0xe6060000 0 176 <0 0xe6060000 0 0x16c>, <0 0xe6060800 0 0x16c>,
196 <0 0xe6061000 0 177 <0 0xe6061000 0 0x16c>, <0 0xe6061800 0 0x16c>;
197 }; 178 };
198 179
199 gpio0: gpio@e6050180 { 180 gpio0: gpio@e6050180 {
200 compatible = "renesas, 181 compatible = "renesas,gpio-r8a779h0",
201 "renesas, 182 "renesas,rcar-gen4-gpio";
202 reg = <0 0xe6050180 0 183 reg = <0 0xe6050180 0 0x54>;
203 interrupts = <GIC_SPI 184 interrupts = <GIC_SPI 619 IRQ_TYPE_LEVEL_HIGH>;
204 #gpio-cells = <2>; 185 #gpio-cells = <2>;
205 gpio-controller; 186 gpio-controller;
206 gpio-ranges = <&pfc 0 187 gpio-ranges = <&pfc 0 0 19>;
207 #interrupt-cells = <2> 188 #interrupt-cells = <2>;
208 interrupt-controller; 189 interrupt-controller;
209 clocks = <&cpg CPG_MOD 190 clocks = <&cpg CPG_MOD 915>;
210 power-domains = <&sysc 191 power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
211 resets = <&cpg 915>; 192 resets = <&cpg 915>;
212 }; 193 };
213 194
214 gpio1: gpio@e6050980 { 195 gpio1: gpio@e6050980 {
215 compatible = "renesas, 196 compatible = "renesas,gpio-r8a779h0",
216 "renesas, 197 "renesas,rcar-gen4-gpio";
217 reg = <0 0xe6050980 0 198 reg = <0 0xe6050980 0 0x54>;
218 interrupts = <GIC_SPI 199 interrupts = <GIC_SPI 623 IRQ_TYPE_LEVEL_HIGH>;
219 #gpio-cells = <2>; 200 #gpio-cells = <2>;
220 gpio-controller; 201 gpio-controller;
221 gpio-ranges = <&pfc 0 202 gpio-ranges = <&pfc 0 32 30>;
222 #interrupt-cells = <2> 203 #interrupt-cells = <2>;
223 interrupt-controller; 204 interrupt-controller;
224 clocks = <&cpg CPG_MOD 205 clocks = <&cpg CPG_MOD 915>;
225 power-domains = <&sysc 206 power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
226 resets = <&cpg 915>; 207 resets = <&cpg 915>;
227 }; 208 };
228 209
229 gpio2: gpio@e6058180 { 210 gpio2: gpio@e6058180 {
230 compatible = "renesas, 211 compatible = "renesas,gpio-r8a779h0",
231 "renesas, 212 "renesas,rcar-gen4-gpio";
232 reg = <0 0xe6058180 0 213 reg = <0 0xe6058180 0 0x54>;
233 interrupts = <GIC_SPI 214 interrupts = <GIC_SPI 627 IRQ_TYPE_LEVEL_HIGH>;
234 #gpio-cells = <2>; 215 #gpio-cells = <2>;
235 gpio-controller; 216 gpio-controller;
236 gpio-ranges = <&pfc 0 217 gpio-ranges = <&pfc 0 64 20>;
237 #interrupt-cells = <2> 218 #interrupt-cells = <2>;
238 interrupt-controller; 219 interrupt-controller;
239 clocks = <&cpg CPG_MOD 220 clocks = <&cpg CPG_MOD 916>;
240 power-domains = <&sysc 221 power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
241 resets = <&cpg 916>; 222 resets = <&cpg 916>;
242 }; 223 };
243 224
244 gpio3: gpio@e6058980 { 225 gpio3: gpio@e6058980 {
245 compatible = "renesas, 226 compatible = "renesas,gpio-r8a779h0",
246 "renesas, 227 "renesas,rcar-gen4-gpio";
247 reg = <0 0xe6058980 0 228 reg = <0 0xe6058980 0 0x54>;
248 interrupts = <GIC_SPI 229 interrupts = <GIC_SPI 631 IRQ_TYPE_LEVEL_HIGH>;
249 #gpio-cells = <2>; 230 #gpio-cells = <2>;
250 gpio-controller; 231 gpio-controller;
251 gpio-ranges = <&pfc 0 232 gpio-ranges = <&pfc 0 96 32>;
252 #interrupt-cells = <2> 233 #interrupt-cells = <2>;
253 interrupt-controller; 234 interrupt-controller;
254 clocks = <&cpg CPG_MOD 235 clocks = <&cpg CPG_MOD 916>;
255 power-domains = <&sysc 236 power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
256 resets = <&cpg 916>; 237 resets = <&cpg 916>;
257 }; 238 };
258 239
259 gpio4: gpio@e6060180 { 240 gpio4: gpio@e6060180 {
260 compatible = "renesas, 241 compatible = "renesas,gpio-r8a779h0",
261 "renesas, 242 "renesas,rcar-gen4-gpio";
262 reg = <0 0xe6060180 0 243 reg = <0 0xe6060180 0 0x54>;
263 interrupts = <GIC_SPI 244 interrupts = <GIC_SPI 635 IRQ_TYPE_LEVEL_HIGH>;
264 #gpio-cells = <2>; 245 #gpio-cells = <2>;
265 gpio-controller; 246 gpio-controller;
266 gpio-ranges = <&pfc 0 247 gpio-ranges = <&pfc 0 128 25>;
267 #interrupt-cells = <2> 248 #interrupt-cells = <2>;
268 interrupt-controller; 249 interrupt-controller;
269 clocks = <&cpg CPG_MOD 250 clocks = <&cpg CPG_MOD 917>;
270 power-domains = <&sysc 251 power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
271 resets = <&cpg 917>; 252 resets = <&cpg 917>;
272 }; 253 };
273 254
274 gpio5: gpio@e6060980 { 255 gpio5: gpio@e6060980 {
275 compatible = "renesas, 256 compatible = "renesas,gpio-r8a779h0",
276 "renesas, 257 "renesas,rcar-gen4-gpio";
277 reg = <0 0xe6060980 0 258 reg = <0 0xe6060980 0 0x54>;
278 interrupts = <GIC_SPI 259 interrupts = <GIC_SPI 639 IRQ_TYPE_LEVEL_HIGH>;
279 #gpio-cells = <2>; 260 #gpio-cells = <2>;
280 gpio-controller; 261 gpio-controller;
281 gpio-ranges = <&pfc 0 262 gpio-ranges = <&pfc 0 160 21>;
282 #interrupt-cells = <2> 263 #interrupt-cells = <2>;
283 interrupt-controller; 264 interrupt-controller;
284 clocks = <&cpg CPG_MOD 265 clocks = <&cpg CPG_MOD 917>;
285 power-domains = <&sysc 266 power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
286 resets = <&cpg 917>; 267 resets = <&cpg 917>;
287 }; 268 };
288 269
289 gpio6: gpio@e6061180 { 270 gpio6: gpio@e6061180 {
290 compatible = "renesas, 271 compatible = "renesas,gpio-r8a779h0",
291 "renesas, 272 "renesas,rcar-gen4-gpio";
292 reg = <0 0xe6061180 0 273 reg = <0 0xe6061180 0 0x54>;
293 interrupts = <GIC_SPI 274 interrupts = <GIC_SPI 643 IRQ_TYPE_LEVEL_HIGH>;
294 #gpio-cells = <2>; 275 #gpio-cells = <2>;
295 gpio-controller; 276 gpio-controller;
296 gpio-ranges = <&pfc 0 277 gpio-ranges = <&pfc 0 192 21>;
297 #interrupt-cells = <2> 278 #interrupt-cells = <2>;
298 interrupt-controller; 279 interrupt-controller;
299 clocks = <&cpg CPG_MOD 280 clocks = <&cpg CPG_MOD 917>;
300 power-domains = <&sysc 281 power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
301 resets = <&cpg 917>; 282 resets = <&cpg 917>;
302 }; 283 };
303 284
304 gpio7: gpio@e6061980 { 285 gpio7: gpio@e6061980 {
305 compatible = "renesas, 286 compatible = "renesas,gpio-r8a779h0",
306 "renesas, 287 "renesas,rcar-gen4-gpio";
307 reg = <0 0xe6061980 0 288 reg = <0 0xe6061980 0 0x54>;
308 interrupts = <GIC_SPI 289 interrupts = <GIC_SPI 647 IRQ_TYPE_LEVEL_HIGH>;
309 #gpio-cells = <2>; 290 #gpio-cells = <2>;
310 gpio-controller; 291 gpio-controller;
311 gpio-ranges = <&pfc 0 292 gpio-ranges = <&pfc 0 224 21>;
312 #interrupt-cells = <2> 293 #interrupt-cells = <2>;
313 interrupt-controller; 294 interrupt-controller;
314 clocks = <&cpg CPG_MOD 295 clocks = <&cpg CPG_MOD 917>;
315 power-domains = <&sysc 296 power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
316 resets = <&cpg 917>; 297 resets = <&cpg 917>;
317 }; 298 };
318 299
319 cmt0: timer@e60f0000 { <<
320 compatible = "renesas, <<
321 "renesas, <<
322 reg = <0 0xe60f0000 0 <<
323 interrupts = <GIC_SPI <<
324 <GIC_SPI <<
325 clocks = <&cpg CPG_MOD <<
326 clock-names = "fck"; <<
327 power-domains = <&sysc <<
328 resets = <&cpg 910>; <<
329 status = "disabled"; <<
330 }; <<
331 <<
332 cmt1: timer@e6130000 { <<
333 compatible = "renesas, <<
334 "renesas, <<
335 reg = <0 0xe6130000 0 <<
336 interrupts = <GIC_SPI <<
337 <GIC_SPI <<
338 <GIC_SPI <<
339 <GIC_SPI <<
340 <GIC_SPI <<
341 <GIC_SPI <<
342 <GIC_SPI <<
343 <GIC_SPI <<
344 clocks = <&cpg CPG_MOD <<
345 clock-names = "fck"; <<
346 power-domains = <&sysc <<
347 resets = <&cpg 911>; <<
348 status = "disabled"; <<
349 }; <<
350 <<
351 cmt2: timer@e6140000 { <<
352 compatible = "renesas, <<
353 "renesas, <<
354 reg = <0 0xe6140000 0 <<
355 interrupts = <GIC_SPI <<
356 <GIC_SPI <<
357 <GIC_SPI <<
358 <GIC_SPI <<
359 <GIC_SPI <<
360 <GIC_SPI <<
361 <GIC_SPI <<
362 <GIC_SPI <<
363 clocks = <&cpg CPG_MOD <<
364 clock-names = "fck"; <<
365 power-domains = <&sysc <<
366 resets = <&cpg 912>; <<
367 status = "disabled"; <<
368 }; <<
369 <<
370 cmt3: timer@e6148000 { <<
371 compatible = "renesas, <<
372 "renesas, <<
373 reg = <0 0xe6148000 0 <<
374 interrupts = <GIC_SPI <<
375 <GIC_SPI <<
376 <GIC_SPI <<
377 <GIC_SPI <<
378 <GIC_SPI <<
379 <GIC_SPI <<
380 <GIC_SPI <<
381 <GIC_SPI <<
382 clocks = <&cpg CPG_MOD <<
383 clock-names = "fck"; <<
384 power-domains = <&sysc <<
385 resets = <&cpg 913>; <<
386 status = "disabled"; <<
387 }; <<
388 <<
389 cpg: clock-controller@e6150000 300 cpg: clock-controller@e6150000 {
390 compatible = "renesas, 301 compatible = "renesas,r8a779h0-cpg-mssr";
391 reg = <0 0xe6150000 0 302 reg = <0 0xe6150000 0 0x4000>;
392 clocks = <&extal_clk>, 303 clocks = <&extal_clk>, <&extalr_clk>;
393 clock-names = "extal", 304 clock-names = "extal", "extalr";
394 #clock-cells = <2>; 305 #clock-cells = <2>;
395 #power-domain-cells = 306 #power-domain-cells = <0>;
396 #reset-cells = <1>; 307 #reset-cells = <1>;
397 }; 308 };
398 309
399 rst: reset-controller@e6160000 310 rst: reset-controller@e6160000 {
400 compatible = "renesas, 311 compatible = "renesas,r8a779h0-rst";
401 reg = <0 0xe6160000 0 312 reg = <0 0xe6160000 0 0x4000>;
402 }; 313 };
403 314
404 sysc: system-controller@e61800 315 sysc: system-controller@e6180000 {
405 compatible = "renesas, 316 compatible = "renesas,r8a779h0-sysc";
406 reg = <0 0xe6180000 0 317 reg = <0 0xe6180000 0 0x4000>;
407 #power-domain-cells = 318 #power-domain-cells = <1>;
408 }; 319 };
409 320
410 tsc: thermal@e6198000 { <<
411 compatible = "renesas, <<
412 reg = <0 0xe6198000 0 <<
413 <0 0xe61a0000 0 <<
414 clocks = <&cpg CPG_MOD <<
415 power-domains = <&sysc <<
416 resets = <&cpg 919>; <<
417 #thermal-sensor-cells <<
418 }; <<
419 <<
420 intc_ex: interrupt-controller@ <<
421 compatible = "renesas, <<
422 #interrupt-cells = <2> <<
423 interrupt-controller; <<
424 reg = <0 0xe61c0000 0 <<
425 interrupts = <GIC_SPI <<
426 <GIC_SPI <<
427 <GIC_SPI <<
428 <GIC_SPI <<
429 <GIC_SPI <<
430 <GIC_SPI <<
431 clocks = <&cpg CPG_MOD <<
432 power-domains = <&sysc <<
433 resets = <&cpg 611>; <<
434 }; <<
435 <<
436 tmu0: timer@e61e0000 { <<
437 compatible = "renesas, <<
438 reg = <0 0xe61e0000 0 <<
439 interrupts = <GIC_SPI <<
440 <GIC_SPI <<
441 <GIC_SPI <<
442 interrupt-names = "tun <<
443 clocks = <&cpg CPG_MOD <<
444 clock-names = "fck"; <<
445 power-domains = <&sysc <<
446 resets = <&cpg 713>; <<
447 status = "disabled"; <<
448 }; <<
449 <<
450 tmu1: timer@e6fc0000 { <<
451 compatible = "renesas, <<
452 reg = <0 0xe6fc0000 0 <<
453 interrupts = <GIC_SPI <<
454 <GIC_SPI <<
455 <GIC_SPI <<
456 <GIC_SPI <<
457 interrupt-names = "tun <<
458 clocks = <&cpg CPG_MOD <<
459 clock-names = "fck"; <<
460 power-domains = <&sysc <<
461 resets = <&cpg 714>; <<
462 status = "disabled"; <<
463 }; <<
464 <<
465 tmu2: timer@e6fd0000 { <<
466 compatible = "renesas, <<
467 reg = <0 0xe6fd0000 0 <<
468 interrupts = <GIC_SPI <<
469 <GIC_SPI <<
470 <GIC_SPI <<
471 <GIC_SPI <<
472 interrupt-names = "tun <<
473 clocks = <&cpg CPG_MOD <<
474 clock-names = "fck"; <<
475 power-domains = <&sysc <<
476 resets = <&cpg 715>; <<
477 status = "disabled"; <<
478 }; <<
479 <<
480 tmu3: timer@e6fe0000 { <<
481 compatible = "renesas, <<
482 reg = <0 0xe6fe0000 0 <<
483 interrupts = <GIC_SPI <<
484 <GIC_SPI <<
485 <GIC_SPI <<
486 <GIC_SPI <<
487 interrupt-names = "tun <<
488 clocks = <&cpg CPG_MOD <<
489 clock-names = "fck"; <<
490 power-domains = <&sysc <<
491 resets = <&cpg 716>; <<
492 status = "disabled"; <<
493 }; <<
494 <<
495 tmu4: timer@ffc00000 { <<
496 compatible = "renesas, <<
497 reg = <0 0xffc00000 0 <<
498 interrupts = <GIC_SPI <<
499 <GIC_SPI <<
500 <GIC_SPI <<
501 <GIC_SPI <<
502 interrupt-names = "tun <<
503 clocks = <&cpg CPG_MOD <<
504 clock-names = "fck"; <<
505 power-domains = <&sysc <<
506 resets = <&cpg 717>; <<
507 status = "disabled"; <<
508 }; <<
509 <<
510 i2c0: i2c@e6500000 { 321 i2c0: i2c@e6500000 {
511 compatible = "renesas, 322 compatible = "renesas,i2c-r8a779h0",
512 "renesas, 323 "renesas,rcar-gen4-i2c";
513 reg = <0 0xe6500000 0 324 reg = <0 0xe6500000 0 0x40>;
514 interrupts = <GIC_SPI 325 interrupts = <GIC_SPI 610 IRQ_TYPE_LEVEL_HIGH>;
515 clocks = <&cpg CPG_MOD 326 clocks = <&cpg CPG_MOD 518>;
516 power-domains = <&sysc 327 power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
517 resets = <&cpg 518>; 328 resets = <&cpg 518>;
518 dmas = <&dmac1 0x91>, 329 dmas = <&dmac1 0x91>, <&dmac1 0x90>,
519 <&dmac2 0x91>, 330 <&dmac2 0x91>, <&dmac2 0x90>;
520 dma-names = "tx", "rx" 331 dma-names = "tx", "rx", "tx", "rx";
521 i2c-scl-internal-delay 332 i2c-scl-internal-delay-ns = <110>;
522 #address-cells = <1>; 333 #address-cells = <1>;
523 #size-cells = <0>; 334 #size-cells = <0>;
524 status = "disabled"; 335 status = "disabled";
525 }; 336 };
526 337
527 i2c1: i2c@e6508000 { 338 i2c1: i2c@e6508000 {
528 compatible = "renesas, 339 compatible = "renesas,i2c-r8a779h0",
529 "renesas, 340 "renesas,rcar-gen4-i2c";
530 reg = <0 0xe6508000 0 341 reg = <0 0xe6508000 0 0x40>;
531 interrupts = <GIC_SPI 342 interrupts = <GIC_SPI 611 IRQ_TYPE_LEVEL_HIGH>;
532 clocks = <&cpg CPG_MOD 343 clocks = <&cpg CPG_MOD 519>;
533 power-domains = <&sysc 344 power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
534 resets = <&cpg 519>; 345 resets = <&cpg 519>;
535 dmas = <&dmac1 0x93>, 346 dmas = <&dmac1 0x93>, <&dmac1 0x92>,
536 <&dmac2 0x93>, 347 <&dmac2 0x93>, <&dmac2 0x92>;
537 dma-names = "tx", "rx" 348 dma-names = "tx", "rx", "tx", "rx";
538 i2c-scl-internal-delay 349 i2c-scl-internal-delay-ns = <110>;
539 #address-cells = <1>; 350 #address-cells = <1>;
540 #size-cells = <0>; 351 #size-cells = <0>;
541 status = "disabled"; 352 status = "disabled";
542 }; 353 };
543 354
544 i2c2: i2c@e6510000 { 355 i2c2: i2c@e6510000 {
545 compatible = "renesas, 356 compatible = "renesas,i2c-r8a779h0",
546 "renesas, 357 "renesas,rcar-gen4-i2c";
547 reg = <0 0xe6510000 0 358 reg = <0 0xe6510000 0 0x40>;
548 interrupts = <GIC_SPI 359 interrupts = <GIC_SPI 612 IRQ_TYPE_LEVEL_HIGH>;
549 clocks = <&cpg CPG_MOD 360 clocks = <&cpg CPG_MOD 520>;
550 power-domains = <&sysc 361 power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
551 resets = <&cpg 520>; 362 resets = <&cpg 520>;
552 dmas = <&dmac1 0x95>, 363 dmas = <&dmac1 0x95>, <&dmac1 0x94>,
553 <&dmac2 0x95>, 364 <&dmac2 0x95>, <&dmac2 0x94>;
554 dma-names = "tx", "rx" 365 dma-names = "tx", "rx", "tx", "rx";
555 i2c-scl-internal-delay 366 i2c-scl-internal-delay-ns = <110>;
556 #address-cells = <1>; 367 #address-cells = <1>;
557 #size-cells = <0>; 368 #size-cells = <0>;
558 status = "disabled"; 369 status = "disabled";
559 }; 370 };
560 371
561 i2c3: i2c@e66d0000 { 372 i2c3: i2c@e66d0000 {
562 compatible = "renesas, 373 compatible = "renesas,i2c-r8a779h0",
563 "renesas, 374 "renesas,rcar-gen4-i2c";
564 reg = <0 0xe66d0000 0 375 reg = <0 0xe66d0000 0 0x40>;
565 interrupts = <GIC_SPI 376 interrupts = <GIC_SPI 613 IRQ_TYPE_LEVEL_HIGH>;
566 clocks = <&cpg CPG_MOD 377 clocks = <&cpg CPG_MOD 521>;
567 power-domains = <&sysc 378 power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
568 resets = <&cpg 521>; 379 resets = <&cpg 521>;
569 dmas = <&dmac1 0x97>, 380 dmas = <&dmac1 0x97>, <&dmac1 0x96>,
570 <&dmac2 0x97>, 381 <&dmac2 0x97>, <&dmac2 0x96>;
571 dma-names = "tx", "rx" 382 dma-names = "tx", "rx", "tx", "rx";
572 i2c-scl-internal-delay 383 i2c-scl-internal-delay-ns = <110>;
573 #address-cells = <1>; 384 #address-cells = <1>;
574 #size-cells = <0>; 385 #size-cells = <0>;
575 status = "disabled"; 386 status = "disabled";
576 }; 387 };
577 388
578 hscif0: serial@e6540000 { 389 hscif0: serial@e6540000 {
579 compatible = "renesas, 390 compatible = "renesas,hscif-r8a779h0",
580 "renesas, 391 "renesas,rcar-gen4-hscif", "renesas,hscif";
581 reg = <0 0xe6540000 0 392 reg = <0 0xe6540000 0 0x60>;
582 interrupts = <GIC_SPI 393 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
583 clocks = <&cpg CPG_MOD 394 clocks = <&cpg CPG_MOD 514>,
584 <&cpg CPG_COR 395 <&cpg CPG_CORE R8A779H0_CLK_SASYNCPERD1>,
585 <&scif_clk>; 396 <&scif_clk>;
586 clock-names = "fck", " 397 clock-names = "fck", "brg_int", "scif_clk";
587 power-domains = <&sysc 398 power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
588 resets = <&cpg 514>; 399 resets = <&cpg 514>;
589 dmas = <&dmac1 0x31>, 400 dmas = <&dmac1 0x31>, <&dmac1 0x30>,
590 <&dmac2 0x31>, 401 <&dmac2 0x31>, <&dmac2 0x30>;
591 dma-names = "tx", "rx" 402 dma-names = "tx", "rx", "tx", "rx";
592 status = "disabled"; 403 status = "disabled";
593 }; 404 };
594 405
595 hscif1: serial@e6550000 { <<
596 compatible = "renesas, <<
597 "renesas, <<
598 reg = <0 0xe6550000 0 <<
599 interrupts = <GIC_SPI <<
600 clocks = <&cpg CPG_MOD <<
601 <&cpg CPG_COR <<
602 <&scif_clk>; <<
603 clock-names = "fck", " <<
604 power-domains = <&sysc <<
605 resets = <&cpg 515>; <<
606 dmas = <&dmac1 0x33>, <<
607 <&dmac2 0x33>, <<
608 dma-names = "tx", "rx" <<
609 status = "disabled"; <<
610 }; <<
611 <<
612 hscif2: serial@e6560000 { <<
613 compatible = "renesas, <<
614 "renesas, <<
615 reg = <0 0xe6560000 0 <<
616 interrupts = <GIC_SPI <<
617 clocks = <&cpg CPG_MOD <<
618 <&cpg CPG_COR <<
619 <&scif_clk2>; <<
620 clock-names = "fck", " <<
621 power-domains = <&sysc <<
622 resets = <&cpg 516>; <<
623 dmas = <&dmac1 0x35>, <<
624 <&dmac2 0x35>, <<
625 dma-names = "tx", "rx" <<
626 status = "disabled"; <<
627 }; <<
628 <<
629 hscif3: serial@e66a0000 { <<
630 compatible = "renesas, <<
631 "renesas, <<
632 reg = <0 0xe66a0000 0 <<
633 interrupts = <GIC_SPI <<
634 clocks = <&cpg CPG_MOD <<
635 <&cpg CPG_COR <<
636 <&scif_clk>; <<
637 clock-names = "fck", " <<
638 power-domains = <&sysc <<
639 resets = <&cpg 517>; <<
640 dmas = <&dmac1 0x37>, <<
641 <&dmac2 0x37>, <<
642 dma-names = "tx", "rx" <<
643 status = "disabled"; <<
644 }; <<
645 <<
646 canfd: can@e6660000 { <<
647 compatible = "renesas, <<
648 "renesas, <<
649 reg = <0 0xe6660000 0 <<
650 interrupts = <GIC_SPI <<
651 <GIC_SPI <<
652 interrupt-names = "ch_ <<
653 clocks = <&cpg CPG_MOD <<
654 <&cpg CPG_COR <<
655 <&can_clk>; <<
656 clock-names = "fck", " <<
657 assigned-clocks = <&cp <<
658 assigned-clock-rates = <<
659 power-domains = <&sysc <<
660 resets = <&cpg 328>; <<
661 status = "disabled"; <<
662 <<
663 channel0 { <<
664 status = "disa <<
665 }; <<
666 <<
667 channel1 { <<
668 status = "disa <<
669 }; <<
670 <<
671 channel2 { <<
672 status = "disa <<
673 }; <<
674 <<
675 channel3 { <<
676 status = "disa <<
677 }; <<
678 }; <<
679 <<
680 avb0: ethernet@e6800000 { 406 avb0: ethernet@e6800000 {
681 compatible = "renesas, 407 compatible = "renesas,etheravb-r8a779h0",
682 "renesas, 408 "renesas,etheravb-rcar-gen4";
683 reg = <0 0xe6800000 0 409 reg = <0 0xe6800000 0 0x1000>;
684 interrupts = <GIC_SPI 410 interrupts = <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
685 <GIC_SPI 411 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
686 <GIC_SPI 412 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
687 <GIC_SPI 413 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
688 <GIC_SPI 414 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
689 <GIC_SPI 415 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
690 <GIC_SPI 416 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
691 <GIC_SPI 417 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
692 <GIC_SPI 418 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
693 <GIC_SPI 419 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
694 <GIC_SPI 420 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
695 <GIC_SPI 421 <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>,
696 <GIC_SPI 422 <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
697 <GIC_SPI 423 <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>,
698 <GIC_SPI 424 <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>,
699 <GIC_SPI 425 <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>,
700 <GIC_SPI 426 <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>,
701 <GIC_SPI 427 <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>,
702 <GIC_SPI 428 <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>,
703 <GIC_SPI 429 <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>,
704 <GIC_SPI 430 <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>,
705 <GIC_SPI 431 <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>,
706 <GIC_SPI 432 <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>,
707 <GIC_SPI 433 <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>,
708 <GIC_SPI 434 <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
709 interrupt-names = "ch0 435 interrupt-names = "ch0", "ch1", "ch2", "ch3",
710 "ch4 436 "ch4", "ch5", "ch6", "ch7",
711 "ch8 437 "ch8", "ch9", "ch10", "ch11",
712 "ch1 438 "ch12", "ch13", "ch14", "ch15",
713 "ch1 439 "ch16", "ch17", "ch18", "ch19",
714 "ch2 440 "ch20", "ch21", "ch22", "ch23",
715 "ch2 441 "ch24";
716 clocks = <&cpg CPG_MOD 442 clocks = <&cpg CPG_MOD 211>;
717 clock-names = "fck"; 443 clock-names = "fck";
718 power-domains = <&sysc 444 power-domains = <&sysc R8A779H0_PD_C4>;
719 resets = <&cpg 211>; 445 resets = <&cpg 211>;
720 phy-mode = "rgmii"; 446 phy-mode = "rgmii";
721 rx-internal-delay-ps = 447 rx-internal-delay-ps = <0>;
722 tx-internal-delay-ps = 448 tx-internal-delay-ps = <0>;
723 iommus = <&ipmmu_hc 0> <<
724 #address-cells = <1>; 449 #address-cells = <1>;
725 #size-cells = <0>; 450 #size-cells = <0>;
726 status = "disabled"; 451 status = "disabled";
727 }; 452 };
728 453
729 avb1: ethernet@e6810000 { 454 avb1: ethernet@e6810000 {
730 compatible = "renesas, 455 compatible = "renesas,etheravb-r8a779h0",
731 "renesas, 456 "renesas,etheravb-rcar-gen4";
732 reg = <0 0xe6810000 0 457 reg = <0 0xe6810000 0 0x1000>;
733 interrupts = <GIC_SPI 458 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>,
734 <GIC_SPI 459 <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>,
735 <GIC_SPI 460 <GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH>,
736 <GIC_SPI 461 <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>,
737 <GIC_SPI 462 <GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH>,
738 <GIC_SPI 463 <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH>,
739 <GIC_SPI 464 <GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>,
740 <GIC_SPI 465 <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>,
741 <GIC_SPI 466 <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>,
742 <GIC_SPI 467 <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>,
743 <GIC_SPI 468 <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>,
744 <GIC_SPI 469 <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>,
745 <GIC_SPI 470 <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>,
746 <GIC_SPI 471 <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>,
747 <GIC_SPI 472 <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>,
748 <GIC_SPI 473 <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>,
749 <GIC_SPI 474 <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>,
750 <GIC_SPI 475 <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>,
751 <GIC_SPI 476 <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>,
752 <GIC_SPI 477 <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>,
753 <GIC_SPI 478 <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>,
754 <GIC_SPI 479 <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>,
755 <GIC_SPI 480 <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>,
756 <GIC_SPI 481 <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>,
757 <GIC_SPI 482 <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>;
758 interrupt-names = "ch0 483 interrupt-names = "ch0", "ch1", "ch2", "ch3",
759 "ch4 484 "ch4", "ch5", "ch6", "ch7",
760 "ch8 485 "ch8", "ch9", "ch10", "ch11",
761 "ch1 486 "ch12", "ch13", "ch14", "ch15",
762 "ch1 487 "ch16", "ch17", "ch18", "ch19",
763 "ch2 488 "ch20", "ch21", "ch22", "ch23",
764 "ch2 489 "ch24";
765 clocks = <&cpg CPG_MOD 490 clocks = <&cpg CPG_MOD 212>;
766 clock-names = "fck"; 491 clock-names = "fck";
767 power-domains = <&sysc 492 power-domains = <&sysc R8A779H0_PD_C4>;
768 resets = <&cpg 212>; 493 resets = <&cpg 212>;
769 phy-mode = "rgmii"; 494 phy-mode = "rgmii";
770 rx-internal-delay-ps = 495 rx-internal-delay-ps = <0>;
771 tx-internal-delay-ps = 496 tx-internal-delay-ps = <0>;
772 iommus = <&ipmmu_hc 1> <<
773 #address-cells = <1>; 497 #address-cells = <1>;
774 #size-cells = <0>; 498 #size-cells = <0>;
775 status = "disabled"; 499 status = "disabled";
776 }; 500 };
777 501
778 avb2: ethernet@e6820000 { 502 avb2: ethernet@e6820000 {
779 compatible = "renesas, 503 compatible = "renesas,etheravb-r8a779h0",
780 "renesas, 504 "renesas,etheravb-rcar-gen4";
781 reg = <0 0xe6820000 0 505 reg = <0 0xe6820000 0 0x1000>;
782 interrupts = <GIC_SPI 506 interrupts = <GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>,
783 <GIC_SPI 507 <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>,
784 <GIC_SPI 508 <GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>,
785 <GIC_SPI 509 <GIC_SPI 388 IRQ_TYPE_LEVEL_HIGH>,
786 <GIC_SPI 510 <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>,
787 <GIC_SPI 511 <GIC_SPI 390 IRQ_TYPE_LEVEL_HIGH>,
788 <GIC_SPI 512 <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH>,
789 <GIC_SPI 513 <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH>,
790 <GIC_SPI 514 <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>,
791 <GIC_SPI 515 <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>,
792 <GIC_SPI 516 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
793 <GIC_SPI 517 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
794 <GIC_SPI 518 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
795 <GIC_SPI 519 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
796 <GIC_SPI 520 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
797 <GIC_SPI 521 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
798 <GIC_SPI 522 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
799 <GIC_SPI 523 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
800 <GIC_SPI 524 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
801 <GIC_SPI 525 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
802 <GIC_SPI 526 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
803 <GIC_SPI 527 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
804 <GIC_SPI 528 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
805 <GIC_SPI 529 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
806 <GIC_SPI 530 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>;
807 interrupt-names = "ch0 531 interrupt-names = "ch0", "ch1", "ch2", "ch3",
808 "ch4 532 "ch4", "ch5", "ch6", "ch7",
809 "ch8 533 "ch8", "ch9", "ch10", "ch11",
810 "ch1 534 "ch12", "ch13", "ch14", "ch15",
811 "ch1 535 "ch16", "ch17", "ch18", "ch19",
812 "ch2 536 "ch20", "ch21", "ch22", "ch23",
813 "ch2 537 "ch24";
814 clocks = <&cpg CPG_MOD 538 clocks = <&cpg CPG_MOD 213>;
815 clock-names = "fck"; 539 clock-names = "fck";
816 power-domains = <&sysc 540 power-domains = <&sysc R8A779H0_PD_C4>;
817 resets = <&cpg 213>; 541 resets = <&cpg 213>;
818 phy-mode = "rgmii"; 542 phy-mode = "rgmii";
819 rx-internal-delay-ps = 543 rx-internal-delay-ps = <0>;
820 tx-internal-delay-ps = 544 tx-internal-delay-ps = <0>;
821 iommus = <&ipmmu_hc 2> <<
822 #address-cells = <1>; 545 #address-cells = <1>;
823 #size-cells = <0>; 546 #size-cells = <0>;
824 status = "disabled"; 547 status = "disabled";
825 }; 548 };
826 549
827 pwm0: pwm@e6e30000 { <<
828 compatible = "renesas, <<
829 reg = <0 0xe6e30000 0 <<
830 #pwm-cells = <2>; <<
831 clocks = <&cpg CPG_MOD <<
832 power-domains = <&sysc <<
833 resets = <&cpg 628>; <<
834 status = "disabled"; <<
835 }; <<
836 <<
837 pwm1: pwm@e6e31000 { <<
838 compatible = "renesas, <<
839 reg = <0 0xe6e31000 0 <<
840 #pwm-cells = <2>; <<
841 clocks = <&cpg CPG_MOD <<
842 power-domains = <&sysc <<
843 resets = <&cpg 628>; <<
844 status = "disabled"; <<
845 }; <<
846 <<
847 pwm2: pwm@e6e32000 { <<
848 compatible = "renesas, <<
849 reg = <0 0xe6e32000 0 <<
850 #pwm-cells = <2>; <<
851 clocks = <&cpg CPG_MOD <<
852 power-domains = <&sysc <<
853 resets = <&cpg 628>; <<
854 status = "disabled"; <<
855 }; <<
856 <<
857 pwm3: pwm@e6e33000 { <<
858 compatible = "renesas, <<
859 reg = <0 0xe6e33000 0 <<
860 #pwm-cells = <2>; <<
861 clocks = <&cpg CPG_MOD <<
862 power-domains = <&sysc <<
863 resets = <&cpg 628>; <<
864 status = "disabled"; <<
865 }; <<
866 <<
867 pwm4: pwm@e6e34000 { <<
868 compatible = "renesas, <<
869 reg = <0 0xe6e34000 0 <<
870 #pwm-cells = <2>; <<
871 clocks = <&cpg CPG_MOD <<
872 power-domains = <&sysc <<
873 resets = <&cpg 628>; <<
874 status = "disabled"; <<
875 }; <<
876 <<
877 scif0: serial@e6e60000 { <<
878 compatible = "renesas, <<
879 "renesas, <<
880 reg = <0 0xe6e60000 0 <<
881 interrupts = <GIC_SPI <<
882 clocks = <&cpg CPG_MOD <<
883 <&cpg CPG_COR <<
884 <&scif_clk>; <<
885 clock-names = "fck", " <<
886 power-domains = <&sysc <<
887 resets = <&cpg 702>; <<
888 dmas = <&dmac1 0x51>, <<
889 <&dmac2 0x51>, <<
890 dma-names = "tx", "rx" <<
891 status = "disabled"; <<
892 }; <<
893 <<
894 scif1: serial@e6e68000 { <<
895 compatible = "renesas, <<
896 "renesas, <<
897 reg = <0 0xe6e68000 0 <<
898 interrupts = <GIC_SPI <<
899 clocks = <&cpg CPG_MOD <<
900 <&cpg CPG_COR <<
901 <&scif_clk>; <<
902 clock-names = "fck", " <<
903 power-domains = <&sysc <<
904 resets = <&cpg 703>; <<
905 dmas = <&dmac1 0x53>, <<
906 <&dmac2 0x53>, <<
907 dma-names = "tx", "rx" <<
908 status = "disabled"; <<
909 }; <<
910 <<
911 scif3: serial@e6c50000 { <<
912 compatible = "renesas, <<
913 "renesas, <<
914 reg = <0 0xe6c50000 0 <<
915 interrupts = <GIC_SPI <<
916 clocks = <&cpg CPG_MOD <<
917 <&cpg CPG_COR <<
918 <&scif_clk>; <<
919 clock-names = "fck", " <<
920 power-domains = <&sysc <<
921 resets = <&cpg 704>; <<
922 dmas = <&dmac1 0x57>, <<
923 <&dmac2 0x57>, <<
924 dma-names = "tx", "rx" <<
925 status = "disabled"; <<
926 }; <<
927 <<
928 scif4: serial@e6c40000 { <<
929 compatible = "renesas, <<
930 "renesas, <<
931 reg = <0 0xe6c40000 0 <<
932 interrupts = <GIC_SPI <<
933 clocks = <&cpg CPG_MOD <<
934 <&cpg CPG_COR <<
935 <&scif_clk2>; <<
936 clock-names = "fck", " <<
937 power-domains = <&sysc <<
938 resets = <&cpg 705>; <<
939 dmas = <&dmac1 0x59>, <<
940 <&dmac2 0x59>, <<
941 dma-names = "tx", "rx" <<
942 status = "disabled"; <<
943 }; <<
944 <<
945 msiof0: spi@e6e90000 { <<
946 compatible = "renesas, <<
947 "renesas, <<
948 reg = <0 0xe6e90000 0 <<
949 interrupts = <GIC_SPI <<
950 clocks = <&cpg CPG_MOD <<
951 dmas = <&dmac1 0x41>, <<
952 <&dmac2 0x41>, <<
953 dma-names = "tx", "rx" <<
954 power-domains = <&sysc <<
955 resets = <&cpg 618>; <<
956 #address-cells = <1>; <<
957 #size-cells = <0>; <<
958 status = "disabled"; <<
959 }; <<
960 <<
961 msiof1: spi@e6ea0000 { <<
962 compatible = "renesas, <<
963 "renesas, <<
964 reg = <0 0xe6ea0000 0 <<
965 interrupts = <GIC_SPI <<
966 clocks = <&cpg CPG_MOD <<
967 dmas = <&dmac1 0x43>, <<
968 <&dmac2 0x43>, <<
969 dma-names = "tx", "rx" <<
970 power-domains = <&sysc <<
971 resets = <&cpg 619>; <<
972 #address-cells = <1>; <<
973 #size-cells = <0>; <<
974 status = "disabled"; <<
975 }; <<
976 <<
977 msiof2: spi@e6c00000 { <<
978 compatible = "renesas, <<
979 "renesas, <<
980 reg = <0 0xe6c00000 0 <<
981 interrupts = <GIC_SPI <<
982 clocks = <&cpg CPG_MOD <<
983 dmas = <&dmac1 0x45>, <<
984 <&dmac2 0x45>, <<
985 dma-names = "tx", "rx" <<
986 power-domains = <&sysc <<
987 resets = <&cpg 620>; <<
988 #address-cells = <1>; <<
989 #size-cells = <0>; <<
990 status = "disabled"; <<
991 }; <<
992 <<
993 msiof3: spi@e6c10000 { <<
994 compatible = "renesas, <<
995 "renesas, <<
996 reg = <0 0xe6c10000 0 <<
997 interrupts = <GIC_SPI <<
998 clocks = <&cpg CPG_MOD <<
999 dmas = <&dmac1 0x47>, <<
1000 <&dmac2 0x47>, <<
1001 dma-names = "tx", "rx <<
1002 power-domains = <&sys <<
1003 resets = <&cpg 621>; <<
1004 #address-cells = <1>; <<
1005 #size-cells = <0>; <<
1006 status = "disabled"; <<
1007 }; <<
1008 <<
1009 msiof4: spi@e6c20000 { <<
1010 compatible = "renesas <<
1011 "renesas <<
1012 reg = <0 0xe6c20000 0 <<
1013 interrupts = <GIC_SPI <<
1014 clocks = <&cpg CPG_MO <<
1015 dmas = <&dmac1 0x49>, <<
1016 <&dmac2 0x49>, <<
1017 dma-names = "tx", "rx <<
1018 power-domains = <&sys <<
1019 resets = <&cpg 622>; <<
1020 #address-cells = <1>; <<
1021 #size-cells = <0>; <<
1022 status = "disabled"; <<
1023 }; <<
1024 <<
1025 msiof5: spi@e6c28000 { <<
1026 compatible = "renesas <<
1027 "renesas <<
1028 reg = <0 0xe6c28000 0 <<
1029 interrupts = <GIC_SPI <<
1030 clocks = <&cpg CPG_MO <<
1031 dmas = <&dmac1 0x4b>, <<
1032 <&dmac2 0x4b>, <<
1033 dma-names = "tx", "rx <<
1034 power-domains = <&sys <<
1035 resets = <&cpg 623>; <<
1036 #address-cells = <1>; <<
1037 #size-cells = <0>; <<
1038 status = "disabled"; <<
1039 }; <<
1040 <<
1041 vin00: video@e6ef0000 { <<
1042 compatible = "renesas <<
1043 "renesas <<
1044 reg = <0 0xe6ef0000 0 <<
1045 interrupts = <GIC_SPI <<
1046 clocks = <&cpg CPG_MO <<
1047 power-domains = <&sys <<
1048 resets = <&cpg 730>; <<
1049 renesas,id = <0>; <<
1050 status = "disabled"; <<
1051 <<
1052 ports { <<
1053 #address-cell <<
1054 #size-cells = <<
1055 <<
1056 port@2 { <<
1057 #addr <<
1058 #size <<
1059 <<
1060 reg = <<
1061 <<
1062 vin00 <<
1063 <<
1064 <<
1065 }; <<
1066 }; <<
1067 }; <<
1068 }; <<
1069 <<
1070 vin01: video@e6ef1000 { <<
1071 compatible = "renesas <<
1072 "renesas <<
1073 reg = <0 0xe6ef1000 0 <<
1074 interrupts = <GIC_SPI <<
1075 clocks = <&cpg CPG_MO <<
1076 power-domains = <&sys <<
1077 resets = <&cpg 731>; <<
1078 renesas,id = <1>; <<
1079 status = "disabled"; <<
1080 <<
1081 ports { <<
1082 #address-cell <<
1083 #size-cells = <<
1084 <<
1085 port@2 { <<
1086 #addr <<
1087 #size <<
1088 <<
1089 reg = <<
1090 <<
1091 vin01 <<
1092 <<
1093 <<
1094 }; <<
1095 }; <<
1096 }; <<
1097 }; <<
1098 <<
1099 vin02: video@e6ef2000 { <<
1100 compatible = "renesas <<
1101 "renesas <<
1102 reg = <0 0xe6ef2000 0 <<
1103 interrupts = <GIC_SPI <<
1104 clocks = <&cpg CPG_MO <<
1105 power-domains = <&sys <<
1106 resets = <&cpg 800>; <<
1107 renesas,id = <2>; <<
1108 status = "disabled"; <<
1109 <<
1110 ports { <<
1111 #address-cell <<
1112 #size-cells = <<
1113 <<
1114 port@2 { <<
1115 #addr <<
1116 #size <<
1117 <<
1118 reg = <<
1119 <<
1120 vin02 <<
1121 <<
1122 <<
1123 }; <<
1124 }; <<
1125 }; <<
1126 }; <<
1127 <<
1128 vin03: video@e6ef3000 { <<
1129 compatible = "renesas <<
1130 "renesas <<
1131 reg = <0 0xe6ef3000 0 <<
1132 interrupts = <GIC_SPI <<
1133 clocks = <&cpg CPG_MO <<
1134 power-domains = <&sys <<
1135 resets = <&cpg 801>; <<
1136 renesas,id = <3>; <<
1137 status = "disabled"; <<
1138 <<
1139 ports { <<
1140 #address-cell <<
1141 #size-cells = <<
1142 <<
1143 port@2 { <<
1144 #addr <<
1145 #size <<
1146 <<
1147 reg = <<
1148 <<
1149 vin03 <<
1150 <<
1151 <<
1152 }; <<
1153 }; <<
1154 }; <<
1155 }; <<
1156 <<
1157 vin04: video@e6ef4000 { <<
1158 compatible = "renesas <<
1159 "renesas <<
1160 reg = <0 0xe6ef4000 0 <<
1161 interrupts = <GIC_SPI <<
1162 clocks = <&cpg CPG_MO <<
1163 power-domains = <&sys <<
1164 resets = <&cpg 802>; <<
1165 renesas,id = <4>; <<
1166 status = "disabled"; <<
1167 <<
1168 ports { <<
1169 #address-cell <<
1170 #size-cells = <<
1171 <<
1172 port@2 { <<
1173 #addr <<
1174 #size <<
1175 <<
1176 reg = <<
1177 <<
1178 vin04 <<
1179 <<
1180 <<
1181 }; <<
1182 }; <<
1183 }; <<
1184 }; <<
1185 <<
1186 vin05: video@e6ef5000 { <<
1187 compatible = "renesas <<
1188 "renesas <<
1189 reg = <0 0xe6ef5000 0 <<
1190 interrupts = <GIC_SPI <<
1191 clocks = <&cpg CPG_MO <<
1192 power-domains = <&sys <<
1193 resets = <&cpg 803>; <<
1194 renesas,id = <5>; <<
1195 status = "disabled"; <<
1196 <<
1197 ports { <<
1198 #address-cell <<
1199 #size-cells = <<
1200 <<
1201 port@2 { <<
1202 #addr <<
1203 #size <<
1204 <<
1205 reg = <<
1206 <<
1207 vin05 <<
1208 <<
1209 <<
1210 }; <<
1211 }; <<
1212 }; <<
1213 }; <<
1214 <<
1215 vin06: video@e6ef6000 { <<
1216 compatible = "renesas <<
1217 "renesas <<
1218 reg = <0 0xe6ef6000 0 <<
1219 interrupts = <GIC_SPI <<
1220 clocks = <&cpg CPG_MO <<
1221 power-domains = <&sys <<
1222 resets = <&cpg 804>; <<
1223 renesas,id = <6>; <<
1224 status = "disabled"; <<
1225 <<
1226 ports { <<
1227 #address-cell <<
1228 #size-cells = <<
1229 <<
1230 port@2 { <<
1231 #addr <<
1232 #size <<
1233 <<
1234 reg = <<
1235 <<
1236 vin06 <<
1237 <<
1238 <<
1239 }; <<
1240 }; <<
1241 }; <<
1242 }; <<
1243 <<
1244 vin07: video@e6ef7000 { <<
1245 compatible = "renesas <<
1246 "renesas <<
1247 reg = <0 0xe6ef7000 0 <<
1248 interrupts = <GIC_SPI <<
1249 clocks = <&cpg CPG_MO <<
1250 power-domains = <&sys <<
1251 resets = <&cpg 805>; <<
1252 renesas,id = <7>; <<
1253 status = "disabled"; <<
1254 <<
1255 ports { <<
1256 #address-cell <<
1257 #size-cells = <<
1258 <<
1259 port@2 { <<
1260 #addr <<
1261 #size <<
1262 <<
1263 reg = <<
1264 <<
1265 vin07 <<
1266 <<
1267 <<
1268 }; <<
1269 }; <<
1270 }; <<
1271 }; <<
1272 <<
1273 vin08: video@e6ef8000 { <<
1274 compatible = "renesas <<
1275 "renesas <<
1276 reg = <0 0xe6ef8000 0 <<
1277 interrupts = <GIC_SPI <<
1278 clocks = <&cpg CPG_MO <<
1279 power-domains = <&sys <<
1280 resets = <&cpg 806>; <<
1281 renesas,id = <8>; <<
1282 status = "disabled"; <<
1283 <<
1284 ports { <<
1285 #address-cell <<
1286 #size-cells = <<
1287 <<
1288 port@2 { <<
1289 #addr <<
1290 #size <<
1291 <<
1292 reg = <<
1293 <<
1294 vin08 <<
1295 <<
1296 <<
1297 }; <<
1298 }; <<
1299 }; <<
1300 }; <<
1301 <<
1302 vin09: video@e6ef9000 { <<
1303 compatible = "renesas <<
1304 "renesas <<
1305 reg = <0 0xe6ef9000 0 <<
1306 interrupts = <GIC_SPI <<
1307 clocks = <&cpg CPG_MO <<
1308 power-domains = <&sys <<
1309 resets = <&cpg 807>; <<
1310 renesas,id = <9>; <<
1311 status = "disabled"; <<
1312 <<
1313 ports { <<
1314 #address-cell <<
1315 #size-cells = <<
1316 <<
1317 port@2 { <<
1318 #addr <<
1319 #size <<
1320 <<
1321 reg = <<
1322 <<
1323 vin09 <<
1324 <<
1325 <<
1326 }; <<
1327 }; <<
1328 }; <<
1329 }; <<
1330 <<
1331 vin10: video@e6efa000 { <<
1332 compatible = "renesas <<
1333 "renesas <<
1334 reg = <0 0xe6efa000 0 <<
1335 interrupts = <GIC_SPI <<
1336 clocks = <&cpg CPG_MO <<
1337 power-domains = <&sys <<
1338 resets = <&cpg 808>; <<
1339 renesas,id = <10>; <<
1340 status = "disabled"; <<
1341 <<
1342 ports { <<
1343 #address-cell <<
1344 #size-cells = <<
1345 <<
1346 port@2 { <<
1347 #addr <<
1348 #size <<
1349 <<
1350 reg = <<
1351 <<
1352 vin10 <<
1353 <<
1354 <<
1355 }; <<
1356 }; <<
1357 }; <<
1358 }; <<
1359 <<
1360 vin11: video@e6efb000 { <<
1361 compatible = "renesas <<
1362 "renesas <<
1363 reg = <0 0xe6efb000 0 <<
1364 interrupts = <GIC_SPI <<
1365 clocks = <&cpg CPG_MO <<
1366 power-domains = <&sys <<
1367 resets = <&cpg 809>; <<
1368 renesas,id = <11>; <<
1369 status = "disabled"; <<
1370 <<
1371 ports { <<
1372 #address-cell <<
1373 #size-cells = <<
1374 <<
1375 port@2 { <<
1376 #addr <<
1377 #size <<
1378 <<
1379 reg = <<
1380 <<
1381 vin11 <<
1382 <<
1383 <<
1384 }; <<
1385 }; <<
1386 }; <<
1387 }; <<
1388 <<
1389 vin12: video@e6efc000 { <<
1390 compatible = "renesas <<
1391 "renesas <<
1392 reg = <0 0xe6efc000 0 <<
1393 interrupts = <GIC_SPI <<
1394 clocks = <&cpg CPG_MO <<
1395 power-domains = <&sys <<
1396 resets = <&cpg 810>; <<
1397 renesas,id = <12>; <<
1398 status = "disabled"; <<
1399 <<
1400 ports { <<
1401 #address-cell <<
1402 #size-cells = <<
1403 <<
1404 port@2 { <<
1405 #addr <<
1406 #size <<
1407 <<
1408 reg = <<
1409 <<
1410 vin12 <<
1411 <<
1412 <<
1413 }; <<
1414 }; <<
1415 }; <<
1416 }; <<
1417 <<
1418 vin13: video@e6efd000 { <<
1419 compatible = "renesas <<
1420 "renesas <<
1421 reg = <0 0xe6efd000 0 <<
1422 interrupts = <GIC_SPI <<
1423 clocks = <&cpg CPG_MO <<
1424 power-domains = <&sys <<
1425 resets = <&cpg 811>; <<
1426 renesas,id = <13>; <<
1427 status = "disabled"; <<
1428 <<
1429 ports { <<
1430 #address-cell <<
1431 #size-cells = <<
1432 <<
1433 port@2 { <<
1434 #addr <<
1435 #size <<
1436 <<
1437 reg = <<
1438 <<
1439 vin13 <<
1440 <<
1441 <<
1442 }; <<
1443 }; <<
1444 }; <<
1445 }; <<
1446 <<
1447 vin14: video@e6efe000 { <<
1448 compatible = "renesas <<
1449 "renesas <<
1450 reg = <0 0xe6efe000 0 <<
1451 interrupts = <GIC_SPI <<
1452 clocks = <&cpg CPG_MO <<
1453 power-domains = <&sys <<
1454 resets = <&cpg 812>; <<
1455 renesas,id = <14>; <<
1456 status = "disabled"; <<
1457 <<
1458 ports { <<
1459 #address-cell <<
1460 #size-cells = <<
1461 <<
1462 port@2 { <<
1463 #addr <<
1464 #size <<
1465 <<
1466 reg = <<
1467 <<
1468 vin14 <<
1469 <<
1470 <<
1471 }; <<
1472 }; <<
1473 }; <<
1474 }; <<
1475 <<
1476 vin15: video@e6eff000 { <<
1477 compatible = "renesas <<
1478 "renesas <<
1479 reg = <0 0xe6eff000 0 <<
1480 interrupts = <GIC_SPI <<
1481 clocks = <&cpg CPG_MO <<
1482 power-domains = <&sys <<
1483 resets = <&cpg 813>; <<
1484 renesas,id = <15>; <<
1485 status = "disabled"; <<
1486 <<
1487 ports { <<
1488 #address-cell <<
1489 #size-cells = <<
1490 <<
1491 port@2 { <<
1492 #addr <<
1493 #size <<
1494 <<
1495 reg = <<
1496 <<
1497 vin15 <<
1498 <<
1499 <<
1500 }; <<
1501 }; <<
1502 }; <<
1503 }; <<
1504 <<
1505 dmac1: dma-controller@e735000 550 dmac1: dma-controller@e7350000 {
1506 compatible = "renesas 551 compatible = "renesas,dmac-r8a779h0",
1507 "renesas 552 "renesas,rcar-gen4-dmac";
1508 reg = <0 0xe7350000 0 553 reg = <0 0xe7350000 0 0x1000>,
1509 <0 0xe7300000 0 554 <0 0xe7300000 0 0x10000>;
1510 interrupts = <GIC_SPI 555 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
1511 <GIC_SPI 556 <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
1512 <GIC_SPI 557 <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
1513 <GIC_SPI 558 <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
1514 <GIC_SPI 559 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
1515 <GIC_SPI 560 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
1516 <GIC_SPI 561 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
1517 <GIC_SPI 562 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
1518 <GIC_SPI 563 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
1519 <GIC_SPI 564 <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
1520 <GIC_SPI 565 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
1521 <GIC_SPI 566 <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
1522 <GIC_SPI 567 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
1523 <GIC_SPI 568 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
1524 <GIC_SPI 569 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
1525 <GIC_SPI 570 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
1526 <GIC_SPI 571 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
1527 interrupt-names = "er 572 interrupt-names = "error",
1528 "ch 573 "ch0", "ch1", "ch2", "ch3", "ch4",
1529 "ch 574 "ch5", "ch6", "ch7", "ch8", "ch9",
1530 "ch 575 "ch10", "ch11", "ch12", "ch13",
1531 "ch 576 "ch14", "ch15";
1532 clocks = <&cpg CPG_MO 577 clocks = <&cpg CPG_MOD 709>;
1533 clock-names = "fck"; 578 clock-names = "fck";
1534 power-domains = <&sys 579 power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
1535 resets = <&cpg 709>; 580 resets = <&cpg 709>;
1536 #dma-cells = <1>; 581 #dma-cells = <1>;
1537 dma-channels = <16>; 582 dma-channels = <16>;
1538 iommus = <&ipmmu_ds0 <<
1539 <&ipmmu_ds0 <<
1540 <&ipmmu_ds0 <<
1541 <&ipmmu_ds0 <<
1542 <&ipmmu_ds0 <<
1543 <&ipmmu_ds0 <<
1544 <&ipmmu_ds0 <<
1545 <&ipmmu_ds0 <<
1546 }; 583 };
1547 584
1548 dmac2: dma-controller@e735100 585 dmac2: dma-controller@e7351000 {
1549 compatible = "renesas 586 compatible = "renesas,dmac-r8a779h0",
1550 "renesas 587 "renesas,rcar-gen4-dmac";
1551 reg = <0 0xe7351000 0 588 reg = <0 0xe7351000 0 0x1000>,
1552 <0 0xe7310000 0 589 <0 0xe7310000 0 0x10000>;
1553 interrupts = <GIC_SPI 590 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
1554 <GIC_SPI 591 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
1555 <GIC_SPI 592 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
1556 <GIC_SPI 593 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
1557 <GIC_SPI 594 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
1558 <GIC_SPI 595 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
1559 <GIC_SPI 596 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
1560 <GIC_SPI 597 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
1561 <GIC_SPI 598 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
1562 interrupt-names = "er 599 interrupt-names = "error",
1563 "ch 600 "ch0", "ch1", "ch2", "ch3", "ch4",
1564 "ch 601 "ch5", "ch6", "ch7";
1565 clocks = <&cpg CPG_MO 602 clocks = <&cpg CPG_MOD 710>;
1566 clock-names = "fck"; 603 clock-names = "fck";
1567 power-domains = <&sys 604 power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
1568 resets = <&cpg 710>; 605 resets = <&cpg 710>;
1569 #dma-cells = <1>; 606 #dma-cells = <1>;
1570 dma-channels = <8>; 607 dma-channels = <8>;
1571 iommus = <&ipmmu_ds0 <<
1572 <&ipmmu_ds0 <<
1573 <&ipmmu_ds0 <<
1574 <&ipmmu_ds0 <<
1575 }; <<
1576 <<
1577 rcar_sound: sound@ec400000 { <<
1578 compatible = "renesas <<
1579 reg = <0 0xec400000 0 <<
1580 <0 0xec540000 0 <<
1581 <0 0xec541000 0 <<
1582 <0 0xec5a0000 0 <<
1583 reg-names = "sdmc", " <<
1584 clocks = <&cpg CPG_MO <<
1585 clock-names = "ssiu.0 <<
1586 /* #clock-cells is fi <<
1587 #clock-cells = <0>; <<
1588 /* #sound-dai-cells i <<
1589 #sound-dai-cells = <0 <<
1590 <<
1591 power-domains = <&sys <<
1592 resets = <&cpg 2926>, <<
1593 reset-names = "ssiu.0 <<
1594 status = "disabled"; <<
1595 <<
1596 rcar_sound,ssiu { <<
1597 ssiu00: ssiu- <<
1598 dmas <<
1599 dma-n <<
1600 }; <<
1601 ssiu01: ssiu- <<
1602 dmas <<
1603 dma-n <<
1604 }; <<
1605 ssiu02: ssiu- <<
1606 dmas <<
1607 dma-n <<
1608 }; <<
1609 ssiu03: ssiu- <<
1610 dmas <<
1611 dma-n <<
1612 }; <<
1613 ssiu04: ssiu- <<
1614 dmas <<
1615 dma-n <<
1616 }; <<
1617 ssiu05: ssiu- <<
1618 dmas <<
1619 dma-n <<
1620 }; <<
1621 ssiu06: ssiu- <<
1622 dmas <<
1623 dma-n <<
1624 }; <<
1625 ssiu07: ssiu- <<
1626 dmas <<
1627 dma-n <<
1628 }; <<
1629 }; <<
1630 <<
1631 rcar_sound,ssi { <<
1632 ssi0: ssi-0 { <<
1633 inter <<
1634 }; <<
1635 }; <<
1636 }; 608 };
1637 609
1638 mmc0: mmc@ee140000 { 610 mmc0: mmc@ee140000 {
1639 compatible = "renesas 611 compatible = "renesas,sdhi-r8a779h0",
1640 "renesas 612 "renesas,rcar-gen4-sdhi";
1641 reg = <0 0xee140000 0 613 reg = <0 0xee140000 0 0x2000>;
1642 interrupts = <GIC_SPI 614 interrupts = <GIC_SPI 440 IRQ_TYPE_LEVEL_HIGH>;
1643 clocks = <&cpg CPG_MO 615 clocks = <&cpg CPG_MOD 706>,
1644 <&cpg CPG_CO 616 <&cpg CPG_CORE R8A779H0_CLK_SD0H>;
1645 clock-names = "core", 617 clock-names = "core", "clkh";
1646 power-domains = <&sys 618 power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
1647 resets = <&cpg 706>; 619 resets = <&cpg 706>;
1648 max-frequency = <2000 620 max-frequency = <200000000>;
1649 iommus = <&ipmmu_ds0 <<
1650 status = "disabled"; 621 status = "disabled";
1651 }; 622 };
1652 623
1653 rpc: spi@ee200000 { 624 rpc: spi@ee200000 {
1654 compatible = "renesas 625 compatible = "renesas,r8a779h0-rpc-if",
1655 "renesas 626 "renesas,rcar-gen4-rpc-if";
1656 reg = <0 0xee200000 0 627 reg = <0 0xee200000 0 0x200>,
1657 <0 0x08000000 0 628 <0 0x08000000 0 0x04000000>,
1658 <0 0xee208000 0 629 <0 0xee208000 0 0x100>;
1659 reg-names = "regs", " 630 reg-names = "regs", "dirmap", "wbuf";
1660 interrupts = <GIC_SPI 631 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
1661 clocks = <&cpg CPG_MO 632 clocks = <&cpg CPG_MOD 629>;
1662 power-domains = <&sys 633 power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
1663 resets = <&cpg 629>; 634 resets = <&cpg 629>;
1664 #address-cells = <1>; 635 #address-cells = <1>;
1665 #size-cells = <0>; 636 #size-cells = <0>;
1666 status = "disabled"; 637 status = "disabled";
1667 }; 638 };
1668 639
1669 ipmmu_rt0: iommu@ee480000 { <<
1670 compatible = "renesas <<
1671 "renesas <<
1672 reg = <0 0xee480000 0 <<
1673 renesas,ipmmu-main = <<
1674 power-domains = <&sys <<
1675 #iommu-cells = <1>; <<
1676 }; <<
1677 <<
1678 ipmmu_rt1: iommu@ee4c0000 { <<
1679 compatible = "renesas <<
1680 "renesas <<
1681 reg = <0 0xee4c0000 0 <<
1682 renesas,ipmmu-main = <<
1683 power-domains = <&sys <<
1684 #iommu-cells = <1>; <<
1685 }; <<
1686 <<
1687 ipmmu_ds0: iommu@eed00000 { <<
1688 compatible = "renesas <<
1689 "renesas <<
1690 reg = <0 0xeed00000 0 <<
1691 renesas,ipmmu-main = <<
1692 power-domains = <&sys <<
1693 #iommu-cells = <1>; <<
1694 }; <<
1695 <<
1696 ipmmu_hc: iommu@eed40000 { <<
1697 compatible = "renesas <<
1698 "renesas <<
1699 reg = <0 0xeed40000 0 <<
1700 renesas,ipmmu-main = <<
1701 power-domains = <&sys <<
1702 #iommu-cells = <1>; <<
1703 }; <<
1704 <<
1705 ipmmu_ir: iommu@eed80000 { <<
1706 compatible = "renesas <<
1707 "renesas <<
1708 reg = <0 0xeed80000 0 <<
1709 renesas,ipmmu-main = <<
1710 power-domains = <&sys <<
1711 #iommu-cells = <1>; <<
1712 }; <<
1713 <<
1714 ipmmu_vc: iommu@eedc0000 { <<
1715 compatible = "renesas <<
1716 "renesas <<
1717 reg = <0 0xeedc0000 0 <<
1718 renesas,ipmmu-main = <<
1719 power-domains = <&sys <<
1720 #iommu-cells = <1>; <<
1721 }; <<
1722 <<
1723 ipmmu_3dg: iommu@eee00000 { <<
1724 compatible = "renesas <<
1725 "renesas <<
1726 reg = <0 0xeee00000 0 <<
1727 renesas,ipmmu-main = <<
1728 power-domains = <&sys <<
1729 #iommu-cells = <1>; <<
1730 }; <<
1731 <<
1732 ipmmu_vi0: iommu@eee80000 { <<
1733 compatible = "renesas <<
1734 "renesas <<
1735 reg = <0 0xeee80000 0 <<
1736 renesas,ipmmu-main = <<
1737 power-domains = <&sys <<
1738 #iommu-cells = <1>; <<
1739 }; <<
1740 <<
1741 ipmmu_vi1: iommu@eeec0000 { <<
1742 compatible = "renesas <<
1743 "renesas <<
1744 reg = <0 0xeeec0000 0 <<
1745 renesas,ipmmu-main = <<
1746 power-domains = <&sys <<
1747 #iommu-cells = <1>; <<
1748 }; <<
1749 <<
1750 ipmmu_vip0: iommu@eef00000 { <<
1751 compatible = "renesas <<
1752 "renesas <<
1753 reg = <0 0xeef00000 0 <<
1754 renesas,ipmmu-main = <<
1755 power-domains = <&sys <<
1756 #iommu-cells = <1>; <<
1757 }; <<
1758 <<
1759 ipmmu_mm: iommu@eefc0000 { <<
1760 compatible = "renesas <<
1761 "renesas <<
1762 reg = <0 0xeefc0000 0 <<
1763 interrupts = <GIC_SPI <<
1764 <GIC_SPI <<
1765 power-domains = <&sys <<
1766 #iommu-cells = <1>; <<
1767 }; <<
1768 <<
1769 gic: interrupt-controller@f10 640 gic: interrupt-controller@f1000000 {
1770 compatible = "arm,gic 641 compatible = "arm,gic-v3";
1771 #interrupt-cells = <3 642 #interrupt-cells = <3>;
1772 #address-cells = <0>; 643 #address-cells = <0>;
1773 interrupt-controller; 644 interrupt-controller;
1774 reg = <0x0 0xf1000000 645 reg = <0x0 0xf1000000 0 0x20000>,
1775 <0x0 0xf1060000 646 <0x0 0xf1060000 0 0x110000>;
1776 interrupts = <GIC_PPI 647 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
1777 }; 648 };
1778 649
1779 csi40: csi2@fe500000 { <<
1780 compatible = "renesas <<
1781 reg = <0 0xfe500000 0 <<
1782 interrupts = <GIC_SPI <<
1783 clocks = <&cpg CPG_MO <<
1784 power-domains = <&sys <<
1785 resets = <&cpg 331>; <<
1786 status = "disabled"; <<
1787 <<
1788 ports { <<
1789 #address-cell <<
1790 #size-cells = <<
1791 <<
1792 port@0 { <<
1793 reg = <<
1794 }; <<
1795 <<
1796 port@1 { <<
1797 reg = <<
1798 csi40 <<
1799 <<
1800 }; <<
1801 }; <<
1802 }; <<
1803 }; <<
1804 <<
1805 csi41: csi2@fe540000 { <<
1806 compatible = "renesas <<
1807 reg = <0 0xfe540000 0 <<
1808 interrupts = <GIC_SPI <<
1809 clocks = <&cpg CPG_MO <<
1810 power-domains = <&sys <<
1811 resets = <&cpg 400>; <<
1812 status = "disabled"; <<
1813 <<
1814 ports { <<
1815 #address-cell <<
1816 #size-cells = <<
1817 <<
1818 port@0 { <<
1819 reg = <<
1820 }; <<
1821 <<
1822 port@1 { <<
1823 reg = <<
1824 csi41 <<
1825 <<
1826 }; <<
1827 }; <<
1828 }; <<
1829 }; <<
1830 <<
1831 isp0: isp@fed00000 { <<
1832 compatible = "renesas <<
1833 "renesas <<
1834 reg = <0 0xfed00000 0 <<
1835 interrupts = <GIC_SPI <<
1836 clocks = <&cpg CPG_MO <<
1837 power-domains = <&sys <<
1838 resets = <&cpg 612>; <<
1839 status = "disabled"; <<
1840 <<
1841 ports { <<
1842 #address-cell <<
1843 #size-cells = <<
1844 <<
1845 port@0 { <<
1846 #addr <<
1847 #size <<
1848 <<
1849 reg = <<
1850 <<
1851 isp0c <<
1852 <<
1853 <<
1854 }; <<
1855 }; <<
1856 <<
1857 port@1 { <<
1858 reg = <<
1859 isp0v <<
1860 <<
1861 }; <<
1862 }; <<
1863 <<
1864 port@2 { <<
1865 reg = <<
1866 isp0v <<
1867 <<
1868 }; <<
1869 }; <<
1870 <<
1871 port@3 { <<
1872 reg = <<
1873 isp0v <<
1874 <<
1875 }; <<
1876 }; <<
1877 <<
1878 port@4 { <<
1879 reg = <<
1880 isp0v <<
1881 <<
1882 }; <<
1883 }; <<
1884 <<
1885 port@5 { <<
1886 reg = <<
1887 isp0v <<
1888 <<
1889 }; <<
1890 }; <<
1891 <<
1892 port@6 { <<
1893 reg = <<
1894 isp0v <<
1895 <<
1896 }; <<
1897 }; <<
1898 <<
1899 port@7 { <<
1900 reg = <<
1901 isp0v <<
1902 <<
1903 }; <<
1904 }; <<
1905 <<
1906 port@8 { <<
1907 reg = <<
1908 isp0v <<
1909 <<
1910 }; <<
1911 }; <<
1912 }; <<
1913 }; <<
1914 <<
1915 isp1: isp@fed20000 { <<
1916 compatible = "renesas <<
1917 "renesas <<
1918 reg = <0 0xfed20000 0 <<
1919 interrupts = <GIC_SPI <<
1920 clocks = <&cpg CPG_MO <<
1921 power-domains = <&sys <<
1922 resets = <&cpg 613>; <<
1923 status = "disabled"; <<
1924 <<
1925 ports { <<
1926 #address-cell <<
1927 #size-cells = <<
1928 <<
1929 port@0 { <<
1930 #addr <<
1931 #size <<
1932 <<
1933 reg = <<
1934 <<
1935 isp1c <<
1936 <<
1937 <<
1938 }; <<
1939 }; <<
1940 <<
1941 port@1 { <<
1942 reg = <<
1943 isp1v <<
1944 <<
1945 }; <<
1946 }; <<
1947 <<
1948 port@2 { <<
1949 reg = <<
1950 isp1v <<
1951 <<
1952 }; <<
1953 }; <<
1954 <<
1955 port@3 { <<
1956 reg = <<
1957 isp1v <<
1958 <<
1959 }; <<
1960 }; <<
1961 <<
1962 port@4 { <<
1963 reg = <<
1964 isp1v <<
1965 <<
1966 }; <<
1967 }; <<
1968 <<
1969 port@5 { <<
1970 reg = <<
1971 isp1v <<
1972 <<
1973 }; <<
1974 }; <<
1975 <<
1976 port@6 { <<
1977 reg = <<
1978 isp1v <<
1979 <<
1980 }; <<
1981 }; <<
1982 <<
1983 port@7 { <<
1984 reg = <<
1985 isp1v <<
1986 <<
1987 }; <<
1988 }; <<
1989 <<
1990 port@8 { <<
1991 reg = <<
1992 isp1v <<
1993 <<
1994 }; <<
1995 }; <<
1996 }; <<
1997 }; <<
1998 <<
1999 prr: chipid@fff00044 { 650 prr: chipid@fff00044 {
2000 compatible = "renesas 651 compatible = "renesas,prr";
2001 reg = <0 0xfff00044 0 652 reg = <0 0xfff00044 0 4>;
2002 }; 653 };
2003 }; 654 };
2004 655
2005 thermal-zones { <<
2006 sensor_thermal_cr52: sensor1- <<
2007 polling-delay-passive <<
2008 polling-delay = <1000 <<
2009 thermal-sensors = <&t <<
2010 <<
2011 trips { <<
2012 sensor1_crit: <<
2013 tempe <<
2014 hyste <<
2015 type <<
2016 }; <<
2017 }; <<
2018 }; <<
2019 <<
2020 sensor_thermal_ca76: sensor2- <<
2021 polling-delay-passive <<
2022 polling-delay = <1000 <<
2023 thermal-sensors = <&t <<
2024 <<
2025 trips { <<
2026 sensor2_crit: <<
2027 tempe <<
2028 hyste <<
2029 type <<
2030 }; <<
2031 }; <<
2032 }; <<
2033 }; <<
2034 <<
2035 timer { 656 timer {
2036 compatible = "arm,armv8-timer 657 compatible = "arm,armv8-timer";
2037 interrupts-extended = <&gic G 658 interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
2038 <&gic G 659 <&gic GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
2039 <&gic G 660 <&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
2040 <&gic G 661 <&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>,
2041 <&gic G 662 <&gic GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>;
2042 interrupt-names = "sec-phys", <<
2043 "hyp-virt"; <<
2044 }; 663 };
2045 }; 664 };
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