1 // SPDX-License-Identifier: (GPL-2.0-only OR B
2 /*
3 * Device Tree Source for the RZ/G2L and RZ/G2
4 *
5 * Copyright (C) 2021 Renesas Electronics Corp
6 */
7
8 #include <dt-bindings/interrupt-controller/arm
9 #include <dt-bindings/clock/r9a07g044-cpg.h>
10
11 / {
12 compatible = "renesas,r9a07g044";
13 #address-cells = <2>;
14 #size-cells = <2>;
15
16 audio_clk1: audio1-clk {
17 compatible = "fixed-clock";
18 #clock-cells = <0>;
19 /* This value must be overridd
20 clock-frequency = <0>;
21 };
22
23 audio_clk2: audio2-clk {
24 compatible = "fixed-clock";
25 #clock-cells = <0>;
26 /* This value must be overridd
27 clock-frequency = <0>;
28 };
29
30 /* External CAN clock - to be overridd
31 can_clk: can-clk {
32 compatible = "fixed-clock";
33 #clock-cells = <0>;
34 clock-frequency = <0>;
35 };
36
37 /* clock can be either from exclk or c
38 extal_clk: extal-clk {
39 compatible = "fixed-clock";
40 #clock-cells = <0>;
41 /* This value must be overridd
42 clock-frequency = <0>;
43 };
44
45 cluster0_opp: opp-table-0 {
46 compatible = "operating-points
47 opp-shared;
48
49 opp-150000000 {
50 opp-hz = /bits/ 64 <15
51 opp-microvolt = <11000
52 clock-latency-ns = <30
53 };
54 opp-300000000 {
55 opp-hz = /bits/ 64 <30
56 opp-microvolt = <11000
57 clock-latency-ns = <30
58 };
59 opp-600000000 {
60 opp-hz = /bits/ 64 <60
61 opp-microvolt = <11000
62 clock-latency-ns = <30
63 };
64 opp-1200000000 {
65 opp-hz = /bits/ 64 <12
66 opp-microvolt = <11000
67 clock-latency-ns = <30
68 opp-suspend;
69 };
70 };
71
72 cpus {
73 #address-cells = <1>;
74 #size-cells = <0>;
75
76 cpu-map {
77 cluster0 {
78 core0 {
79 cpu =
80 };
81 core1 {
82 cpu =
83 };
84 };
85 };
86
87 cpu0: cpu@0 {
88 compatible = "arm,cort
89 reg = <0>;
90 device_type = "cpu";
91 #cooling-cells = <2>;
92 next-level-cache = <&L
93 enable-method = "psci"
94 clocks = <&cpg CPG_COR
95 operating-points-v2 =
96 };
97
98 cpu1: cpu@100 {
99 compatible = "arm,cort
100 reg = <0x100>;
101 device_type = "cpu";
102 next-level-cache = <&L
103 enable-method = "psci"
104 clocks = <&cpg CPG_COR
105 operating-points-v2 =
106 };
107
108 L3_CA55: cache-controller-0 {
109 compatible = "cache";
110 cache-unified;
111 cache-size = <0x40000>
112 cache-level = <3>;
113 };
114 };
115
116 gpu_opp_table: opp-table-1 {
117 compatible = "operating-points
118
119 opp-500000000 {
120 opp-hz = /bits/ 64 <50
121 opp-microvolt = <11000
122 };
123
124 opp-400000000 {
125 opp-hz = /bits/ 64 <40
126 opp-microvolt = <11000
127 };
128
129 opp-250000000 {
130 opp-hz = /bits/ 64 <25
131 opp-microvolt = <11000
132 };
133
134 opp-200000000 {
135 opp-hz = /bits/ 64 <20
136 opp-microvolt = <11000
137 };
138
139 opp-125000000 {
140 opp-hz = /bits/ 64 <12
141 opp-microvolt = <11000
142 };
143
144 opp-100000000 {
145 opp-hz = /bits/ 64 <10
146 opp-microvolt = <11000
147 };
148
149 opp-62500000 {
150 opp-hz = /bits/ 64 <62
151 opp-microvolt = <11000
152 };
153
154 opp-50000000 {
155 opp-hz = /bits/ 64 <50
156 opp-microvolt = <11000
157 };
158 };
159
160 pmu {
161 compatible = "arm,cortex-a55-p
162 interrupts-extended = <&gic GI
163 };
164
165 psci {
166 compatible = "arm,psci-1.0", "
167 method = "smc";
168 };
169
170 soc: soc {
171 compatible = "simple-bus";
172 interrupt-parent = <&gic>;
173 #address-cells = <2>;
174 #size-cells = <2>;
175 ranges;
176
177 mtu3: timer@10001200 {
178 compatible = "renesas,
179 "renesas,
180 reg = <0 0x10001200 0
181 interrupts = <GIC_SPI
182 <GIC_SPI
183 <GIC_SPI
184 <GIC_SPI
185 <GIC_SPI
186 <GIC_SPI
187 <GIC_SPI
188 <GIC_SPI
189 <GIC_SPI
190 <GIC_SPI
191 <GIC_SPI
192 <GIC_SPI
193 <GIC_SPI
194 <GIC_SPI
195 <GIC_SPI
196 <GIC_SPI
197 <GIC_SPI
198 <GIC_SPI
199 <GIC_SPI
200 <GIC_SPI
201 <GIC_SPI
202 <GIC_SPI
203 <GIC_SPI
204 <GIC_SPI
205 <GIC_SPI
206 <GIC_SPI
207 <GIC_SPI
208 <GIC_SPI
209 <GIC_SPI
210 <GIC_SPI
211 <GIC_SPI
212 <GIC_SPI
213 <GIC_SPI
214 <GIC_SPI
215 <GIC_SPI
216 <GIC_SPI
217 <GIC_SPI
218 <GIC_SPI
219 <GIC_SPI
220 <GIC_SPI
221 <GIC_SPI
222 <GIC_SPI
223 <GIC_SPI
224 <GIC_SPI
225 interrupt-names = "tgi
226 "tci
227 "tgi
228 "tgi
229 "tgi
230 "tci
231 "tgi
232 "tci
233 "tgi
234 "tgi
235 "tci
236 "tgi
237 "tci
238 "tgi
239 "tci
240 clocks = <&cpg CPG_MOD
241 power-domains = <&cpg>
242 resets = <&cpg R9A07G0
243 #pwm-cells = <2>;
244 status = "disabled";
245 };
246
247 ssi0: ssi@10049c00 {
248 compatible = "renesas,
249 "renesas,
250 reg = <0 0x10049c00 0
251 interrupts = <GIC_SPI
252 <GIC_SPI
253 <GIC_SPI
254 interrupt-names = "int
255 clocks = <&cpg CPG_MOD
256 <&cpg CPG_MOD
257 <&audio_clk1>
258 clock-names = "ssi", "
259 resets = <&cpg R9A07G0
260 dmas = <&dmac 0x2655>,
261 dma-names = "tx", "rx"
262 power-domains = <&cpg>
263 #sound-dai-cells = <0>
264 status = "disabled";
265 };
266
267 ssi1: ssi@1004a000 {
268 compatible = "renesas,
269 "renesas,
270 reg = <0 0x1004a000 0
271 interrupts = <GIC_SPI
272 <GIC_SPI
273 <GIC_SPI
274 interrupt-names = "int
275 clocks = <&cpg CPG_MOD
276 <&cpg CPG_MOD
277 <&audio_clk1>
278 clock-names = "ssi", "
279 resets = <&cpg R9A07G0
280 dmas = <&dmac 0x2659>,
281 dma-names = "tx", "rx"
282 power-domains = <&cpg>
283 #sound-dai-cells = <0>
284 status = "disabled";
285 };
286
287 ssi2: ssi@1004a400 {
288 compatible = "renesas,
289 "renesas,
290 reg = <0 0x1004a400 0
291 interrupts = <GIC_SPI
292 <GIC_SPI
293 interrupt-names = "int
294 clocks = <&cpg CPG_MOD
295 <&cpg CPG_MOD
296 <&audio_clk1>
297 clock-names = "ssi", "
298 resets = <&cpg R9A07G0
299 dmas = <&dmac 0x265f>;
300 dma-names = "rt";
301 power-domains = <&cpg>
302 #sound-dai-cells = <0>
303 status = "disabled";
304 };
305
306 ssi3: ssi@1004a800 {
307 compatible = "renesas,
308 "renesas,
309 reg = <0 0x1004a800 0
310 interrupts = <GIC_SPI
311 <GIC_SPI
312 <GIC_SPI
313 interrupt-names = "int
314 clocks = <&cpg CPG_MOD
315 <&cpg CPG_MOD
316 <&audio_clk1>
317 clock-names = "ssi", "
318 resets = <&cpg R9A07G0
319 dmas = <&dmac 0x2661>,
320 dma-names = "tx", "rx"
321 power-domains = <&cpg>
322 #sound-dai-cells = <0>
323 status = "disabled";
324 };
325
326 spi0: spi@1004ac00 {
327 compatible = "renesas,
328 reg = <0 0x1004ac00 0
329 interrupts = <GIC_SPI
330 <GIC_SPI
331 <GIC_SPI
332 interrupt-names = "err
333 clocks = <&cpg CPG_MOD
334 resets = <&cpg R9A07G0
335 dmas = <&dmac 0x2e95>,
336 dma-names = "tx", "rx"
337 power-domains = <&cpg>
338 num-cs = <1>;
339 #address-cells = <1>;
340 #size-cells = <0>;
341 status = "disabled";
342 };
343
344 spi1: spi@1004b000 {
345 compatible = "renesas,
346 reg = <0 0x1004b000 0
347 interrupts = <GIC_SPI
348 <GIC_SPI
349 <GIC_SPI
350 interrupt-names = "err
351 clocks = <&cpg CPG_MOD
352 resets = <&cpg R9A07G0
353 dmas = <&dmac 0x2e99>,
354 dma-names = "tx", "rx"
355 power-domains = <&cpg>
356 num-cs = <1>;
357 #address-cells = <1>;
358 #size-cells = <0>;
359 status = "disabled";
360 };
361
362 spi2: spi@1004b400 {
363 compatible = "renesas,
364 reg = <0 0x1004b400 0
365 interrupts = <GIC_SPI
366 <GIC_SPI
367 <GIC_SPI
368 interrupt-names = "err
369 clocks = <&cpg CPG_MOD
370 resets = <&cpg R9A07G0
371 dmas = <&dmac 0x2e9d>,
372 dma-names = "tx", "rx"
373 power-domains = <&cpg>
374 num-cs = <1>;
375 #address-cells = <1>;
376 #size-cells = <0>;
377 status = "disabled";
378 };
379
380 scif0: serial@1004b800 {
381 compatible = "renesas,
382 reg = <0 0x1004b800 0
383 interrupts = <GIC_SPI
384 <GIC_SPI
385 <GIC_SPI
386 <GIC_SPI
387 <GIC_SPI
388 <GIC_SPI
389 interrupt-names = "eri
390 "bri
391 clocks = <&cpg CPG_MOD
392 clock-names = "fck";
393 power-domains = <&cpg>
394 resets = <&cpg R9A07G0
395 status = "disabled";
396 };
397
398 scif1: serial@1004bc00 {
399 compatible = "renesas,
400 reg = <0 0x1004bc00 0
401 interrupts = <GIC_SPI
402 <GIC_SPI
403 <GIC_SPI
404 <GIC_SPI
405 <GIC_SPI
406 <GIC_SPI
407 interrupt-names = "eri
408 "bri
409 clocks = <&cpg CPG_MOD
410 clock-names = "fck";
411 power-domains = <&cpg>
412 resets = <&cpg R9A07G0
413 status = "disabled";
414 };
415
416 scif2: serial@1004c000 {
417 compatible = "renesas,
418 reg = <0 0x1004c000 0
419 interrupts = <GIC_SPI
420 <GIC_SPI
421 <GIC_SPI
422 <GIC_SPI
423 <GIC_SPI
424 <GIC_SPI
425 interrupt-names = "eri
426 "bri
427 clocks = <&cpg CPG_MOD
428 clock-names = "fck";
429 power-domains = <&cpg>
430 resets = <&cpg R9A07G0
431 status = "disabled";
432 };
433
434 scif3: serial@1004c400 {
435 compatible = "renesas,
436 reg = <0 0x1004c400 0
437 interrupts = <GIC_SPI
438 <GIC_SPI
439 <GIC_SPI
440 <GIC_SPI
441 <GIC_SPI
442 <GIC_SPI
443 interrupt-names = "eri
444 "bri
445 clocks = <&cpg CPG_MOD
446 clock-names = "fck";
447 power-domains = <&cpg>
448 resets = <&cpg R9A07G0
449 status = "disabled";
450 };
451
452 scif4: serial@1004c800 {
453 compatible = "renesas,
454 reg = <0 0x1004c800 0
455 interrupts = <GIC_SPI
456 <GIC_SPI
457 <GIC_SPI
458 <GIC_SPI
459 <GIC_SPI
460 <GIC_SPI
461 interrupt-names = "eri
462 "bri
463 clocks = <&cpg CPG_MOD
464 clock-names = "fck";
465 power-domains = <&cpg>
466 resets = <&cpg R9A07G0
467 status = "disabled";
468 };
469
470 sci0: serial@1004d000 {
471 compatible = "renesas,
472 reg = <0 0x1004d000 0
473 interrupts = <GIC_SPI
474 <GIC_SPI
475 <GIC_SPI
476 <GIC_SPI
477 interrupt-names = "eri
478 clocks = <&cpg CPG_MOD
479 clock-names = "fck";
480 power-domains = <&cpg>
481 resets = <&cpg R9A07G0
482 status = "disabled";
483 };
484
485 sci1: serial@1004d400 {
486 compatible = "renesas,
487 reg = <0 0x1004d400 0
488 interrupts = <GIC_SPI
489 <GIC_SPI
490 <GIC_SPI
491 <GIC_SPI
492 interrupt-names = "eri
493 clocks = <&cpg CPG_MOD
494 clock-names = "fck";
495 power-domains = <&cpg>
496 resets = <&cpg R9A07G0
497 status = "disabled";
498 };
499
500 canfd: can@10050000 {
501 compatible = "renesas,
502 reg = <0 0x10050000 0
503 interrupts = <GIC_SPI
504 <GIC_SPI
505 <GIC_SPI
506 <GIC_SPI
507 <GIC_SPI
508 <GIC_SPI
509 <GIC_SPI
510 <GIC_SPI
511 interrupt-names = "g_e
512 "ch0
513 "ch1
514 clocks = <&cpg CPG_MOD
515 <&cpg CPG_COR
516 <&can_clk>;
517 clock-names = "fck", "
518 assigned-clocks = <&cp
519 assigned-clock-rates =
520 resets = <&cpg R9A07G0
521 <&cpg R9A07G0
522 reset-names = "rstp_n"
523 power-domains = <&cpg>
524 status = "disabled";
525
526 channel0 {
527 status = "disa
528 };
529 channel1 {
530 status = "disa
531 };
532 };
533
534 i2c0: i2c@10058000 {
535 #address-cells = <1>;
536 #size-cells = <0>;
537 compatible = "renesas,
538 reg = <0 0x10058000 0
539 interrupts = <GIC_SPI
540 <GIC_SPI
541 <GIC_SPI
542 <GIC_SPI
543 <GIC_SPI
544 <GIC_SPI
545 <GIC_SPI
546 <GIC_SPI
547 interrupt-names = "tei
548 "nak
549 clocks = <&cpg CPG_MOD
550 clock-frequency = <100
551 resets = <&cpg R9A07G0
552 power-domains = <&cpg>
553 status = "disabled";
554 };
555
556 i2c1: i2c@10058400 {
557 #address-cells = <1>;
558 #size-cells = <0>;
559 compatible = "renesas,
560 reg = <0 0x10058400 0
561 interrupts = <GIC_SPI
562 <GIC_SPI
563 <GIC_SPI
564 <GIC_SPI
565 <GIC_SPI
566 <GIC_SPI
567 <GIC_SPI
568 <GIC_SPI
569 interrupt-names = "tei
570 "nak
571 clocks = <&cpg CPG_MOD
572 clock-frequency = <100
573 resets = <&cpg R9A07G0
574 power-domains = <&cpg>
575 status = "disabled";
576 };
577
578 i2c2: i2c@10058800 {
579 #address-cells = <1>;
580 #size-cells = <0>;
581 compatible = "renesas,
582 reg = <0 0x10058800 0
583 interrupts = <GIC_SPI
584 <GIC_SPI
585 <GIC_SPI
586 <GIC_SPI
587 <GIC_SPI
588 <GIC_SPI
589 <GIC_SPI
590 <GIC_SPI
591 interrupt-names = "tei
592 "nak
593 clocks = <&cpg CPG_MOD
594 clock-frequency = <100
595 resets = <&cpg R9A07G0
596 power-domains = <&cpg>
597 status = "disabled";
598 };
599
600 i2c3: i2c@10058c00 {
601 #address-cells = <1>;
602 #size-cells = <0>;
603 compatible = "renesas,
604 reg = <0 0x10058c00 0
605 interrupts = <GIC_SPI
606 <GIC_SPI
607 <GIC_SPI
608 <GIC_SPI
609 <GIC_SPI
610 <GIC_SPI
611 <GIC_SPI
612 <GIC_SPI
613 interrupt-names = "tei
614 "nak
615 clocks = <&cpg CPG_MOD
616 clock-frequency = <100
617 resets = <&cpg R9A07G0
618 power-domains = <&cpg>
619 status = "disabled";
620 };
621
622 adc: adc@10059000 {
623 compatible = "renesas,
624 reg = <0 0x10059000 0
625 interrupts = <GIC_SPI
626 clocks = <&cpg CPG_MOD
627 <&cpg CPG_MOD
628 clock-names = "adclk",
629 resets = <&cpg R9A07G0
630 <&cpg R9A07G0
631 reset-names = "presetn
632 power-domains = <&cpg>
633 status = "disabled";
634
635 #address-cells = <1>;
636 #size-cells = <0>;
637
638 channel@0 {
639 reg = <0>;
640 };
641 channel@1 {
642 reg = <1>;
643 };
644 channel@2 {
645 reg = <2>;
646 };
647 channel@3 {
648 reg = <3>;
649 };
650 channel@4 {
651 reg = <4>;
652 };
653 channel@5 {
654 reg = <5>;
655 };
656 channel@6 {
657 reg = <6>;
658 };
659 channel@7 {
660 reg = <7>;
661 };
662 };
663
664 tsu: thermal@10059400 {
665 compatible = "renesas,
666 "renesas,
667 reg = <0 0x10059400 0
668 clocks = <&cpg CPG_MOD
669 resets = <&cpg R9A07G0
670 power-domains = <&cpg>
671 #thermal-sensor-cells
672 };
673
674 sbc: spi@10060000 {
675 compatible = "renesas,
676 "renesas,
677 reg = <0 0x10060000 0
678 <0 0x20000000 0
679 <0 0x10070000 0
680 reg-names = "regs", "d
681 interrupts = <GIC_SPI
682 clocks = <&cpg CPG_MOD
683 <&cpg CPG_MOD
684 resets = <&cpg R9A07G0
685 power-domains = <&cpg>
686 #address-cells = <1>;
687 #size-cells = <0>;
688 status = "disabled";
689 };
690
691 cru: video@10830000 {
692 compatible = "renesas,
693 reg = <0 0x10830000 0
694 clocks = <&cpg CPG_MOD
695 <&cpg CPG_MOD
696 <&cpg CPG_MOD
697 clock-names = "video",
698 interrupts = <GIC_SPI
699 <GIC_SPI
700 <GIC_SPI
701 interrupt-names = "ima
702 resets = <&cpg R9A07G0
703 <&cpg R9A07G0
704 reset-names = "presetn
705 power-domains = <&cpg>
706 status = "disabled";
707
708 ports {
709 #address-cells
710 #size-cells =
711
712 port@0 {
713 #addre
714 #size-
715
716 reg =
717 crupar
718
719 };
720 };
721
722 port@1 {
723 #addre
724 #size-
725
726 reg =
727 crucsi
728
729
730 };
731 };
732 };
733 };
734
735 csi2: csi2@10830400 {
736 compatible = "renesas,
737 reg = <0 0x10830400 0
738 interrupts = <GIC_SPI
739 clocks = <&cpg CPG_MOD
740 <&cpg CPG_MOD
741 <&cpg CPG_MOD
742 clock-names = "system"
743 resets = <&cpg R9A07G0
744 <&cpg R9A07G0
745 reset-names = "presetn
746 power-domains = <&cpg>
747 status = "disabled";
748
749 ports {
750 #address-cells
751 #size-cells =
752
753 port@0 {
754 reg =
755 };
756
757 port@1 {
758 #addre
759 #size-
760 reg =
761
762 csi2cr
763
764
765 };
766 };
767 };
768 };
769
770 dsi: dsi@10850000 {
771 compatible = "renesas,
772 "renesas,
773 reg = <0 0x10850000 0
774 interrupts = <GIC_SPI
775 <GIC_SPI
776 <GIC_SPI
777 <GIC_SPI
778 <GIC_SPI
779 <GIC_SPI
780 <GIC_SPI
781 interrupt-names = "seq
782 "fer
783 clocks = <&cpg CPG_MOD
784 <&cpg CPG_MOD
785 <&cpg CPG_MOD
786 <&cpg CPG_MOD
787 <&cpg CPG_MOD
788 <&cpg CPG_MOD
789 clock-names = "pllclk"
790 resets = <&cpg R9A07G0
791 <&cpg R9A07G0
792 <&cpg R9A07G0
793 reset-names = "rst", "
794 power-domains = <&cpg>
795 status = "disabled";
796
797 ports {
798 #address-cells
799 #size-cells =
800
801 port@0 {
802 reg =
803 dsi0_i
804
805 };
806 };
807
808 port@1 {
809 reg =
810 };
811 };
812 };
813
814 vspd: vsp@10870000 {
815 compatible = "renesas,
816 reg = <0 0x10870000 0
817 interrupts = <GIC_SPI
818 clocks = <&cpg CPG_MOD
819 <&cpg CPG_MOD
820 <&cpg CPG_MOD
821 clock-names = "aclk",
822 power-domains = <&cpg>
823 resets = <&cpg R9A07G0
824 renesas,fcp = <&fcpvd>
825 };
826
827 fcpvd: fcp@10880000 {
828 compatible = "renesas,
829 "renesas,
830 reg = <0 0x10880000 0
831 clocks = <&cpg CPG_MOD
832 <&cpg CPG_MOD
833 <&cpg CPG_MOD
834 clock-names = "aclk",
835 power-domains = <&cpg>
836 resets = <&cpg R9A07G0
837 };
838
839 du: display@10890000 {
840 compatible = "renesas,
841 reg = <0 0x10890000 0
842 interrupts = <GIC_SPI
843 clocks = <&cpg CPG_MOD
844 <&cpg CPG_MOD
845 <&cpg CPG_MOD
846 clock-names = "aclk",
847 power-domains = <&cpg>
848 resets = <&cpg R9A07G0
849 renesas,vsps = <&vspd
850 status = "disabled";
851
852 ports {
853 #address-cells
854 #size-cells =
855
856 port@0 {
857 reg =
858 du_out
859
860 };
861 };
862
863 port@1 {
864 reg =
865 };
866 };
867 };
868
869 cpg: clock-controller@11010000
870 compatible = "renesas,
871 reg = <0 0x11010000 0
872 clocks = <&extal_clk>;
873 clock-names = "extal";
874 #clock-cells = <2>;
875 #reset-cells = <1>;
876 #power-domain-cells =
877 };
878
879 sysc: system-controller@110200
880 compatible = "renesas,
881 reg = <0 0x11020000 0
882 interrupts = <GIC_SPI
883 <GIC_SPI
884 <GIC_SPI
885 <GIC_SPI
886 interrupt-names = "lpm
887 "cm3
888 status = "disabled";
889 };
890
891 pinctrl: pinctrl@11030000 {
892 compatible = "renesas,
893 reg = <0 0x11030000 0
894 gpio-controller;
895 #gpio-cells = <2>;
896 #interrupt-cells = <2>
897 interrupt-parent = <&i
898 interrupt-controller;
899 gpio-ranges = <&pinctr
900 clocks = <&cpg CPG_MOD
901 power-domains = <&cpg>
902 resets = <&cpg R9A07G0
903 <&cpg R9A07G0
904 <&cpg R9A07G0
905 };
906
907 irqc: interrupt-controller@110
908 compatible = "renesas,
909 "renesas,
910 #interrupt-cells = <2>
911 #address-cells = <0>;
912 interrupt-controller;
913 reg = <0 0x110a0000 0
914 interrupts = <GIC_SPI
915 <GIC_SPI
916 <GIC_SPI
917 <GIC_SPI
918 <GIC_SPI
919 <GIC_SPI
920 <GIC_SPI
921 <GIC_SPI
922 <GIC_SPI
923 <GIC_SPI
924 <GIC_SPI
925 <GIC_SPI
926 <GIC_SPI
927 <GIC_SPI
928 <GIC_SPI
929 <GIC_SPI
930 <GIC_SPI
931 <GIC_SPI
932 <GIC_SPI
933 <GIC_SPI
934 <GIC_SPI
935 <GIC_SPI
936 <GIC_SPI
937 <GIC_SPI
938 <GIC_SPI
939 <GIC_SPI
940 <GIC_SPI
941 <GIC_SPI
942 <GIC_SPI
943 <GIC_SPI
944 <GIC_SPI
945 <GIC_SPI
946 <GIC_SPI
947 <GIC_SPI
948 <GIC_SPI
949 <GIC_SPI
950 <GIC_SPI
951 <GIC_SPI
952 <GIC_SPI
953 <GIC_SPI
954 <GIC_SPI
955 <GIC_SPI
956 <GIC_SPI
957 <GIC_SPI
958 <GIC_SPI
959 <GIC_SPI
960 <GIC_SPI
961 <GIC_SPI
962 interrupt-names = "nmi
963 "irq
964 "tin
965 "tin
966 "tin
967 "tin
968 "tin
969 "tin
970 "tin
971 "tin
972 "bus
973 "ec7
974 "ec7
975 clocks = <&cpg CPG_MOD
976 <&cpg CPG_MOD
977 clock-names = "clk", "
978 power-domains = <&cpg>
979 resets = <&cpg R9A07G0
980 };
981
982 dmac: dma-controller@11820000
983 compatible = "renesas,
984 "renesas,
985 reg = <0 0x11820000 0
986 <0 0x11830000 0
987 interrupts = <GIC_SPI
988 <GIC_SPI
989 <GIC_SPI
990 <GIC_SPI
991 <GIC_SPI
992 <GIC_SPI
993 <GIC_SPI
994 <GIC_SPI
995 <GIC_SPI
996 <GIC_SPI
997 <GIC_SPI
998 <GIC_SPI
999 <GIC_SPI
1000 <GIC_SPI
1001 <GIC_SPI
1002 <GIC_SPI
1003 <GIC_SPI
1004 interrupt-names = "er
1005 "ch
1006 "ch
1007 "ch
1008 "ch
1009 clocks = <&cpg CPG_MO
1010 <&cpg CPG_MO
1011 clock-names = "main",
1012 power-domains = <&cpg
1013 resets = <&cpg R9A07G
1014 <&cpg R9A07G
1015 reset-names = "arst",
1016 #dma-cells = <1>;
1017 dma-channels = <16>;
1018 };
1019
1020 gpu: gpu@11840000 {
1021 compatible = "renesas
1022 "arm,mal
1023 reg = <0x0 0x11840000
1024 interrupts = <GIC_SPI
1025 <GIC_SPI
1026 <GIC_SPI
1027 <GIC_SPI
1028 interrupt-names = "jo
1029 clocks = <&cpg CPG_MO
1030 <&cpg CPG_MO
1031 <&cpg CPG_MO
1032 clock-names = "gpu",
1033 power-domains = <&cpg
1034 resets = <&cpg R9A07G
1035 <&cpg R9A07G
1036 <&cpg R9A07G
1037 reset-names = "rst",
1038 operating-points-v2 =
1039 };
1040
1041 gic: interrupt-controller@119
1042 compatible = "arm,gic
1043 #interrupt-cells = <3
1044 #address-cells = <0>;
1045 interrupt-controller;
1046 reg = <0x0 0x11900000
1047 <0x0 0x11940000
1048 interrupts = <GIC_PPI
1049 };
1050
1051 sdhi0: mmc@11c00000 {
1052 compatible = "renesas
1053 "renesas
1054 reg = <0x0 0x11c00000
1055 interrupts = <GIC_SPI
1056 <GIC_SPI
1057 clocks = <&cpg CPG_MO
1058 <&cpg CPG_MO
1059 <&cpg CPG_MO
1060 <&cpg CPG_MO
1061 clock-names = "core",
1062 resets = <&cpg R9A07G
1063 power-domains = <&cpg
1064 status = "disabled";
1065 };
1066
1067 sdhi1: mmc@11c10000 {
1068 compatible = "renesas
1069 "renesas
1070 reg = <0x0 0x11c10000
1071 interrupts = <GIC_SPI
1072 <GIC_SPI
1073 clocks = <&cpg CPG_MO
1074 <&cpg CPG_MO
1075 <&cpg CPG_MO
1076 <&cpg CPG_MO
1077 clock-names = "core",
1078 resets = <&cpg R9A07G
1079 power-domains = <&cpg
1080 status = "disabled";
1081 };
1082
1083 eth0: ethernet@11c20000 {
1084 compatible = "renesas
1085 "renesas
1086 reg = <0 0x11c20000 0
1087 interrupts = <GIC_SPI
1088 <GIC_SPI
1089 <GIC_SPI
1090 interrupt-names = "mu
1091 phy-mode = "rgmii";
1092 clocks = <&cpg CPG_MO
1093 <&cpg CPG_MO
1094 <&cpg CPG_CO
1095 clock-names = "axi",
1096 resets = <&cpg R9A07G
1097 power-domains = <&cpg
1098 #address-cells = <1>;
1099 #size-cells = <0>;
1100 status = "disabled";
1101 };
1102
1103 eth1: ethernet@11c30000 {
1104 compatible = "renesas
1105 "renesas
1106 reg = <0 0x11c30000 0
1107 interrupts = <GIC_SPI
1108 <GIC_SPI
1109 <GIC_SPI
1110 interrupt-names = "mu
1111 phy-mode = "rgmii";
1112 clocks = <&cpg CPG_MO
1113 <&cpg CPG_MO
1114 <&cpg CPG_CO
1115 clock-names = "axi",
1116 resets = <&cpg R9A07G
1117 power-domains = <&cpg
1118 #address-cells = <1>;
1119 #size-cells = <0>;
1120 status = "disabled";
1121 };
1122
1123 phyrst: usbphy-ctrl@11c40000
1124 compatible = "renesas
1125 "renesas
1126 reg = <0 0x11c40000 0
1127 clocks = <&cpg CPG_MO
1128 resets = <&cpg R9A07G
1129 power-domains = <&cpg
1130 #reset-cells = <1>;
1131 status = "disabled";
1132
1133 usb0_vbus_otg: regula
1134 regulator-nam
1135 };
1136 };
1137
1138 ohci0: usb@11c50000 {
1139 compatible = "generic
1140 reg = <0 0x11c50000 0
1141 interrupts = <GIC_SPI
1142 clocks = <&cpg CPG_MO
1143 <&cpg CPG_MO
1144 resets = <&phyrst 0>,
1145 <&cpg R9A07G
1146 phys = <&usb2_phy0 1>
1147 phy-names = "usb";
1148 power-domains = <&cpg
1149 status = "disabled";
1150 };
1151
1152 ohci1: usb@11c70000 {
1153 compatible = "generic
1154 reg = <0 0x11c70000 0
1155 interrupts = <GIC_SPI
1156 clocks = <&cpg CPG_MO
1157 <&cpg CPG_MO
1158 resets = <&phyrst 1>,
1159 <&cpg R9A07G
1160 phys = <&usb2_phy1 1>
1161 phy-names = "usb";
1162 power-domains = <&cpg
1163 status = "disabled";
1164 };
1165
1166 ehci0: usb@11c50100 {
1167 compatible = "generic
1168 reg = <0 0x11c50100 0
1169 interrupts = <GIC_SPI
1170 clocks = <&cpg CPG_MO
1171 <&cpg CPG_MO
1172 resets = <&phyrst 0>,
1173 <&cpg R9A07G
1174 phys = <&usb2_phy0 2>
1175 phy-names = "usb";
1176 companion = <&ohci0>;
1177 power-domains = <&cpg
1178 status = "disabled";
1179 };
1180
1181 ehci1: usb@11c70100 {
1182 compatible = "generic
1183 reg = <0 0x11c70100 0
1184 interrupts = <GIC_SPI
1185 clocks = <&cpg CPG_MO
1186 <&cpg CPG_MO
1187 resets = <&phyrst 1>,
1188 <&cpg R9A07G
1189 phys = <&usb2_phy1 2>
1190 phy-names = "usb";
1191 companion = <&ohci1>;
1192 power-domains = <&cpg
1193 status = "disabled";
1194 };
1195
1196 usb2_phy0: usb-phy@11c50200 {
1197 compatible = "renesas
1198 "renesas
1199 reg = <0 0x11c50200 0
1200 interrupts = <GIC_SPI
1201 clocks = <&cpg CPG_MO
1202 <&cpg CPG_MO
1203 resets = <&phyrst 0>;
1204 #phy-cells = <1>;
1205 power-domains = <&cpg
1206 status = "disabled";
1207 };
1208
1209 usb2_phy1: usb-phy@11c70200 {
1210 compatible = "renesas
1211 "renesas
1212 reg = <0 0x11c70200 0
1213 interrupts = <GIC_SPI
1214 clocks = <&cpg CPG_MO
1215 <&cpg CPG_MO
1216 resets = <&phyrst 1>;
1217 #phy-cells = <1>;
1218 power-domains = <&cpg
1219 status = "disabled";
1220 };
1221
1222 hsusb: usb@11c60000 {
1223 compatible = "renesas
1224 "renesas
1225 reg = <0 0x11c60000 0
1226 interrupts = <GIC_SPI
1227 <GIC_SPI
1228 <GIC_SPI
1229 <GIC_SPI
1230 clocks = <&cpg CPG_MO
1231 <&cpg CPG_MO
1232 resets = <&phyrst 0>,
1233 <&cpg R9A07G
1234 renesas,buswait = <7>
1235 phys = <&usb2_phy0 3>
1236 phy-names = "usb";
1237 power-domains = <&cpg
1238 status = "disabled";
1239 };
1240
1241 wdt0: watchdog@12800800 {
1242 compatible = "renesas
1243 "renesas
1244 reg = <0 0x12800800 0
1245 clocks = <&cpg CPG_MO
1246 <&cpg CPG_MO
1247 clock-names = "pclk",
1248 interrupts = <GIC_SPI
1249 <GIC_SPI
1250 interrupt-names = "wd
1251 resets = <&cpg R9A07G
1252 power-domains = <&cpg
1253 status = "disabled";
1254 };
1255
1256 wdt1: watchdog@12800c00 {
1257 compatible = "renesas
1258 "renesas
1259 reg = <0 0x12800C00 0
1260 clocks = <&cpg CPG_MO
1261 <&cpg CPG_MO
1262 clock-names = "pclk",
1263 interrupts = <GIC_SPI
1264 <GIC_SPI
1265 interrupt-names = "wd
1266 resets = <&cpg R9A07G
1267 power-domains = <&cpg
1268 status = "disabled";
1269 };
1270
1271 ostm0: timer@12801000 {
1272 compatible = "renesas
1273 "renesas
1274 reg = <0x0 0x12801000
1275 interrupts = <GIC_SPI
1276 clocks = <&cpg CPG_MO
1277 resets = <&cpg R9A07G
1278 power-domains = <&cpg
1279 status = "disabled";
1280 };
1281
1282 ostm1: timer@12801400 {
1283 compatible = "renesas
1284 "renesas
1285 reg = <0x0 0x12801400
1286 interrupts = <GIC_SPI
1287 clocks = <&cpg CPG_MO
1288 resets = <&cpg R9A07G
1289 power-domains = <&cpg
1290 status = "disabled";
1291 };
1292
1293 ostm2: timer@12801800 {
1294 compatible = "renesas
1295 "renesas
1296 reg = <0x0 0x12801800
1297 interrupts = <GIC_SPI
1298 clocks = <&cpg CPG_MO
1299 resets = <&cpg R9A07G
1300 power-domains = <&cpg
1301 status = "disabled";
1302 };
1303 };
1304
1305 thermal-zones {
1306 cpu-thermal {
1307 polling-delay-passive
1308 polling-delay = <1000
1309 thermal-sensors = <&t
1310 sustainable-power = <
1311
1312 cooling-maps {
1313 map0 {
1314 trip
1315 cooli
1316 contr
1317 };
1318 };
1319
1320 trips {
1321 sensor_crit:
1322 tempe
1323 hyste
1324 type
1325 };
1326
1327 target: trip-
1328 tempe
1329 hyste
1330 type
1331 };
1332 };
1333 };
1334 };
1335
1336 timer {
1337 compatible = "arm,armv8-timer
1338 interrupts-extended = <&gic G
1339 <&gic G
1340 <&gic G
1341 <&gic G
1342 <&gic G
1343 interrupt-names = "sec-phys",
1344 "hyp-virt";
1345 };
1346 };
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