1 // SPDX-License-Identifier: (GPL-2.0-only OR B 1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 /* 2 /*
3 * Device Tree Source for the RZ/G2L and RZ/G2 3 * Device Tree Source for the RZ/G2L and RZ/G2LC common SoC parts
4 * 4 *
5 * Copyright (C) 2021 Renesas Electronics Corp 5 * Copyright (C) 2021 Renesas Electronics Corp.
6 */ 6 */
7 7
8 #include <dt-bindings/interrupt-controller/arm 8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/clock/r9a07g044-cpg.h> 9 #include <dt-bindings/clock/r9a07g044-cpg.h>
10 10
11 / { 11 / {
12 compatible = "renesas,r9a07g044"; 12 compatible = "renesas,r9a07g044";
13 #address-cells = <2>; 13 #address-cells = <2>;
14 #size-cells = <2>; 14 #size-cells = <2>;
15 15
16 audio_clk1: audio1-clk { !! 16 audio_clk1: audio_clk1 {
17 compatible = "fixed-clock"; 17 compatible = "fixed-clock";
18 #clock-cells = <0>; 18 #clock-cells = <0>;
19 /* This value must be overridd 19 /* This value must be overridden by boards that provide it */
20 clock-frequency = <0>; 20 clock-frequency = <0>;
21 }; 21 };
22 22
23 audio_clk2: audio2-clk { !! 23 audio_clk2: audio_clk2 {
24 compatible = "fixed-clock"; 24 compatible = "fixed-clock";
25 #clock-cells = <0>; 25 #clock-cells = <0>;
26 /* This value must be overridd 26 /* This value must be overridden by boards that provide it */
27 clock-frequency = <0>; 27 clock-frequency = <0>;
28 }; 28 };
29 29
30 /* External CAN clock - to be overridd 30 /* External CAN clock - to be overridden by boards that provide it */
31 can_clk: can-clk { !! 31 can_clk: can {
32 compatible = "fixed-clock"; 32 compatible = "fixed-clock";
33 #clock-cells = <0>; 33 #clock-cells = <0>;
34 clock-frequency = <0>; 34 clock-frequency = <0>;
35 }; 35 };
36 36
37 /* clock can be either from exclk or c 37 /* clock can be either from exclk or crystal oscillator (XIN/XOUT) */
38 extal_clk: extal-clk { !! 38 extal_clk: extal {
39 compatible = "fixed-clock"; 39 compatible = "fixed-clock";
40 #clock-cells = <0>; 40 #clock-cells = <0>;
41 /* This value must be overridd 41 /* This value must be overridden by the board */
42 clock-frequency = <0>; 42 clock-frequency = <0>;
43 }; 43 };
44 44
45 cluster0_opp: opp-table-0 { !! 45 psci {
46 compatible = "operating-points !! 46 compatible = "arm,psci-1.0", "arm,psci-0.2";
47 opp-shared; !! 47 method = "smc";
48 <<
49 opp-150000000 { <<
50 opp-hz = /bits/ 64 <15 <<
51 opp-microvolt = <11000 <<
52 clock-latency-ns = <30 <<
53 }; <<
54 opp-300000000 { <<
55 opp-hz = /bits/ 64 <30 <<
56 opp-microvolt = <11000 <<
57 clock-latency-ns = <30 <<
58 }; <<
59 opp-600000000 { <<
60 opp-hz = /bits/ 64 <60 <<
61 opp-microvolt = <11000 <<
62 clock-latency-ns = <30 <<
63 }; <<
64 opp-1200000000 { <<
65 opp-hz = /bits/ 64 <12 <<
66 opp-microvolt = <11000 <<
67 clock-latency-ns = <30 <<
68 opp-suspend; <<
69 }; <<
70 }; 48 };
71 49
72 cpus { 50 cpus {
73 #address-cells = <1>; 51 #address-cells = <1>;
74 #size-cells = <0>; 52 #size-cells = <0>;
75 53
76 cpu-map { 54 cpu-map {
77 cluster0 { 55 cluster0 {
78 core0 { 56 core0 {
79 cpu = 57 cpu = <&cpu0>;
80 }; 58 };
81 core1 { 59 core1 {
82 cpu = 60 cpu = <&cpu1>;
83 }; 61 };
84 }; 62 };
85 }; 63 };
86 64
87 cpu0: cpu@0 { 65 cpu0: cpu@0 {
88 compatible = "arm,cort 66 compatible = "arm,cortex-a55";
89 reg = <0>; 67 reg = <0>;
90 device_type = "cpu"; 68 device_type = "cpu";
91 #cooling-cells = <2>; <<
92 next-level-cache = <&L 69 next-level-cache = <&L3_CA55>;
93 enable-method = "psci" 70 enable-method = "psci";
94 clocks = <&cpg CPG_COR <<
95 operating-points-v2 = <<
96 }; 71 };
97 72
98 cpu1: cpu@100 { 73 cpu1: cpu@100 {
99 compatible = "arm,cort 74 compatible = "arm,cortex-a55";
100 reg = <0x100>; 75 reg = <0x100>;
101 device_type = "cpu"; 76 device_type = "cpu";
102 next-level-cache = <&L 77 next-level-cache = <&L3_CA55>;
103 enable-method = "psci" 78 enable-method = "psci";
104 clocks = <&cpg CPG_COR <<
105 operating-points-v2 = <<
106 }; 79 };
107 80
108 L3_CA55: cache-controller-0 { 81 L3_CA55: cache-controller-0 {
109 compatible = "cache"; 82 compatible = "cache";
110 cache-unified; 83 cache-unified;
111 cache-size = <0x40000> 84 cache-size = <0x40000>;
112 cache-level = <3>; <<
113 }; 85 };
114 }; 86 };
115 87
116 gpu_opp_table: opp-table-1 { <<
117 compatible = "operating-points <<
118 <<
119 opp-500000000 { <<
120 opp-hz = /bits/ 64 <50 <<
121 opp-microvolt = <11000 <<
122 }; <<
123 <<
124 opp-400000000 { <<
125 opp-hz = /bits/ 64 <40 <<
126 opp-microvolt = <11000 <<
127 }; <<
128 <<
129 opp-250000000 { <<
130 opp-hz = /bits/ 64 <25 <<
131 opp-microvolt = <11000 <<
132 }; <<
133 <<
134 opp-200000000 { <<
135 opp-hz = /bits/ 64 <20 <<
136 opp-microvolt = <11000 <<
137 }; <<
138 <<
139 opp-125000000 { <<
140 opp-hz = /bits/ 64 <12 <<
141 opp-microvolt = <11000 <<
142 }; <<
143 <<
144 opp-100000000 { <<
145 opp-hz = /bits/ 64 <10 <<
146 opp-microvolt = <11000 <<
147 }; <<
148 <<
149 opp-62500000 { <<
150 opp-hz = /bits/ 64 <62 <<
151 opp-microvolt = <11000 <<
152 }; <<
153 <<
154 opp-50000000 { <<
155 opp-hz = /bits/ 64 <50 <<
156 opp-microvolt = <11000 <<
157 }; <<
158 }; <<
159 <<
160 pmu { <<
161 compatible = "arm,cortex-a55-p <<
162 interrupts-extended = <&gic GI <<
163 }; <<
164 <<
165 psci { <<
166 compatible = "arm,psci-1.0", " <<
167 method = "smc"; <<
168 }; <<
169 <<
170 soc: soc { 88 soc: soc {
171 compatible = "simple-bus"; 89 compatible = "simple-bus";
172 interrupt-parent = <&gic>; 90 interrupt-parent = <&gic>;
173 #address-cells = <2>; 91 #address-cells = <2>;
174 #size-cells = <2>; 92 #size-cells = <2>;
175 ranges; 93 ranges;
176 94
177 mtu3: timer@10001200 { <<
178 compatible = "renesas, <<
179 "renesas, <<
180 reg = <0 0x10001200 0 <<
181 interrupts = <GIC_SPI <<
182 <GIC_SPI <<
183 <GIC_SPI <<
184 <GIC_SPI <<
185 <GIC_SPI <<
186 <GIC_SPI <<
187 <GIC_SPI <<
188 <GIC_SPI <<
189 <GIC_SPI <<
190 <GIC_SPI <<
191 <GIC_SPI <<
192 <GIC_SPI <<
193 <GIC_SPI <<
194 <GIC_SPI <<
195 <GIC_SPI <<
196 <GIC_SPI <<
197 <GIC_SPI <<
198 <GIC_SPI <<
199 <GIC_SPI <<
200 <GIC_SPI <<
201 <GIC_SPI <<
202 <GIC_SPI <<
203 <GIC_SPI <<
204 <GIC_SPI <<
205 <GIC_SPI <<
206 <GIC_SPI <<
207 <GIC_SPI <<
208 <GIC_SPI <<
209 <GIC_SPI <<
210 <GIC_SPI <<
211 <GIC_SPI <<
212 <GIC_SPI <<
213 <GIC_SPI <<
214 <GIC_SPI <<
215 <GIC_SPI <<
216 <GIC_SPI <<
217 <GIC_SPI <<
218 <GIC_SPI <<
219 <GIC_SPI <<
220 <GIC_SPI <<
221 <GIC_SPI <<
222 <GIC_SPI <<
223 <GIC_SPI <<
224 <GIC_SPI <<
225 interrupt-names = "tgi <<
226 "tci <<
227 "tgi <<
228 "tgi <<
229 "tgi <<
230 "tci <<
231 "tgi <<
232 "tci <<
233 "tgi <<
234 "tgi <<
235 "tci <<
236 "tgi <<
237 "tci <<
238 "tgi <<
239 "tci <<
240 clocks = <&cpg CPG_MOD <<
241 power-domains = <&cpg> <<
242 resets = <&cpg R9A07G0 <<
243 #pwm-cells = <2>; <<
244 status = "disabled"; <<
245 }; <<
246 <<
247 ssi0: ssi@10049c00 { 95 ssi0: ssi@10049c00 {
248 compatible = "renesas, 96 compatible = "renesas,r9a07g044-ssi",
249 "renesas, 97 "renesas,rz-ssi";
250 reg = <0 0x10049c00 0 98 reg = <0 0x10049c00 0 0x400>;
251 interrupts = <GIC_SPI 99 interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
252 <GIC_SPI 100 <GIC_SPI 327 IRQ_TYPE_EDGE_RISING>,
253 <GIC_SPI !! 101 <GIC_SPI 328 IRQ_TYPE_EDGE_RISING>,
254 interrupt-names = "int !! 102 <GIC_SPI 329 IRQ_TYPE_EDGE_RISING>;
>> 103 interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt";
255 clocks = <&cpg CPG_MOD 104 clocks = <&cpg CPG_MOD R9A07G044_SSI0_PCLK2>,
256 <&cpg CPG_MOD 105 <&cpg CPG_MOD R9A07G044_SSI0_PCLK_SFR>,
257 <&audio_clk1> 106 <&audio_clk1>, <&audio_clk2>;
258 clock-names = "ssi", " 107 clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2";
259 resets = <&cpg R9A07G0 108 resets = <&cpg R9A07G044_SSI0_RST_M2_REG>;
260 dmas = <&dmac 0x2655>, 109 dmas = <&dmac 0x2655>, <&dmac 0x2656>;
261 dma-names = "tx", "rx" 110 dma-names = "tx", "rx";
262 power-domains = <&cpg> 111 power-domains = <&cpg>;
263 #sound-dai-cells = <0> 112 #sound-dai-cells = <0>;
264 status = "disabled"; 113 status = "disabled";
265 }; 114 };
266 115
267 ssi1: ssi@1004a000 { 116 ssi1: ssi@1004a000 {
268 compatible = "renesas, 117 compatible = "renesas,r9a07g044-ssi",
269 "renesas, 118 "renesas,rz-ssi";
270 reg = <0 0x1004a000 0 119 reg = <0 0x1004a000 0 0x400>;
271 interrupts = <GIC_SPI 120 interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
272 <GIC_SPI 121 <GIC_SPI 331 IRQ_TYPE_EDGE_RISING>,
273 <GIC_SPI !! 122 <GIC_SPI 332 IRQ_TYPE_EDGE_RISING>,
274 interrupt-names = "int !! 123 <GIC_SPI 333 IRQ_TYPE_EDGE_RISING>;
>> 124 interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt";
275 clocks = <&cpg CPG_MOD 125 clocks = <&cpg CPG_MOD R9A07G044_SSI1_PCLK2>,
276 <&cpg CPG_MOD 126 <&cpg CPG_MOD R9A07G044_SSI1_PCLK_SFR>,
277 <&audio_clk1> 127 <&audio_clk1>, <&audio_clk2>;
278 clock-names = "ssi", " 128 clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2";
279 resets = <&cpg R9A07G0 129 resets = <&cpg R9A07G044_SSI1_RST_M2_REG>;
280 dmas = <&dmac 0x2659>, 130 dmas = <&dmac 0x2659>, <&dmac 0x265a>;
281 dma-names = "tx", "rx" 131 dma-names = "tx", "rx";
282 power-domains = <&cpg> 132 power-domains = <&cpg>;
283 #sound-dai-cells = <0> 133 #sound-dai-cells = <0>;
284 status = "disabled"; 134 status = "disabled";
285 }; 135 };
286 136
287 ssi2: ssi@1004a400 { 137 ssi2: ssi@1004a400 {
288 compatible = "renesas, 138 compatible = "renesas,r9a07g044-ssi",
289 "renesas, 139 "renesas,rz-ssi";
290 reg = <0 0x1004a400 0 140 reg = <0 0x1004a400 0 0x400>;
291 interrupts = <GIC_SPI 141 interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
>> 142 <GIC_SPI 335 IRQ_TYPE_EDGE_RISING>,
>> 143 <GIC_SPI 336 IRQ_TYPE_EDGE_RISING>,
292 <GIC_SPI 144 <GIC_SPI 337 IRQ_TYPE_EDGE_RISING>;
293 interrupt-names = "int !! 145 interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt";
294 clocks = <&cpg CPG_MOD 146 clocks = <&cpg CPG_MOD R9A07G044_SSI2_PCLK2>,
295 <&cpg CPG_MOD 147 <&cpg CPG_MOD R9A07G044_SSI2_PCLK_SFR>,
296 <&audio_clk1> 148 <&audio_clk1>, <&audio_clk2>;
297 clock-names = "ssi", " 149 clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2";
298 resets = <&cpg R9A07G0 150 resets = <&cpg R9A07G044_SSI2_RST_M2_REG>;
299 dmas = <&dmac 0x265f>; 151 dmas = <&dmac 0x265f>;
300 dma-names = "rt"; 152 dma-names = "rt";
301 power-domains = <&cpg> 153 power-domains = <&cpg>;
302 #sound-dai-cells = <0> 154 #sound-dai-cells = <0>;
303 status = "disabled"; 155 status = "disabled";
304 }; 156 };
305 157
306 ssi3: ssi@1004a800 { 158 ssi3: ssi@1004a800 {
307 compatible = "renesas, 159 compatible = "renesas,r9a07g044-ssi",
308 "renesas, 160 "renesas,rz-ssi";
309 reg = <0 0x1004a800 0 161 reg = <0 0x1004a800 0 0x400>;
310 interrupts = <GIC_SPI 162 interrupts = <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
311 <GIC_SPI 163 <GIC_SPI 339 IRQ_TYPE_EDGE_RISING>,
312 <GIC_SPI !! 164 <GIC_SPI 340 IRQ_TYPE_EDGE_RISING>,
313 interrupt-names = "int !! 165 <GIC_SPI 341 IRQ_TYPE_EDGE_RISING>;
>> 166 interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt";
314 clocks = <&cpg CPG_MOD 167 clocks = <&cpg CPG_MOD R9A07G044_SSI3_PCLK2>,
315 <&cpg CPG_MOD 168 <&cpg CPG_MOD R9A07G044_SSI3_PCLK_SFR>,
316 <&audio_clk1> 169 <&audio_clk1>, <&audio_clk2>;
317 clock-names = "ssi", " 170 clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2";
318 resets = <&cpg R9A07G0 171 resets = <&cpg R9A07G044_SSI3_RST_M2_REG>;
319 dmas = <&dmac 0x2661>, 172 dmas = <&dmac 0x2661>, <&dmac 0x2662>;
320 dma-names = "tx", "rx" 173 dma-names = "tx", "rx";
321 power-domains = <&cpg> 174 power-domains = <&cpg>;
322 #sound-dai-cells = <0> 175 #sound-dai-cells = <0>;
323 status = "disabled"; 176 status = "disabled";
324 }; 177 };
325 178
326 spi0: spi@1004ac00 { <<
327 compatible = "renesas, <<
328 reg = <0 0x1004ac00 0 <<
329 interrupts = <GIC_SPI <<
330 <GIC_SPI <<
331 <GIC_SPI <<
332 interrupt-names = "err <<
333 clocks = <&cpg CPG_MOD <<
334 resets = <&cpg R9A07G0 <<
335 dmas = <&dmac 0x2e95>, <<
336 dma-names = "tx", "rx" <<
337 power-domains = <&cpg> <<
338 num-cs = <1>; <<
339 #address-cells = <1>; <<
340 #size-cells = <0>; <<
341 status = "disabled"; <<
342 }; <<
343 <<
344 spi1: spi@1004b000 { <<
345 compatible = "renesas, <<
346 reg = <0 0x1004b000 0 <<
347 interrupts = <GIC_SPI <<
348 <GIC_SPI <<
349 <GIC_SPI <<
350 interrupt-names = "err <<
351 clocks = <&cpg CPG_MOD <<
352 resets = <&cpg R9A07G0 <<
353 dmas = <&dmac 0x2e99>, <<
354 dma-names = "tx", "rx" <<
355 power-domains = <&cpg> <<
356 num-cs = <1>; <<
357 #address-cells = <1>; <<
358 #size-cells = <0>; <<
359 status = "disabled"; <<
360 }; <<
361 <<
362 spi2: spi@1004b400 { <<
363 compatible = "renesas, <<
364 reg = <0 0x1004b400 0 <<
365 interrupts = <GIC_SPI <<
366 <GIC_SPI <<
367 <GIC_SPI <<
368 interrupt-names = "err <<
369 clocks = <&cpg CPG_MOD <<
370 resets = <&cpg R9A07G0 <<
371 dmas = <&dmac 0x2e9d>, <<
372 dma-names = "tx", "rx" <<
373 power-domains = <&cpg> <<
374 num-cs = <1>; <<
375 #address-cells = <1>; <<
376 #size-cells = <0>; <<
377 status = "disabled"; <<
378 }; <<
379 <<
380 scif0: serial@1004b800 { 179 scif0: serial@1004b800 {
381 compatible = "renesas, 180 compatible = "renesas,scif-r9a07g044";
382 reg = <0 0x1004b800 0 181 reg = <0 0x1004b800 0 0x400>;
383 interrupts = <GIC_SPI 182 interrupts = <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>,
384 <GIC_SPI 183 <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>,
385 <GIC_SPI 184 <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>,
386 <GIC_SPI 185 <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>,
387 <GIC_SPI 186 <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>,
388 <GIC_SPI 187 <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>;
389 interrupt-names = "eri 188 interrupt-names = "eri", "rxi", "txi",
390 "bri 189 "bri", "dri", "tei";
391 clocks = <&cpg CPG_MOD 190 clocks = <&cpg CPG_MOD R9A07G044_SCIF0_CLK_PCK>;
392 clock-names = "fck"; 191 clock-names = "fck";
393 power-domains = <&cpg> 192 power-domains = <&cpg>;
394 resets = <&cpg R9A07G0 193 resets = <&cpg R9A07G044_SCIF0_RST_SYSTEM_N>;
395 status = "disabled"; 194 status = "disabled";
396 }; 195 };
397 196
398 scif1: serial@1004bc00 { <<
399 compatible = "renesas, <<
400 reg = <0 0x1004bc00 0 <<
401 interrupts = <GIC_SPI <<
402 <GIC_SPI <<
403 <GIC_SPI <<
404 <GIC_SPI <<
405 <GIC_SPI <<
406 <GIC_SPI <<
407 interrupt-names = "eri <<
408 "bri <<
409 clocks = <&cpg CPG_MOD <<
410 clock-names = "fck"; <<
411 power-domains = <&cpg> <<
412 resets = <&cpg R9A07G0 <<
413 status = "disabled"; <<
414 }; <<
415 <<
416 scif2: serial@1004c000 { <<
417 compatible = "renesas, <<
418 reg = <0 0x1004c000 0 <<
419 interrupts = <GIC_SPI <<
420 <GIC_SPI <<
421 <GIC_SPI <<
422 <GIC_SPI <<
423 <GIC_SPI <<
424 <GIC_SPI <<
425 interrupt-names = "eri <<
426 "bri <<
427 clocks = <&cpg CPG_MOD <<
428 clock-names = "fck"; <<
429 power-domains = <&cpg> <<
430 resets = <&cpg R9A07G0 <<
431 status = "disabled"; <<
432 }; <<
433 <<
434 scif3: serial@1004c400 { <<
435 compatible = "renesas, <<
436 reg = <0 0x1004c400 0 <<
437 interrupts = <GIC_SPI <<
438 <GIC_SPI <<
439 <GIC_SPI <<
440 <GIC_SPI <<
441 <GIC_SPI <<
442 <GIC_SPI <<
443 interrupt-names = "eri <<
444 "bri <<
445 clocks = <&cpg CPG_MOD <<
446 clock-names = "fck"; <<
447 power-domains = <&cpg> <<
448 resets = <&cpg R9A07G0 <<
449 status = "disabled"; <<
450 }; <<
451 <<
452 scif4: serial@1004c800 { <<
453 compatible = "renesas, <<
454 reg = <0 0x1004c800 0 <<
455 interrupts = <GIC_SPI <<
456 <GIC_SPI <<
457 <GIC_SPI <<
458 <GIC_SPI <<
459 <GIC_SPI <<
460 <GIC_SPI <<
461 interrupt-names = "eri <<
462 "bri <<
463 clocks = <&cpg CPG_MOD <<
464 clock-names = "fck"; <<
465 power-domains = <&cpg> <<
466 resets = <&cpg R9A07G0 <<
467 status = "disabled"; <<
468 }; <<
469 <<
470 sci0: serial@1004d000 { <<
471 compatible = "renesas, <<
472 reg = <0 0x1004d000 0 <<
473 interrupts = <GIC_SPI <<
474 <GIC_SPI <<
475 <GIC_SPI <<
476 <GIC_SPI <<
477 interrupt-names = "eri <<
478 clocks = <&cpg CPG_MOD <<
479 clock-names = "fck"; <<
480 power-domains = <&cpg> <<
481 resets = <&cpg R9A07G0 <<
482 status = "disabled"; <<
483 }; <<
484 <<
485 sci1: serial@1004d400 { <<
486 compatible = "renesas, <<
487 reg = <0 0x1004d400 0 <<
488 interrupts = <GIC_SPI <<
489 <GIC_SPI <<
490 <GIC_SPI <<
491 <GIC_SPI <<
492 interrupt-names = "eri <<
493 clocks = <&cpg CPG_MOD <<
494 clock-names = "fck"; <<
495 power-domains = <&cpg> <<
496 resets = <&cpg R9A07G0 <<
497 status = "disabled"; <<
498 }; <<
499 <<
500 canfd: can@10050000 { 197 canfd: can@10050000 {
501 compatible = "renesas, 198 compatible = "renesas,r9a07g044-canfd", "renesas,rzg2l-canfd";
502 reg = <0 0x10050000 0 199 reg = <0 0x10050000 0 0x8000>;
503 interrupts = <GIC_SPI 200 interrupts = <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>,
504 <GIC_SPI 201 <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>,
505 <GIC_SPI 202 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
506 <GIC_SPI 203 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
507 <GIC_SPI 204 <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>,
508 <GIC_SPI 205 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
509 <GIC_SPI 206 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
510 <GIC_SPI 207 <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>;
511 interrupt-names = "g_e 208 interrupt-names = "g_err", "g_recc",
512 "ch0 209 "ch0_err", "ch0_rec", "ch0_trx",
513 "ch1 210 "ch1_err", "ch1_rec", "ch1_trx";
514 clocks = <&cpg CPG_MOD 211 clocks = <&cpg CPG_MOD R9A07G044_CANFD_PCLK>,
515 <&cpg CPG_COR 212 <&cpg CPG_CORE R9A07G044_CLK_P0_DIV2>,
516 <&can_clk>; 213 <&can_clk>;
517 clock-names = "fck", " 214 clock-names = "fck", "canfd", "can_clk";
518 assigned-clocks = <&cp 215 assigned-clocks = <&cpg CPG_CORE R9A07G044_CLK_P0_DIV2>;
519 assigned-clock-rates = 216 assigned-clock-rates = <50000000>;
520 resets = <&cpg R9A07G0 217 resets = <&cpg R9A07G044_CANFD_RSTP_N>,
521 <&cpg R9A07G0 218 <&cpg R9A07G044_CANFD_RSTC_N>;
522 reset-names = "rstp_n" 219 reset-names = "rstp_n", "rstc_n";
523 power-domains = <&cpg> 220 power-domains = <&cpg>;
524 status = "disabled"; 221 status = "disabled";
525 222
526 channel0 { 223 channel0 {
527 status = "disa 224 status = "disabled";
528 }; 225 };
529 channel1 { 226 channel1 {
530 status = "disa 227 status = "disabled";
531 }; 228 };
532 }; 229 };
533 230
534 i2c0: i2c@10058000 { 231 i2c0: i2c@10058000 {
535 #address-cells = <1>; 232 #address-cells = <1>;
536 #size-cells = <0>; 233 #size-cells = <0>;
537 compatible = "renesas, 234 compatible = "renesas,riic-r9a07g044", "renesas,riic-rz";
538 reg = <0 0x10058000 0 235 reg = <0 0x10058000 0 0x400>;
539 interrupts = <GIC_SPI 236 interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>,
540 <GIC_SPI 237 <GIC_SPI 348 IRQ_TYPE_EDGE_RISING>,
541 <GIC_SPI 238 <GIC_SPI 349 IRQ_TYPE_EDGE_RISING>,
542 <GIC_SPI 239 <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>,
543 <GIC_SPI 240 <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>,
544 <GIC_SPI 241 <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>,
545 <GIC_SPI 242 <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>,
546 <GIC_SPI 243 <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
547 interrupt-names = "tei 244 interrupt-names = "tei", "ri", "ti", "spi", "sti",
548 "nak 245 "naki", "ali", "tmoi";
549 clocks = <&cpg CPG_MOD 246 clocks = <&cpg CPG_MOD R9A07G044_I2C0_PCLK>;
550 clock-frequency = <100 247 clock-frequency = <100000>;
551 resets = <&cpg R9A07G0 248 resets = <&cpg R9A07G044_I2C0_MRST>;
552 power-domains = <&cpg> 249 power-domains = <&cpg>;
553 status = "disabled"; 250 status = "disabled";
554 }; 251 };
555 252
556 i2c1: i2c@10058400 { 253 i2c1: i2c@10058400 {
557 #address-cells = <1>; 254 #address-cells = <1>;
558 #size-cells = <0>; 255 #size-cells = <0>;
559 compatible = "renesas, 256 compatible = "renesas,riic-r9a07g044", "renesas,riic-rz";
560 reg = <0 0x10058400 0 257 reg = <0 0x10058400 0 0x400>;
561 interrupts = <GIC_SPI 258 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>,
562 <GIC_SPI 259 <GIC_SPI 356 IRQ_TYPE_EDGE_RISING>,
563 <GIC_SPI 260 <GIC_SPI 357 IRQ_TYPE_EDGE_RISING>,
564 <GIC_SPI 261 <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>,
565 <GIC_SPI 262 <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>,
566 <GIC_SPI 263 <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>,
567 <GIC_SPI 264 <GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH>,
568 <GIC_SPI 265 <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>;
569 interrupt-names = "tei 266 interrupt-names = "tei", "ri", "ti", "spi", "sti",
570 "nak 267 "naki", "ali", "tmoi";
571 clocks = <&cpg CPG_MOD 268 clocks = <&cpg CPG_MOD R9A07G044_I2C1_PCLK>;
572 clock-frequency = <100 269 clock-frequency = <100000>;
573 resets = <&cpg R9A07G0 270 resets = <&cpg R9A07G044_I2C1_MRST>;
574 power-domains = <&cpg> 271 power-domains = <&cpg>;
575 status = "disabled"; 272 status = "disabled";
576 }; 273 };
577 274
578 i2c2: i2c@10058800 { 275 i2c2: i2c@10058800 {
579 #address-cells = <1>; 276 #address-cells = <1>;
580 #size-cells = <0>; 277 #size-cells = <0>;
581 compatible = "renesas, 278 compatible = "renesas,riic-r9a07g044", "renesas,riic-rz";
582 reg = <0 0x10058800 0 279 reg = <0 0x10058800 0 0x400>;
583 interrupts = <GIC_SPI 280 interrupts = <GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>,
584 <GIC_SPI 281 <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>,
585 <GIC_SPI 282 <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>,
586 <GIC_SPI 283 <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>,
587 <GIC_SPI 284 <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>,
588 <GIC_SPI 285 <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>,
589 <GIC_SPI 286 <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>,
590 <GIC_SPI 287 <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
591 interrupt-names = "tei 288 interrupt-names = "tei", "ri", "ti", "spi", "sti",
592 "nak 289 "naki", "ali", "tmoi";
593 clocks = <&cpg CPG_MOD 290 clocks = <&cpg CPG_MOD R9A07G044_I2C2_PCLK>;
594 clock-frequency = <100 291 clock-frequency = <100000>;
595 resets = <&cpg R9A07G0 292 resets = <&cpg R9A07G044_I2C2_MRST>;
596 power-domains = <&cpg> 293 power-domains = <&cpg>;
597 status = "disabled"; 294 status = "disabled";
598 }; 295 };
599 296
600 i2c3: i2c@10058c00 { 297 i2c3: i2c@10058c00 {
601 #address-cells = <1>; 298 #address-cells = <1>;
602 #size-cells = <0>; 299 #size-cells = <0>;
603 compatible = "renesas, 300 compatible = "renesas,riic-r9a07g044", "renesas,riic-rz";
604 reg = <0 0x10058c00 0 301 reg = <0 0x10058c00 0 0x400>;
605 interrupts = <GIC_SPI 302 interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>,
606 <GIC_SPI 303 <GIC_SPI 372 IRQ_TYPE_EDGE_RISING>,
607 <GIC_SPI 304 <GIC_SPI 373 IRQ_TYPE_EDGE_RISING>,
608 <GIC_SPI 305 <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>,
609 <GIC_SPI 306 <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>,
610 <GIC_SPI 307 <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>,
611 <GIC_SPI 308 <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>,
612 <GIC_SPI 309 <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
613 interrupt-names = "tei 310 interrupt-names = "tei", "ri", "ti", "spi", "sti",
614 "nak 311 "naki", "ali", "tmoi";
615 clocks = <&cpg CPG_MOD 312 clocks = <&cpg CPG_MOD R9A07G044_I2C3_PCLK>;
616 clock-frequency = <100 313 clock-frequency = <100000>;
617 resets = <&cpg R9A07G0 314 resets = <&cpg R9A07G044_I2C3_MRST>;
618 power-domains = <&cpg> 315 power-domains = <&cpg>;
619 status = "disabled"; 316 status = "disabled";
620 }; 317 };
621 318
622 adc: adc@10059000 { 319 adc: adc@10059000 {
623 compatible = "renesas, 320 compatible = "renesas,r9a07g044-adc", "renesas,rzg2l-adc";
624 reg = <0 0x10059000 0 321 reg = <0 0x10059000 0 0x400>;
625 interrupts = <GIC_SPI 322 interrupts = <GIC_SPI 347 IRQ_TYPE_EDGE_RISING>;
626 clocks = <&cpg CPG_MOD 323 clocks = <&cpg CPG_MOD R9A07G044_ADC_ADCLK>,
627 <&cpg CPG_MOD 324 <&cpg CPG_MOD R9A07G044_ADC_PCLK>;
628 clock-names = "adclk", 325 clock-names = "adclk", "pclk";
629 resets = <&cpg R9A07G0 326 resets = <&cpg R9A07G044_ADC_PRESETN>,
630 <&cpg R9A07G0 327 <&cpg R9A07G044_ADC_ADRST_N>;
631 reset-names = "presetn 328 reset-names = "presetn", "adrst-n";
632 power-domains = <&cpg> 329 power-domains = <&cpg>;
633 status = "disabled"; 330 status = "disabled";
634 331
635 #address-cells = <1>; 332 #address-cells = <1>;
636 #size-cells = <0>; 333 #size-cells = <0>;
637 334
638 channel@0 { 335 channel@0 {
639 reg = <0>; 336 reg = <0>;
640 }; 337 };
641 channel@1 { 338 channel@1 {
642 reg = <1>; 339 reg = <1>;
643 }; 340 };
644 channel@2 { 341 channel@2 {
645 reg = <2>; 342 reg = <2>;
646 }; 343 };
647 channel@3 { 344 channel@3 {
648 reg = <3>; 345 reg = <3>;
649 }; 346 };
650 channel@4 { 347 channel@4 {
651 reg = <4>; 348 reg = <4>;
652 }; 349 };
653 channel@5 { 350 channel@5 {
654 reg = <5>; 351 reg = <5>;
655 }; 352 };
656 channel@6 { 353 channel@6 {
657 reg = <6>; 354 reg = <6>;
658 }; 355 };
659 channel@7 { 356 channel@7 {
660 reg = <7>; 357 reg = <7>;
661 }; 358 };
662 }; 359 };
663 360
664 tsu: thermal@10059400 { <<
665 compatible = "renesas, <<
666 "renesas, <<
667 reg = <0 0x10059400 0 <<
668 clocks = <&cpg CPG_MOD <<
669 resets = <&cpg R9A07G0 <<
670 power-domains = <&cpg> <<
671 #thermal-sensor-cells <<
672 }; <<
673 <<
674 sbc: spi@10060000 { 361 sbc: spi@10060000 {
675 compatible = "renesas, 362 compatible = "renesas,r9a07g044-rpc-if",
676 "renesas, 363 "renesas,rzg2l-rpc-if";
677 reg = <0 0x10060000 0 364 reg = <0 0x10060000 0 0x10000>,
678 <0 0x20000000 0 365 <0 0x20000000 0 0x10000000>,
679 <0 0x10070000 0 366 <0 0x10070000 0 0x10000>;
680 reg-names = "regs", "d 367 reg-names = "regs", "dirmap", "wbuf";
681 interrupts = <GIC_SPI 368 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
682 clocks = <&cpg CPG_MOD 369 clocks = <&cpg CPG_MOD R9A07G044_SPI_CLK2>,
683 <&cpg CPG_MOD 370 <&cpg CPG_MOD R9A07G044_SPI_CLK>;
684 resets = <&cpg R9A07G0 371 resets = <&cpg R9A07G044_SPI_RST>;
685 power-domains = <&cpg> 372 power-domains = <&cpg>;
686 #address-cells = <1>; 373 #address-cells = <1>;
687 #size-cells = <0>; 374 #size-cells = <0>;
688 status = "disabled"; 375 status = "disabled";
689 }; 376 };
690 377
691 cru: video@10830000 { <<
692 compatible = "renesas, <<
693 reg = <0 0x10830000 0 <<
694 clocks = <&cpg CPG_MOD <<
695 <&cpg CPG_MOD <<
696 <&cpg CPG_MOD <<
697 clock-names = "video", <<
698 interrupts = <GIC_SPI <<
699 <GIC_SPI <<
700 <GIC_SPI <<
701 interrupt-names = "ima <<
702 resets = <&cpg R9A07G0 <<
703 <&cpg R9A07G0 <<
704 reset-names = "presetn <<
705 power-domains = <&cpg> <<
706 status = "disabled"; <<
707 <<
708 ports { <<
709 #address-cells <<
710 #size-cells = <<
711 <<
712 port@0 { <<
713 #addre <<
714 #size- <<
715 <<
716 reg = <<
717 crupar <<
718 <<
719 }; <<
720 }; <<
721 <<
722 port@1 { <<
723 #addre <<
724 #size- <<
725 <<
726 reg = <<
727 crucsi <<
728 <<
729 <<
730 }; <<
731 }; <<
732 }; <<
733 }; <<
734 <<
735 csi2: csi2@10830400 { <<
736 compatible = "renesas, <<
737 reg = <0 0x10830400 0 <<
738 interrupts = <GIC_SPI <<
739 clocks = <&cpg CPG_MOD <<
740 <&cpg CPG_MOD <<
741 <&cpg CPG_MOD <<
742 clock-names = "system" <<
743 resets = <&cpg R9A07G0 <<
744 <&cpg R9A07G0 <<
745 reset-names = "presetn <<
746 power-domains = <&cpg> <<
747 status = "disabled"; <<
748 <<
749 ports { <<
750 #address-cells <<
751 #size-cells = <<
752 <<
753 port@0 { <<
754 reg = <<
755 }; <<
756 <<
757 port@1 { <<
758 #addre <<
759 #size- <<
760 reg = <<
761 <<
762 csi2cr <<
763 <<
764 <<
765 }; <<
766 }; <<
767 }; <<
768 }; <<
769 <<
770 dsi: dsi@10850000 { <<
771 compatible = "renesas, <<
772 "renesas, <<
773 reg = <0 0x10850000 0 <<
774 interrupts = <GIC_SPI <<
775 <GIC_SPI <<
776 <GIC_SPI <<
777 <GIC_SPI <<
778 <GIC_SPI <<
779 <GIC_SPI <<
780 <GIC_SPI <<
781 interrupt-names = "seq <<
782 "fer <<
783 clocks = <&cpg CPG_MOD <<
784 <&cpg CPG_MOD <<
785 <&cpg CPG_MOD <<
786 <&cpg CPG_MOD <<
787 <&cpg CPG_MOD <<
788 <&cpg CPG_MOD <<
789 clock-names = "pllclk" <<
790 resets = <&cpg R9A07G0 <<
791 <&cpg R9A07G0 <<
792 <&cpg R9A07G0 <<
793 reset-names = "rst", " <<
794 power-domains = <&cpg> <<
795 status = "disabled"; <<
796 <<
797 ports { <<
798 #address-cells <<
799 #size-cells = <<
800 <<
801 port@0 { <<
802 reg = <<
803 dsi0_i <<
804 <<
805 }; <<
806 }; <<
807 <<
808 port@1 { <<
809 reg = <<
810 }; <<
811 }; <<
812 }; <<
813 <<
814 vspd: vsp@10870000 { <<
815 compatible = "renesas, <<
816 reg = <0 0x10870000 0 <<
817 interrupts = <GIC_SPI <<
818 clocks = <&cpg CPG_MOD <<
819 <&cpg CPG_MOD <<
820 <&cpg CPG_MOD <<
821 clock-names = "aclk", <<
822 power-domains = <&cpg> <<
823 resets = <&cpg R9A07G0 <<
824 renesas,fcp = <&fcpvd> <<
825 }; <<
826 <<
827 fcpvd: fcp@10880000 { <<
828 compatible = "renesas, <<
829 "renesas, <<
830 reg = <0 0x10880000 0 <<
831 clocks = <&cpg CPG_MOD <<
832 <&cpg CPG_MOD <<
833 <&cpg CPG_MOD <<
834 clock-names = "aclk", <<
835 power-domains = <&cpg> <<
836 resets = <&cpg R9A07G0 <<
837 }; <<
838 <<
839 du: display@10890000 { <<
840 compatible = "renesas, <<
841 reg = <0 0x10890000 0 <<
842 interrupts = <GIC_SPI <<
843 clocks = <&cpg CPG_MOD <<
844 <&cpg CPG_MOD <<
845 <&cpg CPG_MOD <<
846 clock-names = "aclk", <<
847 power-domains = <&cpg> <<
848 resets = <&cpg R9A07G0 <<
849 renesas,vsps = <&vspd <<
850 status = "disabled"; <<
851 <<
852 ports { <<
853 #address-cells <<
854 #size-cells = <<
855 <<
856 port@0 { <<
857 reg = <<
858 du_out <<
859 <<
860 }; <<
861 }; <<
862 <<
863 port@1 { <<
864 reg = <<
865 }; <<
866 }; <<
867 }; <<
868 <<
869 cpg: clock-controller@11010000 378 cpg: clock-controller@11010000 {
870 compatible = "renesas, 379 compatible = "renesas,r9a07g044-cpg";
871 reg = <0 0x11010000 0 380 reg = <0 0x11010000 0 0x10000>;
872 clocks = <&extal_clk>; 381 clocks = <&extal_clk>;
873 clock-names = "extal"; 382 clock-names = "extal";
874 #clock-cells = <2>; 383 #clock-cells = <2>;
875 #reset-cells = <1>; 384 #reset-cells = <1>;
876 #power-domain-cells = 385 #power-domain-cells = <0>;
877 }; 386 };
878 387
879 sysc: system-controller@110200 388 sysc: system-controller@11020000 {
880 compatible = "renesas, 389 compatible = "renesas,r9a07g044-sysc";
881 reg = <0 0x11020000 0 390 reg = <0 0x11020000 0 0x10000>;
882 interrupts = <GIC_SPI 391 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
883 <GIC_SPI 392 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
884 <GIC_SPI 393 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
885 <GIC_SPI 394 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
886 interrupt-names = "lpm 395 interrupt-names = "lpm_int", "ca55stbydone_int",
887 "cm3 396 "cm33stbyr_int", "ca55_deny";
888 status = "disabled"; 397 status = "disabled";
889 }; 398 };
890 399
891 pinctrl: pinctrl@11030000 { !! 400 pinctrl: pin-controller@11030000 {
892 compatible = "renesas, 401 compatible = "renesas,r9a07g044-pinctrl";
893 reg = <0 0x11030000 0 402 reg = <0 0x11030000 0 0x10000>;
894 gpio-controller; 403 gpio-controller;
895 #gpio-cells = <2>; 404 #gpio-cells = <2>;
896 #interrupt-cells = <2> <<
897 interrupt-parent = <&i <<
898 interrupt-controller; <<
899 gpio-ranges = <&pinctr 405 gpio-ranges = <&pinctrl 0 0 392>;
900 clocks = <&cpg CPG_MOD 406 clocks = <&cpg CPG_MOD R9A07G044_GPIO_HCLK>;
901 power-domains = <&cpg> 407 power-domains = <&cpg>;
902 resets = <&cpg R9A07G0 408 resets = <&cpg R9A07G044_GPIO_RSTN>,
903 <&cpg R9A07G0 409 <&cpg R9A07G044_GPIO_PORT_RESETN>,
904 <&cpg R9A07G0 410 <&cpg R9A07G044_GPIO_SPARE_RESETN>;
905 }; 411 };
906 412
907 irqc: interrupt-controller@110 <<
908 compatible = "renesas, <<
909 "renesas, <<
910 #interrupt-cells = <2> <<
911 #address-cells = <0>; <<
912 interrupt-controller; <<
913 reg = <0 0x110a0000 0 <<
914 interrupts = <GIC_SPI <<
915 <GIC_SPI <<
916 <GIC_SPI <<
917 <GIC_SPI <<
918 <GIC_SPI <<
919 <GIC_SPI <<
920 <GIC_SPI <<
921 <GIC_SPI <<
922 <GIC_SPI <<
923 <GIC_SPI <<
924 <GIC_SPI <<
925 <GIC_SPI <<
926 <GIC_SPI <<
927 <GIC_SPI <<
928 <GIC_SPI <<
929 <GIC_SPI <<
930 <GIC_SPI <<
931 <GIC_SPI <<
932 <GIC_SPI <<
933 <GIC_SPI <<
934 <GIC_SPI <<
935 <GIC_SPI <<
936 <GIC_SPI <<
937 <GIC_SPI <<
938 <GIC_SPI <<
939 <GIC_SPI <<
940 <GIC_SPI <<
941 <GIC_SPI <<
942 <GIC_SPI <<
943 <GIC_SPI <<
944 <GIC_SPI <<
945 <GIC_SPI <<
946 <GIC_SPI <<
947 <GIC_SPI <<
948 <GIC_SPI <<
949 <GIC_SPI <<
950 <GIC_SPI <<
951 <GIC_SPI <<
952 <GIC_SPI <<
953 <GIC_SPI <<
954 <GIC_SPI <<
955 <GIC_SPI <<
956 <GIC_SPI <<
957 <GIC_SPI <<
958 <GIC_SPI <<
959 <GIC_SPI <<
960 <GIC_SPI <<
961 <GIC_SPI <<
962 interrupt-names = "nmi <<
963 "irq <<
964 "tin <<
965 "tin <<
966 "tin <<
967 "tin <<
968 "tin <<
969 "tin <<
970 "tin <<
971 "tin <<
972 "bus <<
973 "ec7 <<
974 "ec7 <<
975 clocks = <&cpg CPG_MOD <<
976 <&cpg CPG_MOD <<
977 clock-names = "clk", " <<
978 power-domains = <&cpg> <<
979 resets = <&cpg R9A07G0 <<
980 }; <<
981 <<
982 dmac: dma-controller@11820000 413 dmac: dma-controller@11820000 {
983 compatible = "renesas, 414 compatible = "renesas,r9a07g044-dmac",
984 "renesas, 415 "renesas,rz-dmac";
985 reg = <0 0x11820000 0 416 reg = <0 0x11820000 0 0x10000>,
986 <0 0x11830000 0 417 <0 0x11830000 0 0x10000>;
987 interrupts = <GIC_SPI 418 interrupts = <GIC_SPI 141 IRQ_TYPE_EDGE_RISING>,
988 <GIC_SPI 419 <GIC_SPI 125 IRQ_TYPE_EDGE_RISING>,
989 <GIC_SPI 420 <GIC_SPI 126 IRQ_TYPE_EDGE_RISING>,
990 <GIC_SPI 421 <GIC_SPI 127 IRQ_TYPE_EDGE_RISING>,
991 <GIC_SPI 422 <GIC_SPI 128 IRQ_TYPE_EDGE_RISING>,
992 <GIC_SPI 423 <GIC_SPI 129 IRQ_TYPE_EDGE_RISING>,
993 <GIC_SPI 424 <GIC_SPI 130 IRQ_TYPE_EDGE_RISING>,
994 <GIC_SPI 425 <GIC_SPI 131 IRQ_TYPE_EDGE_RISING>,
995 <GIC_SPI 426 <GIC_SPI 132 IRQ_TYPE_EDGE_RISING>,
996 <GIC_SPI 427 <GIC_SPI 133 IRQ_TYPE_EDGE_RISING>,
997 <GIC_SPI 428 <GIC_SPI 134 IRQ_TYPE_EDGE_RISING>,
998 <GIC_SPI 429 <GIC_SPI 135 IRQ_TYPE_EDGE_RISING>,
999 <GIC_SPI 430 <GIC_SPI 136 IRQ_TYPE_EDGE_RISING>,
1000 <GIC_SPI 431 <GIC_SPI 137 IRQ_TYPE_EDGE_RISING>,
1001 <GIC_SPI 432 <GIC_SPI 138 IRQ_TYPE_EDGE_RISING>,
1002 <GIC_SPI 433 <GIC_SPI 139 IRQ_TYPE_EDGE_RISING>,
1003 <GIC_SPI 434 <GIC_SPI 140 IRQ_TYPE_EDGE_RISING>;
1004 interrupt-names = "er 435 interrupt-names = "error",
1005 "ch 436 "ch0", "ch1", "ch2", "ch3",
1006 "ch 437 "ch4", "ch5", "ch6", "ch7",
1007 "ch 438 "ch8", "ch9", "ch10", "ch11",
1008 "ch 439 "ch12", "ch13", "ch14", "ch15";
1009 clocks = <&cpg CPG_MO 440 clocks = <&cpg CPG_MOD R9A07G044_DMAC_ACLK>,
1010 <&cpg CPG_MO 441 <&cpg CPG_MOD R9A07G044_DMAC_PCLK>;
1011 clock-names = "main", <<
1012 power-domains = <&cpg 442 power-domains = <&cpg>;
1013 resets = <&cpg R9A07G 443 resets = <&cpg R9A07G044_DMAC_ARESETN>,
1014 <&cpg R9A07G 444 <&cpg R9A07G044_DMAC_RST_ASYNC>;
1015 reset-names = "arst", <<
1016 #dma-cells = <1>; 445 #dma-cells = <1>;
1017 dma-channels = <16>; 446 dma-channels = <16>;
1018 }; 447 };
1019 448
1020 gpu: gpu@11840000 { <<
1021 compatible = "renesas <<
1022 "arm,mal <<
1023 reg = <0x0 0x11840000 <<
1024 interrupts = <GIC_SPI <<
1025 <GIC_SPI <<
1026 <GIC_SPI <<
1027 <GIC_SPI <<
1028 interrupt-names = "jo <<
1029 clocks = <&cpg CPG_MO <<
1030 <&cpg CPG_MO <<
1031 <&cpg CPG_MO <<
1032 clock-names = "gpu", <<
1033 power-domains = <&cpg <<
1034 resets = <&cpg R9A07G <<
1035 <&cpg R9A07G <<
1036 <&cpg R9A07G <<
1037 reset-names = "rst", <<
1038 operating-points-v2 = <<
1039 }; <<
1040 <<
1041 gic: interrupt-controller@119 449 gic: interrupt-controller@11900000 {
1042 compatible = "arm,gic 450 compatible = "arm,gic-v3";
1043 #interrupt-cells = <3 451 #interrupt-cells = <3>;
1044 #address-cells = <0>; 452 #address-cells = <0>;
1045 interrupt-controller; 453 interrupt-controller;
1046 reg = <0x0 0x11900000 !! 454 reg = <0x0 0x11900000 0 0x40000>,
1047 <0x0 0x11940000 !! 455 <0x0 0x11940000 0 0x60000>;
1048 interrupts = <GIC_PPI 456 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
1049 }; 457 };
1050 458
1051 sdhi0: mmc@11c00000 { !! 459 sdhi0: mmc@11c00000 {
1052 compatible = "renesas 460 compatible = "renesas,sdhi-r9a07g044",
1053 "renesas !! 461 "renesas,rcar-gen3-sdhi";
1054 reg = <0x0 0x11c00000 462 reg = <0x0 0x11c00000 0 0x10000>;
1055 interrupts = <GIC_SPI 463 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
1056 <GIC_SPI 464 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
1057 clocks = <&cpg CPG_MO 465 clocks = <&cpg CPG_MOD R9A07G044_SDHI0_IMCLK>,
1058 <&cpg CPG_MO <<
1059 <&cpg CPG_MO 466 <&cpg CPG_MOD R9A07G044_SDHI0_IMCLK2>,
>> 467 <&cpg CPG_MOD R9A07G044_SDHI0_CLK_HS>,
1060 <&cpg CPG_MO 468 <&cpg CPG_MOD R9A07G044_SDHI0_ACLK>;
1061 clock-names = "core", !! 469 clock-names = "imclk", "imclk2", "clk_hs", "aclk";
1062 resets = <&cpg R9A07G 470 resets = <&cpg R9A07G044_SDHI0_IXRST>;
1063 power-domains = <&cpg 471 power-domains = <&cpg>;
1064 status = "disabled"; 472 status = "disabled";
1065 }; 473 };
1066 474
1067 sdhi1: mmc@11c10000 { 475 sdhi1: mmc@11c10000 {
1068 compatible = "renesas 476 compatible = "renesas,sdhi-r9a07g044",
1069 "renesas !! 477 "renesas,rcar-gen3-sdhi";
1070 reg = <0x0 0x11c10000 478 reg = <0x0 0x11c10000 0 0x10000>;
1071 interrupts = <GIC_SPI 479 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
1072 <GIC_SPI 480 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
1073 clocks = <&cpg CPG_MO 481 clocks = <&cpg CPG_MOD R9A07G044_SDHI1_IMCLK>,
1074 <&cpg CPG_MO <<
1075 <&cpg CPG_MO 482 <&cpg CPG_MOD R9A07G044_SDHI1_IMCLK2>,
>> 483 <&cpg CPG_MOD R9A07G044_SDHI1_CLK_HS>,
1076 <&cpg CPG_MO 484 <&cpg CPG_MOD R9A07G044_SDHI1_ACLK>;
1077 clock-names = "core", !! 485 clock-names = "imclk", "imclk2", "clk_hs", "aclk";
1078 resets = <&cpg R9A07G 486 resets = <&cpg R9A07G044_SDHI1_IXRST>;
1079 power-domains = <&cpg 487 power-domains = <&cpg>;
1080 status = "disabled"; 488 status = "disabled";
1081 }; 489 };
1082 490
1083 eth0: ethernet@11c20000 { 491 eth0: ethernet@11c20000 {
1084 compatible = "renesas 492 compatible = "renesas,r9a07g044-gbeth",
1085 "renesas 493 "renesas,rzg2l-gbeth";
1086 reg = <0 0x11c20000 0 494 reg = <0 0x11c20000 0 0x10000>;
1087 interrupts = <GIC_SPI 495 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
1088 <GIC_SPI 496 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
1089 <GIC_SPI 497 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
1090 interrupt-names = "mu 498 interrupt-names = "mux", "fil", "arp_ns";
1091 phy-mode = "rgmii"; 499 phy-mode = "rgmii";
1092 clocks = <&cpg CPG_MO 500 clocks = <&cpg CPG_MOD R9A07G044_ETH0_CLK_AXI>,
1093 <&cpg CPG_MO 501 <&cpg CPG_MOD R9A07G044_ETH0_CLK_CHI>,
1094 <&cpg CPG_CO 502 <&cpg CPG_CORE R9A07G044_CLK_HP>;
1095 clock-names = "axi", 503 clock-names = "axi", "chi", "refclk";
1096 resets = <&cpg R9A07G 504 resets = <&cpg R9A07G044_ETH0_RST_HW_N>;
1097 power-domains = <&cpg 505 power-domains = <&cpg>;
1098 #address-cells = <1>; 506 #address-cells = <1>;
1099 #size-cells = <0>; 507 #size-cells = <0>;
1100 status = "disabled"; 508 status = "disabled";
1101 }; 509 };
1102 510
1103 eth1: ethernet@11c30000 { 511 eth1: ethernet@11c30000 {
1104 compatible = "renesas 512 compatible = "renesas,r9a07g044-gbeth",
1105 "renesas 513 "renesas,rzg2l-gbeth";
1106 reg = <0 0x11c30000 0 514 reg = <0 0x11c30000 0 0x10000>;
1107 interrupts = <GIC_SPI 515 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
1108 <GIC_SPI 516 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
1109 <GIC_SPI 517 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
1110 interrupt-names = "mu 518 interrupt-names = "mux", "fil", "arp_ns";
1111 phy-mode = "rgmii"; 519 phy-mode = "rgmii";
1112 clocks = <&cpg CPG_MO 520 clocks = <&cpg CPG_MOD R9A07G044_ETH1_CLK_AXI>,
1113 <&cpg CPG_MO 521 <&cpg CPG_MOD R9A07G044_ETH1_CLK_CHI>,
1114 <&cpg CPG_CO 522 <&cpg CPG_CORE R9A07G044_CLK_HP>;
1115 clock-names = "axi", 523 clock-names = "axi", "chi", "refclk";
1116 resets = <&cpg R9A07G 524 resets = <&cpg R9A07G044_ETH1_RST_HW_N>;
1117 power-domains = <&cpg 525 power-domains = <&cpg>;
1118 #address-cells = <1>; 526 #address-cells = <1>;
1119 #size-cells = <0>; 527 #size-cells = <0>;
1120 status = "disabled"; 528 status = "disabled";
1121 }; 529 };
1122 530
1123 phyrst: usbphy-ctrl@11c40000 531 phyrst: usbphy-ctrl@11c40000 {
1124 compatible = "renesas 532 compatible = "renesas,r9a07g044-usbphy-ctrl",
1125 "renesas 533 "renesas,rzg2l-usbphy-ctrl";
1126 reg = <0 0x11c40000 0 534 reg = <0 0x11c40000 0 0x10000>;
1127 clocks = <&cpg CPG_MO 535 clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>;
1128 resets = <&cpg R9A07G 536 resets = <&cpg R9A07G044_USB_PRESETN>;
1129 power-domains = <&cpg 537 power-domains = <&cpg>;
1130 #reset-cells = <1>; 538 #reset-cells = <1>;
1131 status = "disabled"; 539 status = "disabled";
1132 <<
1133 usb0_vbus_otg: regula <<
1134 regulator-nam <<
1135 }; <<
1136 }; 540 };
1137 541
1138 ohci0: usb@11c50000 { 542 ohci0: usb@11c50000 {
1139 compatible = "generic 543 compatible = "generic-ohci";
1140 reg = <0 0x11c50000 0 544 reg = <0 0x11c50000 0 0x100>;
1141 interrupts = <GIC_SPI 545 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
1142 clocks = <&cpg CPG_MO 546 clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>,
1143 <&cpg CPG_MO 547 <&cpg CPG_MOD R9A07G044_USB_U2H0_HCLK>;
1144 resets = <&phyrst 0>, 548 resets = <&phyrst 0>,
1145 <&cpg R9A07G 549 <&cpg R9A07G044_USB_U2H0_HRESETN>;
1146 phys = <&usb2_phy0 1> 550 phys = <&usb2_phy0 1>;
1147 phy-names = "usb"; 551 phy-names = "usb";
1148 power-domains = <&cpg 552 power-domains = <&cpg>;
1149 status = "disabled"; 553 status = "disabled";
1150 }; 554 };
1151 555
1152 ohci1: usb@11c70000 { 556 ohci1: usb@11c70000 {
1153 compatible = "generic 557 compatible = "generic-ohci";
1154 reg = <0 0x11c70000 0 558 reg = <0 0x11c70000 0 0x100>;
1155 interrupts = <GIC_SPI 559 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
1156 clocks = <&cpg CPG_MO 560 clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>,
1157 <&cpg CPG_MO 561 <&cpg CPG_MOD R9A07G044_USB_U2H1_HCLK>;
1158 resets = <&phyrst 1>, 562 resets = <&phyrst 1>,
1159 <&cpg R9A07G 563 <&cpg R9A07G044_USB_U2H1_HRESETN>;
1160 phys = <&usb2_phy1 1> 564 phys = <&usb2_phy1 1>;
1161 phy-names = "usb"; 565 phy-names = "usb";
1162 power-domains = <&cpg 566 power-domains = <&cpg>;
1163 status = "disabled"; 567 status = "disabled";
1164 }; 568 };
1165 569
1166 ehci0: usb@11c50100 { 570 ehci0: usb@11c50100 {
1167 compatible = "generic 571 compatible = "generic-ehci";
1168 reg = <0 0x11c50100 0 572 reg = <0 0x11c50100 0 0x100>;
1169 interrupts = <GIC_SPI 573 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
1170 clocks = <&cpg CPG_MO 574 clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>,
1171 <&cpg CPG_MO 575 <&cpg CPG_MOD R9A07G044_USB_U2H0_HCLK>;
1172 resets = <&phyrst 0>, 576 resets = <&phyrst 0>,
1173 <&cpg R9A07G 577 <&cpg R9A07G044_USB_U2H0_HRESETN>;
1174 phys = <&usb2_phy0 2> 578 phys = <&usb2_phy0 2>;
1175 phy-names = "usb"; 579 phy-names = "usb";
1176 companion = <&ohci0>; 580 companion = <&ohci0>;
1177 power-domains = <&cpg 581 power-domains = <&cpg>;
1178 status = "disabled"; 582 status = "disabled";
1179 }; 583 };
1180 584
1181 ehci1: usb@11c70100 { 585 ehci1: usb@11c70100 {
1182 compatible = "generic 586 compatible = "generic-ehci";
1183 reg = <0 0x11c70100 0 587 reg = <0 0x11c70100 0 0x100>;
1184 interrupts = <GIC_SPI 588 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
1185 clocks = <&cpg CPG_MO 589 clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>,
1186 <&cpg CPG_MO 590 <&cpg CPG_MOD R9A07G044_USB_U2H1_HCLK>;
1187 resets = <&phyrst 1>, 591 resets = <&phyrst 1>,
1188 <&cpg R9A07G 592 <&cpg R9A07G044_USB_U2H1_HRESETN>;
1189 phys = <&usb2_phy1 2> 593 phys = <&usb2_phy1 2>;
1190 phy-names = "usb"; 594 phy-names = "usb";
1191 companion = <&ohci1>; 595 companion = <&ohci1>;
1192 power-domains = <&cpg 596 power-domains = <&cpg>;
1193 status = "disabled"; 597 status = "disabled";
1194 }; 598 };
1195 599
1196 usb2_phy0: usb-phy@11c50200 { 600 usb2_phy0: usb-phy@11c50200 {
1197 compatible = "renesas 601 compatible = "renesas,usb2-phy-r9a07g044",
1198 "renesas 602 "renesas,rzg2l-usb2-phy";
1199 reg = <0 0x11c50200 0 603 reg = <0 0x11c50200 0 0x700>;
1200 interrupts = <GIC_SPI 604 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
1201 clocks = <&cpg CPG_MO 605 clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>,
1202 <&cpg CPG_MO 606 <&cpg CPG_MOD R9A07G044_USB_U2H0_HCLK>;
1203 resets = <&phyrst 0>; 607 resets = <&phyrst 0>;
1204 #phy-cells = <1>; 608 #phy-cells = <1>;
1205 power-domains = <&cpg 609 power-domains = <&cpg>;
1206 status = "disabled"; 610 status = "disabled";
1207 }; 611 };
1208 612
1209 usb2_phy1: usb-phy@11c70200 { 613 usb2_phy1: usb-phy@11c70200 {
1210 compatible = "renesas 614 compatible = "renesas,usb2-phy-r9a07g044",
1211 "renesas 615 "renesas,rzg2l-usb2-phy";
1212 reg = <0 0x11c70200 0 616 reg = <0 0x11c70200 0 0x700>;
1213 interrupts = <GIC_SPI 617 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
1214 clocks = <&cpg CPG_MO 618 clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>,
1215 <&cpg CPG_MO 619 <&cpg CPG_MOD R9A07G044_USB_U2H1_HCLK>;
1216 resets = <&phyrst 1>; 620 resets = <&phyrst 1>;
1217 #phy-cells = <1>; 621 #phy-cells = <1>;
1218 power-domains = <&cpg 622 power-domains = <&cpg>;
1219 status = "disabled"; 623 status = "disabled";
1220 }; 624 };
1221 625
1222 hsusb: usb@11c60000 { 626 hsusb: usb@11c60000 {
1223 compatible = "renesas 627 compatible = "renesas,usbhs-r9a07g044",
1224 "renesas !! 628 "renesas,rza2-usbhs";
1225 reg = <0 0x11c60000 0 629 reg = <0 0x11c60000 0 0x10000>;
1226 interrupts = <GIC_SPI 630 interrupts = <GIC_SPI 100 IRQ_TYPE_EDGE_RISING>,
1227 <GIC_SPI 631 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
1228 <GIC_SPI 632 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
1229 <GIC_SPI 633 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
1230 clocks = <&cpg CPG_MO 634 clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>,
1231 <&cpg CPG_MO 635 <&cpg CPG_MOD R9A07G044_USB_U2P_EXR_CPUCLK>;
1232 resets = <&phyrst 0>, 636 resets = <&phyrst 0>,
1233 <&cpg R9A07G 637 <&cpg R9A07G044_USB_U2P_EXL_SYSRST>;
1234 renesas,buswait = <7> 638 renesas,buswait = <7>;
1235 phys = <&usb2_phy0 3> 639 phys = <&usb2_phy0 3>;
1236 phy-names = "usb"; 640 phy-names = "usb";
1237 power-domains = <&cpg 641 power-domains = <&cpg>;
1238 status = "disabled"; 642 status = "disabled";
1239 }; 643 };
1240 <<
1241 wdt0: watchdog@12800800 { <<
1242 compatible = "renesas <<
1243 "renesas <<
1244 reg = <0 0x12800800 0 <<
1245 clocks = <&cpg CPG_MO <<
1246 <&cpg CPG_MO <<
1247 clock-names = "pclk", <<
1248 interrupts = <GIC_SPI <<
1249 <GIC_SPI <<
1250 interrupt-names = "wd <<
1251 resets = <&cpg R9A07G <<
1252 power-domains = <&cpg <<
1253 status = "disabled"; <<
1254 }; <<
1255 <<
1256 wdt1: watchdog@12800c00 { <<
1257 compatible = "renesas <<
1258 "renesas <<
1259 reg = <0 0x12800C00 0 <<
1260 clocks = <&cpg CPG_MO <<
1261 <&cpg CPG_MO <<
1262 clock-names = "pclk", <<
1263 interrupts = <GIC_SPI <<
1264 <GIC_SPI <<
1265 interrupt-names = "wd <<
1266 resets = <&cpg R9A07G <<
1267 power-domains = <&cpg <<
1268 status = "disabled"; <<
1269 }; <<
1270 <<
1271 ostm0: timer@12801000 { <<
1272 compatible = "renesas <<
1273 "renesas <<
1274 reg = <0x0 0x12801000 <<
1275 interrupts = <GIC_SPI <<
1276 clocks = <&cpg CPG_MO <<
1277 resets = <&cpg R9A07G <<
1278 power-domains = <&cpg <<
1279 status = "disabled"; <<
1280 }; <<
1281 <<
1282 ostm1: timer@12801400 { <<
1283 compatible = "renesas <<
1284 "renesas <<
1285 reg = <0x0 0x12801400 <<
1286 interrupts = <GIC_SPI <<
1287 clocks = <&cpg CPG_MO <<
1288 resets = <&cpg R9A07G <<
1289 power-domains = <&cpg <<
1290 status = "disabled"; <<
1291 }; <<
1292 <<
1293 ostm2: timer@12801800 { <<
1294 compatible = "renesas <<
1295 "renesas <<
1296 reg = <0x0 0x12801800 <<
1297 interrupts = <GIC_SPI <<
1298 clocks = <&cpg CPG_MO <<
1299 resets = <&cpg R9A07G <<
1300 power-domains = <&cpg <<
1301 status = "disabled"; <<
1302 }; <<
1303 }; <<
1304 <<
1305 thermal-zones { <<
1306 cpu-thermal { <<
1307 polling-delay-passive <<
1308 polling-delay = <1000 <<
1309 thermal-sensors = <&t <<
1310 sustainable-power = < <<
1311 <<
1312 cooling-maps { <<
1313 map0 { <<
1314 trip <<
1315 cooli <<
1316 contr <<
1317 }; <<
1318 }; <<
1319 <<
1320 trips { <<
1321 sensor_crit: <<
1322 tempe <<
1323 hyste <<
1324 type <<
1325 }; <<
1326 <<
1327 target: trip- <<
1328 tempe <<
1329 hyste <<
1330 type <<
1331 }; <<
1332 }; <<
1333 }; <<
1334 }; 644 };
1335 645
1336 timer { 646 timer {
1337 compatible = "arm,armv8-timer 647 compatible = "arm,armv8-timer";
1338 interrupts-extended = <&gic G !! 648 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
1339 <&gic G !! 649 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
1340 <&gic G !! 650 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
1341 <&gic G !! 651 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
1342 <&gic G <<
1343 interrupt-names = "sec-phys", <<
1344 "hyp-virt"; <<
1345 }; 652 };
1346 }; 653 };
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