1 // SPDX-License-Identifier: (GPL-2.0-only OR B 1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 /* 2 /*
3 * Device Tree Source for the RZ/G2L and RZ/G2 3 * Device Tree Source for the RZ/G2L and RZ/G2LC common SoC parts
4 * 4 *
5 * Copyright (C) 2021 Renesas Electronics Corp 5 * Copyright (C) 2021 Renesas Electronics Corp.
6 */ 6 */
7 7
8 #include <dt-bindings/interrupt-controller/arm 8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/clock/r9a07g044-cpg.h> 9 #include <dt-bindings/clock/r9a07g044-cpg.h>
10 10
11 / { 11 / {
12 compatible = "renesas,r9a07g044"; 12 compatible = "renesas,r9a07g044";
13 #address-cells = <2>; 13 #address-cells = <2>;
14 #size-cells = <2>; 14 #size-cells = <2>;
15 15
16 audio_clk1: audio1-clk { 16 audio_clk1: audio1-clk {
17 compatible = "fixed-clock"; 17 compatible = "fixed-clock";
18 #clock-cells = <0>; 18 #clock-cells = <0>;
19 /* This value must be overridd 19 /* This value must be overridden by boards that provide it */
20 clock-frequency = <0>; 20 clock-frequency = <0>;
21 }; 21 };
22 22
23 audio_clk2: audio2-clk { 23 audio_clk2: audio2-clk {
24 compatible = "fixed-clock"; 24 compatible = "fixed-clock";
25 #clock-cells = <0>; 25 #clock-cells = <0>;
26 /* This value must be overridd 26 /* This value must be overridden by boards that provide it */
27 clock-frequency = <0>; 27 clock-frequency = <0>;
28 }; 28 };
29 29
30 /* External CAN clock - to be overridd 30 /* External CAN clock - to be overridden by boards that provide it */
31 can_clk: can-clk { 31 can_clk: can-clk {
32 compatible = "fixed-clock"; 32 compatible = "fixed-clock";
33 #clock-cells = <0>; 33 #clock-cells = <0>;
34 clock-frequency = <0>; 34 clock-frequency = <0>;
35 }; 35 };
36 36
37 /* clock can be either from exclk or c 37 /* clock can be either from exclk or crystal oscillator (XIN/XOUT) */
38 extal_clk: extal-clk { 38 extal_clk: extal-clk {
39 compatible = "fixed-clock"; 39 compatible = "fixed-clock";
40 #clock-cells = <0>; 40 #clock-cells = <0>;
41 /* This value must be overridd 41 /* This value must be overridden by the board */
42 clock-frequency = <0>; 42 clock-frequency = <0>;
43 }; 43 };
44 44
45 cluster0_opp: opp-table-0 { 45 cluster0_opp: opp-table-0 {
46 compatible = "operating-points 46 compatible = "operating-points-v2";
47 opp-shared; 47 opp-shared;
48 48
49 opp-150000000 { 49 opp-150000000 {
50 opp-hz = /bits/ 64 <15 50 opp-hz = /bits/ 64 <150000000>;
51 opp-microvolt = <11000 51 opp-microvolt = <1100000>;
52 clock-latency-ns = <30 52 clock-latency-ns = <300000>;
53 }; 53 };
54 opp-300000000 { 54 opp-300000000 {
55 opp-hz = /bits/ 64 <30 55 opp-hz = /bits/ 64 <300000000>;
56 opp-microvolt = <11000 56 opp-microvolt = <1100000>;
57 clock-latency-ns = <30 57 clock-latency-ns = <300000>;
58 }; 58 };
59 opp-600000000 { 59 opp-600000000 {
60 opp-hz = /bits/ 64 <60 60 opp-hz = /bits/ 64 <600000000>;
61 opp-microvolt = <11000 61 opp-microvolt = <1100000>;
62 clock-latency-ns = <30 62 clock-latency-ns = <300000>;
63 }; 63 };
64 opp-1200000000 { 64 opp-1200000000 {
65 opp-hz = /bits/ 64 <12 65 opp-hz = /bits/ 64 <1200000000>;
66 opp-microvolt = <11000 66 opp-microvolt = <1100000>;
67 clock-latency-ns = <30 67 clock-latency-ns = <300000>;
68 opp-suspend; 68 opp-suspend;
69 }; 69 };
70 }; 70 };
71 71
72 cpus { 72 cpus {
73 #address-cells = <1>; 73 #address-cells = <1>;
74 #size-cells = <0>; 74 #size-cells = <0>;
75 75
76 cpu-map { 76 cpu-map {
77 cluster0 { 77 cluster0 {
78 core0 { 78 core0 {
79 cpu = 79 cpu = <&cpu0>;
80 }; 80 };
81 core1 { 81 core1 {
82 cpu = 82 cpu = <&cpu1>;
83 }; 83 };
84 }; 84 };
85 }; 85 };
86 86
87 cpu0: cpu@0 { 87 cpu0: cpu@0 {
88 compatible = "arm,cort 88 compatible = "arm,cortex-a55";
89 reg = <0>; 89 reg = <0>;
90 device_type = "cpu"; 90 device_type = "cpu";
91 #cooling-cells = <2>; 91 #cooling-cells = <2>;
92 next-level-cache = <&L 92 next-level-cache = <&L3_CA55>;
93 enable-method = "psci" 93 enable-method = "psci";
94 clocks = <&cpg CPG_COR 94 clocks = <&cpg CPG_CORE R9A07G044_CLK_I>;
95 operating-points-v2 = 95 operating-points-v2 = <&cluster0_opp>;
96 }; 96 };
97 97
98 cpu1: cpu@100 { 98 cpu1: cpu@100 {
99 compatible = "arm,cort 99 compatible = "arm,cortex-a55";
100 reg = <0x100>; 100 reg = <0x100>;
101 device_type = "cpu"; 101 device_type = "cpu";
102 next-level-cache = <&L 102 next-level-cache = <&L3_CA55>;
103 enable-method = "psci" 103 enable-method = "psci";
104 clocks = <&cpg CPG_COR 104 clocks = <&cpg CPG_CORE R9A07G044_CLK_I>;
105 operating-points-v2 = 105 operating-points-v2 = <&cluster0_opp>;
106 }; 106 };
107 107
108 L3_CA55: cache-controller-0 { 108 L3_CA55: cache-controller-0 {
109 compatible = "cache"; 109 compatible = "cache";
110 cache-unified; 110 cache-unified;
111 cache-size = <0x40000> 111 cache-size = <0x40000>;
112 cache-level = <3>; <<
113 }; 112 };
114 }; 113 };
115 114
116 gpu_opp_table: opp-table-1 { 115 gpu_opp_table: opp-table-1 {
117 compatible = "operating-points 116 compatible = "operating-points-v2";
118 117
119 opp-500000000 { 118 opp-500000000 {
120 opp-hz = /bits/ 64 <50 119 opp-hz = /bits/ 64 <500000000>;
121 opp-microvolt = <11000 120 opp-microvolt = <1100000>;
122 }; 121 };
123 122
124 opp-400000000 { 123 opp-400000000 {
125 opp-hz = /bits/ 64 <40 124 opp-hz = /bits/ 64 <400000000>;
126 opp-microvolt = <11000 125 opp-microvolt = <1100000>;
127 }; 126 };
128 127
129 opp-250000000 { 128 opp-250000000 {
130 opp-hz = /bits/ 64 <25 129 opp-hz = /bits/ 64 <250000000>;
131 opp-microvolt = <11000 130 opp-microvolt = <1100000>;
132 }; 131 };
133 132
134 opp-200000000 { 133 opp-200000000 {
135 opp-hz = /bits/ 64 <20 134 opp-hz = /bits/ 64 <200000000>;
136 opp-microvolt = <11000 135 opp-microvolt = <1100000>;
137 }; 136 };
138 137
139 opp-125000000 { 138 opp-125000000 {
140 opp-hz = /bits/ 64 <12 139 opp-hz = /bits/ 64 <125000000>;
141 opp-microvolt = <11000 140 opp-microvolt = <1100000>;
142 }; 141 };
143 142
144 opp-100000000 { 143 opp-100000000 {
145 opp-hz = /bits/ 64 <10 144 opp-hz = /bits/ 64 <100000000>;
146 opp-microvolt = <11000 145 opp-microvolt = <1100000>;
147 }; 146 };
148 147
149 opp-62500000 { 148 opp-62500000 {
150 opp-hz = /bits/ 64 <62 149 opp-hz = /bits/ 64 <62500000>;
151 opp-microvolt = <11000 150 opp-microvolt = <1100000>;
152 }; 151 };
153 152
154 opp-50000000 { 153 opp-50000000 {
155 opp-hz = /bits/ 64 <50 154 opp-hz = /bits/ 64 <50000000>;
156 opp-microvolt = <11000 155 opp-microvolt = <1100000>;
157 }; 156 };
158 }; 157 };
159 158
160 pmu { <<
161 compatible = "arm,cortex-a55-p <<
162 interrupts-extended = <&gic GI <<
163 }; <<
164 <<
165 psci { 159 psci {
166 compatible = "arm,psci-1.0", " 160 compatible = "arm,psci-1.0", "arm,psci-0.2";
167 method = "smc"; 161 method = "smc";
168 }; 162 };
169 163
170 soc: soc { 164 soc: soc {
171 compatible = "simple-bus"; 165 compatible = "simple-bus";
172 interrupt-parent = <&gic>; 166 interrupt-parent = <&gic>;
173 #address-cells = <2>; 167 #address-cells = <2>;
174 #size-cells = <2>; 168 #size-cells = <2>;
175 ranges; 169 ranges;
176 170
177 mtu3: timer@10001200 { <<
178 compatible = "renesas, <<
179 "renesas, <<
180 reg = <0 0x10001200 0 <<
181 interrupts = <GIC_SPI <<
182 <GIC_SPI <<
183 <GIC_SPI <<
184 <GIC_SPI <<
185 <GIC_SPI <<
186 <GIC_SPI <<
187 <GIC_SPI <<
188 <GIC_SPI <<
189 <GIC_SPI <<
190 <GIC_SPI <<
191 <GIC_SPI <<
192 <GIC_SPI <<
193 <GIC_SPI <<
194 <GIC_SPI <<
195 <GIC_SPI <<
196 <GIC_SPI <<
197 <GIC_SPI <<
198 <GIC_SPI <<
199 <GIC_SPI <<
200 <GIC_SPI <<
201 <GIC_SPI <<
202 <GIC_SPI <<
203 <GIC_SPI <<
204 <GIC_SPI <<
205 <GIC_SPI <<
206 <GIC_SPI <<
207 <GIC_SPI <<
208 <GIC_SPI <<
209 <GIC_SPI <<
210 <GIC_SPI <<
211 <GIC_SPI <<
212 <GIC_SPI <<
213 <GIC_SPI <<
214 <GIC_SPI <<
215 <GIC_SPI <<
216 <GIC_SPI <<
217 <GIC_SPI <<
218 <GIC_SPI <<
219 <GIC_SPI <<
220 <GIC_SPI <<
221 <GIC_SPI <<
222 <GIC_SPI <<
223 <GIC_SPI <<
224 <GIC_SPI <<
225 interrupt-names = "tgi <<
226 "tci <<
227 "tgi <<
228 "tgi <<
229 "tgi <<
230 "tci <<
231 "tgi <<
232 "tci <<
233 "tgi <<
234 "tgi <<
235 "tci <<
236 "tgi <<
237 "tci <<
238 "tgi <<
239 "tci <<
240 clocks = <&cpg CPG_MOD <<
241 power-domains = <&cpg> <<
242 resets = <&cpg R9A07G0 <<
243 #pwm-cells = <2>; <<
244 status = "disabled"; <<
245 }; <<
246 <<
247 ssi0: ssi@10049c00 { 171 ssi0: ssi@10049c00 {
248 compatible = "renesas, 172 compatible = "renesas,r9a07g044-ssi",
249 "renesas, 173 "renesas,rz-ssi";
250 reg = <0 0x10049c00 0 174 reg = <0 0x10049c00 0 0x400>;
251 interrupts = <GIC_SPI 175 interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
252 <GIC_SPI 176 <GIC_SPI 327 IRQ_TYPE_EDGE_RISING>,
253 <GIC_SPI !! 177 <GIC_SPI 328 IRQ_TYPE_EDGE_RISING>,
254 interrupt-names = "int !! 178 <GIC_SPI 329 IRQ_TYPE_EDGE_RISING>;
>> 179 interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt";
255 clocks = <&cpg CPG_MOD 180 clocks = <&cpg CPG_MOD R9A07G044_SSI0_PCLK2>,
256 <&cpg CPG_MOD 181 <&cpg CPG_MOD R9A07G044_SSI0_PCLK_SFR>,
257 <&audio_clk1> 182 <&audio_clk1>, <&audio_clk2>;
258 clock-names = "ssi", " 183 clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2";
259 resets = <&cpg R9A07G0 184 resets = <&cpg R9A07G044_SSI0_RST_M2_REG>;
260 dmas = <&dmac 0x2655>, 185 dmas = <&dmac 0x2655>, <&dmac 0x2656>;
261 dma-names = "tx", "rx" 186 dma-names = "tx", "rx";
262 power-domains = <&cpg> 187 power-domains = <&cpg>;
263 #sound-dai-cells = <0> 188 #sound-dai-cells = <0>;
264 status = "disabled"; 189 status = "disabled";
265 }; 190 };
266 191
267 ssi1: ssi@1004a000 { 192 ssi1: ssi@1004a000 {
268 compatible = "renesas, 193 compatible = "renesas,r9a07g044-ssi",
269 "renesas, 194 "renesas,rz-ssi";
270 reg = <0 0x1004a000 0 195 reg = <0 0x1004a000 0 0x400>;
271 interrupts = <GIC_SPI 196 interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
272 <GIC_SPI 197 <GIC_SPI 331 IRQ_TYPE_EDGE_RISING>,
273 <GIC_SPI !! 198 <GIC_SPI 332 IRQ_TYPE_EDGE_RISING>,
274 interrupt-names = "int !! 199 <GIC_SPI 333 IRQ_TYPE_EDGE_RISING>;
>> 200 interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt";
275 clocks = <&cpg CPG_MOD 201 clocks = <&cpg CPG_MOD R9A07G044_SSI1_PCLK2>,
276 <&cpg CPG_MOD 202 <&cpg CPG_MOD R9A07G044_SSI1_PCLK_SFR>,
277 <&audio_clk1> 203 <&audio_clk1>, <&audio_clk2>;
278 clock-names = "ssi", " 204 clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2";
279 resets = <&cpg R9A07G0 205 resets = <&cpg R9A07G044_SSI1_RST_M2_REG>;
280 dmas = <&dmac 0x2659>, 206 dmas = <&dmac 0x2659>, <&dmac 0x265a>;
281 dma-names = "tx", "rx" 207 dma-names = "tx", "rx";
282 power-domains = <&cpg> 208 power-domains = <&cpg>;
283 #sound-dai-cells = <0> 209 #sound-dai-cells = <0>;
284 status = "disabled"; 210 status = "disabled";
285 }; 211 };
286 212
287 ssi2: ssi@1004a400 { 213 ssi2: ssi@1004a400 {
288 compatible = "renesas, 214 compatible = "renesas,r9a07g044-ssi",
289 "renesas, 215 "renesas,rz-ssi";
290 reg = <0 0x1004a400 0 216 reg = <0 0x1004a400 0 0x400>;
291 interrupts = <GIC_SPI 217 interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
>> 218 <GIC_SPI 335 IRQ_TYPE_EDGE_RISING>,
>> 219 <GIC_SPI 336 IRQ_TYPE_EDGE_RISING>,
292 <GIC_SPI 220 <GIC_SPI 337 IRQ_TYPE_EDGE_RISING>;
293 interrupt-names = "int !! 221 interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt";
294 clocks = <&cpg CPG_MOD 222 clocks = <&cpg CPG_MOD R9A07G044_SSI2_PCLK2>,
295 <&cpg CPG_MOD 223 <&cpg CPG_MOD R9A07G044_SSI2_PCLK_SFR>,
296 <&audio_clk1> 224 <&audio_clk1>, <&audio_clk2>;
297 clock-names = "ssi", " 225 clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2";
298 resets = <&cpg R9A07G0 226 resets = <&cpg R9A07G044_SSI2_RST_M2_REG>;
299 dmas = <&dmac 0x265f>; 227 dmas = <&dmac 0x265f>;
300 dma-names = "rt"; 228 dma-names = "rt";
301 power-domains = <&cpg> 229 power-domains = <&cpg>;
302 #sound-dai-cells = <0> 230 #sound-dai-cells = <0>;
303 status = "disabled"; 231 status = "disabled";
304 }; 232 };
305 233
306 ssi3: ssi@1004a800 { 234 ssi3: ssi@1004a800 {
307 compatible = "renesas, 235 compatible = "renesas,r9a07g044-ssi",
308 "renesas, 236 "renesas,rz-ssi";
309 reg = <0 0x1004a800 0 237 reg = <0 0x1004a800 0 0x400>;
310 interrupts = <GIC_SPI 238 interrupts = <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
311 <GIC_SPI 239 <GIC_SPI 339 IRQ_TYPE_EDGE_RISING>,
312 <GIC_SPI !! 240 <GIC_SPI 340 IRQ_TYPE_EDGE_RISING>,
313 interrupt-names = "int !! 241 <GIC_SPI 341 IRQ_TYPE_EDGE_RISING>;
>> 242 interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt";
314 clocks = <&cpg CPG_MOD 243 clocks = <&cpg CPG_MOD R9A07G044_SSI3_PCLK2>,
315 <&cpg CPG_MOD 244 <&cpg CPG_MOD R9A07G044_SSI3_PCLK_SFR>,
316 <&audio_clk1> 245 <&audio_clk1>, <&audio_clk2>;
317 clock-names = "ssi", " 246 clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2";
318 resets = <&cpg R9A07G0 247 resets = <&cpg R9A07G044_SSI3_RST_M2_REG>;
319 dmas = <&dmac 0x2661>, 248 dmas = <&dmac 0x2661>, <&dmac 0x2662>;
320 dma-names = "tx", "rx" 249 dma-names = "tx", "rx";
321 power-domains = <&cpg> 250 power-domains = <&cpg>;
322 #sound-dai-cells = <0> 251 #sound-dai-cells = <0>;
323 status = "disabled"; 252 status = "disabled";
324 }; 253 };
325 254
326 spi0: spi@1004ac00 { 255 spi0: spi@1004ac00 {
327 compatible = "renesas, 256 compatible = "renesas,r9a07g044-rspi", "renesas,rspi-rz";
328 reg = <0 0x1004ac00 0 257 reg = <0 0x1004ac00 0 0x400>;
329 interrupts = <GIC_SPI 258 interrupts = <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>,
330 <GIC_SPI 259 <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>,
331 <GIC_SPI 260 <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>;
332 interrupt-names = "err 261 interrupt-names = "error", "rx", "tx";
333 clocks = <&cpg CPG_MOD 262 clocks = <&cpg CPG_MOD R9A07G044_RSPI0_CLKB>;
334 resets = <&cpg R9A07G0 263 resets = <&cpg R9A07G044_RSPI0_RST>;
335 dmas = <&dmac 0x2e95>, <<
336 dma-names = "tx", "rx" <<
337 power-domains = <&cpg> 264 power-domains = <&cpg>;
338 num-cs = <1>; 265 num-cs = <1>;
339 #address-cells = <1>; 266 #address-cells = <1>;
340 #size-cells = <0>; 267 #size-cells = <0>;
341 status = "disabled"; 268 status = "disabled";
342 }; 269 };
343 270
344 spi1: spi@1004b000 { 271 spi1: spi@1004b000 {
345 compatible = "renesas, 272 compatible = "renesas,r9a07g044-rspi", "renesas,rspi-rz";
346 reg = <0 0x1004b000 0 273 reg = <0 0x1004b000 0 0x400>;
347 interrupts = <GIC_SPI 274 interrupts = <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
348 <GIC_SPI 275 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
349 <GIC_SPI 276 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>;
350 interrupt-names = "err 277 interrupt-names = "error", "rx", "tx";
351 clocks = <&cpg CPG_MOD 278 clocks = <&cpg CPG_MOD R9A07G044_RSPI1_CLKB>;
352 resets = <&cpg R9A07G0 279 resets = <&cpg R9A07G044_RSPI1_RST>;
353 dmas = <&dmac 0x2e99>, <<
354 dma-names = "tx", "rx" <<
355 power-domains = <&cpg> 280 power-domains = <&cpg>;
356 num-cs = <1>; 281 num-cs = <1>;
357 #address-cells = <1>; 282 #address-cells = <1>;
358 #size-cells = <0>; 283 #size-cells = <0>;
359 status = "disabled"; 284 status = "disabled";
360 }; 285 };
361 286
362 spi2: spi@1004b400 { 287 spi2: spi@1004b400 {
363 compatible = "renesas, 288 compatible = "renesas,r9a07g044-rspi", "renesas,rspi-rz";
364 reg = <0 0x1004b400 0 289 reg = <0 0x1004b400 0 0x400>;
365 interrupts = <GIC_SPI 290 interrupts = <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
366 <GIC_SPI 291 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
367 <GIC_SPI 292 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>;
368 interrupt-names = "err 293 interrupt-names = "error", "rx", "tx";
369 clocks = <&cpg CPG_MOD 294 clocks = <&cpg CPG_MOD R9A07G044_RSPI2_CLKB>;
370 resets = <&cpg R9A07G0 295 resets = <&cpg R9A07G044_RSPI2_RST>;
371 dmas = <&dmac 0x2e9d>, <<
372 dma-names = "tx", "rx" <<
373 power-domains = <&cpg> 296 power-domains = <&cpg>;
374 num-cs = <1>; 297 num-cs = <1>;
375 #address-cells = <1>; 298 #address-cells = <1>;
376 #size-cells = <0>; 299 #size-cells = <0>;
377 status = "disabled"; 300 status = "disabled";
378 }; 301 };
379 302
380 scif0: serial@1004b800 { 303 scif0: serial@1004b800 {
381 compatible = "renesas, 304 compatible = "renesas,scif-r9a07g044";
382 reg = <0 0x1004b800 0 305 reg = <0 0x1004b800 0 0x400>;
383 interrupts = <GIC_SPI 306 interrupts = <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>,
384 <GIC_SPI 307 <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>,
385 <GIC_SPI 308 <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>,
386 <GIC_SPI 309 <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>,
387 <GIC_SPI 310 <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>,
388 <GIC_SPI 311 <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>;
389 interrupt-names = "eri 312 interrupt-names = "eri", "rxi", "txi",
390 "bri 313 "bri", "dri", "tei";
391 clocks = <&cpg CPG_MOD 314 clocks = <&cpg CPG_MOD R9A07G044_SCIF0_CLK_PCK>;
392 clock-names = "fck"; 315 clock-names = "fck";
393 power-domains = <&cpg> 316 power-domains = <&cpg>;
394 resets = <&cpg R9A07G0 317 resets = <&cpg R9A07G044_SCIF0_RST_SYSTEM_N>;
395 status = "disabled"; 318 status = "disabled";
396 }; 319 };
397 320
398 scif1: serial@1004bc00 { 321 scif1: serial@1004bc00 {
399 compatible = "renesas, 322 compatible = "renesas,scif-r9a07g044";
400 reg = <0 0x1004bc00 0 323 reg = <0 0x1004bc00 0 0x400>;
401 interrupts = <GIC_SPI 324 interrupts = <GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>,
402 <GIC_SPI 325 <GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>,
403 <GIC_SPI 326 <GIC_SPI 388 IRQ_TYPE_LEVEL_HIGH>,
404 <GIC_SPI 327 <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>,
405 <GIC_SPI 328 <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>,
406 <GIC_SPI 329 <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>;
407 interrupt-names = "eri 330 interrupt-names = "eri", "rxi", "txi",
408 "bri 331 "bri", "dri", "tei";
409 clocks = <&cpg CPG_MOD 332 clocks = <&cpg CPG_MOD R9A07G044_SCIF1_CLK_PCK>;
410 clock-names = "fck"; 333 clock-names = "fck";
411 power-domains = <&cpg> 334 power-domains = <&cpg>;
412 resets = <&cpg R9A07G0 335 resets = <&cpg R9A07G044_SCIF1_RST_SYSTEM_N>;
413 status = "disabled"; 336 status = "disabled";
414 }; 337 };
415 338
416 scif2: serial@1004c000 { 339 scif2: serial@1004c000 {
417 compatible = "renesas, 340 compatible = "renesas,scif-r9a07g044";
418 reg = <0 0x1004c000 0 341 reg = <0 0x1004c000 0 0x400>;
419 interrupts = <GIC_SPI 342 interrupts = <GIC_SPI 390 IRQ_TYPE_LEVEL_HIGH>,
420 <GIC_SPI 343 <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH>,
421 <GIC_SPI 344 <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>,
422 <GIC_SPI 345 <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH>,
423 <GIC_SPI 346 <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>,
424 <GIC_SPI 347 <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>;
425 interrupt-names = "eri 348 interrupt-names = "eri", "rxi", "txi",
426 "bri 349 "bri", "dri", "tei";
427 clocks = <&cpg CPG_MOD 350 clocks = <&cpg CPG_MOD R9A07G044_SCIF2_CLK_PCK>;
428 clock-names = "fck"; 351 clock-names = "fck";
429 power-domains = <&cpg> 352 power-domains = <&cpg>;
430 resets = <&cpg R9A07G0 353 resets = <&cpg R9A07G044_SCIF2_RST_SYSTEM_N>;
431 status = "disabled"; 354 status = "disabled";
432 }; 355 };
433 356
434 scif3: serial@1004c400 { 357 scif3: serial@1004c400 {
435 compatible = "renesas, 358 compatible = "renesas,scif-r9a07g044";
436 reg = <0 0x1004c400 0 359 reg = <0 0x1004c400 0 0x400>;
437 interrupts = <GIC_SPI 360 interrupts = <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
438 <GIC_SPI 361 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
439 <GIC_SPI 362 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
440 <GIC_SPI 363 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
441 <GIC_SPI 364 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
442 <GIC_SPI 365 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>;
443 interrupt-names = "eri 366 interrupt-names = "eri", "rxi", "txi",
444 "bri 367 "bri", "dri", "tei";
445 clocks = <&cpg CPG_MOD 368 clocks = <&cpg CPG_MOD R9A07G044_SCIF3_CLK_PCK>;
446 clock-names = "fck"; 369 clock-names = "fck";
447 power-domains = <&cpg> 370 power-domains = <&cpg>;
448 resets = <&cpg R9A07G0 371 resets = <&cpg R9A07G044_SCIF3_RST_SYSTEM_N>;
449 status = "disabled"; 372 status = "disabled";
450 }; 373 };
451 374
452 scif4: serial@1004c800 { 375 scif4: serial@1004c800 {
453 compatible = "renesas, 376 compatible = "renesas,scif-r9a07g044";
454 reg = <0 0x1004c800 0 377 reg = <0 0x1004c800 0 0x400>;
455 interrupts = <GIC_SPI 378 interrupts = <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
456 <GIC_SPI 379 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
457 <GIC_SPI 380 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
458 <GIC_SPI 381 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
459 <GIC_SPI 382 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
460 <GIC_SPI 383 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>;
461 interrupt-names = "eri 384 interrupt-names = "eri", "rxi", "txi",
462 "bri 385 "bri", "dri", "tei";
463 clocks = <&cpg CPG_MOD 386 clocks = <&cpg CPG_MOD R9A07G044_SCIF4_CLK_PCK>;
464 clock-names = "fck"; 387 clock-names = "fck";
465 power-domains = <&cpg> 388 power-domains = <&cpg>;
466 resets = <&cpg R9A07G0 389 resets = <&cpg R9A07G044_SCIF4_RST_SYSTEM_N>;
467 status = "disabled"; 390 status = "disabled";
468 }; 391 };
469 392
470 sci0: serial@1004d000 { 393 sci0: serial@1004d000 {
471 compatible = "renesas, 394 compatible = "renesas,r9a07g044-sci", "renesas,sci";
472 reg = <0 0x1004d000 0 395 reg = <0 0x1004d000 0 0x400>;
473 interrupts = <GIC_SPI 396 interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
474 <GIC_SPI 397 <GIC_SPI 406 IRQ_TYPE_EDGE_RISING>,
475 <GIC_SPI 398 <GIC_SPI 407 IRQ_TYPE_EDGE_RISING>,
476 <GIC_SPI 399 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>;
477 interrupt-names = "eri 400 interrupt-names = "eri", "rxi", "txi", "tei";
478 clocks = <&cpg CPG_MOD 401 clocks = <&cpg CPG_MOD R9A07G044_SCI0_CLKP>;
479 clock-names = "fck"; 402 clock-names = "fck";
480 power-domains = <&cpg> 403 power-domains = <&cpg>;
481 resets = <&cpg R9A07G0 404 resets = <&cpg R9A07G044_SCI0_RST>;
482 status = "disabled"; 405 status = "disabled";
483 }; 406 };
484 407
485 sci1: serial@1004d400 { 408 sci1: serial@1004d400 {
486 compatible = "renesas, 409 compatible = "renesas,r9a07g044-sci", "renesas,sci";
487 reg = <0 0x1004d400 0 410 reg = <0 0x1004d400 0 0x400>;
488 interrupts = <GIC_SPI 411 interrupts = <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
489 <GIC_SPI 412 <GIC_SPI 410 IRQ_TYPE_EDGE_RISING>,
490 <GIC_SPI 413 <GIC_SPI 411 IRQ_TYPE_EDGE_RISING>,
491 <GIC_SPI 414 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>;
492 interrupt-names = "eri 415 interrupt-names = "eri", "rxi", "txi", "tei";
493 clocks = <&cpg CPG_MOD 416 clocks = <&cpg CPG_MOD R9A07G044_SCI1_CLKP>;
494 clock-names = "fck"; 417 clock-names = "fck";
495 power-domains = <&cpg> 418 power-domains = <&cpg>;
496 resets = <&cpg R9A07G0 419 resets = <&cpg R9A07G044_SCI1_RST>;
497 status = "disabled"; 420 status = "disabled";
498 }; 421 };
499 422
500 canfd: can@10050000 { 423 canfd: can@10050000 {
501 compatible = "renesas, 424 compatible = "renesas,r9a07g044-canfd", "renesas,rzg2l-canfd";
502 reg = <0 0x10050000 0 425 reg = <0 0x10050000 0 0x8000>;
503 interrupts = <GIC_SPI 426 interrupts = <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>,
504 <GIC_SPI 427 <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>,
505 <GIC_SPI 428 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
506 <GIC_SPI 429 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
507 <GIC_SPI 430 <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>,
508 <GIC_SPI 431 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
509 <GIC_SPI 432 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
510 <GIC_SPI 433 <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>;
511 interrupt-names = "g_e 434 interrupt-names = "g_err", "g_recc",
512 "ch0 435 "ch0_err", "ch0_rec", "ch0_trx",
513 "ch1 436 "ch1_err", "ch1_rec", "ch1_trx";
514 clocks = <&cpg CPG_MOD 437 clocks = <&cpg CPG_MOD R9A07G044_CANFD_PCLK>,
515 <&cpg CPG_COR 438 <&cpg CPG_CORE R9A07G044_CLK_P0_DIV2>,
516 <&can_clk>; 439 <&can_clk>;
517 clock-names = "fck", " 440 clock-names = "fck", "canfd", "can_clk";
518 assigned-clocks = <&cp 441 assigned-clocks = <&cpg CPG_CORE R9A07G044_CLK_P0_DIV2>;
519 assigned-clock-rates = 442 assigned-clock-rates = <50000000>;
520 resets = <&cpg R9A07G0 443 resets = <&cpg R9A07G044_CANFD_RSTP_N>,
521 <&cpg R9A07G0 444 <&cpg R9A07G044_CANFD_RSTC_N>;
522 reset-names = "rstp_n" 445 reset-names = "rstp_n", "rstc_n";
523 power-domains = <&cpg> 446 power-domains = <&cpg>;
524 status = "disabled"; 447 status = "disabled";
525 448
526 channel0 { 449 channel0 {
527 status = "disa 450 status = "disabled";
528 }; 451 };
529 channel1 { 452 channel1 {
530 status = "disa 453 status = "disabled";
531 }; 454 };
532 }; 455 };
533 456
534 i2c0: i2c@10058000 { 457 i2c0: i2c@10058000 {
535 #address-cells = <1>; 458 #address-cells = <1>;
536 #size-cells = <0>; 459 #size-cells = <0>;
537 compatible = "renesas, 460 compatible = "renesas,riic-r9a07g044", "renesas,riic-rz";
538 reg = <0 0x10058000 0 461 reg = <0 0x10058000 0 0x400>;
539 interrupts = <GIC_SPI 462 interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>,
540 <GIC_SPI 463 <GIC_SPI 348 IRQ_TYPE_EDGE_RISING>,
541 <GIC_SPI 464 <GIC_SPI 349 IRQ_TYPE_EDGE_RISING>,
542 <GIC_SPI 465 <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>,
543 <GIC_SPI 466 <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>,
544 <GIC_SPI 467 <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>,
545 <GIC_SPI 468 <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>,
546 <GIC_SPI 469 <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
547 interrupt-names = "tei 470 interrupt-names = "tei", "ri", "ti", "spi", "sti",
548 "nak 471 "naki", "ali", "tmoi";
549 clocks = <&cpg CPG_MOD 472 clocks = <&cpg CPG_MOD R9A07G044_I2C0_PCLK>;
550 clock-frequency = <100 473 clock-frequency = <100000>;
551 resets = <&cpg R9A07G0 474 resets = <&cpg R9A07G044_I2C0_MRST>;
552 power-domains = <&cpg> 475 power-domains = <&cpg>;
553 status = "disabled"; 476 status = "disabled";
554 }; 477 };
555 478
556 i2c1: i2c@10058400 { 479 i2c1: i2c@10058400 {
557 #address-cells = <1>; 480 #address-cells = <1>;
558 #size-cells = <0>; 481 #size-cells = <0>;
559 compatible = "renesas, 482 compatible = "renesas,riic-r9a07g044", "renesas,riic-rz";
560 reg = <0 0x10058400 0 483 reg = <0 0x10058400 0 0x400>;
561 interrupts = <GIC_SPI 484 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>,
562 <GIC_SPI 485 <GIC_SPI 356 IRQ_TYPE_EDGE_RISING>,
563 <GIC_SPI 486 <GIC_SPI 357 IRQ_TYPE_EDGE_RISING>,
564 <GIC_SPI 487 <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>,
565 <GIC_SPI 488 <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>,
566 <GIC_SPI 489 <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>,
567 <GIC_SPI 490 <GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH>,
568 <GIC_SPI 491 <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>;
569 interrupt-names = "tei 492 interrupt-names = "tei", "ri", "ti", "spi", "sti",
570 "nak 493 "naki", "ali", "tmoi";
571 clocks = <&cpg CPG_MOD 494 clocks = <&cpg CPG_MOD R9A07G044_I2C1_PCLK>;
572 clock-frequency = <100 495 clock-frequency = <100000>;
573 resets = <&cpg R9A07G0 496 resets = <&cpg R9A07G044_I2C1_MRST>;
574 power-domains = <&cpg> 497 power-domains = <&cpg>;
575 status = "disabled"; 498 status = "disabled";
576 }; 499 };
577 500
578 i2c2: i2c@10058800 { 501 i2c2: i2c@10058800 {
579 #address-cells = <1>; 502 #address-cells = <1>;
580 #size-cells = <0>; 503 #size-cells = <0>;
581 compatible = "renesas, 504 compatible = "renesas,riic-r9a07g044", "renesas,riic-rz";
582 reg = <0 0x10058800 0 505 reg = <0 0x10058800 0 0x400>;
583 interrupts = <GIC_SPI 506 interrupts = <GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>,
584 <GIC_SPI 507 <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>,
585 <GIC_SPI 508 <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>,
586 <GIC_SPI 509 <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>,
587 <GIC_SPI 510 <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>,
588 <GIC_SPI 511 <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>,
589 <GIC_SPI 512 <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>,
590 <GIC_SPI 513 <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
591 interrupt-names = "tei 514 interrupt-names = "tei", "ri", "ti", "spi", "sti",
592 "nak 515 "naki", "ali", "tmoi";
593 clocks = <&cpg CPG_MOD 516 clocks = <&cpg CPG_MOD R9A07G044_I2C2_PCLK>;
594 clock-frequency = <100 517 clock-frequency = <100000>;
595 resets = <&cpg R9A07G0 518 resets = <&cpg R9A07G044_I2C2_MRST>;
596 power-domains = <&cpg> 519 power-domains = <&cpg>;
597 status = "disabled"; 520 status = "disabled";
598 }; 521 };
599 522
600 i2c3: i2c@10058c00 { 523 i2c3: i2c@10058c00 {
601 #address-cells = <1>; 524 #address-cells = <1>;
602 #size-cells = <0>; 525 #size-cells = <0>;
603 compatible = "renesas, 526 compatible = "renesas,riic-r9a07g044", "renesas,riic-rz";
604 reg = <0 0x10058c00 0 527 reg = <0 0x10058c00 0 0x400>;
605 interrupts = <GIC_SPI 528 interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>,
606 <GIC_SPI 529 <GIC_SPI 372 IRQ_TYPE_EDGE_RISING>,
607 <GIC_SPI 530 <GIC_SPI 373 IRQ_TYPE_EDGE_RISING>,
608 <GIC_SPI 531 <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>,
609 <GIC_SPI 532 <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>,
610 <GIC_SPI 533 <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>,
611 <GIC_SPI 534 <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>,
612 <GIC_SPI 535 <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
613 interrupt-names = "tei 536 interrupt-names = "tei", "ri", "ti", "spi", "sti",
614 "nak 537 "naki", "ali", "tmoi";
615 clocks = <&cpg CPG_MOD 538 clocks = <&cpg CPG_MOD R9A07G044_I2C3_PCLK>;
616 clock-frequency = <100 539 clock-frequency = <100000>;
617 resets = <&cpg R9A07G0 540 resets = <&cpg R9A07G044_I2C3_MRST>;
618 power-domains = <&cpg> 541 power-domains = <&cpg>;
619 status = "disabled"; 542 status = "disabled";
620 }; 543 };
621 544
622 adc: adc@10059000 { 545 adc: adc@10059000 {
623 compatible = "renesas, 546 compatible = "renesas,r9a07g044-adc", "renesas,rzg2l-adc";
624 reg = <0 0x10059000 0 547 reg = <0 0x10059000 0 0x400>;
625 interrupts = <GIC_SPI 548 interrupts = <GIC_SPI 347 IRQ_TYPE_EDGE_RISING>;
626 clocks = <&cpg CPG_MOD 549 clocks = <&cpg CPG_MOD R9A07G044_ADC_ADCLK>,
627 <&cpg CPG_MOD 550 <&cpg CPG_MOD R9A07G044_ADC_PCLK>;
628 clock-names = "adclk", 551 clock-names = "adclk", "pclk";
629 resets = <&cpg R9A07G0 552 resets = <&cpg R9A07G044_ADC_PRESETN>,
630 <&cpg R9A07G0 553 <&cpg R9A07G044_ADC_ADRST_N>;
631 reset-names = "presetn 554 reset-names = "presetn", "adrst-n";
632 power-domains = <&cpg> 555 power-domains = <&cpg>;
633 status = "disabled"; 556 status = "disabled";
634 557
635 #address-cells = <1>; 558 #address-cells = <1>;
636 #size-cells = <0>; 559 #size-cells = <0>;
637 560
638 channel@0 { 561 channel@0 {
639 reg = <0>; 562 reg = <0>;
640 }; 563 };
641 channel@1 { 564 channel@1 {
642 reg = <1>; 565 reg = <1>;
643 }; 566 };
644 channel@2 { 567 channel@2 {
645 reg = <2>; 568 reg = <2>;
646 }; 569 };
647 channel@3 { 570 channel@3 {
648 reg = <3>; 571 reg = <3>;
649 }; 572 };
650 channel@4 { 573 channel@4 {
651 reg = <4>; 574 reg = <4>;
652 }; 575 };
653 channel@5 { 576 channel@5 {
654 reg = <5>; 577 reg = <5>;
655 }; 578 };
656 channel@6 { 579 channel@6 {
657 reg = <6>; 580 reg = <6>;
658 }; 581 };
659 channel@7 { 582 channel@7 {
660 reg = <7>; 583 reg = <7>;
661 }; 584 };
662 }; 585 };
663 586
664 tsu: thermal@10059400 { 587 tsu: thermal@10059400 {
665 compatible = "renesas, 588 compatible = "renesas,r9a07g044-tsu",
666 "renesas, 589 "renesas,rzg2l-tsu";
667 reg = <0 0x10059400 0 590 reg = <0 0x10059400 0 0x400>;
668 clocks = <&cpg CPG_MOD 591 clocks = <&cpg CPG_MOD R9A07G044_TSU_PCLK>;
669 resets = <&cpg R9A07G0 592 resets = <&cpg R9A07G044_TSU_PRESETN>;
670 power-domains = <&cpg> 593 power-domains = <&cpg>;
671 #thermal-sensor-cells 594 #thermal-sensor-cells = <1>;
672 }; 595 };
673 596
674 sbc: spi@10060000 { 597 sbc: spi@10060000 {
675 compatible = "renesas, 598 compatible = "renesas,r9a07g044-rpc-if",
676 "renesas, 599 "renesas,rzg2l-rpc-if";
677 reg = <0 0x10060000 0 600 reg = <0 0x10060000 0 0x10000>,
678 <0 0x20000000 0 601 <0 0x20000000 0 0x10000000>,
679 <0 0x10070000 0 602 <0 0x10070000 0 0x10000>;
680 reg-names = "regs", "d 603 reg-names = "regs", "dirmap", "wbuf";
681 interrupts = <GIC_SPI 604 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
682 clocks = <&cpg CPG_MOD 605 clocks = <&cpg CPG_MOD R9A07G044_SPI_CLK2>,
683 <&cpg CPG_MOD 606 <&cpg CPG_MOD R9A07G044_SPI_CLK>;
684 resets = <&cpg R9A07G0 607 resets = <&cpg R9A07G044_SPI_RST>;
685 power-domains = <&cpg> 608 power-domains = <&cpg>;
686 #address-cells = <1>; 609 #address-cells = <1>;
687 #size-cells = <0>; 610 #size-cells = <0>;
688 status = "disabled"; 611 status = "disabled";
689 }; 612 };
690 613
691 cru: video@10830000 { <<
692 compatible = "renesas, <<
693 reg = <0 0x10830000 0 <<
694 clocks = <&cpg CPG_MOD <<
695 <&cpg CPG_MOD <<
696 <&cpg CPG_MOD <<
697 clock-names = "video", <<
698 interrupts = <GIC_SPI <<
699 <GIC_SPI <<
700 <GIC_SPI <<
701 interrupt-names = "ima <<
702 resets = <&cpg R9A07G0 <<
703 <&cpg R9A07G0 <<
704 reset-names = "presetn <<
705 power-domains = <&cpg> <<
706 status = "disabled"; <<
707 <<
708 ports { <<
709 #address-cells <<
710 #size-cells = <<
711 <<
712 port@0 { <<
713 #addre <<
714 #size- <<
715 <<
716 reg = <<
717 crupar <<
718 <<
719 }; <<
720 }; <<
721 <<
722 port@1 { <<
723 #addre <<
724 #size- <<
725 <<
726 reg = <<
727 crucsi <<
728 <<
729 <<
730 }; <<
731 }; <<
732 }; <<
733 }; <<
734 <<
735 csi2: csi2@10830400 { <<
736 compatible = "renesas, <<
737 reg = <0 0x10830400 0 <<
738 interrupts = <GIC_SPI <<
739 clocks = <&cpg CPG_MOD <<
740 <&cpg CPG_MOD <<
741 <&cpg CPG_MOD <<
742 clock-names = "system" <<
743 resets = <&cpg R9A07G0 <<
744 <&cpg R9A07G0 <<
745 reset-names = "presetn <<
746 power-domains = <&cpg> <<
747 status = "disabled"; <<
748 <<
749 ports { <<
750 #address-cells <<
751 #size-cells = <<
752 <<
753 port@0 { <<
754 reg = <<
755 }; <<
756 <<
757 port@1 { <<
758 #addre <<
759 #size- <<
760 reg = <<
761 <<
762 csi2cr <<
763 <<
764 <<
765 }; <<
766 }; <<
767 }; <<
768 }; <<
769 <<
770 dsi: dsi@10850000 { <<
771 compatible = "renesas, <<
772 "renesas, <<
773 reg = <0 0x10850000 0 <<
774 interrupts = <GIC_SPI <<
775 <GIC_SPI <<
776 <GIC_SPI <<
777 <GIC_SPI <<
778 <GIC_SPI <<
779 <GIC_SPI <<
780 <GIC_SPI <<
781 interrupt-names = "seq <<
782 "fer <<
783 clocks = <&cpg CPG_MOD <<
784 <&cpg CPG_MOD <<
785 <&cpg CPG_MOD <<
786 <&cpg CPG_MOD <<
787 <&cpg CPG_MOD <<
788 <&cpg CPG_MOD <<
789 clock-names = "pllclk" <<
790 resets = <&cpg R9A07G0 <<
791 <&cpg R9A07G0 <<
792 <&cpg R9A07G0 <<
793 reset-names = "rst", " <<
794 power-domains = <&cpg> <<
795 status = "disabled"; <<
796 <<
797 ports { <<
798 #address-cells <<
799 #size-cells = <<
800 <<
801 port@0 { <<
802 reg = <<
803 dsi0_i <<
804 <<
805 }; <<
806 }; <<
807 <<
808 port@1 { <<
809 reg = <<
810 }; <<
811 }; <<
812 }; <<
813 <<
814 vspd: vsp@10870000 { <<
815 compatible = "renesas, <<
816 reg = <0 0x10870000 0 <<
817 interrupts = <GIC_SPI <<
818 clocks = <&cpg CPG_MOD <<
819 <&cpg CPG_MOD <<
820 <&cpg CPG_MOD <<
821 clock-names = "aclk", <<
822 power-domains = <&cpg> <<
823 resets = <&cpg R9A07G0 <<
824 renesas,fcp = <&fcpvd> <<
825 }; <<
826 <<
827 fcpvd: fcp@10880000 { <<
828 compatible = "renesas, <<
829 "renesas, <<
830 reg = <0 0x10880000 0 <<
831 clocks = <&cpg CPG_MOD <<
832 <&cpg CPG_MOD <<
833 <&cpg CPG_MOD <<
834 clock-names = "aclk", <<
835 power-domains = <&cpg> <<
836 resets = <&cpg R9A07G0 <<
837 }; <<
838 <<
839 du: display@10890000 { <<
840 compatible = "renesas, <<
841 reg = <0 0x10890000 0 <<
842 interrupts = <GIC_SPI <<
843 clocks = <&cpg CPG_MOD <<
844 <&cpg CPG_MOD <<
845 <&cpg CPG_MOD <<
846 clock-names = "aclk", <<
847 power-domains = <&cpg> <<
848 resets = <&cpg R9A07G0 <<
849 renesas,vsps = <&vspd <<
850 status = "disabled"; <<
851 <<
852 ports { <<
853 #address-cells <<
854 #size-cells = <<
855 <<
856 port@0 { <<
857 reg = <<
858 du_out <<
859 <<
860 }; <<
861 }; <<
862 <<
863 port@1 { <<
864 reg = <<
865 }; <<
866 }; <<
867 }; <<
868 <<
869 cpg: clock-controller@11010000 614 cpg: clock-controller@11010000 {
870 compatible = "renesas, 615 compatible = "renesas,r9a07g044-cpg";
871 reg = <0 0x11010000 0 616 reg = <0 0x11010000 0 0x10000>;
872 clocks = <&extal_clk>; 617 clocks = <&extal_clk>;
873 clock-names = "extal"; 618 clock-names = "extal";
874 #clock-cells = <2>; 619 #clock-cells = <2>;
875 #reset-cells = <1>; 620 #reset-cells = <1>;
876 #power-domain-cells = 621 #power-domain-cells = <0>;
877 }; 622 };
878 623
879 sysc: system-controller@110200 624 sysc: system-controller@11020000 {
880 compatible = "renesas, 625 compatible = "renesas,r9a07g044-sysc";
881 reg = <0 0x11020000 0 626 reg = <0 0x11020000 0 0x10000>;
882 interrupts = <GIC_SPI 627 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
883 <GIC_SPI 628 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
884 <GIC_SPI 629 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
885 <GIC_SPI 630 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
886 interrupt-names = "lpm 631 interrupt-names = "lpm_int", "ca55stbydone_int",
887 "cm3 632 "cm33stbyr_int", "ca55_deny";
888 status = "disabled"; 633 status = "disabled";
889 }; 634 };
890 635
891 pinctrl: pinctrl@11030000 { 636 pinctrl: pinctrl@11030000 {
892 compatible = "renesas, 637 compatible = "renesas,r9a07g044-pinctrl";
893 reg = <0 0x11030000 0 638 reg = <0 0x11030000 0 0x10000>;
894 gpio-controller; 639 gpio-controller;
895 #gpio-cells = <2>; 640 #gpio-cells = <2>;
896 #interrupt-cells = <2> <<
897 interrupt-parent = <&i <<
898 interrupt-controller; <<
899 gpio-ranges = <&pinctr 641 gpio-ranges = <&pinctrl 0 0 392>;
900 clocks = <&cpg CPG_MOD 642 clocks = <&cpg CPG_MOD R9A07G044_GPIO_HCLK>;
901 power-domains = <&cpg> 643 power-domains = <&cpg>;
902 resets = <&cpg R9A07G0 644 resets = <&cpg R9A07G044_GPIO_RSTN>,
903 <&cpg R9A07G0 645 <&cpg R9A07G044_GPIO_PORT_RESETN>,
904 <&cpg R9A07G0 646 <&cpg R9A07G044_GPIO_SPARE_RESETN>;
905 }; 647 };
906 648
907 irqc: interrupt-controller@110 <<
908 compatible = "renesas, <<
909 "renesas, <<
910 #interrupt-cells = <2> <<
911 #address-cells = <0>; <<
912 interrupt-controller; <<
913 reg = <0 0x110a0000 0 <<
914 interrupts = <GIC_SPI <<
915 <GIC_SPI <<
916 <GIC_SPI <<
917 <GIC_SPI <<
918 <GIC_SPI <<
919 <GIC_SPI <<
920 <GIC_SPI <<
921 <GIC_SPI <<
922 <GIC_SPI <<
923 <GIC_SPI <<
924 <GIC_SPI <<
925 <GIC_SPI <<
926 <GIC_SPI <<
927 <GIC_SPI <<
928 <GIC_SPI <<
929 <GIC_SPI <<
930 <GIC_SPI <<
931 <GIC_SPI <<
932 <GIC_SPI <<
933 <GIC_SPI <<
934 <GIC_SPI <<
935 <GIC_SPI <<
936 <GIC_SPI <<
937 <GIC_SPI <<
938 <GIC_SPI <<
939 <GIC_SPI <<
940 <GIC_SPI <<
941 <GIC_SPI <<
942 <GIC_SPI <<
943 <GIC_SPI <<
944 <GIC_SPI <<
945 <GIC_SPI <<
946 <GIC_SPI <<
947 <GIC_SPI <<
948 <GIC_SPI <<
949 <GIC_SPI <<
950 <GIC_SPI <<
951 <GIC_SPI <<
952 <GIC_SPI <<
953 <GIC_SPI <<
954 <GIC_SPI <<
955 <GIC_SPI <<
956 <GIC_SPI <<
957 <GIC_SPI <<
958 <GIC_SPI <<
959 <GIC_SPI <<
960 <GIC_SPI <<
961 <GIC_SPI <<
962 interrupt-names = "nmi <<
963 "irq <<
964 "tin <<
965 "tin <<
966 "tin <<
967 "tin <<
968 "tin <<
969 "tin <<
970 "tin <<
971 "tin <<
972 "bus <<
973 "ec7 <<
974 "ec7 <<
975 clocks = <&cpg CPG_MOD <<
976 <&cpg CPG_MOD <<
977 clock-names = "clk", " <<
978 power-domains = <&cpg> <<
979 resets = <&cpg R9A07G0 <<
980 }; <<
981 <<
982 dmac: dma-controller@11820000 649 dmac: dma-controller@11820000 {
983 compatible = "renesas, 650 compatible = "renesas,r9a07g044-dmac",
984 "renesas, 651 "renesas,rz-dmac";
985 reg = <0 0x11820000 0 652 reg = <0 0x11820000 0 0x10000>,
986 <0 0x11830000 0 653 <0 0x11830000 0 0x10000>;
987 interrupts = <GIC_SPI 654 interrupts = <GIC_SPI 141 IRQ_TYPE_EDGE_RISING>,
988 <GIC_SPI 655 <GIC_SPI 125 IRQ_TYPE_EDGE_RISING>,
989 <GIC_SPI 656 <GIC_SPI 126 IRQ_TYPE_EDGE_RISING>,
990 <GIC_SPI 657 <GIC_SPI 127 IRQ_TYPE_EDGE_RISING>,
991 <GIC_SPI 658 <GIC_SPI 128 IRQ_TYPE_EDGE_RISING>,
992 <GIC_SPI 659 <GIC_SPI 129 IRQ_TYPE_EDGE_RISING>,
993 <GIC_SPI 660 <GIC_SPI 130 IRQ_TYPE_EDGE_RISING>,
994 <GIC_SPI 661 <GIC_SPI 131 IRQ_TYPE_EDGE_RISING>,
995 <GIC_SPI 662 <GIC_SPI 132 IRQ_TYPE_EDGE_RISING>,
996 <GIC_SPI 663 <GIC_SPI 133 IRQ_TYPE_EDGE_RISING>,
997 <GIC_SPI 664 <GIC_SPI 134 IRQ_TYPE_EDGE_RISING>,
998 <GIC_SPI 665 <GIC_SPI 135 IRQ_TYPE_EDGE_RISING>,
999 <GIC_SPI 666 <GIC_SPI 136 IRQ_TYPE_EDGE_RISING>,
1000 <GIC_SPI 667 <GIC_SPI 137 IRQ_TYPE_EDGE_RISING>,
1001 <GIC_SPI 668 <GIC_SPI 138 IRQ_TYPE_EDGE_RISING>,
1002 <GIC_SPI 669 <GIC_SPI 139 IRQ_TYPE_EDGE_RISING>,
1003 <GIC_SPI 670 <GIC_SPI 140 IRQ_TYPE_EDGE_RISING>;
1004 interrupt-names = "er 671 interrupt-names = "error",
1005 "ch 672 "ch0", "ch1", "ch2", "ch3",
1006 "ch 673 "ch4", "ch5", "ch6", "ch7",
1007 "ch 674 "ch8", "ch9", "ch10", "ch11",
1008 "ch 675 "ch12", "ch13", "ch14", "ch15";
1009 clocks = <&cpg CPG_MO 676 clocks = <&cpg CPG_MOD R9A07G044_DMAC_ACLK>,
1010 <&cpg CPG_MO 677 <&cpg CPG_MOD R9A07G044_DMAC_PCLK>;
1011 clock-names = "main", <<
1012 power-domains = <&cpg 678 power-domains = <&cpg>;
1013 resets = <&cpg R9A07G 679 resets = <&cpg R9A07G044_DMAC_ARESETN>,
1014 <&cpg R9A07G 680 <&cpg R9A07G044_DMAC_RST_ASYNC>;
1015 reset-names = "arst", <<
1016 #dma-cells = <1>; 681 #dma-cells = <1>;
1017 dma-channels = <16>; 682 dma-channels = <16>;
1018 }; 683 };
1019 684
1020 gpu: gpu@11840000 { 685 gpu: gpu@11840000 {
1021 compatible = "renesas 686 compatible = "renesas,r9a07g044-mali",
1022 "arm,mal 687 "arm,mali-bifrost";
1023 reg = <0x0 0x11840000 688 reg = <0x0 0x11840000 0x0 0x10000>;
1024 interrupts = <GIC_SPI 689 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
1025 <GIC_SPI 690 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
1026 <GIC_SPI 691 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
1027 <GIC_SPI 692 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
1028 interrupt-names = "jo 693 interrupt-names = "job", "mmu", "gpu", "event";
1029 clocks = <&cpg CPG_MO 694 clocks = <&cpg CPG_MOD R9A07G044_GPU_CLK>,
1030 <&cpg CPG_MO 695 <&cpg CPG_MOD R9A07G044_GPU_AXI_CLK>,
1031 <&cpg CPG_MO 696 <&cpg CPG_MOD R9A07G044_GPU_ACE_CLK>;
1032 clock-names = "gpu", 697 clock-names = "gpu", "bus", "bus_ace";
1033 power-domains = <&cpg 698 power-domains = <&cpg>;
1034 resets = <&cpg R9A07G 699 resets = <&cpg R9A07G044_GPU_RESETN>,
1035 <&cpg R9A07G 700 <&cpg R9A07G044_GPU_AXI_RESETN>,
1036 <&cpg R9A07G 701 <&cpg R9A07G044_GPU_ACE_RESETN>;
1037 reset-names = "rst", 702 reset-names = "rst", "axi_rst", "ace_rst";
1038 operating-points-v2 = 703 operating-points-v2 = <&gpu_opp_table>;
1039 }; 704 };
1040 705
1041 gic: interrupt-controller@119 706 gic: interrupt-controller@11900000 {
1042 compatible = "arm,gic 707 compatible = "arm,gic-v3";
1043 #interrupt-cells = <3 708 #interrupt-cells = <3>;
1044 #address-cells = <0>; 709 #address-cells = <0>;
1045 interrupt-controller; 710 interrupt-controller;
1046 reg = <0x0 0x11900000 !! 711 reg = <0x0 0x11900000 0 0x40000>,
1047 <0x0 0x11940000 !! 712 <0x0 0x11940000 0 0x60000>;
1048 interrupts = <GIC_PPI 713 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
1049 }; 714 };
1050 715
1051 sdhi0: mmc@11c00000 { !! 716 sdhi0: mmc@11c00000 {
1052 compatible = "renesas 717 compatible = "renesas,sdhi-r9a07g044",
1053 "renesas !! 718 "renesas,rcar-gen3-sdhi";
1054 reg = <0x0 0x11c00000 719 reg = <0x0 0x11c00000 0 0x10000>;
1055 interrupts = <GIC_SPI 720 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
1056 <GIC_SPI 721 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
1057 clocks = <&cpg CPG_MO 722 clocks = <&cpg CPG_MOD R9A07G044_SDHI0_IMCLK>,
1058 <&cpg CPG_MO 723 <&cpg CPG_MOD R9A07G044_SDHI0_CLK_HS>,
1059 <&cpg CPG_MO 724 <&cpg CPG_MOD R9A07G044_SDHI0_IMCLK2>,
1060 <&cpg CPG_MO 725 <&cpg CPG_MOD R9A07G044_SDHI0_ACLK>;
1061 clock-names = "core", 726 clock-names = "core", "clkh", "cd", "aclk";
1062 resets = <&cpg R9A07G 727 resets = <&cpg R9A07G044_SDHI0_IXRST>;
1063 power-domains = <&cpg 728 power-domains = <&cpg>;
1064 status = "disabled"; 729 status = "disabled";
1065 }; 730 };
1066 731
1067 sdhi1: mmc@11c10000 { 732 sdhi1: mmc@11c10000 {
1068 compatible = "renesas 733 compatible = "renesas,sdhi-r9a07g044",
1069 "renesas !! 734 "renesas,rcar-gen3-sdhi";
1070 reg = <0x0 0x11c10000 735 reg = <0x0 0x11c10000 0 0x10000>;
1071 interrupts = <GIC_SPI 736 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
1072 <GIC_SPI 737 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
1073 clocks = <&cpg CPG_MO 738 clocks = <&cpg CPG_MOD R9A07G044_SDHI1_IMCLK>,
1074 <&cpg CPG_MO 739 <&cpg CPG_MOD R9A07G044_SDHI1_CLK_HS>,
1075 <&cpg CPG_MO 740 <&cpg CPG_MOD R9A07G044_SDHI1_IMCLK2>,
1076 <&cpg CPG_MO 741 <&cpg CPG_MOD R9A07G044_SDHI1_ACLK>;
1077 clock-names = "core", 742 clock-names = "core", "clkh", "cd", "aclk";
1078 resets = <&cpg R9A07G 743 resets = <&cpg R9A07G044_SDHI1_IXRST>;
1079 power-domains = <&cpg 744 power-domains = <&cpg>;
1080 status = "disabled"; 745 status = "disabled";
1081 }; 746 };
1082 747
1083 eth0: ethernet@11c20000 { 748 eth0: ethernet@11c20000 {
1084 compatible = "renesas 749 compatible = "renesas,r9a07g044-gbeth",
1085 "renesas 750 "renesas,rzg2l-gbeth";
1086 reg = <0 0x11c20000 0 751 reg = <0 0x11c20000 0 0x10000>;
1087 interrupts = <GIC_SPI 752 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
1088 <GIC_SPI 753 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
1089 <GIC_SPI 754 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
1090 interrupt-names = "mu 755 interrupt-names = "mux", "fil", "arp_ns";
1091 phy-mode = "rgmii"; 756 phy-mode = "rgmii";
1092 clocks = <&cpg CPG_MO 757 clocks = <&cpg CPG_MOD R9A07G044_ETH0_CLK_AXI>,
1093 <&cpg CPG_MO 758 <&cpg CPG_MOD R9A07G044_ETH0_CLK_CHI>,
1094 <&cpg CPG_CO 759 <&cpg CPG_CORE R9A07G044_CLK_HP>;
1095 clock-names = "axi", 760 clock-names = "axi", "chi", "refclk";
1096 resets = <&cpg R9A07G 761 resets = <&cpg R9A07G044_ETH0_RST_HW_N>;
1097 power-domains = <&cpg 762 power-domains = <&cpg>;
1098 #address-cells = <1>; 763 #address-cells = <1>;
1099 #size-cells = <0>; 764 #size-cells = <0>;
1100 status = "disabled"; 765 status = "disabled";
1101 }; 766 };
1102 767
1103 eth1: ethernet@11c30000 { 768 eth1: ethernet@11c30000 {
1104 compatible = "renesas 769 compatible = "renesas,r9a07g044-gbeth",
1105 "renesas 770 "renesas,rzg2l-gbeth";
1106 reg = <0 0x11c30000 0 771 reg = <0 0x11c30000 0 0x10000>;
1107 interrupts = <GIC_SPI 772 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
1108 <GIC_SPI 773 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
1109 <GIC_SPI 774 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
1110 interrupt-names = "mu 775 interrupt-names = "mux", "fil", "arp_ns";
1111 phy-mode = "rgmii"; 776 phy-mode = "rgmii";
1112 clocks = <&cpg CPG_MO 777 clocks = <&cpg CPG_MOD R9A07G044_ETH1_CLK_AXI>,
1113 <&cpg CPG_MO 778 <&cpg CPG_MOD R9A07G044_ETH1_CLK_CHI>,
1114 <&cpg CPG_CO 779 <&cpg CPG_CORE R9A07G044_CLK_HP>;
1115 clock-names = "axi", 780 clock-names = "axi", "chi", "refclk";
1116 resets = <&cpg R9A07G 781 resets = <&cpg R9A07G044_ETH1_RST_HW_N>;
1117 power-domains = <&cpg 782 power-domains = <&cpg>;
1118 #address-cells = <1>; 783 #address-cells = <1>;
1119 #size-cells = <0>; 784 #size-cells = <0>;
1120 status = "disabled"; 785 status = "disabled";
1121 }; 786 };
1122 787
1123 phyrst: usbphy-ctrl@11c40000 788 phyrst: usbphy-ctrl@11c40000 {
1124 compatible = "renesas 789 compatible = "renesas,r9a07g044-usbphy-ctrl",
1125 "renesas 790 "renesas,rzg2l-usbphy-ctrl";
1126 reg = <0 0x11c40000 0 791 reg = <0 0x11c40000 0 0x10000>;
1127 clocks = <&cpg CPG_MO 792 clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>;
1128 resets = <&cpg R9A07G 793 resets = <&cpg R9A07G044_USB_PRESETN>;
1129 power-domains = <&cpg 794 power-domains = <&cpg>;
1130 #reset-cells = <1>; 795 #reset-cells = <1>;
1131 status = "disabled"; 796 status = "disabled";
1132 <<
1133 usb0_vbus_otg: regula <<
1134 regulator-nam <<
1135 }; <<
1136 }; 797 };
1137 798
1138 ohci0: usb@11c50000 { 799 ohci0: usb@11c50000 {
1139 compatible = "generic 800 compatible = "generic-ohci";
1140 reg = <0 0x11c50000 0 801 reg = <0 0x11c50000 0 0x100>;
1141 interrupts = <GIC_SPI 802 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
1142 clocks = <&cpg CPG_MO 803 clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>,
1143 <&cpg CPG_MO 804 <&cpg CPG_MOD R9A07G044_USB_U2H0_HCLK>;
1144 resets = <&phyrst 0>, 805 resets = <&phyrst 0>,
1145 <&cpg R9A07G 806 <&cpg R9A07G044_USB_U2H0_HRESETN>;
1146 phys = <&usb2_phy0 1> 807 phys = <&usb2_phy0 1>;
1147 phy-names = "usb"; 808 phy-names = "usb";
1148 power-domains = <&cpg 809 power-domains = <&cpg>;
1149 status = "disabled"; 810 status = "disabled";
1150 }; 811 };
1151 812
1152 ohci1: usb@11c70000 { 813 ohci1: usb@11c70000 {
1153 compatible = "generic 814 compatible = "generic-ohci";
1154 reg = <0 0x11c70000 0 815 reg = <0 0x11c70000 0 0x100>;
1155 interrupts = <GIC_SPI 816 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
1156 clocks = <&cpg CPG_MO 817 clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>,
1157 <&cpg CPG_MO 818 <&cpg CPG_MOD R9A07G044_USB_U2H1_HCLK>;
1158 resets = <&phyrst 1>, 819 resets = <&phyrst 1>,
1159 <&cpg R9A07G 820 <&cpg R9A07G044_USB_U2H1_HRESETN>;
1160 phys = <&usb2_phy1 1> 821 phys = <&usb2_phy1 1>;
1161 phy-names = "usb"; 822 phy-names = "usb";
1162 power-domains = <&cpg 823 power-domains = <&cpg>;
1163 status = "disabled"; 824 status = "disabled";
1164 }; 825 };
1165 826
1166 ehci0: usb@11c50100 { 827 ehci0: usb@11c50100 {
1167 compatible = "generic 828 compatible = "generic-ehci";
1168 reg = <0 0x11c50100 0 829 reg = <0 0x11c50100 0 0x100>;
1169 interrupts = <GIC_SPI 830 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
1170 clocks = <&cpg CPG_MO 831 clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>,
1171 <&cpg CPG_MO 832 <&cpg CPG_MOD R9A07G044_USB_U2H0_HCLK>;
1172 resets = <&phyrst 0>, 833 resets = <&phyrst 0>,
1173 <&cpg R9A07G 834 <&cpg R9A07G044_USB_U2H0_HRESETN>;
1174 phys = <&usb2_phy0 2> 835 phys = <&usb2_phy0 2>;
1175 phy-names = "usb"; 836 phy-names = "usb";
1176 companion = <&ohci0>; 837 companion = <&ohci0>;
1177 power-domains = <&cpg 838 power-domains = <&cpg>;
1178 status = "disabled"; 839 status = "disabled";
1179 }; 840 };
1180 841
1181 ehci1: usb@11c70100 { 842 ehci1: usb@11c70100 {
1182 compatible = "generic 843 compatible = "generic-ehci";
1183 reg = <0 0x11c70100 0 844 reg = <0 0x11c70100 0 0x100>;
1184 interrupts = <GIC_SPI 845 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
1185 clocks = <&cpg CPG_MO 846 clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>,
1186 <&cpg CPG_MO 847 <&cpg CPG_MOD R9A07G044_USB_U2H1_HCLK>;
1187 resets = <&phyrst 1>, 848 resets = <&phyrst 1>,
1188 <&cpg R9A07G 849 <&cpg R9A07G044_USB_U2H1_HRESETN>;
1189 phys = <&usb2_phy1 2> 850 phys = <&usb2_phy1 2>;
1190 phy-names = "usb"; 851 phy-names = "usb";
1191 companion = <&ohci1>; 852 companion = <&ohci1>;
1192 power-domains = <&cpg 853 power-domains = <&cpg>;
1193 status = "disabled"; 854 status = "disabled";
1194 }; 855 };
1195 856
1196 usb2_phy0: usb-phy@11c50200 { 857 usb2_phy0: usb-phy@11c50200 {
1197 compatible = "renesas 858 compatible = "renesas,usb2-phy-r9a07g044",
1198 "renesas 859 "renesas,rzg2l-usb2-phy";
1199 reg = <0 0x11c50200 0 860 reg = <0 0x11c50200 0 0x700>;
1200 interrupts = <GIC_SPI 861 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
1201 clocks = <&cpg CPG_MO 862 clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>,
1202 <&cpg CPG_MO 863 <&cpg CPG_MOD R9A07G044_USB_U2H0_HCLK>;
1203 resets = <&phyrst 0>; 864 resets = <&phyrst 0>;
1204 #phy-cells = <1>; 865 #phy-cells = <1>;
1205 power-domains = <&cpg 866 power-domains = <&cpg>;
1206 status = "disabled"; 867 status = "disabled";
1207 }; 868 };
1208 869
1209 usb2_phy1: usb-phy@11c70200 { 870 usb2_phy1: usb-phy@11c70200 {
1210 compatible = "renesas 871 compatible = "renesas,usb2-phy-r9a07g044",
1211 "renesas 872 "renesas,rzg2l-usb2-phy";
1212 reg = <0 0x11c70200 0 873 reg = <0 0x11c70200 0 0x700>;
1213 interrupts = <GIC_SPI 874 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
1214 clocks = <&cpg CPG_MO 875 clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>,
1215 <&cpg CPG_MO 876 <&cpg CPG_MOD R9A07G044_USB_U2H1_HCLK>;
1216 resets = <&phyrst 1>; 877 resets = <&phyrst 1>;
1217 #phy-cells = <1>; 878 #phy-cells = <1>;
1218 power-domains = <&cpg 879 power-domains = <&cpg>;
1219 status = "disabled"; 880 status = "disabled";
1220 }; 881 };
1221 882
1222 hsusb: usb@11c60000 { 883 hsusb: usb@11c60000 {
1223 compatible = "renesas 884 compatible = "renesas,usbhs-r9a07g044",
1224 "renesas !! 885 "renesas,rza2-usbhs";
1225 reg = <0 0x11c60000 0 886 reg = <0 0x11c60000 0 0x10000>;
1226 interrupts = <GIC_SPI 887 interrupts = <GIC_SPI 100 IRQ_TYPE_EDGE_RISING>,
1227 <GIC_SPI 888 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
1228 <GIC_SPI 889 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
1229 <GIC_SPI 890 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
1230 clocks = <&cpg CPG_MO 891 clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>,
1231 <&cpg CPG_MO 892 <&cpg CPG_MOD R9A07G044_USB_U2P_EXR_CPUCLK>;
1232 resets = <&phyrst 0>, 893 resets = <&phyrst 0>,
1233 <&cpg R9A07G 894 <&cpg R9A07G044_USB_U2P_EXL_SYSRST>;
1234 renesas,buswait = <7> 895 renesas,buswait = <7>;
1235 phys = <&usb2_phy0 3> 896 phys = <&usb2_phy0 3>;
1236 phy-names = "usb"; 897 phy-names = "usb";
1237 power-domains = <&cpg 898 power-domains = <&cpg>;
1238 status = "disabled"; 899 status = "disabled";
1239 }; 900 };
1240 901
1241 wdt0: watchdog@12800800 { 902 wdt0: watchdog@12800800 {
1242 compatible = "renesas 903 compatible = "renesas,r9a07g044-wdt",
1243 "renesas 904 "renesas,rzg2l-wdt";
1244 reg = <0 0x12800800 0 905 reg = <0 0x12800800 0 0x400>;
1245 clocks = <&cpg CPG_MO 906 clocks = <&cpg CPG_MOD R9A07G044_WDT0_PCLK>,
1246 <&cpg CPG_MO 907 <&cpg CPG_MOD R9A07G044_WDT0_CLK>;
1247 clock-names = "pclk", 908 clock-names = "pclk", "oscclk";
1248 interrupts = <GIC_SPI 909 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
1249 <GIC_SPI 910 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
1250 interrupt-names = "wd 911 interrupt-names = "wdt", "perrout";
1251 resets = <&cpg R9A07G 912 resets = <&cpg R9A07G044_WDT0_PRESETN>;
1252 power-domains = <&cpg 913 power-domains = <&cpg>;
1253 status = "disabled"; 914 status = "disabled";
1254 }; 915 };
1255 916
1256 wdt1: watchdog@12800c00 { 917 wdt1: watchdog@12800c00 {
1257 compatible = "renesas 918 compatible = "renesas,r9a07g044-wdt",
1258 "renesas 919 "renesas,rzg2l-wdt";
1259 reg = <0 0x12800C00 0 920 reg = <0 0x12800C00 0 0x400>;
1260 clocks = <&cpg CPG_MO 921 clocks = <&cpg CPG_MOD R9A07G044_WDT1_PCLK>,
1261 <&cpg CPG_MO 922 <&cpg CPG_MOD R9A07G044_WDT1_CLK>;
1262 clock-names = "pclk", 923 clock-names = "pclk", "oscclk";
1263 interrupts = <GIC_SPI 924 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
1264 <GIC_SPI 925 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
1265 interrupt-names = "wd 926 interrupt-names = "wdt", "perrout";
1266 resets = <&cpg R9A07G 927 resets = <&cpg R9A07G044_WDT1_PRESETN>;
1267 power-domains = <&cpg 928 power-domains = <&cpg>;
1268 status = "disabled"; 929 status = "disabled";
1269 }; 930 };
1270 931
>> 932 wdt2: watchdog@12800400 {
>> 933 compatible = "renesas,r9a07g044-wdt",
>> 934 "renesas,rzg2l-wdt";
>> 935 reg = <0 0x12800400 0 0x400>;
>> 936 clocks = <&cpg CPG_MOD R9A07G044_WDT2_PCLK>,
>> 937 <&cpg CPG_MOD R9A07G044_WDT2_CLK>;
>> 938 clock-names = "pclk", "oscclk";
>> 939 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
>> 940 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
>> 941 interrupt-names = "wdt", "perrout";
>> 942 resets = <&cpg R9A07G044_WDT2_PRESETN>;
>> 943 power-domains = <&cpg>;
>> 944 status = "disabled";
>> 945 };
>> 946
1271 ostm0: timer@12801000 { 947 ostm0: timer@12801000 {
1272 compatible = "renesas 948 compatible = "renesas,r9a07g044-ostm",
1273 "renesas 949 "renesas,ostm";
1274 reg = <0x0 0x12801000 950 reg = <0x0 0x12801000 0x0 0x400>;
1275 interrupts = <GIC_SPI 951 interrupts = <GIC_SPI 46 IRQ_TYPE_EDGE_RISING>;
1276 clocks = <&cpg CPG_MO 952 clocks = <&cpg CPG_MOD R9A07G044_OSTM0_PCLK>;
1277 resets = <&cpg R9A07G 953 resets = <&cpg R9A07G044_OSTM0_PRESETZ>;
1278 power-domains = <&cpg 954 power-domains = <&cpg>;
1279 status = "disabled"; 955 status = "disabled";
1280 }; 956 };
1281 957
1282 ostm1: timer@12801400 { 958 ostm1: timer@12801400 {
1283 compatible = "renesas 959 compatible = "renesas,r9a07g044-ostm",
1284 "renesas 960 "renesas,ostm";
1285 reg = <0x0 0x12801400 961 reg = <0x0 0x12801400 0x0 0x400>;
1286 interrupts = <GIC_SPI 962 interrupts = <GIC_SPI 47 IRQ_TYPE_EDGE_RISING>;
1287 clocks = <&cpg CPG_MO 963 clocks = <&cpg CPG_MOD R9A07G044_OSTM1_PCLK>;
1288 resets = <&cpg R9A07G 964 resets = <&cpg R9A07G044_OSTM1_PRESETZ>;
1289 power-domains = <&cpg 965 power-domains = <&cpg>;
1290 status = "disabled"; 966 status = "disabled";
1291 }; 967 };
1292 968
1293 ostm2: timer@12801800 { 969 ostm2: timer@12801800 {
1294 compatible = "renesas 970 compatible = "renesas,r9a07g044-ostm",
1295 "renesas 971 "renesas,ostm";
1296 reg = <0x0 0x12801800 972 reg = <0x0 0x12801800 0x0 0x400>;
1297 interrupts = <GIC_SPI 973 interrupts = <GIC_SPI 48 IRQ_TYPE_EDGE_RISING>;
1298 clocks = <&cpg CPG_MO 974 clocks = <&cpg CPG_MOD R9A07G044_OSTM2_PCLK>;
1299 resets = <&cpg R9A07G 975 resets = <&cpg R9A07G044_OSTM2_PRESETZ>;
1300 power-domains = <&cpg 976 power-domains = <&cpg>;
1301 status = "disabled"; 977 status = "disabled";
1302 }; 978 };
1303 }; 979 };
1304 980
1305 thermal-zones { 981 thermal-zones {
1306 cpu-thermal { 982 cpu-thermal {
1307 polling-delay-passive 983 polling-delay-passive = <250>;
1308 polling-delay = <1000 984 polling-delay = <1000>;
1309 thermal-sensors = <&t 985 thermal-sensors = <&tsu 0>;
1310 sustainable-power = < 986 sustainable-power = <717>;
1311 987
1312 cooling-maps { 988 cooling-maps {
1313 map0 { 989 map0 {
1314 trip 990 trip = <&target>;
1315 cooli 991 cooling-device = <&cpu0 0 2>;
1316 contr 992 contribution = <1024>;
1317 }; 993 };
1318 }; 994 };
1319 995
1320 trips { 996 trips {
1321 sensor_crit: 997 sensor_crit: sensor-crit {
1322 tempe 998 temperature = <125000>;
1323 hyste 999 hysteresis = <1000>;
1324 type 1000 type = "critical";
1325 }; 1001 };
1326 1002
1327 target: trip- 1003 target: trip-point {
1328 tempe 1004 temperature = <100000>;
1329 hyste 1005 hysteresis = <1000>;
1330 type 1006 type = "passive";
1331 }; 1007 };
1332 }; 1008 };
1333 }; 1009 };
1334 }; 1010 };
1335 1011
1336 timer { 1012 timer {
1337 compatible = "arm,armv8-timer 1013 compatible = "arm,armv8-timer";
1338 interrupts-extended = <&gic G !! 1014 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
1339 <&gic G !! 1015 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
1340 <&gic G !! 1016 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
1341 <&gic G !! 1017 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
1342 <&gic G <<
1343 interrupt-names = "sec-phys", <<
1344 "hyp-virt"; <<
1345 }; 1018 };
1346 }; 1019 };
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