1 // SPDX-License-Identifier: (GPL-2.0-only OR B 1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 /* 2 /*
3 * Device Tree Source for the RZ/G2L and RZ/G2 3 * Device Tree Source for the RZ/G2L and RZ/G2LC common SoC parts
4 * 4 *
5 * Copyright (C) 2021 Renesas Electronics Corp 5 * Copyright (C) 2021 Renesas Electronics Corp.
6 */ 6 */
7 7
8 #include <dt-bindings/interrupt-controller/arm 8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/clock/r9a07g044-cpg.h> 9 #include <dt-bindings/clock/r9a07g044-cpg.h>
10 10
11 / { 11 / {
12 compatible = "renesas,r9a07g044"; 12 compatible = "renesas,r9a07g044";
13 #address-cells = <2>; 13 #address-cells = <2>;
14 #size-cells = <2>; 14 #size-cells = <2>;
15 15
16 audio_clk1: audio1-clk { 16 audio_clk1: audio1-clk {
17 compatible = "fixed-clock"; 17 compatible = "fixed-clock";
18 #clock-cells = <0>; 18 #clock-cells = <0>;
19 /* This value must be overridd 19 /* This value must be overridden by boards that provide it */
20 clock-frequency = <0>; 20 clock-frequency = <0>;
21 }; 21 };
22 22
23 audio_clk2: audio2-clk { 23 audio_clk2: audio2-clk {
24 compatible = "fixed-clock"; 24 compatible = "fixed-clock";
25 #clock-cells = <0>; 25 #clock-cells = <0>;
26 /* This value must be overridd 26 /* This value must be overridden by boards that provide it */
27 clock-frequency = <0>; 27 clock-frequency = <0>;
28 }; 28 };
29 29
30 /* External CAN clock - to be overridd 30 /* External CAN clock - to be overridden by boards that provide it */
31 can_clk: can-clk { 31 can_clk: can-clk {
32 compatible = "fixed-clock"; 32 compatible = "fixed-clock";
33 #clock-cells = <0>; 33 #clock-cells = <0>;
34 clock-frequency = <0>; 34 clock-frequency = <0>;
35 }; 35 };
36 36
37 /* clock can be either from exclk or c 37 /* clock can be either from exclk or crystal oscillator (XIN/XOUT) */
38 extal_clk: extal-clk { 38 extal_clk: extal-clk {
39 compatible = "fixed-clock"; 39 compatible = "fixed-clock";
40 #clock-cells = <0>; 40 #clock-cells = <0>;
41 /* This value must be overridd 41 /* This value must be overridden by the board */
42 clock-frequency = <0>; 42 clock-frequency = <0>;
43 }; 43 };
44 44
45 cluster0_opp: opp-table-0 { 45 cluster0_opp: opp-table-0 {
46 compatible = "operating-points 46 compatible = "operating-points-v2";
47 opp-shared; 47 opp-shared;
48 48
49 opp-150000000 { 49 opp-150000000 {
50 opp-hz = /bits/ 64 <15 50 opp-hz = /bits/ 64 <150000000>;
51 opp-microvolt = <11000 51 opp-microvolt = <1100000>;
52 clock-latency-ns = <30 52 clock-latency-ns = <300000>;
53 }; 53 };
54 opp-300000000 { 54 opp-300000000 {
55 opp-hz = /bits/ 64 <30 55 opp-hz = /bits/ 64 <300000000>;
56 opp-microvolt = <11000 56 opp-microvolt = <1100000>;
57 clock-latency-ns = <30 57 clock-latency-ns = <300000>;
58 }; 58 };
59 opp-600000000 { 59 opp-600000000 {
60 opp-hz = /bits/ 64 <60 60 opp-hz = /bits/ 64 <600000000>;
61 opp-microvolt = <11000 61 opp-microvolt = <1100000>;
62 clock-latency-ns = <30 62 clock-latency-ns = <300000>;
63 }; 63 };
64 opp-1200000000 { 64 opp-1200000000 {
65 opp-hz = /bits/ 64 <12 65 opp-hz = /bits/ 64 <1200000000>;
66 opp-microvolt = <11000 66 opp-microvolt = <1100000>;
67 clock-latency-ns = <30 67 clock-latency-ns = <300000>;
68 opp-suspend; 68 opp-suspend;
69 }; 69 };
70 }; 70 };
71 71
72 cpus { 72 cpus {
73 #address-cells = <1>; 73 #address-cells = <1>;
74 #size-cells = <0>; 74 #size-cells = <0>;
75 75
76 cpu-map { 76 cpu-map {
77 cluster0 { 77 cluster0 {
78 core0 { 78 core0 {
79 cpu = 79 cpu = <&cpu0>;
80 }; 80 };
81 core1 { 81 core1 {
82 cpu = 82 cpu = <&cpu1>;
83 }; 83 };
84 }; 84 };
85 }; 85 };
86 86
87 cpu0: cpu@0 { 87 cpu0: cpu@0 {
88 compatible = "arm,cort 88 compatible = "arm,cortex-a55";
89 reg = <0>; 89 reg = <0>;
90 device_type = "cpu"; 90 device_type = "cpu";
91 #cooling-cells = <2>; 91 #cooling-cells = <2>;
92 next-level-cache = <&L 92 next-level-cache = <&L3_CA55>;
93 enable-method = "psci" 93 enable-method = "psci";
94 clocks = <&cpg CPG_COR 94 clocks = <&cpg CPG_CORE R9A07G044_CLK_I>;
95 operating-points-v2 = 95 operating-points-v2 = <&cluster0_opp>;
96 }; 96 };
97 97
98 cpu1: cpu@100 { 98 cpu1: cpu@100 {
99 compatible = "arm,cort 99 compatible = "arm,cortex-a55";
100 reg = <0x100>; 100 reg = <0x100>;
101 device_type = "cpu"; 101 device_type = "cpu";
102 next-level-cache = <&L 102 next-level-cache = <&L3_CA55>;
103 enable-method = "psci" 103 enable-method = "psci";
104 clocks = <&cpg CPG_COR 104 clocks = <&cpg CPG_CORE R9A07G044_CLK_I>;
105 operating-points-v2 = 105 operating-points-v2 = <&cluster0_opp>;
106 }; 106 };
107 107
108 L3_CA55: cache-controller-0 { 108 L3_CA55: cache-controller-0 {
109 compatible = "cache"; 109 compatible = "cache";
110 cache-unified; 110 cache-unified;
111 cache-size = <0x40000> 111 cache-size = <0x40000>;
112 cache-level = <3>; <<
113 }; 112 };
114 }; 113 };
115 114
116 gpu_opp_table: opp-table-1 { 115 gpu_opp_table: opp-table-1 {
117 compatible = "operating-points 116 compatible = "operating-points-v2";
118 117
119 opp-500000000 { 118 opp-500000000 {
120 opp-hz = /bits/ 64 <50 119 opp-hz = /bits/ 64 <500000000>;
121 opp-microvolt = <11000 120 opp-microvolt = <1100000>;
122 }; 121 };
123 122
124 opp-400000000 { 123 opp-400000000 {
125 opp-hz = /bits/ 64 <40 124 opp-hz = /bits/ 64 <400000000>;
126 opp-microvolt = <11000 125 opp-microvolt = <1100000>;
127 }; 126 };
128 127
129 opp-250000000 { 128 opp-250000000 {
130 opp-hz = /bits/ 64 <25 129 opp-hz = /bits/ 64 <250000000>;
131 opp-microvolt = <11000 130 opp-microvolt = <1100000>;
132 }; 131 };
133 132
134 opp-200000000 { 133 opp-200000000 {
135 opp-hz = /bits/ 64 <20 134 opp-hz = /bits/ 64 <200000000>;
136 opp-microvolt = <11000 135 opp-microvolt = <1100000>;
137 }; 136 };
138 137
139 opp-125000000 { 138 opp-125000000 {
140 opp-hz = /bits/ 64 <12 139 opp-hz = /bits/ 64 <125000000>;
141 opp-microvolt = <11000 140 opp-microvolt = <1100000>;
142 }; 141 };
143 142
144 opp-100000000 { 143 opp-100000000 {
145 opp-hz = /bits/ 64 <10 144 opp-hz = /bits/ 64 <100000000>;
146 opp-microvolt = <11000 145 opp-microvolt = <1100000>;
147 }; 146 };
148 147
149 opp-62500000 { 148 opp-62500000 {
150 opp-hz = /bits/ 64 <62 149 opp-hz = /bits/ 64 <62500000>;
151 opp-microvolt = <11000 150 opp-microvolt = <1100000>;
152 }; 151 };
153 152
154 opp-50000000 { 153 opp-50000000 {
155 opp-hz = /bits/ 64 <50 154 opp-hz = /bits/ 64 <50000000>;
156 opp-microvolt = <11000 155 opp-microvolt = <1100000>;
157 }; 156 };
158 }; 157 };
159 158
160 pmu { <<
161 compatible = "arm,cortex-a55-p <<
162 interrupts-extended = <&gic GI <<
163 }; <<
164 <<
165 psci { 159 psci {
166 compatible = "arm,psci-1.0", " 160 compatible = "arm,psci-1.0", "arm,psci-0.2";
167 method = "smc"; 161 method = "smc";
168 }; 162 };
169 163
170 soc: soc { 164 soc: soc {
171 compatible = "simple-bus"; 165 compatible = "simple-bus";
172 interrupt-parent = <&gic>; 166 interrupt-parent = <&gic>;
173 #address-cells = <2>; 167 #address-cells = <2>;
174 #size-cells = <2>; 168 #size-cells = <2>;
175 ranges; 169 ranges;
176 170
177 mtu3: timer@10001200 { <<
178 compatible = "renesas, <<
179 "renesas, <<
180 reg = <0 0x10001200 0 <<
181 interrupts = <GIC_SPI <<
182 <GIC_SPI <<
183 <GIC_SPI <<
184 <GIC_SPI <<
185 <GIC_SPI <<
186 <GIC_SPI <<
187 <GIC_SPI <<
188 <GIC_SPI <<
189 <GIC_SPI <<
190 <GIC_SPI <<
191 <GIC_SPI <<
192 <GIC_SPI <<
193 <GIC_SPI <<
194 <GIC_SPI <<
195 <GIC_SPI <<
196 <GIC_SPI <<
197 <GIC_SPI <<
198 <GIC_SPI <<
199 <GIC_SPI <<
200 <GIC_SPI <<
201 <GIC_SPI <<
202 <GIC_SPI <<
203 <GIC_SPI <<
204 <GIC_SPI <<
205 <GIC_SPI <<
206 <GIC_SPI <<
207 <GIC_SPI <<
208 <GIC_SPI <<
209 <GIC_SPI <<
210 <GIC_SPI <<
211 <GIC_SPI <<
212 <GIC_SPI <<
213 <GIC_SPI <<
214 <GIC_SPI <<
215 <GIC_SPI <<
216 <GIC_SPI <<
217 <GIC_SPI <<
218 <GIC_SPI <<
219 <GIC_SPI <<
220 <GIC_SPI <<
221 <GIC_SPI <<
222 <GIC_SPI <<
223 <GIC_SPI <<
224 <GIC_SPI <<
225 interrupt-names = "tgi <<
226 "tci <<
227 "tgi <<
228 "tgi <<
229 "tgi <<
230 "tci <<
231 "tgi <<
232 "tci <<
233 "tgi <<
234 "tgi <<
235 "tci <<
236 "tgi <<
237 "tci <<
238 "tgi <<
239 "tci <<
240 clocks = <&cpg CPG_MOD <<
241 power-domains = <&cpg> <<
242 resets = <&cpg R9A07G0 <<
243 #pwm-cells = <2>; <<
244 status = "disabled"; <<
245 }; <<
246 <<
247 ssi0: ssi@10049c00 { 171 ssi0: ssi@10049c00 {
248 compatible = "renesas, 172 compatible = "renesas,r9a07g044-ssi",
249 "renesas, 173 "renesas,rz-ssi";
250 reg = <0 0x10049c00 0 174 reg = <0 0x10049c00 0 0x400>;
251 interrupts = <GIC_SPI 175 interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
252 <GIC_SPI 176 <GIC_SPI 327 IRQ_TYPE_EDGE_RISING>,
253 <GIC_SPI 177 <GIC_SPI 328 IRQ_TYPE_EDGE_RISING>;
254 interrupt-names = "int 178 interrupt-names = "int_req", "dma_rx", "dma_tx";
255 clocks = <&cpg CPG_MOD 179 clocks = <&cpg CPG_MOD R9A07G044_SSI0_PCLK2>,
256 <&cpg CPG_MOD 180 <&cpg CPG_MOD R9A07G044_SSI0_PCLK_SFR>,
257 <&audio_clk1> 181 <&audio_clk1>, <&audio_clk2>;
258 clock-names = "ssi", " 182 clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2";
259 resets = <&cpg R9A07G0 183 resets = <&cpg R9A07G044_SSI0_RST_M2_REG>;
260 dmas = <&dmac 0x2655>, 184 dmas = <&dmac 0x2655>, <&dmac 0x2656>;
261 dma-names = "tx", "rx" 185 dma-names = "tx", "rx";
262 power-domains = <&cpg> 186 power-domains = <&cpg>;
263 #sound-dai-cells = <0> 187 #sound-dai-cells = <0>;
264 status = "disabled"; 188 status = "disabled";
265 }; 189 };
266 190
267 ssi1: ssi@1004a000 { 191 ssi1: ssi@1004a000 {
268 compatible = "renesas, 192 compatible = "renesas,r9a07g044-ssi",
269 "renesas, 193 "renesas,rz-ssi";
270 reg = <0 0x1004a000 0 194 reg = <0 0x1004a000 0 0x400>;
271 interrupts = <GIC_SPI 195 interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
272 <GIC_SPI 196 <GIC_SPI 331 IRQ_TYPE_EDGE_RISING>,
273 <GIC_SPI 197 <GIC_SPI 332 IRQ_TYPE_EDGE_RISING>;
274 interrupt-names = "int 198 interrupt-names = "int_req", "dma_rx", "dma_tx";
275 clocks = <&cpg CPG_MOD 199 clocks = <&cpg CPG_MOD R9A07G044_SSI1_PCLK2>,
276 <&cpg CPG_MOD 200 <&cpg CPG_MOD R9A07G044_SSI1_PCLK_SFR>,
277 <&audio_clk1> 201 <&audio_clk1>, <&audio_clk2>;
278 clock-names = "ssi", " 202 clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2";
279 resets = <&cpg R9A07G0 203 resets = <&cpg R9A07G044_SSI1_RST_M2_REG>;
280 dmas = <&dmac 0x2659>, 204 dmas = <&dmac 0x2659>, <&dmac 0x265a>;
281 dma-names = "tx", "rx" 205 dma-names = "tx", "rx";
282 power-domains = <&cpg> 206 power-domains = <&cpg>;
283 #sound-dai-cells = <0> 207 #sound-dai-cells = <0>;
284 status = "disabled"; 208 status = "disabled";
285 }; 209 };
286 210
287 ssi2: ssi@1004a400 { 211 ssi2: ssi@1004a400 {
288 compatible = "renesas, 212 compatible = "renesas,r9a07g044-ssi",
289 "renesas, 213 "renesas,rz-ssi";
290 reg = <0 0x1004a400 0 214 reg = <0 0x1004a400 0 0x400>;
291 interrupts = <GIC_SPI 215 interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
292 <GIC_SPI 216 <GIC_SPI 337 IRQ_TYPE_EDGE_RISING>;
293 interrupt-names = "int 217 interrupt-names = "int_req", "dma_rt";
294 clocks = <&cpg CPG_MOD 218 clocks = <&cpg CPG_MOD R9A07G044_SSI2_PCLK2>,
295 <&cpg CPG_MOD 219 <&cpg CPG_MOD R9A07G044_SSI2_PCLK_SFR>,
296 <&audio_clk1> 220 <&audio_clk1>, <&audio_clk2>;
297 clock-names = "ssi", " 221 clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2";
298 resets = <&cpg R9A07G0 222 resets = <&cpg R9A07G044_SSI2_RST_M2_REG>;
299 dmas = <&dmac 0x265f>; 223 dmas = <&dmac 0x265f>;
300 dma-names = "rt"; 224 dma-names = "rt";
301 power-domains = <&cpg> 225 power-domains = <&cpg>;
302 #sound-dai-cells = <0> 226 #sound-dai-cells = <0>;
303 status = "disabled"; 227 status = "disabled";
304 }; 228 };
305 229
306 ssi3: ssi@1004a800 { 230 ssi3: ssi@1004a800 {
307 compatible = "renesas, 231 compatible = "renesas,r9a07g044-ssi",
308 "renesas, 232 "renesas,rz-ssi";
309 reg = <0 0x1004a800 0 233 reg = <0 0x1004a800 0 0x400>;
310 interrupts = <GIC_SPI 234 interrupts = <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
311 <GIC_SPI 235 <GIC_SPI 339 IRQ_TYPE_EDGE_RISING>,
312 <GIC_SPI 236 <GIC_SPI 340 IRQ_TYPE_EDGE_RISING>;
313 interrupt-names = "int 237 interrupt-names = "int_req", "dma_rx", "dma_tx";
314 clocks = <&cpg CPG_MOD 238 clocks = <&cpg CPG_MOD R9A07G044_SSI3_PCLK2>,
315 <&cpg CPG_MOD 239 <&cpg CPG_MOD R9A07G044_SSI3_PCLK_SFR>,
316 <&audio_clk1> 240 <&audio_clk1>, <&audio_clk2>;
317 clock-names = "ssi", " 241 clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2";
318 resets = <&cpg R9A07G0 242 resets = <&cpg R9A07G044_SSI3_RST_M2_REG>;
319 dmas = <&dmac 0x2661>, 243 dmas = <&dmac 0x2661>, <&dmac 0x2662>;
320 dma-names = "tx", "rx" 244 dma-names = "tx", "rx";
321 power-domains = <&cpg> 245 power-domains = <&cpg>;
322 #sound-dai-cells = <0> 246 #sound-dai-cells = <0>;
323 status = "disabled"; 247 status = "disabled";
324 }; 248 };
325 249
326 spi0: spi@1004ac00 { 250 spi0: spi@1004ac00 {
327 compatible = "renesas, 251 compatible = "renesas,r9a07g044-rspi", "renesas,rspi-rz";
328 reg = <0 0x1004ac00 0 252 reg = <0 0x1004ac00 0 0x400>;
329 interrupts = <GIC_SPI 253 interrupts = <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>,
330 <GIC_SPI 254 <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>,
331 <GIC_SPI 255 <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>;
332 interrupt-names = "err 256 interrupt-names = "error", "rx", "tx";
333 clocks = <&cpg CPG_MOD 257 clocks = <&cpg CPG_MOD R9A07G044_RSPI0_CLKB>;
334 resets = <&cpg R9A07G0 258 resets = <&cpg R9A07G044_RSPI0_RST>;
335 dmas = <&dmac 0x2e95>, 259 dmas = <&dmac 0x2e95>, <&dmac 0x2e96>;
336 dma-names = "tx", "rx" 260 dma-names = "tx", "rx";
337 power-domains = <&cpg> 261 power-domains = <&cpg>;
338 num-cs = <1>; 262 num-cs = <1>;
339 #address-cells = <1>; 263 #address-cells = <1>;
340 #size-cells = <0>; 264 #size-cells = <0>;
341 status = "disabled"; 265 status = "disabled";
342 }; 266 };
343 267
344 spi1: spi@1004b000 { 268 spi1: spi@1004b000 {
345 compatible = "renesas, 269 compatible = "renesas,r9a07g044-rspi", "renesas,rspi-rz";
346 reg = <0 0x1004b000 0 270 reg = <0 0x1004b000 0 0x400>;
347 interrupts = <GIC_SPI 271 interrupts = <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
348 <GIC_SPI 272 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
349 <GIC_SPI 273 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>;
350 interrupt-names = "err 274 interrupt-names = "error", "rx", "tx";
351 clocks = <&cpg CPG_MOD 275 clocks = <&cpg CPG_MOD R9A07G044_RSPI1_CLKB>;
352 resets = <&cpg R9A07G0 276 resets = <&cpg R9A07G044_RSPI1_RST>;
353 dmas = <&dmac 0x2e99>, 277 dmas = <&dmac 0x2e99>, <&dmac 0x2e9a>;
354 dma-names = "tx", "rx" 278 dma-names = "tx", "rx";
355 power-domains = <&cpg> 279 power-domains = <&cpg>;
356 num-cs = <1>; 280 num-cs = <1>;
357 #address-cells = <1>; 281 #address-cells = <1>;
358 #size-cells = <0>; 282 #size-cells = <0>;
359 status = "disabled"; 283 status = "disabled";
360 }; 284 };
361 285
362 spi2: spi@1004b400 { 286 spi2: spi@1004b400 {
363 compatible = "renesas, 287 compatible = "renesas,r9a07g044-rspi", "renesas,rspi-rz";
364 reg = <0 0x1004b400 0 288 reg = <0 0x1004b400 0 0x400>;
365 interrupts = <GIC_SPI 289 interrupts = <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
366 <GIC_SPI 290 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
367 <GIC_SPI 291 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>;
368 interrupt-names = "err 292 interrupt-names = "error", "rx", "tx";
369 clocks = <&cpg CPG_MOD 293 clocks = <&cpg CPG_MOD R9A07G044_RSPI2_CLKB>;
370 resets = <&cpg R9A07G0 294 resets = <&cpg R9A07G044_RSPI2_RST>;
371 dmas = <&dmac 0x2e9d>, 295 dmas = <&dmac 0x2e9d>, <&dmac 0x2e9e>;
372 dma-names = "tx", "rx" 296 dma-names = "tx", "rx";
373 power-domains = <&cpg> 297 power-domains = <&cpg>;
374 num-cs = <1>; 298 num-cs = <1>;
375 #address-cells = <1>; 299 #address-cells = <1>;
376 #size-cells = <0>; 300 #size-cells = <0>;
377 status = "disabled"; 301 status = "disabled";
378 }; 302 };
379 303
380 scif0: serial@1004b800 { 304 scif0: serial@1004b800 {
381 compatible = "renesas, 305 compatible = "renesas,scif-r9a07g044";
382 reg = <0 0x1004b800 0 306 reg = <0 0x1004b800 0 0x400>;
383 interrupts = <GIC_SPI 307 interrupts = <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>,
384 <GIC_SPI 308 <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>,
385 <GIC_SPI 309 <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>,
386 <GIC_SPI 310 <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>,
387 <GIC_SPI 311 <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>,
388 <GIC_SPI 312 <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>;
389 interrupt-names = "eri 313 interrupt-names = "eri", "rxi", "txi",
390 "bri 314 "bri", "dri", "tei";
391 clocks = <&cpg CPG_MOD 315 clocks = <&cpg CPG_MOD R9A07G044_SCIF0_CLK_PCK>;
392 clock-names = "fck"; 316 clock-names = "fck";
393 power-domains = <&cpg> 317 power-domains = <&cpg>;
394 resets = <&cpg R9A07G0 318 resets = <&cpg R9A07G044_SCIF0_RST_SYSTEM_N>;
395 status = "disabled"; 319 status = "disabled";
396 }; 320 };
397 321
398 scif1: serial@1004bc00 { 322 scif1: serial@1004bc00 {
399 compatible = "renesas, 323 compatible = "renesas,scif-r9a07g044";
400 reg = <0 0x1004bc00 0 324 reg = <0 0x1004bc00 0 0x400>;
401 interrupts = <GIC_SPI 325 interrupts = <GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>,
402 <GIC_SPI 326 <GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>,
403 <GIC_SPI 327 <GIC_SPI 388 IRQ_TYPE_LEVEL_HIGH>,
404 <GIC_SPI 328 <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>,
405 <GIC_SPI 329 <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>,
406 <GIC_SPI 330 <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>;
407 interrupt-names = "eri 331 interrupt-names = "eri", "rxi", "txi",
408 "bri 332 "bri", "dri", "tei";
409 clocks = <&cpg CPG_MOD 333 clocks = <&cpg CPG_MOD R9A07G044_SCIF1_CLK_PCK>;
410 clock-names = "fck"; 334 clock-names = "fck";
411 power-domains = <&cpg> 335 power-domains = <&cpg>;
412 resets = <&cpg R9A07G0 336 resets = <&cpg R9A07G044_SCIF1_RST_SYSTEM_N>;
413 status = "disabled"; 337 status = "disabled";
414 }; 338 };
415 339
416 scif2: serial@1004c000 { 340 scif2: serial@1004c000 {
417 compatible = "renesas, 341 compatible = "renesas,scif-r9a07g044";
418 reg = <0 0x1004c000 0 342 reg = <0 0x1004c000 0 0x400>;
419 interrupts = <GIC_SPI 343 interrupts = <GIC_SPI 390 IRQ_TYPE_LEVEL_HIGH>,
420 <GIC_SPI 344 <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH>,
421 <GIC_SPI 345 <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>,
422 <GIC_SPI 346 <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH>,
423 <GIC_SPI 347 <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>,
424 <GIC_SPI 348 <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>;
425 interrupt-names = "eri 349 interrupt-names = "eri", "rxi", "txi",
426 "bri 350 "bri", "dri", "tei";
427 clocks = <&cpg CPG_MOD 351 clocks = <&cpg CPG_MOD R9A07G044_SCIF2_CLK_PCK>;
428 clock-names = "fck"; 352 clock-names = "fck";
429 power-domains = <&cpg> 353 power-domains = <&cpg>;
430 resets = <&cpg R9A07G0 354 resets = <&cpg R9A07G044_SCIF2_RST_SYSTEM_N>;
431 status = "disabled"; 355 status = "disabled";
432 }; 356 };
433 357
434 scif3: serial@1004c400 { 358 scif3: serial@1004c400 {
435 compatible = "renesas, 359 compatible = "renesas,scif-r9a07g044";
436 reg = <0 0x1004c400 0 360 reg = <0 0x1004c400 0 0x400>;
437 interrupts = <GIC_SPI 361 interrupts = <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
438 <GIC_SPI 362 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
439 <GIC_SPI 363 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
440 <GIC_SPI 364 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
441 <GIC_SPI 365 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
442 <GIC_SPI 366 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>;
443 interrupt-names = "eri 367 interrupt-names = "eri", "rxi", "txi",
444 "bri 368 "bri", "dri", "tei";
445 clocks = <&cpg CPG_MOD 369 clocks = <&cpg CPG_MOD R9A07G044_SCIF3_CLK_PCK>;
446 clock-names = "fck"; 370 clock-names = "fck";
447 power-domains = <&cpg> 371 power-domains = <&cpg>;
448 resets = <&cpg R9A07G0 372 resets = <&cpg R9A07G044_SCIF3_RST_SYSTEM_N>;
449 status = "disabled"; 373 status = "disabled";
450 }; 374 };
451 375
452 scif4: serial@1004c800 { 376 scif4: serial@1004c800 {
453 compatible = "renesas, 377 compatible = "renesas,scif-r9a07g044";
454 reg = <0 0x1004c800 0 378 reg = <0 0x1004c800 0 0x400>;
455 interrupts = <GIC_SPI 379 interrupts = <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
456 <GIC_SPI 380 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
457 <GIC_SPI 381 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
458 <GIC_SPI 382 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
459 <GIC_SPI 383 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
460 <GIC_SPI 384 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>;
461 interrupt-names = "eri 385 interrupt-names = "eri", "rxi", "txi",
462 "bri 386 "bri", "dri", "tei";
463 clocks = <&cpg CPG_MOD 387 clocks = <&cpg CPG_MOD R9A07G044_SCIF4_CLK_PCK>;
464 clock-names = "fck"; 388 clock-names = "fck";
465 power-domains = <&cpg> 389 power-domains = <&cpg>;
466 resets = <&cpg R9A07G0 390 resets = <&cpg R9A07G044_SCIF4_RST_SYSTEM_N>;
467 status = "disabled"; 391 status = "disabled";
468 }; 392 };
469 393
470 sci0: serial@1004d000 { 394 sci0: serial@1004d000 {
471 compatible = "renesas, 395 compatible = "renesas,r9a07g044-sci", "renesas,sci";
472 reg = <0 0x1004d000 0 396 reg = <0 0x1004d000 0 0x400>;
473 interrupts = <GIC_SPI 397 interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
474 <GIC_SPI 398 <GIC_SPI 406 IRQ_TYPE_EDGE_RISING>,
475 <GIC_SPI 399 <GIC_SPI 407 IRQ_TYPE_EDGE_RISING>,
476 <GIC_SPI 400 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>;
477 interrupt-names = "eri 401 interrupt-names = "eri", "rxi", "txi", "tei";
478 clocks = <&cpg CPG_MOD 402 clocks = <&cpg CPG_MOD R9A07G044_SCI0_CLKP>;
479 clock-names = "fck"; 403 clock-names = "fck";
480 power-domains = <&cpg> 404 power-domains = <&cpg>;
481 resets = <&cpg R9A07G0 405 resets = <&cpg R9A07G044_SCI0_RST>;
482 status = "disabled"; 406 status = "disabled";
483 }; 407 };
484 408
485 sci1: serial@1004d400 { 409 sci1: serial@1004d400 {
486 compatible = "renesas, 410 compatible = "renesas,r9a07g044-sci", "renesas,sci";
487 reg = <0 0x1004d400 0 411 reg = <0 0x1004d400 0 0x400>;
488 interrupts = <GIC_SPI 412 interrupts = <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
489 <GIC_SPI 413 <GIC_SPI 410 IRQ_TYPE_EDGE_RISING>,
490 <GIC_SPI 414 <GIC_SPI 411 IRQ_TYPE_EDGE_RISING>,
491 <GIC_SPI 415 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>;
492 interrupt-names = "eri 416 interrupt-names = "eri", "rxi", "txi", "tei";
493 clocks = <&cpg CPG_MOD 417 clocks = <&cpg CPG_MOD R9A07G044_SCI1_CLKP>;
494 clock-names = "fck"; 418 clock-names = "fck";
495 power-domains = <&cpg> 419 power-domains = <&cpg>;
496 resets = <&cpg R9A07G0 420 resets = <&cpg R9A07G044_SCI1_RST>;
497 status = "disabled"; 421 status = "disabled";
498 }; 422 };
499 423
500 canfd: can@10050000 { 424 canfd: can@10050000 {
501 compatible = "renesas, 425 compatible = "renesas,r9a07g044-canfd", "renesas,rzg2l-canfd";
502 reg = <0 0x10050000 0 426 reg = <0 0x10050000 0 0x8000>;
503 interrupts = <GIC_SPI 427 interrupts = <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>,
504 <GIC_SPI 428 <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>,
505 <GIC_SPI 429 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
506 <GIC_SPI 430 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
507 <GIC_SPI 431 <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>,
508 <GIC_SPI 432 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
509 <GIC_SPI 433 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
510 <GIC_SPI 434 <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>;
511 interrupt-names = "g_e 435 interrupt-names = "g_err", "g_recc",
512 "ch0 436 "ch0_err", "ch0_rec", "ch0_trx",
513 "ch1 437 "ch1_err", "ch1_rec", "ch1_trx";
514 clocks = <&cpg CPG_MOD 438 clocks = <&cpg CPG_MOD R9A07G044_CANFD_PCLK>,
515 <&cpg CPG_COR 439 <&cpg CPG_CORE R9A07G044_CLK_P0_DIV2>,
516 <&can_clk>; 440 <&can_clk>;
517 clock-names = "fck", " 441 clock-names = "fck", "canfd", "can_clk";
518 assigned-clocks = <&cp 442 assigned-clocks = <&cpg CPG_CORE R9A07G044_CLK_P0_DIV2>;
519 assigned-clock-rates = 443 assigned-clock-rates = <50000000>;
520 resets = <&cpg R9A07G0 444 resets = <&cpg R9A07G044_CANFD_RSTP_N>,
521 <&cpg R9A07G0 445 <&cpg R9A07G044_CANFD_RSTC_N>;
522 reset-names = "rstp_n" 446 reset-names = "rstp_n", "rstc_n";
523 power-domains = <&cpg> 447 power-domains = <&cpg>;
524 status = "disabled"; 448 status = "disabled";
525 449
526 channel0 { 450 channel0 {
527 status = "disa 451 status = "disabled";
528 }; 452 };
529 channel1 { 453 channel1 {
530 status = "disa 454 status = "disabled";
531 }; 455 };
532 }; 456 };
533 457
534 i2c0: i2c@10058000 { 458 i2c0: i2c@10058000 {
535 #address-cells = <1>; 459 #address-cells = <1>;
536 #size-cells = <0>; 460 #size-cells = <0>;
537 compatible = "renesas, 461 compatible = "renesas,riic-r9a07g044", "renesas,riic-rz";
538 reg = <0 0x10058000 0 462 reg = <0 0x10058000 0 0x400>;
539 interrupts = <GIC_SPI 463 interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>,
540 <GIC_SPI 464 <GIC_SPI 348 IRQ_TYPE_EDGE_RISING>,
541 <GIC_SPI 465 <GIC_SPI 349 IRQ_TYPE_EDGE_RISING>,
542 <GIC_SPI 466 <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>,
543 <GIC_SPI 467 <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>,
544 <GIC_SPI 468 <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>,
545 <GIC_SPI 469 <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>,
546 <GIC_SPI 470 <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
547 interrupt-names = "tei 471 interrupt-names = "tei", "ri", "ti", "spi", "sti",
548 "nak 472 "naki", "ali", "tmoi";
549 clocks = <&cpg CPG_MOD 473 clocks = <&cpg CPG_MOD R9A07G044_I2C0_PCLK>;
550 clock-frequency = <100 474 clock-frequency = <100000>;
551 resets = <&cpg R9A07G0 475 resets = <&cpg R9A07G044_I2C0_MRST>;
552 power-domains = <&cpg> 476 power-domains = <&cpg>;
553 status = "disabled"; 477 status = "disabled";
554 }; 478 };
555 479
556 i2c1: i2c@10058400 { 480 i2c1: i2c@10058400 {
557 #address-cells = <1>; 481 #address-cells = <1>;
558 #size-cells = <0>; 482 #size-cells = <0>;
559 compatible = "renesas, 483 compatible = "renesas,riic-r9a07g044", "renesas,riic-rz";
560 reg = <0 0x10058400 0 484 reg = <0 0x10058400 0 0x400>;
561 interrupts = <GIC_SPI 485 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>,
562 <GIC_SPI 486 <GIC_SPI 356 IRQ_TYPE_EDGE_RISING>,
563 <GIC_SPI 487 <GIC_SPI 357 IRQ_TYPE_EDGE_RISING>,
564 <GIC_SPI 488 <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>,
565 <GIC_SPI 489 <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>,
566 <GIC_SPI 490 <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>,
567 <GIC_SPI 491 <GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH>,
568 <GIC_SPI 492 <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>;
569 interrupt-names = "tei 493 interrupt-names = "tei", "ri", "ti", "spi", "sti",
570 "nak 494 "naki", "ali", "tmoi";
571 clocks = <&cpg CPG_MOD 495 clocks = <&cpg CPG_MOD R9A07G044_I2C1_PCLK>;
572 clock-frequency = <100 496 clock-frequency = <100000>;
573 resets = <&cpg R9A07G0 497 resets = <&cpg R9A07G044_I2C1_MRST>;
574 power-domains = <&cpg> 498 power-domains = <&cpg>;
575 status = "disabled"; 499 status = "disabled";
576 }; 500 };
577 501
578 i2c2: i2c@10058800 { 502 i2c2: i2c@10058800 {
579 #address-cells = <1>; 503 #address-cells = <1>;
580 #size-cells = <0>; 504 #size-cells = <0>;
581 compatible = "renesas, 505 compatible = "renesas,riic-r9a07g044", "renesas,riic-rz";
582 reg = <0 0x10058800 0 506 reg = <0 0x10058800 0 0x400>;
583 interrupts = <GIC_SPI 507 interrupts = <GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>,
584 <GIC_SPI 508 <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>,
585 <GIC_SPI 509 <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>,
586 <GIC_SPI 510 <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>,
587 <GIC_SPI 511 <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>,
588 <GIC_SPI 512 <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>,
589 <GIC_SPI 513 <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>,
590 <GIC_SPI 514 <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
591 interrupt-names = "tei 515 interrupt-names = "tei", "ri", "ti", "spi", "sti",
592 "nak 516 "naki", "ali", "tmoi";
593 clocks = <&cpg CPG_MOD 517 clocks = <&cpg CPG_MOD R9A07G044_I2C2_PCLK>;
594 clock-frequency = <100 518 clock-frequency = <100000>;
595 resets = <&cpg R9A07G0 519 resets = <&cpg R9A07G044_I2C2_MRST>;
596 power-domains = <&cpg> 520 power-domains = <&cpg>;
597 status = "disabled"; 521 status = "disabled";
598 }; 522 };
599 523
600 i2c3: i2c@10058c00 { 524 i2c3: i2c@10058c00 {
601 #address-cells = <1>; 525 #address-cells = <1>;
602 #size-cells = <0>; 526 #size-cells = <0>;
603 compatible = "renesas, 527 compatible = "renesas,riic-r9a07g044", "renesas,riic-rz";
604 reg = <0 0x10058c00 0 528 reg = <0 0x10058c00 0 0x400>;
605 interrupts = <GIC_SPI 529 interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>,
606 <GIC_SPI 530 <GIC_SPI 372 IRQ_TYPE_EDGE_RISING>,
607 <GIC_SPI 531 <GIC_SPI 373 IRQ_TYPE_EDGE_RISING>,
608 <GIC_SPI 532 <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>,
609 <GIC_SPI 533 <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>,
610 <GIC_SPI 534 <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>,
611 <GIC_SPI 535 <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>,
612 <GIC_SPI 536 <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
613 interrupt-names = "tei 537 interrupt-names = "tei", "ri", "ti", "spi", "sti",
614 "nak 538 "naki", "ali", "tmoi";
615 clocks = <&cpg CPG_MOD 539 clocks = <&cpg CPG_MOD R9A07G044_I2C3_PCLK>;
616 clock-frequency = <100 540 clock-frequency = <100000>;
617 resets = <&cpg R9A07G0 541 resets = <&cpg R9A07G044_I2C3_MRST>;
618 power-domains = <&cpg> 542 power-domains = <&cpg>;
619 status = "disabled"; 543 status = "disabled";
620 }; 544 };
621 545
622 adc: adc@10059000 { 546 adc: adc@10059000 {
623 compatible = "renesas, 547 compatible = "renesas,r9a07g044-adc", "renesas,rzg2l-adc";
624 reg = <0 0x10059000 0 548 reg = <0 0x10059000 0 0x400>;
625 interrupts = <GIC_SPI 549 interrupts = <GIC_SPI 347 IRQ_TYPE_EDGE_RISING>;
626 clocks = <&cpg CPG_MOD 550 clocks = <&cpg CPG_MOD R9A07G044_ADC_ADCLK>,
627 <&cpg CPG_MOD 551 <&cpg CPG_MOD R9A07G044_ADC_PCLK>;
628 clock-names = "adclk", 552 clock-names = "adclk", "pclk";
629 resets = <&cpg R9A07G0 553 resets = <&cpg R9A07G044_ADC_PRESETN>,
630 <&cpg R9A07G0 554 <&cpg R9A07G044_ADC_ADRST_N>;
631 reset-names = "presetn 555 reset-names = "presetn", "adrst-n";
632 power-domains = <&cpg> 556 power-domains = <&cpg>;
633 status = "disabled"; 557 status = "disabled";
634 558
635 #address-cells = <1>; 559 #address-cells = <1>;
636 #size-cells = <0>; 560 #size-cells = <0>;
637 561
638 channel@0 { 562 channel@0 {
639 reg = <0>; 563 reg = <0>;
640 }; 564 };
641 channel@1 { 565 channel@1 {
642 reg = <1>; 566 reg = <1>;
643 }; 567 };
644 channel@2 { 568 channel@2 {
645 reg = <2>; 569 reg = <2>;
646 }; 570 };
647 channel@3 { 571 channel@3 {
648 reg = <3>; 572 reg = <3>;
649 }; 573 };
650 channel@4 { 574 channel@4 {
651 reg = <4>; 575 reg = <4>;
652 }; 576 };
653 channel@5 { 577 channel@5 {
654 reg = <5>; 578 reg = <5>;
655 }; 579 };
656 channel@6 { 580 channel@6 {
657 reg = <6>; 581 reg = <6>;
658 }; 582 };
659 channel@7 { 583 channel@7 {
660 reg = <7>; 584 reg = <7>;
661 }; 585 };
662 }; 586 };
663 587
664 tsu: thermal@10059400 { 588 tsu: thermal@10059400 {
665 compatible = "renesas, 589 compatible = "renesas,r9a07g044-tsu",
666 "renesas, 590 "renesas,rzg2l-tsu";
667 reg = <0 0x10059400 0 591 reg = <0 0x10059400 0 0x400>;
668 clocks = <&cpg CPG_MOD 592 clocks = <&cpg CPG_MOD R9A07G044_TSU_PCLK>;
669 resets = <&cpg R9A07G0 593 resets = <&cpg R9A07G044_TSU_PRESETN>;
670 power-domains = <&cpg> 594 power-domains = <&cpg>;
671 #thermal-sensor-cells 595 #thermal-sensor-cells = <1>;
672 }; 596 };
673 597
674 sbc: spi@10060000 { 598 sbc: spi@10060000 {
675 compatible = "renesas, 599 compatible = "renesas,r9a07g044-rpc-if",
676 "renesas, 600 "renesas,rzg2l-rpc-if";
677 reg = <0 0x10060000 0 601 reg = <0 0x10060000 0 0x10000>,
678 <0 0x20000000 0 602 <0 0x20000000 0 0x10000000>,
679 <0 0x10070000 0 603 <0 0x10070000 0 0x10000>;
680 reg-names = "regs", "d 604 reg-names = "regs", "dirmap", "wbuf";
681 interrupts = <GIC_SPI 605 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
682 clocks = <&cpg CPG_MOD 606 clocks = <&cpg CPG_MOD R9A07G044_SPI_CLK2>,
683 <&cpg CPG_MOD 607 <&cpg CPG_MOD R9A07G044_SPI_CLK>;
684 resets = <&cpg R9A07G0 608 resets = <&cpg R9A07G044_SPI_RST>;
685 power-domains = <&cpg> 609 power-domains = <&cpg>;
686 #address-cells = <1>; 610 #address-cells = <1>;
687 #size-cells = <0>; 611 #size-cells = <0>;
688 status = "disabled"; 612 status = "disabled";
689 }; 613 };
690 614
691 cru: video@10830000 { <<
692 compatible = "renesas, <<
693 reg = <0 0x10830000 0 <<
694 clocks = <&cpg CPG_MOD <<
695 <&cpg CPG_MOD <<
696 <&cpg CPG_MOD <<
697 clock-names = "video", <<
698 interrupts = <GIC_SPI <<
699 <GIC_SPI <<
700 <GIC_SPI <<
701 interrupt-names = "ima <<
702 resets = <&cpg R9A07G0 <<
703 <&cpg R9A07G0 <<
704 reset-names = "presetn <<
705 power-domains = <&cpg> <<
706 status = "disabled"; <<
707 <<
708 ports { <<
709 #address-cells <<
710 #size-cells = <<
711 <<
712 port@0 { <<
713 #addre <<
714 #size- <<
715 <<
716 reg = <<
717 crupar <<
718 <<
719 }; <<
720 }; <<
721 <<
722 port@1 { <<
723 #addre <<
724 #size- <<
725 <<
726 reg = <<
727 crucsi <<
728 <<
729 <<
730 }; <<
731 }; <<
732 }; <<
733 }; <<
734 <<
735 csi2: csi2@10830400 { <<
736 compatible = "renesas, <<
737 reg = <0 0x10830400 0 <<
738 interrupts = <GIC_SPI <<
739 clocks = <&cpg CPG_MOD <<
740 <&cpg CPG_MOD <<
741 <&cpg CPG_MOD <<
742 clock-names = "system" <<
743 resets = <&cpg R9A07G0 <<
744 <&cpg R9A07G0 <<
745 reset-names = "presetn <<
746 power-domains = <&cpg> <<
747 status = "disabled"; <<
748 <<
749 ports { <<
750 #address-cells <<
751 #size-cells = <<
752 <<
753 port@0 { <<
754 reg = <<
755 }; <<
756 <<
757 port@1 { <<
758 #addre <<
759 #size- <<
760 reg = <<
761 <<
762 csi2cr <<
763 <<
764 <<
765 }; <<
766 }; <<
767 }; <<
768 }; <<
769 <<
770 dsi: dsi@10850000 { <<
771 compatible = "renesas, <<
772 "renesas, <<
773 reg = <0 0x10850000 0 <<
774 interrupts = <GIC_SPI <<
775 <GIC_SPI <<
776 <GIC_SPI <<
777 <GIC_SPI <<
778 <GIC_SPI <<
779 <GIC_SPI <<
780 <GIC_SPI <<
781 interrupt-names = "seq <<
782 "fer <<
783 clocks = <&cpg CPG_MOD <<
784 <&cpg CPG_MOD <<
785 <&cpg CPG_MOD <<
786 <&cpg CPG_MOD <<
787 <&cpg CPG_MOD <<
788 <&cpg CPG_MOD <<
789 clock-names = "pllclk" <<
790 resets = <&cpg R9A07G0 <<
791 <&cpg R9A07G0 <<
792 <&cpg R9A07G0 <<
793 reset-names = "rst", " <<
794 power-domains = <&cpg> <<
795 status = "disabled"; <<
796 <<
797 ports { <<
798 #address-cells <<
799 #size-cells = <<
800 <<
801 port@0 { <<
802 reg = <<
803 dsi0_i <<
804 <<
805 }; <<
806 }; <<
807 <<
808 port@1 { <<
809 reg = <<
810 }; <<
811 }; <<
812 }; <<
813 <<
814 vspd: vsp@10870000 { <<
815 compatible = "renesas, <<
816 reg = <0 0x10870000 0 <<
817 interrupts = <GIC_SPI <<
818 clocks = <&cpg CPG_MOD <<
819 <&cpg CPG_MOD <<
820 <&cpg CPG_MOD <<
821 clock-names = "aclk", <<
822 power-domains = <&cpg> <<
823 resets = <&cpg R9A07G0 <<
824 renesas,fcp = <&fcpvd> <<
825 }; <<
826 <<
827 fcpvd: fcp@10880000 { <<
828 compatible = "renesas, <<
829 "renesas, <<
830 reg = <0 0x10880000 0 <<
831 clocks = <&cpg CPG_MOD <<
832 <&cpg CPG_MOD <<
833 <&cpg CPG_MOD <<
834 clock-names = "aclk", <<
835 power-domains = <&cpg> <<
836 resets = <&cpg R9A07G0 <<
837 }; <<
838 <<
839 du: display@10890000 { <<
840 compatible = "renesas, <<
841 reg = <0 0x10890000 0 <<
842 interrupts = <GIC_SPI <<
843 clocks = <&cpg CPG_MOD <<
844 <&cpg CPG_MOD <<
845 <&cpg CPG_MOD <<
846 clock-names = "aclk", <<
847 power-domains = <&cpg> <<
848 resets = <&cpg R9A07G0 <<
849 renesas,vsps = <&vspd <<
850 status = "disabled"; <<
851 <<
852 ports { <<
853 #address-cells <<
854 #size-cells = <<
855 <<
856 port@0 { <<
857 reg = <<
858 du_out <<
859 <<
860 }; <<
861 }; <<
862 <<
863 port@1 { <<
864 reg = <<
865 }; <<
866 }; <<
867 }; <<
868 <<
869 cpg: clock-controller@11010000 615 cpg: clock-controller@11010000 {
870 compatible = "renesas, 616 compatible = "renesas,r9a07g044-cpg";
871 reg = <0 0x11010000 0 617 reg = <0 0x11010000 0 0x10000>;
872 clocks = <&extal_clk>; 618 clocks = <&extal_clk>;
873 clock-names = "extal"; 619 clock-names = "extal";
874 #clock-cells = <2>; 620 #clock-cells = <2>;
875 #reset-cells = <1>; 621 #reset-cells = <1>;
876 #power-domain-cells = 622 #power-domain-cells = <0>;
877 }; 623 };
878 624
879 sysc: system-controller@110200 625 sysc: system-controller@11020000 {
880 compatible = "renesas, 626 compatible = "renesas,r9a07g044-sysc";
881 reg = <0 0x11020000 0 627 reg = <0 0x11020000 0 0x10000>;
882 interrupts = <GIC_SPI 628 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
883 <GIC_SPI 629 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
884 <GIC_SPI 630 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
885 <GIC_SPI 631 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
886 interrupt-names = "lpm 632 interrupt-names = "lpm_int", "ca55stbydone_int",
887 "cm3 633 "cm33stbyr_int", "ca55_deny";
888 status = "disabled"; 634 status = "disabled";
889 }; 635 };
890 636
891 pinctrl: pinctrl@11030000 { 637 pinctrl: pinctrl@11030000 {
892 compatible = "renesas, 638 compatible = "renesas,r9a07g044-pinctrl";
893 reg = <0 0x11030000 0 639 reg = <0 0x11030000 0 0x10000>;
894 gpio-controller; 640 gpio-controller;
895 #gpio-cells = <2>; 641 #gpio-cells = <2>;
>> 642 #address-cells = <2>;
896 #interrupt-cells = <2> 643 #interrupt-cells = <2>;
897 interrupt-parent = <&i 644 interrupt-parent = <&irqc>;
898 interrupt-controller; 645 interrupt-controller;
899 gpio-ranges = <&pinctr 646 gpio-ranges = <&pinctrl 0 0 392>;
900 clocks = <&cpg CPG_MOD 647 clocks = <&cpg CPG_MOD R9A07G044_GPIO_HCLK>;
901 power-domains = <&cpg> 648 power-domains = <&cpg>;
902 resets = <&cpg R9A07G0 649 resets = <&cpg R9A07G044_GPIO_RSTN>,
903 <&cpg R9A07G0 650 <&cpg R9A07G044_GPIO_PORT_RESETN>,
904 <&cpg R9A07G0 651 <&cpg R9A07G044_GPIO_SPARE_RESETN>;
905 }; 652 };
906 653
907 irqc: interrupt-controller@110 654 irqc: interrupt-controller@110a0000 {
908 compatible = "renesas, 655 compatible = "renesas,r9a07g044-irqc",
909 "renesas, 656 "renesas,rzg2l-irqc";
910 #interrupt-cells = <2> 657 #interrupt-cells = <2>;
911 #address-cells = <0>; 658 #address-cells = <0>;
912 interrupt-controller; 659 interrupt-controller;
913 reg = <0 0x110a0000 0 660 reg = <0 0x110a0000 0 0x10000>;
914 interrupts = <GIC_SPI 661 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
915 <GIC_SPI 662 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
916 <GIC_SPI 663 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
917 <GIC_SPI 664 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
918 <GIC_SPI 665 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
919 <GIC_SPI 666 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
920 <GIC_SPI 667 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
921 <GIC_SPI 668 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
922 <GIC_SPI 669 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
923 <GIC_SPI 670 <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>,
924 <GIC_SPI 671 <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>,
925 <GIC_SPI 672 <GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>,
926 <GIC_SPI 673 <GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>,
927 <GIC_SPI 674 <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>,
928 <GIC_SPI 675 <GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>,
929 <GIC_SPI 676 <GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH>,
930 <GIC_SPI 677 <GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>,
931 <GIC_SPI 678 <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>,
932 <GIC_SPI 679 <GIC_SPI 453 IRQ_TYPE_LEVEL_HIGH>,
933 <GIC_SPI 680 <GIC_SPI 454 IRQ_TYPE_LEVEL_HIGH>,
934 <GIC_SPI 681 <GIC_SPI 455 IRQ_TYPE_LEVEL_HIGH>,
935 <GIC_SPI 682 <GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>,
936 <GIC_SPI 683 <GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>,
937 <GIC_SPI 684 <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>,
938 <GIC_SPI 685 <GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>,
939 <GIC_SPI 686 <GIC_SPI 460 IRQ_TYPE_LEVEL_HIGH>,
940 <GIC_SPI 687 <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>,
941 <GIC_SPI 688 <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>,
942 <GIC_SPI 689 <GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH>,
943 <GIC_SPI 690 <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>,
944 <GIC_SPI 691 <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>,
945 <GIC_SPI 692 <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>,
946 <GIC_SPI 693 <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>,
947 <GIC_SPI 694 <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>,
948 <GIC_SPI 695 <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>,
949 <GIC_SPI 696 <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>,
950 <GIC_SPI 697 <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>,
951 <GIC_SPI 698 <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>,
952 <GIC_SPI 699 <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>,
953 <GIC_SPI 700 <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>,
954 <GIC_SPI 701 <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>,
955 <GIC_SPI 702 <GIC_SPI 25 IRQ_TYPE_EDGE_RISING>,
956 <GIC_SPI 703 <GIC_SPI 34 IRQ_TYPE_EDGE_RISING>,
957 <GIC_SPI 704 <GIC_SPI 35 IRQ_TYPE_EDGE_RISING>,
958 <GIC_SPI 705 <GIC_SPI 36 IRQ_TYPE_EDGE_RISING>,
959 <GIC_SPI 706 <GIC_SPI 37 IRQ_TYPE_EDGE_RISING>,
960 <GIC_SPI 707 <GIC_SPI 38 IRQ_TYPE_EDGE_RISING>,
961 <GIC_SPI 708 <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>;
962 interrupt-names = "nmi 709 interrupt-names = "nmi", "irq0", "irq1", "irq2", "irq3",
963 "irq 710 "irq4", "irq5", "irq6", "irq7",
964 "tin 711 "tint0", "tint1", "tint2", "tint3",
965 "tin 712 "tint4", "tint5", "tint6", "tint7",
966 "tin 713 "tint8", "tint9", "tint10", "tint11",
967 "tin 714 "tint12", "tint13", "tint14", "tint15",
968 "tin 715 "tint16", "tint17", "tint18", "tint19",
969 "tin 716 "tint20", "tint21", "tint22", "tint23",
970 "tin 717 "tint24", "tint25", "tint26", "tint27",
971 "tin 718 "tint28", "tint29", "tint30", "tint31",
972 "bus 719 "bus-err", "ec7tie1-0", "ec7tie2-0",
973 "ec7 720 "ec7tiovf-0", "ec7tie1-1", "ec7tie2-1",
974 "ec7 721 "ec7tiovf-1";
975 clocks = <&cpg CPG_MOD 722 clocks = <&cpg CPG_MOD R9A07G044_IA55_CLK>,
976 <&cpg CPG_MOD 723 <&cpg CPG_MOD R9A07G044_IA55_PCLK>;
977 clock-names = "clk", " 724 clock-names = "clk", "pclk";
978 power-domains = <&cpg> 725 power-domains = <&cpg>;
979 resets = <&cpg R9A07G0 726 resets = <&cpg R9A07G044_IA55_RESETN>;
980 }; 727 };
981 728
982 dmac: dma-controller@11820000 729 dmac: dma-controller@11820000 {
983 compatible = "renesas, 730 compatible = "renesas,r9a07g044-dmac",
984 "renesas, 731 "renesas,rz-dmac";
985 reg = <0 0x11820000 0 732 reg = <0 0x11820000 0 0x10000>,
986 <0 0x11830000 0 733 <0 0x11830000 0 0x10000>;
987 interrupts = <GIC_SPI 734 interrupts = <GIC_SPI 141 IRQ_TYPE_EDGE_RISING>,
988 <GIC_SPI 735 <GIC_SPI 125 IRQ_TYPE_EDGE_RISING>,
989 <GIC_SPI 736 <GIC_SPI 126 IRQ_TYPE_EDGE_RISING>,
990 <GIC_SPI 737 <GIC_SPI 127 IRQ_TYPE_EDGE_RISING>,
991 <GIC_SPI 738 <GIC_SPI 128 IRQ_TYPE_EDGE_RISING>,
992 <GIC_SPI 739 <GIC_SPI 129 IRQ_TYPE_EDGE_RISING>,
993 <GIC_SPI 740 <GIC_SPI 130 IRQ_TYPE_EDGE_RISING>,
994 <GIC_SPI 741 <GIC_SPI 131 IRQ_TYPE_EDGE_RISING>,
995 <GIC_SPI 742 <GIC_SPI 132 IRQ_TYPE_EDGE_RISING>,
996 <GIC_SPI 743 <GIC_SPI 133 IRQ_TYPE_EDGE_RISING>,
997 <GIC_SPI 744 <GIC_SPI 134 IRQ_TYPE_EDGE_RISING>,
998 <GIC_SPI 745 <GIC_SPI 135 IRQ_TYPE_EDGE_RISING>,
999 <GIC_SPI 746 <GIC_SPI 136 IRQ_TYPE_EDGE_RISING>,
1000 <GIC_SPI 747 <GIC_SPI 137 IRQ_TYPE_EDGE_RISING>,
1001 <GIC_SPI 748 <GIC_SPI 138 IRQ_TYPE_EDGE_RISING>,
1002 <GIC_SPI 749 <GIC_SPI 139 IRQ_TYPE_EDGE_RISING>,
1003 <GIC_SPI 750 <GIC_SPI 140 IRQ_TYPE_EDGE_RISING>;
1004 interrupt-names = "er 751 interrupt-names = "error",
1005 "ch 752 "ch0", "ch1", "ch2", "ch3",
1006 "ch 753 "ch4", "ch5", "ch6", "ch7",
1007 "ch 754 "ch8", "ch9", "ch10", "ch11",
1008 "ch 755 "ch12", "ch13", "ch14", "ch15";
1009 clocks = <&cpg CPG_MO 756 clocks = <&cpg CPG_MOD R9A07G044_DMAC_ACLK>,
1010 <&cpg CPG_MO 757 <&cpg CPG_MOD R9A07G044_DMAC_PCLK>;
1011 clock-names = "main", <<
1012 power-domains = <&cpg 758 power-domains = <&cpg>;
1013 resets = <&cpg R9A07G 759 resets = <&cpg R9A07G044_DMAC_ARESETN>,
1014 <&cpg R9A07G 760 <&cpg R9A07G044_DMAC_RST_ASYNC>;
1015 reset-names = "arst", <<
1016 #dma-cells = <1>; 761 #dma-cells = <1>;
1017 dma-channels = <16>; 762 dma-channels = <16>;
1018 }; 763 };
1019 764
1020 gpu: gpu@11840000 { 765 gpu: gpu@11840000 {
1021 compatible = "renesas 766 compatible = "renesas,r9a07g044-mali",
1022 "arm,mal 767 "arm,mali-bifrost";
1023 reg = <0x0 0x11840000 768 reg = <0x0 0x11840000 0x0 0x10000>;
1024 interrupts = <GIC_SPI 769 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
1025 <GIC_SPI 770 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
1026 <GIC_SPI 771 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
1027 <GIC_SPI 772 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
1028 interrupt-names = "jo 773 interrupt-names = "job", "mmu", "gpu", "event";
1029 clocks = <&cpg CPG_MO 774 clocks = <&cpg CPG_MOD R9A07G044_GPU_CLK>,
1030 <&cpg CPG_MO 775 <&cpg CPG_MOD R9A07G044_GPU_AXI_CLK>,
1031 <&cpg CPG_MO 776 <&cpg CPG_MOD R9A07G044_GPU_ACE_CLK>;
1032 clock-names = "gpu", 777 clock-names = "gpu", "bus", "bus_ace";
1033 power-domains = <&cpg 778 power-domains = <&cpg>;
1034 resets = <&cpg R9A07G 779 resets = <&cpg R9A07G044_GPU_RESETN>,
1035 <&cpg R9A07G 780 <&cpg R9A07G044_GPU_AXI_RESETN>,
1036 <&cpg R9A07G 781 <&cpg R9A07G044_GPU_ACE_RESETN>;
1037 reset-names = "rst", 782 reset-names = "rst", "axi_rst", "ace_rst";
1038 operating-points-v2 = 783 operating-points-v2 = <&gpu_opp_table>;
1039 }; 784 };
1040 785
1041 gic: interrupt-controller@119 786 gic: interrupt-controller@11900000 {
1042 compatible = "arm,gic 787 compatible = "arm,gic-v3";
1043 #interrupt-cells = <3 788 #interrupt-cells = <3>;
1044 #address-cells = <0>; 789 #address-cells = <0>;
1045 interrupt-controller; 790 interrupt-controller;
1046 reg = <0x0 0x11900000 791 reg = <0x0 0x11900000 0 0x20000>,
1047 <0x0 0x11940000 792 <0x0 0x11940000 0 0x40000>;
1048 interrupts = <GIC_PPI 793 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
1049 }; 794 };
1050 795
1051 sdhi0: mmc@11c00000 { 796 sdhi0: mmc@11c00000 {
1052 compatible = "renesas 797 compatible = "renesas,sdhi-r9a07g044",
1053 "renesas !! 798 "renesas,rcar-gen3-sdhi";
1054 reg = <0x0 0x11c00000 799 reg = <0x0 0x11c00000 0 0x10000>;
1055 interrupts = <GIC_SPI 800 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
1056 <GIC_SPI 801 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
1057 clocks = <&cpg CPG_MO 802 clocks = <&cpg CPG_MOD R9A07G044_SDHI0_IMCLK>,
1058 <&cpg CPG_MO 803 <&cpg CPG_MOD R9A07G044_SDHI0_CLK_HS>,
1059 <&cpg CPG_MO 804 <&cpg CPG_MOD R9A07G044_SDHI0_IMCLK2>,
1060 <&cpg CPG_MO 805 <&cpg CPG_MOD R9A07G044_SDHI0_ACLK>;
1061 clock-names = "core", 806 clock-names = "core", "clkh", "cd", "aclk";
1062 resets = <&cpg R9A07G 807 resets = <&cpg R9A07G044_SDHI0_IXRST>;
1063 power-domains = <&cpg 808 power-domains = <&cpg>;
1064 status = "disabled"; 809 status = "disabled";
1065 }; 810 };
1066 811
1067 sdhi1: mmc@11c10000 { 812 sdhi1: mmc@11c10000 {
1068 compatible = "renesas 813 compatible = "renesas,sdhi-r9a07g044",
1069 "renesas !! 814 "renesas,rcar-gen3-sdhi";
1070 reg = <0x0 0x11c10000 815 reg = <0x0 0x11c10000 0 0x10000>;
1071 interrupts = <GIC_SPI 816 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
1072 <GIC_SPI 817 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
1073 clocks = <&cpg CPG_MO 818 clocks = <&cpg CPG_MOD R9A07G044_SDHI1_IMCLK>,
1074 <&cpg CPG_MO 819 <&cpg CPG_MOD R9A07G044_SDHI1_CLK_HS>,
1075 <&cpg CPG_MO 820 <&cpg CPG_MOD R9A07G044_SDHI1_IMCLK2>,
1076 <&cpg CPG_MO 821 <&cpg CPG_MOD R9A07G044_SDHI1_ACLK>;
1077 clock-names = "core", 822 clock-names = "core", "clkh", "cd", "aclk";
1078 resets = <&cpg R9A07G 823 resets = <&cpg R9A07G044_SDHI1_IXRST>;
1079 power-domains = <&cpg 824 power-domains = <&cpg>;
1080 status = "disabled"; 825 status = "disabled";
1081 }; 826 };
1082 827
1083 eth0: ethernet@11c20000 { 828 eth0: ethernet@11c20000 {
1084 compatible = "renesas 829 compatible = "renesas,r9a07g044-gbeth",
1085 "renesas 830 "renesas,rzg2l-gbeth";
1086 reg = <0 0x11c20000 0 831 reg = <0 0x11c20000 0 0x10000>;
1087 interrupts = <GIC_SPI 832 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
1088 <GIC_SPI 833 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
1089 <GIC_SPI 834 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
1090 interrupt-names = "mu 835 interrupt-names = "mux", "fil", "arp_ns";
1091 phy-mode = "rgmii"; 836 phy-mode = "rgmii";
1092 clocks = <&cpg CPG_MO 837 clocks = <&cpg CPG_MOD R9A07G044_ETH0_CLK_AXI>,
1093 <&cpg CPG_MO 838 <&cpg CPG_MOD R9A07G044_ETH0_CLK_CHI>,
1094 <&cpg CPG_CO 839 <&cpg CPG_CORE R9A07G044_CLK_HP>;
1095 clock-names = "axi", 840 clock-names = "axi", "chi", "refclk";
1096 resets = <&cpg R9A07G 841 resets = <&cpg R9A07G044_ETH0_RST_HW_N>;
1097 power-domains = <&cpg 842 power-domains = <&cpg>;
1098 #address-cells = <1>; 843 #address-cells = <1>;
1099 #size-cells = <0>; 844 #size-cells = <0>;
1100 status = "disabled"; 845 status = "disabled";
1101 }; 846 };
1102 847
1103 eth1: ethernet@11c30000 { 848 eth1: ethernet@11c30000 {
1104 compatible = "renesas 849 compatible = "renesas,r9a07g044-gbeth",
1105 "renesas 850 "renesas,rzg2l-gbeth";
1106 reg = <0 0x11c30000 0 851 reg = <0 0x11c30000 0 0x10000>;
1107 interrupts = <GIC_SPI 852 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
1108 <GIC_SPI 853 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
1109 <GIC_SPI 854 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
1110 interrupt-names = "mu 855 interrupt-names = "mux", "fil", "arp_ns";
1111 phy-mode = "rgmii"; 856 phy-mode = "rgmii";
1112 clocks = <&cpg CPG_MO 857 clocks = <&cpg CPG_MOD R9A07G044_ETH1_CLK_AXI>,
1113 <&cpg CPG_MO 858 <&cpg CPG_MOD R9A07G044_ETH1_CLK_CHI>,
1114 <&cpg CPG_CO 859 <&cpg CPG_CORE R9A07G044_CLK_HP>;
1115 clock-names = "axi", 860 clock-names = "axi", "chi", "refclk";
1116 resets = <&cpg R9A07G 861 resets = <&cpg R9A07G044_ETH1_RST_HW_N>;
1117 power-domains = <&cpg 862 power-domains = <&cpg>;
1118 #address-cells = <1>; 863 #address-cells = <1>;
1119 #size-cells = <0>; 864 #size-cells = <0>;
1120 status = "disabled"; 865 status = "disabled";
1121 }; 866 };
1122 867
1123 phyrst: usbphy-ctrl@11c40000 868 phyrst: usbphy-ctrl@11c40000 {
1124 compatible = "renesas 869 compatible = "renesas,r9a07g044-usbphy-ctrl",
1125 "renesas 870 "renesas,rzg2l-usbphy-ctrl";
1126 reg = <0 0x11c40000 0 871 reg = <0 0x11c40000 0 0x10000>;
1127 clocks = <&cpg CPG_MO 872 clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>;
1128 resets = <&cpg R9A07G 873 resets = <&cpg R9A07G044_USB_PRESETN>;
1129 power-domains = <&cpg 874 power-domains = <&cpg>;
1130 #reset-cells = <1>; 875 #reset-cells = <1>;
1131 status = "disabled"; 876 status = "disabled";
1132 <<
1133 usb0_vbus_otg: regula <<
1134 regulator-nam <<
1135 }; <<
1136 }; 877 };
1137 878
1138 ohci0: usb@11c50000 { 879 ohci0: usb@11c50000 {
1139 compatible = "generic 880 compatible = "generic-ohci";
1140 reg = <0 0x11c50000 0 881 reg = <0 0x11c50000 0 0x100>;
1141 interrupts = <GIC_SPI 882 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
1142 clocks = <&cpg CPG_MO 883 clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>,
1143 <&cpg CPG_MO 884 <&cpg CPG_MOD R9A07G044_USB_U2H0_HCLK>;
1144 resets = <&phyrst 0>, 885 resets = <&phyrst 0>,
1145 <&cpg R9A07G 886 <&cpg R9A07G044_USB_U2H0_HRESETN>;
1146 phys = <&usb2_phy0 1> 887 phys = <&usb2_phy0 1>;
1147 phy-names = "usb"; 888 phy-names = "usb";
1148 power-domains = <&cpg 889 power-domains = <&cpg>;
1149 status = "disabled"; 890 status = "disabled";
1150 }; 891 };
1151 892
1152 ohci1: usb@11c70000 { 893 ohci1: usb@11c70000 {
1153 compatible = "generic 894 compatible = "generic-ohci";
1154 reg = <0 0x11c70000 0 895 reg = <0 0x11c70000 0 0x100>;
1155 interrupts = <GIC_SPI 896 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
1156 clocks = <&cpg CPG_MO 897 clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>,
1157 <&cpg CPG_MO 898 <&cpg CPG_MOD R9A07G044_USB_U2H1_HCLK>;
1158 resets = <&phyrst 1>, 899 resets = <&phyrst 1>,
1159 <&cpg R9A07G 900 <&cpg R9A07G044_USB_U2H1_HRESETN>;
1160 phys = <&usb2_phy1 1> 901 phys = <&usb2_phy1 1>;
1161 phy-names = "usb"; 902 phy-names = "usb";
1162 power-domains = <&cpg 903 power-domains = <&cpg>;
1163 status = "disabled"; 904 status = "disabled";
1164 }; 905 };
1165 906
1166 ehci0: usb@11c50100 { 907 ehci0: usb@11c50100 {
1167 compatible = "generic 908 compatible = "generic-ehci";
1168 reg = <0 0x11c50100 0 909 reg = <0 0x11c50100 0 0x100>;
1169 interrupts = <GIC_SPI 910 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
1170 clocks = <&cpg CPG_MO 911 clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>,
1171 <&cpg CPG_MO 912 <&cpg CPG_MOD R9A07G044_USB_U2H0_HCLK>;
1172 resets = <&phyrst 0>, 913 resets = <&phyrst 0>,
1173 <&cpg R9A07G 914 <&cpg R9A07G044_USB_U2H0_HRESETN>;
1174 phys = <&usb2_phy0 2> 915 phys = <&usb2_phy0 2>;
1175 phy-names = "usb"; 916 phy-names = "usb";
1176 companion = <&ohci0>; 917 companion = <&ohci0>;
1177 power-domains = <&cpg 918 power-domains = <&cpg>;
1178 status = "disabled"; 919 status = "disabled";
1179 }; 920 };
1180 921
1181 ehci1: usb@11c70100 { 922 ehci1: usb@11c70100 {
1182 compatible = "generic 923 compatible = "generic-ehci";
1183 reg = <0 0x11c70100 0 924 reg = <0 0x11c70100 0 0x100>;
1184 interrupts = <GIC_SPI 925 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
1185 clocks = <&cpg CPG_MO 926 clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>,
1186 <&cpg CPG_MO 927 <&cpg CPG_MOD R9A07G044_USB_U2H1_HCLK>;
1187 resets = <&phyrst 1>, 928 resets = <&phyrst 1>,
1188 <&cpg R9A07G 929 <&cpg R9A07G044_USB_U2H1_HRESETN>;
1189 phys = <&usb2_phy1 2> 930 phys = <&usb2_phy1 2>;
1190 phy-names = "usb"; 931 phy-names = "usb";
1191 companion = <&ohci1>; 932 companion = <&ohci1>;
1192 power-domains = <&cpg 933 power-domains = <&cpg>;
1193 status = "disabled"; 934 status = "disabled";
1194 }; 935 };
1195 936
1196 usb2_phy0: usb-phy@11c50200 { 937 usb2_phy0: usb-phy@11c50200 {
1197 compatible = "renesas 938 compatible = "renesas,usb2-phy-r9a07g044",
1198 "renesas 939 "renesas,rzg2l-usb2-phy";
1199 reg = <0 0x11c50200 0 940 reg = <0 0x11c50200 0 0x700>;
1200 interrupts = <GIC_SPI 941 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
1201 clocks = <&cpg CPG_MO 942 clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>,
1202 <&cpg CPG_MO 943 <&cpg CPG_MOD R9A07G044_USB_U2H0_HCLK>;
1203 resets = <&phyrst 0>; 944 resets = <&phyrst 0>;
1204 #phy-cells = <1>; 945 #phy-cells = <1>;
1205 power-domains = <&cpg 946 power-domains = <&cpg>;
1206 status = "disabled"; 947 status = "disabled";
1207 }; 948 };
1208 949
1209 usb2_phy1: usb-phy@11c70200 { 950 usb2_phy1: usb-phy@11c70200 {
1210 compatible = "renesas 951 compatible = "renesas,usb2-phy-r9a07g044",
1211 "renesas 952 "renesas,rzg2l-usb2-phy";
1212 reg = <0 0x11c70200 0 953 reg = <0 0x11c70200 0 0x700>;
1213 interrupts = <GIC_SPI 954 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
1214 clocks = <&cpg CPG_MO 955 clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>,
1215 <&cpg CPG_MO 956 <&cpg CPG_MOD R9A07G044_USB_U2H1_HCLK>;
1216 resets = <&phyrst 1>; 957 resets = <&phyrst 1>;
1217 #phy-cells = <1>; 958 #phy-cells = <1>;
1218 power-domains = <&cpg 959 power-domains = <&cpg>;
1219 status = "disabled"; 960 status = "disabled";
1220 }; 961 };
1221 962
1222 hsusb: usb@11c60000 { 963 hsusb: usb@11c60000 {
1223 compatible = "renesas 964 compatible = "renesas,usbhs-r9a07g044",
1224 "renesas !! 965 "renesas,rza2-usbhs";
1225 reg = <0 0x11c60000 0 966 reg = <0 0x11c60000 0 0x10000>;
1226 interrupts = <GIC_SPI 967 interrupts = <GIC_SPI 100 IRQ_TYPE_EDGE_RISING>,
1227 <GIC_SPI 968 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
1228 <GIC_SPI 969 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
1229 <GIC_SPI 970 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
1230 clocks = <&cpg CPG_MO 971 clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>,
1231 <&cpg CPG_MO 972 <&cpg CPG_MOD R9A07G044_USB_U2P_EXR_CPUCLK>;
1232 resets = <&phyrst 0>, 973 resets = <&phyrst 0>,
1233 <&cpg R9A07G 974 <&cpg R9A07G044_USB_U2P_EXL_SYSRST>;
1234 renesas,buswait = <7> 975 renesas,buswait = <7>;
1235 phys = <&usb2_phy0 3> 976 phys = <&usb2_phy0 3>;
1236 phy-names = "usb"; 977 phy-names = "usb";
1237 power-domains = <&cpg 978 power-domains = <&cpg>;
1238 status = "disabled"; 979 status = "disabled";
1239 }; 980 };
1240 981
1241 wdt0: watchdog@12800800 { 982 wdt0: watchdog@12800800 {
1242 compatible = "renesas 983 compatible = "renesas,r9a07g044-wdt",
1243 "renesas 984 "renesas,rzg2l-wdt";
1244 reg = <0 0x12800800 0 985 reg = <0 0x12800800 0 0x400>;
1245 clocks = <&cpg CPG_MO 986 clocks = <&cpg CPG_MOD R9A07G044_WDT0_PCLK>,
1246 <&cpg CPG_MO 987 <&cpg CPG_MOD R9A07G044_WDT0_CLK>;
1247 clock-names = "pclk", 988 clock-names = "pclk", "oscclk";
1248 interrupts = <GIC_SPI 989 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
1249 <GIC_SPI 990 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
1250 interrupt-names = "wd 991 interrupt-names = "wdt", "perrout";
1251 resets = <&cpg R9A07G 992 resets = <&cpg R9A07G044_WDT0_PRESETN>;
1252 power-domains = <&cpg 993 power-domains = <&cpg>;
1253 status = "disabled"; 994 status = "disabled";
1254 }; 995 };
1255 996
1256 wdt1: watchdog@12800c00 { 997 wdt1: watchdog@12800c00 {
1257 compatible = "renesas 998 compatible = "renesas,r9a07g044-wdt",
1258 "renesas 999 "renesas,rzg2l-wdt";
1259 reg = <0 0x12800C00 0 1000 reg = <0 0x12800C00 0 0x400>;
1260 clocks = <&cpg CPG_MO 1001 clocks = <&cpg CPG_MOD R9A07G044_WDT1_PCLK>,
1261 <&cpg CPG_MO 1002 <&cpg CPG_MOD R9A07G044_WDT1_CLK>;
1262 clock-names = "pclk", 1003 clock-names = "pclk", "oscclk";
1263 interrupts = <GIC_SPI 1004 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
1264 <GIC_SPI 1005 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
1265 interrupt-names = "wd 1006 interrupt-names = "wdt", "perrout";
1266 resets = <&cpg R9A07G 1007 resets = <&cpg R9A07G044_WDT1_PRESETN>;
>> 1008 power-domains = <&cpg>;
>> 1009 status = "disabled";
>> 1010 };
>> 1011
>> 1012 wdt2: watchdog@12800400 {
>> 1013 compatible = "renesas,r9a07g044-wdt",
>> 1014 "renesas,rzg2l-wdt";
>> 1015 reg = <0 0x12800400 0 0x400>;
>> 1016 clocks = <&cpg CPG_MOD R9A07G044_WDT2_PCLK>,
>> 1017 <&cpg CPG_MOD R9A07G044_WDT2_CLK>;
>> 1018 clock-names = "pclk", "oscclk";
>> 1019 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
>> 1020 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
>> 1021 interrupt-names = "wdt", "perrout";
>> 1022 resets = <&cpg R9A07G044_WDT2_PRESETN>;
1267 power-domains = <&cpg 1023 power-domains = <&cpg>;
1268 status = "disabled"; 1024 status = "disabled";
1269 }; 1025 };
1270 1026
1271 ostm0: timer@12801000 { 1027 ostm0: timer@12801000 {
1272 compatible = "renesas 1028 compatible = "renesas,r9a07g044-ostm",
1273 "renesas 1029 "renesas,ostm";
1274 reg = <0x0 0x12801000 1030 reg = <0x0 0x12801000 0x0 0x400>;
1275 interrupts = <GIC_SPI 1031 interrupts = <GIC_SPI 46 IRQ_TYPE_EDGE_RISING>;
1276 clocks = <&cpg CPG_MO 1032 clocks = <&cpg CPG_MOD R9A07G044_OSTM0_PCLK>;
1277 resets = <&cpg R9A07G 1033 resets = <&cpg R9A07G044_OSTM0_PRESETZ>;
1278 power-domains = <&cpg 1034 power-domains = <&cpg>;
1279 status = "disabled"; 1035 status = "disabled";
1280 }; 1036 };
1281 1037
1282 ostm1: timer@12801400 { 1038 ostm1: timer@12801400 {
1283 compatible = "renesas 1039 compatible = "renesas,r9a07g044-ostm",
1284 "renesas 1040 "renesas,ostm";
1285 reg = <0x0 0x12801400 1041 reg = <0x0 0x12801400 0x0 0x400>;
1286 interrupts = <GIC_SPI 1042 interrupts = <GIC_SPI 47 IRQ_TYPE_EDGE_RISING>;
1287 clocks = <&cpg CPG_MO 1043 clocks = <&cpg CPG_MOD R9A07G044_OSTM1_PCLK>;
1288 resets = <&cpg R9A07G 1044 resets = <&cpg R9A07G044_OSTM1_PRESETZ>;
1289 power-domains = <&cpg 1045 power-domains = <&cpg>;
1290 status = "disabled"; 1046 status = "disabled";
1291 }; 1047 };
1292 1048
1293 ostm2: timer@12801800 { 1049 ostm2: timer@12801800 {
1294 compatible = "renesas 1050 compatible = "renesas,r9a07g044-ostm",
1295 "renesas 1051 "renesas,ostm";
1296 reg = <0x0 0x12801800 1052 reg = <0x0 0x12801800 0x0 0x400>;
1297 interrupts = <GIC_SPI 1053 interrupts = <GIC_SPI 48 IRQ_TYPE_EDGE_RISING>;
1298 clocks = <&cpg CPG_MO 1054 clocks = <&cpg CPG_MOD R9A07G044_OSTM2_PCLK>;
1299 resets = <&cpg R9A07G 1055 resets = <&cpg R9A07G044_OSTM2_PRESETZ>;
1300 power-domains = <&cpg 1056 power-domains = <&cpg>;
1301 status = "disabled"; 1057 status = "disabled";
1302 }; 1058 };
1303 }; 1059 };
1304 1060
1305 thermal-zones { 1061 thermal-zones {
1306 cpu-thermal { 1062 cpu-thermal {
1307 polling-delay-passive 1063 polling-delay-passive = <250>;
1308 polling-delay = <1000 1064 polling-delay = <1000>;
1309 thermal-sensors = <&t 1065 thermal-sensors = <&tsu 0>;
1310 sustainable-power = < 1066 sustainable-power = <717>;
1311 1067
1312 cooling-maps { 1068 cooling-maps {
1313 map0 { 1069 map0 {
1314 trip 1070 trip = <&target>;
1315 cooli 1071 cooling-device = <&cpu0 0 2>;
1316 contr 1072 contribution = <1024>;
1317 }; 1073 };
1318 }; 1074 };
1319 1075
1320 trips { 1076 trips {
1321 sensor_crit: 1077 sensor_crit: sensor-crit {
1322 tempe 1078 temperature = <125000>;
1323 hyste 1079 hysteresis = <1000>;
1324 type 1080 type = "critical";
1325 }; 1081 };
1326 1082
1327 target: trip- 1083 target: trip-point {
1328 tempe 1084 temperature = <100000>;
1329 hyste 1085 hysteresis = <1000>;
1330 type 1086 type = "passive";
1331 }; 1087 };
1332 }; 1088 };
1333 }; 1089 };
1334 }; 1090 };
1335 1091
1336 timer { 1092 timer {
1337 compatible = "arm,armv8-timer 1093 compatible = "arm,armv8-timer";
1338 interrupts-extended = <&gic G 1094 interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
1339 <&gic G 1095 <&gic GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
1340 <&gic G 1096 <&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
1341 <&gic G 1097 <&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>,
1342 <&gic G 1098 <&gic GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>;
1343 interrupt-names = "sec-phys", 1099 interrupt-names = "sec-phys", "phys", "virt", "hyp-phys",
1344 "hyp-virt"; 1100 "hyp-virt";
1345 }; 1101 };
1346 }; 1102 };
Linux® is a registered trademark of Linus Torvalds in the United States and other countries.
TOMOYO® is a registered trademark of NTT DATA CORPORATION.