1 // SPDX-License-Identifier: (GPL-2.0-only OR B 1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 /* 2 /*
3 * Device Tree Source for the RZ/G2L and RZ/G2 3 * Device Tree Source for the RZ/G2L and RZ/G2LC common SoC parts
4 * 4 *
5 * Copyright (C) 2021 Renesas Electronics Corp 5 * Copyright (C) 2021 Renesas Electronics Corp.
6 */ 6 */
7 7
8 #include <dt-bindings/interrupt-controller/arm 8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/clock/r9a07g044-cpg.h> 9 #include <dt-bindings/clock/r9a07g044-cpg.h>
10 10
11 / { 11 / {
12 compatible = "renesas,r9a07g044"; 12 compatible = "renesas,r9a07g044";
13 #address-cells = <2>; 13 #address-cells = <2>;
14 #size-cells = <2>; 14 #size-cells = <2>;
15 15
16 audio_clk1: audio1-clk { 16 audio_clk1: audio1-clk {
17 compatible = "fixed-clock"; 17 compatible = "fixed-clock";
18 #clock-cells = <0>; 18 #clock-cells = <0>;
19 /* This value must be overridd 19 /* This value must be overridden by boards that provide it */
20 clock-frequency = <0>; 20 clock-frequency = <0>;
21 }; 21 };
22 22
23 audio_clk2: audio2-clk { 23 audio_clk2: audio2-clk {
24 compatible = "fixed-clock"; 24 compatible = "fixed-clock";
25 #clock-cells = <0>; 25 #clock-cells = <0>;
26 /* This value must be overridd 26 /* This value must be overridden by boards that provide it */
27 clock-frequency = <0>; 27 clock-frequency = <0>;
28 }; 28 };
29 29
30 /* External CAN clock - to be overridd 30 /* External CAN clock - to be overridden by boards that provide it */
31 can_clk: can-clk { 31 can_clk: can-clk {
32 compatible = "fixed-clock"; 32 compatible = "fixed-clock";
33 #clock-cells = <0>; 33 #clock-cells = <0>;
34 clock-frequency = <0>; 34 clock-frequency = <0>;
35 }; 35 };
36 36
37 /* clock can be either from exclk or c 37 /* clock can be either from exclk or crystal oscillator (XIN/XOUT) */
38 extal_clk: extal-clk { 38 extal_clk: extal-clk {
39 compatible = "fixed-clock"; 39 compatible = "fixed-clock";
40 #clock-cells = <0>; 40 #clock-cells = <0>;
41 /* This value must be overridd 41 /* This value must be overridden by the board */
42 clock-frequency = <0>; 42 clock-frequency = <0>;
43 }; 43 };
44 44
45 cluster0_opp: opp-table-0 { 45 cluster0_opp: opp-table-0 {
46 compatible = "operating-points 46 compatible = "operating-points-v2";
47 opp-shared; 47 opp-shared;
48 48
49 opp-150000000 { 49 opp-150000000 {
50 opp-hz = /bits/ 64 <15 50 opp-hz = /bits/ 64 <150000000>;
51 opp-microvolt = <11000 51 opp-microvolt = <1100000>;
52 clock-latency-ns = <30 52 clock-latency-ns = <300000>;
53 }; 53 };
54 opp-300000000 { 54 opp-300000000 {
55 opp-hz = /bits/ 64 <30 55 opp-hz = /bits/ 64 <300000000>;
56 opp-microvolt = <11000 56 opp-microvolt = <1100000>;
57 clock-latency-ns = <30 57 clock-latency-ns = <300000>;
58 }; 58 };
59 opp-600000000 { 59 opp-600000000 {
60 opp-hz = /bits/ 64 <60 60 opp-hz = /bits/ 64 <600000000>;
61 opp-microvolt = <11000 61 opp-microvolt = <1100000>;
62 clock-latency-ns = <30 62 clock-latency-ns = <300000>;
63 }; 63 };
64 opp-1200000000 { 64 opp-1200000000 {
65 opp-hz = /bits/ 64 <12 65 opp-hz = /bits/ 64 <1200000000>;
66 opp-microvolt = <11000 66 opp-microvolt = <1100000>;
67 clock-latency-ns = <30 67 clock-latency-ns = <300000>;
68 opp-suspend; 68 opp-suspend;
69 }; 69 };
70 }; 70 };
71 71
72 cpus { 72 cpus {
73 #address-cells = <1>; 73 #address-cells = <1>;
74 #size-cells = <0>; 74 #size-cells = <0>;
75 75
76 cpu-map { 76 cpu-map {
77 cluster0 { 77 cluster0 {
78 core0 { 78 core0 {
79 cpu = 79 cpu = <&cpu0>;
80 }; 80 };
81 core1 { 81 core1 {
82 cpu = 82 cpu = <&cpu1>;
83 }; 83 };
84 }; 84 };
85 }; 85 };
86 86
87 cpu0: cpu@0 { 87 cpu0: cpu@0 {
88 compatible = "arm,cort 88 compatible = "arm,cortex-a55";
89 reg = <0>; 89 reg = <0>;
90 device_type = "cpu"; 90 device_type = "cpu";
91 #cooling-cells = <2>; 91 #cooling-cells = <2>;
92 next-level-cache = <&L 92 next-level-cache = <&L3_CA55>;
93 enable-method = "psci" 93 enable-method = "psci";
94 clocks = <&cpg CPG_COR 94 clocks = <&cpg CPG_CORE R9A07G044_CLK_I>;
95 operating-points-v2 = 95 operating-points-v2 = <&cluster0_opp>;
96 }; 96 };
97 97
98 cpu1: cpu@100 { 98 cpu1: cpu@100 {
99 compatible = "arm,cort 99 compatible = "arm,cortex-a55";
100 reg = <0x100>; 100 reg = <0x100>;
101 device_type = "cpu"; 101 device_type = "cpu";
102 next-level-cache = <&L 102 next-level-cache = <&L3_CA55>;
103 enable-method = "psci" 103 enable-method = "psci";
104 clocks = <&cpg CPG_COR 104 clocks = <&cpg CPG_CORE R9A07G044_CLK_I>;
105 operating-points-v2 = 105 operating-points-v2 = <&cluster0_opp>;
106 }; 106 };
107 107
108 L3_CA55: cache-controller-0 { 108 L3_CA55: cache-controller-0 {
109 compatible = "cache"; 109 compatible = "cache";
110 cache-unified; 110 cache-unified;
111 cache-size = <0x40000> 111 cache-size = <0x40000>;
112 cache-level = <3>; 112 cache-level = <3>;
113 }; 113 };
114 }; 114 };
115 115
116 gpu_opp_table: opp-table-1 { 116 gpu_opp_table: opp-table-1 {
117 compatible = "operating-points 117 compatible = "operating-points-v2";
118 118
119 opp-500000000 { 119 opp-500000000 {
120 opp-hz = /bits/ 64 <50 120 opp-hz = /bits/ 64 <500000000>;
121 opp-microvolt = <11000 121 opp-microvolt = <1100000>;
122 }; 122 };
123 123
124 opp-400000000 { 124 opp-400000000 {
125 opp-hz = /bits/ 64 <40 125 opp-hz = /bits/ 64 <400000000>;
126 opp-microvolt = <11000 126 opp-microvolt = <1100000>;
127 }; 127 };
128 128
129 opp-250000000 { 129 opp-250000000 {
130 opp-hz = /bits/ 64 <25 130 opp-hz = /bits/ 64 <250000000>;
131 opp-microvolt = <11000 131 opp-microvolt = <1100000>;
132 }; 132 };
133 133
134 opp-200000000 { 134 opp-200000000 {
135 opp-hz = /bits/ 64 <20 135 opp-hz = /bits/ 64 <200000000>;
136 opp-microvolt = <11000 136 opp-microvolt = <1100000>;
137 }; 137 };
138 138
139 opp-125000000 { 139 opp-125000000 {
140 opp-hz = /bits/ 64 <12 140 opp-hz = /bits/ 64 <125000000>;
141 opp-microvolt = <11000 141 opp-microvolt = <1100000>;
142 }; 142 };
143 143
144 opp-100000000 { 144 opp-100000000 {
145 opp-hz = /bits/ 64 <10 145 opp-hz = /bits/ 64 <100000000>;
146 opp-microvolt = <11000 146 opp-microvolt = <1100000>;
147 }; 147 };
148 148
149 opp-62500000 { 149 opp-62500000 {
150 opp-hz = /bits/ 64 <62 150 opp-hz = /bits/ 64 <62500000>;
151 opp-microvolt = <11000 151 opp-microvolt = <1100000>;
152 }; 152 };
153 153
154 opp-50000000 { 154 opp-50000000 {
155 opp-hz = /bits/ 64 <50 155 opp-hz = /bits/ 64 <50000000>;
156 opp-microvolt = <11000 156 opp-microvolt = <1100000>;
157 }; 157 };
158 }; 158 };
159 159
160 pmu { 160 pmu {
161 compatible = "arm,cortex-a55-p 161 compatible = "arm,cortex-a55-pmu";
162 interrupts-extended = <&gic GI 162 interrupts-extended = <&gic GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
163 }; 163 };
164 164
165 psci { 165 psci {
166 compatible = "arm,psci-1.0", " 166 compatible = "arm,psci-1.0", "arm,psci-0.2";
167 method = "smc"; 167 method = "smc";
168 }; 168 };
169 169
170 soc: soc { 170 soc: soc {
171 compatible = "simple-bus"; 171 compatible = "simple-bus";
172 interrupt-parent = <&gic>; 172 interrupt-parent = <&gic>;
173 #address-cells = <2>; 173 #address-cells = <2>;
174 #size-cells = <2>; 174 #size-cells = <2>;
175 ranges; 175 ranges;
176 176
177 mtu3: timer@10001200 { 177 mtu3: timer@10001200 {
178 compatible = "renesas, 178 compatible = "renesas,r9a07g044-mtu3",
179 "renesas, 179 "renesas,rz-mtu3";
180 reg = <0 0x10001200 0 180 reg = <0 0x10001200 0 0xb00>;
181 interrupts = <GIC_SPI 181 interrupts = <GIC_SPI 170 IRQ_TYPE_EDGE_RISING>,
182 <GIC_SPI 182 <GIC_SPI 171 IRQ_TYPE_EDGE_RISING>,
183 <GIC_SPI 183 <GIC_SPI 172 IRQ_TYPE_EDGE_RISING>,
184 <GIC_SPI 184 <GIC_SPI 173 IRQ_TYPE_EDGE_RISING>,
185 <GIC_SPI 185 <GIC_SPI 174 IRQ_TYPE_EDGE_RISING>,
186 <GIC_SPI 186 <GIC_SPI 175 IRQ_TYPE_EDGE_RISING>,
187 <GIC_SPI 187 <GIC_SPI 176 IRQ_TYPE_EDGE_RISING>,
188 <GIC_SPI 188 <GIC_SPI 177 IRQ_TYPE_EDGE_RISING>,
189 <GIC_SPI 189 <GIC_SPI 178 IRQ_TYPE_EDGE_RISING>,
190 <GIC_SPI 190 <GIC_SPI 179 IRQ_TYPE_EDGE_RISING>,
191 <GIC_SPI 191 <GIC_SPI 180 IRQ_TYPE_EDGE_RISING>,
192 <GIC_SPI 192 <GIC_SPI 181 IRQ_TYPE_EDGE_RISING>,
193 <GIC_SPI 193 <GIC_SPI 182 IRQ_TYPE_EDGE_RISING>,
194 <GIC_SPI 194 <GIC_SPI 183 IRQ_TYPE_EDGE_RISING>,
195 <GIC_SPI 195 <GIC_SPI 184 IRQ_TYPE_EDGE_RISING>,
196 <GIC_SPI 196 <GIC_SPI 185 IRQ_TYPE_EDGE_RISING>,
197 <GIC_SPI 197 <GIC_SPI 186 IRQ_TYPE_EDGE_RISING>,
198 <GIC_SPI 198 <GIC_SPI 187 IRQ_TYPE_EDGE_RISING>,
199 <GIC_SPI 199 <GIC_SPI 188 IRQ_TYPE_EDGE_RISING>,
200 <GIC_SPI 200 <GIC_SPI 189 IRQ_TYPE_EDGE_RISING>,
201 <GIC_SPI 201 <GIC_SPI 190 IRQ_TYPE_EDGE_RISING>,
202 <GIC_SPI 202 <GIC_SPI 191 IRQ_TYPE_EDGE_RISING>,
203 <GIC_SPI 203 <GIC_SPI 192 IRQ_TYPE_EDGE_RISING>,
204 <GIC_SPI 204 <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>,
205 <GIC_SPI 205 <GIC_SPI 194 IRQ_TYPE_EDGE_RISING>,
206 <GIC_SPI 206 <GIC_SPI 195 IRQ_TYPE_EDGE_RISING>,
207 <GIC_SPI 207 <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>,
208 <GIC_SPI 208 <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>,
209 <GIC_SPI 209 <GIC_SPI 198 IRQ_TYPE_EDGE_RISING>,
210 <GIC_SPI 210 <GIC_SPI 199 IRQ_TYPE_EDGE_RISING>,
211 <GIC_SPI 211 <GIC_SPI 200 IRQ_TYPE_EDGE_RISING>,
212 <GIC_SPI 212 <GIC_SPI 201 IRQ_TYPE_EDGE_RISING>,
213 <GIC_SPI 213 <GIC_SPI 202 IRQ_TYPE_EDGE_RISING>,
214 <GIC_SPI 214 <GIC_SPI 203 IRQ_TYPE_EDGE_RISING>,
215 <GIC_SPI 215 <GIC_SPI 204 IRQ_TYPE_EDGE_RISING>,
216 <GIC_SPI 216 <GIC_SPI 205 IRQ_TYPE_EDGE_RISING>,
217 <GIC_SPI 217 <GIC_SPI 206 IRQ_TYPE_EDGE_RISING>,
218 <GIC_SPI 218 <GIC_SPI 207 IRQ_TYPE_EDGE_RISING>,
219 <GIC_SPI 219 <GIC_SPI 208 IRQ_TYPE_EDGE_RISING>,
220 <GIC_SPI 220 <GIC_SPI 209 IRQ_TYPE_EDGE_RISING>,
221 <GIC_SPI 221 <GIC_SPI 210 IRQ_TYPE_EDGE_RISING>,
222 <GIC_SPI 222 <GIC_SPI 211 IRQ_TYPE_EDGE_RISING>,
223 <GIC_SPI 223 <GIC_SPI 212 IRQ_TYPE_EDGE_RISING>,
224 <GIC_SPI 224 <GIC_SPI 213 IRQ_TYPE_EDGE_RISING>;
225 interrupt-names = "tgi 225 interrupt-names = "tgia0", "tgib0", "tgic0", "tgid0",
226 "tci 226 "tciv0", "tgie0", "tgif0",
227 "tgi 227 "tgia1", "tgib1", "tciv1", "tciu1",
228 "tgi 228 "tgia2", "tgib2", "tciv2", "tciu2",
229 "tgi 229 "tgia3", "tgib3", "tgic3", "tgid3",
230 "tci 230 "tciv3",
231 "tgi 231 "tgia4", "tgib4", "tgic4", "tgid4",
232 "tci 232 "tciv4",
233 "tgi 233 "tgiu5", "tgiv5", "tgiw5",
234 "tgi 234 "tgia6", "tgib6", "tgic6", "tgid6",
235 "tci 235 "tciv6",
236 "tgi 236 "tgia7", "tgib7", "tgic7", "tgid7",
237 "tci 237 "tciv7",
238 "tgi 238 "tgia8", "tgib8", "tgic8", "tgid8",
239 "tci 239 "tciv8", "tciu8";
240 clocks = <&cpg CPG_MOD 240 clocks = <&cpg CPG_MOD R9A07G044_MTU_X_MCK_MTU3>;
241 power-domains = <&cpg> 241 power-domains = <&cpg>;
242 resets = <&cpg R9A07G0 242 resets = <&cpg R9A07G044_MTU_X_PRESET_MTU3>;
243 #pwm-cells = <2>; 243 #pwm-cells = <2>;
244 status = "disabled"; 244 status = "disabled";
245 }; 245 };
246 246
247 ssi0: ssi@10049c00 { 247 ssi0: ssi@10049c00 {
248 compatible = "renesas, 248 compatible = "renesas,r9a07g044-ssi",
249 "renesas, 249 "renesas,rz-ssi";
250 reg = <0 0x10049c00 0 250 reg = <0 0x10049c00 0 0x400>;
251 interrupts = <GIC_SPI 251 interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
252 <GIC_SPI 252 <GIC_SPI 327 IRQ_TYPE_EDGE_RISING>,
253 <GIC_SPI 253 <GIC_SPI 328 IRQ_TYPE_EDGE_RISING>;
254 interrupt-names = "int 254 interrupt-names = "int_req", "dma_rx", "dma_tx";
255 clocks = <&cpg CPG_MOD 255 clocks = <&cpg CPG_MOD R9A07G044_SSI0_PCLK2>,
256 <&cpg CPG_MOD 256 <&cpg CPG_MOD R9A07G044_SSI0_PCLK_SFR>,
257 <&audio_clk1> 257 <&audio_clk1>, <&audio_clk2>;
258 clock-names = "ssi", " 258 clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2";
259 resets = <&cpg R9A07G0 259 resets = <&cpg R9A07G044_SSI0_RST_M2_REG>;
260 dmas = <&dmac 0x2655>, 260 dmas = <&dmac 0x2655>, <&dmac 0x2656>;
261 dma-names = "tx", "rx" 261 dma-names = "tx", "rx";
262 power-domains = <&cpg> 262 power-domains = <&cpg>;
263 #sound-dai-cells = <0> 263 #sound-dai-cells = <0>;
264 status = "disabled"; 264 status = "disabled";
265 }; 265 };
266 266
267 ssi1: ssi@1004a000 { 267 ssi1: ssi@1004a000 {
268 compatible = "renesas, 268 compatible = "renesas,r9a07g044-ssi",
269 "renesas, 269 "renesas,rz-ssi";
270 reg = <0 0x1004a000 0 270 reg = <0 0x1004a000 0 0x400>;
271 interrupts = <GIC_SPI 271 interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
272 <GIC_SPI 272 <GIC_SPI 331 IRQ_TYPE_EDGE_RISING>,
273 <GIC_SPI 273 <GIC_SPI 332 IRQ_TYPE_EDGE_RISING>;
274 interrupt-names = "int 274 interrupt-names = "int_req", "dma_rx", "dma_tx";
275 clocks = <&cpg CPG_MOD 275 clocks = <&cpg CPG_MOD R9A07G044_SSI1_PCLK2>,
276 <&cpg CPG_MOD 276 <&cpg CPG_MOD R9A07G044_SSI1_PCLK_SFR>,
277 <&audio_clk1> 277 <&audio_clk1>, <&audio_clk2>;
278 clock-names = "ssi", " 278 clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2";
279 resets = <&cpg R9A07G0 279 resets = <&cpg R9A07G044_SSI1_RST_M2_REG>;
280 dmas = <&dmac 0x2659>, 280 dmas = <&dmac 0x2659>, <&dmac 0x265a>;
281 dma-names = "tx", "rx" 281 dma-names = "tx", "rx";
282 power-domains = <&cpg> 282 power-domains = <&cpg>;
283 #sound-dai-cells = <0> 283 #sound-dai-cells = <0>;
284 status = "disabled"; 284 status = "disabled";
285 }; 285 };
286 286
287 ssi2: ssi@1004a400 { 287 ssi2: ssi@1004a400 {
288 compatible = "renesas, 288 compatible = "renesas,r9a07g044-ssi",
289 "renesas, 289 "renesas,rz-ssi";
290 reg = <0 0x1004a400 0 290 reg = <0 0x1004a400 0 0x400>;
291 interrupts = <GIC_SPI 291 interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
292 <GIC_SPI 292 <GIC_SPI 337 IRQ_TYPE_EDGE_RISING>;
293 interrupt-names = "int 293 interrupt-names = "int_req", "dma_rt";
294 clocks = <&cpg CPG_MOD 294 clocks = <&cpg CPG_MOD R9A07G044_SSI2_PCLK2>,
295 <&cpg CPG_MOD 295 <&cpg CPG_MOD R9A07G044_SSI2_PCLK_SFR>,
296 <&audio_clk1> 296 <&audio_clk1>, <&audio_clk2>;
297 clock-names = "ssi", " 297 clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2";
298 resets = <&cpg R9A07G0 298 resets = <&cpg R9A07G044_SSI2_RST_M2_REG>;
299 dmas = <&dmac 0x265f>; 299 dmas = <&dmac 0x265f>;
300 dma-names = "rt"; 300 dma-names = "rt";
301 power-domains = <&cpg> 301 power-domains = <&cpg>;
302 #sound-dai-cells = <0> 302 #sound-dai-cells = <0>;
303 status = "disabled"; 303 status = "disabled";
304 }; 304 };
305 305
306 ssi3: ssi@1004a800 { 306 ssi3: ssi@1004a800 {
307 compatible = "renesas, 307 compatible = "renesas,r9a07g044-ssi",
308 "renesas, 308 "renesas,rz-ssi";
309 reg = <0 0x1004a800 0 309 reg = <0 0x1004a800 0 0x400>;
310 interrupts = <GIC_SPI 310 interrupts = <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
311 <GIC_SPI 311 <GIC_SPI 339 IRQ_TYPE_EDGE_RISING>,
312 <GIC_SPI 312 <GIC_SPI 340 IRQ_TYPE_EDGE_RISING>;
313 interrupt-names = "int 313 interrupt-names = "int_req", "dma_rx", "dma_tx";
314 clocks = <&cpg CPG_MOD 314 clocks = <&cpg CPG_MOD R9A07G044_SSI3_PCLK2>,
315 <&cpg CPG_MOD 315 <&cpg CPG_MOD R9A07G044_SSI3_PCLK_SFR>,
316 <&audio_clk1> 316 <&audio_clk1>, <&audio_clk2>;
317 clock-names = "ssi", " 317 clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2";
318 resets = <&cpg R9A07G0 318 resets = <&cpg R9A07G044_SSI3_RST_M2_REG>;
319 dmas = <&dmac 0x2661>, 319 dmas = <&dmac 0x2661>, <&dmac 0x2662>;
320 dma-names = "tx", "rx" 320 dma-names = "tx", "rx";
321 power-domains = <&cpg> 321 power-domains = <&cpg>;
322 #sound-dai-cells = <0> 322 #sound-dai-cells = <0>;
323 status = "disabled"; 323 status = "disabled";
324 }; 324 };
325 325
326 spi0: spi@1004ac00 { 326 spi0: spi@1004ac00 {
327 compatible = "renesas, 327 compatible = "renesas,r9a07g044-rspi", "renesas,rspi-rz";
328 reg = <0 0x1004ac00 0 328 reg = <0 0x1004ac00 0 0x400>;
329 interrupts = <GIC_SPI 329 interrupts = <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>,
330 <GIC_SPI 330 <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>,
331 <GIC_SPI 331 <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>;
332 interrupt-names = "err 332 interrupt-names = "error", "rx", "tx";
333 clocks = <&cpg CPG_MOD 333 clocks = <&cpg CPG_MOD R9A07G044_RSPI0_CLKB>;
334 resets = <&cpg R9A07G0 334 resets = <&cpg R9A07G044_RSPI0_RST>;
335 dmas = <&dmac 0x2e95>, 335 dmas = <&dmac 0x2e95>, <&dmac 0x2e96>;
336 dma-names = "tx", "rx" 336 dma-names = "tx", "rx";
337 power-domains = <&cpg> 337 power-domains = <&cpg>;
338 num-cs = <1>; 338 num-cs = <1>;
339 #address-cells = <1>; 339 #address-cells = <1>;
340 #size-cells = <0>; 340 #size-cells = <0>;
341 status = "disabled"; 341 status = "disabled";
342 }; 342 };
343 343
344 spi1: spi@1004b000 { 344 spi1: spi@1004b000 {
345 compatible = "renesas, 345 compatible = "renesas,r9a07g044-rspi", "renesas,rspi-rz";
346 reg = <0 0x1004b000 0 346 reg = <0 0x1004b000 0 0x400>;
347 interrupts = <GIC_SPI 347 interrupts = <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
348 <GIC_SPI 348 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
349 <GIC_SPI 349 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>;
350 interrupt-names = "err 350 interrupt-names = "error", "rx", "tx";
351 clocks = <&cpg CPG_MOD 351 clocks = <&cpg CPG_MOD R9A07G044_RSPI1_CLKB>;
352 resets = <&cpg R9A07G0 352 resets = <&cpg R9A07G044_RSPI1_RST>;
353 dmas = <&dmac 0x2e99>, 353 dmas = <&dmac 0x2e99>, <&dmac 0x2e9a>;
354 dma-names = "tx", "rx" 354 dma-names = "tx", "rx";
355 power-domains = <&cpg> 355 power-domains = <&cpg>;
356 num-cs = <1>; 356 num-cs = <1>;
357 #address-cells = <1>; 357 #address-cells = <1>;
358 #size-cells = <0>; 358 #size-cells = <0>;
359 status = "disabled"; 359 status = "disabled";
360 }; 360 };
361 361
362 spi2: spi@1004b400 { 362 spi2: spi@1004b400 {
363 compatible = "renesas, 363 compatible = "renesas,r9a07g044-rspi", "renesas,rspi-rz";
364 reg = <0 0x1004b400 0 364 reg = <0 0x1004b400 0 0x400>;
365 interrupts = <GIC_SPI 365 interrupts = <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
366 <GIC_SPI 366 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
367 <GIC_SPI 367 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>;
368 interrupt-names = "err 368 interrupt-names = "error", "rx", "tx";
369 clocks = <&cpg CPG_MOD 369 clocks = <&cpg CPG_MOD R9A07G044_RSPI2_CLKB>;
370 resets = <&cpg R9A07G0 370 resets = <&cpg R9A07G044_RSPI2_RST>;
371 dmas = <&dmac 0x2e9d>, 371 dmas = <&dmac 0x2e9d>, <&dmac 0x2e9e>;
372 dma-names = "tx", "rx" 372 dma-names = "tx", "rx";
373 power-domains = <&cpg> 373 power-domains = <&cpg>;
374 num-cs = <1>; 374 num-cs = <1>;
375 #address-cells = <1>; 375 #address-cells = <1>;
376 #size-cells = <0>; 376 #size-cells = <0>;
377 status = "disabled"; 377 status = "disabled";
378 }; 378 };
379 379
380 scif0: serial@1004b800 { 380 scif0: serial@1004b800 {
381 compatible = "renesas, 381 compatible = "renesas,scif-r9a07g044";
382 reg = <0 0x1004b800 0 382 reg = <0 0x1004b800 0 0x400>;
383 interrupts = <GIC_SPI 383 interrupts = <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>,
384 <GIC_SPI 384 <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>,
385 <GIC_SPI 385 <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>,
386 <GIC_SPI 386 <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>,
387 <GIC_SPI 387 <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>,
388 <GIC_SPI 388 <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>;
389 interrupt-names = "eri 389 interrupt-names = "eri", "rxi", "txi",
390 "bri 390 "bri", "dri", "tei";
391 clocks = <&cpg CPG_MOD 391 clocks = <&cpg CPG_MOD R9A07G044_SCIF0_CLK_PCK>;
392 clock-names = "fck"; 392 clock-names = "fck";
393 power-domains = <&cpg> 393 power-domains = <&cpg>;
394 resets = <&cpg R9A07G0 394 resets = <&cpg R9A07G044_SCIF0_RST_SYSTEM_N>;
395 status = "disabled"; 395 status = "disabled";
396 }; 396 };
397 397
398 scif1: serial@1004bc00 { 398 scif1: serial@1004bc00 {
399 compatible = "renesas, 399 compatible = "renesas,scif-r9a07g044";
400 reg = <0 0x1004bc00 0 400 reg = <0 0x1004bc00 0 0x400>;
401 interrupts = <GIC_SPI 401 interrupts = <GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>,
402 <GIC_SPI 402 <GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>,
403 <GIC_SPI 403 <GIC_SPI 388 IRQ_TYPE_LEVEL_HIGH>,
404 <GIC_SPI 404 <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>,
405 <GIC_SPI 405 <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>,
406 <GIC_SPI 406 <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>;
407 interrupt-names = "eri 407 interrupt-names = "eri", "rxi", "txi",
408 "bri 408 "bri", "dri", "tei";
409 clocks = <&cpg CPG_MOD 409 clocks = <&cpg CPG_MOD R9A07G044_SCIF1_CLK_PCK>;
410 clock-names = "fck"; 410 clock-names = "fck";
411 power-domains = <&cpg> 411 power-domains = <&cpg>;
412 resets = <&cpg R9A07G0 412 resets = <&cpg R9A07G044_SCIF1_RST_SYSTEM_N>;
413 status = "disabled"; 413 status = "disabled";
414 }; 414 };
415 415
416 scif2: serial@1004c000 { 416 scif2: serial@1004c000 {
417 compatible = "renesas, 417 compatible = "renesas,scif-r9a07g044";
418 reg = <0 0x1004c000 0 418 reg = <0 0x1004c000 0 0x400>;
419 interrupts = <GIC_SPI 419 interrupts = <GIC_SPI 390 IRQ_TYPE_LEVEL_HIGH>,
420 <GIC_SPI 420 <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH>,
421 <GIC_SPI 421 <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>,
422 <GIC_SPI 422 <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH>,
423 <GIC_SPI 423 <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>,
424 <GIC_SPI 424 <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>;
425 interrupt-names = "eri 425 interrupt-names = "eri", "rxi", "txi",
426 "bri 426 "bri", "dri", "tei";
427 clocks = <&cpg CPG_MOD 427 clocks = <&cpg CPG_MOD R9A07G044_SCIF2_CLK_PCK>;
428 clock-names = "fck"; 428 clock-names = "fck";
429 power-domains = <&cpg> 429 power-domains = <&cpg>;
430 resets = <&cpg R9A07G0 430 resets = <&cpg R9A07G044_SCIF2_RST_SYSTEM_N>;
431 status = "disabled"; 431 status = "disabled";
432 }; 432 };
433 433
434 scif3: serial@1004c400 { 434 scif3: serial@1004c400 {
435 compatible = "renesas, 435 compatible = "renesas,scif-r9a07g044";
436 reg = <0 0x1004c400 0 436 reg = <0 0x1004c400 0 0x400>;
437 interrupts = <GIC_SPI 437 interrupts = <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
438 <GIC_SPI 438 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
439 <GIC_SPI 439 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
440 <GIC_SPI 440 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
441 <GIC_SPI 441 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
442 <GIC_SPI 442 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>;
443 interrupt-names = "eri 443 interrupt-names = "eri", "rxi", "txi",
444 "bri 444 "bri", "dri", "tei";
445 clocks = <&cpg CPG_MOD 445 clocks = <&cpg CPG_MOD R9A07G044_SCIF3_CLK_PCK>;
446 clock-names = "fck"; 446 clock-names = "fck";
447 power-domains = <&cpg> 447 power-domains = <&cpg>;
448 resets = <&cpg R9A07G0 448 resets = <&cpg R9A07G044_SCIF3_RST_SYSTEM_N>;
449 status = "disabled"; 449 status = "disabled";
450 }; 450 };
451 451
452 scif4: serial@1004c800 { 452 scif4: serial@1004c800 {
453 compatible = "renesas, 453 compatible = "renesas,scif-r9a07g044";
454 reg = <0 0x1004c800 0 454 reg = <0 0x1004c800 0 0x400>;
455 interrupts = <GIC_SPI 455 interrupts = <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
456 <GIC_SPI 456 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
457 <GIC_SPI 457 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
458 <GIC_SPI 458 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
459 <GIC_SPI 459 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
460 <GIC_SPI 460 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>;
461 interrupt-names = "eri 461 interrupt-names = "eri", "rxi", "txi",
462 "bri 462 "bri", "dri", "tei";
463 clocks = <&cpg CPG_MOD 463 clocks = <&cpg CPG_MOD R9A07G044_SCIF4_CLK_PCK>;
464 clock-names = "fck"; 464 clock-names = "fck";
465 power-domains = <&cpg> 465 power-domains = <&cpg>;
466 resets = <&cpg R9A07G0 466 resets = <&cpg R9A07G044_SCIF4_RST_SYSTEM_N>;
467 status = "disabled"; 467 status = "disabled";
468 }; 468 };
469 469
470 sci0: serial@1004d000 { 470 sci0: serial@1004d000 {
471 compatible = "renesas, 471 compatible = "renesas,r9a07g044-sci", "renesas,sci";
472 reg = <0 0x1004d000 0 472 reg = <0 0x1004d000 0 0x400>;
473 interrupts = <GIC_SPI 473 interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
474 <GIC_SPI 474 <GIC_SPI 406 IRQ_TYPE_EDGE_RISING>,
475 <GIC_SPI 475 <GIC_SPI 407 IRQ_TYPE_EDGE_RISING>,
476 <GIC_SPI 476 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>;
477 interrupt-names = "eri 477 interrupt-names = "eri", "rxi", "txi", "tei";
478 clocks = <&cpg CPG_MOD 478 clocks = <&cpg CPG_MOD R9A07G044_SCI0_CLKP>;
479 clock-names = "fck"; 479 clock-names = "fck";
480 power-domains = <&cpg> 480 power-domains = <&cpg>;
481 resets = <&cpg R9A07G0 481 resets = <&cpg R9A07G044_SCI0_RST>;
482 status = "disabled"; 482 status = "disabled";
483 }; 483 };
484 484
485 sci1: serial@1004d400 { 485 sci1: serial@1004d400 {
486 compatible = "renesas, 486 compatible = "renesas,r9a07g044-sci", "renesas,sci";
487 reg = <0 0x1004d400 0 487 reg = <0 0x1004d400 0 0x400>;
488 interrupts = <GIC_SPI 488 interrupts = <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
489 <GIC_SPI 489 <GIC_SPI 410 IRQ_TYPE_EDGE_RISING>,
490 <GIC_SPI 490 <GIC_SPI 411 IRQ_TYPE_EDGE_RISING>,
491 <GIC_SPI 491 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>;
492 interrupt-names = "eri 492 interrupt-names = "eri", "rxi", "txi", "tei";
493 clocks = <&cpg CPG_MOD 493 clocks = <&cpg CPG_MOD R9A07G044_SCI1_CLKP>;
494 clock-names = "fck"; 494 clock-names = "fck";
495 power-domains = <&cpg> 495 power-domains = <&cpg>;
496 resets = <&cpg R9A07G0 496 resets = <&cpg R9A07G044_SCI1_RST>;
497 status = "disabled"; 497 status = "disabled";
498 }; 498 };
499 499
500 canfd: can@10050000 { 500 canfd: can@10050000 {
501 compatible = "renesas, 501 compatible = "renesas,r9a07g044-canfd", "renesas,rzg2l-canfd";
502 reg = <0 0x10050000 0 502 reg = <0 0x10050000 0 0x8000>;
503 interrupts = <GIC_SPI 503 interrupts = <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>,
504 <GIC_SPI 504 <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>,
505 <GIC_SPI 505 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
506 <GIC_SPI 506 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
507 <GIC_SPI 507 <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>,
508 <GIC_SPI 508 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
509 <GIC_SPI 509 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
510 <GIC_SPI 510 <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>;
511 interrupt-names = "g_e 511 interrupt-names = "g_err", "g_recc",
512 "ch0 512 "ch0_err", "ch0_rec", "ch0_trx",
513 "ch1 513 "ch1_err", "ch1_rec", "ch1_trx";
514 clocks = <&cpg CPG_MOD 514 clocks = <&cpg CPG_MOD R9A07G044_CANFD_PCLK>,
515 <&cpg CPG_COR 515 <&cpg CPG_CORE R9A07G044_CLK_P0_DIV2>,
516 <&can_clk>; 516 <&can_clk>;
517 clock-names = "fck", " 517 clock-names = "fck", "canfd", "can_clk";
518 assigned-clocks = <&cp 518 assigned-clocks = <&cpg CPG_CORE R9A07G044_CLK_P0_DIV2>;
519 assigned-clock-rates = 519 assigned-clock-rates = <50000000>;
520 resets = <&cpg R9A07G0 520 resets = <&cpg R9A07G044_CANFD_RSTP_N>,
521 <&cpg R9A07G0 521 <&cpg R9A07G044_CANFD_RSTC_N>;
522 reset-names = "rstp_n" 522 reset-names = "rstp_n", "rstc_n";
523 power-domains = <&cpg> 523 power-domains = <&cpg>;
524 status = "disabled"; 524 status = "disabled";
525 525
526 channel0 { 526 channel0 {
527 status = "disa 527 status = "disabled";
528 }; 528 };
529 channel1 { 529 channel1 {
530 status = "disa 530 status = "disabled";
531 }; 531 };
532 }; 532 };
533 533
534 i2c0: i2c@10058000 { 534 i2c0: i2c@10058000 {
535 #address-cells = <1>; 535 #address-cells = <1>;
536 #size-cells = <0>; 536 #size-cells = <0>;
537 compatible = "renesas, 537 compatible = "renesas,riic-r9a07g044", "renesas,riic-rz";
538 reg = <0 0x10058000 0 538 reg = <0 0x10058000 0 0x400>;
539 interrupts = <GIC_SPI 539 interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>,
540 <GIC_SPI 540 <GIC_SPI 348 IRQ_TYPE_EDGE_RISING>,
541 <GIC_SPI 541 <GIC_SPI 349 IRQ_TYPE_EDGE_RISING>,
542 <GIC_SPI 542 <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>,
543 <GIC_SPI 543 <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>,
544 <GIC_SPI 544 <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>,
545 <GIC_SPI 545 <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>,
546 <GIC_SPI 546 <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
547 interrupt-names = "tei 547 interrupt-names = "tei", "ri", "ti", "spi", "sti",
548 "nak 548 "naki", "ali", "tmoi";
549 clocks = <&cpg CPG_MOD 549 clocks = <&cpg CPG_MOD R9A07G044_I2C0_PCLK>;
550 clock-frequency = <100 550 clock-frequency = <100000>;
551 resets = <&cpg R9A07G0 551 resets = <&cpg R9A07G044_I2C0_MRST>;
552 power-domains = <&cpg> 552 power-domains = <&cpg>;
553 status = "disabled"; 553 status = "disabled";
554 }; 554 };
555 555
556 i2c1: i2c@10058400 { 556 i2c1: i2c@10058400 {
557 #address-cells = <1>; 557 #address-cells = <1>;
558 #size-cells = <0>; 558 #size-cells = <0>;
559 compatible = "renesas, 559 compatible = "renesas,riic-r9a07g044", "renesas,riic-rz";
560 reg = <0 0x10058400 0 560 reg = <0 0x10058400 0 0x400>;
561 interrupts = <GIC_SPI 561 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>,
562 <GIC_SPI 562 <GIC_SPI 356 IRQ_TYPE_EDGE_RISING>,
563 <GIC_SPI 563 <GIC_SPI 357 IRQ_TYPE_EDGE_RISING>,
564 <GIC_SPI 564 <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>,
565 <GIC_SPI 565 <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>,
566 <GIC_SPI 566 <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>,
567 <GIC_SPI 567 <GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH>,
568 <GIC_SPI 568 <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>;
569 interrupt-names = "tei 569 interrupt-names = "tei", "ri", "ti", "spi", "sti",
570 "nak 570 "naki", "ali", "tmoi";
571 clocks = <&cpg CPG_MOD 571 clocks = <&cpg CPG_MOD R9A07G044_I2C1_PCLK>;
572 clock-frequency = <100 572 clock-frequency = <100000>;
573 resets = <&cpg R9A07G0 573 resets = <&cpg R9A07G044_I2C1_MRST>;
574 power-domains = <&cpg> 574 power-domains = <&cpg>;
575 status = "disabled"; 575 status = "disabled";
576 }; 576 };
577 577
578 i2c2: i2c@10058800 { 578 i2c2: i2c@10058800 {
579 #address-cells = <1>; 579 #address-cells = <1>;
580 #size-cells = <0>; 580 #size-cells = <0>;
581 compatible = "renesas, 581 compatible = "renesas,riic-r9a07g044", "renesas,riic-rz";
582 reg = <0 0x10058800 0 582 reg = <0 0x10058800 0 0x400>;
583 interrupts = <GIC_SPI 583 interrupts = <GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>,
584 <GIC_SPI 584 <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>,
585 <GIC_SPI 585 <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>,
586 <GIC_SPI 586 <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>,
587 <GIC_SPI 587 <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>,
588 <GIC_SPI 588 <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>,
589 <GIC_SPI 589 <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>,
590 <GIC_SPI 590 <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
591 interrupt-names = "tei 591 interrupt-names = "tei", "ri", "ti", "spi", "sti",
592 "nak 592 "naki", "ali", "tmoi";
593 clocks = <&cpg CPG_MOD 593 clocks = <&cpg CPG_MOD R9A07G044_I2C2_PCLK>;
594 clock-frequency = <100 594 clock-frequency = <100000>;
595 resets = <&cpg R9A07G0 595 resets = <&cpg R9A07G044_I2C2_MRST>;
596 power-domains = <&cpg> 596 power-domains = <&cpg>;
597 status = "disabled"; 597 status = "disabled";
598 }; 598 };
599 599
600 i2c3: i2c@10058c00 { 600 i2c3: i2c@10058c00 {
601 #address-cells = <1>; 601 #address-cells = <1>;
602 #size-cells = <0>; 602 #size-cells = <0>;
603 compatible = "renesas, 603 compatible = "renesas,riic-r9a07g044", "renesas,riic-rz";
604 reg = <0 0x10058c00 0 604 reg = <0 0x10058c00 0 0x400>;
605 interrupts = <GIC_SPI 605 interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>,
606 <GIC_SPI 606 <GIC_SPI 372 IRQ_TYPE_EDGE_RISING>,
607 <GIC_SPI 607 <GIC_SPI 373 IRQ_TYPE_EDGE_RISING>,
608 <GIC_SPI 608 <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>,
609 <GIC_SPI 609 <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>,
610 <GIC_SPI 610 <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>,
611 <GIC_SPI 611 <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>,
612 <GIC_SPI 612 <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
613 interrupt-names = "tei 613 interrupt-names = "tei", "ri", "ti", "spi", "sti",
614 "nak 614 "naki", "ali", "tmoi";
615 clocks = <&cpg CPG_MOD 615 clocks = <&cpg CPG_MOD R9A07G044_I2C3_PCLK>;
616 clock-frequency = <100 616 clock-frequency = <100000>;
617 resets = <&cpg R9A07G0 617 resets = <&cpg R9A07G044_I2C3_MRST>;
618 power-domains = <&cpg> 618 power-domains = <&cpg>;
619 status = "disabled"; 619 status = "disabled";
620 }; 620 };
621 621
622 adc: adc@10059000 { 622 adc: adc@10059000 {
623 compatible = "renesas, 623 compatible = "renesas,r9a07g044-adc", "renesas,rzg2l-adc";
624 reg = <0 0x10059000 0 624 reg = <0 0x10059000 0 0x400>;
625 interrupts = <GIC_SPI 625 interrupts = <GIC_SPI 347 IRQ_TYPE_EDGE_RISING>;
626 clocks = <&cpg CPG_MOD 626 clocks = <&cpg CPG_MOD R9A07G044_ADC_ADCLK>,
627 <&cpg CPG_MOD 627 <&cpg CPG_MOD R9A07G044_ADC_PCLK>;
628 clock-names = "adclk", 628 clock-names = "adclk", "pclk";
629 resets = <&cpg R9A07G0 629 resets = <&cpg R9A07G044_ADC_PRESETN>,
630 <&cpg R9A07G0 630 <&cpg R9A07G044_ADC_ADRST_N>;
631 reset-names = "presetn 631 reset-names = "presetn", "adrst-n";
632 power-domains = <&cpg> 632 power-domains = <&cpg>;
633 status = "disabled"; 633 status = "disabled";
634 634
635 #address-cells = <1>; 635 #address-cells = <1>;
636 #size-cells = <0>; 636 #size-cells = <0>;
637 637
638 channel@0 { 638 channel@0 {
639 reg = <0>; 639 reg = <0>;
640 }; 640 };
641 channel@1 { 641 channel@1 {
642 reg = <1>; 642 reg = <1>;
643 }; 643 };
644 channel@2 { 644 channel@2 {
645 reg = <2>; 645 reg = <2>;
646 }; 646 };
647 channel@3 { 647 channel@3 {
648 reg = <3>; 648 reg = <3>;
649 }; 649 };
650 channel@4 { 650 channel@4 {
651 reg = <4>; 651 reg = <4>;
652 }; 652 };
653 channel@5 { 653 channel@5 {
654 reg = <5>; 654 reg = <5>;
655 }; 655 };
656 channel@6 { 656 channel@6 {
657 reg = <6>; 657 reg = <6>;
658 }; 658 };
659 channel@7 { 659 channel@7 {
660 reg = <7>; 660 reg = <7>;
661 }; 661 };
662 }; 662 };
663 663
664 tsu: thermal@10059400 { 664 tsu: thermal@10059400 {
665 compatible = "renesas, 665 compatible = "renesas,r9a07g044-tsu",
666 "renesas, 666 "renesas,rzg2l-tsu";
667 reg = <0 0x10059400 0 667 reg = <0 0x10059400 0 0x400>;
668 clocks = <&cpg CPG_MOD 668 clocks = <&cpg CPG_MOD R9A07G044_TSU_PCLK>;
669 resets = <&cpg R9A07G0 669 resets = <&cpg R9A07G044_TSU_PRESETN>;
670 power-domains = <&cpg> 670 power-domains = <&cpg>;
671 #thermal-sensor-cells 671 #thermal-sensor-cells = <1>;
672 }; 672 };
673 673
674 sbc: spi@10060000 { 674 sbc: spi@10060000 {
675 compatible = "renesas, 675 compatible = "renesas,r9a07g044-rpc-if",
676 "renesas, 676 "renesas,rzg2l-rpc-if";
677 reg = <0 0x10060000 0 677 reg = <0 0x10060000 0 0x10000>,
678 <0 0x20000000 0 678 <0 0x20000000 0 0x10000000>,
679 <0 0x10070000 0 679 <0 0x10070000 0 0x10000>;
680 reg-names = "regs", "d 680 reg-names = "regs", "dirmap", "wbuf";
681 interrupts = <GIC_SPI 681 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
682 clocks = <&cpg CPG_MOD 682 clocks = <&cpg CPG_MOD R9A07G044_SPI_CLK2>,
683 <&cpg CPG_MOD 683 <&cpg CPG_MOD R9A07G044_SPI_CLK>;
684 resets = <&cpg R9A07G0 684 resets = <&cpg R9A07G044_SPI_RST>;
685 power-domains = <&cpg> 685 power-domains = <&cpg>;
686 #address-cells = <1>; 686 #address-cells = <1>;
687 #size-cells = <0>; 687 #size-cells = <0>;
688 status = "disabled"; 688 status = "disabled";
689 }; 689 };
690 690
691 cru: video@10830000 { 691 cru: video@10830000 {
692 compatible = "renesas, 692 compatible = "renesas,r9a07g044-cru", "renesas,rzg2l-cru";
693 reg = <0 0x10830000 0 693 reg = <0 0x10830000 0 0x400>;
694 clocks = <&cpg CPG_MOD 694 clocks = <&cpg CPG_MOD R9A07G044_CRU_VCLK>,
695 <&cpg CPG_MOD 695 <&cpg CPG_MOD R9A07G044_CRU_PCLK>,
696 <&cpg CPG_MOD 696 <&cpg CPG_MOD R9A07G044_CRU_ACLK>;
697 clock-names = "video", 697 clock-names = "video", "apb", "axi";
698 interrupts = <GIC_SPI 698 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
699 <GIC_SPI 699 <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
700 <GIC_SPI 700 <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
701 interrupt-names = "ima 701 interrupt-names = "image_conv", "image_conv_err", "axi_mst_err";
702 resets = <&cpg R9A07G0 702 resets = <&cpg R9A07G044_CRU_PRESETN>,
703 <&cpg R9A07G0 703 <&cpg R9A07G044_CRU_ARESETN>;
704 reset-names = "presetn 704 reset-names = "presetn", "aresetn";
705 power-domains = <&cpg> 705 power-domains = <&cpg>;
706 status = "disabled"; 706 status = "disabled";
707 707
708 ports { 708 ports {
709 #address-cells 709 #address-cells = <1>;
710 #size-cells = 710 #size-cells = <0>;
711 711
712 port@0 { 712 port@0 {
713 #addre 713 #address-cells = <1>;
714 #size- 714 #size-cells = <0>;
715 715
716 reg = 716 reg = <0>;
717 crupar 717 cruparallel: endpoint@0 {
718 718 reg = <0>;
719 }; 719 };
720 }; 720 };
721 721
722 port@1 { 722 port@1 {
723 #addre 723 #address-cells = <1>;
724 #size- 724 #size-cells = <0>;
725 725
726 reg = 726 reg = <1>;
727 crucsi 727 crucsi2: endpoint@0 {
728 728 reg = <0>;
729 729 remote-endpoint = <&csi2cru>;
730 }; 730 };
731 }; 731 };
732 }; 732 };
733 }; 733 };
734 734
735 csi2: csi2@10830400 { 735 csi2: csi2@10830400 {
736 compatible = "renesas, 736 compatible = "renesas,r9a07g044-csi2", "renesas,rzg2l-csi2";
737 reg = <0 0x10830400 0 737 reg = <0 0x10830400 0 0xfc00>;
738 interrupts = <GIC_SPI 738 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
739 clocks = <&cpg CPG_MOD 739 clocks = <&cpg CPG_MOD R9A07G044_CRU_SYSCLK>,
740 <&cpg CPG_MOD 740 <&cpg CPG_MOD R9A07G044_CRU_VCLK>,
741 <&cpg CPG_MOD 741 <&cpg CPG_MOD R9A07G044_CRU_PCLK>;
742 clock-names = "system" 742 clock-names = "system", "video", "apb";
743 resets = <&cpg R9A07G0 743 resets = <&cpg R9A07G044_CRU_PRESETN>,
744 <&cpg R9A07G0 744 <&cpg R9A07G044_CRU_CMN_RSTB>;
745 reset-names = "presetn 745 reset-names = "presetn", "cmn-rstb";
746 power-domains = <&cpg> 746 power-domains = <&cpg>;
747 status = "disabled"; 747 status = "disabled";
748 748
749 ports { 749 ports {
750 #address-cells 750 #address-cells = <1>;
751 #size-cells = 751 #size-cells = <0>;
752 752
753 port@0 { 753 port@0 {
754 reg = 754 reg = <0>;
755 }; 755 };
756 756
757 port@1 { 757 port@1 {
758 #addre 758 #address-cells = <1>;
759 #size- 759 #size-cells = <0>;
760 reg = 760 reg = <1>;
761 761
762 csi2cr 762 csi2cru: endpoint@0 {
763 763 reg = <0>;
764 764 remote-endpoint = <&crucsi2>;
765 }; 765 };
766 }; 766 };
767 }; 767 };
768 }; 768 };
769 769
770 dsi: dsi@10850000 { 770 dsi: dsi@10850000 {
771 compatible = "renesas, 771 compatible = "renesas,r9a07g044-mipi-dsi",
772 "renesas, 772 "renesas,rzg2l-mipi-dsi";
773 reg = <0 0x10850000 0 773 reg = <0 0x10850000 0 0x20000>;
774 interrupts = <GIC_SPI 774 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
775 <GIC_SPI 775 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
776 <GIC_SPI 776 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
777 <GIC_SPI 777 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
778 <GIC_SPI 778 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
779 <GIC_SPI 779 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
780 <GIC_SPI 780 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
781 interrupt-names = "seq 781 interrupt-names = "seq0", "seq1", "vin1", "rcv",
782 "fer 782 "ferr", "ppi", "debug";
783 clocks = <&cpg CPG_MOD 783 clocks = <&cpg CPG_MOD R9A07G044_MIPI_DSI_PLLCLK>,
784 <&cpg CPG_MOD 784 <&cpg CPG_MOD R9A07G044_MIPI_DSI_SYSCLK>,
785 <&cpg CPG_MOD 785 <&cpg CPG_MOD R9A07G044_MIPI_DSI_ACLK>,
786 <&cpg CPG_MOD 786 <&cpg CPG_MOD R9A07G044_MIPI_DSI_PCLK>,
787 <&cpg CPG_MOD 787 <&cpg CPG_MOD R9A07G044_MIPI_DSI_VCLK>,
788 <&cpg CPG_MOD 788 <&cpg CPG_MOD R9A07G044_MIPI_DSI_LPCLK>;
789 clock-names = "pllclk" 789 clock-names = "pllclk", "sysclk", "aclk", "pclk", "vclk", "lpclk";
790 resets = <&cpg R9A07G0 790 resets = <&cpg R9A07G044_MIPI_DSI_CMN_RSTB>,
791 <&cpg R9A07G0 791 <&cpg R9A07G044_MIPI_DSI_ARESET_N>,
792 <&cpg R9A07G0 792 <&cpg R9A07G044_MIPI_DSI_PRESET_N>;
793 reset-names = "rst", " 793 reset-names = "rst", "arst", "prst";
794 power-domains = <&cpg> 794 power-domains = <&cpg>;
795 status = "disabled"; 795 status = "disabled";
796 796
797 ports { 797 ports {
798 #address-cells 798 #address-cells = <1>;
799 #size-cells = 799 #size-cells = <0>;
800 800
801 port@0 { 801 port@0 {
802 reg = 802 reg = <0>;
803 dsi0_i 803 dsi0_in: endpoint {
804 804 remote-endpoint = <&du_out_dsi>;
805 }; 805 };
806 }; 806 };
807 807
808 port@1 { 808 port@1 {
809 reg = 809 reg = <1>;
810 }; 810 };
811 }; 811 };
812 }; 812 };
813 813
814 vspd: vsp@10870000 { 814 vspd: vsp@10870000 {
815 compatible = "renesas, 815 compatible = "renesas,r9a07g044-vsp2";
816 reg = <0 0x10870000 0 816 reg = <0 0x10870000 0 0x10000>;
817 interrupts = <GIC_SPI 817 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
818 clocks = <&cpg CPG_MOD 818 clocks = <&cpg CPG_MOD R9A07G044_LCDC_CLK_A>,
819 <&cpg CPG_MOD 819 <&cpg CPG_MOD R9A07G044_LCDC_CLK_P>,
820 <&cpg CPG_MOD 820 <&cpg CPG_MOD R9A07G044_LCDC_CLK_D>;
821 clock-names = "aclk", 821 clock-names = "aclk", "pclk", "vclk";
822 power-domains = <&cpg> 822 power-domains = <&cpg>;
823 resets = <&cpg R9A07G0 823 resets = <&cpg R9A07G044_LCDC_RESET_N>;
824 renesas,fcp = <&fcpvd> 824 renesas,fcp = <&fcpvd>;
825 }; 825 };
826 826
827 fcpvd: fcp@10880000 { 827 fcpvd: fcp@10880000 {
828 compatible = "renesas, 828 compatible = "renesas,r9a07g044-fcpvd",
829 "renesas, 829 "renesas,fcpv";
830 reg = <0 0x10880000 0 830 reg = <0 0x10880000 0 0x10000>;
831 clocks = <&cpg CPG_MOD 831 clocks = <&cpg CPG_MOD R9A07G044_LCDC_CLK_A>,
832 <&cpg CPG_MOD 832 <&cpg CPG_MOD R9A07G044_LCDC_CLK_P>,
833 <&cpg CPG_MOD 833 <&cpg CPG_MOD R9A07G044_LCDC_CLK_D>;
834 clock-names = "aclk", 834 clock-names = "aclk", "pclk", "vclk";
835 power-domains = <&cpg> 835 power-domains = <&cpg>;
836 resets = <&cpg R9A07G0 836 resets = <&cpg R9A07G044_LCDC_RESET_N>;
837 }; 837 };
838 838
839 du: display@10890000 { 839 du: display@10890000 {
840 compatible = "renesas, 840 compatible = "renesas,r9a07g044-du";
841 reg = <0 0x10890000 0 841 reg = <0 0x10890000 0 0x10000>;
842 interrupts = <GIC_SPI 842 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
843 clocks = <&cpg CPG_MOD 843 clocks = <&cpg CPG_MOD R9A07G044_LCDC_CLK_A>,
844 <&cpg CPG_MOD 844 <&cpg CPG_MOD R9A07G044_LCDC_CLK_P>,
845 <&cpg CPG_MOD 845 <&cpg CPG_MOD R9A07G044_LCDC_CLK_D>;
846 clock-names = "aclk", 846 clock-names = "aclk", "pclk", "vclk";
847 power-domains = <&cpg> 847 power-domains = <&cpg>;
848 resets = <&cpg R9A07G0 848 resets = <&cpg R9A07G044_LCDC_RESET_N>;
849 renesas,vsps = <&vspd 849 renesas,vsps = <&vspd 0>;
850 status = "disabled"; 850 status = "disabled";
851 851
852 ports { 852 ports {
853 #address-cells 853 #address-cells = <1>;
854 #size-cells = 854 #size-cells = <0>;
855 855
856 port@0 { 856 port@0 {
857 reg = 857 reg = <0>;
858 du_out 858 du_out_dsi: endpoint {
859 859 remote-endpoint = <&dsi0_in>;
860 }; 860 };
861 }; 861 };
862 862
863 port@1 { 863 port@1 {
864 reg = 864 reg = <1>;
865 }; 865 };
866 }; 866 };
867 }; 867 };
868 868
869 cpg: clock-controller@11010000 869 cpg: clock-controller@11010000 {
870 compatible = "renesas, 870 compatible = "renesas,r9a07g044-cpg";
871 reg = <0 0x11010000 0 871 reg = <0 0x11010000 0 0x10000>;
872 clocks = <&extal_clk>; 872 clocks = <&extal_clk>;
873 clock-names = "extal"; 873 clock-names = "extal";
874 #clock-cells = <2>; 874 #clock-cells = <2>;
875 #reset-cells = <1>; 875 #reset-cells = <1>;
876 #power-domain-cells = 876 #power-domain-cells = <0>;
877 }; 877 };
878 878
879 sysc: system-controller@110200 879 sysc: system-controller@11020000 {
880 compatible = "renesas, 880 compatible = "renesas,r9a07g044-sysc";
881 reg = <0 0x11020000 0 881 reg = <0 0x11020000 0 0x10000>;
882 interrupts = <GIC_SPI 882 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
883 <GIC_SPI 883 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
884 <GIC_SPI 884 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
885 <GIC_SPI 885 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
886 interrupt-names = "lpm 886 interrupt-names = "lpm_int", "ca55stbydone_int",
887 "cm3 887 "cm33stbyr_int", "ca55_deny";
888 status = "disabled"; 888 status = "disabled";
889 }; 889 };
890 890
891 pinctrl: pinctrl@11030000 { 891 pinctrl: pinctrl@11030000 {
892 compatible = "renesas, 892 compatible = "renesas,r9a07g044-pinctrl";
893 reg = <0 0x11030000 0 893 reg = <0 0x11030000 0 0x10000>;
894 gpio-controller; 894 gpio-controller;
895 #gpio-cells = <2>; 895 #gpio-cells = <2>;
896 #interrupt-cells = <2> 896 #interrupt-cells = <2>;
897 interrupt-parent = <&i 897 interrupt-parent = <&irqc>;
898 interrupt-controller; 898 interrupt-controller;
899 gpio-ranges = <&pinctr 899 gpio-ranges = <&pinctrl 0 0 392>;
900 clocks = <&cpg CPG_MOD 900 clocks = <&cpg CPG_MOD R9A07G044_GPIO_HCLK>;
901 power-domains = <&cpg> 901 power-domains = <&cpg>;
902 resets = <&cpg R9A07G0 902 resets = <&cpg R9A07G044_GPIO_RSTN>,
903 <&cpg R9A07G0 903 <&cpg R9A07G044_GPIO_PORT_RESETN>,
904 <&cpg R9A07G0 904 <&cpg R9A07G044_GPIO_SPARE_RESETN>;
905 }; 905 };
906 906
907 irqc: interrupt-controller@110 907 irqc: interrupt-controller@110a0000 {
908 compatible = "renesas, 908 compatible = "renesas,r9a07g044-irqc",
909 "renesas, 909 "renesas,rzg2l-irqc";
910 #interrupt-cells = <2> 910 #interrupt-cells = <2>;
911 #address-cells = <0>; 911 #address-cells = <0>;
912 interrupt-controller; 912 interrupt-controller;
913 reg = <0 0x110a0000 0 913 reg = <0 0x110a0000 0 0x10000>;
914 interrupts = <GIC_SPI 914 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
915 <GIC_SPI 915 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
916 <GIC_SPI 916 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
917 <GIC_SPI 917 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
918 <GIC_SPI 918 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
919 <GIC_SPI 919 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
920 <GIC_SPI 920 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
921 <GIC_SPI 921 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
922 <GIC_SPI 922 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
923 <GIC_SPI 923 <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>,
924 <GIC_SPI 924 <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>,
925 <GIC_SPI 925 <GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>,
926 <GIC_SPI 926 <GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>,
927 <GIC_SPI 927 <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>,
928 <GIC_SPI 928 <GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>,
929 <GIC_SPI 929 <GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH>,
930 <GIC_SPI 930 <GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>,
931 <GIC_SPI 931 <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>,
932 <GIC_SPI 932 <GIC_SPI 453 IRQ_TYPE_LEVEL_HIGH>,
933 <GIC_SPI 933 <GIC_SPI 454 IRQ_TYPE_LEVEL_HIGH>,
934 <GIC_SPI 934 <GIC_SPI 455 IRQ_TYPE_LEVEL_HIGH>,
935 <GIC_SPI 935 <GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>,
936 <GIC_SPI 936 <GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>,
937 <GIC_SPI 937 <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>,
938 <GIC_SPI 938 <GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>,
939 <GIC_SPI 939 <GIC_SPI 460 IRQ_TYPE_LEVEL_HIGH>,
940 <GIC_SPI 940 <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>,
941 <GIC_SPI 941 <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>,
942 <GIC_SPI 942 <GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH>,
943 <GIC_SPI 943 <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>,
944 <GIC_SPI 944 <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>,
945 <GIC_SPI 945 <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>,
946 <GIC_SPI 946 <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>,
947 <GIC_SPI 947 <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>,
948 <GIC_SPI 948 <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>,
949 <GIC_SPI 949 <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>,
950 <GIC_SPI 950 <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>,
951 <GIC_SPI 951 <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>,
952 <GIC_SPI 952 <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>,
953 <GIC_SPI 953 <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>,
954 <GIC_SPI 954 <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>,
955 <GIC_SPI 955 <GIC_SPI 25 IRQ_TYPE_EDGE_RISING>,
956 <GIC_SPI 956 <GIC_SPI 34 IRQ_TYPE_EDGE_RISING>,
957 <GIC_SPI 957 <GIC_SPI 35 IRQ_TYPE_EDGE_RISING>,
958 <GIC_SPI 958 <GIC_SPI 36 IRQ_TYPE_EDGE_RISING>,
959 <GIC_SPI 959 <GIC_SPI 37 IRQ_TYPE_EDGE_RISING>,
960 <GIC_SPI 960 <GIC_SPI 38 IRQ_TYPE_EDGE_RISING>,
961 <GIC_SPI 961 <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>;
962 interrupt-names = "nmi 962 interrupt-names = "nmi", "irq0", "irq1", "irq2", "irq3",
963 "irq 963 "irq4", "irq5", "irq6", "irq7",
964 "tin 964 "tint0", "tint1", "tint2", "tint3",
965 "tin 965 "tint4", "tint5", "tint6", "tint7",
966 "tin 966 "tint8", "tint9", "tint10", "tint11",
967 "tin 967 "tint12", "tint13", "tint14", "tint15",
968 "tin 968 "tint16", "tint17", "tint18", "tint19",
969 "tin 969 "tint20", "tint21", "tint22", "tint23",
970 "tin 970 "tint24", "tint25", "tint26", "tint27",
971 "tin 971 "tint28", "tint29", "tint30", "tint31",
972 "bus 972 "bus-err", "ec7tie1-0", "ec7tie2-0",
973 "ec7 973 "ec7tiovf-0", "ec7tie1-1", "ec7tie2-1",
974 "ec7 974 "ec7tiovf-1";
975 clocks = <&cpg CPG_MOD 975 clocks = <&cpg CPG_MOD R9A07G044_IA55_CLK>,
976 <&cpg CPG_MOD 976 <&cpg CPG_MOD R9A07G044_IA55_PCLK>;
977 clock-names = "clk", " 977 clock-names = "clk", "pclk";
978 power-domains = <&cpg> 978 power-domains = <&cpg>;
979 resets = <&cpg R9A07G0 979 resets = <&cpg R9A07G044_IA55_RESETN>;
980 }; 980 };
981 981
982 dmac: dma-controller@11820000 982 dmac: dma-controller@11820000 {
983 compatible = "renesas, 983 compatible = "renesas,r9a07g044-dmac",
984 "renesas, 984 "renesas,rz-dmac";
985 reg = <0 0x11820000 0 985 reg = <0 0x11820000 0 0x10000>,
986 <0 0x11830000 0 986 <0 0x11830000 0 0x10000>;
987 interrupts = <GIC_SPI 987 interrupts = <GIC_SPI 141 IRQ_TYPE_EDGE_RISING>,
988 <GIC_SPI 988 <GIC_SPI 125 IRQ_TYPE_EDGE_RISING>,
989 <GIC_SPI 989 <GIC_SPI 126 IRQ_TYPE_EDGE_RISING>,
990 <GIC_SPI 990 <GIC_SPI 127 IRQ_TYPE_EDGE_RISING>,
991 <GIC_SPI 991 <GIC_SPI 128 IRQ_TYPE_EDGE_RISING>,
992 <GIC_SPI 992 <GIC_SPI 129 IRQ_TYPE_EDGE_RISING>,
993 <GIC_SPI 993 <GIC_SPI 130 IRQ_TYPE_EDGE_RISING>,
994 <GIC_SPI 994 <GIC_SPI 131 IRQ_TYPE_EDGE_RISING>,
995 <GIC_SPI 995 <GIC_SPI 132 IRQ_TYPE_EDGE_RISING>,
996 <GIC_SPI 996 <GIC_SPI 133 IRQ_TYPE_EDGE_RISING>,
997 <GIC_SPI 997 <GIC_SPI 134 IRQ_TYPE_EDGE_RISING>,
998 <GIC_SPI 998 <GIC_SPI 135 IRQ_TYPE_EDGE_RISING>,
999 <GIC_SPI 999 <GIC_SPI 136 IRQ_TYPE_EDGE_RISING>,
1000 <GIC_SPI 1000 <GIC_SPI 137 IRQ_TYPE_EDGE_RISING>,
1001 <GIC_SPI 1001 <GIC_SPI 138 IRQ_TYPE_EDGE_RISING>,
1002 <GIC_SPI 1002 <GIC_SPI 139 IRQ_TYPE_EDGE_RISING>,
1003 <GIC_SPI 1003 <GIC_SPI 140 IRQ_TYPE_EDGE_RISING>;
1004 interrupt-names = "er 1004 interrupt-names = "error",
1005 "ch 1005 "ch0", "ch1", "ch2", "ch3",
1006 "ch 1006 "ch4", "ch5", "ch6", "ch7",
1007 "ch 1007 "ch8", "ch9", "ch10", "ch11",
1008 "ch 1008 "ch12", "ch13", "ch14", "ch15";
1009 clocks = <&cpg CPG_MO 1009 clocks = <&cpg CPG_MOD R9A07G044_DMAC_ACLK>,
1010 <&cpg CPG_MO 1010 <&cpg CPG_MOD R9A07G044_DMAC_PCLK>;
1011 clock-names = "main", 1011 clock-names = "main", "register";
1012 power-domains = <&cpg 1012 power-domains = <&cpg>;
1013 resets = <&cpg R9A07G 1013 resets = <&cpg R9A07G044_DMAC_ARESETN>,
1014 <&cpg R9A07G 1014 <&cpg R9A07G044_DMAC_RST_ASYNC>;
1015 reset-names = "arst", 1015 reset-names = "arst", "rst_async";
1016 #dma-cells = <1>; 1016 #dma-cells = <1>;
1017 dma-channels = <16>; 1017 dma-channels = <16>;
1018 }; 1018 };
1019 1019
1020 gpu: gpu@11840000 { 1020 gpu: gpu@11840000 {
1021 compatible = "renesas 1021 compatible = "renesas,r9a07g044-mali",
1022 "arm,mal 1022 "arm,mali-bifrost";
1023 reg = <0x0 0x11840000 1023 reg = <0x0 0x11840000 0x0 0x10000>;
1024 interrupts = <GIC_SPI 1024 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
1025 <GIC_SPI 1025 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
1026 <GIC_SPI 1026 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
1027 <GIC_SPI 1027 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
1028 interrupt-names = "jo 1028 interrupt-names = "job", "mmu", "gpu", "event";
1029 clocks = <&cpg CPG_MO 1029 clocks = <&cpg CPG_MOD R9A07G044_GPU_CLK>,
1030 <&cpg CPG_MO 1030 <&cpg CPG_MOD R9A07G044_GPU_AXI_CLK>,
1031 <&cpg CPG_MO 1031 <&cpg CPG_MOD R9A07G044_GPU_ACE_CLK>;
1032 clock-names = "gpu", 1032 clock-names = "gpu", "bus", "bus_ace";
1033 power-domains = <&cpg 1033 power-domains = <&cpg>;
1034 resets = <&cpg R9A07G 1034 resets = <&cpg R9A07G044_GPU_RESETN>,
1035 <&cpg R9A07G 1035 <&cpg R9A07G044_GPU_AXI_RESETN>,
1036 <&cpg R9A07G 1036 <&cpg R9A07G044_GPU_ACE_RESETN>;
1037 reset-names = "rst", 1037 reset-names = "rst", "axi_rst", "ace_rst";
1038 operating-points-v2 = 1038 operating-points-v2 = <&gpu_opp_table>;
1039 }; 1039 };
1040 1040
1041 gic: interrupt-controller@119 1041 gic: interrupt-controller@11900000 {
1042 compatible = "arm,gic 1042 compatible = "arm,gic-v3";
1043 #interrupt-cells = <3 1043 #interrupt-cells = <3>;
1044 #address-cells = <0>; 1044 #address-cells = <0>;
1045 interrupt-controller; 1045 interrupt-controller;
1046 reg = <0x0 0x11900000 1046 reg = <0x0 0x11900000 0 0x20000>,
1047 <0x0 0x11940000 1047 <0x0 0x11940000 0 0x40000>;
1048 interrupts = <GIC_PPI 1048 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
1049 }; 1049 };
1050 1050
1051 sdhi0: mmc@11c00000 { 1051 sdhi0: mmc@11c00000 {
1052 compatible = "renesas 1052 compatible = "renesas,sdhi-r9a07g044",
1053 "renesas !! 1053 "renesas,rcar-gen3-sdhi";
1054 reg = <0x0 0x11c00000 1054 reg = <0x0 0x11c00000 0 0x10000>;
1055 interrupts = <GIC_SPI 1055 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
1056 <GIC_SPI 1056 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
1057 clocks = <&cpg CPG_MO 1057 clocks = <&cpg CPG_MOD R9A07G044_SDHI0_IMCLK>,
1058 <&cpg CPG_MO 1058 <&cpg CPG_MOD R9A07G044_SDHI0_CLK_HS>,
1059 <&cpg CPG_MO 1059 <&cpg CPG_MOD R9A07G044_SDHI0_IMCLK2>,
1060 <&cpg CPG_MO 1060 <&cpg CPG_MOD R9A07G044_SDHI0_ACLK>;
1061 clock-names = "core", 1061 clock-names = "core", "clkh", "cd", "aclk";
1062 resets = <&cpg R9A07G 1062 resets = <&cpg R9A07G044_SDHI0_IXRST>;
1063 power-domains = <&cpg 1063 power-domains = <&cpg>;
1064 status = "disabled"; 1064 status = "disabled";
1065 }; 1065 };
1066 1066
1067 sdhi1: mmc@11c10000 { 1067 sdhi1: mmc@11c10000 {
1068 compatible = "renesas 1068 compatible = "renesas,sdhi-r9a07g044",
1069 "renesas !! 1069 "renesas,rcar-gen3-sdhi";
1070 reg = <0x0 0x11c10000 1070 reg = <0x0 0x11c10000 0 0x10000>;
1071 interrupts = <GIC_SPI 1071 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
1072 <GIC_SPI 1072 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
1073 clocks = <&cpg CPG_MO 1073 clocks = <&cpg CPG_MOD R9A07G044_SDHI1_IMCLK>,
1074 <&cpg CPG_MO 1074 <&cpg CPG_MOD R9A07G044_SDHI1_CLK_HS>,
1075 <&cpg CPG_MO 1075 <&cpg CPG_MOD R9A07G044_SDHI1_IMCLK2>,
1076 <&cpg CPG_MO 1076 <&cpg CPG_MOD R9A07G044_SDHI1_ACLK>;
1077 clock-names = "core", 1077 clock-names = "core", "clkh", "cd", "aclk";
1078 resets = <&cpg R9A07G 1078 resets = <&cpg R9A07G044_SDHI1_IXRST>;
1079 power-domains = <&cpg 1079 power-domains = <&cpg>;
1080 status = "disabled"; 1080 status = "disabled";
1081 }; 1081 };
1082 1082
1083 eth0: ethernet@11c20000 { 1083 eth0: ethernet@11c20000 {
1084 compatible = "renesas 1084 compatible = "renesas,r9a07g044-gbeth",
1085 "renesas 1085 "renesas,rzg2l-gbeth";
1086 reg = <0 0x11c20000 0 1086 reg = <0 0x11c20000 0 0x10000>;
1087 interrupts = <GIC_SPI 1087 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
1088 <GIC_SPI 1088 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
1089 <GIC_SPI 1089 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
1090 interrupt-names = "mu 1090 interrupt-names = "mux", "fil", "arp_ns";
1091 phy-mode = "rgmii"; 1091 phy-mode = "rgmii";
1092 clocks = <&cpg CPG_MO 1092 clocks = <&cpg CPG_MOD R9A07G044_ETH0_CLK_AXI>,
1093 <&cpg CPG_MO 1093 <&cpg CPG_MOD R9A07G044_ETH0_CLK_CHI>,
1094 <&cpg CPG_CO 1094 <&cpg CPG_CORE R9A07G044_CLK_HP>;
1095 clock-names = "axi", 1095 clock-names = "axi", "chi", "refclk";
1096 resets = <&cpg R9A07G 1096 resets = <&cpg R9A07G044_ETH0_RST_HW_N>;
1097 power-domains = <&cpg 1097 power-domains = <&cpg>;
1098 #address-cells = <1>; 1098 #address-cells = <1>;
1099 #size-cells = <0>; 1099 #size-cells = <0>;
1100 status = "disabled"; 1100 status = "disabled";
1101 }; 1101 };
1102 1102
1103 eth1: ethernet@11c30000 { 1103 eth1: ethernet@11c30000 {
1104 compatible = "renesas 1104 compatible = "renesas,r9a07g044-gbeth",
1105 "renesas 1105 "renesas,rzg2l-gbeth";
1106 reg = <0 0x11c30000 0 1106 reg = <0 0x11c30000 0 0x10000>;
1107 interrupts = <GIC_SPI 1107 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
1108 <GIC_SPI 1108 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
1109 <GIC_SPI 1109 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
1110 interrupt-names = "mu 1110 interrupt-names = "mux", "fil", "arp_ns";
1111 phy-mode = "rgmii"; 1111 phy-mode = "rgmii";
1112 clocks = <&cpg CPG_MO 1112 clocks = <&cpg CPG_MOD R9A07G044_ETH1_CLK_AXI>,
1113 <&cpg CPG_MO 1113 <&cpg CPG_MOD R9A07G044_ETH1_CLK_CHI>,
1114 <&cpg CPG_CO 1114 <&cpg CPG_CORE R9A07G044_CLK_HP>;
1115 clock-names = "axi", 1115 clock-names = "axi", "chi", "refclk";
1116 resets = <&cpg R9A07G 1116 resets = <&cpg R9A07G044_ETH1_RST_HW_N>;
1117 power-domains = <&cpg 1117 power-domains = <&cpg>;
1118 #address-cells = <1>; 1118 #address-cells = <1>;
1119 #size-cells = <0>; 1119 #size-cells = <0>;
1120 status = "disabled"; 1120 status = "disabled";
1121 }; 1121 };
1122 1122
1123 phyrst: usbphy-ctrl@11c40000 1123 phyrst: usbphy-ctrl@11c40000 {
1124 compatible = "renesas 1124 compatible = "renesas,r9a07g044-usbphy-ctrl",
1125 "renesas 1125 "renesas,rzg2l-usbphy-ctrl";
1126 reg = <0 0x11c40000 0 1126 reg = <0 0x11c40000 0 0x10000>;
1127 clocks = <&cpg CPG_MO 1127 clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>;
1128 resets = <&cpg R9A07G 1128 resets = <&cpg R9A07G044_USB_PRESETN>;
1129 power-domains = <&cpg 1129 power-domains = <&cpg>;
1130 #reset-cells = <1>; 1130 #reset-cells = <1>;
1131 status = "disabled"; 1131 status = "disabled";
1132 <<
1133 usb0_vbus_otg: regula <<
1134 regulator-nam <<
1135 }; <<
1136 }; 1132 };
1137 1133
1138 ohci0: usb@11c50000 { 1134 ohci0: usb@11c50000 {
1139 compatible = "generic 1135 compatible = "generic-ohci";
1140 reg = <0 0x11c50000 0 1136 reg = <0 0x11c50000 0 0x100>;
1141 interrupts = <GIC_SPI 1137 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
1142 clocks = <&cpg CPG_MO 1138 clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>,
1143 <&cpg CPG_MO 1139 <&cpg CPG_MOD R9A07G044_USB_U2H0_HCLK>;
1144 resets = <&phyrst 0>, 1140 resets = <&phyrst 0>,
1145 <&cpg R9A07G 1141 <&cpg R9A07G044_USB_U2H0_HRESETN>;
1146 phys = <&usb2_phy0 1> 1142 phys = <&usb2_phy0 1>;
1147 phy-names = "usb"; 1143 phy-names = "usb";
1148 power-domains = <&cpg 1144 power-domains = <&cpg>;
1149 status = "disabled"; 1145 status = "disabled";
1150 }; 1146 };
1151 1147
1152 ohci1: usb@11c70000 { 1148 ohci1: usb@11c70000 {
1153 compatible = "generic 1149 compatible = "generic-ohci";
1154 reg = <0 0x11c70000 0 1150 reg = <0 0x11c70000 0 0x100>;
1155 interrupts = <GIC_SPI 1151 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
1156 clocks = <&cpg CPG_MO 1152 clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>,
1157 <&cpg CPG_MO 1153 <&cpg CPG_MOD R9A07G044_USB_U2H1_HCLK>;
1158 resets = <&phyrst 1>, 1154 resets = <&phyrst 1>,
1159 <&cpg R9A07G 1155 <&cpg R9A07G044_USB_U2H1_HRESETN>;
1160 phys = <&usb2_phy1 1> 1156 phys = <&usb2_phy1 1>;
1161 phy-names = "usb"; 1157 phy-names = "usb";
1162 power-domains = <&cpg 1158 power-domains = <&cpg>;
1163 status = "disabled"; 1159 status = "disabled";
1164 }; 1160 };
1165 1161
1166 ehci0: usb@11c50100 { 1162 ehci0: usb@11c50100 {
1167 compatible = "generic 1163 compatible = "generic-ehci";
1168 reg = <0 0x11c50100 0 1164 reg = <0 0x11c50100 0 0x100>;
1169 interrupts = <GIC_SPI 1165 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
1170 clocks = <&cpg CPG_MO 1166 clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>,
1171 <&cpg CPG_MO 1167 <&cpg CPG_MOD R9A07G044_USB_U2H0_HCLK>;
1172 resets = <&phyrst 0>, 1168 resets = <&phyrst 0>,
1173 <&cpg R9A07G 1169 <&cpg R9A07G044_USB_U2H0_HRESETN>;
1174 phys = <&usb2_phy0 2> 1170 phys = <&usb2_phy0 2>;
1175 phy-names = "usb"; 1171 phy-names = "usb";
1176 companion = <&ohci0>; 1172 companion = <&ohci0>;
1177 power-domains = <&cpg 1173 power-domains = <&cpg>;
1178 status = "disabled"; 1174 status = "disabled";
1179 }; 1175 };
1180 1176
1181 ehci1: usb@11c70100 { 1177 ehci1: usb@11c70100 {
1182 compatible = "generic 1178 compatible = "generic-ehci";
1183 reg = <0 0x11c70100 0 1179 reg = <0 0x11c70100 0 0x100>;
1184 interrupts = <GIC_SPI 1180 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
1185 clocks = <&cpg CPG_MO 1181 clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>,
1186 <&cpg CPG_MO 1182 <&cpg CPG_MOD R9A07G044_USB_U2H1_HCLK>;
1187 resets = <&phyrst 1>, 1183 resets = <&phyrst 1>,
1188 <&cpg R9A07G 1184 <&cpg R9A07G044_USB_U2H1_HRESETN>;
1189 phys = <&usb2_phy1 2> 1185 phys = <&usb2_phy1 2>;
1190 phy-names = "usb"; 1186 phy-names = "usb";
1191 companion = <&ohci1>; 1187 companion = <&ohci1>;
1192 power-domains = <&cpg 1188 power-domains = <&cpg>;
1193 status = "disabled"; 1189 status = "disabled";
1194 }; 1190 };
1195 1191
1196 usb2_phy0: usb-phy@11c50200 { 1192 usb2_phy0: usb-phy@11c50200 {
1197 compatible = "renesas 1193 compatible = "renesas,usb2-phy-r9a07g044",
1198 "renesas 1194 "renesas,rzg2l-usb2-phy";
1199 reg = <0 0x11c50200 0 1195 reg = <0 0x11c50200 0 0x700>;
1200 interrupts = <GIC_SPI 1196 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
1201 clocks = <&cpg CPG_MO 1197 clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>,
1202 <&cpg CPG_MO 1198 <&cpg CPG_MOD R9A07G044_USB_U2H0_HCLK>;
1203 resets = <&phyrst 0>; 1199 resets = <&phyrst 0>;
1204 #phy-cells = <1>; 1200 #phy-cells = <1>;
1205 power-domains = <&cpg 1201 power-domains = <&cpg>;
1206 status = "disabled"; 1202 status = "disabled";
1207 }; 1203 };
1208 1204
1209 usb2_phy1: usb-phy@11c70200 { 1205 usb2_phy1: usb-phy@11c70200 {
1210 compatible = "renesas 1206 compatible = "renesas,usb2-phy-r9a07g044",
1211 "renesas 1207 "renesas,rzg2l-usb2-phy";
1212 reg = <0 0x11c70200 0 1208 reg = <0 0x11c70200 0 0x700>;
1213 interrupts = <GIC_SPI 1209 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
1214 clocks = <&cpg CPG_MO 1210 clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>,
1215 <&cpg CPG_MO 1211 <&cpg CPG_MOD R9A07G044_USB_U2H1_HCLK>;
1216 resets = <&phyrst 1>; 1212 resets = <&phyrst 1>;
1217 #phy-cells = <1>; 1213 #phy-cells = <1>;
1218 power-domains = <&cpg 1214 power-domains = <&cpg>;
1219 status = "disabled"; 1215 status = "disabled";
1220 }; 1216 };
1221 1217
1222 hsusb: usb@11c60000 { 1218 hsusb: usb@11c60000 {
1223 compatible = "renesas 1219 compatible = "renesas,usbhs-r9a07g044",
1224 "renesas 1220 "renesas,rzg2l-usbhs";
1225 reg = <0 0x11c60000 0 1221 reg = <0 0x11c60000 0 0x10000>;
1226 interrupts = <GIC_SPI 1222 interrupts = <GIC_SPI 100 IRQ_TYPE_EDGE_RISING>,
1227 <GIC_SPI 1223 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
1228 <GIC_SPI 1224 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
1229 <GIC_SPI 1225 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
1230 clocks = <&cpg CPG_MO 1226 clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>,
1231 <&cpg CPG_MO 1227 <&cpg CPG_MOD R9A07G044_USB_U2P_EXR_CPUCLK>;
1232 resets = <&phyrst 0>, 1228 resets = <&phyrst 0>,
1233 <&cpg R9A07G 1229 <&cpg R9A07G044_USB_U2P_EXL_SYSRST>;
1234 renesas,buswait = <7> 1230 renesas,buswait = <7>;
1235 phys = <&usb2_phy0 3> 1231 phys = <&usb2_phy0 3>;
1236 phy-names = "usb"; 1232 phy-names = "usb";
1237 power-domains = <&cpg 1233 power-domains = <&cpg>;
1238 status = "disabled"; 1234 status = "disabled";
1239 }; 1235 };
1240 1236
1241 wdt0: watchdog@12800800 { 1237 wdt0: watchdog@12800800 {
1242 compatible = "renesas 1238 compatible = "renesas,r9a07g044-wdt",
1243 "renesas 1239 "renesas,rzg2l-wdt";
1244 reg = <0 0x12800800 0 1240 reg = <0 0x12800800 0 0x400>;
1245 clocks = <&cpg CPG_MO 1241 clocks = <&cpg CPG_MOD R9A07G044_WDT0_PCLK>,
1246 <&cpg CPG_MO 1242 <&cpg CPG_MOD R9A07G044_WDT0_CLK>;
1247 clock-names = "pclk", 1243 clock-names = "pclk", "oscclk";
1248 interrupts = <GIC_SPI 1244 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
1249 <GIC_SPI 1245 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
1250 interrupt-names = "wd 1246 interrupt-names = "wdt", "perrout";
1251 resets = <&cpg R9A07G 1247 resets = <&cpg R9A07G044_WDT0_PRESETN>;
1252 power-domains = <&cpg 1248 power-domains = <&cpg>;
1253 status = "disabled"; 1249 status = "disabled";
1254 }; 1250 };
1255 1251
1256 wdt1: watchdog@12800c00 { 1252 wdt1: watchdog@12800c00 {
1257 compatible = "renesas 1253 compatible = "renesas,r9a07g044-wdt",
1258 "renesas 1254 "renesas,rzg2l-wdt";
1259 reg = <0 0x12800C00 0 1255 reg = <0 0x12800C00 0 0x400>;
1260 clocks = <&cpg CPG_MO 1256 clocks = <&cpg CPG_MOD R9A07G044_WDT1_PCLK>,
1261 <&cpg CPG_MO 1257 <&cpg CPG_MOD R9A07G044_WDT1_CLK>;
1262 clock-names = "pclk", 1258 clock-names = "pclk", "oscclk";
1263 interrupts = <GIC_SPI 1259 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
1264 <GIC_SPI 1260 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
1265 interrupt-names = "wd 1261 interrupt-names = "wdt", "perrout";
1266 resets = <&cpg R9A07G 1262 resets = <&cpg R9A07G044_WDT1_PRESETN>;
1267 power-domains = <&cpg 1263 power-domains = <&cpg>;
1268 status = "disabled"; 1264 status = "disabled";
1269 }; 1265 };
1270 1266
1271 ostm0: timer@12801000 { 1267 ostm0: timer@12801000 {
1272 compatible = "renesas 1268 compatible = "renesas,r9a07g044-ostm",
1273 "renesas 1269 "renesas,ostm";
1274 reg = <0x0 0x12801000 1270 reg = <0x0 0x12801000 0x0 0x400>;
1275 interrupts = <GIC_SPI 1271 interrupts = <GIC_SPI 46 IRQ_TYPE_EDGE_RISING>;
1276 clocks = <&cpg CPG_MO 1272 clocks = <&cpg CPG_MOD R9A07G044_OSTM0_PCLK>;
1277 resets = <&cpg R9A07G 1273 resets = <&cpg R9A07G044_OSTM0_PRESETZ>;
1278 power-domains = <&cpg 1274 power-domains = <&cpg>;
1279 status = "disabled"; 1275 status = "disabled";
1280 }; 1276 };
1281 1277
1282 ostm1: timer@12801400 { 1278 ostm1: timer@12801400 {
1283 compatible = "renesas 1279 compatible = "renesas,r9a07g044-ostm",
1284 "renesas 1280 "renesas,ostm";
1285 reg = <0x0 0x12801400 1281 reg = <0x0 0x12801400 0x0 0x400>;
1286 interrupts = <GIC_SPI 1282 interrupts = <GIC_SPI 47 IRQ_TYPE_EDGE_RISING>;
1287 clocks = <&cpg CPG_MO 1283 clocks = <&cpg CPG_MOD R9A07G044_OSTM1_PCLK>;
1288 resets = <&cpg R9A07G 1284 resets = <&cpg R9A07G044_OSTM1_PRESETZ>;
1289 power-domains = <&cpg 1285 power-domains = <&cpg>;
1290 status = "disabled"; 1286 status = "disabled";
1291 }; 1287 };
1292 1288
1293 ostm2: timer@12801800 { 1289 ostm2: timer@12801800 {
1294 compatible = "renesas 1290 compatible = "renesas,r9a07g044-ostm",
1295 "renesas 1291 "renesas,ostm";
1296 reg = <0x0 0x12801800 1292 reg = <0x0 0x12801800 0x0 0x400>;
1297 interrupts = <GIC_SPI 1293 interrupts = <GIC_SPI 48 IRQ_TYPE_EDGE_RISING>;
1298 clocks = <&cpg CPG_MO 1294 clocks = <&cpg CPG_MOD R9A07G044_OSTM2_PCLK>;
1299 resets = <&cpg R9A07G 1295 resets = <&cpg R9A07G044_OSTM2_PRESETZ>;
1300 power-domains = <&cpg 1296 power-domains = <&cpg>;
1301 status = "disabled"; 1297 status = "disabled";
1302 }; 1298 };
1303 }; 1299 };
1304 1300
1305 thermal-zones { 1301 thermal-zones {
1306 cpu-thermal { 1302 cpu-thermal {
1307 polling-delay-passive 1303 polling-delay-passive = <250>;
1308 polling-delay = <1000 1304 polling-delay = <1000>;
1309 thermal-sensors = <&t 1305 thermal-sensors = <&tsu 0>;
1310 sustainable-power = < 1306 sustainable-power = <717>;
1311 1307
1312 cooling-maps { 1308 cooling-maps {
1313 map0 { 1309 map0 {
1314 trip 1310 trip = <&target>;
1315 cooli 1311 cooling-device = <&cpu0 0 2>;
1316 contr 1312 contribution = <1024>;
1317 }; 1313 };
1318 }; 1314 };
1319 1315
1320 trips { 1316 trips {
1321 sensor_crit: 1317 sensor_crit: sensor-crit {
1322 tempe 1318 temperature = <125000>;
1323 hyste 1319 hysteresis = <1000>;
1324 type 1320 type = "critical";
1325 }; 1321 };
1326 1322
1327 target: trip- 1323 target: trip-point {
1328 tempe 1324 temperature = <100000>;
1329 hyste 1325 hysteresis = <1000>;
1330 type 1326 type = "passive";
1331 }; 1327 };
1332 }; 1328 };
1333 }; 1329 };
1334 }; 1330 };
1335 1331
1336 timer { 1332 timer {
1337 compatible = "arm,armv8-timer 1333 compatible = "arm,armv8-timer";
1338 interrupts-extended = <&gic G 1334 interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
1339 <&gic G 1335 <&gic GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
1340 <&gic G 1336 <&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
1341 <&gic G 1337 <&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>,
1342 <&gic G 1338 <&gic GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>;
1343 interrupt-names = "sec-phys", 1339 interrupt-names = "sec-phys", "phys", "virt", "hyp-phys",
1344 "hyp-virt"; 1340 "hyp-virt";
1345 }; 1341 };
1346 }; 1342 };
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