1 // SPDX-License-Identifier: (GPL-2.0-only OR B 1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 /* 2 /*
3 * Device Tree Source for the RZ/G2L and RZ/G2 3 * Device Tree Source for the RZ/G2L and RZ/G2LC common SoC parts
4 * 4 *
5 * Copyright (C) 2021 Renesas Electronics Corp 5 * Copyright (C) 2021 Renesas Electronics Corp.
6 */ 6 */
7 7
8 #include <dt-bindings/interrupt-controller/arm 8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/clock/r9a07g044-cpg.h> 9 #include <dt-bindings/clock/r9a07g044-cpg.h>
10 10
11 / { 11 / {
12 compatible = "renesas,r9a07g044"; 12 compatible = "renesas,r9a07g044";
13 #address-cells = <2>; 13 #address-cells = <2>;
14 #size-cells = <2>; 14 #size-cells = <2>;
15 15
16 audio_clk1: audio1-clk { 16 audio_clk1: audio1-clk {
17 compatible = "fixed-clock"; 17 compatible = "fixed-clock";
18 #clock-cells = <0>; 18 #clock-cells = <0>;
19 /* This value must be overridd 19 /* This value must be overridden by boards that provide it */
20 clock-frequency = <0>; 20 clock-frequency = <0>;
21 }; 21 };
22 22
23 audio_clk2: audio2-clk { 23 audio_clk2: audio2-clk {
24 compatible = "fixed-clock"; 24 compatible = "fixed-clock";
25 #clock-cells = <0>; 25 #clock-cells = <0>;
26 /* This value must be overridd 26 /* This value must be overridden by boards that provide it */
27 clock-frequency = <0>; 27 clock-frequency = <0>;
28 }; 28 };
29 29
30 /* External CAN clock - to be overridd 30 /* External CAN clock - to be overridden by boards that provide it */
31 can_clk: can-clk { 31 can_clk: can-clk {
32 compatible = "fixed-clock"; 32 compatible = "fixed-clock";
33 #clock-cells = <0>; 33 #clock-cells = <0>;
34 clock-frequency = <0>; 34 clock-frequency = <0>;
35 }; 35 };
36 36
37 /* clock can be either from exclk or c 37 /* clock can be either from exclk or crystal oscillator (XIN/XOUT) */
38 extal_clk: extal-clk { 38 extal_clk: extal-clk {
39 compatible = "fixed-clock"; 39 compatible = "fixed-clock";
40 #clock-cells = <0>; 40 #clock-cells = <0>;
41 /* This value must be overridd 41 /* This value must be overridden by the board */
42 clock-frequency = <0>; 42 clock-frequency = <0>;
43 }; 43 };
44 44
45 cluster0_opp: opp-table-0 { 45 cluster0_opp: opp-table-0 {
46 compatible = "operating-points 46 compatible = "operating-points-v2";
47 opp-shared; 47 opp-shared;
48 48
49 opp-150000000 { 49 opp-150000000 {
50 opp-hz = /bits/ 64 <15 50 opp-hz = /bits/ 64 <150000000>;
51 opp-microvolt = <11000 51 opp-microvolt = <1100000>;
52 clock-latency-ns = <30 52 clock-latency-ns = <300000>;
53 }; 53 };
54 opp-300000000 { 54 opp-300000000 {
55 opp-hz = /bits/ 64 <30 55 opp-hz = /bits/ 64 <300000000>;
56 opp-microvolt = <11000 56 opp-microvolt = <1100000>;
57 clock-latency-ns = <30 57 clock-latency-ns = <300000>;
58 }; 58 };
59 opp-600000000 { 59 opp-600000000 {
60 opp-hz = /bits/ 64 <60 60 opp-hz = /bits/ 64 <600000000>;
61 opp-microvolt = <11000 61 opp-microvolt = <1100000>;
62 clock-latency-ns = <30 62 clock-latency-ns = <300000>;
63 }; 63 };
64 opp-1200000000 { 64 opp-1200000000 {
65 opp-hz = /bits/ 64 <12 65 opp-hz = /bits/ 64 <1200000000>;
66 opp-microvolt = <11000 66 opp-microvolt = <1100000>;
67 clock-latency-ns = <30 67 clock-latency-ns = <300000>;
68 opp-suspend; 68 opp-suspend;
69 }; 69 };
70 }; 70 };
71 71
72 cpus { 72 cpus {
73 #address-cells = <1>; 73 #address-cells = <1>;
74 #size-cells = <0>; 74 #size-cells = <0>;
75 75
76 cpu-map { 76 cpu-map {
77 cluster0 { 77 cluster0 {
78 core0 { 78 core0 {
79 cpu = 79 cpu = <&cpu0>;
80 }; 80 };
81 core1 { 81 core1 {
82 cpu = 82 cpu = <&cpu1>;
83 }; 83 };
84 }; 84 };
85 }; 85 };
86 86
87 cpu0: cpu@0 { 87 cpu0: cpu@0 {
88 compatible = "arm,cort 88 compatible = "arm,cortex-a55";
89 reg = <0>; 89 reg = <0>;
90 device_type = "cpu"; 90 device_type = "cpu";
91 #cooling-cells = <2>; 91 #cooling-cells = <2>;
92 next-level-cache = <&L 92 next-level-cache = <&L3_CA55>;
93 enable-method = "psci" 93 enable-method = "psci";
94 clocks = <&cpg CPG_COR 94 clocks = <&cpg CPG_CORE R9A07G044_CLK_I>;
95 operating-points-v2 = 95 operating-points-v2 = <&cluster0_opp>;
96 }; 96 };
97 97
98 cpu1: cpu@100 { 98 cpu1: cpu@100 {
99 compatible = "arm,cort 99 compatible = "arm,cortex-a55";
100 reg = <0x100>; 100 reg = <0x100>;
101 device_type = "cpu"; 101 device_type = "cpu";
102 next-level-cache = <&L 102 next-level-cache = <&L3_CA55>;
103 enable-method = "psci" 103 enable-method = "psci";
104 clocks = <&cpg CPG_COR 104 clocks = <&cpg CPG_CORE R9A07G044_CLK_I>;
105 operating-points-v2 = 105 operating-points-v2 = <&cluster0_opp>;
106 }; 106 };
107 107
108 L3_CA55: cache-controller-0 { 108 L3_CA55: cache-controller-0 {
109 compatible = "cache"; 109 compatible = "cache";
110 cache-unified; 110 cache-unified;
111 cache-size = <0x40000> 111 cache-size = <0x40000>;
112 cache-level = <3>; 112 cache-level = <3>;
113 }; 113 };
114 }; 114 };
115 115
116 gpu_opp_table: opp-table-1 { 116 gpu_opp_table: opp-table-1 {
117 compatible = "operating-points 117 compatible = "operating-points-v2";
118 118
119 opp-500000000 { 119 opp-500000000 {
120 opp-hz = /bits/ 64 <50 120 opp-hz = /bits/ 64 <500000000>;
121 opp-microvolt = <11000 121 opp-microvolt = <1100000>;
122 }; 122 };
123 123
124 opp-400000000 { 124 opp-400000000 {
125 opp-hz = /bits/ 64 <40 125 opp-hz = /bits/ 64 <400000000>;
126 opp-microvolt = <11000 126 opp-microvolt = <1100000>;
127 }; 127 };
128 128
129 opp-250000000 { 129 opp-250000000 {
130 opp-hz = /bits/ 64 <25 130 opp-hz = /bits/ 64 <250000000>;
131 opp-microvolt = <11000 131 opp-microvolt = <1100000>;
132 }; 132 };
133 133
134 opp-200000000 { 134 opp-200000000 {
135 opp-hz = /bits/ 64 <20 135 opp-hz = /bits/ 64 <200000000>;
136 opp-microvolt = <11000 136 opp-microvolt = <1100000>;
137 }; 137 };
138 138
139 opp-125000000 { 139 opp-125000000 {
140 opp-hz = /bits/ 64 <12 140 opp-hz = /bits/ 64 <125000000>;
141 opp-microvolt = <11000 141 opp-microvolt = <1100000>;
142 }; 142 };
143 143
144 opp-100000000 { 144 opp-100000000 {
145 opp-hz = /bits/ 64 <10 145 opp-hz = /bits/ 64 <100000000>;
146 opp-microvolt = <11000 146 opp-microvolt = <1100000>;
147 }; 147 };
148 148
149 opp-62500000 { 149 opp-62500000 {
150 opp-hz = /bits/ 64 <62 150 opp-hz = /bits/ 64 <62500000>;
151 opp-microvolt = <11000 151 opp-microvolt = <1100000>;
152 }; 152 };
153 153
154 opp-50000000 { 154 opp-50000000 {
155 opp-hz = /bits/ 64 <50 155 opp-hz = /bits/ 64 <50000000>;
156 opp-microvolt = <11000 156 opp-microvolt = <1100000>;
157 }; 157 };
158 }; 158 };
159 159
160 pmu { <<
161 compatible = "arm,cortex-a55-p <<
162 interrupts-extended = <&gic GI <<
163 }; <<
164 <<
165 psci { 160 psci {
166 compatible = "arm,psci-1.0", " 161 compatible = "arm,psci-1.0", "arm,psci-0.2";
167 method = "smc"; 162 method = "smc";
168 }; 163 };
169 164
170 soc: soc { 165 soc: soc {
171 compatible = "simple-bus"; 166 compatible = "simple-bus";
172 interrupt-parent = <&gic>; 167 interrupt-parent = <&gic>;
173 #address-cells = <2>; 168 #address-cells = <2>;
174 #size-cells = <2>; 169 #size-cells = <2>;
175 ranges; 170 ranges;
176 171
177 mtu3: timer@10001200 { <<
178 compatible = "renesas, <<
179 "renesas, <<
180 reg = <0 0x10001200 0 <<
181 interrupts = <GIC_SPI <<
182 <GIC_SPI <<
183 <GIC_SPI <<
184 <GIC_SPI <<
185 <GIC_SPI <<
186 <GIC_SPI <<
187 <GIC_SPI <<
188 <GIC_SPI <<
189 <GIC_SPI <<
190 <GIC_SPI <<
191 <GIC_SPI <<
192 <GIC_SPI <<
193 <GIC_SPI <<
194 <GIC_SPI <<
195 <GIC_SPI <<
196 <GIC_SPI <<
197 <GIC_SPI <<
198 <GIC_SPI <<
199 <GIC_SPI <<
200 <GIC_SPI <<
201 <GIC_SPI <<
202 <GIC_SPI <<
203 <GIC_SPI <<
204 <GIC_SPI <<
205 <GIC_SPI <<
206 <GIC_SPI <<
207 <GIC_SPI <<
208 <GIC_SPI <<
209 <GIC_SPI <<
210 <GIC_SPI <<
211 <GIC_SPI <<
212 <GIC_SPI <<
213 <GIC_SPI <<
214 <GIC_SPI <<
215 <GIC_SPI <<
216 <GIC_SPI <<
217 <GIC_SPI <<
218 <GIC_SPI <<
219 <GIC_SPI <<
220 <GIC_SPI <<
221 <GIC_SPI <<
222 <GIC_SPI <<
223 <GIC_SPI <<
224 <GIC_SPI <<
225 interrupt-names = "tgi <<
226 "tci <<
227 "tgi <<
228 "tgi <<
229 "tgi <<
230 "tci <<
231 "tgi <<
232 "tci <<
233 "tgi <<
234 "tgi <<
235 "tci <<
236 "tgi <<
237 "tci <<
238 "tgi <<
239 "tci <<
240 clocks = <&cpg CPG_MOD <<
241 power-domains = <&cpg> <<
242 resets = <&cpg R9A07G0 <<
243 #pwm-cells = <2>; <<
244 status = "disabled"; <<
245 }; <<
246 <<
247 ssi0: ssi@10049c00 { 172 ssi0: ssi@10049c00 {
248 compatible = "renesas, 173 compatible = "renesas,r9a07g044-ssi",
249 "renesas, 174 "renesas,rz-ssi";
250 reg = <0 0x10049c00 0 175 reg = <0 0x10049c00 0 0x400>;
251 interrupts = <GIC_SPI 176 interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
252 <GIC_SPI 177 <GIC_SPI 327 IRQ_TYPE_EDGE_RISING>,
253 <GIC_SPI 178 <GIC_SPI 328 IRQ_TYPE_EDGE_RISING>;
254 interrupt-names = "int 179 interrupt-names = "int_req", "dma_rx", "dma_tx";
255 clocks = <&cpg CPG_MOD 180 clocks = <&cpg CPG_MOD R9A07G044_SSI0_PCLK2>,
256 <&cpg CPG_MOD 181 <&cpg CPG_MOD R9A07G044_SSI0_PCLK_SFR>,
257 <&audio_clk1> 182 <&audio_clk1>, <&audio_clk2>;
258 clock-names = "ssi", " 183 clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2";
259 resets = <&cpg R9A07G0 184 resets = <&cpg R9A07G044_SSI0_RST_M2_REG>;
260 dmas = <&dmac 0x2655>, 185 dmas = <&dmac 0x2655>, <&dmac 0x2656>;
261 dma-names = "tx", "rx" 186 dma-names = "tx", "rx";
262 power-domains = <&cpg> 187 power-domains = <&cpg>;
263 #sound-dai-cells = <0> 188 #sound-dai-cells = <0>;
264 status = "disabled"; 189 status = "disabled";
265 }; 190 };
266 191
267 ssi1: ssi@1004a000 { 192 ssi1: ssi@1004a000 {
268 compatible = "renesas, 193 compatible = "renesas,r9a07g044-ssi",
269 "renesas, 194 "renesas,rz-ssi";
270 reg = <0 0x1004a000 0 195 reg = <0 0x1004a000 0 0x400>;
271 interrupts = <GIC_SPI 196 interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
272 <GIC_SPI 197 <GIC_SPI 331 IRQ_TYPE_EDGE_RISING>,
273 <GIC_SPI 198 <GIC_SPI 332 IRQ_TYPE_EDGE_RISING>;
274 interrupt-names = "int 199 interrupt-names = "int_req", "dma_rx", "dma_tx";
275 clocks = <&cpg CPG_MOD 200 clocks = <&cpg CPG_MOD R9A07G044_SSI1_PCLK2>,
276 <&cpg CPG_MOD 201 <&cpg CPG_MOD R9A07G044_SSI1_PCLK_SFR>,
277 <&audio_clk1> 202 <&audio_clk1>, <&audio_clk2>;
278 clock-names = "ssi", " 203 clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2";
279 resets = <&cpg R9A07G0 204 resets = <&cpg R9A07G044_SSI1_RST_M2_REG>;
280 dmas = <&dmac 0x2659>, 205 dmas = <&dmac 0x2659>, <&dmac 0x265a>;
281 dma-names = "tx", "rx" 206 dma-names = "tx", "rx";
282 power-domains = <&cpg> 207 power-domains = <&cpg>;
283 #sound-dai-cells = <0> 208 #sound-dai-cells = <0>;
284 status = "disabled"; 209 status = "disabled";
285 }; 210 };
286 211
287 ssi2: ssi@1004a400 { 212 ssi2: ssi@1004a400 {
288 compatible = "renesas, 213 compatible = "renesas,r9a07g044-ssi",
289 "renesas, 214 "renesas,rz-ssi";
290 reg = <0 0x1004a400 0 215 reg = <0 0x1004a400 0 0x400>;
291 interrupts = <GIC_SPI 216 interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
292 <GIC_SPI 217 <GIC_SPI 337 IRQ_TYPE_EDGE_RISING>;
293 interrupt-names = "int 218 interrupt-names = "int_req", "dma_rt";
294 clocks = <&cpg CPG_MOD 219 clocks = <&cpg CPG_MOD R9A07G044_SSI2_PCLK2>,
295 <&cpg CPG_MOD 220 <&cpg CPG_MOD R9A07G044_SSI2_PCLK_SFR>,
296 <&audio_clk1> 221 <&audio_clk1>, <&audio_clk2>;
297 clock-names = "ssi", " 222 clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2";
298 resets = <&cpg R9A07G0 223 resets = <&cpg R9A07G044_SSI2_RST_M2_REG>;
299 dmas = <&dmac 0x265f>; 224 dmas = <&dmac 0x265f>;
300 dma-names = "rt"; 225 dma-names = "rt";
301 power-domains = <&cpg> 226 power-domains = <&cpg>;
302 #sound-dai-cells = <0> 227 #sound-dai-cells = <0>;
303 status = "disabled"; 228 status = "disabled";
304 }; 229 };
305 230
306 ssi3: ssi@1004a800 { 231 ssi3: ssi@1004a800 {
307 compatible = "renesas, 232 compatible = "renesas,r9a07g044-ssi",
308 "renesas, 233 "renesas,rz-ssi";
309 reg = <0 0x1004a800 0 234 reg = <0 0x1004a800 0 0x400>;
310 interrupts = <GIC_SPI 235 interrupts = <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
311 <GIC_SPI 236 <GIC_SPI 339 IRQ_TYPE_EDGE_RISING>,
312 <GIC_SPI 237 <GIC_SPI 340 IRQ_TYPE_EDGE_RISING>;
313 interrupt-names = "int 238 interrupt-names = "int_req", "dma_rx", "dma_tx";
314 clocks = <&cpg CPG_MOD 239 clocks = <&cpg CPG_MOD R9A07G044_SSI3_PCLK2>,
315 <&cpg CPG_MOD 240 <&cpg CPG_MOD R9A07G044_SSI3_PCLK_SFR>,
316 <&audio_clk1> 241 <&audio_clk1>, <&audio_clk2>;
317 clock-names = "ssi", " 242 clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2";
318 resets = <&cpg R9A07G0 243 resets = <&cpg R9A07G044_SSI3_RST_M2_REG>;
319 dmas = <&dmac 0x2661>, 244 dmas = <&dmac 0x2661>, <&dmac 0x2662>;
320 dma-names = "tx", "rx" 245 dma-names = "tx", "rx";
321 power-domains = <&cpg> 246 power-domains = <&cpg>;
322 #sound-dai-cells = <0> 247 #sound-dai-cells = <0>;
323 status = "disabled"; 248 status = "disabled";
324 }; 249 };
325 250
326 spi0: spi@1004ac00 { 251 spi0: spi@1004ac00 {
327 compatible = "renesas, 252 compatible = "renesas,r9a07g044-rspi", "renesas,rspi-rz";
328 reg = <0 0x1004ac00 0 253 reg = <0 0x1004ac00 0 0x400>;
329 interrupts = <GIC_SPI 254 interrupts = <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>,
330 <GIC_SPI 255 <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>,
331 <GIC_SPI 256 <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>;
332 interrupt-names = "err 257 interrupt-names = "error", "rx", "tx";
333 clocks = <&cpg CPG_MOD 258 clocks = <&cpg CPG_MOD R9A07G044_RSPI0_CLKB>;
334 resets = <&cpg R9A07G0 259 resets = <&cpg R9A07G044_RSPI0_RST>;
335 dmas = <&dmac 0x2e95>, 260 dmas = <&dmac 0x2e95>, <&dmac 0x2e96>;
336 dma-names = "tx", "rx" 261 dma-names = "tx", "rx";
337 power-domains = <&cpg> 262 power-domains = <&cpg>;
338 num-cs = <1>; 263 num-cs = <1>;
339 #address-cells = <1>; 264 #address-cells = <1>;
340 #size-cells = <0>; 265 #size-cells = <0>;
341 status = "disabled"; 266 status = "disabled";
342 }; 267 };
343 268
344 spi1: spi@1004b000 { 269 spi1: spi@1004b000 {
345 compatible = "renesas, 270 compatible = "renesas,r9a07g044-rspi", "renesas,rspi-rz";
346 reg = <0 0x1004b000 0 271 reg = <0 0x1004b000 0 0x400>;
347 interrupts = <GIC_SPI 272 interrupts = <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
348 <GIC_SPI 273 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
349 <GIC_SPI 274 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>;
350 interrupt-names = "err 275 interrupt-names = "error", "rx", "tx";
351 clocks = <&cpg CPG_MOD 276 clocks = <&cpg CPG_MOD R9A07G044_RSPI1_CLKB>;
352 resets = <&cpg R9A07G0 277 resets = <&cpg R9A07G044_RSPI1_RST>;
353 dmas = <&dmac 0x2e99>, 278 dmas = <&dmac 0x2e99>, <&dmac 0x2e9a>;
354 dma-names = "tx", "rx" 279 dma-names = "tx", "rx";
355 power-domains = <&cpg> 280 power-domains = <&cpg>;
356 num-cs = <1>; 281 num-cs = <1>;
357 #address-cells = <1>; 282 #address-cells = <1>;
358 #size-cells = <0>; 283 #size-cells = <0>;
359 status = "disabled"; 284 status = "disabled";
360 }; 285 };
361 286
362 spi2: spi@1004b400 { 287 spi2: spi@1004b400 {
363 compatible = "renesas, 288 compatible = "renesas,r9a07g044-rspi", "renesas,rspi-rz";
364 reg = <0 0x1004b400 0 289 reg = <0 0x1004b400 0 0x400>;
365 interrupts = <GIC_SPI 290 interrupts = <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
366 <GIC_SPI 291 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
367 <GIC_SPI 292 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>;
368 interrupt-names = "err 293 interrupt-names = "error", "rx", "tx";
369 clocks = <&cpg CPG_MOD 294 clocks = <&cpg CPG_MOD R9A07G044_RSPI2_CLKB>;
370 resets = <&cpg R9A07G0 295 resets = <&cpg R9A07G044_RSPI2_RST>;
371 dmas = <&dmac 0x2e9d>, 296 dmas = <&dmac 0x2e9d>, <&dmac 0x2e9e>;
372 dma-names = "tx", "rx" 297 dma-names = "tx", "rx";
373 power-domains = <&cpg> 298 power-domains = <&cpg>;
374 num-cs = <1>; 299 num-cs = <1>;
375 #address-cells = <1>; 300 #address-cells = <1>;
376 #size-cells = <0>; 301 #size-cells = <0>;
377 status = "disabled"; 302 status = "disabled";
378 }; 303 };
379 304
380 scif0: serial@1004b800 { 305 scif0: serial@1004b800 {
381 compatible = "renesas, 306 compatible = "renesas,scif-r9a07g044";
382 reg = <0 0x1004b800 0 307 reg = <0 0x1004b800 0 0x400>;
383 interrupts = <GIC_SPI 308 interrupts = <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>,
384 <GIC_SPI 309 <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>,
385 <GIC_SPI 310 <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>,
386 <GIC_SPI 311 <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>,
387 <GIC_SPI 312 <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>,
388 <GIC_SPI 313 <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>;
389 interrupt-names = "eri 314 interrupt-names = "eri", "rxi", "txi",
390 "bri 315 "bri", "dri", "tei";
391 clocks = <&cpg CPG_MOD 316 clocks = <&cpg CPG_MOD R9A07G044_SCIF0_CLK_PCK>;
392 clock-names = "fck"; 317 clock-names = "fck";
393 power-domains = <&cpg> 318 power-domains = <&cpg>;
394 resets = <&cpg R9A07G0 319 resets = <&cpg R9A07G044_SCIF0_RST_SYSTEM_N>;
395 status = "disabled"; 320 status = "disabled";
396 }; 321 };
397 322
398 scif1: serial@1004bc00 { 323 scif1: serial@1004bc00 {
399 compatible = "renesas, 324 compatible = "renesas,scif-r9a07g044";
400 reg = <0 0x1004bc00 0 325 reg = <0 0x1004bc00 0 0x400>;
401 interrupts = <GIC_SPI 326 interrupts = <GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>,
402 <GIC_SPI 327 <GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>,
403 <GIC_SPI 328 <GIC_SPI 388 IRQ_TYPE_LEVEL_HIGH>,
404 <GIC_SPI 329 <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>,
405 <GIC_SPI 330 <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>,
406 <GIC_SPI 331 <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>;
407 interrupt-names = "eri 332 interrupt-names = "eri", "rxi", "txi",
408 "bri 333 "bri", "dri", "tei";
409 clocks = <&cpg CPG_MOD 334 clocks = <&cpg CPG_MOD R9A07G044_SCIF1_CLK_PCK>;
410 clock-names = "fck"; 335 clock-names = "fck";
411 power-domains = <&cpg> 336 power-domains = <&cpg>;
412 resets = <&cpg R9A07G0 337 resets = <&cpg R9A07G044_SCIF1_RST_SYSTEM_N>;
413 status = "disabled"; 338 status = "disabled";
414 }; 339 };
415 340
416 scif2: serial@1004c000 { 341 scif2: serial@1004c000 {
417 compatible = "renesas, 342 compatible = "renesas,scif-r9a07g044";
418 reg = <0 0x1004c000 0 343 reg = <0 0x1004c000 0 0x400>;
419 interrupts = <GIC_SPI 344 interrupts = <GIC_SPI 390 IRQ_TYPE_LEVEL_HIGH>,
420 <GIC_SPI 345 <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH>,
421 <GIC_SPI 346 <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>,
422 <GIC_SPI 347 <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH>,
423 <GIC_SPI 348 <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>,
424 <GIC_SPI 349 <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>;
425 interrupt-names = "eri 350 interrupt-names = "eri", "rxi", "txi",
426 "bri 351 "bri", "dri", "tei";
427 clocks = <&cpg CPG_MOD 352 clocks = <&cpg CPG_MOD R9A07G044_SCIF2_CLK_PCK>;
428 clock-names = "fck"; 353 clock-names = "fck";
429 power-domains = <&cpg> 354 power-domains = <&cpg>;
430 resets = <&cpg R9A07G0 355 resets = <&cpg R9A07G044_SCIF2_RST_SYSTEM_N>;
431 status = "disabled"; 356 status = "disabled";
432 }; 357 };
433 358
434 scif3: serial@1004c400 { 359 scif3: serial@1004c400 {
435 compatible = "renesas, 360 compatible = "renesas,scif-r9a07g044";
436 reg = <0 0x1004c400 0 361 reg = <0 0x1004c400 0 0x400>;
437 interrupts = <GIC_SPI 362 interrupts = <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
438 <GIC_SPI 363 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
439 <GIC_SPI 364 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
440 <GIC_SPI 365 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
441 <GIC_SPI 366 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
442 <GIC_SPI 367 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>;
443 interrupt-names = "eri 368 interrupt-names = "eri", "rxi", "txi",
444 "bri 369 "bri", "dri", "tei";
445 clocks = <&cpg CPG_MOD 370 clocks = <&cpg CPG_MOD R9A07G044_SCIF3_CLK_PCK>;
446 clock-names = "fck"; 371 clock-names = "fck";
447 power-domains = <&cpg> 372 power-domains = <&cpg>;
448 resets = <&cpg R9A07G0 373 resets = <&cpg R9A07G044_SCIF3_RST_SYSTEM_N>;
449 status = "disabled"; 374 status = "disabled";
450 }; 375 };
451 376
452 scif4: serial@1004c800 { 377 scif4: serial@1004c800 {
453 compatible = "renesas, 378 compatible = "renesas,scif-r9a07g044";
454 reg = <0 0x1004c800 0 379 reg = <0 0x1004c800 0 0x400>;
455 interrupts = <GIC_SPI 380 interrupts = <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
456 <GIC_SPI 381 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
457 <GIC_SPI 382 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
458 <GIC_SPI 383 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
459 <GIC_SPI 384 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
460 <GIC_SPI 385 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>;
461 interrupt-names = "eri 386 interrupt-names = "eri", "rxi", "txi",
462 "bri 387 "bri", "dri", "tei";
463 clocks = <&cpg CPG_MOD 388 clocks = <&cpg CPG_MOD R9A07G044_SCIF4_CLK_PCK>;
464 clock-names = "fck"; 389 clock-names = "fck";
465 power-domains = <&cpg> 390 power-domains = <&cpg>;
466 resets = <&cpg R9A07G0 391 resets = <&cpg R9A07G044_SCIF4_RST_SYSTEM_N>;
467 status = "disabled"; 392 status = "disabled";
468 }; 393 };
469 394
470 sci0: serial@1004d000 { 395 sci0: serial@1004d000 {
471 compatible = "renesas, 396 compatible = "renesas,r9a07g044-sci", "renesas,sci";
472 reg = <0 0x1004d000 0 397 reg = <0 0x1004d000 0 0x400>;
473 interrupts = <GIC_SPI 398 interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
474 <GIC_SPI 399 <GIC_SPI 406 IRQ_TYPE_EDGE_RISING>,
475 <GIC_SPI 400 <GIC_SPI 407 IRQ_TYPE_EDGE_RISING>,
476 <GIC_SPI 401 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>;
477 interrupt-names = "eri 402 interrupt-names = "eri", "rxi", "txi", "tei";
478 clocks = <&cpg CPG_MOD 403 clocks = <&cpg CPG_MOD R9A07G044_SCI0_CLKP>;
479 clock-names = "fck"; 404 clock-names = "fck";
480 power-domains = <&cpg> 405 power-domains = <&cpg>;
481 resets = <&cpg R9A07G0 406 resets = <&cpg R9A07G044_SCI0_RST>;
482 status = "disabled"; 407 status = "disabled";
483 }; 408 };
484 409
485 sci1: serial@1004d400 { 410 sci1: serial@1004d400 {
486 compatible = "renesas, 411 compatible = "renesas,r9a07g044-sci", "renesas,sci";
487 reg = <0 0x1004d400 0 412 reg = <0 0x1004d400 0 0x400>;
488 interrupts = <GIC_SPI 413 interrupts = <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
489 <GIC_SPI 414 <GIC_SPI 410 IRQ_TYPE_EDGE_RISING>,
490 <GIC_SPI 415 <GIC_SPI 411 IRQ_TYPE_EDGE_RISING>,
491 <GIC_SPI 416 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>;
492 interrupt-names = "eri 417 interrupt-names = "eri", "rxi", "txi", "tei";
493 clocks = <&cpg CPG_MOD 418 clocks = <&cpg CPG_MOD R9A07G044_SCI1_CLKP>;
494 clock-names = "fck"; 419 clock-names = "fck";
495 power-domains = <&cpg> 420 power-domains = <&cpg>;
496 resets = <&cpg R9A07G0 421 resets = <&cpg R9A07G044_SCI1_RST>;
497 status = "disabled"; 422 status = "disabled";
498 }; 423 };
499 424
500 canfd: can@10050000 { 425 canfd: can@10050000 {
501 compatible = "renesas, 426 compatible = "renesas,r9a07g044-canfd", "renesas,rzg2l-canfd";
502 reg = <0 0x10050000 0 427 reg = <0 0x10050000 0 0x8000>;
503 interrupts = <GIC_SPI 428 interrupts = <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>,
504 <GIC_SPI 429 <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>,
505 <GIC_SPI 430 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
506 <GIC_SPI 431 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
507 <GIC_SPI 432 <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>,
508 <GIC_SPI 433 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
509 <GIC_SPI 434 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
510 <GIC_SPI 435 <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>;
511 interrupt-names = "g_e 436 interrupt-names = "g_err", "g_recc",
512 "ch0 437 "ch0_err", "ch0_rec", "ch0_trx",
513 "ch1 438 "ch1_err", "ch1_rec", "ch1_trx";
514 clocks = <&cpg CPG_MOD 439 clocks = <&cpg CPG_MOD R9A07G044_CANFD_PCLK>,
515 <&cpg CPG_COR 440 <&cpg CPG_CORE R9A07G044_CLK_P0_DIV2>,
516 <&can_clk>; 441 <&can_clk>;
517 clock-names = "fck", " 442 clock-names = "fck", "canfd", "can_clk";
518 assigned-clocks = <&cp 443 assigned-clocks = <&cpg CPG_CORE R9A07G044_CLK_P0_DIV2>;
519 assigned-clock-rates = 444 assigned-clock-rates = <50000000>;
520 resets = <&cpg R9A07G0 445 resets = <&cpg R9A07G044_CANFD_RSTP_N>,
521 <&cpg R9A07G0 446 <&cpg R9A07G044_CANFD_RSTC_N>;
522 reset-names = "rstp_n" 447 reset-names = "rstp_n", "rstc_n";
523 power-domains = <&cpg> 448 power-domains = <&cpg>;
524 status = "disabled"; 449 status = "disabled";
525 450
526 channel0 { 451 channel0 {
527 status = "disa 452 status = "disabled";
528 }; 453 };
529 channel1 { 454 channel1 {
530 status = "disa 455 status = "disabled";
531 }; 456 };
532 }; 457 };
533 458
534 i2c0: i2c@10058000 { 459 i2c0: i2c@10058000 {
535 #address-cells = <1>; 460 #address-cells = <1>;
536 #size-cells = <0>; 461 #size-cells = <0>;
537 compatible = "renesas, 462 compatible = "renesas,riic-r9a07g044", "renesas,riic-rz";
538 reg = <0 0x10058000 0 463 reg = <0 0x10058000 0 0x400>;
539 interrupts = <GIC_SPI 464 interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>,
540 <GIC_SPI 465 <GIC_SPI 348 IRQ_TYPE_EDGE_RISING>,
541 <GIC_SPI 466 <GIC_SPI 349 IRQ_TYPE_EDGE_RISING>,
542 <GIC_SPI 467 <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>,
543 <GIC_SPI 468 <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>,
544 <GIC_SPI 469 <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>,
545 <GIC_SPI 470 <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>,
546 <GIC_SPI 471 <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
547 interrupt-names = "tei 472 interrupt-names = "tei", "ri", "ti", "spi", "sti",
548 "nak 473 "naki", "ali", "tmoi";
549 clocks = <&cpg CPG_MOD 474 clocks = <&cpg CPG_MOD R9A07G044_I2C0_PCLK>;
550 clock-frequency = <100 475 clock-frequency = <100000>;
551 resets = <&cpg R9A07G0 476 resets = <&cpg R9A07G044_I2C0_MRST>;
552 power-domains = <&cpg> 477 power-domains = <&cpg>;
553 status = "disabled"; 478 status = "disabled";
554 }; 479 };
555 480
556 i2c1: i2c@10058400 { 481 i2c1: i2c@10058400 {
557 #address-cells = <1>; 482 #address-cells = <1>;
558 #size-cells = <0>; 483 #size-cells = <0>;
559 compatible = "renesas, 484 compatible = "renesas,riic-r9a07g044", "renesas,riic-rz";
560 reg = <0 0x10058400 0 485 reg = <0 0x10058400 0 0x400>;
561 interrupts = <GIC_SPI 486 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>,
562 <GIC_SPI 487 <GIC_SPI 356 IRQ_TYPE_EDGE_RISING>,
563 <GIC_SPI 488 <GIC_SPI 357 IRQ_TYPE_EDGE_RISING>,
564 <GIC_SPI 489 <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>,
565 <GIC_SPI 490 <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>,
566 <GIC_SPI 491 <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>,
567 <GIC_SPI 492 <GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH>,
568 <GIC_SPI 493 <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>;
569 interrupt-names = "tei 494 interrupt-names = "tei", "ri", "ti", "spi", "sti",
570 "nak 495 "naki", "ali", "tmoi";
571 clocks = <&cpg CPG_MOD 496 clocks = <&cpg CPG_MOD R9A07G044_I2C1_PCLK>;
572 clock-frequency = <100 497 clock-frequency = <100000>;
573 resets = <&cpg R9A07G0 498 resets = <&cpg R9A07G044_I2C1_MRST>;
574 power-domains = <&cpg> 499 power-domains = <&cpg>;
575 status = "disabled"; 500 status = "disabled";
576 }; 501 };
577 502
578 i2c2: i2c@10058800 { 503 i2c2: i2c@10058800 {
579 #address-cells = <1>; 504 #address-cells = <1>;
580 #size-cells = <0>; 505 #size-cells = <0>;
581 compatible = "renesas, 506 compatible = "renesas,riic-r9a07g044", "renesas,riic-rz";
582 reg = <0 0x10058800 0 507 reg = <0 0x10058800 0 0x400>;
583 interrupts = <GIC_SPI 508 interrupts = <GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>,
584 <GIC_SPI 509 <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>,
585 <GIC_SPI 510 <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>,
586 <GIC_SPI 511 <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>,
587 <GIC_SPI 512 <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>,
588 <GIC_SPI 513 <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>,
589 <GIC_SPI 514 <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>,
590 <GIC_SPI 515 <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
591 interrupt-names = "tei 516 interrupt-names = "tei", "ri", "ti", "spi", "sti",
592 "nak 517 "naki", "ali", "tmoi";
593 clocks = <&cpg CPG_MOD 518 clocks = <&cpg CPG_MOD R9A07G044_I2C2_PCLK>;
594 clock-frequency = <100 519 clock-frequency = <100000>;
595 resets = <&cpg R9A07G0 520 resets = <&cpg R9A07G044_I2C2_MRST>;
596 power-domains = <&cpg> 521 power-domains = <&cpg>;
597 status = "disabled"; 522 status = "disabled";
598 }; 523 };
599 524
600 i2c3: i2c@10058c00 { 525 i2c3: i2c@10058c00 {
601 #address-cells = <1>; 526 #address-cells = <1>;
602 #size-cells = <0>; 527 #size-cells = <0>;
603 compatible = "renesas, 528 compatible = "renesas,riic-r9a07g044", "renesas,riic-rz";
604 reg = <0 0x10058c00 0 529 reg = <0 0x10058c00 0 0x400>;
605 interrupts = <GIC_SPI 530 interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>,
606 <GIC_SPI 531 <GIC_SPI 372 IRQ_TYPE_EDGE_RISING>,
607 <GIC_SPI 532 <GIC_SPI 373 IRQ_TYPE_EDGE_RISING>,
608 <GIC_SPI 533 <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>,
609 <GIC_SPI 534 <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>,
610 <GIC_SPI 535 <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>,
611 <GIC_SPI 536 <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>,
612 <GIC_SPI 537 <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
613 interrupt-names = "tei 538 interrupt-names = "tei", "ri", "ti", "spi", "sti",
614 "nak 539 "naki", "ali", "tmoi";
615 clocks = <&cpg CPG_MOD 540 clocks = <&cpg CPG_MOD R9A07G044_I2C3_PCLK>;
616 clock-frequency = <100 541 clock-frequency = <100000>;
617 resets = <&cpg R9A07G0 542 resets = <&cpg R9A07G044_I2C3_MRST>;
618 power-domains = <&cpg> 543 power-domains = <&cpg>;
619 status = "disabled"; 544 status = "disabled";
620 }; 545 };
621 546
622 adc: adc@10059000 { 547 adc: adc@10059000 {
623 compatible = "renesas, 548 compatible = "renesas,r9a07g044-adc", "renesas,rzg2l-adc";
624 reg = <0 0x10059000 0 549 reg = <0 0x10059000 0 0x400>;
625 interrupts = <GIC_SPI 550 interrupts = <GIC_SPI 347 IRQ_TYPE_EDGE_RISING>;
626 clocks = <&cpg CPG_MOD 551 clocks = <&cpg CPG_MOD R9A07G044_ADC_ADCLK>,
627 <&cpg CPG_MOD 552 <&cpg CPG_MOD R9A07G044_ADC_PCLK>;
628 clock-names = "adclk", 553 clock-names = "adclk", "pclk";
629 resets = <&cpg R9A07G0 554 resets = <&cpg R9A07G044_ADC_PRESETN>,
630 <&cpg R9A07G0 555 <&cpg R9A07G044_ADC_ADRST_N>;
631 reset-names = "presetn 556 reset-names = "presetn", "adrst-n";
632 power-domains = <&cpg> 557 power-domains = <&cpg>;
633 status = "disabled"; 558 status = "disabled";
634 559
635 #address-cells = <1>; 560 #address-cells = <1>;
636 #size-cells = <0>; 561 #size-cells = <0>;
637 562
638 channel@0 { 563 channel@0 {
639 reg = <0>; 564 reg = <0>;
640 }; 565 };
641 channel@1 { 566 channel@1 {
642 reg = <1>; 567 reg = <1>;
643 }; 568 };
644 channel@2 { 569 channel@2 {
645 reg = <2>; 570 reg = <2>;
646 }; 571 };
647 channel@3 { 572 channel@3 {
648 reg = <3>; 573 reg = <3>;
649 }; 574 };
650 channel@4 { 575 channel@4 {
651 reg = <4>; 576 reg = <4>;
652 }; 577 };
653 channel@5 { 578 channel@5 {
654 reg = <5>; 579 reg = <5>;
655 }; 580 };
656 channel@6 { 581 channel@6 {
657 reg = <6>; 582 reg = <6>;
658 }; 583 };
659 channel@7 { 584 channel@7 {
660 reg = <7>; 585 reg = <7>;
661 }; 586 };
662 }; 587 };
663 588
664 tsu: thermal@10059400 { 589 tsu: thermal@10059400 {
665 compatible = "renesas, 590 compatible = "renesas,r9a07g044-tsu",
666 "renesas, 591 "renesas,rzg2l-tsu";
667 reg = <0 0x10059400 0 592 reg = <0 0x10059400 0 0x400>;
668 clocks = <&cpg CPG_MOD 593 clocks = <&cpg CPG_MOD R9A07G044_TSU_PCLK>;
669 resets = <&cpg R9A07G0 594 resets = <&cpg R9A07G044_TSU_PRESETN>;
670 power-domains = <&cpg> 595 power-domains = <&cpg>;
671 #thermal-sensor-cells 596 #thermal-sensor-cells = <1>;
672 }; 597 };
673 598
674 sbc: spi@10060000 { 599 sbc: spi@10060000 {
675 compatible = "renesas, 600 compatible = "renesas,r9a07g044-rpc-if",
676 "renesas, 601 "renesas,rzg2l-rpc-if";
677 reg = <0 0x10060000 0 602 reg = <0 0x10060000 0 0x10000>,
678 <0 0x20000000 0 603 <0 0x20000000 0 0x10000000>,
679 <0 0x10070000 0 604 <0 0x10070000 0 0x10000>;
680 reg-names = "regs", "d 605 reg-names = "regs", "dirmap", "wbuf";
681 interrupts = <GIC_SPI 606 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
682 clocks = <&cpg CPG_MOD 607 clocks = <&cpg CPG_MOD R9A07G044_SPI_CLK2>,
683 <&cpg CPG_MOD 608 <&cpg CPG_MOD R9A07G044_SPI_CLK>;
684 resets = <&cpg R9A07G0 609 resets = <&cpg R9A07G044_SPI_RST>;
685 power-domains = <&cpg> 610 power-domains = <&cpg>;
686 #address-cells = <1>; 611 #address-cells = <1>;
687 #size-cells = <0>; 612 #size-cells = <0>;
688 status = "disabled"; 613 status = "disabled";
689 }; 614 };
690 615
691 cru: video@10830000 { <<
692 compatible = "renesas, <<
693 reg = <0 0x10830000 0 <<
694 clocks = <&cpg CPG_MOD <<
695 <&cpg CPG_MOD <<
696 <&cpg CPG_MOD <<
697 clock-names = "video", <<
698 interrupts = <GIC_SPI <<
699 <GIC_SPI <<
700 <GIC_SPI <<
701 interrupt-names = "ima <<
702 resets = <&cpg R9A07G0 <<
703 <&cpg R9A07G0 <<
704 reset-names = "presetn <<
705 power-domains = <&cpg> <<
706 status = "disabled"; <<
707 <<
708 ports { <<
709 #address-cells <<
710 #size-cells = <<
711 <<
712 port@0 { <<
713 #addre <<
714 #size- <<
715 <<
716 reg = <<
717 crupar <<
718 <<
719 }; <<
720 }; <<
721 <<
722 port@1 { <<
723 #addre <<
724 #size- <<
725 <<
726 reg = <<
727 crucsi <<
728 <<
729 <<
730 }; <<
731 }; <<
732 }; <<
733 }; <<
734 <<
735 csi2: csi2@10830400 { <<
736 compatible = "renesas, <<
737 reg = <0 0x10830400 0 <<
738 interrupts = <GIC_SPI <<
739 clocks = <&cpg CPG_MOD <<
740 <&cpg CPG_MOD <<
741 <&cpg CPG_MOD <<
742 clock-names = "system" <<
743 resets = <&cpg R9A07G0 <<
744 <&cpg R9A07G0 <<
745 reset-names = "presetn <<
746 power-domains = <&cpg> <<
747 status = "disabled"; <<
748 <<
749 ports { <<
750 #address-cells <<
751 #size-cells = <<
752 <<
753 port@0 { <<
754 reg = <<
755 }; <<
756 <<
757 port@1 { <<
758 #addre <<
759 #size- <<
760 reg = <<
761 <<
762 csi2cr <<
763 <<
764 <<
765 }; <<
766 }; <<
767 }; <<
768 }; <<
769 <<
770 dsi: dsi@10850000 { <<
771 compatible = "renesas, <<
772 "renesas, <<
773 reg = <0 0x10850000 0 <<
774 interrupts = <GIC_SPI <<
775 <GIC_SPI <<
776 <GIC_SPI <<
777 <GIC_SPI <<
778 <GIC_SPI <<
779 <GIC_SPI <<
780 <GIC_SPI <<
781 interrupt-names = "seq <<
782 "fer <<
783 clocks = <&cpg CPG_MOD <<
784 <&cpg CPG_MOD <<
785 <&cpg CPG_MOD <<
786 <&cpg CPG_MOD <<
787 <&cpg CPG_MOD <<
788 <&cpg CPG_MOD <<
789 clock-names = "pllclk" <<
790 resets = <&cpg R9A07G0 <<
791 <&cpg R9A07G0 <<
792 <&cpg R9A07G0 <<
793 reset-names = "rst", " <<
794 power-domains = <&cpg> <<
795 status = "disabled"; <<
796 <<
797 ports { <<
798 #address-cells <<
799 #size-cells = <<
800 <<
801 port@0 { <<
802 reg = <<
803 dsi0_i <<
804 <<
805 }; <<
806 }; <<
807 <<
808 port@1 { <<
809 reg = <<
810 }; <<
811 }; <<
812 }; <<
813 <<
814 vspd: vsp@10870000 { <<
815 compatible = "renesas, <<
816 reg = <0 0x10870000 0 <<
817 interrupts = <GIC_SPI <<
818 clocks = <&cpg CPG_MOD <<
819 <&cpg CPG_MOD <<
820 <&cpg CPG_MOD <<
821 clock-names = "aclk", <<
822 power-domains = <&cpg> <<
823 resets = <&cpg R9A07G0 <<
824 renesas,fcp = <&fcpvd> <<
825 }; <<
826 <<
827 fcpvd: fcp@10880000 { <<
828 compatible = "renesas, <<
829 "renesas, <<
830 reg = <0 0x10880000 0 <<
831 clocks = <&cpg CPG_MOD <<
832 <&cpg CPG_MOD <<
833 <&cpg CPG_MOD <<
834 clock-names = "aclk", <<
835 power-domains = <&cpg> <<
836 resets = <&cpg R9A07G0 <<
837 }; <<
838 <<
839 du: display@10890000 { <<
840 compatible = "renesas, <<
841 reg = <0 0x10890000 0 <<
842 interrupts = <GIC_SPI <<
843 clocks = <&cpg CPG_MOD <<
844 <&cpg CPG_MOD <<
845 <&cpg CPG_MOD <<
846 clock-names = "aclk", <<
847 power-domains = <&cpg> <<
848 resets = <&cpg R9A07G0 <<
849 renesas,vsps = <&vspd <<
850 status = "disabled"; <<
851 <<
852 ports { <<
853 #address-cells <<
854 #size-cells = <<
855 <<
856 port@0 { <<
857 reg = <<
858 du_out <<
859 <<
860 }; <<
861 }; <<
862 <<
863 port@1 { <<
864 reg = <<
865 }; <<
866 }; <<
867 }; <<
868 <<
869 cpg: clock-controller@11010000 616 cpg: clock-controller@11010000 {
870 compatible = "renesas, 617 compatible = "renesas,r9a07g044-cpg";
871 reg = <0 0x11010000 0 618 reg = <0 0x11010000 0 0x10000>;
872 clocks = <&extal_clk>; 619 clocks = <&extal_clk>;
873 clock-names = "extal"; 620 clock-names = "extal";
874 #clock-cells = <2>; 621 #clock-cells = <2>;
875 #reset-cells = <1>; 622 #reset-cells = <1>;
876 #power-domain-cells = 623 #power-domain-cells = <0>;
877 }; 624 };
878 625
879 sysc: system-controller@110200 626 sysc: system-controller@11020000 {
880 compatible = "renesas, 627 compatible = "renesas,r9a07g044-sysc";
881 reg = <0 0x11020000 0 628 reg = <0 0x11020000 0 0x10000>;
882 interrupts = <GIC_SPI 629 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
883 <GIC_SPI 630 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
884 <GIC_SPI 631 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
885 <GIC_SPI 632 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
886 interrupt-names = "lpm 633 interrupt-names = "lpm_int", "ca55stbydone_int",
887 "cm3 634 "cm33stbyr_int", "ca55_deny";
888 status = "disabled"; 635 status = "disabled";
889 }; 636 };
890 637
891 pinctrl: pinctrl@11030000 { 638 pinctrl: pinctrl@11030000 {
892 compatible = "renesas, 639 compatible = "renesas,r9a07g044-pinctrl";
893 reg = <0 0x11030000 0 640 reg = <0 0x11030000 0 0x10000>;
894 gpio-controller; 641 gpio-controller;
895 #gpio-cells = <2>; 642 #gpio-cells = <2>;
896 #interrupt-cells = <2> 643 #interrupt-cells = <2>;
897 interrupt-parent = <&i 644 interrupt-parent = <&irqc>;
898 interrupt-controller; 645 interrupt-controller;
899 gpio-ranges = <&pinctr 646 gpio-ranges = <&pinctrl 0 0 392>;
900 clocks = <&cpg CPG_MOD 647 clocks = <&cpg CPG_MOD R9A07G044_GPIO_HCLK>;
901 power-domains = <&cpg> 648 power-domains = <&cpg>;
902 resets = <&cpg R9A07G0 649 resets = <&cpg R9A07G044_GPIO_RSTN>,
903 <&cpg R9A07G0 650 <&cpg R9A07G044_GPIO_PORT_RESETN>,
904 <&cpg R9A07G0 651 <&cpg R9A07G044_GPIO_SPARE_RESETN>;
905 }; 652 };
906 653
907 irqc: interrupt-controller@110 654 irqc: interrupt-controller@110a0000 {
908 compatible = "renesas, 655 compatible = "renesas,r9a07g044-irqc",
909 "renesas, 656 "renesas,rzg2l-irqc";
910 #interrupt-cells = <2> 657 #interrupt-cells = <2>;
911 #address-cells = <0>; 658 #address-cells = <0>;
912 interrupt-controller; 659 interrupt-controller;
913 reg = <0 0x110a0000 0 660 reg = <0 0x110a0000 0 0x10000>;
914 interrupts = <GIC_SPI 661 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
915 <GIC_SPI 662 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
916 <GIC_SPI 663 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
917 <GIC_SPI 664 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
918 <GIC_SPI 665 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
919 <GIC_SPI 666 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
920 <GIC_SPI 667 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
921 <GIC_SPI 668 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
922 <GIC_SPI 669 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
923 <GIC_SPI 670 <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>,
924 <GIC_SPI 671 <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>,
925 <GIC_SPI 672 <GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>,
926 <GIC_SPI 673 <GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>,
927 <GIC_SPI 674 <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>,
928 <GIC_SPI 675 <GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>,
929 <GIC_SPI 676 <GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH>,
930 <GIC_SPI 677 <GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>,
931 <GIC_SPI 678 <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>,
932 <GIC_SPI 679 <GIC_SPI 453 IRQ_TYPE_LEVEL_HIGH>,
933 <GIC_SPI 680 <GIC_SPI 454 IRQ_TYPE_LEVEL_HIGH>,
934 <GIC_SPI 681 <GIC_SPI 455 IRQ_TYPE_LEVEL_HIGH>,
935 <GIC_SPI 682 <GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>,
936 <GIC_SPI 683 <GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>,
937 <GIC_SPI 684 <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>,
938 <GIC_SPI 685 <GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>,
939 <GIC_SPI 686 <GIC_SPI 460 IRQ_TYPE_LEVEL_HIGH>,
940 <GIC_SPI 687 <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>,
941 <GIC_SPI 688 <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>,
942 <GIC_SPI 689 <GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH>,
943 <GIC_SPI 690 <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>,
944 <GIC_SPI 691 <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>,
945 <GIC_SPI 692 <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>,
946 <GIC_SPI 693 <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>,
947 <GIC_SPI 694 <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>,
948 <GIC_SPI 695 <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>,
949 <GIC_SPI 696 <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>,
950 <GIC_SPI 697 <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>,
951 <GIC_SPI 698 <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>,
952 <GIC_SPI 699 <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>,
953 <GIC_SPI 700 <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>,
954 <GIC_SPI !! 701 <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>;
955 <GIC_SPI <<
956 <GIC_SPI <<
957 <GIC_SPI <<
958 <GIC_SPI <<
959 <GIC_SPI <<
960 <GIC_SPI <<
961 <GIC_SPI <<
962 interrupt-names = "nmi <<
963 "irq <<
964 "tin <<
965 "tin <<
966 "tin <<
967 "tin <<
968 "tin <<
969 "tin <<
970 "tin <<
971 "tin <<
972 "bus <<
973 "ec7 <<
974 "ec7 <<
975 clocks = <&cpg CPG_MOD 702 clocks = <&cpg CPG_MOD R9A07G044_IA55_CLK>,
976 <&cpg CPG_MOD 703 <&cpg CPG_MOD R9A07G044_IA55_PCLK>;
977 clock-names = "clk", " 704 clock-names = "clk", "pclk";
978 power-domains = <&cpg> 705 power-domains = <&cpg>;
979 resets = <&cpg R9A07G0 706 resets = <&cpg R9A07G044_IA55_RESETN>;
980 }; 707 };
981 708
982 dmac: dma-controller@11820000 709 dmac: dma-controller@11820000 {
983 compatible = "renesas, 710 compatible = "renesas,r9a07g044-dmac",
984 "renesas, 711 "renesas,rz-dmac";
985 reg = <0 0x11820000 0 712 reg = <0 0x11820000 0 0x10000>,
986 <0 0x11830000 0 713 <0 0x11830000 0 0x10000>;
987 interrupts = <GIC_SPI 714 interrupts = <GIC_SPI 141 IRQ_TYPE_EDGE_RISING>,
988 <GIC_SPI 715 <GIC_SPI 125 IRQ_TYPE_EDGE_RISING>,
989 <GIC_SPI 716 <GIC_SPI 126 IRQ_TYPE_EDGE_RISING>,
990 <GIC_SPI 717 <GIC_SPI 127 IRQ_TYPE_EDGE_RISING>,
991 <GIC_SPI 718 <GIC_SPI 128 IRQ_TYPE_EDGE_RISING>,
992 <GIC_SPI 719 <GIC_SPI 129 IRQ_TYPE_EDGE_RISING>,
993 <GIC_SPI 720 <GIC_SPI 130 IRQ_TYPE_EDGE_RISING>,
994 <GIC_SPI 721 <GIC_SPI 131 IRQ_TYPE_EDGE_RISING>,
995 <GIC_SPI 722 <GIC_SPI 132 IRQ_TYPE_EDGE_RISING>,
996 <GIC_SPI 723 <GIC_SPI 133 IRQ_TYPE_EDGE_RISING>,
997 <GIC_SPI 724 <GIC_SPI 134 IRQ_TYPE_EDGE_RISING>,
998 <GIC_SPI 725 <GIC_SPI 135 IRQ_TYPE_EDGE_RISING>,
999 <GIC_SPI 726 <GIC_SPI 136 IRQ_TYPE_EDGE_RISING>,
1000 <GIC_SPI 727 <GIC_SPI 137 IRQ_TYPE_EDGE_RISING>,
1001 <GIC_SPI 728 <GIC_SPI 138 IRQ_TYPE_EDGE_RISING>,
1002 <GIC_SPI 729 <GIC_SPI 139 IRQ_TYPE_EDGE_RISING>,
1003 <GIC_SPI 730 <GIC_SPI 140 IRQ_TYPE_EDGE_RISING>;
1004 interrupt-names = "er 731 interrupt-names = "error",
1005 "ch 732 "ch0", "ch1", "ch2", "ch3",
1006 "ch 733 "ch4", "ch5", "ch6", "ch7",
1007 "ch 734 "ch8", "ch9", "ch10", "ch11",
1008 "ch 735 "ch12", "ch13", "ch14", "ch15";
1009 clocks = <&cpg CPG_MO 736 clocks = <&cpg CPG_MOD R9A07G044_DMAC_ACLK>,
1010 <&cpg CPG_MO 737 <&cpg CPG_MOD R9A07G044_DMAC_PCLK>;
1011 clock-names = "main", <<
1012 power-domains = <&cpg 738 power-domains = <&cpg>;
1013 resets = <&cpg R9A07G 739 resets = <&cpg R9A07G044_DMAC_ARESETN>,
1014 <&cpg R9A07G 740 <&cpg R9A07G044_DMAC_RST_ASYNC>;
1015 reset-names = "arst", <<
1016 #dma-cells = <1>; 741 #dma-cells = <1>;
1017 dma-channels = <16>; 742 dma-channels = <16>;
1018 }; 743 };
1019 744
1020 gpu: gpu@11840000 { 745 gpu: gpu@11840000 {
1021 compatible = "renesas 746 compatible = "renesas,r9a07g044-mali",
1022 "arm,mal 747 "arm,mali-bifrost";
1023 reg = <0x0 0x11840000 748 reg = <0x0 0x11840000 0x0 0x10000>;
1024 interrupts = <GIC_SPI 749 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
1025 <GIC_SPI 750 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
1026 <GIC_SPI 751 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
1027 <GIC_SPI 752 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
1028 interrupt-names = "jo 753 interrupt-names = "job", "mmu", "gpu", "event";
1029 clocks = <&cpg CPG_MO 754 clocks = <&cpg CPG_MOD R9A07G044_GPU_CLK>,
1030 <&cpg CPG_MO 755 <&cpg CPG_MOD R9A07G044_GPU_AXI_CLK>,
1031 <&cpg CPG_MO 756 <&cpg CPG_MOD R9A07G044_GPU_ACE_CLK>;
1032 clock-names = "gpu", 757 clock-names = "gpu", "bus", "bus_ace";
1033 power-domains = <&cpg 758 power-domains = <&cpg>;
1034 resets = <&cpg R9A07G 759 resets = <&cpg R9A07G044_GPU_RESETN>,
1035 <&cpg R9A07G 760 <&cpg R9A07G044_GPU_AXI_RESETN>,
1036 <&cpg R9A07G 761 <&cpg R9A07G044_GPU_ACE_RESETN>;
1037 reset-names = "rst", 762 reset-names = "rst", "axi_rst", "ace_rst";
1038 operating-points-v2 = 763 operating-points-v2 = <&gpu_opp_table>;
1039 }; 764 };
1040 765
1041 gic: interrupt-controller@119 766 gic: interrupt-controller@11900000 {
1042 compatible = "arm,gic 767 compatible = "arm,gic-v3";
1043 #interrupt-cells = <3 768 #interrupt-cells = <3>;
1044 #address-cells = <0>; 769 #address-cells = <0>;
1045 interrupt-controller; 770 interrupt-controller;
1046 reg = <0x0 0x11900000 !! 771 reg = <0x0 0x11900000 0 0x40000>,
1047 <0x0 0x11940000 !! 772 <0x0 0x11940000 0 0x60000>;
1048 interrupts = <GIC_PPI 773 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
1049 }; 774 };
1050 775
1051 sdhi0: mmc@11c00000 { 776 sdhi0: mmc@11c00000 {
1052 compatible = "renesas 777 compatible = "renesas,sdhi-r9a07g044",
1053 "renesas !! 778 "renesas,rcar-gen3-sdhi";
1054 reg = <0x0 0x11c00000 779 reg = <0x0 0x11c00000 0 0x10000>;
1055 interrupts = <GIC_SPI 780 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
1056 <GIC_SPI 781 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
1057 clocks = <&cpg CPG_MO 782 clocks = <&cpg CPG_MOD R9A07G044_SDHI0_IMCLK>,
1058 <&cpg CPG_MO 783 <&cpg CPG_MOD R9A07G044_SDHI0_CLK_HS>,
1059 <&cpg CPG_MO 784 <&cpg CPG_MOD R9A07G044_SDHI0_IMCLK2>,
1060 <&cpg CPG_MO 785 <&cpg CPG_MOD R9A07G044_SDHI0_ACLK>;
1061 clock-names = "core", 786 clock-names = "core", "clkh", "cd", "aclk";
1062 resets = <&cpg R9A07G 787 resets = <&cpg R9A07G044_SDHI0_IXRST>;
1063 power-domains = <&cpg 788 power-domains = <&cpg>;
1064 status = "disabled"; 789 status = "disabled";
1065 }; 790 };
1066 791
1067 sdhi1: mmc@11c10000 { 792 sdhi1: mmc@11c10000 {
1068 compatible = "renesas 793 compatible = "renesas,sdhi-r9a07g044",
1069 "renesas !! 794 "renesas,rcar-gen3-sdhi";
1070 reg = <0x0 0x11c10000 795 reg = <0x0 0x11c10000 0 0x10000>;
1071 interrupts = <GIC_SPI 796 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
1072 <GIC_SPI 797 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
1073 clocks = <&cpg CPG_MO 798 clocks = <&cpg CPG_MOD R9A07G044_SDHI1_IMCLK>,
1074 <&cpg CPG_MO 799 <&cpg CPG_MOD R9A07G044_SDHI1_CLK_HS>,
1075 <&cpg CPG_MO 800 <&cpg CPG_MOD R9A07G044_SDHI1_IMCLK2>,
1076 <&cpg CPG_MO 801 <&cpg CPG_MOD R9A07G044_SDHI1_ACLK>;
1077 clock-names = "core", 802 clock-names = "core", "clkh", "cd", "aclk";
1078 resets = <&cpg R9A07G 803 resets = <&cpg R9A07G044_SDHI1_IXRST>;
1079 power-domains = <&cpg 804 power-domains = <&cpg>;
1080 status = "disabled"; 805 status = "disabled";
1081 }; 806 };
1082 807
1083 eth0: ethernet@11c20000 { 808 eth0: ethernet@11c20000 {
1084 compatible = "renesas 809 compatible = "renesas,r9a07g044-gbeth",
1085 "renesas 810 "renesas,rzg2l-gbeth";
1086 reg = <0 0x11c20000 0 811 reg = <0 0x11c20000 0 0x10000>;
1087 interrupts = <GIC_SPI 812 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
1088 <GIC_SPI 813 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
1089 <GIC_SPI 814 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
1090 interrupt-names = "mu 815 interrupt-names = "mux", "fil", "arp_ns";
1091 phy-mode = "rgmii"; 816 phy-mode = "rgmii";
1092 clocks = <&cpg CPG_MO 817 clocks = <&cpg CPG_MOD R9A07G044_ETH0_CLK_AXI>,
1093 <&cpg CPG_MO 818 <&cpg CPG_MOD R9A07G044_ETH0_CLK_CHI>,
1094 <&cpg CPG_CO 819 <&cpg CPG_CORE R9A07G044_CLK_HP>;
1095 clock-names = "axi", 820 clock-names = "axi", "chi", "refclk";
1096 resets = <&cpg R9A07G 821 resets = <&cpg R9A07G044_ETH0_RST_HW_N>;
1097 power-domains = <&cpg 822 power-domains = <&cpg>;
1098 #address-cells = <1>; 823 #address-cells = <1>;
1099 #size-cells = <0>; 824 #size-cells = <0>;
1100 status = "disabled"; 825 status = "disabled";
1101 }; 826 };
1102 827
1103 eth1: ethernet@11c30000 { 828 eth1: ethernet@11c30000 {
1104 compatible = "renesas 829 compatible = "renesas,r9a07g044-gbeth",
1105 "renesas 830 "renesas,rzg2l-gbeth";
1106 reg = <0 0x11c30000 0 831 reg = <0 0x11c30000 0 0x10000>;
1107 interrupts = <GIC_SPI 832 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
1108 <GIC_SPI 833 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
1109 <GIC_SPI 834 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
1110 interrupt-names = "mu 835 interrupt-names = "mux", "fil", "arp_ns";
1111 phy-mode = "rgmii"; 836 phy-mode = "rgmii";
1112 clocks = <&cpg CPG_MO 837 clocks = <&cpg CPG_MOD R9A07G044_ETH1_CLK_AXI>,
1113 <&cpg CPG_MO 838 <&cpg CPG_MOD R9A07G044_ETH1_CLK_CHI>,
1114 <&cpg CPG_CO 839 <&cpg CPG_CORE R9A07G044_CLK_HP>;
1115 clock-names = "axi", 840 clock-names = "axi", "chi", "refclk";
1116 resets = <&cpg R9A07G 841 resets = <&cpg R9A07G044_ETH1_RST_HW_N>;
1117 power-domains = <&cpg 842 power-domains = <&cpg>;
1118 #address-cells = <1>; 843 #address-cells = <1>;
1119 #size-cells = <0>; 844 #size-cells = <0>;
1120 status = "disabled"; 845 status = "disabled";
1121 }; 846 };
1122 847
1123 phyrst: usbphy-ctrl@11c40000 848 phyrst: usbphy-ctrl@11c40000 {
1124 compatible = "renesas 849 compatible = "renesas,r9a07g044-usbphy-ctrl",
1125 "renesas 850 "renesas,rzg2l-usbphy-ctrl";
1126 reg = <0 0x11c40000 0 851 reg = <0 0x11c40000 0 0x10000>;
1127 clocks = <&cpg CPG_MO 852 clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>;
1128 resets = <&cpg R9A07G 853 resets = <&cpg R9A07G044_USB_PRESETN>;
1129 power-domains = <&cpg 854 power-domains = <&cpg>;
1130 #reset-cells = <1>; 855 #reset-cells = <1>;
1131 status = "disabled"; 856 status = "disabled";
1132 <<
1133 usb0_vbus_otg: regula <<
1134 regulator-nam <<
1135 }; <<
1136 }; 857 };
1137 858
1138 ohci0: usb@11c50000 { 859 ohci0: usb@11c50000 {
1139 compatible = "generic 860 compatible = "generic-ohci";
1140 reg = <0 0x11c50000 0 861 reg = <0 0x11c50000 0 0x100>;
1141 interrupts = <GIC_SPI 862 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
1142 clocks = <&cpg CPG_MO 863 clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>,
1143 <&cpg CPG_MO 864 <&cpg CPG_MOD R9A07G044_USB_U2H0_HCLK>;
1144 resets = <&phyrst 0>, 865 resets = <&phyrst 0>,
1145 <&cpg R9A07G 866 <&cpg R9A07G044_USB_U2H0_HRESETN>;
1146 phys = <&usb2_phy0 1> 867 phys = <&usb2_phy0 1>;
1147 phy-names = "usb"; 868 phy-names = "usb";
1148 power-domains = <&cpg 869 power-domains = <&cpg>;
1149 status = "disabled"; 870 status = "disabled";
1150 }; 871 };
1151 872
1152 ohci1: usb@11c70000 { 873 ohci1: usb@11c70000 {
1153 compatible = "generic 874 compatible = "generic-ohci";
1154 reg = <0 0x11c70000 0 875 reg = <0 0x11c70000 0 0x100>;
1155 interrupts = <GIC_SPI 876 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
1156 clocks = <&cpg CPG_MO 877 clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>,
1157 <&cpg CPG_MO 878 <&cpg CPG_MOD R9A07G044_USB_U2H1_HCLK>;
1158 resets = <&phyrst 1>, 879 resets = <&phyrst 1>,
1159 <&cpg R9A07G 880 <&cpg R9A07G044_USB_U2H1_HRESETN>;
1160 phys = <&usb2_phy1 1> 881 phys = <&usb2_phy1 1>;
1161 phy-names = "usb"; 882 phy-names = "usb";
1162 power-domains = <&cpg 883 power-domains = <&cpg>;
1163 status = "disabled"; 884 status = "disabled";
1164 }; 885 };
1165 886
1166 ehci0: usb@11c50100 { 887 ehci0: usb@11c50100 {
1167 compatible = "generic 888 compatible = "generic-ehci";
1168 reg = <0 0x11c50100 0 889 reg = <0 0x11c50100 0 0x100>;
1169 interrupts = <GIC_SPI 890 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
1170 clocks = <&cpg CPG_MO 891 clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>,
1171 <&cpg CPG_MO 892 <&cpg CPG_MOD R9A07G044_USB_U2H0_HCLK>;
1172 resets = <&phyrst 0>, 893 resets = <&phyrst 0>,
1173 <&cpg R9A07G 894 <&cpg R9A07G044_USB_U2H0_HRESETN>;
1174 phys = <&usb2_phy0 2> 895 phys = <&usb2_phy0 2>;
1175 phy-names = "usb"; 896 phy-names = "usb";
1176 companion = <&ohci0>; 897 companion = <&ohci0>;
1177 power-domains = <&cpg 898 power-domains = <&cpg>;
1178 status = "disabled"; 899 status = "disabled";
1179 }; 900 };
1180 901
1181 ehci1: usb@11c70100 { 902 ehci1: usb@11c70100 {
1182 compatible = "generic 903 compatible = "generic-ehci";
1183 reg = <0 0x11c70100 0 904 reg = <0 0x11c70100 0 0x100>;
1184 interrupts = <GIC_SPI 905 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
1185 clocks = <&cpg CPG_MO 906 clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>,
1186 <&cpg CPG_MO 907 <&cpg CPG_MOD R9A07G044_USB_U2H1_HCLK>;
1187 resets = <&phyrst 1>, 908 resets = <&phyrst 1>,
1188 <&cpg R9A07G 909 <&cpg R9A07G044_USB_U2H1_HRESETN>;
1189 phys = <&usb2_phy1 2> 910 phys = <&usb2_phy1 2>;
1190 phy-names = "usb"; 911 phy-names = "usb";
1191 companion = <&ohci1>; 912 companion = <&ohci1>;
1192 power-domains = <&cpg 913 power-domains = <&cpg>;
1193 status = "disabled"; 914 status = "disabled";
1194 }; 915 };
1195 916
1196 usb2_phy0: usb-phy@11c50200 { 917 usb2_phy0: usb-phy@11c50200 {
1197 compatible = "renesas 918 compatible = "renesas,usb2-phy-r9a07g044",
1198 "renesas 919 "renesas,rzg2l-usb2-phy";
1199 reg = <0 0x11c50200 0 920 reg = <0 0x11c50200 0 0x700>;
1200 interrupts = <GIC_SPI 921 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
1201 clocks = <&cpg CPG_MO 922 clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>,
1202 <&cpg CPG_MO 923 <&cpg CPG_MOD R9A07G044_USB_U2H0_HCLK>;
1203 resets = <&phyrst 0>; 924 resets = <&phyrst 0>;
1204 #phy-cells = <1>; 925 #phy-cells = <1>;
1205 power-domains = <&cpg 926 power-domains = <&cpg>;
1206 status = "disabled"; 927 status = "disabled";
1207 }; 928 };
1208 929
1209 usb2_phy1: usb-phy@11c70200 { 930 usb2_phy1: usb-phy@11c70200 {
1210 compatible = "renesas 931 compatible = "renesas,usb2-phy-r9a07g044",
1211 "renesas 932 "renesas,rzg2l-usb2-phy";
1212 reg = <0 0x11c70200 0 933 reg = <0 0x11c70200 0 0x700>;
1213 interrupts = <GIC_SPI 934 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
1214 clocks = <&cpg CPG_MO 935 clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>,
1215 <&cpg CPG_MO 936 <&cpg CPG_MOD R9A07G044_USB_U2H1_HCLK>;
1216 resets = <&phyrst 1>; 937 resets = <&phyrst 1>;
1217 #phy-cells = <1>; 938 #phy-cells = <1>;
1218 power-domains = <&cpg 939 power-domains = <&cpg>;
1219 status = "disabled"; 940 status = "disabled";
1220 }; 941 };
1221 942
1222 hsusb: usb@11c60000 { 943 hsusb: usb@11c60000 {
1223 compatible = "renesas 944 compatible = "renesas,usbhs-r9a07g044",
1224 "renesas !! 945 "renesas,rza2-usbhs";
1225 reg = <0 0x11c60000 0 946 reg = <0 0x11c60000 0 0x10000>;
1226 interrupts = <GIC_SPI 947 interrupts = <GIC_SPI 100 IRQ_TYPE_EDGE_RISING>,
1227 <GIC_SPI 948 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
1228 <GIC_SPI 949 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
1229 <GIC_SPI 950 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
1230 clocks = <&cpg CPG_MO 951 clocks = <&cpg CPG_MOD R9A07G044_USB_PCLK>,
1231 <&cpg CPG_MO 952 <&cpg CPG_MOD R9A07G044_USB_U2P_EXR_CPUCLK>;
1232 resets = <&phyrst 0>, 953 resets = <&phyrst 0>,
1233 <&cpg R9A07G 954 <&cpg R9A07G044_USB_U2P_EXL_SYSRST>;
1234 renesas,buswait = <7> 955 renesas,buswait = <7>;
1235 phys = <&usb2_phy0 3> 956 phys = <&usb2_phy0 3>;
1236 phy-names = "usb"; 957 phy-names = "usb";
1237 power-domains = <&cpg 958 power-domains = <&cpg>;
1238 status = "disabled"; 959 status = "disabled";
1239 }; 960 };
1240 961
1241 wdt0: watchdog@12800800 { 962 wdt0: watchdog@12800800 {
1242 compatible = "renesas 963 compatible = "renesas,r9a07g044-wdt",
1243 "renesas 964 "renesas,rzg2l-wdt";
1244 reg = <0 0x12800800 0 965 reg = <0 0x12800800 0 0x400>;
1245 clocks = <&cpg CPG_MO 966 clocks = <&cpg CPG_MOD R9A07G044_WDT0_PCLK>,
1246 <&cpg CPG_MO 967 <&cpg CPG_MOD R9A07G044_WDT0_CLK>;
1247 clock-names = "pclk", 968 clock-names = "pclk", "oscclk";
1248 interrupts = <GIC_SPI 969 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
1249 <GIC_SPI 970 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
1250 interrupt-names = "wd 971 interrupt-names = "wdt", "perrout";
1251 resets = <&cpg R9A07G 972 resets = <&cpg R9A07G044_WDT0_PRESETN>;
1252 power-domains = <&cpg 973 power-domains = <&cpg>;
1253 status = "disabled"; 974 status = "disabled";
1254 }; 975 };
1255 976
1256 wdt1: watchdog@12800c00 { 977 wdt1: watchdog@12800c00 {
1257 compatible = "renesas 978 compatible = "renesas,r9a07g044-wdt",
1258 "renesas 979 "renesas,rzg2l-wdt";
1259 reg = <0 0x12800C00 0 980 reg = <0 0x12800C00 0 0x400>;
1260 clocks = <&cpg CPG_MO 981 clocks = <&cpg CPG_MOD R9A07G044_WDT1_PCLK>,
1261 <&cpg CPG_MO 982 <&cpg CPG_MOD R9A07G044_WDT1_CLK>;
1262 clock-names = "pclk", 983 clock-names = "pclk", "oscclk";
1263 interrupts = <GIC_SPI 984 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
1264 <GIC_SPI 985 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
1265 interrupt-names = "wd 986 interrupt-names = "wdt", "perrout";
1266 resets = <&cpg R9A07G 987 resets = <&cpg R9A07G044_WDT1_PRESETN>;
1267 power-domains = <&cpg 988 power-domains = <&cpg>;
1268 status = "disabled"; 989 status = "disabled";
1269 }; 990 };
1270 991
1271 ostm0: timer@12801000 { 992 ostm0: timer@12801000 {
1272 compatible = "renesas 993 compatible = "renesas,r9a07g044-ostm",
1273 "renesas 994 "renesas,ostm";
1274 reg = <0x0 0x12801000 995 reg = <0x0 0x12801000 0x0 0x400>;
1275 interrupts = <GIC_SPI 996 interrupts = <GIC_SPI 46 IRQ_TYPE_EDGE_RISING>;
1276 clocks = <&cpg CPG_MO 997 clocks = <&cpg CPG_MOD R9A07G044_OSTM0_PCLK>;
1277 resets = <&cpg R9A07G 998 resets = <&cpg R9A07G044_OSTM0_PRESETZ>;
1278 power-domains = <&cpg 999 power-domains = <&cpg>;
1279 status = "disabled"; 1000 status = "disabled";
1280 }; 1001 };
1281 1002
1282 ostm1: timer@12801400 { 1003 ostm1: timer@12801400 {
1283 compatible = "renesas 1004 compatible = "renesas,r9a07g044-ostm",
1284 "renesas 1005 "renesas,ostm";
1285 reg = <0x0 0x12801400 1006 reg = <0x0 0x12801400 0x0 0x400>;
1286 interrupts = <GIC_SPI 1007 interrupts = <GIC_SPI 47 IRQ_TYPE_EDGE_RISING>;
1287 clocks = <&cpg CPG_MO 1008 clocks = <&cpg CPG_MOD R9A07G044_OSTM1_PCLK>;
1288 resets = <&cpg R9A07G 1009 resets = <&cpg R9A07G044_OSTM1_PRESETZ>;
1289 power-domains = <&cpg 1010 power-domains = <&cpg>;
1290 status = "disabled"; 1011 status = "disabled";
1291 }; 1012 };
1292 1013
1293 ostm2: timer@12801800 { 1014 ostm2: timer@12801800 {
1294 compatible = "renesas 1015 compatible = "renesas,r9a07g044-ostm",
1295 "renesas 1016 "renesas,ostm";
1296 reg = <0x0 0x12801800 1017 reg = <0x0 0x12801800 0x0 0x400>;
1297 interrupts = <GIC_SPI 1018 interrupts = <GIC_SPI 48 IRQ_TYPE_EDGE_RISING>;
1298 clocks = <&cpg CPG_MO 1019 clocks = <&cpg CPG_MOD R9A07G044_OSTM2_PCLK>;
1299 resets = <&cpg R9A07G 1020 resets = <&cpg R9A07G044_OSTM2_PRESETZ>;
1300 power-domains = <&cpg 1021 power-domains = <&cpg>;
1301 status = "disabled"; 1022 status = "disabled";
1302 }; 1023 };
1303 }; 1024 };
1304 1025
1305 thermal-zones { 1026 thermal-zones {
1306 cpu-thermal { 1027 cpu-thermal {
1307 polling-delay-passive 1028 polling-delay-passive = <250>;
1308 polling-delay = <1000 1029 polling-delay = <1000>;
1309 thermal-sensors = <&t 1030 thermal-sensors = <&tsu 0>;
1310 sustainable-power = < 1031 sustainable-power = <717>;
1311 1032
1312 cooling-maps { 1033 cooling-maps {
1313 map0 { 1034 map0 {
1314 trip 1035 trip = <&target>;
1315 cooli 1036 cooling-device = <&cpu0 0 2>;
1316 contr 1037 contribution = <1024>;
1317 }; 1038 };
1318 }; 1039 };
1319 1040
1320 trips { 1041 trips {
1321 sensor_crit: 1042 sensor_crit: sensor-crit {
1322 tempe 1043 temperature = <125000>;
1323 hyste 1044 hysteresis = <1000>;
1324 type 1045 type = "critical";
1325 }; 1046 };
1326 1047
1327 target: trip- 1048 target: trip-point {
1328 tempe 1049 temperature = <100000>;
1329 hyste 1050 hysteresis = <1000>;
1330 type 1051 type = "passive";
1331 }; 1052 };
1332 }; 1053 };
1333 }; 1054 };
1334 }; 1055 };
1335 1056
1336 timer { 1057 timer {
1337 compatible = "arm,armv8-timer 1058 compatible = "arm,armv8-timer";
1338 interrupts-extended = <&gic G !! 1059 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
1339 <&gic G !! 1060 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
1340 <&gic G !! 1061 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
1341 <&gic G !! 1062 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
1342 <&gic G <<
1343 interrupt-names = "sec-phys", <<
1344 "hyp-virt"; <<
1345 }; 1063 };
1346 }; 1064 };
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