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Linux/scripts/dtc/include-prefixes/arm64/renesas/r9a07g044c2-smarc.dts

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Diff markup

Differences between /scripts/dtc/include-prefixes/arm64/renesas/r9a07g044c2-smarc.dts (Version linux-6.12-rc7) and /scripts/dtc/include-prefixes/arm64/renesas/r9a07g044c2-smarc.dts (Version linux-6.10.14)


  1 // SPDX-License-Identifier: (GPL-2.0-only OR B      1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
  2 /*                                                  2 /*
  3  * Device Tree Source for the RZ/G2LC SMARC EV      3  * Device Tree Source for the RZ/G2LC SMARC EVK board
  4  *                                                  4  *
  5  * Copyright (C) 2021 Renesas Electronics Corp      5  * Copyright (C) 2021 Renesas Electronics Corp.
  6  */                                                 6  */
  7                                                     7 
  8 /dts-v1/;                                           8 /dts-v1/;
  9                                                     9 
 10 /*                                                 10 /*
 11  * DIP-Switch SW1 setting on SoM                   11  * DIP-Switch SW1 setting on SoM
 12  * 1 : High; 0: Low                                12  * 1 : High; 0: Low
 13  * SW1-2 : SW_SD0_DEV_SEL       (1: eMMC; 0: u     13  * SW1-2 : SW_SD0_DEV_SEL       (1: eMMC; 0: uSD)
 14  * SW1-3 : SW_SCIF_CAN          (1: CAN1; 0: S     14  * SW1-3 : SW_SCIF_CAN          (1: CAN1; 0: SCIF1)
 15  * SW1-4 : SW_RSPI_CAN          (1: CAN1; 0: R     15  * SW1-4 : SW_RSPI_CAN          (1: CAN1; 0: RSPI1)
 16  * SW1-5 : SW_I2S0_I2S1         (1: I2S2 (HDMI     16  * SW1-5 : SW_I2S0_I2S1         (1: I2S2 (HDMI audio); 0: I2S0)
 17  * Please change below macros according to SW1     17  * Please change below macros according to SW1 setting
 18  */                                                18  */
 19                                                    19 
 20 #define SW_SD0_DEV_SEL  1                          20 #define SW_SD0_DEV_SEL  1
 21                                                    21 
 22 #define SW_SCIF_CAN     0                          22 #define SW_SCIF_CAN     0
 23 #if (SW_SCIF_CAN)                                  23 #if (SW_SCIF_CAN)
 24 /* Due to HW routing, SW_RSPI_CAN is always 0      24 /* Due to HW routing, SW_RSPI_CAN is always 0 when SW_SCIF_CAN is set to 1 */
 25 #define SW_RSPI_CAN     0                          25 #define SW_RSPI_CAN     0
 26 #else                                              26 #else
 27 /* Please set SW_RSPI_CAN. Default value is 1      27 /* Please set SW_RSPI_CAN. Default value is 1 */
 28 #define SW_RSPI_CAN     1                          28 #define SW_RSPI_CAN     1
 29 #endif                                             29 #endif
 30                                                    30 
 31 #if (SW_SCIF_CAN && SW_RSPI_CAN)                   31 #if (SW_SCIF_CAN && SW_RSPI_CAN)
 32 #error "Can not set 1 to both SW_SCIF_CAN and      32 #error "Can not set 1 to both SW_SCIF_CAN and SW_RSPI_CAN due to HW routing"
 33 #endif                                             33 #endif
 34                                                    34 
 35 /* comment the #define statement to disable SC     35 /* comment the #define statement to disable SCIF1 (SER0) on PMOD1 (CN7) */
 36 #define PMOD1_SER0      1                          36 #define PMOD1_SER0      1
 37                                                    37 
 38 /*                                                 38 /*
 39  * To enable MTU3a PWM on PMOD0,                   39  * To enable MTU3a PWM on PMOD0,
 40  *  - Set DIP-Switch SW1-4 to Off position.        40  *  - Set DIP-Switch SW1-4 to Off position.
 41  *  - Set SW_RSPI_CAN macro to 0.                  41  *  - Set SW_RSPI_CAN macro to 0.
 42  *  - Set PMOD_MTU3 macro to 1.                    42  *  - Set PMOD_MTU3 macro to 1.
 43  */                                                43  */
 44 #define PMOD_MTU3       0                          44 #define PMOD_MTU3       0
 45                                                    45 
 46 #if (PMOD_MTU3 && SW_RSPI_CAN)                     46 #if (PMOD_MTU3 && SW_RSPI_CAN)
 47 #error "Cannot set as both PMOD_MTU3 and SW_RS     47 #error "Cannot set as both PMOD_MTU3 and SW_RSPI_CAN are mutually exclusive"
 48 #endif                                             48 #endif
 49                                                    49 
 50 /* Please set SW_I2S0_I2S1. Default value is 0 << 
 51 #define SW_I2S0_I2S1   0                       << 
 52                                                << 
 53 #include "r9a07g044c2.dtsi"                        50 #include "r9a07g044c2.dtsi"
 54 #include "rzg2lc-smarc-som.dtsi"                   51 #include "rzg2lc-smarc-som.dtsi"
 55 #include "rzg2lc-smarc.dtsi"                       52 #include "rzg2lc-smarc.dtsi"
 56                                                    53 
 57 / {                                                54 / {
 58         model = "Renesas SMARC EVK based on r9     55         model = "Renesas SMARC EVK based on r9a07g044c2";
 59         compatible = "renesas,smarc-evk", "ren     56         compatible = "renesas,smarc-evk", "renesas,r9a07g044c2", "renesas,r9a07g044";
 60 };                                                 57 };
                                                      

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