1 // SPDX-License-Identifier: (GPL-2.0-only OR B 1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 /* 2 /*
3 * Device Tree Source for the RZ/V2L SoC 3 * Device Tree Source for the RZ/V2L SoC
4 * 4 *
5 * Copyright (C) 2021 Renesas Electronics Corp 5 * Copyright (C) 2021 Renesas Electronics Corp.
6 */ 6 */
7 7
8 #include <dt-bindings/interrupt-controller/arm 8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/clock/r9a07g054-cpg.h> 9 #include <dt-bindings/clock/r9a07g054-cpg.h>
10 10
11 / { 11 / {
12 compatible = "renesas,r9a07g054"; 12 compatible = "renesas,r9a07g054";
13 #address-cells = <2>; 13 #address-cells = <2>;
14 #size-cells = <2>; 14 #size-cells = <2>;
15 15
16 audio_clk1: audio1-clk { !! 16 audio_clk1: audio_clk1 {
17 compatible = "fixed-clock"; 17 compatible = "fixed-clock";
18 #clock-cells = <0>; 18 #clock-cells = <0>;
19 /* This value must be overridd 19 /* This value must be overridden by boards that provide it */
20 clock-frequency = <0>; 20 clock-frequency = <0>;
21 }; 21 };
22 22
23 audio_clk2: audio2-clk { !! 23 audio_clk2: audio_clk2 {
24 compatible = "fixed-clock"; 24 compatible = "fixed-clock";
25 #clock-cells = <0>; 25 #clock-cells = <0>;
26 /* This value must be overridd 26 /* This value must be overridden by boards that provide it */
27 clock-frequency = <0>; 27 clock-frequency = <0>;
28 }; 28 };
29 29
30 /* External CAN clock - to be overridd 30 /* External CAN clock - to be overridden by boards that provide it */
31 can_clk: can-clk { !! 31 can_clk: can {
32 compatible = "fixed-clock"; 32 compatible = "fixed-clock";
33 #clock-cells = <0>; 33 #clock-cells = <0>;
34 clock-frequency = <0>; 34 clock-frequency = <0>;
35 }; 35 };
36 36
37 /* clock can be either from exclk or c 37 /* clock can be either from exclk or crystal oscillator (XIN/XOUT) */
38 extal_clk: extal-clk { !! 38 extal_clk: extal {
39 compatible = "fixed-clock"; 39 compatible = "fixed-clock";
40 #clock-cells = <0>; 40 #clock-cells = <0>;
41 /* This value must be overridd 41 /* This value must be overridden by the board */
42 clock-frequency = <0>; 42 clock-frequency = <0>;
43 }; 43 };
44 44
45 cluster0_opp: opp-table-0 { <<
46 compatible = "operating-points <<
47 opp-shared; <<
48 <<
49 opp-150000000 { <<
50 opp-hz = /bits/ 64 <15 <<
51 opp-microvolt = <11000 <<
52 clock-latency-ns = <30 <<
53 }; <<
54 opp-300000000 { <<
55 opp-hz = /bits/ 64 <30 <<
56 opp-microvolt = <11000 <<
57 clock-latency-ns = <30 <<
58 }; <<
59 opp-600000000 { <<
60 opp-hz = /bits/ 64 <60 <<
61 opp-microvolt = <11000 <<
62 clock-latency-ns = <30 <<
63 }; <<
64 opp-1200000000 { <<
65 opp-hz = /bits/ 64 <12 <<
66 opp-microvolt = <11000 <<
67 clock-latency-ns = <30 <<
68 opp-suspend; <<
69 }; <<
70 }; <<
71 <<
72 cpus { 45 cpus {
73 #address-cells = <1>; 46 #address-cells = <1>;
74 #size-cells = <0>; 47 #size-cells = <0>;
75 48
76 cpu-map { 49 cpu-map {
77 cluster0 { 50 cluster0 {
78 core0 { 51 core0 {
79 cpu = 52 cpu = <&cpu0>;
80 }; 53 };
81 core1 { 54 core1 {
82 cpu = 55 cpu = <&cpu1>;
83 }; 56 };
84 }; 57 };
85 }; 58 };
86 59
87 cpu0: cpu@0 { 60 cpu0: cpu@0 {
88 compatible = "arm,cort 61 compatible = "arm,cortex-a55";
89 reg = <0>; 62 reg = <0>;
90 device_type = "cpu"; 63 device_type = "cpu";
91 #cooling-cells = <2>; 64 #cooling-cells = <2>;
92 next-level-cache = <&L 65 next-level-cache = <&L3_CA55>;
93 enable-method = "psci" 66 enable-method = "psci";
94 clocks = <&cpg CPG_COR 67 clocks = <&cpg CPG_CORE R9A07G054_CLK_I>;
95 operating-points-v2 = <<
96 }; 68 };
97 69
98 cpu1: cpu@100 { 70 cpu1: cpu@100 {
99 compatible = "arm,cort 71 compatible = "arm,cortex-a55";
100 reg = <0x100>; 72 reg = <0x100>;
101 device_type = "cpu"; 73 device_type = "cpu";
102 next-level-cache = <&L 74 next-level-cache = <&L3_CA55>;
103 enable-method = "psci" 75 enable-method = "psci";
104 clocks = <&cpg CPG_COR 76 clocks = <&cpg CPG_CORE R9A07G054_CLK_I>;
105 operating-points-v2 = <<
106 }; 77 };
107 78
108 L3_CA55: cache-controller-0 { 79 L3_CA55: cache-controller-0 {
109 compatible = "cache"; 80 compatible = "cache";
110 cache-unified; 81 cache-unified;
111 cache-size = <0x40000> 82 cache-size = <0x40000>;
112 cache-level = <3>; <<
113 }; <<
114 }; <<
115 <<
116 gpu_opp_table: opp-table-1 { <<
117 compatible = "operating-points <<
118 <<
119 opp-500000000 { <<
120 opp-hz = /bits/ 64 <50 <<
121 opp-microvolt = <11000 <<
122 }; <<
123 <<
124 opp-400000000 { <<
125 opp-hz = /bits/ 64 <40 <<
126 opp-microvolt = <11000 <<
127 }; <<
128 <<
129 opp-250000000 { <<
130 opp-hz = /bits/ 64 <25 <<
131 opp-microvolt = <11000 <<
132 }; <<
133 <<
134 opp-200000000 { <<
135 opp-hz = /bits/ 64 <20 <<
136 opp-microvolt = <11000 <<
137 }; <<
138 <<
139 opp-125000000 { <<
140 opp-hz = /bits/ 64 <12 <<
141 opp-microvolt = <11000 <<
142 }; <<
143 <<
144 opp-100000000 { <<
145 opp-hz = /bits/ 64 <10 <<
146 opp-microvolt = <11000 <<
147 }; <<
148 <<
149 opp-62500000 { <<
150 opp-hz = /bits/ 64 <62 <<
151 opp-microvolt = <11000 <<
152 }; <<
153 <<
154 opp-50000000 { <<
155 opp-hz = /bits/ 64 <50 <<
156 opp-microvolt = <11000 <<
157 }; 83 };
158 }; 84 };
159 85
160 pmu { <<
161 compatible = "arm,cortex-a55-p <<
162 interrupts-extended = <&gic GI <<
163 }; <<
164 <<
165 psci { 86 psci {
166 compatible = "arm,psci-1.0", " 87 compatible = "arm,psci-1.0", "arm,psci-0.2";
167 method = "smc"; 88 method = "smc";
168 }; 89 };
169 90
170 soc: soc { 91 soc: soc {
171 compatible = "simple-bus"; 92 compatible = "simple-bus";
172 interrupt-parent = <&gic>; 93 interrupt-parent = <&gic>;
173 #address-cells = <2>; 94 #address-cells = <2>;
174 #size-cells = <2>; 95 #size-cells = <2>;
175 ranges; 96 ranges;
176 97
177 mtu3: timer@10001200 { <<
178 compatible = "renesas, <<
179 "renesas, <<
180 reg = <0 0x10001200 0 <<
181 interrupts = <GIC_SPI <<
182 <GIC_SPI <<
183 <GIC_SPI <<
184 <GIC_SPI <<
185 <GIC_SPI <<
186 <GIC_SPI <<
187 <GIC_SPI <<
188 <GIC_SPI <<
189 <GIC_SPI <<
190 <GIC_SPI <<
191 <GIC_SPI <<
192 <GIC_SPI <<
193 <GIC_SPI <<
194 <GIC_SPI <<
195 <GIC_SPI <<
196 <GIC_SPI <<
197 <GIC_SPI <<
198 <GIC_SPI <<
199 <GIC_SPI <<
200 <GIC_SPI <<
201 <GIC_SPI <<
202 <GIC_SPI <<
203 <GIC_SPI <<
204 <GIC_SPI <<
205 <GIC_SPI <<
206 <GIC_SPI <<
207 <GIC_SPI <<
208 <GIC_SPI <<
209 <GIC_SPI <<
210 <GIC_SPI <<
211 <GIC_SPI <<
212 <GIC_SPI <<
213 <GIC_SPI <<
214 <GIC_SPI <<
215 <GIC_SPI <<
216 <GIC_SPI <<
217 <GIC_SPI <<
218 <GIC_SPI <<
219 <GIC_SPI <<
220 <GIC_SPI <<
221 <GIC_SPI <<
222 <GIC_SPI <<
223 <GIC_SPI <<
224 <GIC_SPI <<
225 interrupt-names = "tgi <<
226 "tci <<
227 "tgi <<
228 "tgi <<
229 "tgi <<
230 "tci <<
231 "tgi <<
232 "tci <<
233 "tgi <<
234 "tgi <<
235 "tci <<
236 "tgi <<
237 "tci <<
238 "tgi <<
239 "tci <<
240 clocks = <&cpg CPG_MOD <<
241 power-domains = <&cpg> <<
242 resets = <&cpg R9A07G0 <<
243 #pwm-cells = <2>; <<
244 status = "disabled"; <<
245 }; <<
246 <<
247 ssi0: ssi@10049c00 { 98 ssi0: ssi@10049c00 {
248 compatible = "renesas, <<
249 "renesas, <<
250 reg = <0 0x10049c00 0 99 reg = <0 0x10049c00 0 0x400>;
251 interrupts = <GIC_SPI <<
252 <GIC_SPI <<
253 <GIC_SPI <<
254 interrupt-names = "int <<
255 clocks = <&cpg CPG_MOD <<
256 <&cpg CPG_MOD <<
257 <&audio_clk1> <<
258 clock-names = "ssi", " <<
259 resets = <&cpg R9A07G0 <<
260 dmas = <&dmac 0x2655>, <<
261 dma-names = "tx", "rx" <<
262 power-domains = <&cpg> <<
263 #sound-dai-cells = <0> <<
264 status = "disabled"; <<
265 }; <<
266 <<
267 ssi1: ssi@1004a000 { <<
268 compatible = "renesas, <<
269 "renesas, <<
270 reg = <0 0x1004a000 0 <<
271 interrupts = <GIC_SPI <<
272 <GIC_SPI <<
273 <GIC_SPI <<
274 interrupt-names = "int <<
275 clocks = <&cpg CPG_MOD <<
276 <&cpg CPG_MOD <<
277 <&audio_clk1> <<
278 clock-names = "ssi", " <<
279 resets = <&cpg R9A07G0 <<
280 dmas = <&dmac 0x2659>, <<
281 dma-names = "tx", "rx" <<
282 power-domains = <&cpg> <<
283 #sound-dai-cells = <0> <<
284 status = "disabled"; <<
285 }; <<
286 <<
287 ssi2: ssi@1004a400 { <<
288 compatible = "renesas, <<
289 "renesas, <<
290 reg = <0 0x1004a400 0 <<
291 interrupts = <GIC_SPI <<
292 <GIC_SPI <<
293 interrupt-names = "int <<
294 clocks = <&cpg CPG_MOD <<
295 <&cpg CPG_MOD <<
296 <&audio_clk1> <<
297 clock-names = "ssi", " <<
298 resets = <&cpg R9A07G0 <<
299 dmas = <&dmac 0x265f>; <<
300 dma-names = "rt"; <<
301 power-domains = <&cpg> <<
302 #sound-dai-cells = <0> <<
303 status = "disabled"; <<
304 }; <<
305 <<
306 ssi3: ssi@1004a800 { <<
307 compatible = "renesas, <<
308 "renesas, <<
309 reg = <0 0x1004a800 0 <<
310 interrupts = <GIC_SPI <<
311 <GIC_SPI <<
312 <GIC_SPI <<
313 interrupt-names = "int <<
314 clocks = <&cpg CPG_MOD <<
315 <&cpg CPG_MOD <<
316 <&audio_clk1> <<
317 clock-names = "ssi", " <<
318 resets = <&cpg R9A07G0 <<
319 dmas = <&dmac 0x2661>, <<
320 dma-names = "tx", "rx" <<
321 power-domains = <&cpg> <<
322 #sound-dai-cells = <0> 100 #sound-dai-cells = <0>;
323 status = "disabled"; !! 101 /* place holder */
324 }; <<
325 <<
326 spi0: spi@1004ac00 { <<
327 compatible = "renesas, <<
328 reg = <0 0x1004ac00 0 <<
329 interrupts = <GIC_SPI <<
330 <GIC_SPI <<
331 <GIC_SPI <<
332 interrupt-names = "err <<
333 clocks = <&cpg CPG_MOD <<
334 resets = <&cpg R9A07G0 <<
335 dmas = <&dmac 0x2e95>, <<
336 dma-names = "tx", "rx" <<
337 power-domains = <&cpg> <<
338 num-cs = <1>; <<
339 #address-cells = <1>; <<
340 #size-cells = <0>; <<
341 status = "disabled"; <<
342 }; 102 };
343 103
344 spi1: spi@1004b000 { 104 spi1: spi@1004b000 {
345 compatible = "renesas, <<
346 reg = <0 0x1004b000 0 105 reg = <0 0x1004b000 0 0x400>;
347 interrupts = <GIC_SPI <<
348 <GIC_SPI <<
349 <GIC_SPI <<
350 interrupt-names = "err <<
351 clocks = <&cpg CPG_MOD <<
352 resets = <&cpg R9A07G0 <<
353 dmas = <&dmac 0x2e99>, <<
354 dma-names = "tx", "rx" <<
355 power-domains = <&cpg> <<
356 num-cs = <1>; <<
357 #address-cells = <1>; <<
358 #size-cells = <0>; <<
359 status = "disabled"; <<
360 }; <<
361 <<
362 spi2: spi@1004b400 { <<
363 compatible = "renesas, <<
364 reg = <0 0x1004b400 0 <<
365 interrupts = <GIC_SPI <<
366 <GIC_SPI <<
367 <GIC_SPI <<
368 interrupt-names = "err <<
369 clocks = <&cpg CPG_MOD <<
370 resets = <&cpg R9A07G0 <<
371 dmas = <&dmac 0x2e9d>, <<
372 dma-names = "tx", "rx" <<
373 power-domains = <&cpg> <<
374 num-cs = <1>; <<
375 #address-cells = <1>; 106 #address-cells = <1>;
376 #size-cells = <0>; 107 #size-cells = <0>;
377 status = "disabled"; !! 108 /* place holder */
378 }; 109 };
379 110
380 scif0: serial@1004b800 { 111 scif0: serial@1004b800 {
381 compatible = "renesas, 112 compatible = "renesas,scif-r9a07g054",
382 "renesas, 113 "renesas,scif-r9a07g044";
383 reg = <0 0x1004b800 0 114 reg = <0 0x1004b800 0 0x400>;
384 interrupts = <GIC_SPI 115 interrupts = <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>,
385 <GIC_SPI 116 <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>,
386 <GIC_SPI 117 <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>,
387 <GIC_SPI 118 <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>,
388 <GIC_SPI 119 <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>,
389 <GIC_SPI 120 <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>;
390 interrupt-names = "eri 121 interrupt-names = "eri", "rxi", "txi",
391 "bri 122 "bri", "dri", "tei";
392 clocks = <&cpg CPG_MOD 123 clocks = <&cpg CPG_MOD R9A07G054_SCIF0_CLK_PCK>;
393 clock-names = "fck"; 124 clock-names = "fck";
394 power-domains = <&cpg> 125 power-domains = <&cpg>;
395 resets = <&cpg R9A07G0 126 resets = <&cpg R9A07G054_SCIF0_RST_SYSTEM_N>;
396 status = "disabled"; 127 status = "disabled";
397 }; 128 };
398 129
399 scif1: serial@1004bc00 { 130 scif1: serial@1004bc00 {
400 compatible = "renesas, 131 compatible = "renesas,scif-r9a07g054",
401 "renesas, 132 "renesas,scif-r9a07g044";
402 reg = <0 0x1004bc00 0 133 reg = <0 0x1004bc00 0 0x400>;
403 interrupts = <GIC_SPI 134 interrupts = <GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>,
404 <GIC_SPI 135 <GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>,
405 <GIC_SPI 136 <GIC_SPI 388 IRQ_TYPE_LEVEL_HIGH>,
406 <GIC_SPI 137 <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>,
407 <GIC_SPI 138 <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>,
408 <GIC_SPI 139 <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>;
409 interrupt-names = "eri 140 interrupt-names = "eri", "rxi", "txi",
410 "bri 141 "bri", "dri", "tei";
411 clocks = <&cpg CPG_MOD 142 clocks = <&cpg CPG_MOD R9A07G054_SCIF1_CLK_PCK>;
412 clock-names = "fck"; 143 clock-names = "fck";
413 power-domains = <&cpg> 144 power-domains = <&cpg>;
414 resets = <&cpg R9A07G0 145 resets = <&cpg R9A07G054_SCIF1_RST_SYSTEM_N>;
415 status = "disabled"; 146 status = "disabled";
416 }; 147 };
417 148
418 scif2: serial@1004c000 { 149 scif2: serial@1004c000 {
419 compatible = "renesas, 150 compatible = "renesas,scif-r9a07g054",
420 "renesas, 151 "renesas,scif-r9a07g044";
421 reg = <0 0x1004c000 0 152 reg = <0 0x1004c000 0 0x400>;
422 interrupts = <GIC_SPI 153 interrupts = <GIC_SPI 390 IRQ_TYPE_LEVEL_HIGH>,
423 <GIC_SPI 154 <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH>,
424 <GIC_SPI 155 <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>,
425 <GIC_SPI 156 <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH>,
426 <GIC_SPI 157 <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>,
427 <GIC_SPI 158 <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>;
428 interrupt-names = "eri 159 interrupt-names = "eri", "rxi", "txi",
429 "bri 160 "bri", "dri", "tei";
430 clocks = <&cpg CPG_MOD 161 clocks = <&cpg CPG_MOD R9A07G054_SCIF2_CLK_PCK>;
431 clock-names = "fck"; 162 clock-names = "fck";
432 power-domains = <&cpg> 163 power-domains = <&cpg>;
433 resets = <&cpg R9A07G0 164 resets = <&cpg R9A07G054_SCIF2_RST_SYSTEM_N>;
434 status = "disabled"; 165 status = "disabled";
435 }; 166 };
436 167
437 scif3: serial@1004c400 { 168 scif3: serial@1004c400 {
438 compatible = "renesas, 169 compatible = "renesas,scif-r9a07g054",
439 "renesas, 170 "renesas,scif-r9a07g044";
440 reg = <0 0x1004c400 0 171 reg = <0 0x1004c400 0 0x400>;
441 interrupts = <GIC_SPI 172 interrupts = <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
442 <GIC_SPI 173 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
443 <GIC_SPI 174 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
444 <GIC_SPI 175 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
445 <GIC_SPI 176 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
446 <GIC_SPI 177 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>;
447 interrupt-names = "eri 178 interrupt-names = "eri", "rxi", "txi",
448 "bri 179 "bri", "dri", "tei";
449 clocks = <&cpg CPG_MOD 180 clocks = <&cpg CPG_MOD R9A07G054_SCIF3_CLK_PCK>;
450 clock-names = "fck"; 181 clock-names = "fck";
451 power-domains = <&cpg> 182 power-domains = <&cpg>;
452 resets = <&cpg R9A07G0 183 resets = <&cpg R9A07G054_SCIF3_RST_SYSTEM_N>;
453 status = "disabled"; 184 status = "disabled";
454 }; 185 };
455 186
456 scif4: serial@1004c800 { 187 scif4: serial@1004c800 {
457 compatible = "renesas, 188 compatible = "renesas,scif-r9a07g054",
458 "renesas, 189 "renesas,scif-r9a07g044";
459 reg = <0 0x1004c800 0 190 reg = <0 0x1004c800 0 0x400>;
460 interrupts = <GIC_SPI 191 interrupts = <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
461 <GIC_SPI 192 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
462 <GIC_SPI 193 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
463 <GIC_SPI 194 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
464 <GIC_SPI 195 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
465 <GIC_SPI 196 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>;
466 interrupt-names = "eri 197 interrupt-names = "eri", "rxi", "txi",
467 "bri 198 "bri", "dri", "tei";
468 clocks = <&cpg CPG_MOD 199 clocks = <&cpg CPG_MOD R9A07G054_SCIF4_CLK_PCK>;
469 clock-names = "fck"; 200 clock-names = "fck";
470 power-domains = <&cpg> 201 power-domains = <&cpg>;
471 resets = <&cpg R9A07G0 202 resets = <&cpg R9A07G054_SCIF4_RST_SYSTEM_N>;
472 status = "disabled"; 203 status = "disabled";
473 }; 204 };
474 205
475 sci0: serial@1004d000 { 206 sci0: serial@1004d000 {
476 compatible = "renesas, 207 compatible = "renesas,r9a07g054-sci", "renesas,sci";
477 reg = <0 0x1004d000 0 208 reg = <0 0x1004d000 0 0x400>;
478 interrupts = <GIC_SPI 209 interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
479 <GIC_SPI !! 210 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
480 <GIC_SPI !! 211 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
481 <GIC_SPI 212 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>;
482 interrupt-names = "eri 213 interrupt-names = "eri", "rxi", "txi", "tei";
483 clocks = <&cpg CPG_MOD 214 clocks = <&cpg CPG_MOD R9A07G054_SCI0_CLKP>;
484 clock-names = "fck"; 215 clock-names = "fck";
485 power-domains = <&cpg> 216 power-domains = <&cpg>;
486 resets = <&cpg R9A07G0 217 resets = <&cpg R9A07G054_SCI0_RST>;
487 status = "disabled"; 218 status = "disabled";
488 }; 219 };
489 220
490 sci1: serial@1004d400 { 221 sci1: serial@1004d400 {
491 compatible = "renesas, 222 compatible = "renesas,r9a07g054-sci", "renesas,sci";
492 reg = <0 0x1004d400 0 223 reg = <0 0x1004d400 0 0x400>;
493 interrupts = <GIC_SPI 224 interrupts = <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
494 <GIC_SPI !! 225 <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>,
495 <GIC_SPI !! 226 <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>,
496 <GIC_SPI 227 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>;
497 interrupt-names = "eri 228 interrupt-names = "eri", "rxi", "txi", "tei";
498 clocks = <&cpg CPG_MOD 229 clocks = <&cpg CPG_MOD R9A07G054_SCI1_CLKP>;
499 clock-names = "fck"; 230 clock-names = "fck";
500 power-domains = <&cpg> 231 power-domains = <&cpg>;
501 resets = <&cpg R9A07G0 232 resets = <&cpg R9A07G054_SCI1_RST>;
502 status = "disabled"; 233 status = "disabled";
503 }; 234 };
504 235
505 canfd: can@10050000 { 236 canfd: can@10050000 {
506 compatible = "renesas, <<
507 reg = <0 0x10050000 0 237 reg = <0 0x10050000 0 0x8000>;
508 interrupts = <GIC_SPI !! 238 /* place holder */
509 <GIC_SPI <<
510 <GIC_SPI <<
511 <GIC_SPI <<
512 <GIC_SPI <<
513 <GIC_SPI <<
514 <GIC_SPI <<
515 <GIC_SPI <<
516 interrupt-names = "g_e <<
517 "ch0 <<
518 "ch1 <<
519 clocks = <&cpg CPG_MOD <<
520 <&cpg CPG_COR <<
521 <&can_clk>; <<
522 clock-names = "fck", " <<
523 assigned-clocks = <&cp <<
524 assigned-clock-rates = <<
525 resets = <&cpg R9A07G0 <<
526 <&cpg R9A07G0 <<
527 reset-names = "rstp_n" <<
528 power-domains = <&cpg> <<
529 status = "disabled"; <<
530 <<
531 channel0 { <<
532 status = "disa <<
533 }; <<
534 channel1 { <<
535 status = "disa <<
536 }; <<
537 }; 239 };
538 240
539 i2c0: i2c@10058000 { 241 i2c0: i2c@10058000 {
540 #address-cells = <1>; 242 #address-cells = <1>;
541 #size-cells = <0>; 243 #size-cells = <0>;
542 compatible = "renesas, <<
543 reg = <0 0x10058000 0 244 reg = <0 0x10058000 0 0x400>;
544 interrupts = <GIC_SPI !! 245 /* place holder */
545 <GIC_SPI <<
546 <GIC_SPI <<
547 <GIC_SPI <<
548 <GIC_SPI <<
549 <GIC_SPI <<
550 <GIC_SPI <<
551 <GIC_SPI <<
552 interrupt-names = "tei <<
553 "nak <<
554 clocks = <&cpg CPG_MOD <<
555 clock-frequency = <100 <<
556 resets = <&cpg R9A07G0 <<
557 power-domains = <&cpg> <<
558 status = "disabled"; <<
559 }; 246 };
560 247
561 i2c1: i2c@10058400 { 248 i2c1: i2c@10058400 {
562 #address-cells = <1>; 249 #address-cells = <1>;
563 #size-cells = <0>; 250 #size-cells = <0>;
564 compatible = "renesas, <<
565 reg = <0 0x10058400 0 251 reg = <0 0x10058400 0 0x400>;
566 interrupts = <GIC_SPI !! 252 /* place holder */
567 <GIC_SPI <<
568 <GIC_SPI <<
569 <GIC_SPI <<
570 <GIC_SPI <<
571 <GIC_SPI <<
572 <GIC_SPI <<
573 <GIC_SPI <<
574 interrupt-names = "tei <<
575 "nak <<
576 clocks = <&cpg CPG_MOD <<
577 clock-frequency = <100 <<
578 resets = <&cpg R9A07G0 <<
579 power-domains = <&cpg> <<
580 status = "disabled"; <<
581 }; <<
582 <<
583 i2c2: i2c@10058800 { <<
584 #address-cells = <1>; <<
585 #size-cells = <0>; <<
586 compatible = "renesas, <<
587 reg = <0 0x10058800 0 <<
588 interrupts = <GIC_SPI <<
589 <GIC_SPI <<
590 <GIC_SPI <<
591 <GIC_SPI <<
592 <GIC_SPI <<
593 <GIC_SPI <<
594 <GIC_SPI <<
595 <GIC_SPI <<
596 interrupt-names = "tei <<
597 "nak <<
598 clocks = <&cpg CPG_MOD <<
599 clock-frequency = <100 <<
600 resets = <&cpg R9A07G0 <<
601 power-domains = <&cpg> <<
602 status = "disabled"; <<
603 }; 253 };
604 254
605 i2c3: i2c@10058c00 { 255 i2c3: i2c@10058c00 {
606 #address-cells = <1>; 256 #address-cells = <1>;
607 #size-cells = <0>; 257 #size-cells = <0>;
608 compatible = "renesas, <<
609 reg = <0 0x10058c00 0 258 reg = <0 0x10058c00 0 0x400>;
610 interrupts = <GIC_SPI !! 259 /* place holder */
611 <GIC_SPI <<
612 <GIC_SPI <<
613 <GIC_SPI <<
614 <GIC_SPI <<
615 <GIC_SPI <<
616 <GIC_SPI <<
617 <GIC_SPI <<
618 interrupt-names = "tei <<
619 "nak <<
620 clocks = <&cpg CPG_MOD <<
621 clock-frequency = <100 <<
622 resets = <&cpg R9A07G0 <<
623 power-domains = <&cpg> <<
624 status = "disabled"; <<
625 }; 260 };
626 261
627 adc: adc@10059000 { 262 adc: adc@10059000 {
628 compatible = "renesas, <<
629 reg = <0 0x10059000 0 263 reg = <0 0x10059000 0 0x400>;
630 interrupts = <GIC_SPI !! 264 /* place holder */
631 clocks = <&cpg CPG_MOD <<
632 <&cpg CPG_MOD <<
633 clock-names = "adclk", <<
634 resets = <&cpg R9A07G0 <<
635 <&cpg R9A07G0 <<
636 reset-names = "presetn <<
637 power-domains = <&cpg> <<
638 status = "disabled"; <<
639 <<
640 #address-cells = <1>; <<
641 #size-cells = <0>; <<
642 <<
643 channel@0 { <<
644 reg = <0>; <<
645 }; <<
646 channel@1 { <<
647 reg = <1>; <<
648 }; <<
649 channel@2 { <<
650 reg = <2>; <<
651 }; <<
652 channel@3 { <<
653 reg = <3>; <<
654 }; <<
655 channel@4 { <<
656 reg = <4>; <<
657 }; <<
658 channel@5 { <<
659 reg = <5>; <<
660 }; <<
661 channel@6 { <<
662 reg = <6>; <<
663 }; <<
664 channel@7 { <<
665 reg = <7>; <<
666 }; <<
667 }; <<
668 <<
669 tsu: thermal@10059400 { <<
670 compatible = "renesas, <<
671 "renesas, <<
672 reg = <0 0x10059400 0 <<
673 clocks = <&cpg CPG_MOD <<
674 resets = <&cpg R9A07G0 <<
675 power-domains = <&cpg> <<
676 #thermal-sensor-cells <<
677 }; 265 };
678 266
679 sbc: spi@10060000 { 267 sbc: spi@10060000 {
680 compatible = "renesas, <<
681 "renesas, <<
682 reg = <0 0x10060000 0 268 reg = <0 0x10060000 0 0x10000>,
683 <0 0x20000000 0 269 <0 0x20000000 0 0x10000000>,
684 <0 0x10070000 0 270 <0 0x10070000 0 0x10000>;
685 reg-names = "regs", "d <<
686 interrupts = <GIC_SPI <<
687 clocks = <&cpg CPG_MOD <<
688 <&cpg CPG_MOD <<
689 resets = <&cpg R9A07G0 <<
690 power-domains = <&cpg> <<
691 #address-cells = <1>; 271 #address-cells = <1>;
692 #size-cells = <0>; 272 #size-cells = <0>;
693 status = "disabled"; !! 273 /* place holder */
694 }; <<
695 <<
696 cru: video@10830000 { <<
697 compatible = "renesas, <<
698 reg = <0 0x10830000 0 <<
699 clocks = <&cpg CPG_MOD <<
700 <&cpg CPG_MOD <<
701 <&cpg CPG_MOD <<
702 clock-names = "video", <<
703 interrupts = <GIC_SPI <<
704 <GIC_SPI <<
705 <GIC_SPI <<
706 interrupt-names = "ima <<
707 resets = <&cpg R9A07G0 <<
708 <&cpg R9A07G0 <<
709 reset-names = "presetn <<
710 power-domains = <&cpg> <<
711 status = "disabled"; <<
712 <<
713 ports { <<
714 #address-cells <<
715 #size-cells = <<
716 <<
717 port@0 { <<
718 #addre <<
719 #size- <<
720 <<
721 reg = <<
722 crupar <<
723 <<
724 }; <<
725 }; <<
726 <<
727 port@1 { <<
728 #addre <<
729 #size- <<
730 <<
731 reg = <<
732 crucsi <<
733 <<
734 <<
735 }; <<
736 }; <<
737 }; <<
738 }; <<
739 <<
740 csi2: csi2@10830400 { <<
741 compatible = "renesas, <<
742 reg = <0 0x10830400 0 <<
743 interrupts = <GIC_SPI <<
744 clocks = <&cpg CPG_MOD <<
745 <&cpg CPG_MOD <<
746 <&cpg CPG_MOD <<
747 clock-names = "system" <<
748 resets = <&cpg R9A07G0 <<
749 <&cpg R9A07G0 <<
750 reset-names = "presetn <<
751 power-domains = <&cpg> <<
752 status = "disabled"; <<
753 <<
754 ports { <<
755 #address-cells <<
756 #size-cells = <<
757 <<
758 port@0 { <<
759 reg = <<
760 }; <<
761 <<
762 port@1 { <<
763 #addre <<
764 #size- <<
765 reg = <<
766 <<
767 csi2cr <<
768 <<
769 <<
770 }; <<
771 }; <<
772 }; <<
773 }; <<
774 <<
775 dsi: dsi@10850000 { <<
776 compatible = "renesas, <<
777 "renesas, <<
778 reg = <0 0x10850000 0 <<
779 interrupts = <GIC_SPI <<
780 <GIC_SPI <<
781 <GIC_SPI <<
782 <GIC_SPI <<
783 <GIC_SPI <<
784 <GIC_SPI <<
785 <GIC_SPI <<
786 interrupt-names = "seq <<
787 "fer <<
788 clocks = <&cpg CPG_MOD <<
789 <&cpg CPG_MOD <<
790 <&cpg CPG_MOD <<
791 <&cpg CPG_MOD <<
792 <&cpg CPG_MOD <<
793 <&cpg CPG_MOD <<
794 clock-names = "pllclk" <<
795 resets = <&cpg R9A07G0 <<
796 <&cpg R9A07G0 <<
797 <&cpg R9A07G0 <<
798 reset-names = "rst", " <<
799 power-domains = <&cpg> <<
800 status = "disabled"; <<
801 <<
802 ports { <<
803 #address-cells <<
804 #size-cells = <<
805 <<
806 port@0 { <<
807 reg = <<
808 dsi0_i <<
809 <<
810 }; <<
811 }; <<
812 <<
813 port@1 { <<
814 reg = <<
815 }; <<
816 }; <<
817 }; <<
818 <<
819 vspd: vsp@10870000 { <<
820 compatible = "renesas, <<
821 "renesas, <<
822 reg = <0 0x10870000 0 <<
823 interrupts = <GIC_SPI <<
824 clocks = <&cpg CPG_MOD <<
825 <&cpg CPG_MOD <<
826 <&cpg CPG_MOD <<
827 clock-names = "aclk", <<
828 power-domains = <&cpg> <<
829 resets = <&cpg R9A07G0 <<
830 renesas,fcp = <&fcpvd> <<
831 }; <<
832 <<
833 fcpvd: fcp@10880000 { <<
834 compatible = "renesas, <<
835 "renesas, <<
836 reg = <0 0x10880000 0 <<
837 clocks = <&cpg CPG_MOD <<
838 <&cpg CPG_MOD <<
839 <&cpg CPG_MOD <<
840 clock-names = "aclk", <<
841 power-domains = <&cpg> <<
842 resets = <&cpg R9A07G0 <<
843 }; <<
844 <<
845 du: display@10890000 { <<
846 compatible = "renesas, <<
847 "renesas, <<
848 reg = <0 0x10890000 0 <<
849 interrupts = <GIC_SPI <<
850 clocks = <&cpg CPG_MOD <<
851 <&cpg CPG_MOD <<
852 <&cpg CPG_MOD <<
853 clock-names = "aclk", <<
854 power-domains = <&cpg> <<
855 resets = <&cpg R9A07G0 <<
856 renesas,vsps = <&vspd <<
857 status = "disabled"; <<
858 <<
859 ports { <<
860 #address-cells <<
861 #size-cells = <<
862 <<
863 port@0 { <<
864 reg = <<
865 du_out <<
866 <<
867 }; <<
868 }; <<
869 <<
870 port@1 { <<
871 reg = <<
872 }; <<
873 }; <<
874 }; 274 };
875 275
876 cpg: clock-controller@11010000 276 cpg: clock-controller@11010000 {
877 compatible = "renesas, 277 compatible = "renesas,r9a07g054-cpg";
878 reg = <0 0x11010000 0 278 reg = <0 0x11010000 0 0x10000>;
879 clocks = <&extal_clk>; 279 clocks = <&extal_clk>;
880 clock-names = "extal"; 280 clock-names = "extal";
881 #clock-cells = <2>; 281 #clock-cells = <2>;
882 #reset-cells = <1>; 282 #reset-cells = <1>;
883 #power-domain-cells = 283 #power-domain-cells = <0>;
884 }; 284 };
885 285
886 sysc: system-controller@110200 286 sysc: system-controller@11020000 {
887 compatible = "renesas, 287 compatible = "renesas,r9a07g054-sysc";
888 reg = <0 0x11020000 0 288 reg = <0 0x11020000 0 0x10000>;
889 interrupts = <GIC_SPI 289 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
890 <GIC_SPI 290 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
891 <GIC_SPI 291 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
892 <GIC_SPI 292 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
893 interrupt-names = "lpm 293 interrupt-names = "lpm_int", "ca55stbydone_int",
894 "cm3 294 "cm33stbyr_int", "ca55_deny";
895 status = "disabled"; 295 status = "disabled";
896 }; 296 };
897 297
898 pinctrl: pinctrl@11030000 { 298 pinctrl: pinctrl@11030000 {
899 compatible = "renesas, 299 compatible = "renesas,r9a07g054-pinctrl",
900 "renesas, 300 "renesas,r9a07g044-pinctrl";
901 reg = <0 0x11030000 0 301 reg = <0 0x11030000 0 0x10000>;
902 gpio-controller; 302 gpio-controller;
903 #gpio-cells = <2>; 303 #gpio-cells = <2>;
904 #interrupt-cells = <2> <<
905 interrupt-parent = <&i <<
906 interrupt-controller; <<
907 gpio-ranges = <&pinctr 304 gpio-ranges = <&pinctrl 0 0 392>;
908 clocks = <&cpg CPG_MOD 305 clocks = <&cpg CPG_MOD R9A07G054_GPIO_HCLK>;
909 power-domains = <&cpg> 306 power-domains = <&cpg>;
910 resets = <&cpg R9A07G0 307 resets = <&cpg R9A07G054_GPIO_RSTN>,
911 <&cpg R9A07G0 308 <&cpg R9A07G054_GPIO_PORT_RESETN>,
912 <&cpg R9A07G0 309 <&cpg R9A07G054_GPIO_SPARE_RESETN>;
913 }; 310 };
914 311
915 irqc: interrupt-controller@110 <<
916 compatible = "renesas, <<
917 "renesas, <<
918 #interrupt-cells = <2> <<
919 #address-cells = <0>; <<
920 interrupt-controller; <<
921 reg = <0 0x110a0000 0 <<
922 interrupts = <GIC_SPI <<
923 <GIC_SPI <<
924 <GIC_SPI <<
925 <GIC_SPI <<
926 <GIC_SPI <<
927 <GIC_SPI <<
928 <GIC_SPI <<
929 <GIC_SPI <<
930 <GIC_SPI <<
931 <GIC_SPI <<
932 <GIC_SPI <<
933 <GIC_SPI <<
934 <GIC_SPI <<
935 <GIC_SPI <<
936 <GIC_SPI <<
937 <GIC_SPI <<
938 <GIC_SPI <<
939 <GIC_SPI <<
940 <GIC_SPI <<
941 <GIC_SPI <<
942 <GIC_SPI <<
943 <GIC_SPI <<
944 <GIC_SPI <<
945 <GIC_SPI <<
946 <GIC_SPI <<
947 <GIC_SPI <<
948 <GIC_SPI <<
949 <GIC_SPI <<
950 <GIC_SPI <<
951 <GIC_SPI <<
952 <GIC_SPI <<
953 <GIC_SPI <<
954 <GIC_SPI <<
955 <GIC_SPI <<
956 <GIC_SPI <<
957 <GIC_SPI <<
958 <GIC_SPI <<
959 <GIC_SPI <<
960 <GIC_SPI <<
961 <GIC_SPI <<
962 <GIC_SPI <<
963 <GIC_SPI <<
964 <GIC_SPI <<
965 <GIC_SPI <<
966 <GIC_SPI <<
967 <GIC_SPI <<
968 <GIC_SPI <<
969 <GIC_SPI <<
970 interrupt-names = "nmi <<
971 "irq <<
972 "tin <<
973 "tin <<
974 "tin <<
975 "tin <<
976 "tin <<
977 "tin <<
978 "tin <<
979 "tin <<
980 "bus <<
981 "ec7 <<
982 "ec7 <<
983 clocks = <&cpg CPG_MOD <<
984 <&cpg CPG_MOD <<
985 clock-names = "clk", " <<
986 power-domains = <&cpg> <<
987 resets = <&cpg R9A07G0 <<
988 }; <<
989 <<
990 dmac: dma-controller@11820000 312 dmac: dma-controller@11820000 {
991 compatible = "renesas, 313 compatible = "renesas,r9a07g054-dmac",
992 "renesas, 314 "renesas,rz-dmac";
993 reg = <0 0x11820000 0 315 reg = <0 0x11820000 0 0x10000>,
994 <0 0x11830000 0 316 <0 0x11830000 0 0x10000>;
995 interrupts = <GIC_SPI 317 interrupts = <GIC_SPI 141 IRQ_TYPE_EDGE_RISING>,
996 <GIC_SPI 318 <GIC_SPI 125 IRQ_TYPE_EDGE_RISING>,
997 <GIC_SPI 319 <GIC_SPI 126 IRQ_TYPE_EDGE_RISING>,
998 <GIC_SPI 320 <GIC_SPI 127 IRQ_TYPE_EDGE_RISING>,
999 <GIC_SPI 321 <GIC_SPI 128 IRQ_TYPE_EDGE_RISING>,
1000 <GIC_SPI 322 <GIC_SPI 129 IRQ_TYPE_EDGE_RISING>,
1001 <GIC_SPI 323 <GIC_SPI 130 IRQ_TYPE_EDGE_RISING>,
1002 <GIC_SPI 324 <GIC_SPI 131 IRQ_TYPE_EDGE_RISING>,
1003 <GIC_SPI 325 <GIC_SPI 132 IRQ_TYPE_EDGE_RISING>,
1004 <GIC_SPI 326 <GIC_SPI 133 IRQ_TYPE_EDGE_RISING>,
1005 <GIC_SPI 327 <GIC_SPI 134 IRQ_TYPE_EDGE_RISING>,
1006 <GIC_SPI 328 <GIC_SPI 135 IRQ_TYPE_EDGE_RISING>,
1007 <GIC_SPI 329 <GIC_SPI 136 IRQ_TYPE_EDGE_RISING>,
1008 <GIC_SPI 330 <GIC_SPI 137 IRQ_TYPE_EDGE_RISING>,
1009 <GIC_SPI 331 <GIC_SPI 138 IRQ_TYPE_EDGE_RISING>,
1010 <GIC_SPI 332 <GIC_SPI 139 IRQ_TYPE_EDGE_RISING>,
1011 <GIC_SPI 333 <GIC_SPI 140 IRQ_TYPE_EDGE_RISING>;
1012 interrupt-names = "er 334 interrupt-names = "error",
1013 "ch 335 "ch0", "ch1", "ch2", "ch3",
1014 "ch 336 "ch4", "ch5", "ch6", "ch7",
1015 "ch 337 "ch8", "ch9", "ch10", "ch11",
1016 "ch 338 "ch12", "ch13", "ch14", "ch15";
1017 clocks = <&cpg CPG_MO 339 clocks = <&cpg CPG_MOD R9A07G054_DMAC_ACLK>,
1018 <&cpg CPG_MO 340 <&cpg CPG_MOD R9A07G054_DMAC_PCLK>;
1019 clock-names = "main", <<
1020 power-domains = <&cpg 341 power-domains = <&cpg>;
1021 resets = <&cpg R9A07G 342 resets = <&cpg R9A07G054_DMAC_ARESETN>,
1022 <&cpg R9A07G 343 <&cpg R9A07G054_DMAC_RST_ASYNC>;
1023 reset-names = "arst", <<
1024 #dma-cells = <1>; 344 #dma-cells = <1>;
1025 dma-channels = <16>; 345 dma-channels = <16>;
1026 }; 346 };
1027 347
1028 gpu: gpu@11840000 { 348 gpu: gpu@11840000 {
1029 compatible = "renesas <<
1030 "arm,mal <<
1031 reg = <0x0 0x11840000 349 reg = <0x0 0x11840000 0x0 0x10000>;
1032 interrupts = <GIC_SPI !! 350 /* place holder */
1033 <GIC_SPI <<
1034 <GIC_SPI <<
1035 <GIC_SPI <<
1036 interrupt-names = "jo <<
1037 clocks = <&cpg CPG_MO <<
1038 <&cpg CPG_MO <<
1039 <&cpg CPG_MO <<
1040 clock-names = "gpu", <<
1041 power-domains = <&cpg <<
1042 resets = <&cpg R9A07G <<
1043 <&cpg R9A07G <<
1044 <&cpg R9A07G <<
1045 reset-names = "rst", <<
1046 operating-points-v2 = <<
1047 }; 351 };
1048 352
1049 gic: interrupt-controller@119 353 gic: interrupt-controller@11900000 {
1050 compatible = "arm,gic 354 compatible = "arm,gic-v3";
1051 #interrupt-cells = <3 355 #interrupt-cells = <3>;
1052 #address-cells = <0>; 356 #address-cells = <0>;
1053 interrupt-controller; 357 interrupt-controller;
1054 reg = <0x0 0x11900000 !! 358 reg = <0x0 0x11900000 0 0x40000>,
1055 <0x0 0x11940000 !! 359 <0x0 0x11940000 0 0x60000>;
1056 interrupts = <GIC_PPI 360 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
1057 }; 361 };
1058 362
1059 sdhi0: mmc@11c00000 { !! 363 sdhi0: mmc@11c00000 {
1060 compatible = "renesas <<
1061 "renesas <<
1062 reg = <0x0 0x11c00000 364 reg = <0x0 0x11c00000 0 0x10000>;
1063 interrupts = <GIC_SPI !! 365 /* place holder */
1064 <GIC_SPI <<
1065 clocks = <&cpg CPG_MO <<
1066 <&cpg CPG_MO <<
1067 <&cpg CPG_MO <<
1068 <&cpg CPG_MO <<
1069 clock-names = "core", <<
1070 resets = <&cpg R9A07G <<
1071 power-domains = <&cpg <<
1072 status = "disabled"; <<
1073 }; 366 };
1074 367
1075 sdhi1: mmc@11c10000 { 368 sdhi1: mmc@11c10000 {
1076 compatible = "renesas <<
1077 "renesas <<
1078 reg = <0x0 0x11c10000 369 reg = <0x0 0x11c10000 0 0x10000>;
1079 interrupts = <GIC_SPI !! 370 /* place holder */
1080 <GIC_SPI <<
1081 clocks = <&cpg CPG_MO <<
1082 <&cpg CPG_MO <<
1083 <&cpg CPG_MO <<
1084 <&cpg CPG_MO <<
1085 clock-names = "core", <<
1086 resets = <&cpg R9A07G <<
1087 power-domains = <&cpg <<
1088 status = "disabled"; <<
1089 }; 371 };
1090 372
1091 eth0: ethernet@11c20000 { 373 eth0: ethernet@11c20000 {
1092 compatible = "renesas 374 compatible = "renesas,r9a07g054-gbeth",
1093 "renesas 375 "renesas,rzg2l-gbeth";
1094 reg = <0 0x11c20000 0 376 reg = <0 0x11c20000 0 0x10000>;
1095 interrupts = <GIC_SPI 377 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
1096 <GIC_SPI 378 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
1097 <GIC_SPI 379 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
1098 interrupt-names = "mu 380 interrupt-names = "mux", "fil", "arp_ns";
1099 phy-mode = "rgmii"; 381 phy-mode = "rgmii";
1100 clocks = <&cpg CPG_MO 382 clocks = <&cpg CPG_MOD R9A07G054_ETH0_CLK_AXI>,
1101 <&cpg CPG_MO 383 <&cpg CPG_MOD R9A07G054_ETH0_CLK_CHI>,
1102 <&cpg CPG_CO 384 <&cpg CPG_CORE R9A07G054_CLK_HP>;
1103 clock-names = "axi", 385 clock-names = "axi", "chi", "refclk";
1104 resets = <&cpg R9A07G 386 resets = <&cpg R9A07G054_ETH0_RST_HW_N>;
1105 power-domains = <&cpg 387 power-domains = <&cpg>;
1106 #address-cells = <1>; 388 #address-cells = <1>;
1107 #size-cells = <0>; 389 #size-cells = <0>;
1108 status = "disabled"; 390 status = "disabled";
1109 }; 391 };
1110 392
1111 eth1: ethernet@11c30000 { 393 eth1: ethernet@11c30000 {
1112 compatible = "renesas 394 compatible = "renesas,r9a07g054-gbeth",
1113 "renesas 395 "renesas,rzg2l-gbeth";
1114 reg = <0 0x11c30000 0 396 reg = <0 0x11c30000 0 0x10000>;
1115 interrupts = <GIC_SPI 397 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
1116 <GIC_SPI 398 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
1117 <GIC_SPI 399 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
1118 interrupt-names = "mu 400 interrupt-names = "mux", "fil", "arp_ns";
1119 phy-mode = "rgmii"; 401 phy-mode = "rgmii";
1120 clocks = <&cpg CPG_MO 402 clocks = <&cpg CPG_MOD R9A07G054_ETH1_CLK_AXI>,
1121 <&cpg CPG_MO 403 <&cpg CPG_MOD R9A07G054_ETH1_CLK_CHI>,
1122 <&cpg CPG_CO 404 <&cpg CPG_CORE R9A07G054_CLK_HP>;
1123 clock-names = "axi", 405 clock-names = "axi", "chi", "refclk";
1124 resets = <&cpg R9A07G 406 resets = <&cpg R9A07G054_ETH1_RST_HW_N>;
1125 power-domains = <&cpg 407 power-domains = <&cpg>;
1126 #address-cells = <1>; 408 #address-cells = <1>;
1127 #size-cells = <0>; 409 #size-cells = <0>;
1128 status = "disabled"; 410 status = "disabled";
1129 }; 411 };
1130 412
1131 phyrst: usbphy-ctrl@11c40000 413 phyrst: usbphy-ctrl@11c40000 {
1132 compatible = "renesas <<
1133 "renesas <<
1134 reg = <0 0x11c40000 0 414 reg = <0 0x11c40000 0 0x10000>;
1135 clocks = <&cpg CPG_MO !! 415 /* place holder */
1136 resets = <&cpg R9A07G <<
1137 power-domains = <&cpg <<
1138 #reset-cells = <1>; <<
1139 status = "disabled"; <<
1140 <<
1141 usb0_vbus_otg: regula <<
1142 regulator-nam <<
1143 }; <<
1144 }; 416 };
1145 417
1146 ohci0: usb@11c50000 { 418 ohci0: usb@11c50000 {
1147 compatible = "generic <<
1148 reg = <0 0x11c50000 0 419 reg = <0 0x11c50000 0 0x100>;
1149 interrupts = <GIC_SPI !! 420 /* place holder */
1150 clocks = <&cpg CPG_MO <<
1151 <&cpg CPG_MO <<
1152 resets = <&phyrst 0>, <<
1153 <&cpg R9A07G <<
1154 phys = <&usb2_phy0 1> <<
1155 phy-names = "usb"; <<
1156 power-domains = <&cpg <<
1157 status = "disabled"; <<
1158 }; 421 };
1159 422
1160 ohci1: usb@11c70000 { 423 ohci1: usb@11c70000 {
1161 compatible = "generic <<
1162 reg = <0 0x11c70000 0 424 reg = <0 0x11c70000 0 0x100>;
1163 interrupts = <GIC_SPI !! 425 /* place holder */
1164 clocks = <&cpg CPG_MO <<
1165 <&cpg CPG_MO <<
1166 resets = <&phyrst 1>, <<
1167 <&cpg R9A07G <<
1168 phys = <&usb2_phy1 1> <<
1169 phy-names = "usb"; <<
1170 power-domains = <&cpg <<
1171 status = "disabled"; <<
1172 }; 426 };
1173 427
1174 ehci0: usb@11c50100 { 428 ehci0: usb@11c50100 {
1175 compatible = "generic <<
1176 reg = <0 0x11c50100 0 429 reg = <0 0x11c50100 0 0x100>;
1177 interrupts = <GIC_SPI !! 430 /* place holder */
1178 clocks = <&cpg CPG_MO <<
1179 <&cpg CPG_MO <<
1180 resets = <&phyrst 0>, <<
1181 <&cpg R9A07G <<
1182 phys = <&usb2_phy0 2> <<
1183 phy-names = "usb"; <<
1184 companion = <&ohci0>; <<
1185 power-domains = <&cpg <<
1186 status = "disabled"; <<
1187 }; 431 };
1188 432
1189 ehci1: usb@11c70100 { 433 ehci1: usb@11c70100 {
1190 compatible = "generic <<
1191 reg = <0 0x11c70100 0 434 reg = <0 0x11c70100 0 0x100>;
1192 interrupts = <GIC_SPI !! 435 /* place holder */
1193 clocks = <&cpg CPG_MO <<
1194 <&cpg CPG_MO <<
1195 resets = <&phyrst 1>, <<
1196 <&cpg R9A07G <<
1197 phys = <&usb2_phy1 2> <<
1198 phy-names = "usb"; <<
1199 companion = <&ohci1>; <<
1200 power-domains = <&cpg <<
1201 status = "disabled"; <<
1202 }; 436 };
1203 437
1204 usb2_phy0: usb-phy@11c50200 { 438 usb2_phy0: usb-phy@11c50200 {
1205 compatible = "renesas <<
1206 "renesas <<
1207 reg = <0 0x11c50200 0 439 reg = <0 0x11c50200 0 0x700>;
1208 interrupts = <GIC_SPI !! 440 /* place holder */
1209 clocks = <&cpg CPG_MO <<
1210 <&cpg CPG_MO <<
1211 resets = <&phyrst 0>; <<
1212 #phy-cells = <1>; <<
1213 power-domains = <&cpg <<
1214 status = "disabled"; <<
1215 }; 441 };
1216 442
1217 usb2_phy1: usb-phy@11c70200 { 443 usb2_phy1: usb-phy@11c70200 {
1218 compatible = "renesas <<
1219 "renesas <<
1220 reg = <0 0x11c70200 0 444 reg = <0 0x11c70200 0 0x700>;
1221 interrupts = <GIC_SPI !! 445 /* place holder */
1222 clocks = <&cpg CPG_MO <<
1223 <&cpg CPG_MO <<
1224 resets = <&phyrst 1>; <<
1225 #phy-cells = <1>; <<
1226 power-domains = <&cpg <<
1227 status = "disabled"; <<
1228 }; 446 };
1229 447
1230 hsusb: usb@11c60000 { 448 hsusb: usb@11c60000 {
1231 compatible = "renesas <<
1232 "renesas <<
1233 reg = <0 0x11c60000 0 449 reg = <0 0x11c60000 0 0x10000>;
1234 interrupts = <GIC_SPI !! 450 /* place holder */
1235 <GIC_SPI <<
1236 <GIC_SPI <<
1237 <GIC_SPI <<
1238 clocks = <&cpg CPG_MO <<
1239 <&cpg CPG_MO <<
1240 resets = <&phyrst 0>, <<
1241 <&cpg R9A07G <<
1242 renesas,buswait = <7> <<
1243 phys = <&usb2_phy0 3> <<
1244 phy-names = "usb"; <<
1245 power-domains = <&cpg <<
1246 status = "disabled"; <<
1247 }; 451 };
1248 452
1249 wdt0: watchdog@12800800 { 453 wdt0: watchdog@12800800 {
1250 compatible = "renesas <<
1251 "renesas <<
1252 reg = <0 0x12800800 0 454 reg = <0 0x12800800 0 0x400>;
1253 clocks = <&cpg CPG_MO !! 455 /* place holder */
1254 <&cpg CPG_MO <<
1255 clock-names = "pclk", <<
1256 interrupts = <GIC_SPI <<
1257 <GIC_SPI <<
1258 interrupt-names = "wd <<
1259 resets = <&cpg R9A07G <<
1260 power-domains = <&cpg <<
1261 status = "disabled"; <<
1262 }; 456 };
1263 457
1264 wdt1: watchdog@12800c00 { 458 wdt1: watchdog@12800c00 {
1265 compatible = "renesas <<
1266 "renesas <<
1267 reg = <0 0x12800C00 0 459 reg = <0 0x12800C00 0 0x400>;
1268 clocks = <&cpg CPG_MO !! 460 /* place holder */
1269 <&cpg CPG_MO !! 461 };
1270 clock-names = "pclk", !! 462
1271 interrupts = <GIC_SPI !! 463 wdt2: watchdog@12800400 {
1272 <GIC_SPI !! 464 reg = <0 0x12800400 0 0x400>;
1273 interrupt-names = "wd !! 465 /* place holder */
1274 resets = <&cpg R9A07G <<
1275 power-domains = <&cpg <<
1276 status = "disabled"; <<
1277 }; 466 };
1278 467
1279 ostm0: timer@12801000 { 468 ostm0: timer@12801000 {
1280 compatible = "renesas <<
1281 "renesas <<
1282 reg = <0x0 0x12801000 469 reg = <0x0 0x12801000 0x0 0x400>;
1283 interrupts = <GIC_SPI !! 470 /* place holder */
1284 clocks = <&cpg CPG_MO <<
1285 resets = <&cpg R9A07G <<
1286 power-domains = <&cpg <<
1287 status = "disabled"; <<
1288 }; 471 };
1289 472
1290 ostm1: timer@12801400 { 473 ostm1: timer@12801400 {
1291 compatible = "renesas <<
1292 "renesas <<
1293 reg = <0x0 0x12801400 474 reg = <0x0 0x12801400 0x0 0x400>;
1294 interrupts = <GIC_SPI !! 475 /* place holder */
1295 clocks = <&cpg CPG_MO <<
1296 resets = <&cpg R9A07G <<
1297 power-domains = <&cpg <<
1298 status = "disabled"; <<
1299 }; 476 };
1300 477
1301 ostm2: timer@12801800 { 478 ostm2: timer@12801800 {
1302 compatible = "renesas <<
1303 "renesas <<
1304 reg = <0x0 0x12801800 479 reg = <0x0 0x12801800 0x0 0x400>;
1305 interrupts = <GIC_SPI !! 480 /* place holder */
1306 clocks = <&cpg CPG_MO <<
1307 resets = <&cpg R9A07G <<
1308 power-domains = <&cpg <<
1309 status = "disabled"; <<
1310 }; <<
1311 }; <<
1312 <<
1313 thermal-zones { <<
1314 cpu-thermal { <<
1315 polling-delay-passive <<
1316 polling-delay = <1000 <<
1317 thermal-sensors = <&t <<
1318 sustainable-power = < <<
1319 <<
1320 cooling-maps { <<
1321 map0 { <<
1322 trip <<
1323 cooli <<
1324 contr <<
1325 }; <<
1326 }; <<
1327 <<
1328 trips { <<
1329 sensor_crit: <<
1330 tempe <<
1331 hyste <<
1332 type <<
1333 }; <<
1334 <<
1335 target: trip- <<
1336 tempe <<
1337 hyste <<
1338 type <<
1339 }; <<
1340 }; <<
1341 }; 481 };
1342 }; 482 };
1343 483
1344 timer { 484 timer {
1345 compatible = "arm,armv8-timer 485 compatible = "arm,armv8-timer";
1346 interrupts-extended = <&gic G !! 486 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
1347 <&gic G !! 487 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
1348 <&gic G !! 488 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
1349 <&gic G !! 489 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
1350 <&gic G <<
1351 interrupt-names = "sec-phys", <<
1352 "hyp-virt"; <<
1353 }; 490 };
1354 }; 491 };
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