1 // SPDX-License-Identifier: (GPL-2.0-only OR B 1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 /* 2 /*
3 * Device Tree Source for the RZ/V2L SoC 3 * Device Tree Source for the RZ/V2L SoC
4 * 4 *
5 * Copyright (C) 2021 Renesas Electronics Corp 5 * Copyright (C) 2021 Renesas Electronics Corp.
6 */ 6 */
7 7
8 #include <dt-bindings/interrupt-controller/arm 8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/clock/r9a07g054-cpg.h> 9 #include <dt-bindings/clock/r9a07g054-cpg.h>
10 10
11 / { 11 / {
12 compatible = "renesas,r9a07g054"; 12 compatible = "renesas,r9a07g054";
13 #address-cells = <2>; 13 #address-cells = <2>;
14 #size-cells = <2>; 14 #size-cells = <2>;
15 15
16 audio_clk1: audio1-clk { 16 audio_clk1: audio1-clk {
17 compatible = "fixed-clock"; 17 compatible = "fixed-clock";
18 #clock-cells = <0>; 18 #clock-cells = <0>;
19 /* This value must be overridd 19 /* This value must be overridden by boards that provide it */
20 clock-frequency = <0>; 20 clock-frequency = <0>;
21 }; 21 };
22 22
23 audio_clk2: audio2-clk { 23 audio_clk2: audio2-clk {
24 compatible = "fixed-clock"; 24 compatible = "fixed-clock";
25 #clock-cells = <0>; 25 #clock-cells = <0>;
26 /* This value must be overridd 26 /* This value must be overridden by boards that provide it */
27 clock-frequency = <0>; 27 clock-frequency = <0>;
28 }; 28 };
29 29
30 /* External CAN clock - to be overridd 30 /* External CAN clock - to be overridden by boards that provide it */
31 can_clk: can-clk { 31 can_clk: can-clk {
32 compatible = "fixed-clock"; 32 compatible = "fixed-clock";
33 #clock-cells = <0>; 33 #clock-cells = <0>;
34 clock-frequency = <0>; 34 clock-frequency = <0>;
35 }; 35 };
36 36
37 /* clock can be either from exclk or c 37 /* clock can be either from exclk or crystal oscillator (XIN/XOUT) */
38 extal_clk: extal-clk { 38 extal_clk: extal-clk {
39 compatible = "fixed-clock"; 39 compatible = "fixed-clock";
40 #clock-cells = <0>; 40 #clock-cells = <0>;
41 /* This value must be overridd 41 /* This value must be overridden by the board */
42 clock-frequency = <0>; 42 clock-frequency = <0>;
43 }; 43 };
44 44
45 cluster0_opp: opp-table-0 { 45 cluster0_opp: opp-table-0 {
46 compatible = "operating-points 46 compatible = "operating-points-v2";
47 opp-shared; 47 opp-shared;
48 48
49 opp-150000000 { 49 opp-150000000 {
50 opp-hz = /bits/ 64 <15 50 opp-hz = /bits/ 64 <150000000>;
51 opp-microvolt = <11000 51 opp-microvolt = <1100000>;
52 clock-latency-ns = <30 52 clock-latency-ns = <300000>;
53 }; 53 };
54 opp-300000000 { 54 opp-300000000 {
55 opp-hz = /bits/ 64 <30 55 opp-hz = /bits/ 64 <300000000>;
56 opp-microvolt = <11000 56 opp-microvolt = <1100000>;
57 clock-latency-ns = <30 57 clock-latency-ns = <300000>;
58 }; 58 };
59 opp-600000000 { 59 opp-600000000 {
60 opp-hz = /bits/ 64 <60 60 opp-hz = /bits/ 64 <600000000>;
61 opp-microvolt = <11000 61 opp-microvolt = <1100000>;
62 clock-latency-ns = <30 62 clock-latency-ns = <300000>;
63 }; 63 };
64 opp-1200000000 { 64 opp-1200000000 {
65 opp-hz = /bits/ 64 <12 65 opp-hz = /bits/ 64 <1200000000>;
66 opp-microvolt = <11000 66 opp-microvolt = <1100000>;
67 clock-latency-ns = <30 67 clock-latency-ns = <300000>;
68 opp-suspend; 68 opp-suspend;
69 }; 69 };
70 }; 70 };
71 71
72 cpus { 72 cpus {
73 #address-cells = <1>; 73 #address-cells = <1>;
74 #size-cells = <0>; 74 #size-cells = <0>;
75 75
76 cpu-map { 76 cpu-map {
77 cluster0 { 77 cluster0 {
78 core0 { 78 core0 {
79 cpu = 79 cpu = <&cpu0>;
80 }; 80 };
81 core1 { 81 core1 {
82 cpu = 82 cpu = <&cpu1>;
83 }; 83 };
84 }; 84 };
85 }; 85 };
86 86
87 cpu0: cpu@0 { 87 cpu0: cpu@0 {
88 compatible = "arm,cort 88 compatible = "arm,cortex-a55";
89 reg = <0>; 89 reg = <0>;
90 device_type = "cpu"; 90 device_type = "cpu";
91 #cooling-cells = <2>; 91 #cooling-cells = <2>;
92 next-level-cache = <&L 92 next-level-cache = <&L3_CA55>;
93 enable-method = "psci" 93 enable-method = "psci";
94 clocks = <&cpg CPG_COR 94 clocks = <&cpg CPG_CORE R9A07G054_CLK_I>;
95 operating-points-v2 = 95 operating-points-v2 = <&cluster0_opp>;
96 }; 96 };
97 97
98 cpu1: cpu@100 { 98 cpu1: cpu@100 {
99 compatible = "arm,cort 99 compatible = "arm,cortex-a55";
100 reg = <0x100>; 100 reg = <0x100>;
101 device_type = "cpu"; 101 device_type = "cpu";
102 next-level-cache = <&L 102 next-level-cache = <&L3_CA55>;
103 enable-method = "psci" 103 enable-method = "psci";
104 clocks = <&cpg CPG_COR 104 clocks = <&cpg CPG_CORE R9A07G054_CLK_I>;
105 operating-points-v2 = 105 operating-points-v2 = <&cluster0_opp>;
106 }; 106 };
107 107
108 L3_CA55: cache-controller-0 { 108 L3_CA55: cache-controller-0 {
109 compatible = "cache"; 109 compatible = "cache";
110 cache-unified; 110 cache-unified;
111 cache-size = <0x40000> 111 cache-size = <0x40000>;
112 cache-level = <3>; <<
113 }; 112 };
114 }; 113 };
115 114
116 gpu_opp_table: opp-table-1 { 115 gpu_opp_table: opp-table-1 {
117 compatible = "operating-points 116 compatible = "operating-points-v2";
118 117
119 opp-500000000 { 118 opp-500000000 {
120 opp-hz = /bits/ 64 <50 119 opp-hz = /bits/ 64 <500000000>;
121 opp-microvolt = <11000 120 opp-microvolt = <1100000>;
122 }; 121 };
123 122
124 opp-400000000 { 123 opp-400000000 {
125 opp-hz = /bits/ 64 <40 124 opp-hz = /bits/ 64 <400000000>;
126 opp-microvolt = <11000 125 opp-microvolt = <1100000>;
127 }; 126 };
128 127
129 opp-250000000 { 128 opp-250000000 {
130 opp-hz = /bits/ 64 <25 129 opp-hz = /bits/ 64 <250000000>;
131 opp-microvolt = <11000 130 opp-microvolt = <1100000>;
132 }; 131 };
133 132
134 opp-200000000 { 133 opp-200000000 {
135 opp-hz = /bits/ 64 <20 134 opp-hz = /bits/ 64 <200000000>;
136 opp-microvolt = <11000 135 opp-microvolt = <1100000>;
137 }; 136 };
138 137
139 opp-125000000 { 138 opp-125000000 {
140 opp-hz = /bits/ 64 <12 139 opp-hz = /bits/ 64 <125000000>;
141 opp-microvolt = <11000 140 opp-microvolt = <1100000>;
142 }; 141 };
143 142
144 opp-100000000 { 143 opp-100000000 {
145 opp-hz = /bits/ 64 <10 144 opp-hz = /bits/ 64 <100000000>;
146 opp-microvolt = <11000 145 opp-microvolt = <1100000>;
147 }; 146 };
148 147
149 opp-62500000 { 148 opp-62500000 {
150 opp-hz = /bits/ 64 <62 149 opp-hz = /bits/ 64 <62500000>;
151 opp-microvolt = <11000 150 opp-microvolt = <1100000>;
152 }; 151 };
153 152
154 opp-50000000 { 153 opp-50000000 {
155 opp-hz = /bits/ 64 <50 154 opp-hz = /bits/ 64 <50000000>;
156 opp-microvolt = <11000 155 opp-microvolt = <1100000>;
157 }; 156 };
158 }; 157 };
159 158
160 pmu { <<
161 compatible = "arm,cortex-a55-p <<
162 interrupts-extended = <&gic GI <<
163 }; <<
164 <<
165 psci { 159 psci {
166 compatible = "arm,psci-1.0", " 160 compatible = "arm,psci-1.0", "arm,psci-0.2";
167 method = "smc"; 161 method = "smc";
168 }; 162 };
169 163
170 soc: soc { 164 soc: soc {
171 compatible = "simple-bus"; 165 compatible = "simple-bus";
172 interrupt-parent = <&gic>; 166 interrupt-parent = <&gic>;
173 #address-cells = <2>; 167 #address-cells = <2>;
174 #size-cells = <2>; 168 #size-cells = <2>;
175 ranges; 169 ranges;
176 170
177 mtu3: timer@10001200 { <<
178 compatible = "renesas, <<
179 "renesas, <<
180 reg = <0 0x10001200 0 <<
181 interrupts = <GIC_SPI <<
182 <GIC_SPI <<
183 <GIC_SPI <<
184 <GIC_SPI <<
185 <GIC_SPI <<
186 <GIC_SPI <<
187 <GIC_SPI <<
188 <GIC_SPI <<
189 <GIC_SPI <<
190 <GIC_SPI <<
191 <GIC_SPI <<
192 <GIC_SPI <<
193 <GIC_SPI <<
194 <GIC_SPI <<
195 <GIC_SPI <<
196 <GIC_SPI <<
197 <GIC_SPI <<
198 <GIC_SPI <<
199 <GIC_SPI <<
200 <GIC_SPI <<
201 <GIC_SPI <<
202 <GIC_SPI <<
203 <GIC_SPI <<
204 <GIC_SPI <<
205 <GIC_SPI <<
206 <GIC_SPI <<
207 <GIC_SPI <<
208 <GIC_SPI <<
209 <GIC_SPI <<
210 <GIC_SPI <<
211 <GIC_SPI <<
212 <GIC_SPI <<
213 <GIC_SPI <<
214 <GIC_SPI <<
215 <GIC_SPI <<
216 <GIC_SPI <<
217 <GIC_SPI <<
218 <GIC_SPI <<
219 <GIC_SPI <<
220 <GIC_SPI <<
221 <GIC_SPI <<
222 <GIC_SPI <<
223 <GIC_SPI <<
224 <GIC_SPI <<
225 interrupt-names = "tgi <<
226 "tci <<
227 "tgi <<
228 "tgi <<
229 "tgi <<
230 "tci <<
231 "tgi <<
232 "tci <<
233 "tgi <<
234 "tgi <<
235 "tci <<
236 "tgi <<
237 "tci <<
238 "tgi <<
239 "tci <<
240 clocks = <&cpg CPG_MOD <<
241 power-domains = <&cpg> <<
242 resets = <&cpg R9A07G0 <<
243 #pwm-cells = <2>; <<
244 status = "disabled"; <<
245 }; <<
246 <<
247 ssi0: ssi@10049c00 { 171 ssi0: ssi@10049c00 {
248 compatible = "renesas, 172 compatible = "renesas,r9a07g054-ssi",
249 "renesas, 173 "renesas,rz-ssi";
250 reg = <0 0x10049c00 0 174 reg = <0 0x10049c00 0 0x400>;
251 interrupts = <GIC_SPI 175 interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
252 <GIC_SPI 176 <GIC_SPI 327 IRQ_TYPE_EDGE_RISING>,
253 <GIC_SPI !! 177 <GIC_SPI 328 IRQ_TYPE_EDGE_RISING>,
254 interrupt-names = "int !! 178 <GIC_SPI 329 IRQ_TYPE_EDGE_RISING>;
>> 179 interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt";
255 clocks = <&cpg CPG_MOD 180 clocks = <&cpg CPG_MOD R9A07G054_SSI0_PCLK2>,
256 <&cpg CPG_MOD 181 <&cpg CPG_MOD R9A07G054_SSI0_PCLK_SFR>,
257 <&audio_clk1> 182 <&audio_clk1>, <&audio_clk2>;
258 clock-names = "ssi", " 183 clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2";
259 resets = <&cpg R9A07G0 184 resets = <&cpg R9A07G054_SSI0_RST_M2_REG>;
260 dmas = <&dmac 0x2655>, 185 dmas = <&dmac 0x2655>, <&dmac 0x2656>;
261 dma-names = "tx", "rx" 186 dma-names = "tx", "rx";
262 power-domains = <&cpg> 187 power-domains = <&cpg>;
263 #sound-dai-cells = <0> 188 #sound-dai-cells = <0>;
264 status = "disabled"; 189 status = "disabled";
265 }; 190 };
266 191
267 ssi1: ssi@1004a000 { 192 ssi1: ssi@1004a000 {
268 compatible = "renesas, 193 compatible = "renesas,r9a07g054-ssi",
269 "renesas, 194 "renesas,rz-ssi";
270 reg = <0 0x1004a000 0 195 reg = <0 0x1004a000 0 0x400>;
271 interrupts = <GIC_SPI 196 interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
272 <GIC_SPI 197 <GIC_SPI 331 IRQ_TYPE_EDGE_RISING>,
273 <GIC_SPI !! 198 <GIC_SPI 332 IRQ_TYPE_EDGE_RISING>,
274 interrupt-names = "int !! 199 <GIC_SPI 333 IRQ_TYPE_EDGE_RISING>;
>> 200 interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt";
275 clocks = <&cpg CPG_MOD 201 clocks = <&cpg CPG_MOD R9A07G054_SSI1_PCLK2>,
276 <&cpg CPG_MOD 202 <&cpg CPG_MOD R9A07G054_SSI1_PCLK_SFR>,
277 <&audio_clk1> 203 <&audio_clk1>, <&audio_clk2>;
278 clock-names = "ssi", " 204 clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2";
279 resets = <&cpg R9A07G0 205 resets = <&cpg R9A07G054_SSI1_RST_M2_REG>;
280 dmas = <&dmac 0x2659>, 206 dmas = <&dmac 0x2659>, <&dmac 0x265a>;
281 dma-names = "tx", "rx" 207 dma-names = "tx", "rx";
282 power-domains = <&cpg> 208 power-domains = <&cpg>;
283 #sound-dai-cells = <0> 209 #sound-dai-cells = <0>;
284 status = "disabled"; 210 status = "disabled";
285 }; 211 };
286 212
287 ssi2: ssi@1004a400 { 213 ssi2: ssi@1004a400 {
288 compatible = "renesas, 214 compatible = "renesas,r9a07g054-ssi",
289 "renesas, 215 "renesas,rz-ssi";
290 reg = <0 0x1004a400 0 216 reg = <0 0x1004a400 0 0x400>;
291 interrupts = <GIC_SPI 217 interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
>> 218 <GIC_SPI 335 IRQ_TYPE_EDGE_RISING>,
>> 219 <GIC_SPI 336 IRQ_TYPE_EDGE_RISING>,
292 <GIC_SPI 220 <GIC_SPI 337 IRQ_TYPE_EDGE_RISING>;
293 interrupt-names = "int !! 221 interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt";
294 clocks = <&cpg CPG_MOD 222 clocks = <&cpg CPG_MOD R9A07G054_SSI2_PCLK2>,
295 <&cpg CPG_MOD 223 <&cpg CPG_MOD R9A07G054_SSI2_PCLK_SFR>,
296 <&audio_clk1> 224 <&audio_clk1>, <&audio_clk2>;
297 clock-names = "ssi", " 225 clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2";
298 resets = <&cpg R9A07G0 226 resets = <&cpg R9A07G054_SSI2_RST_M2_REG>;
299 dmas = <&dmac 0x265f>; 227 dmas = <&dmac 0x265f>;
300 dma-names = "rt"; 228 dma-names = "rt";
301 power-domains = <&cpg> 229 power-domains = <&cpg>;
302 #sound-dai-cells = <0> 230 #sound-dai-cells = <0>;
303 status = "disabled"; 231 status = "disabled";
304 }; 232 };
305 233
306 ssi3: ssi@1004a800 { 234 ssi3: ssi@1004a800 {
307 compatible = "renesas, 235 compatible = "renesas,r9a07g054-ssi",
308 "renesas, 236 "renesas,rz-ssi";
309 reg = <0 0x1004a800 0 237 reg = <0 0x1004a800 0 0x400>;
310 interrupts = <GIC_SPI 238 interrupts = <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
311 <GIC_SPI 239 <GIC_SPI 339 IRQ_TYPE_EDGE_RISING>,
312 <GIC_SPI !! 240 <GIC_SPI 340 IRQ_TYPE_EDGE_RISING>,
313 interrupt-names = "int !! 241 <GIC_SPI 341 IRQ_TYPE_EDGE_RISING>;
>> 242 interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt";
314 clocks = <&cpg CPG_MOD 243 clocks = <&cpg CPG_MOD R9A07G054_SSI3_PCLK2>,
315 <&cpg CPG_MOD 244 <&cpg CPG_MOD R9A07G054_SSI3_PCLK_SFR>,
316 <&audio_clk1> 245 <&audio_clk1>, <&audio_clk2>;
317 clock-names = "ssi", " 246 clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2";
318 resets = <&cpg R9A07G0 247 resets = <&cpg R9A07G054_SSI3_RST_M2_REG>;
319 dmas = <&dmac 0x2661>, 248 dmas = <&dmac 0x2661>, <&dmac 0x2662>;
320 dma-names = "tx", "rx" 249 dma-names = "tx", "rx";
321 power-domains = <&cpg> 250 power-domains = <&cpg>;
322 #sound-dai-cells = <0> 251 #sound-dai-cells = <0>;
323 status = "disabled"; 252 status = "disabled";
324 }; 253 };
325 254
326 spi0: spi@1004ac00 { 255 spi0: spi@1004ac00 {
327 compatible = "renesas, 256 compatible = "renesas,r9a07g054-rspi", "renesas,rspi-rz";
328 reg = <0 0x1004ac00 0 257 reg = <0 0x1004ac00 0 0x400>;
329 interrupts = <GIC_SPI 258 interrupts = <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>,
330 <GIC_SPI 259 <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>,
331 <GIC_SPI 260 <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>;
332 interrupt-names = "err 261 interrupt-names = "error", "rx", "tx";
333 clocks = <&cpg CPG_MOD 262 clocks = <&cpg CPG_MOD R9A07G054_RSPI0_CLKB>;
334 resets = <&cpg R9A07G0 263 resets = <&cpg R9A07G054_RSPI0_RST>;
335 dmas = <&dmac 0x2e95>, <<
336 dma-names = "tx", "rx" <<
337 power-domains = <&cpg> 264 power-domains = <&cpg>;
338 num-cs = <1>; 265 num-cs = <1>;
339 #address-cells = <1>; 266 #address-cells = <1>;
340 #size-cells = <0>; 267 #size-cells = <0>;
341 status = "disabled"; 268 status = "disabled";
342 }; 269 };
343 270
344 spi1: spi@1004b000 { 271 spi1: spi@1004b000 {
345 compatible = "renesas, 272 compatible = "renesas,r9a07g054-rspi", "renesas,rspi-rz";
346 reg = <0 0x1004b000 0 273 reg = <0 0x1004b000 0 0x400>;
347 interrupts = <GIC_SPI 274 interrupts = <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
348 <GIC_SPI 275 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
349 <GIC_SPI 276 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>;
350 interrupt-names = "err 277 interrupt-names = "error", "rx", "tx";
351 clocks = <&cpg CPG_MOD 278 clocks = <&cpg CPG_MOD R9A07G054_RSPI1_CLKB>;
352 resets = <&cpg R9A07G0 279 resets = <&cpg R9A07G054_RSPI1_RST>;
353 dmas = <&dmac 0x2e99>, <<
354 dma-names = "tx", "rx" <<
355 power-domains = <&cpg> 280 power-domains = <&cpg>;
356 num-cs = <1>; 281 num-cs = <1>;
357 #address-cells = <1>; 282 #address-cells = <1>;
358 #size-cells = <0>; 283 #size-cells = <0>;
359 status = "disabled"; 284 status = "disabled";
360 }; 285 };
361 286
362 spi2: spi@1004b400 { 287 spi2: spi@1004b400 {
363 compatible = "renesas, 288 compatible = "renesas,r9a07g054-rspi", "renesas,rspi-rz";
364 reg = <0 0x1004b400 0 289 reg = <0 0x1004b400 0 0x400>;
365 interrupts = <GIC_SPI 290 interrupts = <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
366 <GIC_SPI 291 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
367 <GIC_SPI 292 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>;
368 interrupt-names = "err 293 interrupt-names = "error", "rx", "tx";
369 clocks = <&cpg CPG_MOD 294 clocks = <&cpg CPG_MOD R9A07G054_RSPI2_CLKB>;
370 resets = <&cpg R9A07G0 295 resets = <&cpg R9A07G054_RSPI2_RST>;
371 dmas = <&dmac 0x2e9d>, <<
372 dma-names = "tx", "rx" <<
373 power-domains = <&cpg> 296 power-domains = <&cpg>;
374 num-cs = <1>; 297 num-cs = <1>;
375 #address-cells = <1>; 298 #address-cells = <1>;
376 #size-cells = <0>; 299 #size-cells = <0>;
377 status = "disabled"; 300 status = "disabled";
378 }; 301 };
379 302
380 scif0: serial@1004b800 { 303 scif0: serial@1004b800 {
381 compatible = "renesas, 304 compatible = "renesas,scif-r9a07g054",
382 "renesas, 305 "renesas,scif-r9a07g044";
383 reg = <0 0x1004b800 0 306 reg = <0 0x1004b800 0 0x400>;
384 interrupts = <GIC_SPI 307 interrupts = <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>,
385 <GIC_SPI 308 <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>,
386 <GIC_SPI 309 <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>,
387 <GIC_SPI 310 <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>,
388 <GIC_SPI 311 <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>,
389 <GIC_SPI 312 <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>;
390 interrupt-names = "eri 313 interrupt-names = "eri", "rxi", "txi",
391 "bri 314 "bri", "dri", "tei";
392 clocks = <&cpg CPG_MOD 315 clocks = <&cpg CPG_MOD R9A07G054_SCIF0_CLK_PCK>;
393 clock-names = "fck"; 316 clock-names = "fck";
394 power-domains = <&cpg> 317 power-domains = <&cpg>;
395 resets = <&cpg R9A07G0 318 resets = <&cpg R9A07G054_SCIF0_RST_SYSTEM_N>;
396 status = "disabled"; 319 status = "disabled";
397 }; 320 };
398 321
399 scif1: serial@1004bc00 { 322 scif1: serial@1004bc00 {
400 compatible = "renesas, 323 compatible = "renesas,scif-r9a07g054",
401 "renesas, 324 "renesas,scif-r9a07g044";
402 reg = <0 0x1004bc00 0 325 reg = <0 0x1004bc00 0 0x400>;
403 interrupts = <GIC_SPI 326 interrupts = <GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>,
404 <GIC_SPI 327 <GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>,
405 <GIC_SPI 328 <GIC_SPI 388 IRQ_TYPE_LEVEL_HIGH>,
406 <GIC_SPI 329 <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>,
407 <GIC_SPI 330 <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>,
408 <GIC_SPI 331 <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>;
409 interrupt-names = "eri 332 interrupt-names = "eri", "rxi", "txi",
410 "bri 333 "bri", "dri", "tei";
411 clocks = <&cpg CPG_MOD 334 clocks = <&cpg CPG_MOD R9A07G054_SCIF1_CLK_PCK>;
412 clock-names = "fck"; 335 clock-names = "fck";
413 power-domains = <&cpg> 336 power-domains = <&cpg>;
414 resets = <&cpg R9A07G0 337 resets = <&cpg R9A07G054_SCIF1_RST_SYSTEM_N>;
415 status = "disabled"; 338 status = "disabled";
416 }; 339 };
417 340
418 scif2: serial@1004c000 { 341 scif2: serial@1004c000 {
419 compatible = "renesas, 342 compatible = "renesas,scif-r9a07g054",
420 "renesas, 343 "renesas,scif-r9a07g044";
421 reg = <0 0x1004c000 0 344 reg = <0 0x1004c000 0 0x400>;
422 interrupts = <GIC_SPI 345 interrupts = <GIC_SPI 390 IRQ_TYPE_LEVEL_HIGH>,
423 <GIC_SPI 346 <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH>,
424 <GIC_SPI 347 <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>,
425 <GIC_SPI 348 <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH>,
426 <GIC_SPI 349 <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>,
427 <GIC_SPI 350 <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>;
428 interrupt-names = "eri 351 interrupt-names = "eri", "rxi", "txi",
429 "bri 352 "bri", "dri", "tei";
430 clocks = <&cpg CPG_MOD 353 clocks = <&cpg CPG_MOD R9A07G054_SCIF2_CLK_PCK>;
431 clock-names = "fck"; 354 clock-names = "fck";
432 power-domains = <&cpg> 355 power-domains = <&cpg>;
433 resets = <&cpg R9A07G0 356 resets = <&cpg R9A07G054_SCIF2_RST_SYSTEM_N>;
434 status = "disabled"; 357 status = "disabled";
435 }; 358 };
436 359
437 scif3: serial@1004c400 { 360 scif3: serial@1004c400 {
438 compatible = "renesas, 361 compatible = "renesas,scif-r9a07g054",
439 "renesas, 362 "renesas,scif-r9a07g044";
440 reg = <0 0x1004c400 0 363 reg = <0 0x1004c400 0 0x400>;
441 interrupts = <GIC_SPI 364 interrupts = <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
442 <GIC_SPI 365 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
443 <GIC_SPI 366 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
444 <GIC_SPI 367 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
445 <GIC_SPI 368 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
446 <GIC_SPI 369 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>;
447 interrupt-names = "eri 370 interrupt-names = "eri", "rxi", "txi",
448 "bri 371 "bri", "dri", "tei";
449 clocks = <&cpg CPG_MOD 372 clocks = <&cpg CPG_MOD R9A07G054_SCIF3_CLK_PCK>;
450 clock-names = "fck"; 373 clock-names = "fck";
451 power-domains = <&cpg> 374 power-domains = <&cpg>;
452 resets = <&cpg R9A07G0 375 resets = <&cpg R9A07G054_SCIF3_RST_SYSTEM_N>;
453 status = "disabled"; 376 status = "disabled";
454 }; 377 };
455 378
456 scif4: serial@1004c800 { 379 scif4: serial@1004c800 {
457 compatible = "renesas, 380 compatible = "renesas,scif-r9a07g054",
458 "renesas, 381 "renesas,scif-r9a07g044";
459 reg = <0 0x1004c800 0 382 reg = <0 0x1004c800 0 0x400>;
460 interrupts = <GIC_SPI 383 interrupts = <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
461 <GIC_SPI 384 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
462 <GIC_SPI 385 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
463 <GIC_SPI 386 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
464 <GIC_SPI 387 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
465 <GIC_SPI 388 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>;
466 interrupt-names = "eri 389 interrupt-names = "eri", "rxi", "txi",
467 "bri 390 "bri", "dri", "tei";
468 clocks = <&cpg CPG_MOD 391 clocks = <&cpg CPG_MOD R9A07G054_SCIF4_CLK_PCK>;
469 clock-names = "fck"; 392 clock-names = "fck";
470 power-domains = <&cpg> 393 power-domains = <&cpg>;
471 resets = <&cpg R9A07G0 394 resets = <&cpg R9A07G054_SCIF4_RST_SYSTEM_N>;
472 status = "disabled"; 395 status = "disabled";
473 }; 396 };
474 397
475 sci0: serial@1004d000 { 398 sci0: serial@1004d000 {
476 compatible = "renesas, 399 compatible = "renesas,r9a07g054-sci", "renesas,sci";
477 reg = <0 0x1004d000 0 400 reg = <0 0x1004d000 0 0x400>;
478 interrupts = <GIC_SPI 401 interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
479 <GIC_SPI 402 <GIC_SPI 406 IRQ_TYPE_EDGE_RISING>,
480 <GIC_SPI 403 <GIC_SPI 407 IRQ_TYPE_EDGE_RISING>,
481 <GIC_SPI 404 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>;
482 interrupt-names = "eri 405 interrupt-names = "eri", "rxi", "txi", "tei";
483 clocks = <&cpg CPG_MOD 406 clocks = <&cpg CPG_MOD R9A07G054_SCI0_CLKP>;
484 clock-names = "fck"; 407 clock-names = "fck";
485 power-domains = <&cpg> 408 power-domains = <&cpg>;
486 resets = <&cpg R9A07G0 409 resets = <&cpg R9A07G054_SCI0_RST>;
487 status = "disabled"; 410 status = "disabled";
488 }; 411 };
489 412
490 sci1: serial@1004d400 { 413 sci1: serial@1004d400 {
491 compatible = "renesas, 414 compatible = "renesas,r9a07g054-sci", "renesas,sci";
492 reg = <0 0x1004d400 0 415 reg = <0 0x1004d400 0 0x400>;
493 interrupts = <GIC_SPI 416 interrupts = <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
494 <GIC_SPI 417 <GIC_SPI 410 IRQ_TYPE_EDGE_RISING>,
495 <GIC_SPI 418 <GIC_SPI 411 IRQ_TYPE_EDGE_RISING>,
496 <GIC_SPI 419 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>;
497 interrupt-names = "eri 420 interrupt-names = "eri", "rxi", "txi", "tei";
498 clocks = <&cpg CPG_MOD 421 clocks = <&cpg CPG_MOD R9A07G054_SCI1_CLKP>;
499 clock-names = "fck"; 422 clock-names = "fck";
500 power-domains = <&cpg> 423 power-domains = <&cpg>;
501 resets = <&cpg R9A07G0 424 resets = <&cpg R9A07G054_SCI1_RST>;
502 status = "disabled"; 425 status = "disabled";
503 }; 426 };
504 427
505 canfd: can@10050000 { 428 canfd: can@10050000 {
506 compatible = "renesas, 429 compatible = "renesas,r9a07g054-canfd", "renesas,rzg2l-canfd";
507 reg = <0 0x10050000 0 430 reg = <0 0x10050000 0 0x8000>;
508 interrupts = <GIC_SPI 431 interrupts = <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>,
509 <GIC_SPI 432 <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>,
510 <GIC_SPI 433 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
511 <GIC_SPI 434 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
512 <GIC_SPI 435 <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>,
513 <GIC_SPI 436 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
514 <GIC_SPI 437 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
515 <GIC_SPI 438 <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>;
516 interrupt-names = "g_e 439 interrupt-names = "g_err", "g_recc",
517 "ch0 440 "ch0_err", "ch0_rec", "ch0_trx",
518 "ch1 441 "ch1_err", "ch1_rec", "ch1_trx";
519 clocks = <&cpg CPG_MOD 442 clocks = <&cpg CPG_MOD R9A07G054_CANFD_PCLK>,
520 <&cpg CPG_COR 443 <&cpg CPG_CORE R9A07G054_CLK_P0_DIV2>,
521 <&can_clk>; 444 <&can_clk>;
522 clock-names = "fck", " 445 clock-names = "fck", "canfd", "can_clk";
523 assigned-clocks = <&cp 446 assigned-clocks = <&cpg CPG_CORE R9A07G054_CLK_P0_DIV2>;
524 assigned-clock-rates = 447 assigned-clock-rates = <50000000>;
525 resets = <&cpg R9A07G0 448 resets = <&cpg R9A07G054_CANFD_RSTP_N>,
526 <&cpg R9A07G0 449 <&cpg R9A07G054_CANFD_RSTC_N>;
527 reset-names = "rstp_n" 450 reset-names = "rstp_n", "rstc_n";
528 power-domains = <&cpg> 451 power-domains = <&cpg>;
529 status = "disabled"; 452 status = "disabled";
530 453
531 channel0 { 454 channel0 {
532 status = "disa 455 status = "disabled";
533 }; 456 };
534 channel1 { 457 channel1 {
535 status = "disa 458 status = "disabled";
536 }; 459 };
537 }; 460 };
538 461
539 i2c0: i2c@10058000 { 462 i2c0: i2c@10058000 {
540 #address-cells = <1>; 463 #address-cells = <1>;
541 #size-cells = <0>; 464 #size-cells = <0>;
542 compatible = "renesas, 465 compatible = "renesas,riic-r9a07g054", "renesas,riic-rz";
543 reg = <0 0x10058000 0 466 reg = <0 0x10058000 0 0x400>;
544 interrupts = <GIC_SPI 467 interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>,
545 <GIC_SPI 468 <GIC_SPI 348 IRQ_TYPE_EDGE_RISING>,
546 <GIC_SPI 469 <GIC_SPI 349 IRQ_TYPE_EDGE_RISING>,
547 <GIC_SPI 470 <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>,
548 <GIC_SPI 471 <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>,
549 <GIC_SPI 472 <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>,
550 <GIC_SPI 473 <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>,
551 <GIC_SPI 474 <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
552 interrupt-names = "tei 475 interrupt-names = "tei", "ri", "ti", "spi", "sti",
553 "nak 476 "naki", "ali", "tmoi";
554 clocks = <&cpg CPG_MOD 477 clocks = <&cpg CPG_MOD R9A07G054_I2C0_PCLK>;
555 clock-frequency = <100 478 clock-frequency = <100000>;
556 resets = <&cpg R9A07G0 479 resets = <&cpg R9A07G054_I2C0_MRST>;
557 power-domains = <&cpg> 480 power-domains = <&cpg>;
558 status = "disabled"; 481 status = "disabled";
559 }; 482 };
560 483
561 i2c1: i2c@10058400 { 484 i2c1: i2c@10058400 {
562 #address-cells = <1>; 485 #address-cells = <1>;
563 #size-cells = <0>; 486 #size-cells = <0>;
564 compatible = "renesas, 487 compatible = "renesas,riic-r9a07g054", "renesas,riic-rz";
565 reg = <0 0x10058400 0 488 reg = <0 0x10058400 0 0x400>;
566 interrupts = <GIC_SPI 489 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>,
567 <GIC_SPI 490 <GIC_SPI 356 IRQ_TYPE_EDGE_RISING>,
568 <GIC_SPI 491 <GIC_SPI 357 IRQ_TYPE_EDGE_RISING>,
569 <GIC_SPI 492 <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>,
570 <GIC_SPI 493 <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>,
571 <GIC_SPI 494 <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>,
572 <GIC_SPI 495 <GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH>,
573 <GIC_SPI 496 <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>;
574 interrupt-names = "tei 497 interrupt-names = "tei", "ri", "ti", "spi", "sti",
575 "nak 498 "naki", "ali", "tmoi";
576 clocks = <&cpg CPG_MOD 499 clocks = <&cpg CPG_MOD R9A07G054_I2C1_PCLK>;
577 clock-frequency = <100 500 clock-frequency = <100000>;
578 resets = <&cpg R9A07G0 501 resets = <&cpg R9A07G054_I2C1_MRST>;
579 power-domains = <&cpg> 502 power-domains = <&cpg>;
580 status = "disabled"; 503 status = "disabled";
581 }; 504 };
582 505
583 i2c2: i2c@10058800 { 506 i2c2: i2c@10058800 {
584 #address-cells = <1>; 507 #address-cells = <1>;
585 #size-cells = <0>; 508 #size-cells = <0>;
586 compatible = "renesas, 509 compatible = "renesas,riic-r9a07g054", "renesas,riic-rz";
587 reg = <0 0x10058800 0 510 reg = <0 0x10058800 0 0x400>;
588 interrupts = <GIC_SPI 511 interrupts = <GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>,
589 <GIC_SPI 512 <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>,
590 <GIC_SPI 513 <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>,
591 <GIC_SPI 514 <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>,
592 <GIC_SPI 515 <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>,
593 <GIC_SPI 516 <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>,
594 <GIC_SPI 517 <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>,
595 <GIC_SPI 518 <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
596 interrupt-names = "tei 519 interrupt-names = "tei", "ri", "ti", "spi", "sti",
597 "nak 520 "naki", "ali", "tmoi";
598 clocks = <&cpg CPG_MOD 521 clocks = <&cpg CPG_MOD R9A07G054_I2C2_PCLK>;
599 clock-frequency = <100 522 clock-frequency = <100000>;
600 resets = <&cpg R9A07G0 523 resets = <&cpg R9A07G054_I2C2_MRST>;
601 power-domains = <&cpg> 524 power-domains = <&cpg>;
602 status = "disabled"; 525 status = "disabled";
603 }; 526 };
604 527
605 i2c3: i2c@10058c00 { 528 i2c3: i2c@10058c00 {
606 #address-cells = <1>; 529 #address-cells = <1>;
607 #size-cells = <0>; 530 #size-cells = <0>;
608 compatible = "renesas, 531 compatible = "renesas,riic-r9a07g054", "renesas,riic-rz";
609 reg = <0 0x10058c00 0 532 reg = <0 0x10058c00 0 0x400>;
610 interrupts = <GIC_SPI 533 interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>,
611 <GIC_SPI 534 <GIC_SPI 372 IRQ_TYPE_EDGE_RISING>,
612 <GIC_SPI 535 <GIC_SPI 373 IRQ_TYPE_EDGE_RISING>,
613 <GIC_SPI 536 <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>,
614 <GIC_SPI 537 <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>,
615 <GIC_SPI 538 <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>,
616 <GIC_SPI 539 <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>,
617 <GIC_SPI 540 <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
618 interrupt-names = "tei 541 interrupt-names = "tei", "ri", "ti", "spi", "sti",
619 "nak 542 "naki", "ali", "tmoi";
620 clocks = <&cpg CPG_MOD 543 clocks = <&cpg CPG_MOD R9A07G054_I2C3_PCLK>;
621 clock-frequency = <100 544 clock-frequency = <100000>;
622 resets = <&cpg R9A07G0 545 resets = <&cpg R9A07G054_I2C3_MRST>;
623 power-domains = <&cpg> 546 power-domains = <&cpg>;
624 status = "disabled"; 547 status = "disabled";
625 }; 548 };
626 549
627 adc: adc@10059000 { 550 adc: adc@10059000 {
628 compatible = "renesas, 551 compatible = "renesas,r9a07g054-adc", "renesas,rzg2l-adc";
629 reg = <0 0x10059000 0 552 reg = <0 0x10059000 0 0x400>;
630 interrupts = <GIC_SPI 553 interrupts = <GIC_SPI 347 IRQ_TYPE_EDGE_RISING>;
631 clocks = <&cpg CPG_MOD 554 clocks = <&cpg CPG_MOD R9A07G054_ADC_ADCLK>,
632 <&cpg CPG_MOD 555 <&cpg CPG_MOD R9A07G054_ADC_PCLK>;
633 clock-names = "adclk", 556 clock-names = "adclk", "pclk";
634 resets = <&cpg R9A07G0 557 resets = <&cpg R9A07G054_ADC_PRESETN>,
635 <&cpg R9A07G0 558 <&cpg R9A07G054_ADC_ADRST_N>;
636 reset-names = "presetn 559 reset-names = "presetn", "adrst-n";
637 power-domains = <&cpg> 560 power-domains = <&cpg>;
638 status = "disabled"; 561 status = "disabled";
639 562
640 #address-cells = <1>; 563 #address-cells = <1>;
641 #size-cells = <0>; 564 #size-cells = <0>;
642 565
643 channel@0 { 566 channel@0 {
644 reg = <0>; 567 reg = <0>;
645 }; 568 };
646 channel@1 { 569 channel@1 {
647 reg = <1>; 570 reg = <1>;
648 }; 571 };
649 channel@2 { 572 channel@2 {
650 reg = <2>; 573 reg = <2>;
651 }; 574 };
652 channel@3 { 575 channel@3 {
653 reg = <3>; 576 reg = <3>;
654 }; 577 };
655 channel@4 { 578 channel@4 {
656 reg = <4>; 579 reg = <4>;
657 }; 580 };
658 channel@5 { 581 channel@5 {
659 reg = <5>; 582 reg = <5>;
660 }; 583 };
661 channel@6 { 584 channel@6 {
662 reg = <6>; 585 reg = <6>;
663 }; 586 };
664 channel@7 { 587 channel@7 {
665 reg = <7>; 588 reg = <7>;
666 }; 589 };
667 }; 590 };
668 591
669 tsu: thermal@10059400 { 592 tsu: thermal@10059400 {
670 compatible = "renesas, 593 compatible = "renesas,r9a07g054-tsu",
671 "renesas, 594 "renesas,rzg2l-tsu";
672 reg = <0 0x10059400 0 595 reg = <0 0x10059400 0 0x400>;
673 clocks = <&cpg CPG_MOD 596 clocks = <&cpg CPG_MOD R9A07G054_TSU_PCLK>;
674 resets = <&cpg R9A07G0 597 resets = <&cpg R9A07G054_TSU_PRESETN>;
675 power-domains = <&cpg> 598 power-domains = <&cpg>;
676 #thermal-sensor-cells 599 #thermal-sensor-cells = <1>;
677 }; 600 };
678 601
679 sbc: spi@10060000 { 602 sbc: spi@10060000 {
680 compatible = "renesas, 603 compatible = "renesas,r9a07g054-rpc-if",
681 "renesas, 604 "renesas,rzg2l-rpc-if";
682 reg = <0 0x10060000 0 605 reg = <0 0x10060000 0 0x10000>,
683 <0 0x20000000 0 606 <0 0x20000000 0 0x10000000>,
684 <0 0x10070000 0 607 <0 0x10070000 0 0x10000>;
685 reg-names = "regs", "d 608 reg-names = "regs", "dirmap", "wbuf";
686 interrupts = <GIC_SPI 609 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
687 clocks = <&cpg CPG_MOD 610 clocks = <&cpg CPG_MOD R9A07G054_SPI_CLK2>,
688 <&cpg CPG_MOD 611 <&cpg CPG_MOD R9A07G054_SPI_CLK>;
689 resets = <&cpg R9A07G0 612 resets = <&cpg R9A07G054_SPI_RST>;
690 power-domains = <&cpg> 613 power-domains = <&cpg>;
691 #address-cells = <1>; 614 #address-cells = <1>;
692 #size-cells = <0>; 615 #size-cells = <0>;
693 status = "disabled"; 616 status = "disabled";
694 }; 617 };
695 618
696 cru: video@10830000 { <<
697 compatible = "renesas, <<
698 reg = <0 0x10830000 0 <<
699 clocks = <&cpg CPG_MOD <<
700 <&cpg CPG_MOD <<
701 <&cpg CPG_MOD <<
702 clock-names = "video", <<
703 interrupts = <GIC_SPI <<
704 <GIC_SPI <<
705 <GIC_SPI <<
706 interrupt-names = "ima <<
707 resets = <&cpg R9A07G0 <<
708 <&cpg R9A07G0 <<
709 reset-names = "presetn <<
710 power-domains = <&cpg> <<
711 status = "disabled"; <<
712 <<
713 ports { <<
714 #address-cells <<
715 #size-cells = <<
716 <<
717 port@0 { <<
718 #addre <<
719 #size- <<
720 <<
721 reg = <<
722 crupar <<
723 <<
724 }; <<
725 }; <<
726 <<
727 port@1 { <<
728 #addre <<
729 #size- <<
730 <<
731 reg = <<
732 crucsi <<
733 <<
734 <<
735 }; <<
736 }; <<
737 }; <<
738 }; <<
739 <<
740 csi2: csi2@10830400 { <<
741 compatible = "renesas, <<
742 reg = <0 0x10830400 0 <<
743 interrupts = <GIC_SPI <<
744 clocks = <&cpg CPG_MOD <<
745 <&cpg CPG_MOD <<
746 <&cpg CPG_MOD <<
747 clock-names = "system" <<
748 resets = <&cpg R9A07G0 <<
749 <&cpg R9A07G0 <<
750 reset-names = "presetn <<
751 power-domains = <&cpg> <<
752 status = "disabled"; <<
753 <<
754 ports { <<
755 #address-cells <<
756 #size-cells = <<
757 <<
758 port@0 { <<
759 reg = <<
760 }; <<
761 <<
762 port@1 { <<
763 #addre <<
764 #size- <<
765 reg = <<
766 <<
767 csi2cr <<
768 <<
769 <<
770 }; <<
771 }; <<
772 }; <<
773 }; <<
774 <<
775 dsi: dsi@10850000 { <<
776 compatible = "renesas, <<
777 "renesas, <<
778 reg = <0 0x10850000 0 <<
779 interrupts = <GIC_SPI <<
780 <GIC_SPI <<
781 <GIC_SPI <<
782 <GIC_SPI <<
783 <GIC_SPI <<
784 <GIC_SPI <<
785 <GIC_SPI <<
786 interrupt-names = "seq <<
787 "fer <<
788 clocks = <&cpg CPG_MOD <<
789 <&cpg CPG_MOD <<
790 <&cpg CPG_MOD <<
791 <&cpg CPG_MOD <<
792 <&cpg CPG_MOD <<
793 <&cpg CPG_MOD <<
794 clock-names = "pllclk" <<
795 resets = <&cpg R9A07G0 <<
796 <&cpg R9A07G0 <<
797 <&cpg R9A07G0 <<
798 reset-names = "rst", " <<
799 power-domains = <&cpg> <<
800 status = "disabled"; <<
801 <<
802 ports { <<
803 #address-cells <<
804 #size-cells = <<
805 <<
806 port@0 { <<
807 reg = <<
808 dsi0_i <<
809 <<
810 }; <<
811 }; <<
812 <<
813 port@1 { <<
814 reg = <<
815 }; <<
816 }; <<
817 }; <<
818 <<
819 vspd: vsp@10870000 { <<
820 compatible = "renesas, <<
821 "renesas, <<
822 reg = <0 0x10870000 0 <<
823 interrupts = <GIC_SPI <<
824 clocks = <&cpg CPG_MOD <<
825 <&cpg CPG_MOD <<
826 <&cpg CPG_MOD <<
827 clock-names = "aclk", <<
828 power-domains = <&cpg> <<
829 resets = <&cpg R9A07G0 <<
830 renesas,fcp = <&fcpvd> <<
831 }; <<
832 <<
833 fcpvd: fcp@10880000 { <<
834 compatible = "renesas, <<
835 "renesas, <<
836 reg = <0 0x10880000 0 <<
837 clocks = <&cpg CPG_MOD <<
838 <&cpg CPG_MOD <<
839 <&cpg CPG_MOD <<
840 clock-names = "aclk", <<
841 power-domains = <&cpg> <<
842 resets = <&cpg R9A07G0 <<
843 }; <<
844 <<
845 du: display@10890000 { <<
846 compatible = "renesas, <<
847 "renesas, <<
848 reg = <0 0x10890000 0 <<
849 interrupts = <GIC_SPI <<
850 clocks = <&cpg CPG_MOD <<
851 <&cpg CPG_MOD <<
852 <&cpg CPG_MOD <<
853 clock-names = "aclk", <<
854 power-domains = <&cpg> <<
855 resets = <&cpg R9A07G0 <<
856 renesas,vsps = <&vspd <<
857 status = "disabled"; <<
858 <<
859 ports { <<
860 #address-cells <<
861 #size-cells = <<
862 <<
863 port@0 { <<
864 reg = <<
865 du_out <<
866 <<
867 }; <<
868 }; <<
869 <<
870 port@1 { <<
871 reg = <<
872 }; <<
873 }; <<
874 }; <<
875 <<
876 cpg: clock-controller@11010000 619 cpg: clock-controller@11010000 {
877 compatible = "renesas, 620 compatible = "renesas,r9a07g054-cpg";
878 reg = <0 0x11010000 0 621 reg = <0 0x11010000 0 0x10000>;
879 clocks = <&extal_clk>; 622 clocks = <&extal_clk>;
880 clock-names = "extal"; 623 clock-names = "extal";
881 #clock-cells = <2>; 624 #clock-cells = <2>;
882 #reset-cells = <1>; 625 #reset-cells = <1>;
883 #power-domain-cells = 626 #power-domain-cells = <0>;
884 }; 627 };
885 628
886 sysc: system-controller@110200 629 sysc: system-controller@11020000 {
887 compatible = "renesas, 630 compatible = "renesas,r9a07g054-sysc";
888 reg = <0 0x11020000 0 631 reg = <0 0x11020000 0 0x10000>;
889 interrupts = <GIC_SPI 632 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
890 <GIC_SPI 633 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
891 <GIC_SPI 634 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
892 <GIC_SPI 635 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
893 interrupt-names = "lpm 636 interrupt-names = "lpm_int", "ca55stbydone_int",
894 "cm3 637 "cm33stbyr_int", "ca55_deny";
895 status = "disabled"; 638 status = "disabled";
896 }; 639 };
897 640
898 pinctrl: pinctrl@11030000 { 641 pinctrl: pinctrl@11030000 {
899 compatible = "renesas, 642 compatible = "renesas,r9a07g054-pinctrl",
900 "renesas, 643 "renesas,r9a07g044-pinctrl";
901 reg = <0 0x11030000 0 644 reg = <0 0x11030000 0 0x10000>;
902 gpio-controller; 645 gpio-controller;
903 #gpio-cells = <2>; 646 #gpio-cells = <2>;
904 #interrupt-cells = <2> <<
905 interrupt-parent = <&i <<
906 interrupt-controller; <<
907 gpio-ranges = <&pinctr 647 gpio-ranges = <&pinctrl 0 0 392>;
908 clocks = <&cpg CPG_MOD 648 clocks = <&cpg CPG_MOD R9A07G054_GPIO_HCLK>;
909 power-domains = <&cpg> 649 power-domains = <&cpg>;
910 resets = <&cpg R9A07G0 650 resets = <&cpg R9A07G054_GPIO_RSTN>,
911 <&cpg R9A07G0 651 <&cpg R9A07G054_GPIO_PORT_RESETN>,
912 <&cpg R9A07G0 652 <&cpg R9A07G054_GPIO_SPARE_RESETN>;
913 }; 653 };
914 654
915 irqc: interrupt-controller@110 <<
916 compatible = "renesas, <<
917 "renesas, <<
918 #interrupt-cells = <2> <<
919 #address-cells = <0>; <<
920 interrupt-controller; <<
921 reg = <0 0x110a0000 0 <<
922 interrupts = <GIC_SPI <<
923 <GIC_SPI <<
924 <GIC_SPI <<
925 <GIC_SPI <<
926 <GIC_SPI <<
927 <GIC_SPI <<
928 <GIC_SPI <<
929 <GIC_SPI <<
930 <GIC_SPI <<
931 <GIC_SPI <<
932 <GIC_SPI <<
933 <GIC_SPI <<
934 <GIC_SPI <<
935 <GIC_SPI <<
936 <GIC_SPI <<
937 <GIC_SPI <<
938 <GIC_SPI <<
939 <GIC_SPI <<
940 <GIC_SPI <<
941 <GIC_SPI <<
942 <GIC_SPI <<
943 <GIC_SPI <<
944 <GIC_SPI <<
945 <GIC_SPI <<
946 <GIC_SPI <<
947 <GIC_SPI <<
948 <GIC_SPI <<
949 <GIC_SPI <<
950 <GIC_SPI <<
951 <GIC_SPI <<
952 <GIC_SPI <<
953 <GIC_SPI <<
954 <GIC_SPI <<
955 <GIC_SPI <<
956 <GIC_SPI <<
957 <GIC_SPI <<
958 <GIC_SPI <<
959 <GIC_SPI <<
960 <GIC_SPI <<
961 <GIC_SPI <<
962 <GIC_SPI <<
963 <GIC_SPI <<
964 <GIC_SPI <<
965 <GIC_SPI <<
966 <GIC_SPI <<
967 <GIC_SPI <<
968 <GIC_SPI <<
969 <GIC_SPI <<
970 interrupt-names = "nmi <<
971 "irq <<
972 "tin <<
973 "tin <<
974 "tin <<
975 "tin <<
976 "tin <<
977 "tin <<
978 "tin <<
979 "tin <<
980 "bus <<
981 "ec7 <<
982 "ec7 <<
983 clocks = <&cpg CPG_MOD <<
984 <&cpg CPG_MOD <<
985 clock-names = "clk", " <<
986 power-domains = <&cpg> <<
987 resets = <&cpg R9A07G0 <<
988 }; <<
989 <<
990 dmac: dma-controller@11820000 655 dmac: dma-controller@11820000 {
991 compatible = "renesas, 656 compatible = "renesas,r9a07g054-dmac",
992 "renesas, 657 "renesas,rz-dmac";
993 reg = <0 0x11820000 0 658 reg = <0 0x11820000 0 0x10000>,
994 <0 0x11830000 0 659 <0 0x11830000 0 0x10000>;
995 interrupts = <GIC_SPI 660 interrupts = <GIC_SPI 141 IRQ_TYPE_EDGE_RISING>,
996 <GIC_SPI 661 <GIC_SPI 125 IRQ_TYPE_EDGE_RISING>,
997 <GIC_SPI 662 <GIC_SPI 126 IRQ_TYPE_EDGE_RISING>,
998 <GIC_SPI 663 <GIC_SPI 127 IRQ_TYPE_EDGE_RISING>,
999 <GIC_SPI 664 <GIC_SPI 128 IRQ_TYPE_EDGE_RISING>,
1000 <GIC_SPI 665 <GIC_SPI 129 IRQ_TYPE_EDGE_RISING>,
1001 <GIC_SPI 666 <GIC_SPI 130 IRQ_TYPE_EDGE_RISING>,
1002 <GIC_SPI 667 <GIC_SPI 131 IRQ_TYPE_EDGE_RISING>,
1003 <GIC_SPI 668 <GIC_SPI 132 IRQ_TYPE_EDGE_RISING>,
1004 <GIC_SPI 669 <GIC_SPI 133 IRQ_TYPE_EDGE_RISING>,
1005 <GIC_SPI 670 <GIC_SPI 134 IRQ_TYPE_EDGE_RISING>,
1006 <GIC_SPI 671 <GIC_SPI 135 IRQ_TYPE_EDGE_RISING>,
1007 <GIC_SPI 672 <GIC_SPI 136 IRQ_TYPE_EDGE_RISING>,
1008 <GIC_SPI 673 <GIC_SPI 137 IRQ_TYPE_EDGE_RISING>,
1009 <GIC_SPI 674 <GIC_SPI 138 IRQ_TYPE_EDGE_RISING>,
1010 <GIC_SPI 675 <GIC_SPI 139 IRQ_TYPE_EDGE_RISING>,
1011 <GIC_SPI 676 <GIC_SPI 140 IRQ_TYPE_EDGE_RISING>;
1012 interrupt-names = "er 677 interrupt-names = "error",
1013 "ch 678 "ch0", "ch1", "ch2", "ch3",
1014 "ch 679 "ch4", "ch5", "ch6", "ch7",
1015 "ch 680 "ch8", "ch9", "ch10", "ch11",
1016 "ch 681 "ch12", "ch13", "ch14", "ch15";
1017 clocks = <&cpg CPG_MO 682 clocks = <&cpg CPG_MOD R9A07G054_DMAC_ACLK>,
1018 <&cpg CPG_MO 683 <&cpg CPG_MOD R9A07G054_DMAC_PCLK>;
1019 clock-names = "main", <<
1020 power-domains = <&cpg 684 power-domains = <&cpg>;
1021 resets = <&cpg R9A07G 685 resets = <&cpg R9A07G054_DMAC_ARESETN>,
1022 <&cpg R9A07G 686 <&cpg R9A07G054_DMAC_RST_ASYNC>;
1023 reset-names = "arst", <<
1024 #dma-cells = <1>; 687 #dma-cells = <1>;
1025 dma-channels = <16>; 688 dma-channels = <16>;
1026 }; 689 };
1027 690
1028 gpu: gpu@11840000 { 691 gpu: gpu@11840000 {
1029 compatible = "renesas 692 compatible = "renesas,r9a07g054-mali",
1030 "arm,mal 693 "arm,mali-bifrost";
1031 reg = <0x0 0x11840000 694 reg = <0x0 0x11840000 0x0 0x10000>;
1032 interrupts = <GIC_SPI 695 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
1033 <GIC_SPI 696 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
1034 <GIC_SPI 697 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
1035 <GIC_SPI 698 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
1036 interrupt-names = "jo 699 interrupt-names = "job", "mmu", "gpu", "event";
1037 clocks = <&cpg CPG_MO 700 clocks = <&cpg CPG_MOD R9A07G054_GPU_CLK>,
1038 <&cpg CPG_MO 701 <&cpg CPG_MOD R9A07G054_GPU_AXI_CLK>,
1039 <&cpg CPG_MO 702 <&cpg CPG_MOD R9A07G054_GPU_ACE_CLK>;
1040 clock-names = "gpu", 703 clock-names = "gpu", "bus", "bus_ace";
1041 power-domains = <&cpg 704 power-domains = <&cpg>;
1042 resets = <&cpg R9A07G 705 resets = <&cpg R9A07G054_GPU_RESETN>,
1043 <&cpg R9A07G 706 <&cpg R9A07G054_GPU_AXI_RESETN>,
1044 <&cpg R9A07G 707 <&cpg R9A07G054_GPU_ACE_RESETN>;
1045 reset-names = "rst", 708 reset-names = "rst", "axi_rst", "ace_rst";
1046 operating-points-v2 = 709 operating-points-v2 = <&gpu_opp_table>;
1047 }; 710 };
1048 711
1049 gic: interrupt-controller@119 712 gic: interrupt-controller@11900000 {
1050 compatible = "arm,gic 713 compatible = "arm,gic-v3";
1051 #interrupt-cells = <3 714 #interrupt-cells = <3>;
1052 #address-cells = <0>; 715 #address-cells = <0>;
1053 interrupt-controller; 716 interrupt-controller;
1054 reg = <0x0 0x11900000 !! 717 reg = <0x0 0x11900000 0 0x40000>,
1055 <0x0 0x11940000 !! 718 <0x0 0x11940000 0 0x60000>;
1056 interrupts = <GIC_PPI 719 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
1057 }; 720 };
1058 721
1059 sdhi0: mmc@11c00000 { !! 722 sdhi0: mmc@11c00000 {
1060 compatible = "renesas 723 compatible = "renesas,sdhi-r9a07g054",
1061 "renesas !! 724 "renesas,rcar-gen3-sdhi";
1062 reg = <0x0 0x11c00000 725 reg = <0x0 0x11c00000 0 0x10000>;
1063 interrupts = <GIC_SPI 726 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
1064 <GIC_SPI 727 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
1065 clocks = <&cpg CPG_MO 728 clocks = <&cpg CPG_MOD R9A07G054_SDHI0_IMCLK>,
1066 <&cpg CPG_MO 729 <&cpg CPG_MOD R9A07G054_SDHI0_CLK_HS>,
1067 <&cpg CPG_MO 730 <&cpg CPG_MOD R9A07G054_SDHI0_IMCLK2>,
1068 <&cpg CPG_MO 731 <&cpg CPG_MOD R9A07G054_SDHI0_ACLK>;
1069 clock-names = "core", 732 clock-names = "core", "clkh", "cd", "aclk";
1070 resets = <&cpg R9A07G 733 resets = <&cpg R9A07G054_SDHI0_IXRST>;
1071 power-domains = <&cpg 734 power-domains = <&cpg>;
1072 status = "disabled"; 735 status = "disabled";
1073 }; 736 };
1074 737
1075 sdhi1: mmc@11c10000 { 738 sdhi1: mmc@11c10000 {
1076 compatible = "renesas 739 compatible = "renesas,sdhi-r9a07g054",
1077 "renesas !! 740 "renesas,rcar-gen3-sdhi";
1078 reg = <0x0 0x11c10000 741 reg = <0x0 0x11c10000 0 0x10000>;
1079 interrupts = <GIC_SPI 742 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
1080 <GIC_SPI 743 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
1081 clocks = <&cpg CPG_MO 744 clocks = <&cpg CPG_MOD R9A07G054_SDHI1_IMCLK>,
1082 <&cpg CPG_MO 745 <&cpg CPG_MOD R9A07G054_SDHI1_CLK_HS>,
1083 <&cpg CPG_MO 746 <&cpg CPG_MOD R9A07G054_SDHI1_IMCLK2>,
1084 <&cpg CPG_MO 747 <&cpg CPG_MOD R9A07G054_SDHI1_ACLK>;
1085 clock-names = "core", 748 clock-names = "core", "clkh", "cd", "aclk";
1086 resets = <&cpg R9A07G 749 resets = <&cpg R9A07G054_SDHI1_IXRST>;
1087 power-domains = <&cpg 750 power-domains = <&cpg>;
1088 status = "disabled"; 751 status = "disabled";
1089 }; 752 };
1090 753
1091 eth0: ethernet@11c20000 { 754 eth0: ethernet@11c20000 {
1092 compatible = "renesas 755 compatible = "renesas,r9a07g054-gbeth",
1093 "renesas 756 "renesas,rzg2l-gbeth";
1094 reg = <0 0x11c20000 0 757 reg = <0 0x11c20000 0 0x10000>;
1095 interrupts = <GIC_SPI 758 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
1096 <GIC_SPI 759 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
1097 <GIC_SPI 760 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
1098 interrupt-names = "mu 761 interrupt-names = "mux", "fil", "arp_ns";
1099 phy-mode = "rgmii"; 762 phy-mode = "rgmii";
1100 clocks = <&cpg CPG_MO 763 clocks = <&cpg CPG_MOD R9A07G054_ETH0_CLK_AXI>,
1101 <&cpg CPG_MO 764 <&cpg CPG_MOD R9A07G054_ETH0_CLK_CHI>,
1102 <&cpg CPG_CO 765 <&cpg CPG_CORE R9A07G054_CLK_HP>;
1103 clock-names = "axi", 766 clock-names = "axi", "chi", "refclk";
1104 resets = <&cpg R9A07G 767 resets = <&cpg R9A07G054_ETH0_RST_HW_N>;
1105 power-domains = <&cpg 768 power-domains = <&cpg>;
1106 #address-cells = <1>; 769 #address-cells = <1>;
1107 #size-cells = <0>; 770 #size-cells = <0>;
1108 status = "disabled"; 771 status = "disabled";
1109 }; 772 };
1110 773
1111 eth1: ethernet@11c30000 { 774 eth1: ethernet@11c30000 {
1112 compatible = "renesas 775 compatible = "renesas,r9a07g054-gbeth",
1113 "renesas 776 "renesas,rzg2l-gbeth";
1114 reg = <0 0x11c30000 0 777 reg = <0 0x11c30000 0 0x10000>;
1115 interrupts = <GIC_SPI 778 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
1116 <GIC_SPI 779 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
1117 <GIC_SPI 780 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
1118 interrupt-names = "mu 781 interrupt-names = "mux", "fil", "arp_ns";
1119 phy-mode = "rgmii"; 782 phy-mode = "rgmii";
1120 clocks = <&cpg CPG_MO 783 clocks = <&cpg CPG_MOD R9A07G054_ETH1_CLK_AXI>,
1121 <&cpg CPG_MO 784 <&cpg CPG_MOD R9A07G054_ETH1_CLK_CHI>,
1122 <&cpg CPG_CO 785 <&cpg CPG_CORE R9A07G054_CLK_HP>;
1123 clock-names = "axi", 786 clock-names = "axi", "chi", "refclk";
1124 resets = <&cpg R9A07G 787 resets = <&cpg R9A07G054_ETH1_RST_HW_N>;
1125 power-domains = <&cpg 788 power-domains = <&cpg>;
1126 #address-cells = <1>; 789 #address-cells = <1>;
1127 #size-cells = <0>; 790 #size-cells = <0>;
1128 status = "disabled"; 791 status = "disabled";
1129 }; 792 };
1130 793
1131 phyrst: usbphy-ctrl@11c40000 794 phyrst: usbphy-ctrl@11c40000 {
1132 compatible = "renesas 795 compatible = "renesas,r9a07g054-usbphy-ctrl",
1133 "renesas 796 "renesas,rzg2l-usbphy-ctrl";
1134 reg = <0 0x11c40000 0 797 reg = <0 0x11c40000 0 0x10000>;
1135 clocks = <&cpg CPG_MO 798 clocks = <&cpg CPG_MOD R9A07G054_USB_PCLK>;
1136 resets = <&cpg R9A07G 799 resets = <&cpg R9A07G054_USB_PRESETN>;
1137 power-domains = <&cpg 800 power-domains = <&cpg>;
1138 #reset-cells = <1>; 801 #reset-cells = <1>;
1139 status = "disabled"; 802 status = "disabled";
1140 <<
1141 usb0_vbus_otg: regula <<
1142 regulator-nam <<
1143 }; <<
1144 }; 803 };
1145 804
1146 ohci0: usb@11c50000 { 805 ohci0: usb@11c50000 {
1147 compatible = "generic 806 compatible = "generic-ohci";
1148 reg = <0 0x11c50000 0 807 reg = <0 0x11c50000 0 0x100>;
1149 interrupts = <GIC_SPI 808 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
1150 clocks = <&cpg CPG_MO 809 clocks = <&cpg CPG_MOD R9A07G054_USB_PCLK>,
1151 <&cpg CPG_MO 810 <&cpg CPG_MOD R9A07G054_USB_U2H0_HCLK>;
1152 resets = <&phyrst 0>, 811 resets = <&phyrst 0>,
1153 <&cpg R9A07G 812 <&cpg R9A07G054_USB_U2H0_HRESETN>;
1154 phys = <&usb2_phy0 1> 813 phys = <&usb2_phy0 1>;
1155 phy-names = "usb"; 814 phy-names = "usb";
1156 power-domains = <&cpg 815 power-domains = <&cpg>;
1157 status = "disabled"; 816 status = "disabled";
1158 }; 817 };
1159 818
1160 ohci1: usb@11c70000 { 819 ohci1: usb@11c70000 {
1161 compatible = "generic 820 compatible = "generic-ohci";
1162 reg = <0 0x11c70000 0 821 reg = <0 0x11c70000 0 0x100>;
1163 interrupts = <GIC_SPI 822 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
1164 clocks = <&cpg CPG_MO 823 clocks = <&cpg CPG_MOD R9A07G054_USB_PCLK>,
1165 <&cpg CPG_MO 824 <&cpg CPG_MOD R9A07G054_USB_U2H1_HCLK>;
1166 resets = <&phyrst 1>, 825 resets = <&phyrst 1>,
1167 <&cpg R9A07G 826 <&cpg R9A07G054_USB_U2H1_HRESETN>;
1168 phys = <&usb2_phy1 1> 827 phys = <&usb2_phy1 1>;
1169 phy-names = "usb"; 828 phy-names = "usb";
1170 power-domains = <&cpg 829 power-domains = <&cpg>;
1171 status = "disabled"; 830 status = "disabled";
1172 }; 831 };
1173 832
1174 ehci0: usb@11c50100 { 833 ehci0: usb@11c50100 {
1175 compatible = "generic 834 compatible = "generic-ehci";
1176 reg = <0 0x11c50100 0 835 reg = <0 0x11c50100 0 0x100>;
1177 interrupts = <GIC_SPI 836 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
1178 clocks = <&cpg CPG_MO 837 clocks = <&cpg CPG_MOD R9A07G054_USB_PCLK>,
1179 <&cpg CPG_MO 838 <&cpg CPG_MOD R9A07G054_USB_U2H0_HCLK>;
1180 resets = <&phyrst 0>, 839 resets = <&phyrst 0>,
1181 <&cpg R9A07G 840 <&cpg R9A07G054_USB_U2H0_HRESETN>;
1182 phys = <&usb2_phy0 2> 841 phys = <&usb2_phy0 2>;
1183 phy-names = "usb"; 842 phy-names = "usb";
1184 companion = <&ohci0>; 843 companion = <&ohci0>;
1185 power-domains = <&cpg 844 power-domains = <&cpg>;
1186 status = "disabled"; 845 status = "disabled";
1187 }; 846 };
1188 847
1189 ehci1: usb@11c70100 { 848 ehci1: usb@11c70100 {
1190 compatible = "generic 849 compatible = "generic-ehci";
1191 reg = <0 0x11c70100 0 850 reg = <0 0x11c70100 0 0x100>;
1192 interrupts = <GIC_SPI 851 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
1193 clocks = <&cpg CPG_MO 852 clocks = <&cpg CPG_MOD R9A07G054_USB_PCLK>,
1194 <&cpg CPG_MO 853 <&cpg CPG_MOD R9A07G054_USB_U2H1_HCLK>;
1195 resets = <&phyrst 1>, 854 resets = <&phyrst 1>,
1196 <&cpg R9A07G 855 <&cpg R9A07G054_USB_U2H1_HRESETN>;
1197 phys = <&usb2_phy1 2> 856 phys = <&usb2_phy1 2>;
1198 phy-names = "usb"; 857 phy-names = "usb";
1199 companion = <&ohci1>; 858 companion = <&ohci1>;
1200 power-domains = <&cpg 859 power-domains = <&cpg>;
1201 status = "disabled"; 860 status = "disabled";
1202 }; 861 };
1203 862
1204 usb2_phy0: usb-phy@11c50200 { 863 usb2_phy0: usb-phy@11c50200 {
1205 compatible = "renesas 864 compatible = "renesas,usb2-phy-r9a07g054",
1206 "renesas 865 "renesas,rzg2l-usb2-phy";
1207 reg = <0 0x11c50200 0 866 reg = <0 0x11c50200 0 0x700>;
1208 interrupts = <GIC_SPI 867 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
1209 clocks = <&cpg CPG_MO 868 clocks = <&cpg CPG_MOD R9A07G054_USB_PCLK>,
1210 <&cpg CPG_MO 869 <&cpg CPG_MOD R9A07G054_USB_U2H0_HCLK>;
1211 resets = <&phyrst 0>; 870 resets = <&phyrst 0>;
1212 #phy-cells = <1>; 871 #phy-cells = <1>;
1213 power-domains = <&cpg 872 power-domains = <&cpg>;
1214 status = "disabled"; 873 status = "disabled";
1215 }; 874 };
1216 875
1217 usb2_phy1: usb-phy@11c70200 { 876 usb2_phy1: usb-phy@11c70200 {
1218 compatible = "renesas 877 compatible = "renesas,usb2-phy-r9a07g054",
1219 "renesas 878 "renesas,rzg2l-usb2-phy";
1220 reg = <0 0x11c70200 0 879 reg = <0 0x11c70200 0 0x700>;
1221 interrupts = <GIC_SPI 880 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
1222 clocks = <&cpg CPG_MO 881 clocks = <&cpg CPG_MOD R9A07G054_USB_PCLK>,
1223 <&cpg CPG_MO 882 <&cpg CPG_MOD R9A07G054_USB_U2H1_HCLK>;
1224 resets = <&phyrst 1>; 883 resets = <&phyrst 1>;
1225 #phy-cells = <1>; 884 #phy-cells = <1>;
1226 power-domains = <&cpg 885 power-domains = <&cpg>;
1227 status = "disabled"; 886 status = "disabled";
1228 }; 887 };
1229 888
1230 hsusb: usb@11c60000 { 889 hsusb: usb@11c60000 {
1231 compatible = "renesas 890 compatible = "renesas,usbhs-r9a07g054",
1232 "renesas !! 891 "renesas,rza2-usbhs";
1233 reg = <0 0x11c60000 0 892 reg = <0 0x11c60000 0 0x10000>;
1234 interrupts = <GIC_SPI 893 interrupts = <GIC_SPI 100 IRQ_TYPE_EDGE_RISING>,
1235 <GIC_SPI 894 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
1236 <GIC_SPI 895 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
1237 <GIC_SPI 896 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
1238 clocks = <&cpg CPG_MO 897 clocks = <&cpg CPG_MOD R9A07G054_USB_PCLK>,
1239 <&cpg CPG_MO 898 <&cpg CPG_MOD R9A07G054_USB_U2P_EXR_CPUCLK>;
1240 resets = <&phyrst 0>, 899 resets = <&phyrst 0>,
1241 <&cpg R9A07G 900 <&cpg R9A07G054_USB_U2P_EXL_SYSRST>;
1242 renesas,buswait = <7> 901 renesas,buswait = <7>;
1243 phys = <&usb2_phy0 3> 902 phys = <&usb2_phy0 3>;
1244 phy-names = "usb"; 903 phy-names = "usb";
1245 power-domains = <&cpg 904 power-domains = <&cpg>;
1246 status = "disabled"; 905 status = "disabled";
1247 }; 906 };
1248 907
1249 wdt0: watchdog@12800800 { 908 wdt0: watchdog@12800800 {
1250 compatible = "renesas 909 compatible = "renesas,r9a07g054-wdt",
1251 "renesas 910 "renesas,rzg2l-wdt";
1252 reg = <0 0x12800800 0 911 reg = <0 0x12800800 0 0x400>;
1253 clocks = <&cpg CPG_MO 912 clocks = <&cpg CPG_MOD R9A07G054_WDT0_PCLK>,
1254 <&cpg CPG_MO 913 <&cpg CPG_MOD R9A07G054_WDT0_CLK>;
1255 clock-names = "pclk", 914 clock-names = "pclk", "oscclk";
1256 interrupts = <GIC_SPI 915 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
1257 <GIC_SPI 916 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
1258 interrupt-names = "wd 917 interrupt-names = "wdt", "perrout";
1259 resets = <&cpg R9A07G 918 resets = <&cpg R9A07G054_WDT0_PRESETN>;
1260 power-domains = <&cpg 919 power-domains = <&cpg>;
1261 status = "disabled"; 920 status = "disabled";
1262 }; 921 };
1263 922
1264 wdt1: watchdog@12800c00 { 923 wdt1: watchdog@12800c00 {
1265 compatible = "renesas 924 compatible = "renesas,r9a07g054-wdt",
1266 "renesas 925 "renesas,rzg2l-wdt";
1267 reg = <0 0x12800C00 0 926 reg = <0 0x12800C00 0 0x400>;
1268 clocks = <&cpg CPG_MO 927 clocks = <&cpg CPG_MOD R9A07G054_WDT1_PCLK>,
1269 <&cpg CPG_MO 928 <&cpg CPG_MOD R9A07G054_WDT1_CLK>;
1270 clock-names = "pclk", 929 clock-names = "pclk", "oscclk";
1271 interrupts = <GIC_SPI 930 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
1272 <GIC_SPI 931 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
1273 interrupt-names = "wd 932 interrupt-names = "wdt", "perrout";
1274 resets = <&cpg R9A07G 933 resets = <&cpg R9A07G054_WDT1_PRESETN>;
1275 power-domains = <&cpg 934 power-domains = <&cpg>;
1276 status = "disabled"; 935 status = "disabled";
1277 }; 936 };
1278 937
>> 938 wdt2: watchdog@12800400 {
>> 939 compatible = "renesas,r9a07g054-wdt",
>> 940 "renesas,rzg2l-wdt";
>> 941 reg = <0 0x12800400 0 0x400>;
>> 942 clocks = <&cpg CPG_MOD R9A07G054_WDT2_PCLK>,
>> 943 <&cpg CPG_MOD R9A07G054_WDT2_CLK>;
>> 944 clock-names = "pclk", "oscclk";
>> 945 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
>> 946 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
>> 947 interrupt-names = "wdt", "perrout";
>> 948 resets = <&cpg R9A07G054_WDT2_PRESETN>;
>> 949 power-domains = <&cpg>;
>> 950 status = "disabled";
>> 951 };
>> 952
1279 ostm0: timer@12801000 { 953 ostm0: timer@12801000 {
1280 compatible = "renesas 954 compatible = "renesas,r9a07g054-ostm",
1281 "renesas 955 "renesas,ostm";
1282 reg = <0x0 0x12801000 956 reg = <0x0 0x12801000 0x0 0x400>;
1283 interrupts = <GIC_SPI 957 interrupts = <GIC_SPI 46 IRQ_TYPE_EDGE_RISING>;
1284 clocks = <&cpg CPG_MO 958 clocks = <&cpg CPG_MOD R9A07G054_OSTM0_PCLK>;
1285 resets = <&cpg R9A07G 959 resets = <&cpg R9A07G054_OSTM0_PRESETZ>;
1286 power-domains = <&cpg 960 power-domains = <&cpg>;
1287 status = "disabled"; 961 status = "disabled";
1288 }; 962 };
1289 963
1290 ostm1: timer@12801400 { 964 ostm1: timer@12801400 {
1291 compatible = "renesas 965 compatible = "renesas,r9a07g054-ostm",
1292 "renesas 966 "renesas,ostm";
1293 reg = <0x0 0x12801400 967 reg = <0x0 0x12801400 0x0 0x400>;
1294 interrupts = <GIC_SPI 968 interrupts = <GIC_SPI 47 IRQ_TYPE_EDGE_RISING>;
1295 clocks = <&cpg CPG_MO 969 clocks = <&cpg CPG_MOD R9A07G054_OSTM1_PCLK>;
1296 resets = <&cpg R9A07G 970 resets = <&cpg R9A07G054_OSTM1_PRESETZ>;
1297 power-domains = <&cpg 971 power-domains = <&cpg>;
1298 status = "disabled"; 972 status = "disabled";
1299 }; 973 };
1300 974
1301 ostm2: timer@12801800 { 975 ostm2: timer@12801800 {
1302 compatible = "renesas 976 compatible = "renesas,r9a07g054-ostm",
1303 "renesas 977 "renesas,ostm";
1304 reg = <0x0 0x12801800 978 reg = <0x0 0x12801800 0x0 0x400>;
1305 interrupts = <GIC_SPI 979 interrupts = <GIC_SPI 48 IRQ_TYPE_EDGE_RISING>;
1306 clocks = <&cpg CPG_MO 980 clocks = <&cpg CPG_MOD R9A07G054_OSTM2_PCLK>;
1307 resets = <&cpg R9A07G 981 resets = <&cpg R9A07G054_OSTM2_PRESETZ>;
1308 power-domains = <&cpg 982 power-domains = <&cpg>;
1309 status = "disabled"; 983 status = "disabled";
1310 }; 984 };
1311 }; 985 };
1312 986
1313 thermal-zones { 987 thermal-zones {
1314 cpu-thermal { 988 cpu-thermal {
1315 polling-delay-passive 989 polling-delay-passive = <250>;
1316 polling-delay = <1000 990 polling-delay = <1000>;
1317 thermal-sensors = <&t 991 thermal-sensors = <&tsu 0>;
1318 sustainable-power = < 992 sustainable-power = <717>;
1319 993
1320 cooling-maps { 994 cooling-maps {
1321 map0 { 995 map0 {
1322 trip 996 trip = <&target>;
1323 cooli 997 cooling-device = <&cpu0 0 2>;
1324 contr 998 contribution = <1024>;
1325 }; 999 };
1326 }; 1000 };
1327 1001
1328 trips { 1002 trips {
1329 sensor_crit: 1003 sensor_crit: sensor-crit {
1330 tempe 1004 temperature = <125000>;
1331 hyste 1005 hysteresis = <1000>;
1332 type 1006 type = "critical";
1333 }; 1007 };
1334 1008
1335 target: trip- 1009 target: trip-point {
1336 tempe 1010 temperature = <100000>;
1337 hyste 1011 hysteresis = <1000>;
1338 type 1012 type = "passive";
1339 }; 1013 };
1340 }; 1014 };
1341 }; 1015 };
1342 }; 1016 };
1343 1017
1344 timer { 1018 timer {
1345 compatible = "arm,armv8-timer 1019 compatible = "arm,armv8-timer";
1346 interrupts-extended = <&gic G !! 1020 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
1347 <&gic G !! 1021 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
1348 <&gic G !! 1022 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
1349 <&gic G !! 1023 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
1350 <&gic G <<
1351 interrupt-names = "sec-phys", <<
1352 "hyp-virt"; <<
1353 }; 1024 };
1354 }; 1025 };
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