1 // SPDX-License-Identifier: (GPL-2.0-only OR B 1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 /* 2 /*
3 * Device Tree Source for the RZ/V2L SoC 3 * Device Tree Source for the RZ/V2L SoC
4 * 4 *
5 * Copyright (C) 2021 Renesas Electronics Corp 5 * Copyright (C) 2021 Renesas Electronics Corp.
6 */ 6 */
7 7
8 #include <dt-bindings/interrupt-controller/arm 8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/clock/r9a07g054-cpg.h> 9 #include <dt-bindings/clock/r9a07g054-cpg.h>
10 10
11 / { 11 / {
12 compatible = "renesas,r9a07g054"; 12 compatible = "renesas,r9a07g054";
13 #address-cells = <2>; 13 #address-cells = <2>;
14 #size-cells = <2>; 14 #size-cells = <2>;
15 15
16 audio_clk1: audio1-clk { 16 audio_clk1: audio1-clk {
17 compatible = "fixed-clock"; 17 compatible = "fixed-clock";
18 #clock-cells = <0>; 18 #clock-cells = <0>;
19 /* This value must be overridd 19 /* This value must be overridden by boards that provide it */
20 clock-frequency = <0>; 20 clock-frequency = <0>;
21 }; 21 };
22 22
23 audio_clk2: audio2-clk { 23 audio_clk2: audio2-clk {
24 compatible = "fixed-clock"; 24 compatible = "fixed-clock";
25 #clock-cells = <0>; 25 #clock-cells = <0>;
26 /* This value must be overridd 26 /* This value must be overridden by boards that provide it */
27 clock-frequency = <0>; 27 clock-frequency = <0>;
28 }; 28 };
29 29
30 /* External CAN clock - to be overridd 30 /* External CAN clock - to be overridden by boards that provide it */
31 can_clk: can-clk { 31 can_clk: can-clk {
32 compatible = "fixed-clock"; 32 compatible = "fixed-clock";
33 #clock-cells = <0>; 33 #clock-cells = <0>;
34 clock-frequency = <0>; 34 clock-frequency = <0>;
35 }; 35 };
36 36
37 /* clock can be either from exclk or c 37 /* clock can be either from exclk or crystal oscillator (XIN/XOUT) */
38 extal_clk: extal-clk { 38 extal_clk: extal-clk {
39 compatible = "fixed-clock"; 39 compatible = "fixed-clock";
40 #clock-cells = <0>; 40 #clock-cells = <0>;
41 /* This value must be overridd 41 /* This value must be overridden by the board */
42 clock-frequency = <0>; 42 clock-frequency = <0>;
43 }; 43 };
44 44
45 cluster0_opp: opp-table-0 { 45 cluster0_opp: opp-table-0 {
46 compatible = "operating-points 46 compatible = "operating-points-v2";
47 opp-shared; 47 opp-shared;
48 48
49 opp-150000000 { 49 opp-150000000 {
50 opp-hz = /bits/ 64 <15 50 opp-hz = /bits/ 64 <150000000>;
51 opp-microvolt = <11000 51 opp-microvolt = <1100000>;
52 clock-latency-ns = <30 52 clock-latency-ns = <300000>;
53 }; 53 };
54 opp-300000000 { 54 opp-300000000 {
55 opp-hz = /bits/ 64 <30 55 opp-hz = /bits/ 64 <300000000>;
56 opp-microvolt = <11000 56 opp-microvolt = <1100000>;
57 clock-latency-ns = <30 57 clock-latency-ns = <300000>;
58 }; 58 };
59 opp-600000000 { 59 opp-600000000 {
60 opp-hz = /bits/ 64 <60 60 opp-hz = /bits/ 64 <600000000>;
61 opp-microvolt = <11000 61 opp-microvolt = <1100000>;
62 clock-latency-ns = <30 62 clock-latency-ns = <300000>;
63 }; 63 };
64 opp-1200000000 { 64 opp-1200000000 {
65 opp-hz = /bits/ 64 <12 65 opp-hz = /bits/ 64 <1200000000>;
66 opp-microvolt = <11000 66 opp-microvolt = <1100000>;
67 clock-latency-ns = <30 67 clock-latency-ns = <300000>;
68 opp-suspend; 68 opp-suspend;
69 }; 69 };
70 }; 70 };
71 71
72 cpus { 72 cpus {
73 #address-cells = <1>; 73 #address-cells = <1>;
74 #size-cells = <0>; 74 #size-cells = <0>;
75 75
76 cpu-map { 76 cpu-map {
77 cluster0 { 77 cluster0 {
78 core0 { 78 core0 {
79 cpu = 79 cpu = <&cpu0>;
80 }; 80 };
81 core1 { 81 core1 {
82 cpu = 82 cpu = <&cpu1>;
83 }; 83 };
84 }; 84 };
85 }; 85 };
86 86
87 cpu0: cpu@0 { 87 cpu0: cpu@0 {
88 compatible = "arm,cort 88 compatible = "arm,cortex-a55";
89 reg = <0>; 89 reg = <0>;
90 device_type = "cpu"; 90 device_type = "cpu";
91 #cooling-cells = <2>; 91 #cooling-cells = <2>;
92 next-level-cache = <&L 92 next-level-cache = <&L3_CA55>;
93 enable-method = "psci" 93 enable-method = "psci";
94 clocks = <&cpg CPG_COR 94 clocks = <&cpg CPG_CORE R9A07G054_CLK_I>;
95 operating-points-v2 = 95 operating-points-v2 = <&cluster0_opp>;
96 }; 96 };
97 97
98 cpu1: cpu@100 { 98 cpu1: cpu@100 {
99 compatible = "arm,cort 99 compatible = "arm,cortex-a55";
100 reg = <0x100>; 100 reg = <0x100>;
101 device_type = "cpu"; 101 device_type = "cpu";
102 next-level-cache = <&L 102 next-level-cache = <&L3_CA55>;
103 enable-method = "psci" 103 enable-method = "psci";
104 clocks = <&cpg CPG_COR 104 clocks = <&cpg CPG_CORE R9A07G054_CLK_I>;
105 operating-points-v2 = 105 operating-points-v2 = <&cluster0_opp>;
106 }; 106 };
107 107
108 L3_CA55: cache-controller-0 { 108 L3_CA55: cache-controller-0 {
109 compatible = "cache"; 109 compatible = "cache";
110 cache-unified; 110 cache-unified;
111 cache-size = <0x40000> 111 cache-size = <0x40000>;
112 cache-level = <3>; 112 cache-level = <3>;
113 }; 113 };
114 }; 114 };
115 115
116 gpu_opp_table: opp-table-1 { 116 gpu_opp_table: opp-table-1 {
117 compatible = "operating-points 117 compatible = "operating-points-v2";
118 118
119 opp-500000000 { 119 opp-500000000 {
120 opp-hz = /bits/ 64 <50 120 opp-hz = /bits/ 64 <500000000>;
121 opp-microvolt = <11000 121 opp-microvolt = <1100000>;
122 }; 122 };
123 123
124 opp-400000000 { 124 opp-400000000 {
125 opp-hz = /bits/ 64 <40 125 opp-hz = /bits/ 64 <400000000>;
126 opp-microvolt = <11000 126 opp-microvolt = <1100000>;
127 }; 127 };
128 128
129 opp-250000000 { 129 opp-250000000 {
130 opp-hz = /bits/ 64 <25 130 opp-hz = /bits/ 64 <250000000>;
131 opp-microvolt = <11000 131 opp-microvolt = <1100000>;
132 }; 132 };
133 133
134 opp-200000000 { 134 opp-200000000 {
135 opp-hz = /bits/ 64 <20 135 opp-hz = /bits/ 64 <200000000>;
136 opp-microvolt = <11000 136 opp-microvolt = <1100000>;
137 }; 137 };
138 138
139 opp-125000000 { 139 opp-125000000 {
140 opp-hz = /bits/ 64 <12 140 opp-hz = /bits/ 64 <125000000>;
141 opp-microvolt = <11000 141 opp-microvolt = <1100000>;
142 }; 142 };
143 143
144 opp-100000000 { 144 opp-100000000 {
145 opp-hz = /bits/ 64 <10 145 opp-hz = /bits/ 64 <100000000>;
146 opp-microvolt = <11000 146 opp-microvolt = <1100000>;
147 }; 147 };
148 148
149 opp-62500000 { 149 opp-62500000 {
150 opp-hz = /bits/ 64 <62 150 opp-hz = /bits/ 64 <62500000>;
151 opp-microvolt = <11000 151 opp-microvolt = <1100000>;
152 }; 152 };
153 153
154 opp-50000000 { 154 opp-50000000 {
155 opp-hz = /bits/ 64 <50 155 opp-hz = /bits/ 64 <50000000>;
156 opp-microvolt = <11000 156 opp-microvolt = <1100000>;
157 }; 157 };
158 }; 158 };
159 159
160 pmu { 160 pmu {
161 compatible = "arm,cortex-a55-p 161 compatible = "arm,cortex-a55-pmu";
162 interrupts-extended = <&gic GI 162 interrupts-extended = <&gic GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
163 }; 163 };
164 164
165 psci { 165 psci {
166 compatible = "arm,psci-1.0", " 166 compatible = "arm,psci-1.0", "arm,psci-0.2";
167 method = "smc"; 167 method = "smc";
168 }; 168 };
169 169
170 soc: soc { 170 soc: soc {
171 compatible = "simple-bus"; 171 compatible = "simple-bus";
172 interrupt-parent = <&gic>; 172 interrupt-parent = <&gic>;
173 #address-cells = <2>; 173 #address-cells = <2>;
174 #size-cells = <2>; 174 #size-cells = <2>;
175 ranges; 175 ranges;
176 176
177 mtu3: timer@10001200 { 177 mtu3: timer@10001200 {
178 compatible = "renesas, 178 compatible = "renesas,r9a07g054-mtu3",
179 "renesas, 179 "renesas,rz-mtu3";
180 reg = <0 0x10001200 0 180 reg = <0 0x10001200 0 0xb00>;
181 interrupts = <GIC_SPI 181 interrupts = <GIC_SPI 170 IRQ_TYPE_EDGE_RISING>,
182 <GIC_SPI 182 <GIC_SPI 171 IRQ_TYPE_EDGE_RISING>,
183 <GIC_SPI 183 <GIC_SPI 172 IRQ_TYPE_EDGE_RISING>,
184 <GIC_SPI 184 <GIC_SPI 173 IRQ_TYPE_EDGE_RISING>,
185 <GIC_SPI 185 <GIC_SPI 174 IRQ_TYPE_EDGE_RISING>,
186 <GIC_SPI 186 <GIC_SPI 175 IRQ_TYPE_EDGE_RISING>,
187 <GIC_SPI 187 <GIC_SPI 176 IRQ_TYPE_EDGE_RISING>,
188 <GIC_SPI 188 <GIC_SPI 177 IRQ_TYPE_EDGE_RISING>,
189 <GIC_SPI 189 <GIC_SPI 178 IRQ_TYPE_EDGE_RISING>,
190 <GIC_SPI 190 <GIC_SPI 179 IRQ_TYPE_EDGE_RISING>,
191 <GIC_SPI 191 <GIC_SPI 180 IRQ_TYPE_EDGE_RISING>,
192 <GIC_SPI 192 <GIC_SPI 181 IRQ_TYPE_EDGE_RISING>,
193 <GIC_SPI 193 <GIC_SPI 182 IRQ_TYPE_EDGE_RISING>,
194 <GIC_SPI 194 <GIC_SPI 183 IRQ_TYPE_EDGE_RISING>,
195 <GIC_SPI 195 <GIC_SPI 184 IRQ_TYPE_EDGE_RISING>,
196 <GIC_SPI 196 <GIC_SPI 185 IRQ_TYPE_EDGE_RISING>,
197 <GIC_SPI 197 <GIC_SPI 186 IRQ_TYPE_EDGE_RISING>,
198 <GIC_SPI 198 <GIC_SPI 187 IRQ_TYPE_EDGE_RISING>,
199 <GIC_SPI 199 <GIC_SPI 188 IRQ_TYPE_EDGE_RISING>,
200 <GIC_SPI 200 <GIC_SPI 189 IRQ_TYPE_EDGE_RISING>,
201 <GIC_SPI 201 <GIC_SPI 190 IRQ_TYPE_EDGE_RISING>,
202 <GIC_SPI 202 <GIC_SPI 191 IRQ_TYPE_EDGE_RISING>,
203 <GIC_SPI 203 <GIC_SPI 192 IRQ_TYPE_EDGE_RISING>,
204 <GIC_SPI 204 <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>,
205 <GIC_SPI 205 <GIC_SPI 194 IRQ_TYPE_EDGE_RISING>,
206 <GIC_SPI 206 <GIC_SPI 195 IRQ_TYPE_EDGE_RISING>,
207 <GIC_SPI 207 <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>,
208 <GIC_SPI 208 <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>,
209 <GIC_SPI 209 <GIC_SPI 198 IRQ_TYPE_EDGE_RISING>,
210 <GIC_SPI 210 <GIC_SPI 199 IRQ_TYPE_EDGE_RISING>,
211 <GIC_SPI 211 <GIC_SPI 200 IRQ_TYPE_EDGE_RISING>,
212 <GIC_SPI 212 <GIC_SPI 201 IRQ_TYPE_EDGE_RISING>,
213 <GIC_SPI 213 <GIC_SPI 202 IRQ_TYPE_EDGE_RISING>,
214 <GIC_SPI 214 <GIC_SPI 203 IRQ_TYPE_EDGE_RISING>,
215 <GIC_SPI 215 <GIC_SPI 204 IRQ_TYPE_EDGE_RISING>,
216 <GIC_SPI 216 <GIC_SPI 205 IRQ_TYPE_EDGE_RISING>,
217 <GIC_SPI 217 <GIC_SPI 206 IRQ_TYPE_EDGE_RISING>,
218 <GIC_SPI 218 <GIC_SPI 207 IRQ_TYPE_EDGE_RISING>,
219 <GIC_SPI 219 <GIC_SPI 208 IRQ_TYPE_EDGE_RISING>,
220 <GIC_SPI 220 <GIC_SPI 209 IRQ_TYPE_EDGE_RISING>,
221 <GIC_SPI 221 <GIC_SPI 210 IRQ_TYPE_EDGE_RISING>,
222 <GIC_SPI 222 <GIC_SPI 211 IRQ_TYPE_EDGE_RISING>,
223 <GIC_SPI 223 <GIC_SPI 212 IRQ_TYPE_EDGE_RISING>,
224 <GIC_SPI 224 <GIC_SPI 213 IRQ_TYPE_EDGE_RISING>;
225 interrupt-names = "tgi 225 interrupt-names = "tgia0", "tgib0", "tgic0", "tgid0",
226 "tci 226 "tciv0", "tgie0", "tgif0",
227 "tgi 227 "tgia1", "tgib1", "tciv1", "tciu1",
228 "tgi 228 "tgia2", "tgib2", "tciv2", "tciu2",
229 "tgi 229 "tgia3", "tgib3", "tgic3", "tgid3",
230 "tci 230 "tciv3",
231 "tgi 231 "tgia4", "tgib4", "tgic4", "tgid4",
232 "tci 232 "tciv4",
233 "tgi 233 "tgiu5", "tgiv5", "tgiw5",
234 "tgi 234 "tgia6", "tgib6", "tgic6", "tgid6",
235 "tci 235 "tciv6",
236 "tgi 236 "tgia7", "tgib7", "tgic7", "tgid7",
237 "tci 237 "tciv7",
238 "tgi 238 "tgia8", "tgib8", "tgic8", "tgid8",
239 "tci 239 "tciv8", "tciu8";
240 clocks = <&cpg CPG_MOD 240 clocks = <&cpg CPG_MOD R9A07G054_MTU_X_MCK_MTU3>;
241 power-domains = <&cpg> 241 power-domains = <&cpg>;
242 resets = <&cpg R9A07G0 242 resets = <&cpg R9A07G054_MTU_X_PRESET_MTU3>;
243 #pwm-cells = <2>; 243 #pwm-cells = <2>;
244 status = "disabled"; 244 status = "disabled";
245 }; 245 };
246 246
247 ssi0: ssi@10049c00 { 247 ssi0: ssi@10049c00 {
248 compatible = "renesas, 248 compatible = "renesas,r9a07g054-ssi",
249 "renesas, 249 "renesas,rz-ssi";
250 reg = <0 0x10049c00 0 250 reg = <0 0x10049c00 0 0x400>;
251 interrupts = <GIC_SPI 251 interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
252 <GIC_SPI 252 <GIC_SPI 327 IRQ_TYPE_EDGE_RISING>,
253 <GIC_SPI 253 <GIC_SPI 328 IRQ_TYPE_EDGE_RISING>;
254 interrupt-names = "int 254 interrupt-names = "int_req", "dma_rx", "dma_tx";
255 clocks = <&cpg CPG_MOD 255 clocks = <&cpg CPG_MOD R9A07G054_SSI0_PCLK2>,
256 <&cpg CPG_MOD 256 <&cpg CPG_MOD R9A07G054_SSI0_PCLK_SFR>,
257 <&audio_clk1> 257 <&audio_clk1>, <&audio_clk2>;
258 clock-names = "ssi", " 258 clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2";
259 resets = <&cpg R9A07G0 259 resets = <&cpg R9A07G054_SSI0_RST_M2_REG>;
260 dmas = <&dmac 0x2655>, 260 dmas = <&dmac 0x2655>, <&dmac 0x2656>;
261 dma-names = "tx", "rx" 261 dma-names = "tx", "rx";
262 power-domains = <&cpg> 262 power-domains = <&cpg>;
263 #sound-dai-cells = <0> 263 #sound-dai-cells = <0>;
264 status = "disabled"; 264 status = "disabled";
265 }; 265 };
266 266
267 ssi1: ssi@1004a000 { 267 ssi1: ssi@1004a000 {
268 compatible = "renesas, 268 compatible = "renesas,r9a07g054-ssi",
269 "renesas, 269 "renesas,rz-ssi";
270 reg = <0 0x1004a000 0 270 reg = <0 0x1004a000 0 0x400>;
271 interrupts = <GIC_SPI 271 interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
272 <GIC_SPI 272 <GIC_SPI 331 IRQ_TYPE_EDGE_RISING>,
273 <GIC_SPI 273 <GIC_SPI 332 IRQ_TYPE_EDGE_RISING>;
274 interrupt-names = "int 274 interrupt-names = "int_req", "dma_rx", "dma_tx";
275 clocks = <&cpg CPG_MOD 275 clocks = <&cpg CPG_MOD R9A07G054_SSI1_PCLK2>,
276 <&cpg CPG_MOD 276 <&cpg CPG_MOD R9A07G054_SSI1_PCLK_SFR>,
277 <&audio_clk1> 277 <&audio_clk1>, <&audio_clk2>;
278 clock-names = "ssi", " 278 clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2";
279 resets = <&cpg R9A07G0 279 resets = <&cpg R9A07G054_SSI1_RST_M2_REG>;
280 dmas = <&dmac 0x2659>, 280 dmas = <&dmac 0x2659>, <&dmac 0x265a>;
281 dma-names = "tx", "rx" 281 dma-names = "tx", "rx";
282 power-domains = <&cpg> 282 power-domains = <&cpg>;
283 #sound-dai-cells = <0> 283 #sound-dai-cells = <0>;
284 status = "disabled"; 284 status = "disabled";
285 }; 285 };
286 286
287 ssi2: ssi@1004a400 { 287 ssi2: ssi@1004a400 {
288 compatible = "renesas, 288 compatible = "renesas,r9a07g054-ssi",
289 "renesas, 289 "renesas,rz-ssi";
290 reg = <0 0x1004a400 0 290 reg = <0 0x1004a400 0 0x400>;
291 interrupts = <GIC_SPI 291 interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
292 <GIC_SPI 292 <GIC_SPI 337 IRQ_TYPE_EDGE_RISING>;
293 interrupt-names = "int 293 interrupt-names = "int_req", "dma_rt";
294 clocks = <&cpg CPG_MOD 294 clocks = <&cpg CPG_MOD R9A07G054_SSI2_PCLK2>,
295 <&cpg CPG_MOD 295 <&cpg CPG_MOD R9A07G054_SSI2_PCLK_SFR>,
296 <&audio_clk1> 296 <&audio_clk1>, <&audio_clk2>;
297 clock-names = "ssi", " 297 clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2";
298 resets = <&cpg R9A07G0 298 resets = <&cpg R9A07G054_SSI2_RST_M2_REG>;
299 dmas = <&dmac 0x265f>; 299 dmas = <&dmac 0x265f>;
300 dma-names = "rt"; 300 dma-names = "rt";
301 power-domains = <&cpg> 301 power-domains = <&cpg>;
302 #sound-dai-cells = <0> 302 #sound-dai-cells = <0>;
303 status = "disabled"; 303 status = "disabled";
304 }; 304 };
305 305
306 ssi3: ssi@1004a800 { 306 ssi3: ssi@1004a800 {
307 compatible = "renesas, 307 compatible = "renesas,r9a07g054-ssi",
308 "renesas, 308 "renesas,rz-ssi";
309 reg = <0 0x1004a800 0 309 reg = <0 0x1004a800 0 0x400>;
310 interrupts = <GIC_SPI 310 interrupts = <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
311 <GIC_SPI 311 <GIC_SPI 339 IRQ_TYPE_EDGE_RISING>,
312 <GIC_SPI 312 <GIC_SPI 340 IRQ_TYPE_EDGE_RISING>;
313 interrupt-names = "int 313 interrupt-names = "int_req", "dma_rx", "dma_tx";
314 clocks = <&cpg CPG_MOD 314 clocks = <&cpg CPG_MOD R9A07G054_SSI3_PCLK2>,
315 <&cpg CPG_MOD 315 <&cpg CPG_MOD R9A07G054_SSI3_PCLK_SFR>,
316 <&audio_clk1> 316 <&audio_clk1>, <&audio_clk2>;
317 clock-names = "ssi", " 317 clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2";
318 resets = <&cpg R9A07G0 318 resets = <&cpg R9A07G054_SSI3_RST_M2_REG>;
319 dmas = <&dmac 0x2661>, 319 dmas = <&dmac 0x2661>, <&dmac 0x2662>;
320 dma-names = "tx", "rx" 320 dma-names = "tx", "rx";
321 power-domains = <&cpg> 321 power-domains = <&cpg>;
322 #sound-dai-cells = <0> 322 #sound-dai-cells = <0>;
323 status = "disabled"; 323 status = "disabled";
324 }; 324 };
325 325
326 spi0: spi@1004ac00 { 326 spi0: spi@1004ac00 {
327 compatible = "renesas, 327 compatible = "renesas,r9a07g054-rspi", "renesas,rspi-rz";
328 reg = <0 0x1004ac00 0 328 reg = <0 0x1004ac00 0 0x400>;
329 interrupts = <GIC_SPI 329 interrupts = <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>,
330 <GIC_SPI 330 <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>,
331 <GIC_SPI 331 <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>;
332 interrupt-names = "err 332 interrupt-names = "error", "rx", "tx";
333 clocks = <&cpg CPG_MOD 333 clocks = <&cpg CPG_MOD R9A07G054_RSPI0_CLKB>;
334 resets = <&cpg R9A07G0 334 resets = <&cpg R9A07G054_RSPI0_RST>;
335 dmas = <&dmac 0x2e95>, 335 dmas = <&dmac 0x2e95>, <&dmac 0x2e96>;
336 dma-names = "tx", "rx" 336 dma-names = "tx", "rx";
337 power-domains = <&cpg> 337 power-domains = <&cpg>;
338 num-cs = <1>; 338 num-cs = <1>;
339 #address-cells = <1>; 339 #address-cells = <1>;
340 #size-cells = <0>; 340 #size-cells = <0>;
341 status = "disabled"; 341 status = "disabled";
342 }; 342 };
343 343
344 spi1: spi@1004b000 { 344 spi1: spi@1004b000 {
345 compatible = "renesas, 345 compatible = "renesas,r9a07g054-rspi", "renesas,rspi-rz";
346 reg = <0 0x1004b000 0 346 reg = <0 0x1004b000 0 0x400>;
347 interrupts = <GIC_SPI 347 interrupts = <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
348 <GIC_SPI 348 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
349 <GIC_SPI 349 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>;
350 interrupt-names = "err 350 interrupt-names = "error", "rx", "tx";
351 clocks = <&cpg CPG_MOD 351 clocks = <&cpg CPG_MOD R9A07G054_RSPI1_CLKB>;
352 resets = <&cpg R9A07G0 352 resets = <&cpg R9A07G054_RSPI1_RST>;
353 dmas = <&dmac 0x2e99>, 353 dmas = <&dmac 0x2e99>, <&dmac 0x2e9a>;
354 dma-names = "tx", "rx" 354 dma-names = "tx", "rx";
355 power-domains = <&cpg> 355 power-domains = <&cpg>;
356 num-cs = <1>; 356 num-cs = <1>;
357 #address-cells = <1>; 357 #address-cells = <1>;
358 #size-cells = <0>; 358 #size-cells = <0>;
359 status = "disabled"; 359 status = "disabled";
360 }; 360 };
361 361
362 spi2: spi@1004b400 { 362 spi2: spi@1004b400 {
363 compatible = "renesas, 363 compatible = "renesas,r9a07g054-rspi", "renesas,rspi-rz";
364 reg = <0 0x1004b400 0 364 reg = <0 0x1004b400 0 0x400>;
365 interrupts = <GIC_SPI 365 interrupts = <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
366 <GIC_SPI 366 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
367 <GIC_SPI 367 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>;
368 interrupt-names = "err 368 interrupt-names = "error", "rx", "tx";
369 clocks = <&cpg CPG_MOD 369 clocks = <&cpg CPG_MOD R9A07G054_RSPI2_CLKB>;
370 resets = <&cpg R9A07G0 370 resets = <&cpg R9A07G054_RSPI2_RST>;
371 dmas = <&dmac 0x2e9d>, 371 dmas = <&dmac 0x2e9d>, <&dmac 0x2e9e>;
372 dma-names = "tx", "rx" 372 dma-names = "tx", "rx";
373 power-domains = <&cpg> 373 power-domains = <&cpg>;
374 num-cs = <1>; 374 num-cs = <1>;
375 #address-cells = <1>; 375 #address-cells = <1>;
376 #size-cells = <0>; 376 #size-cells = <0>;
377 status = "disabled"; 377 status = "disabled";
378 }; 378 };
379 379
380 scif0: serial@1004b800 { 380 scif0: serial@1004b800 {
381 compatible = "renesas, 381 compatible = "renesas,scif-r9a07g054",
382 "renesas, 382 "renesas,scif-r9a07g044";
383 reg = <0 0x1004b800 0 383 reg = <0 0x1004b800 0 0x400>;
384 interrupts = <GIC_SPI 384 interrupts = <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>,
385 <GIC_SPI 385 <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>,
386 <GIC_SPI 386 <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>,
387 <GIC_SPI 387 <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>,
388 <GIC_SPI 388 <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>,
389 <GIC_SPI 389 <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>;
390 interrupt-names = "eri 390 interrupt-names = "eri", "rxi", "txi",
391 "bri 391 "bri", "dri", "tei";
392 clocks = <&cpg CPG_MOD 392 clocks = <&cpg CPG_MOD R9A07G054_SCIF0_CLK_PCK>;
393 clock-names = "fck"; 393 clock-names = "fck";
394 power-domains = <&cpg> 394 power-domains = <&cpg>;
395 resets = <&cpg R9A07G0 395 resets = <&cpg R9A07G054_SCIF0_RST_SYSTEM_N>;
396 status = "disabled"; 396 status = "disabled";
397 }; 397 };
398 398
399 scif1: serial@1004bc00 { 399 scif1: serial@1004bc00 {
400 compatible = "renesas, 400 compatible = "renesas,scif-r9a07g054",
401 "renesas, 401 "renesas,scif-r9a07g044";
402 reg = <0 0x1004bc00 0 402 reg = <0 0x1004bc00 0 0x400>;
403 interrupts = <GIC_SPI 403 interrupts = <GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>,
404 <GIC_SPI 404 <GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>,
405 <GIC_SPI 405 <GIC_SPI 388 IRQ_TYPE_LEVEL_HIGH>,
406 <GIC_SPI 406 <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>,
407 <GIC_SPI 407 <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>,
408 <GIC_SPI 408 <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>;
409 interrupt-names = "eri 409 interrupt-names = "eri", "rxi", "txi",
410 "bri 410 "bri", "dri", "tei";
411 clocks = <&cpg CPG_MOD 411 clocks = <&cpg CPG_MOD R9A07G054_SCIF1_CLK_PCK>;
412 clock-names = "fck"; 412 clock-names = "fck";
413 power-domains = <&cpg> 413 power-domains = <&cpg>;
414 resets = <&cpg R9A07G0 414 resets = <&cpg R9A07G054_SCIF1_RST_SYSTEM_N>;
415 status = "disabled"; 415 status = "disabled";
416 }; 416 };
417 417
418 scif2: serial@1004c000 { 418 scif2: serial@1004c000 {
419 compatible = "renesas, 419 compatible = "renesas,scif-r9a07g054",
420 "renesas, 420 "renesas,scif-r9a07g044";
421 reg = <0 0x1004c000 0 421 reg = <0 0x1004c000 0 0x400>;
422 interrupts = <GIC_SPI 422 interrupts = <GIC_SPI 390 IRQ_TYPE_LEVEL_HIGH>,
423 <GIC_SPI 423 <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH>,
424 <GIC_SPI 424 <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>,
425 <GIC_SPI 425 <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH>,
426 <GIC_SPI 426 <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>,
427 <GIC_SPI 427 <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>;
428 interrupt-names = "eri 428 interrupt-names = "eri", "rxi", "txi",
429 "bri 429 "bri", "dri", "tei";
430 clocks = <&cpg CPG_MOD 430 clocks = <&cpg CPG_MOD R9A07G054_SCIF2_CLK_PCK>;
431 clock-names = "fck"; 431 clock-names = "fck";
432 power-domains = <&cpg> 432 power-domains = <&cpg>;
433 resets = <&cpg R9A07G0 433 resets = <&cpg R9A07G054_SCIF2_RST_SYSTEM_N>;
434 status = "disabled"; 434 status = "disabled";
435 }; 435 };
436 436
437 scif3: serial@1004c400 { 437 scif3: serial@1004c400 {
438 compatible = "renesas, 438 compatible = "renesas,scif-r9a07g054",
439 "renesas, 439 "renesas,scif-r9a07g044";
440 reg = <0 0x1004c400 0 440 reg = <0 0x1004c400 0 0x400>;
441 interrupts = <GIC_SPI 441 interrupts = <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
442 <GIC_SPI 442 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
443 <GIC_SPI 443 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
444 <GIC_SPI 444 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
445 <GIC_SPI 445 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
446 <GIC_SPI 446 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>;
447 interrupt-names = "eri 447 interrupt-names = "eri", "rxi", "txi",
448 "bri 448 "bri", "dri", "tei";
449 clocks = <&cpg CPG_MOD 449 clocks = <&cpg CPG_MOD R9A07G054_SCIF3_CLK_PCK>;
450 clock-names = "fck"; 450 clock-names = "fck";
451 power-domains = <&cpg> 451 power-domains = <&cpg>;
452 resets = <&cpg R9A07G0 452 resets = <&cpg R9A07G054_SCIF3_RST_SYSTEM_N>;
453 status = "disabled"; 453 status = "disabled";
454 }; 454 };
455 455
456 scif4: serial@1004c800 { 456 scif4: serial@1004c800 {
457 compatible = "renesas, 457 compatible = "renesas,scif-r9a07g054",
458 "renesas, 458 "renesas,scif-r9a07g044";
459 reg = <0 0x1004c800 0 459 reg = <0 0x1004c800 0 0x400>;
460 interrupts = <GIC_SPI 460 interrupts = <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
461 <GIC_SPI 461 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
462 <GIC_SPI 462 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
463 <GIC_SPI 463 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
464 <GIC_SPI 464 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
465 <GIC_SPI 465 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>;
466 interrupt-names = "eri 466 interrupt-names = "eri", "rxi", "txi",
467 "bri 467 "bri", "dri", "tei";
468 clocks = <&cpg CPG_MOD 468 clocks = <&cpg CPG_MOD R9A07G054_SCIF4_CLK_PCK>;
469 clock-names = "fck"; 469 clock-names = "fck";
470 power-domains = <&cpg> 470 power-domains = <&cpg>;
471 resets = <&cpg R9A07G0 471 resets = <&cpg R9A07G054_SCIF4_RST_SYSTEM_N>;
472 status = "disabled"; 472 status = "disabled";
473 }; 473 };
474 474
475 sci0: serial@1004d000 { 475 sci0: serial@1004d000 {
476 compatible = "renesas, 476 compatible = "renesas,r9a07g054-sci", "renesas,sci";
477 reg = <0 0x1004d000 0 477 reg = <0 0x1004d000 0 0x400>;
478 interrupts = <GIC_SPI 478 interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
479 <GIC_SPI 479 <GIC_SPI 406 IRQ_TYPE_EDGE_RISING>,
480 <GIC_SPI 480 <GIC_SPI 407 IRQ_TYPE_EDGE_RISING>,
481 <GIC_SPI 481 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>;
482 interrupt-names = "eri 482 interrupt-names = "eri", "rxi", "txi", "tei";
483 clocks = <&cpg CPG_MOD 483 clocks = <&cpg CPG_MOD R9A07G054_SCI0_CLKP>;
484 clock-names = "fck"; 484 clock-names = "fck";
485 power-domains = <&cpg> 485 power-domains = <&cpg>;
486 resets = <&cpg R9A07G0 486 resets = <&cpg R9A07G054_SCI0_RST>;
487 status = "disabled"; 487 status = "disabled";
488 }; 488 };
489 489
490 sci1: serial@1004d400 { 490 sci1: serial@1004d400 {
491 compatible = "renesas, 491 compatible = "renesas,r9a07g054-sci", "renesas,sci";
492 reg = <0 0x1004d400 0 492 reg = <0 0x1004d400 0 0x400>;
493 interrupts = <GIC_SPI 493 interrupts = <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
494 <GIC_SPI 494 <GIC_SPI 410 IRQ_TYPE_EDGE_RISING>,
495 <GIC_SPI 495 <GIC_SPI 411 IRQ_TYPE_EDGE_RISING>,
496 <GIC_SPI 496 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>;
497 interrupt-names = "eri 497 interrupt-names = "eri", "rxi", "txi", "tei";
498 clocks = <&cpg CPG_MOD 498 clocks = <&cpg CPG_MOD R9A07G054_SCI1_CLKP>;
499 clock-names = "fck"; 499 clock-names = "fck";
500 power-domains = <&cpg> 500 power-domains = <&cpg>;
501 resets = <&cpg R9A07G0 501 resets = <&cpg R9A07G054_SCI1_RST>;
502 status = "disabled"; 502 status = "disabled";
503 }; 503 };
504 504
505 canfd: can@10050000 { 505 canfd: can@10050000 {
506 compatible = "renesas, 506 compatible = "renesas,r9a07g054-canfd", "renesas,rzg2l-canfd";
507 reg = <0 0x10050000 0 507 reg = <0 0x10050000 0 0x8000>;
508 interrupts = <GIC_SPI 508 interrupts = <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>,
509 <GIC_SPI 509 <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>,
510 <GIC_SPI 510 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
511 <GIC_SPI 511 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
512 <GIC_SPI 512 <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>,
513 <GIC_SPI 513 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
514 <GIC_SPI 514 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
515 <GIC_SPI 515 <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>;
516 interrupt-names = "g_e 516 interrupt-names = "g_err", "g_recc",
517 "ch0 517 "ch0_err", "ch0_rec", "ch0_trx",
518 "ch1 518 "ch1_err", "ch1_rec", "ch1_trx";
519 clocks = <&cpg CPG_MOD 519 clocks = <&cpg CPG_MOD R9A07G054_CANFD_PCLK>,
520 <&cpg CPG_COR 520 <&cpg CPG_CORE R9A07G054_CLK_P0_DIV2>,
521 <&can_clk>; 521 <&can_clk>;
522 clock-names = "fck", " 522 clock-names = "fck", "canfd", "can_clk";
523 assigned-clocks = <&cp 523 assigned-clocks = <&cpg CPG_CORE R9A07G054_CLK_P0_DIV2>;
524 assigned-clock-rates = 524 assigned-clock-rates = <50000000>;
525 resets = <&cpg R9A07G0 525 resets = <&cpg R9A07G054_CANFD_RSTP_N>,
526 <&cpg R9A07G0 526 <&cpg R9A07G054_CANFD_RSTC_N>;
527 reset-names = "rstp_n" 527 reset-names = "rstp_n", "rstc_n";
528 power-domains = <&cpg> 528 power-domains = <&cpg>;
529 status = "disabled"; 529 status = "disabled";
530 530
531 channel0 { 531 channel0 {
532 status = "disa 532 status = "disabled";
533 }; 533 };
534 channel1 { 534 channel1 {
535 status = "disa 535 status = "disabled";
536 }; 536 };
537 }; 537 };
538 538
539 i2c0: i2c@10058000 { 539 i2c0: i2c@10058000 {
540 #address-cells = <1>; 540 #address-cells = <1>;
541 #size-cells = <0>; 541 #size-cells = <0>;
542 compatible = "renesas, 542 compatible = "renesas,riic-r9a07g054", "renesas,riic-rz";
543 reg = <0 0x10058000 0 543 reg = <0 0x10058000 0 0x400>;
544 interrupts = <GIC_SPI 544 interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>,
545 <GIC_SPI 545 <GIC_SPI 348 IRQ_TYPE_EDGE_RISING>,
546 <GIC_SPI 546 <GIC_SPI 349 IRQ_TYPE_EDGE_RISING>,
547 <GIC_SPI 547 <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>,
548 <GIC_SPI 548 <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>,
549 <GIC_SPI 549 <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>,
550 <GIC_SPI 550 <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>,
551 <GIC_SPI 551 <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
552 interrupt-names = "tei 552 interrupt-names = "tei", "ri", "ti", "spi", "sti",
553 "nak 553 "naki", "ali", "tmoi";
554 clocks = <&cpg CPG_MOD 554 clocks = <&cpg CPG_MOD R9A07G054_I2C0_PCLK>;
555 clock-frequency = <100 555 clock-frequency = <100000>;
556 resets = <&cpg R9A07G0 556 resets = <&cpg R9A07G054_I2C0_MRST>;
557 power-domains = <&cpg> 557 power-domains = <&cpg>;
558 status = "disabled"; 558 status = "disabled";
559 }; 559 };
560 560
561 i2c1: i2c@10058400 { 561 i2c1: i2c@10058400 {
562 #address-cells = <1>; 562 #address-cells = <1>;
563 #size-cells = <0>; 563 #size-cells = <0>;
564 compatible = "renesas, 564 compatible = "renesas,riic-r9a07g054", "renesas,riic-rz";
565 reg = <0 0x10058400 0 565 reg = <0 0x10058400 0 0x400>;
566 interrupts = <GIC_SPI 566 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>,
567 <GIC_SPI 567 <GIC_SPI 356 IRQ_TYPE_EDGE_RISING>,
568 <GIC_SPI 568 <GIC_SPI 357 IRQ_TYPE_EDGE_RISING>,
569 <GIC_SPI 569 <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>,
570 <GIC_SPI 570 <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>,
571 <GIC_SPI 571 <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>,
572 <GIC_SPI 572 <GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH>,
573 <GIC_SPI 573 <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>;
574 interrupt-names = "tei 574 interrupt-names = "tei", "ri", "ti", "spi", "sti",
575 "nak 575 "naki", "ali", "tmoi";
576 clocks = <&cpg CPG_MOD 576 clocks = <&cpg CPG_MOD R9A07G054_I2C1_PCLK>;
577 clock-frequency = <100 577 clock-frequency = <100000>;
578 resets = <&cpg R9A07G0 578 resets = <&cpg R9A07G054_I2C1_MRST>;
579 power-domains = <&cpg> 579 power-domains = <&cpg>;
580 status = "disabled"; 580 status = "disabled";
581 }; 581 };
582 582
583 i2c2: i2c@10058800 { 583 i2c2: i2c@10058800 {
584 #address-cells = <1>; 584 #address-cells = <1>;
585 #size-cells = <0>; 585 #size-cells = <0>;
586 compatible = "renesas, 586 compatible = "renesas,riic-r9a07g054", "renesas,riic-rz";
587 reg = <0 0x10058800 0 587 reg = <0 0x10058800 0 0x400>;
588 interrupts = <GIC_SPI 588 interrupts = <GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>,
589 <GIC_SPI 589 <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>,
590 <GIC_SPI 590 <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>,
591 <GIC_SPI 591 <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>,
592 <GIC_SPI 592 <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>,
593 <GIC_SPI 593 <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>,
594 <GIC_SPI 594 <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>,
595 <GIC_SPI 595 <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
596 interrupt-names = "tei 596 interrupt-names = "tei", "ri", "ti", "spi", "sti",
597 "nak 597 "naki", "ali", "tmoi";
598 clocks = <&cpg CPG_MOD 598 clocks = <&cpg CPG_MOD R9A07G054_I2C2_PCLK>;
599 clock-frequency = <100 599 clock-frequency = <100000>;
600 resets = <&cpg R9A07G0 600 resets = <&cpg R9A07G054_I2C2_MRST>;
601 power-domains = <&cpg> 601 power-domains = <&cpg>;
602 status = "disabled"; 602 status = "disabled";
603 }; 603 };
604 604
605 i2c3: i2c@10058c00 { 605 i2c3: i2c@10058c00 {
606 #address-cells = <1>; 606 #address-cells = <1>;
607 #size-cells = <0>; 607 #size-cells = <0>;
608 compatible = "renesas, 608 compatible = "renesas,riic-r9a07g054", "renesas,riic-rz";
609 reg = <0 0x10058c00 0 609 reg = <0 0x10058c00 0 0x400>;
610 interrupts = <GIC_SPI 610 interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>,
611 <GIC_SPI 611 <GIC_SPI 372 IRQ_TYPE_EDGE_RISING>,
612 <GIC_SPI 612 <GIC_SPI 373 IRQ_TYPE_EDGE_RISING>,
613 <GIC_SPI 613 <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>,
614 <GIC_SPI 614 <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>,
615 <GIC_SPI 615 <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>,
616 <GIC_SPI 616 <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>,
617 <GIC_SPI 617 <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
618 interrupt-names = "tei 618 interrupt-names = "tei", "ri", "ti", "spi", "sti",
619 "nak 619 "naki", "ali", "tmoi";
620 clocks = <&cpg CPG_MOD 620 clocks = <&cpg CPG_MOD R9A07G054_I2C3_PCLK>;
621 clock-frequency = <100 621 clock-frequency = <100000>;
622 resets = <&cpg R9A07G0 622 resets = <&cpg R9A07G054_I2C3_MRST>;
623 power-domains = <&cpg> 623 power-domains = <&cpg>;
624 status = "disabled"; 624 status = "disabled";
625 }; 625 };
626 626
627 adc: adc@10059000 { 627 adc: adc@10059000 {
628 compatible = "renesas, 628 compatible = "renesas,r9a07g054-adc", "renesas,rzg2l-adc";
629 reg = <0 0x10059000 0 629 reg = <0 0x10059000 0 0x400>;
630 interrupts = <GIC_SPI 630 interrupts = <GIC_SPI 347 IRQ_TYPE_EDGE_RISING>;
631 clocks = <&cpg CPG_MOD 631 clocks = <&cpg CPG_MOD R9A07G054_ADC_ADCLK>,
632 <&cpg CPG_MOD 632 <&cpg CPG_MOD R9A07G054_ADC_PCLK>;
633 clock-names = "adclk", 633 clock-names = "adclk", "pclk";
634 resets = <&cpg R9A07G0 634 resets = <&cpg R9A07G054_ADC_PRESETN>,
635 <&cpg R9A07G0 635 <&cpg R9A07G054_ADC_ADRST_N>;
636 reset-names = "presetn 636 reset-names = "presetn", "adrst-n";
637 power-domains = <&cpg> 637 power-domains = <&cpg>;
638 status = "disabled"; 638 status = "disabled";
639 639
640 #address-cells = <1>; 640 #address-cells = <1>;
641 #size-cells = <0>; 641 #size-cells = <0>;
642 642
643 channel@0 { 643 channel@0 {
644 reg = <0>; 644 reg = <0>;
645 }; 645 };
646 channel@1 { 646 channel@1 {
647 reg = <1>; 647 reg = <1>;
648 }; 648 };
649 channel@2 { 649 channel@2 {
650 reg = <2>; 650 reg = <2>;
651 }; 651 };
652 channel@3 { 652 channel@3 {
653 reg = <3>; 653 reg = <3>;
654 }; 654 };
655 channel@4 { 655 channel@4 {
656 reg = <4>; 656 reg = <4>;
657 }; 657 };
658 channel@5 { 658 channel@5 {
659 reg = <5>; 659 reg = <5>;
660 }; 660 };
661 channel@6 { 661 channel@6 {
662 reg = <6>; 662 reg = <6>;
663 }; 663 };
664 channel@7 { 664 channel@7 {
665 reg = <7>; 665 reg = <7>;
666 }; 666 };
667 }; 667 };
668 668
669 tsu: thermal@10059400 { 669 tsu: thermal@10059400 {
670 compatible = "renesas, 670 compatible = "renesas,r9a07g054-tsu",
671 "renesas, 671 "renesas,rzg2l-tsu";
672 reg = <0 0x10059400 0 672 reg = <0 0x10059400 0 0x400>;
673 clocks = <&cpg CPG_MOD 673 clocks = <&cpg CPG_MOD R9A07G054_TSU_PCLK>;
674 resets = <&cpg R9A07G0 674 resets = <&cpg R9A07G054_TSU_PRESETN>;
675 power-domains = <&cpg> 675 power-domains = <&cpg>;
676 #thermal-sensor-cells 676 #thermal-sensor-cells = <1>;
677 }; 677 };
678 678
679 sbc: spi@10060000 { 679 sbc: spi@10060000 {
680 compatible = "renesas, 680 compatible = "renesas,r9a07g054-rpc-if",
681 "renesas, 681 "renesas,rzg2l-rpc-if";
682 reg = <0 0x10060000 0 682 reg = <0 0x10060000 0 0x10000>,
683 <0 0x20000000 0 683 <0 0x20000000 0 0x10000000>,
684 <0 0x10070000 0 684 <0 0x10070000 0 0x10000>;
685 reg-names = "regs", "d 685 reg-names = "regs", "dirmap", "wbuf";
686 interrupts = <GIC_SPI 686 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
687 clocks = <&cpg CPG_MOD 687 clocks = <&cpg CPG_MOD R9A07G054_SPI_CLK2>,
688 <&cpg CPG_MOD 688 <&cpg CPG_MOD R9A07G054_SPI_CLK>;
689 resets = <&cpg R9A07G0 689 resets = <&cpg R9A07G054_SPI_RST>;
690 power-domains = <&cpg> 690 power-domains = <&cpg>;
691 #address-cells = <1>; 691 #address-cells = <1>;
692 #size-cells = <0>; 692 #size-cells = <0>;
693 status = "disabled"; 693 status = "disabled";
694 }; 694 };
695 695
696 cru: video@10830000 { 696 cru: video@10830000 {
697 compatible = "renesas, 697 compatible = "renesas,r9a07g054-cru", "renesas,rzg2l-cru";
698 reg = <0 0x10830000 0 698 reg = <0 0x10830000 0 0x400>;
699 clocks = <&cpg CPG_MOD 699 clocks = <&cpg CPG_MOD R9A07G054_CRU_VCLK>,
700 <&cpg CPG_MOD 700 <&cpg CPG_MOD R9A07G054_CRU_PCLK>,
701 <&cpg CPG_MOD 701 <&cpg CPG_MOD R9A07G054_CRU_ACLK>;
702 clock-names = "video", 702 clock-names = "video", "apb", "axi";
703 interrupts = <GIC_SPI 703 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
704 <GIC_SPI 704 <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
705 <GIC_SPI 705 <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
706 interrupt-names = "ima 706 interrupt-names = "image_conv", "image_conv_err", "axi_mst_err";
707 resets = <&cpg R9A07G0 707 resets = <&cpg R9A07G054_CRU_PRESETN>,
708 <&cpg R9A07G0 708 <&cpg R9A07G054_CRU_ARESETN>;
709 reset-names = "presetn 709 reset-names = "presetn", "aresetn";
710 power-domains = <&cpg> 710 power-domains = <&cpg>;
711 status = "disabled"; 711 status = "disabled";
712 712
713 ports { 713 ports {
714 #address-cells 714 #address-cells = <1>;
715 #size-cells = 715 #size-cells = <0>;
716 716
717 port@0 { 717 port@0 {
718 #addre 718 #address-cells = <1>;
719 #size- 719 #size-cells = <0>;
720 720
721 reg = 721 reg = <0>;
722 crupar 722 cruparallel: endpoint@0 {
723 723 reg = <0>;
724 }; 724 };
725 }; 725 };
726 726
727 port@1 { 727 port@1 {
728 #addre 728 #address-cells = <1>;
729 #size- 729 #size-cells = <0>;
730 730
731 reg = 731 reg = <1>;
732 crucsi 732 crucsi2: endpoint@0 {
733 733 reg = <0>;
734 734 remote-endpoint = <&csi2cru>;
735 }; 735 };
736 }; 736 };
737 }; 737 };
738 }; 738 };
739 739
740 csi2: csi2@10830400 { 740 csi2: csi2@10830400 {
741 compatible = "renesas, 741 compatible = "renesas,r9a07g054-csi2", "renesas,rzg2l-csi2";
742 reg = <0 0x10830400 0 742 reg = <0 0x10830400 0 0xfc00>;
743 interrupts = <GIC_SPI 743 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
744 clocks = <&cpg CPG_MOD 744 clocks = <&cpg CPG_MOD R9A07G054_CRU_SYSCLK>,
745 <&cpg CPG_MOD 745 <&cpg CPG_MOD R9A07G054_CRU_VCLK>,
746 <&cpg CPG_MOD 746 <&cpg CPG_MOD R9A07G054_CRU_PCLK>;
747 clock-names = "system" 747 clock-names = "system", "video", "apb";
748 resets = <&cpg R9A07G0 748 resets = <&cpg R9A07G054_CRU_PRESETN>,
749 <&cpg R9A07G0 749 <&cpg R9A07G054_CRU_CMN_RSTB>;
750 reset-names = "presetn 750 reset-names = "presetn", "cmn-rstb";
751 power-domains = <&cpg> 751 power-domains = <&cpg>;
752 status = "disabled"; 752 status = "disabled";
753 753
754 ports { 754 ports {
755 #address-cells 755 #address-cells = <1>;
756 #size-cells = 756 #size-cells = <0>;
757 757
758 port@0 { 758 port@0 {
759 reg = 759 reg = <0>;
760 }; 760 };
761 761
762 port@1 { 762 port@1 {
763 #addre 763 #address-cells = <1>;
764 #size- 764 #size-cells = <0>;
765 reg = 765 reg = <1>;
766 766
767 csi2cr 767 csi2cru: endpoint@0 {
768 768 reg = <0>;
769 769 remote-endpoint = <&crucsi2>;
770 }; 770 };
771 }; 771 };
772 }; 772 };
773 }; 773 };
774 774
775 dsi: dsi@10850000 { 775 dsi: dsi@10850000 {
776 compatible = "renesas, 776 compatible = "renesas,r9a07g054-mipi-dsi",
777 "renesas, 777 "renesas,rzg2l-mipi-dsi";
778 reg = <0 0x10850000 0 778 reg = <0 0x10850000 0 0x20000>;
779 interrupts = <GIC_SPI 779 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
780 <GIC_SPI 780 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
781 <GIC_SPI 781 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
782 <GIC_SPI 782 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
783 <GIC_SPI 783 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
784 <GIC_SPI 784 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
785 <GIC_SPI 785 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
786 interrupt-names = "seq 786 interrupt-names = "seq0", "seq1", "vin1", "rcv",
787 "fer 787 "ferr", "ppi", "debug";
788 clocks = <&cpg CPG_MOD 788 clocks = <&cpg CPG_MOD R9A07G054_MIPI_DSI_PLLCLK>,
789 <&cpg CPG_MOD 789 <&cpg CPG_MOD R9A07G054_MIPI_DSI_SYSCLK>,
790 <&cpg CPG_MOD 790 <&cpg CPG_MOD R9A07G054_MIPI_DSI_ACLK>,
791 <&cpg CPG_MOD 791 <&cpg CPG_MOD R9A07G054_MIPI_DSI_PCLK>,
792 <&cpg CPG_MOD 792 <&cpg CPG_MOD R9A07G054_MIPI_DSI_VCLK>,
793 <&cpg CPG_MOD 793 <&cpg CPG_MOD R9A07G054_MIPI_DSI_LPCLK>;
794 clock-names = "pllclk" 794 clock-names = "pllclk", "sysclk", "aclk", "pclk", "vclk", "lpclk";
795 resets = <&cpg R9A07G0 795 resets = <&cpg R9A07G054_MIPI_DSI_CMN_RSTB>,
796 <&cpg R9A07G0 796 <&cpg R9A07G054_MIPI_DSI_ARESET_N>,
797 <&cpg R9A07G0 797 <&cpg R9A07G054_MIPI_DSI_PRESET_N>;
798 reset-names = "rst", " 798 reset-names = "rst", "arst", "prst";
799 power-domains = <&cpg> 799 power-domains = <&cpg>;
800 status = "disabled"; 800 status = "disabled";
801 <<
802 ports { <<
803 #address-cells <<
804 #size-cells = <<
805 <<
806 port@0 { <<
807 reg = <<
808 dsi0_i <<
809 <<
810 }; <<
811 }; <<
812 <<
813 port@1 { <<
814 reg = <<
815 }; <<
816 }; <<
817 }; 801 };
818 802
819 vspd: vsp@10870000 { 803 vspd: vsp@10870000 {
820 compatible = "renesas, 804 compatible = "renesas,r9a07g054-vsp2",
821 "renesas, 805 "renesas,r9a07g044-vsp2";
822 reg = <0 0x10870000 0 806 reg = <0 0x10870000 0 0x10000>;
823 interrupts = <GIC_SPI 807 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
824 clocks = <&cpg CPG_MOD 808 clocks = <&cpg CPG_MOD R9A07G054_LCDC_CLK_A>,
825 <&cpg CPG_MOD 809 <&cpg CPG_MOD R9A07G054_LCDC_CLK_P>,
826 <&cpg CPG_MOD 810 <&cpg CPG_MOD R9A07G054_LCDC_CLK_D>;
827 clock-names = "aclk", 811 clock-names = "aclk", "pclk", "vclk";
828 power-domains = <&cpg> 812 power-domains = <&cpg>;
829 resets = <&cpg R9A07G0 813 resets = <&cpg R9A07G054_LCDC_RESET_N>;
830 renesas,fcp = <&fcpvd> 814 renesas,fcp = <&fcpvd>;
831 }; 815 };
832 816
833 fcpvd: fcp@10880000 { 817 fcpvd: fcp@10880000 {
834 compatible = "renesas, 818 compatible = "renesas,r9a07g054-fcpvd",
835 "renesas, 819 "renesas,fcpv";
836 reg = <0 0x10880000 0 820 reg = <0 0x10880000 0 0x10000>;
837 clocks = <&cpg CPG_MOD 821 clocks = <&cpg CPG_MOD R9A07G054_LCDC_CLK_A>,
838 <&cpg CPG_MOD 822 <&cpg CPG_MOD R9A07G054_LCDC_CLK_P>,
839 <&cpg CPG_MOD 823 <&cpg CPG_MOD R9A07G054_LCDC_CLK_D>;
840 clock-names = "aclk", 824 clock-names = "aclk", "pclk", "vclk";
841 power-domains = <&cpg> 825 power-domains = <&cpg>;
842 resets = <&cpg R9A07G0 826 resets = <&cpg R9A07G054_LCDC_RESET_N>;
843 }; 827 };
844 828
845 du: display@10890000 { <<
846 compatible = "renesas, <<
847 "renesas, <<
848 reg = <0 0x10890000 0 <<
849 interrupts = <GIC_SPI <<
850 clocks = <&cpg CPG_MOD <<
851 <&cpg CPG_MOD <<
852 <&cpg CPG_MOD <<
853 clock-names = "aclk", <<
854 power-domains = <&cpg> <<
855 resets = <&cpg R9A07G0 <<
856 renesas,vsps = <&vspd <<
857 status = "disabled"; <<
858 <<
859 ports { <<
860 #address-cells <<
861 #size-cells = <<
862 <<
863 port@0 { <<
864 reg = <<
865 du_out <<
866 <<
867 }; <<
868 }; <<
869 <<
870 port@1 { <<
871 reg = <<
872 }; <<
873 }; <<
874 }; <<
875 <<
876 cpg: clock-controller@11010000 829 cpg: clock-controller@11010000 {
877 compatible = "renesas, 830 compatible = "renesas,r9a07g054-cpg";
878 reg = <0 0x11010000 0 831 reg = <0 0x11010000 0 0x10000>;
879 clocks = <&extal_clk>; 832 clocks = <&extal_clk>;
880 clock-names = "extal"; 833 clock-names = "extal";
881 #clock-cells = <2>; 834 #clock-cells = <2>;
882 #reset-cells = <1>; 835 #reset-cells = <1>;
883 #power-domain-cells = 836 #power-domain-cells = <0>;
884 }; 837 };
885 838
886 sysc: system-controller@110200 839 sysc: system-controller@11020000 {
887 compatible = "renesas, 840 compatible = "renesas,r9a07g054-sysc";
888 reg = <0 0x11020000 0 841 reg = <0 0x11020000 0 0x10000>;
889 interrupts = <GIC_SPI 842 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
890 <GIC_SPI 843 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
891 <GIC_SPI 844 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
892 <GIC_SPI 845 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
893 interrupt-names = "lpm 846 interrupt-names = "lpm_int", "ca55stbydone_int",
894 "cm3 847 "cm33stbyr_int", "ca55_deny";
895 status = "disabled"; 848 status = "disabled";
896 }; 849 };
897 850
898 pinctrl: pinctrl@11030000 { 851 pinctrl: pinctrl@11030000 {
899 compatible = "renesas, 852 compatible = "renesas,r9a07g054-pinctrl",
900 "renesas, 853 "renesas,r9a07g044-pinctrl";
901 reg = <0 0x11030000 0 854 reg = <0 0x11030000 0 0x10000>;
902 gpio-controller; 855 gpio-controller;
903 #gpio-cells = <2>; 856 #gpio-cells = <2>;
904 #interrupt-cells = <2> 857 #interrupt-cells = <2>;
905 interrupt-parent = <&i 858 interrupt-parent = <&irqc>;
906 interrupt-controller; 859 interrupt-controller;
907 gpio-ranges = <&pinctr 860 gpio-ranges = <&pinctrl 0 0 392>;
908 clocks = <&cpg CPG_MOD 861 clocks = <&cpg CPG_MOD R9A07G054_GPIO_HCLK>;
909 power-domains = <&cpg> 862 power-domains = <&cpg>;
910 resets = <&cpg R9A07G0 863 resets = <&cpg R9A07G054_GPIO_RSTN>,
911 <&cpg R9A07G0 864 <&cpg R9A07G054_GPIO_PORT_RESETN>,
912 <&cpg R9A07G0 865 <&cpg R9A07G054_GPIO_SPARE_RESETN>;
913 }; 866 };
914 867
915 irqc: interrupt-controller@110 868 irqc: interrupt-controller@110a0000 {
916 compatible = "renesas, 869 compatible = "renesas,r9a07g054-irqc",
917 "renesas, 870 "renesas,rzg2l-irqc";
918 #interrupt-cells = <2> 871 #interrupt-cells = <2>;
919 #address-cells = <0>; 872 #address-cells = <0>;
920 interrupt-controller; 873 interrupt-controller;
921 reg = <0 0x110a0000 0 874 reg = <0 0x110a0000 0 0x10000>;
922 interrupts = <GIC_SPI 875 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
923 <GIC_SPI 876 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
924 <GIC_SPI 877 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
925 <GIC_SPI 878 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
926 <GIC_SPI 879 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
927 <GIC_SPI 880 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
928 <GIC_SPI 881 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
929 <GIC_SPI 882 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
930 <GIC_SPI 883 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
931 <GIC_SPI 884 <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>,
932 <GIC_SPI 885 <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>,
933 <GIC_SPI 886 <GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>,
934 <GIC_SPI 887 <GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>,
935 <GIC_SPI 888 <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>,
936 <GIC_SPI 889 <GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>,
937 <GIC_SPI 890 <GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH>,
938 <GIC_SPI 891 <GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>,
939 <GIC_SPI 892 <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>,
940 <GIC_SPI 893 <GIC_SPI 453 IRQ_TYPE_LEVEL_HIGH>,
941 <GIC_SPI 894 <GIC_SPI 454 IRQ_TYPE_LEVEL_HIGH>,
942 <GIC_SPI 895 <GIC_SPI 455 IRQ_TYPE_LEVEL_HIGH>,
943 <GIC_SPI 896 <GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>,
944 <GIC_SPI 897 <GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>,
945 <GIC_SPI 898 <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>,
946 <GIC_SPI 899 <GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>,
947 <GIC_SPI 900 <GIC_SPI 460 IRQ_TYPE_LEVEL_HIGH>,
948 <GIC_SPI 901 <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>,
949 <GIC_SPI 902 <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>,
950 <GIC_SPI 903 <GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH>,
951 <GIC_SPI 904 <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>,
952 <GIC_SPI 905 <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>,
953 <GIC_SPI 906 <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>,
954 <GIC_SPI 907 <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>,
955 <GIC_SPI 908 <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>,
956 <GIC_SPI 909 <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>,
957 <GIC_SPI 910 <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>,
958 <GIC_SPI 911 <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>,
959 <GIC_SPI 912 <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>,
960 <GIC_SPI 913 <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>,
961 <GIC_SPI 914 <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>,
962 <GIC_SPI !! 915 <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>;
963 <GIC_SPI <<
964 <GIC_SPI <<
965 <GIC_SPI <<
966 <GIC_SPI <<
967 <GIC_SPI <<
968 <GIC_SPI <<
969 <GIC_SPI <<
970 interrupt-names = "nmi <<
971 "irq <<
972 "tin <<
973 "tin <<
974 "tin <<
975 "tin <<
976 "tin <<
977 "tin <<
978 "tin <<
979 "tin <<
980 "bus <<
981 "ec7 <<
982 "ec7 <<
983 clocks = <&cpg CPG_MOD 916 clocks = <&cpg CPG_MOD R9A07G054_IA55_CLK>,
984 <&cpg CPG_MOD 917 <&cpg CPG_MOD R9A07G054_IA55_PCLK>;
985 clock-names = "clk", " 918 clock-names = "clk", "pclk";
986 power-domains = <&cpg> 919 power-domains = <&cpg>;
987 resets = <&cpg R9A07G0 920 resets = <&cpg R9A07G054_IA55_RESETN>;
988 }; 921 };
989 922
990 dmac: dma-controller@11820000 923 dmac: dma-controller@11820000 {
991 compatible = "renesas, 924 compatible = "renesas,r9a07g054-dmac",
992 "renesas, 925 "renesas,rz-dmac";
993 reg = <0 0x11820000 0 926 reg = <0 0x11820000 0 0x10000>,
994 <0 0x11830000 0 927 <0 0x11830000 0 0x10000>;
995 interrupts = <GIC_SPI 928 interrupts = <GIC_SPI 141 IRQ_TYPE_EDGE_RISING>,
996 <GIC_SPI 929 <GIC_SPI 125 IRQ_TYPE_EDGE_RISING>,
997 <GIC_SPI 930 <GIC_SPI 126 IRQ_TYPE_EDGE_RISING>,
998 <GIC_SPI 931 <GIC_SPI 127 IRQ_TYPE_EDGE_RISING>,
999 <GIC_SPI 932 <GIC_SPI 128 IRQ_TYPE_EDGE_RISING>,
1000 <GIC_SPI 933 <GIC_SPI 129 IRQ_TYPE_EDGE_RISING>,
1001 <GIC_SPI 934 <GIC_SPI 130 IRQ_TYPE_EDGE_RISING>,
1002 <GIC_SPI 935 <GIC_SPI 131 IRQ_TYPE_EDGE_RISING>,
1003 <GIC_SPI 936 <GIC_SPI 132 IRQ_TYPE_EDGE_RISING>,
1004 <GIC_SPI 937 <GIC_SPI 133 IRQ_TYPE_EDGE_RISING>,
1005 <GIC_SPI 938 <GIC_SPI 134 IRQ_TYPE_EDGE_RISING>,
1006 <GIC_SPI 939 <GIC_SPI 135 IRQ_TYPE_EDGE_RISING>,
1007 <GIC_SPI 940 <GIC_SPI 136 IRQ_TYPE_EDGE_RISING>,
1008 <GIC_SPI 941 <GIC_SPI 137 IRQ_TYPE_EDGE_RISING>,
1009 <GIC_SPI 942 <GIC_SPI 138 IRQ_TYPE_EDGE_RISING>,
1010 <GIC_SPI 943 <GIC_SPI 139 IRQ_TYPE_EDGE_RISING>,
1011 <GIC_SPI 944 <GIC_SPI 140 IRQ_TYPE_EDGE_RISING>;
1012 interrupt-names = "er 945 interrupt-names = "error",
1013 "ch 946 "ch0", "ch1", "ch2", "ch3",
1014 "ch 947 "ch4", "ch5", "ch6", "ch7",
1015 "ch 948 "ch8", "ch9", "ch10", "ch11",
1016 "ch 949 "ch12", "ch13", "ch14", "ch15";
1017 clocks = <&cpg CPG_MO 950 clocks = <&cpg CPG_MOD R9A07G054_DMAC_ACLK>,
1018 <&cpg CPG_MO 951 <&cpg CPG_MOD R9A07G054_DMAC_PCLK>;
1019 clock-names = "main", 952 clock-names = "main", "register";
1020 power-domains = <&cpg 953 power-domains = <&cpg>;
1021 resets = <&cpg R9A07G 954 resets = <&cpg R9A07G054_DMAC_ARESETN>,
1022 <&cpg R9A07G 955 <&cpg R9A07G054_DMAC_RST_ASYNC>;
1023 reset-names = "arst", 956 reset-names = "arst", "rst_async";
1024 #dma-cells = <1>; 957 #dma-cells = <1>;
1025 dma-channels = <16>; 958 dma-channels = <16>;
1026 }; 959 };
1027 960
1028 gpu: gpu@11840000 { 961 gpu: gpu@11840000 {
1029 compatible = "renesas 962 compatible = "renesas,r9a07g054-mali",
1030 "arm,mal 963 "arm,mali-bifrost";
1031 reg = <0x0 0x11840000 964 reg = <0x0 0x11840000 0x0 0x10000>;
1032 interrupts = <GIC_SPI 965 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
1033 <GIC_SPI 966 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
1034 <GIC_SPI 967 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
1035 <GIC_SPI 968 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
1036 interrupt-names = "jo 969 interrupt-names = "job", "mmu", "gpu", "event";
1037 clocks = <&cpg CPG_MO 970 clocks = <&cpg CPG_MOD R9A07G054_GPU_CLK>,
1038 <&cpg CPG_MO 971 <&cpg CPG_MOD R9A07G054_GPU_AXI_CLK>,
1039 <&cpg CPG_MO 972 <&cpg CPG_MOD R9A07G054_GPU_ACE_CLK>;
1040 clock-names = "gpu", 973 clock-names = "gpu", "bus", "bus_ace";
1041 power-domains = <&cpg 974 power-domains = <&cpg>;
1042 resets = <&cpg R9A07G 975 resets = <&cpg R9A07G054_GPU_RESETN>,
1043 <&cpg R9A07G 976 <&cpg R9A07G054_GPU_AXI_RESETN>,
1044 <&cpg R9A07G 977 <&cpg R9A07G054_GPU_ACE_RESETN>;
1045 reset-names = "rst", 978 reset-names = "rst", "axi_rst", "ace_rst";
1046 operating-points-v2 = 979 operating-points-v2 = <&gpu_opp_table>;
1047 }; 980 };
1048 981
1049 gic: interrupt-controller@119 982 gic: interrupt-controller@11900000 {
1050 compatible = "arm,gic 983 compatible = "arm,gic-v3";
1051 #interrupt-cells = <3 984 #interrupt-cells = <3>;
1052 #address-cells = <0>; 985 #address-cells = <0>;
1053 interrupt-controller; 986 interrupt-controller;
1054 reg = <0x0 0x11900000 !! 987 reg = <0x0 0x11900000 0 0x40000>,
1055 <0x0 0x11940000 !! 988 <0x0 0x11940000 0 0x60000>;
1056 interrupts = <GIC_PPI 989 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
1057 }; 990 };
1058 991
1059 sdhi0: mmc@11c00000 { 992 sdhi0: mmc@11c00000 {
1060 compatible = "renesas 993 compatible = "renesas,sdhi-r9a07g054",
1061 "renesas !! 994 "renesas,rcar-gen3-sdhi";
1062 reg = <0x0 0x11c00000 995 reg = <0x0 0x11c00000 0 0x10000>;
1063 interrupts = <GIC_SPI 996 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
1064 <GIC_SPI 997 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
1065 clocks = <&cpg CPG_MO 998 clocks = <&cpg CPG_MOD R9A07G054_SDHI0_IMCLK>,
1066 <&cpg CPG_MO 999 <&cpg CPG_MOD R9A07G054_SDHI0_CLK_HS>,
1067 <&cpg CPG_MO 1000 <&cpg CPG_MOD R9A07G054_SDHI0_IMCLK2>,
1068 <&cpg CPG_MO 1001 <&cpg CPG_MOD R9A07G054_SDHI0_ACLK>;
1069 clock-names = "core", 1002 clock-names = "core", "clkh", "cd", "aclk";
1070 resets = <&cpg R9A07G 1003 resets = <&cpg R9A07G054_SDHI0_IXRST>;
1071 power-domains = <&cpg 1004 power-domains = <&cpg>;
1072 status = "disabled"; 1005 status = "disabled";
1073 }; 1006 };
1074 1007
1075 sdhi1: mmc@11c10000 { 1008 sdhi1: mmc@11c10000 {
1076 compatible = "renesas 1009 compatible = "renesas,sdhi-r9a07g054",
1077 "renesas !! 1010 "renesas,rcar-gen3-sdhi";
1078 reg = <0x0 0x11c10000 1011 reg = <0x0 0x11c10000 0 0x10000>;
1079 interrupts = <GIC_SPI 1012 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
1080 <GIC_SPI 1013 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
1081 clocks = <&cpg CPG_MO 1014 clocks = <&cpg CPG_MOD R9A07G054_SDHI1_IMCLK>,
1082 <&cpg CPG_MO 1015 <&cpg CPG_MOD R9A07G054_SDHI1_CLK_HS>,
1083 <&cpg CPG_MO 1016 <&cpg CPG_MOD R9A07G054_SDHI1_IMCLK2>,
1084 <&cpg CPG_MO 1017 <&cpg CPG_MOD R9A07G054_SDHI1_ACLK>;
1085 clock-names = "core", 1018 clock-names = "core", "clkh", "cd", "aclk";
1086 resets = <&cpg R9A07G 1019 resets = <&cpg R9A07G054_SDHI1_IXRST>;
1087 power-domains = <&cpg 1020 power-domains = <&cpg>;
1088 status = "disabled"; 1021 status = "disabled";
1089 }; 1022 };
1090 1023
1091 eth0: ethernet@11c20000 { 1024 eth0: ethernet@11c20000 {
1092 compatible = "renesas 1025 compatible = "renesas,r9a07g054-gbeth",
1093 "renesas 1026 "renesas,rzg2l-gbeth";
1094 reg = <0 0x11c20000 0 1027 reg = <0 0x11c20000 0 0x10000>;
1095 interrupts = <GIC_SPI 1028 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
1096 <GIC_SPI 1029 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
1097 <GIC_SPI 1030 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
1098 interrupt-names = "mu 1031 interrupt-names = "mux", "fil", "arp_ns";
1099 phy-mode = "rgmii"; 1032 phy-mode = "rgmii";
1100 clocks = <&cpg CPG_MO 1033 clocks = <&cpg CPG_MOD R9A07G054_ETH0_CLK_AXI>,
1101 <&cpg CPG_MO 1034 <&cpg CPG_MOD R9A07G054_ETH0_CLK_CHI>,
1102 <&cpg CPG_CO 1035 <&cpg CPG_CORE R9A07G054_CLK_HP>;
1103 clock-names = "axi", 1036 clock-names = "axi", "chi", "refclk";
1104 resets = <&cpg R9A07G 1037 resets = <&cpg R9A07G054_ETH0_RST_HW_N>;
1105 power-domains = <&cpg 1038 power-domains = <&cpg>;
1106 #address-cells = <1>; 1039 #address-cells = <1>;
1107 #size-cells = <0>; 1040 #size-cells = <0>;
1108 status = "disabled"; 1041 status = "disabled";
1109 }; 1042 };
1110 1043
1111 eth1: ethernet@11c30000 { 1044 eth1: ethernet@11c30000 {
1112 compatible = "renesas 1045 compatible = "renesas,r9a07g054-gbeth",
1113 "renesas 1046 "renesas,rzg2l-gbeth";
1114 reg = <0 0x11c30000 0 1047 reg = <0 0x11c30000 0 0x10000>;
1115 interrupts = <GIC_SPI 1048 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
1116 <GIC_SPI 1049 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
1117 <GIC_SPI 1050 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
1118 interrupt-names = "mu 1051 interrupt-names = "mux", "fil", "arp_ns";
1119 phy-mode = "rgmii"; 1052 phy-mode = "rgmii";
1120 clocks = <&cpg CPG_MO 1053 clocks = <&cpg CPG_MOD R9A07G054_ETH1_CLK_AXI>,
1121 <&cpg CPG_MO 1054 <&cpg CPG_MOD R9A07G054_ETH1_CLK_CHI>,
1122 <&cpg CPG_CO 1055 <&cpg CPG_CORE R9A07G054_CLK_HP>;
1123 clock-names = "axi", 1056 clock-names = "axi", "chi", "refclk";
1124 resets = <&cpg R9A07G 1057 resets = <&cpg R9A07G054_ETH1_RST_HW_N>;
1125 power-domains = <&cpg 1058 power-domains = <&cpg>;
1126 #address-cells = <1>; 1059 #address-cells = <1>;
1127 #size-cells = <0>; 1060 #size-cells = <0>;
1128 status = "disabled"; 1061 status = "disabled";
1129 }; 1062 };
1130 1063
1131 phyrst: usbphy-ctrl@11c40000 1064 phyrst: usbphy-ctrl@11c40000 {
1132 compatible = "renesas 1065 compatible = "renesas,r9a07g054-usbphy-ctrl",
1133 "renesas 1066 "renesas,rzg2l-usbphy-ctrl";
1134 reg = <0 0x11c40000 0 1067 reg = <0 0x11c40000 0 0x10000>;
1135 clocks = <&cpg CPG_MO 1068 clocks = <&cpg CPG_MOD R9A07G054_USB_PCLK>;
1136 resets = <&cpg R9A07G 1069 resets = <&cpg R9A07G054_USB_PRESETN>;
1137 power-domains = <&cpg 1070 power-domains = <&cpg>;
1138 #reset-cells = <1>; 1071 #reset-cells = <1>;
1139 status = "disabled"; 1072 status = "disabled";
1140 <<
1141 usb0_vbus_otg: regula <<
1142 regulator-nam <<
1143 }; <<
1144 }; 1073 };
1145 1074
1146 ohci0: usb@11c50000 { 1075 ohci0: usb@11c50000 {
1147 compatible = "generic 1076 compatible = "generic-ohci";
1148 reg = <0 0x11c50000 0 1077 reg = <0 0x11c50000 0 0x100>;
1149 interrupts = <GIC_SPI 1078 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
1150 clocks = <&cpg CPG_MO 1079 clocks = <&cpg CPG_MOD R9A07G054_USB_PCLK>,
1151 <&cpg CPG_MO 1080 <&cpg CPG_MOD R9A07G054_USB_U2H0_HCLK>;
1152 resets = <&phyrst 0>, 1081 resets = <&phyrst 0>,
1153 <&cpg R9A07G 1082 <&cpg R9A07G054_USB_U2H0_HRESETN>;
1154 phys = <&usb2_phy0 1> 1083 phys = <&usb2_phy0 1>;
1155 phy-names = "usb"; 1084 phy-names = "usb";
1156 power-domains = <&cpg 1085 power-domains = <&cpg>;
1157 status = "disabled"; 1086 status = "disabled";
1158 }; 1087 };
1159 1088
1160 ohci1: usb@11c70000 { 1089 ohci1: usb@11c70000 {
1161 compatible = "generic 1090 compatible = "generic-ohci";
1162 reg = <0 0x11c70000 0 1091 reg = <0 0x11c70000 0 0x100>;
1163 interrupts = <GIC_SPI 1092 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
1164 clocks = <&cpg CPG_MO 1093 clocks = <&cpg CPG_MOD R9A07G054_USB_PCLK>,
1165 <&cpg CPG_MO 1094 <&cpg CPG_MOD R9A07G054_USB_U2H1_HCLK>;
1166 resets = <&phyrst 1>, 1095 resets = <&phyrst 1>,
1167 <&cpg R9A07G 1096 <&cpg R9A07G054_USB_U2H1_HRESETN>;
1168 phys = <&usb2_phy1 1> 1097 phys = <&usb2_phy1 1>;
1169 phy-names = "usb"; 1098 phy-names = "usb";
1170 power-domains = <&cpg 1099 power-domains = <&cpg>;
1171 status = "disabled"; 1100 status = "disabled";
1172 }; 1101 };
1173 1102
1174 ehci0: usb@11c50100 { 1103 ehci0: usb@11c50100 {
1175 compatible = "generic 1104 compatible = "generic-ehci";
1176 reg = <0 0x11c50100 0 1105 reg = <0 0x11c50100 0 0x100>;
1177 interrupts = <GIC_SPI 1106 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
1178 clocks = <&cpg CPG_MO 1107 clocks = <&cpg CPG_MOD R9A07G054_USB_PCLK>,
1179 <&cpg CPG_MO 1108 <&cpg CPG_MOD R9A07G054_USB_U2H0_HCLK>;
1180 resets = <&phyrst 0>, 1109 resets = <&phyrst 0>,
1181 <&cpg R9A07G 1110 <&cpg R9A07G054_USB_U2H0_HRESETN>;
1182 phys = <&usb2_phy0 2> 1111 phys = <&usb2_phy0 2>;
1183 phy-names = "usb"; 1112 phy-names = "usb";
1184 companion = <&ohci0>; 1113 companion = <&ohci0>;
1185 power-domains = <&cpg 1114 power-domains = <&cpg>;
1186 status = "disabled"; 1115 status = "disabled";
1187 }; 1116 };
1188 1117
1189 ehci1: usb@11c70100 { 1118 ehci1: usb@11c70100 {
1190 compatible = "generic 1119 compatible = "generic-ehci";
1191 reg = <0 0x11c70100 0 1120 reg = <0 0x11c70100 0 0x100>;
1192 interrupts = <GIC_SPI 1121 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
1193 clocks = <&cpg CPG_MO 1122 clocks = <&cpg CPG_MOD R9A07G054_USB_PCLK>,
1194 <&cpg CPG_MO 1123 <&cpg CPG_MOD R9A07G054_USB_U2H1_HCLK>;
1195 resets = <&phyrst 1>, 1124 resets = <&phyrst 1>,
1196 <&cpg R9A07G 1125 <&cpg R9A07G054_USB_U2H1_HRESETN>;
1197 phys = <&usb2_phy1 2> 1126 phys = <&usb2_phy1 2>;
1198 phy-names = "usb"; 1127 phy-names = "usb";
1199 companion = <&ohci1>; 1128 companion = <&ohci1>;
1200 power-domains = <&cpg 1129 power-domains = <&cpg>;
1201 status = "disabled"; 1130 status = "disabled";
1202 }; 1131 };
1203 1132
1204 usb2_phy0: usb-phy@11c50200 { 1133 usb2_phy0: usb-phy@11c50200 {
1205 compatible = "renesas 1134 compatible = "renesas,usb2-phy-r9a07g054",
1206 "renesas 1135 "renesas,rzg2l-usb2-phy";
1207 reg = <0 0x11c50200 0 1136 reg = <0 0x11c50200 0 0x700>;
1208 interrupts = <GIC_SPI 1137 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
1209 clocks = <&cpg CPG_MO 1138 clocks = <&cpg CPG_MOD R9A07G054_USB_PCLK>,
1210 <&cpg CPG_MO 1139 <&cpg CPG_MOD R9A07G054_USB_U2H0_HCLK>;
1211 resets = <&phyrst 0>; 1140 resets = <&phyrst 0>;
1212 #phy-cells = <1>; 1141 #phy-cells = <1>;
1213 power-domains = <&cpg 1142 power-domains = <&cpg>;
1214 status = "disabled"; 1143 status = "disabled";
1215 }; 1144 };
1216 1145
1217 usb2_phy1: usb-phy@11c70200 { 1146 usb2_phy1: usb-phy@11c70200 {
1218 compatible = "renesas 1147 compatible = "renesas,usb2-phy-r9a07g054",
1219 "renesas 1148 "renesas,rzg2l-usb2-phy";
1220 reg = <0 0x11c70200 0 1149 reg = <0 0x11c70200 0 0x700>;
1221 interrupts = <GIC_SPI 1150 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
1222 clocks = <&cpg CPG_MO 1151 clocks = <&cpg CPG_MOD R9A07G054_USB_PCLK>,
1223 <&cpg CPG_MO 1152 <&cpg CPG_MOD R9A07G054_USB_U2H1_HCLK>;
1224 resets = <&phyrst 1>; 1153 resets = <&phyrst 1>;
1225 #phy-cells = <1>; 1154 #phy-cells = <1>;
1226 power-domains = <&cpg 1155 power-domains = <&cpg>;
1227 status = "disabled"; 1156 status = "disabled";
1228 }; 1157 };
1229 1158
1230 hsusb: usb@11c60000 { 1159 hsusb: usb@11c60000 {
1231 compatible = "renesas 1160 compatible = "renesas,usbhs-r9a07g054",
1232 "renesas !! 1161 "renesas,rza2-usbhs";
1233 reg = <0 0x11c60000 0 1162 reg = <0 0x11c60000 0 0x10000>;
1234 interrupts = <GIC_SPI 1163 interrupts = <GIC_SPI 100 IRQ_TYPE_EDGE_RISING>,
1235 <GIC_SPI 1164 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
1236 <GIC_SPI 1165 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
1237 <GIC_SPI 1166 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
1238 clocks = <&cpg CPG_MO 1167 clocks = <&cpg CPG_MOD R9A07G054_USB_PCLK>,
1239 <&cpg CPG_MO 1168 <&cpg CPG_MOD R9A07G054_USB_U2P_EXR_CPUCLK>;
1240 resets = <&phyrst 0>, 1169 resets = <&phyrst 0>,
1241 <&cpg R9A07G 1170 <&cpg R9A07G054_USB_U2P_EXL_SYSRST>;
1242 renesas,buswait = <7> 1171 renesas,buswait = <7>;
1243 phys = <&usb2_phy0 3> 1172 phys = <&usb2_phy0 3>;
1244 phy-names = "usb"; 1173 phy-names = "usb";
1245 power-domains = <&cpg 1174 power-domains = <&cpg>;
1246 status = "disabled"; 1175 status = "disabled";
1247 }; 1176 };
1248 1177
1249 wdt0: watchdog@12800800 { 1178 wdt0: watchdog@12800800 {
1250 compatible = "renesas 1179 compatible = "renesas,r9a07g054-wdt",
1251 "renesas 1180 "renesas,rzg2l-wdt";
1252 reg = <0 0x12800800 0 1181 reg = <0 0x12800800 0 0x400>;
1253 clocks = <&cpg CPG_MO 1182 clocks = <&cpg CPG_MOD R9A07G054_WDT0_PCLK>,
1254 <&cpg CPG_MO 1183 <&cpg CPG_MOD R9A07G054_WDT0_CLK>;
1255 clock-names = "pclk", 1184 clock-names = "pclk", "oscclk";
1256 interrupts = <GIC_SPI 1185 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
1257 <GIC_SPI 1186 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
1258 interrupt-names = "wd 1187 interrupt-names = "wdt", "perrout";
1259 resets = <&cpg R9A07G 1188 resets = <&cpg R9A07G054_WDT0_PRESETN>;
1260 power-domains = <&cpg 1189 power-domains = <&cpg>;
1261 status = "disabled"; 1190 status = "disabled";
1262 }; 1191 };
1263 1192
1264 wdt1: watchdog@12800c00 { 1193 wdt1: watchdog@12800c00 {
1265 compatible = "renesas 1194 compatible = "renesas,r9a07g054-wdt",
1266 "renesas 1195 "renesas,rzg2l-wdt";
1267 reg = <0 0x12800C00 0 1196 reg = <0 0x12800C00 0 0x400>;
1268 clocks = <&cpg CPG_MO 1197 clocks = <&cpg CPG_MOD R9A07G054_WDT1_PCLK>,
1269 <&cpg CPG_MO 1198 <&cpg CPG_MOD R9A07G054_WDT1_CLK>;
1270 clock-names = "pclk", 1199 clock-names = "pclk", "oscclk";
1271 interrupts = <GIC_SPI 1200 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
1272 <GIC_SPI 1201 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
1273 interrupt-names = "wd 1202 interrupt-names = "wdt", "perrout";
1274 resets = <&cpg R9A07G 1203 resets = <&cpg R9A07G054_WDT1_PRESETN>;
1275 power-domains = <&cpg 1204 power-domains = <&cpg>;
1276 status = "disabled"; 1205 status = "disabled";
1277 }; 1206 };
1278 1207
1279 ostm0: timer@12801000 { 1208 ostm0: timer@12801000 {
1280 compatible = "renesas 1209 compatible = "renesas,r9a07g054-ostm",
1281 "renesas 1210 "renesas,ostm";
1282 reg = <0x0 0x12801000 1211 reg = <0x0 0x12801000 0x0 0x400>;
1283 interrupts = <GIC_SPI 1212 interrupts = <GIC_SPI 46 IRQ_TYPE_EDGE_RISING>;
1284 clocks = <&cpg CPG_MO 1213 clocks = <&cpg CPG_MOD R9A07G054_OSTM0_PCLK>;
1285 resets = <&cpg R9A07G 1214 resets = <&cpg R9A07G054_OSTM0_PRESETZ>;
1286 power-domains = <&cpg 1215 power-domains = <&cpg>;
1287 status = "disabled"; 1216 status = "disabled";
1288 }; 1217 };
1289 1218
1290 ostm1: timer@12801400 { 1219 ostm1: timer@12801400 {
1291 compatible = "renesas 1220 compatible = "renesas,r9a07g054-ostm",
1292 "renesas 1221 "renesas,ostm";
1293 reg = <0x0 0x12801400 1222 reg = <0x0 0x12801400 0x0 0x400>;
1294 interrupts = <GIC_SPI 1223 interrupts = <GIC_SPI 47 IRQ_TYPE_EDGE_RISING>;
1295 clocks = <&cpg CPG_MO 1224 clocks = <&cpg CPG_MOD R9A07G054_OSTM1_PCLK>;
1296 resets = <&cpg R9A07G 1225 resets = <&cpg R9A07G054_OSTM1_PRESETZ>;
1297 power-domains = <&cpg 1226 power-domains = <&cpg>;
1298 status = "disabled"; 1227 status = "disabled";
1299 }; 1228 };
1300 1229
1301 ostm2: timer@12801800 { 1230 ostm2: timer@12801800 {
1302 compatible = "renesas 1231 compatible = "renesas,r9a07g054-ostm",
1303 "renesas 1232 "renesas,ostm";
1304 reg = <0x0 0x12801800 1233 reg = <0x0 0x12801800 0x0 0x400>;
1305 interrupts = <GIC_SPI 1234 interrupts = <GIC_SPI 48 IRQ_TYPE_EDGE_RISING>;
1306 clocks = <&cpg CPG_MO 1235 clocks = <&cpg CPG_MOD R9A07G054_OSTM2_PCLK>;
1307 resets = <&cpg R9A07G 1236 resets = <&cpg R9A07G054_OSTM2_PRESETZ>;
1308 power-domains = <&cpg 1237 power-domains = <&cpg>;
1309 status = "disabled"; 1238 status = "disabled";
1310 }; 1239 };
1311 }; 1240 };
1312 1241
1313 thermal-zones { 1242 thermal-zones {
1314 cpu-thermal { 1243 cpu-thermal {
1315 polling-delay-passive 1244 polling-delay-passive = <250>;
1316 polling-delay = <1000 1245 polling-delay = <1000>;
1317 thermal-sensors = <&t 1246 thermal-sensors = <&tsu 0>;
1318 sustainable-power = < 1247 sustainable-power = <717>;
1319 1248
1320 cooling-maps { 1249 cooling-maps {
1321 map0 { 1250 map0 {
1322 trip 1251 trip = <&target>;
1323 cooli 1252 cooling-device = <&cpu0 0 2>;
1324 contr 1253 contribution = <1024>;
1325 }; 1254 };
1326 }; 1255 };
1327 1256
1328 trips { 1257 trips {
1329 sensor_crit: 1258 sensor_crit: sensor-crit {
1330 tempe 1259 temperature = <125000>;
1331 hyste 1260 hysteresis = <1000>;
1332 type 1261 type = "critical";
1333 }; 1262 };
1334 1263
1335 target: trip- 1264 target: trip-point {
1336 tempe 1265 temperature = <100000>;
1337 hyste 1266 hysteresis = <1000>;
1338 type 1267 type = "passive";
1339 }; 1268 };
1340 }; 1269 };
1341 }; 1270 };
1342 }; 1271 };
1343 1272
1344 timer { 1273 timer {
1345 compatible = "arm,armv8-timer 1274 compatible = "arm,armv8-timer";
1346 interrupts-extended = <&gic G 1275 interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
1347 <&gic G 1276 <&gic GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
1348 <&gic G 1277 <&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
1349 <&gic G !! 1278 <&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
1350 <&gic G <<
1351 interrupt-names = "sec-phys", <<
1352 "hyp-virt"; <<
1353 }; 1279 };
1354 }; 1280 };
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