1 // SPDX-License-Identifier: (GPL-2.0-only OR B
2 /*
3 * Device Tree Source for the RZ/G3S SoC
4 *
5 * Copyright (C) 2023 Renesas Electronics Corp
6 */
7
8 #include <dt-bindings/interrupt-controller/arm
9 #include <dt-bindings/clock/r9a08g045-cpg.h>
10
11 / {
12 compatible = "renesas,r9a08g045";
13 #address-cells = <2>;
14 #size-cells = <2>;
15
16 cpus {
17 #address-cells = <1>;
18 #size-cells = <0>;
19
20 cpu0: cpu@0 {
21 compatible = "arm,cort
22 reg = <0>;
23 device_type = "cpu";
24 #cooling-cells = <2>;
25 next-level-cache = <&L
26 enable-method = "psci"
27 clocks = <&cpg CPG_COR
28 };
29
30 L3_CA55: cache-controller-0 {
31 compatible = "cache";
32 cache-level = <3>;
33 cache-unified;
34 cache-size = <0x40000>
35 };
36 };
37
38 extal_clk: extal-clk {
39 compatible = "fixed-clock";
40 #clock-cells = <0>;
41 /* This value must be overridd
42 clock-frequency = <0>;
43 };
44
45 psci {
46 compatible = "arm,psci-1.0", "
47 method = "smc";
48 };
49
50 soc: soc {
51 compatible = "simple-bus";
52 interrupt-parent = <&gic>;
53 #address-cells = <2>;
54 #size-cells = <2>;
55 ranges;
56
57 scif0: serial@1004b800 {
58 compatible = "renesas,
59 reg = <0 0x1004b800 0
60 interrupts = <GIC_SPI
61 <GIC_SPI
62 <GIC_SPI
63 <GIC_SPI
64 <GIC_SPI
65 <GIC_SPI
66 interrupt-names = "eri
67 "bri
68 clocks = <&cpg CPG_MOD
69 clock-names = "fck";
70 power-domains = <&cpg>
71 resets = <&cpg R9A08G0
72 status = "disabled";
73 };
74
75 i2c0: i2c@10090000 {
76 compatible = "renesas,
77 reg = <0 0x10090000 0
78 interrupts = <GIC_SPI
79 <GIC_SPI
80 <GIC_SPI
81 <GIC_SPI
82 <GIC_SPI
83 <GIC_SPI
84 <GIC_SPI
85 <GIC_SPI
86 interrupt-names = "tei
87 "nak
88 clocks = <&cpg CPG_MOD
89 clock-frequency = <100
90 resets = <&cpg R9A08G0
91 power-domains = <&cpg>
92 #address-cells = <1>;
93 #size-cells = <0>;
94 status = "disabled";
95 };
96
97 i2c1: i2c@10090400 {
98 compatible = "renesas,
99 reg = <0 0x10090400 0
100 interrupts = <GIC_SPI
101 <GIC_SPI
102 <GIC_SPI
103 <GIC_SPI
104 <GIC_SPI
105 <GIC_SPI
106 <GIC_SPI
107 <GIC_SPI
108 interrupt-names = "tei
109 "nak
110 clocks = <&cpg CPG_MOD
111 clock-frequency = <100
112 resets = <&cpg R9A08G0
113 power-domains = <&cpg>
114 #address-cells = <1>;
115 #size-cells = <0>;
116 status = "disabled";
117 };
118
119 i2c2: i2c@10090800 {
120 compatible = "renesas,
121 reg = <0 0x10090800 0
122 interrupts = <GIC_SPI
123 <GIC_SPI
124 <GIC_SPI
125 <GIC_SPI
126 <GIC_SPI
127 <GIC_SPI
128 <GIC_SPI
129 <GIC_SPI
130 interrupt-names = "tei
131 "nak
132 clocks = <&cpg CPG_MOD
133 clock-frequency = <100
134 resets = <&cpg R9A08G0
135 power-domains = <&cpg>
136 #address-cells = <1>;
137 #size-cells = <0>;
138 status = "disabled";
139 };
140
141 i2c3: i2c@10090c00 {
142 compatible = "renesas,
143 reg = <0 0x10090c00 0
144 interrupts = <GIC_SPI
145 <GIC_SPI
146 <GIC_SPI
147 <GIC_SPI
148 <GIC_SPI
149 <GIC_SPI
150 <GIC_SPI
151 <GIC_SPI
152 interrupt-names = "tei
153 "nak
154 clocks = <&cpg CPG_MOD
155 clock-frequency = <100
156 resets = <&cpg R9A08G0
157 power-domains = <&cpg>
158 #address-cells = <1>;
159 #size-cells = <0>;
160 status = "disabled";
161 };
162
163 cpg: clock-controller@11010000
164 compatible = "renesas,
165 reg = <0 0x11010000 0
166 clocks = <&extal_clk>;
167 clock-names = "extal";
168 #clock-cells = <2>;
169 #reset-cells = <1>;
170 #power-domain-cells =
171 };
172
173 sysc: system-controller@110200
174 compatible = "renesas,
175 reg = <0 0x11020000 0
176 interrupts = <GIC_SPI
177 <GIC_SPI
178 <GIC_SPI
179 <GIC_SPI
180 interrupt-names = "lpm
181 "cm3
182 status = "disabled";
183 };
184
185 pinctrl: pinctrl@11030000 {
186 compatible = "renesas,
187 reg = <0 0x11030000 0
188 gpio-controller;
189 #gpio-cells = <2>;
190 interrupt-controller;
191 #interrupt-cells = <2>
192 interrupt-parent = <&i
193 gpio-ranges = <&pinctr
194 clocks = <&cpg CPG_MOD
195 power-domains = <&cpg>
196 resets = <&cpg R9A08G0
197 <&cpg R9A08G0
198 <&cpg R9A08G0
199 };
200
201 irqc: interrupt-controller@110
202 compatible = "renesas,
203 #interrupt-cells = <2>
204 #address-cells = <0>;
205 interrupt-controller;
206 reg = <0 0x11050000 0
207 interrupts = <GIC_SPI
208 <GIC_SPI
209 <GIC_SPI
210 <GIC_SPI
211 <GIC_SPI
212 <GIC_SPI
213 <GIC_SPI
214 <GIC_SPI
215 <GIC_SPI
216 <GIC_SPI
217 <GIC_SPI
218 <GIC_SPI
219 <GIC_SPI
220 <GIC_SPI
221 <GIC_SPI
222 <GIC_SPI
223 <GIC_SPI
224 <GIC_SPI
225 <GIC_SPI
226 <GIC_SPI
227 <GIC_SPI
228 <GIC_SPI
229 <GIC_SPI
230 <GIC_SPI
231 <GIC_SPI
232 <GIC_SPI
233 <GIC_SPI
234 <GIC_SPI
235 <GIC_SPI
236 <GIC_SPI
237 <GIC_SPI
238 <GIC_SPI
239 <GIC_SPI
240 <GIC_SPI
241 <GIC_SPI
242 <GIC_SPI
243 <GIC_SPI
244 <GIC_SPI
245 <GIC_SPI
246 <GIC_SPI
247 <GIC_SPI
248 <GIC_SPI
249 <GIC_SPI
250 <GIC_SPI
251 <GIC_SPI
252 interrupt-names = "nmi
253 "irq
254 "irq
255 "tin
256 "tin
257 "tin
258 "tin
259 "tin
260 "tin
261 "tin
262 "tin
263 "bus
264 "ec7
265 clocks = <&cpg CPG_MOD
266 <&cpg CPG_MOD
267 clock-names = "clk", "
268 power-domains = <&cpg>
269 resets = <&cpg R9A08G0
270 };
271
272 dmac: dma-controller@11820000
273 compatible = "renesas,
274 "renesas,
275 reg = <0 0x11820000 0
276 <0 0x11830000 0
277 interrupts = <GIC_SPI
278 <GIC_SPI
279 <GIC_SPI
280 <GIC_SPI
281 <GIC_SPI
282 <GIC_SPI
283 <GIC_SPI
284 <GIC_SPI
285 <GIC_SPI
286 <GIC_SPI
287 <GIC_SPI
288 <GIC_SPI
289 <GIC_SPI
290 <GIC_SPI
291 <GIC_SPI
292 <GIC_SPI
293 <GIC_SPI
294 interrupt-names = "err
295 "ch0
296 "ch4
297 "ch8
298 "ch1
299 clocks = <&cpg CPG_MOD
300 <&cpg CPG_MOD
301 clock-names = "main",
302 power-domains = <&cpg>
303 resets = <&cpg R9A08G0
304 <&cpg R9A08G0
305 reset-names = "arst",
306 #dma-cells = <1>;
307 dma-channels = <16>;
308 };
309
310 sdhi0: mmc@11c00000 {
311 compatible = "renesas,
312 reg = <0x0 0x11c00000
313 interrupts = <GIC_SPI
314 <GIC_SPI
315 clocks = <&cpg CPG_MOD
316 <&cpg CPG_MOD
317 <&cpg CPG_MOD
318 <&cpg CPG_MOD
319 clock-names = "core",
320 resets = <&cpg R9A08G0
321 power-domains = <&cpg>
322 status = "disabled";
323 };
324
325 sdhi1: mmc@11c10000 {
326 compatible = "renesas,
327 reg = <0x0 0x11c10000
328 interrupts = <GIC_SPI
329 <GIC_SPI
330 clocks = <&cpg CPG_MOD
331 <&cpg CPG_MOD
332 <&cpg CPG_MOD
333 <&cpg CPG_MOD
334 clock-names = "core",
335 resets = <&cpg R9A08G0
336 power-domains = <&cpg>
337 status = "disabled";
338 };
339
340 sdhi2: mmc@11c20000 {
341 compatible = "renesas,
342 reg = <0x0 0x11c20000
343 interrupts = <GIC_SPI
344 <GIC_SPI
345 clocks = <&cpg CPG_MOD
346 <&cpg CPG_MOD
347 <&cpg CPG_MOD
348 <&cpg CPG_MOD
349 clock-names = "core",
350 resets = <&cpg R9A08G0
351 power-domains = <&cpg>
352 status = "disabled";
353 };
354
355 eth0: ethernet@11c30000 {
356 compatible = "renesas,
357 reg = <0 0x11c30000 0
358 interrupts = <GIC_SPI
359 <GIC_SPI
360 <GIC_SPI
361 interrupt-names = "mux
362 phy-mode = "rgmii";
363 clocks = <&cpg CPG_MOD
364 <&cpg CPG_MOD
365 <&cpg CPG_MOD
366 clock-names = "axi", "
367 resets = <&cpg R9A08G0
368 power-domains = <&cpg>
369 #address-cells = <1>;
370 #size-cells = <0>;
371 status = "disabled";
372 };
373
374 eth1: ethernet@11c40000 {
375 compatible = "renesas,
376 reg = <0 0x11c40000 0
377 interrupts = <GIC_SPI
378 <GIC_SPI
379 <GIC_SPI
380 interrupt-names = "mux
381 phy-mode = "rgmii";
382 clocks = <&cpg CPG_MOD
383 <&cpg CPG_MOD
384 <&cpg CPG_MOD
385 clock-names = "axi", "
386 resets = <&cpg R9A08G0
387 power-domains = <&cpg>
388 #address-cells = <1>;
389 #size-cells = <0>;
390 status = "disabled";
391 };
392
393 gic: interrupt-controller@1240
394 compatible = "arm,gic-
395 #interrupt-cells = <3>
396 #address-cells = <0>;
397 interrupt-controller;
398 reg = <0x0 0x12400000
399 <0x0 0x12440000
400 interrupts = <GIC_PPI
401 };
402
403 wdt0: watchdog@12800800 {
404 compatible = "renesas,
405 reg = <0 0x12800800 0
406 clocks = <&cpg CPG_MOD
407 <&cpg CPG_MOD
408 clock-names = "pclk",
409 interrupts = <GIC_SPI
410 <GIC_SPI
411 interrupt-names = "wdt
412 resets = <&cpg R9A08G0
413 power-domains = <&cpg>
414 status = "disabled";
415 };
416 };
417
418 timer {
419 compatible = "arm,armv8-timer"
420 interrupts-extended = <&gic GI
421 <&gic GI
422 <&gic GI
423 <&gic GI
424 <&gic GI
425 interrupt-names = "sec-phys",
426 "hyp-virt";
427 };
428 };
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