Linux/scripts/dtc/include-prefixes/arm64/renesas/r9a08g045.dtsi

Version: ~ [ linux-6.12-rc7 ] ~ [ linux-6.11.7 ] ~ [ linux-6.10.14 ] ~ [ linux-6.9.12 ] ~ [ linux-6.8.12 ] ~ [ linux-6.7.12 ] ~ [ linux-6.6.60 ] ~ [ linux-6.5.13 ] ~ [ linux-6.4.16 ] ~ [ linux-6.3.13 ] ~ [ linux-6.2.16 ] ~ [ linux-6.1.116 ] ~ [ linux-6.0.19 ] ~ [ linux-5.19.17 ] ~ [ linux-5.18.19 ] ~ [ linux-5.17.15 ] ~ [ linux-5.16.20 ] ~ [ linux-5.15.171 ] ~ [ linux-5.14.21 ] ~ [ linux-5.13.19 ] ~ [ linux-5.12.19 ] ~ [ linux-5.11.22 ] ~ [ linux-5.10.229 ] ~ [ linux-5.9.16 ] ~ [ linux-5.8.18 ] ~ [ linux-5.7.19 ] ~ [ linux-5.6.19 ] ~ [ linux-5.5.19 ] ~ [ linux-5.4.285 ] ~ [ linux-5.3.18 ] ~ [ linux-5.2.21 ] ~ [ linux-5.1.21 ] ~ [ linux-5.0.21 ] ~ [ linux-4.20.17 ] ~ [ linux-4.19.323 ] ~ [ linux-4.18.20 ] ~ [ linux-4.17.19 ] ~ [ linux-4.16.18 ] ~ [ linux-4.15.18 ] ~ [ linux-4.14.336 ] ~ [ linux-4.13.16 ] ~ [ linux-4.12.14 ] ~ [ linux-4.11.12 ] ~ [ linux-4.10.17 ] ~ [ linux-4.9.337 ] ~ [ linux-4.4.302 ] ~ [ linux-3.10.108 ] ~ [ linux-2.6.32.71 ] ~ [ linux-2.6.0 ] ~ [ linux-2.4.37.11 ] ~ [ unix-v6-master ] ~ [ ccs-tools-1.8.12 ] ~ [ policy-sample ] ~
Architecture: ~ [ i386 ] ~ [ alpha ] ~ [ m68k ] ~ [ mips ] ~ [ ppc ] ~ [ sparc ] ~ [ sparc64 ] ~

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1 // SPDX-License-Identifier: (GPL-2.0-only OR B 1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 /* 2 /* 3 * Device Tree Source for the RZ/G3S SoC 3 * Device Tree Source for the RZ/G3S SoC 4 * 4 * 5 * Copyright (C) 2023 Renesas Electronics Corp 5 * Copyright (C) 2023 Renesas Electronics Corp. 6 */ 6 */ 7 7 8 #include <dt-bindings/interrupt-controller/arm 8 #include <dt-bindings/interrupt-controller/arm-gic.h> 9 #include <dt-bindings/clock/r9a08g045-cpg.h> 9 #include <dt-bindings/clock/r9a08g045-cpg.h> 10 10 11 / { 11 / { 12 compatible = "renesas,r9a08g045"; 12 compatible = "renesas,r9a08g045"; 13 #address-cells = <2>; 13 #address-cells = <2>; 14 #size-cells = <2>; 14 #size-cells = <2>; 15 15 16 cpus { 16 cpus { 17 #address-cells = <1>; 17 #address-cells = <1>; 18 #size-cells = <0>; 18 #size-cells = <0>; 19 19 20 cpu0: cpu@0 { 20 cpu0: cpu@0 { 21 compatible = "arm,cort 21 compatible = "arm,cortex-a55"; 22 reg = <0>; 22 reg = <0>; 23 device_type = "cpu"; 23 device_type = "cpu"; 24 #cooling-cells = <2>; 24 #cooling-cells = <2>; 25 next-level-cache = <&L 25 next-level-cache = <&L3_CA55>; 26 enable-method = "psci" 26 enable-method = "psci"; 27 clocks = <&cpg CPG_COR 27 clocks = <&cpg CPG_CORE R9A08G045_CLK_I>; 28 }; 28 }; 29 29 30 L3_CA55: cache-controller-0 { 30 L3_CA55: cache-controller-0 { 31 compatible = "cache"; 31 compatible = "cache"; 32 cache-level = <3>; 32 cache-level = <3>; 33 cache-unified; 33 cache-unified; 34 cache-size = <0x40000> 34 cache-size = <0x40000>; 35 }; 35 }; 36 }; 36 }; 37 37 38 extal_clk: extal-clk { 38 extal_clk: extal-clk { 39 compatible = "fixed-clock"; 39 compatible = "fixed-clock"; 40 #clock-cells = <0>; 40 #clock-cells = <0>; 41 /* This value must be overridd 41 /* This value must be overridden by the board. */ 42 clock-frequency = <0>; 42 clock-frequency = <0>; 43 }; 43 }; 44 44 45 psci { << 46 compatible = "arm,psci-1.0", " << 47 method = "smc"; << 48 }; << 49 << 50 soc: soc { 45 soc: soc { 51 compatible = "simple-bus"; 46 compatible = "simple-bus"; 52 interrupt-parent = <&gic>; 47 interrupt-parent = <&gic>; 53 #address-cells = <2>; 48 #address-cells = <2>; 54 #size-cells = <2>; 49 #size-cells = <2>; 55 ranges; 50 ranges; 56 51 57 scif0: serial@1004b800 { 52 scif0: serial@1004b800 { 58 compatible = "renesas, 53 compatible = "renesas,scif-r9a08g045", "renesas,scif-r9a07g044"; 59 reg = <0 0x1004b800 0 54 reg = <0 0x1004b800 0 0x400>; 60 interrupts = <GIC_SPI 55 interrupts = <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 61 <GIC_SPI 56 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 62 <GIC_SPI 57 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 63 <GIC_SPI 58 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 64 <GIC_SPI 59 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 65 <GIC_SPI 60 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>; 66 interrupt-names = "eri 61 interrupt-names = "eri", "rxi", "txi", 67 "bri 62 "bri", "dri", "tei"; 68 clocks = <&cpg CPG_MOD 63 clocks = <&cpg CPG_MOD R9A08G045_SCIF0_CLK_PCK>; 69 clock-names = "fck"; 64 clock-names = "fck"; 70 power-domains = <&cpg> 65 power-domains = <&cpg>; 71 resets = <&cpg R9A08G0 66 resets = <&cpg R9A08G045_SCIF0_RST_SYSTEM_N>; 72 status = "disabled"; 67 status = "disabled"; 73 }; 68 }; 74 69 75 i2c0: i2c@10090000 { << 76 compatible = "renesas, << 77 reg = <0 0x10090000 0 << 78 interrupts = <GIC_SPI << 79 <GIC_SPI << 80 <GIC_SPI << 81 <GIC_SPI << 82 <GIC_SPI << 83 <GIC_SPI << 84 <GIC_SPI << 85 <GIC_SPI << 86 interrupt-names = "tei << 87 "nak << 88 clocks = <&cpg CPG_MOD << 89 clock-frequency = <100 << 90 resets = <&cpg R9A08G0 << 91 power-domains = <&cpg> << 92 #address-cells = <1>; << 93 #size-cells = <0>; << 94 status = "disabled"; << 95 }; << 96 << 97 i2c1: i2c@10090400 { << 98 compatible = "renesas, << 99 reg = <0 0x10090400 0 << 100 interrupts = <GIC_SPI << 101 <GIC_SPI << 102 <GIC_SPI << 103 <GIC_SPI << 104 <GIC_SPI << 105 <GIC_SPI << 106 <GIC_SPI << 107 <GIC_SPI << 108 interrupt-names = "tei << 109 "nak << 110 clocks = <&cpg CPG_MOD << 111 clock-frequency = <100 << 112 resets = <&cpg R9A08G0 << 113 power-domains = <&cpg> << 114 #address-cells = <1>; << 115 #size-cells = <0>; << 116 status = "disabled"; << 117 }; << 118 << 119 i2c2: i2c@10090800 { << 120 compatible = "renesas, << 121 reg = <0 0x10090800 0 << 122 interrupts = <GIC_SPI << 123 <GIC_SPI << 124 <GIC_SPI << 125 <GIC_SPI << 126 <GIC_SPI << 127 <GIC_SPI << 128 <GIC_SPI << 129 <GIC_SPI << 130 interrupt-names = "tei << 131 "nak << 132 clocks = <&cpg CPG_MOD << 133 clock-frequency = <100 << 134 resets = <&cpg R9A08G0 << 135 power-domains = <&cpg> << 136 #address-cells = <1>; << 137 #size-cells = <0>; << 138 status = "disabled"; << 139 }; << 140 << 141 i2c3: i2c@10090c00 { << 142 compatible = "renesas, << 143 reg = <0 0x10090c00 0 << 144 interrupts = <GIC_SPI << 145 <GIC_SPI << 146 <GIC_SPI << 147 <GIC_SPI << 148 <GIC_SPI << 149 <GIC_SPI << 150 <GIC_SPI << 151 <GIC_SPI << 152 interrupt-names = "tei << 153 "nak << 154 clocks = <&cpg CPG_MOD << 155 clock-frequency = <100 << 156 resets = <&cpg R9A08G0 << 157 power-domains = <&cpg> << 158 #address-cells = <1>; << 159 #size-cells = <0>; << 160 status = "disabled"; << 161 }; << 162 << 163 cpg: clock-controller@11010000 70 cpg: clock-controller@11010000 { 164 compatible = "renesas, 71 compatible = "renesas,r9a08g045-cpg"; 165 reg = <0 0x11010000 0 72 reg = <0 0x11010000 0 0x10000>; 166 clocks = <&extal_clk>; 73 clocks = <&extal_clk>; 167 clock-names = "extal"; 74 clock-names = "extal"; 168 #clock-cells = <2>; 75 #clock-cells = <2>; 169 #reset-cells = <1>; 76 #reset-cells = <1>; 170 #power-domain-cells = 77 #power-domain-cells = <0>; 171 }; 78 }; 172 79 173 sysc: system-controller@110200 80 sysc: system-controller@11020000 { 174 compatible = "renesas, 81 compatible = "renesas,r9a08g045-sysc"; 175 reg = <0 0x11020000 0 82 reg = <0 0x11020000 0 0x10000>; 176 interrupts = <GIC_SPI 83 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 177 <GIC_SPI 84 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 178 <GIC_SPI 85 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 179 <GIC_SPI 86 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 180 interrupt-names = "lpm 87 interrupt-names = "lpm_int", "ca55stbydone_int", 181 "cm3 88 "cm33stbyr_int", "ca55_deny"; 182 status = "disabled"; 89 status = "disabled"; 183 }; 90 }; 184 91 185 pinctrl: pinctrl@11030000 { 92 pinctrl: pinctrl@11030000 { 186 compatible = "renesas, 93 compatible = "renesas,r9a08g045-pinctrl"; 187 reg = <0 0x11030000 0 94 reg = <0 0x11030000 0 0x10000>; 188 gpio-controller; 95 gpio-controller; 189 #gpio-cells = <2>; 96 #gpio-cells = <2>; 190 interrupt-controller; 97 interrupt-controller; 191 #interrupt-cells = <2> 98 #interrupt-cells = <2>; 192 interrupt-parent = <&i << 193 gpio-ranges = <&pinctr 99 gpio-ranges = <&pinctrl 0 0 152>; 194 clocks = <&cpg CPG_MOD 100 clocks = <&cpg CPG_MOD R9A08G045_GPIO_HCLK>; 195 power-domains = <&cpg> 101 power-domains = <&cpg>; 196 resets = <&cpg R9A08G0 102 resets = <&cpg R9A08G045_GPIO_RSTN>, 197 <&cpg R9A08G0 103 <&cpg R9A08G045_GPIO_PORT_RESETN>, 198 <&cpg R9A08G0 104 <&cpg R9A08G045_GPIO_SPARE_RESETN>; 199 }; 105 }; 200 106 201 irqc: interrupt-controller@110 << 202 compatible = "renesas, << 203 #interrupt-cells = <2> << 204 #address-cells = <0>; << 205 interrupt-controller; << 206 reg = <0 0x11050000 0 << 207 interrupts = <GIC_SPI << 208 <GIC_SPI << 209 <GIC_SPI << 210 <GIC_SPI << 211 <GIC_SPI << 212 <GIC_SPI << 213 <GIC_SPI << 214 <GIC_SPI << 215 <GIC_SPI << 216 <GIC_SPI << 217 <GIC_SPI << 218 <GIC_SPI << 219 <GIC_SPI << 220 <GIC_SPI << 221 <GIC_SPI << 222 <GIC_SPI << 223 <GIC_SPI << 224 <GIC_SPI << 225 <GIC_SPI << 226 <GIC_SPI << 227 <GIC_SPI << 228 <GIC_SPI << 229 <GIC_SPI << 230 <GIC_SPI << 231 <GIC_SPI << 232 <GIC_SPI << 233 <GIC_SPI << 234 <GIC_SPI << 235 <GIC_SPI << 236 <GIC_SPI << 237 <GIC_SPI << 238 <GIC_SPI << 239 <GIC_SPI << 240 <GIC_SPI << 241 <GIC_SPI << 242 <GIC_SPI << 243 <GIC_SPI << 244 <GIC_SPI << 245 <GIC_SPI << 246 <GIC_SPI << 247 <GIC_SPI << 248 <GIC_SPI << 249 <GIC_SPI << 250 <GIC_SPI << 251 <GIC_SPI << 252 interrupt-names = "nmi << 253 "irq << 254 "irq << 255 "tin << 256 "tin << 257 "tin << 258 "tin << 259 "tin << 260 "tin << 261 "tin << 262 "tin << 263 "bus << 264 "ec7 << 265 clocks = <&cpg CPG_MOD << 266 <&cpg CPG_MOD << 267 clock-names = "clk", " << 268 power-domains = <&cpg> << 269 resets = <&cpg R9A08G0 << 270 }; << 271 << 272 dmac: dma-controller@11820000 << 273 compatible = "renesas, << 274 "renesas, << 275 reg = <0 0x11820000 0 << 276 <0 0x11830000 0 << 277 interrupts = <GIC_SPI << 278 <GIC_SPI << 279 <GIC_SPI << 280 <GIC_SPI << 281 <GIC_SPI << 282 <GIC_SPI << 283 <GIC_SPI << 284 <GIC_SPI << 285 <GIC_SPI << 286 <GIC_SPI << 287 <GIC_SPI << 288 <GIC_SPI << 289 <GIC_SPI << 290 <GIC_SPI << 291 <GIC_SPI << 292 <GIC_SPI << 293 <GIC_SPI << 294 interrupt-names = "err << 295 "ch0 << 296 "ch4 << 297 "ch8 << 298 "ch1 << 299 clocks = <&cpg CPG_MOD << 300 <&cpg CPG_MOD << 301 clock-names = "main", << 302 power-domains = <&cpg> << 303 resets = <&cpg R9A08G0 << 304 <&cpg R9A08G0 << 305 reset-names = "arst", << 306 #dma-cells = <1>; << 307 dma-channels = <16>; << 308 }; << 309 << 310 sdhi0: mmc@11c00000 { 107 sdhi0: mmc@11c00000 { 311 compatible = "renesas, !! 108 compatible = "renesas,sdhi-r9a08g045", "renesas,rcar-gen3-sdhi"; 312 reg = <0x0 0x11c00000 109 reg = <0x0 0x11c00000 0 0x10000>; 313 interrupts = <GIC_SPI 110 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 314 <GIC_SPI 111 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 315 clocks = <&cpg CPG_MOD 112 clocks = <&cpg CPG_MOD R9A08G045_SDHI0_IMCLK>, 316 <&cpg CPG_MOD 113 <&cpg CPG_MOD R9A08G045_SDHI0_CLK_HS>, 317 <&cpg CPG_MOD 114 <&cpg CPG_MOD R9A08G045_SDHI0_IMCLK2>, 318 <&cpg CPG_MOD 115 <&cpg CPG_MOD R9A08G045_SDHI0_ACLK>; 319 clock-names = "core", 116 clock-names = "core", "clkh", "cd", "aclk"; 320 resets = <&cpg R9A08G0 117 resets = <&cpg R9A08G045_SDHI0_IXRST>; 321 power-domains = <&cpg> 118 power-domains = <&cpg>; 322 status = "disabled"; 119 status = "disabled"; 323 }; 120 }; 324 121 325 sdhi1: mmc@11c10000 { 122 sdhi1: mmc@11c10000 { 326 compatible = "renesas, !! 123 compatible = "renesas,sdhi-r9a08g045", "renesas,rcar-gen3-sdhi"; 327 reg = <0x0 0x11c10000 124 reg = <0x0 0x11c10000 0 0x10000>; 328 interrupts = <GIC_SPI 125 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, 329 <GIC_SPI 126 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 330 clocks = <&cpg CPG_MOD 127 clocks = <&cpg CPG_MOD R9A08G045_SDHI1_IMCLK>, 331 <&cpg CPG_MOD 128 <&cpg CPG_MOD R9A08G045_SDHI1_CLK_HS>, 332 <&cpg CPG_MOD 129 <&cpg CPG_MOD R9A08G045_SDHI1_IMCLK2>, 333 <&cpg CPG_MOD 130 <&cpg CPG_MOD R9A08G045_SDHI1_ACLK>; 334 clock-names = "core", 131 clock-names = "core", "clkh", "cd", "aclk"; 335 resets = <&cpg R9A08G0 132 resets = <&cpg R9A08G045_SDHI1_IXRST>; 336 power-domains = <&cpg> 133 power-domains = <&cpg>; 337 status = "disabled"; 134 status = "disabled"; 338 }; 135 }; 339 136 340 sdhi2: mmc@11c20000 { 137 sdhi2: mmc@11c20000 { 341 compatible = "renesas, !! 138 compatible = "renesas,sdhi-r9a08g045", "renesas,rcar-gen3-sdhi"; 342 reg = <0x0 0x11c20000 139 reg = <0x0 0x11c20000 0 0x10000>; 343 interrupts = <GIC_SPI 140 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, 344 <GIC_SPI 141 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 345 clocks = <&cpg CPG_MOD 142 clocks = <&cpg CPG_MOD R9A08G045_SDHI2_IMCLK>, 346 <&cpg CPG_MOD 143 <&cpg CPG_MOD R9A08G045_SDHI2_CLK_HS>, 347 <&cpg CPG_MOD 144 <&cpg CPG_MOD R9A08G045_SDHI2_IMCLK2>, 348 <&cpg CPG_MOD 145 <&cpg CPG_MOD R9A08G045_SDHI2_ACLK>; 349 clock-names = "core", 146 clock-names = "core", "clkh", "cd", "aclk"; 350 resets = <&cpg R9A08G0 147 resets = <&cpg R9A08G045_SDHI2_IXRST>; 351 power-domains = <&cpg> 148 power-domains = <&cpg>; 352 status = "disabled"; 149 status = "disabled"; 353 }; 150 }; 354 151 355 eth0: ethernet@11c30000 { << 356 compatible = "renesas, << 357 reg = <0 0x11c30000 0 << 358 interrupts = <GIC_SPI << 359 <GIC_SPI << 360 <GIC_SPI << 361 interrupt-names = "mux << 362 phy-mode = "rgmii"; << 363 clocks = <&cpg CPG_MOD << 364 <&cpg CPG_MOD << 365 <&cpg CPG_MOD << 366 clock-names = "axi", " << 367 resets = <&cpg R9A08G0 << 368 power-domains = <&cpg> << 369 #address-cells = <1>; << 370 #size-cells = <0>; << 371 status = "disabled"; << 372 }; << 373 << 374 eth1: ethernet@11c40000 { << 375 compatible = "renesas, << 376 reg = <0 0x11c40000 0 << 377 interrupts = <GIC_SPI << 378 <GIC_SPI << 379 <GIC_SPI << 380 interrupt-names = "mux << 381 phy-mode = "rgmii"; << 382 clocks = <&cpg CPG_MOD << 383 <&cpg CPG_MOD << 384 <&cpg CPG_MOD << 385 clock-names = "axi", " << 386 resets = <&cpg R9A08G0 << 387 power-domains = <&cpg> << 388 #address-cells = <1>; << 389 #size-cells = <0>; << 390 status = "disabled"; << 391 }; << 392 << 393 gic: interrupt-controller@1240 152 gic: interrupt-controller@12400000 { 394 compatible = "arm,gic- 153 compatible = "arm,gic-v3"; 395 #interrupt-cells = <3> 154 #interrupt-cells = <3>; 396 #address-cells = <0>; 155 #address-cells = <0>; 397 interrupt-controller; 156 interrupt-controller; 398 reg = <0x0 0x12400000 !! 157 reg = <0x0 0x12400000 0 0x40000>, 399 <0x0 0x12440000 !! 158 <0x0 0x12440000 0 0x60000>; 400 interrupts = <GIC_PPI 159 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; 401 }; 160 }; 402 << 403 wdt0: watchdog@12800800 { << 404 compatible = "renesas, << 405 reg = <0 0x12800800 0 << 406 clocks = <&cpg CPG_MOD << 407 <&cpg CPG_MOD << 408 clock-names = "pclk", << 409 interrupts = <GIC_SPI << 410 <GIC_SPI << 411 interrupt-names = "wdt << 412 resets = <&cpg R9A08G0 << 413 power-domains = <&cpg> << 414 status = "disabled"; << 415 }; << 416 }; 161 }; 417 162 418 timer { 163 timer { 419 compatible = "arm,armv8-timer" 164 compatible = "arm,armv8-timer"; 420 interrupts-extended = <&gic GI 165 interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 421 <&gic GI 166 <&gic GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 422 <&gic GI 167 <&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 423 <&gic GI !! 168 <&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 424 <&gic GI << 425 interrupt-names = "sec-phys", << 426 "hyp-virt"; << 427 }; 169 }; 428 }; 170 };

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TOMOYO Linux Cross Reference
Linux/scripts/dtc/include-prefixes/arm64/renesas/r9a08g045.dtsi