Linux/scripts/dtc/include-prefixes/arm64/renesas/r9a08g045.dtsi

Version: ~ [ linux-6.12-rc7 ] ~ [ linux-6.11.7 ] ~ [ linux-6.10.14 ] ~ [ linux-6.9.12 ] ~ [ linux-6.8.12 ] ~ [ linux-6.7.12 ] ~ [ linux-6.6.60 ] ~ [ linux-6.5.13 ] ~ [ linux-6.4.16 ] ~ [ linux-6.3.13 ] ~ [ linux-6.2.16 ] ~ [ linux-6.1.116 ] ~ [ linux-6.0.19 ] ~ [ linux-5.19.17 ] ~ [ linux-5.18.19 ] ~ [ linux-5.17.15 ] ~ [ linux-5.16.20 ] ~ [ linux-5.15.171 ] ~ [ linux-5.14.21 ] ~ [ linux-5.13.19 ] ~ [ linux-5.12.19 ] ~ [ linux-5.11.22 ] ~ [ linux-5.10.229 ] ~ [ linux-5.9.16 ] ~ [ linux-5.8.18 ] ~ [ linux-5.7.19 ] ~ [ linux-5.6.19 ] ~ [ linux-5.5.19 ] ~ [ linux-5.4.285 ] ~ [ linux-5.3.18 ] ~ [ linux-5.2.21 ] ~ [ linux-5.1.21 ] ~ [ linux-5.0.21 ] ~ [ linux-4.20.17 ] ~ [ linux-4.19.323 ] ~ [ linux-4.18.20 ] ~ [ linux-4.17.19 ] ~ [ linux-4.16.18 ] ~ [ linux-4.15.18 ] ~ [ linux-4.14.336 ] ~ [ linux-4.13.16 ] ~ [ linux-4.12.14 ] ~ [ linux-4.11.12 ] ~ [ linux-4.10.17 ] ~ [ linux-4.9.337 ] ~ [ linux-4.4.302 ] ~ [ linux-3.10.108 ] ~ [ linux-2.6.32.71 ] ~ [ linux-2.6.0 ] ~ [ linux-2.4.37.11 ] ~ [ unix-v6-master ] ~ [ ccs-tools-1.8.12 ] ~ [ policy-sample ] ~
Architecture: ~ [ i386 ] ~ [ alpha ] ~ [ m68k ] ~ [ mips ] ~ [ ppc ] ~ [ sparc ] ~ [ sparc64 ] ~

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1 // SPDX-License-Identifier: (GPL-2.0-only OR B 1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 /* 2 /* 3 * Device Tree Source for the RZ/G3S SoC 3 * Device Tree Source for the RZ/G3S SoC 4 * 4 * 5 * Copyright (C) 2023 Renesas Electronics Corp 5 * Copyright (C) 2023 Renesas Electronics Corp. 6 */ 6 */ 7 7 8 #include <dt-bindings/interrupt-controller/arm 8 #include <dt-bindings/interrupt-controller/arm-gic.h> 9 #include <dt-bindings/clock/r9a08g045-cpg.h> 9 #include <dt-bindings/clock/r9a08g045-cpg.h> 10 10 11 / { 11 / { 12 compatible = "renesas,r9a08g045"; 12 compatible = "renesas,r9a08g045"; 13 #address-cells = <2>; 13 #address-cells = <2>; 14 #size-cells = <2>; 14 #size-cells = <2>; 15 15 16 cpus { 16 cpus { 17 #address-cells = <1>; 17 #address-cells = <1>; 18 #size-cells = <0>; 18 #size-cells = <0>; 19 19 20 cpu0: cpu@0 { 20 cpu0: cpu@0 { 21 compatible = "arm,cort 21 compatible = "arm,cortex-a55"; 22 reg = <0>; 22 reg = <0>; 23 device_type = "cpu"; 23 device_type = "cpu"; 24 #cooling-cells = <2>; 24 #cooling-cells = <2>; 25 next-level-cache = <&L 25 next-level-cache = <&L3_CA55>; 26 enable-method = "psci" 26 enable-method = "psci"; 27 clocks = <&cpg CPG_COR 27 clocks = <&cpg CPG_CORE R9A08G045_CLK_I>; 28 }; 28 }; 29 29 30 L3_CA55: cache-controller-0 { 30 L3_CA55: cache-controller-0 { 31 compatible = "cache"; 31 compatible = "cache"; 32 cache-level = <3>; 32 cache-level = <3>; 33 cache-unified; 33 cache-unified; 34 cache-size = <0x40000> 34 cache-size = <0x40000>; 35 }; 35 }; 36 }; 36 }; 37 37 38 extal_clk: extal-clk { 38 extal_clk: extal-clk { 39 compatible = "fixed-clock"; 39 compatible = "fixed-clock"; 40 #clock-cells = <0>; 40 #clock-cells = <0>; 41 /* This value must be overridd 41 /* This value must be overridden by the board. */ 42 clock-frequency = <0>; 42 clock-frequency = <0>; 43 }; 43 }; 44 44 45 psci { << 46 compatible = "arm,psci-1.0", " << 47 method = "smc"; << 48 }; << 49 << 50 soc: soc { 45 soc: soc { 51 compatible = "simple-bus"; 46 compatible = "simple-bus"; 52 interrupt-parent = <&gic>; 47 interrupt-parent = <&gic>; 53 #address-cells = <2>; 48 #address-cells = <2>; 54 #size-cells = <2>; 49 #size-cells = <2>; 55 ranges; 50 ranges; 56 51 57 scif0: serial@1004b800 { 52 scif0: serial@1004b800 { 58 compatible = "renesas, 53 compatible = "renesas,scif-r9a08g045", "renesas,scif-r9a07g044"; 59 reg = <0 0x1004b800 0 54 reg = <0 0x1004b800 0 0x400>; 60 interrupts = <GIC_SPI 55 interrupts = <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 61 <GIC_SPI 56 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 62 <GIC_SPI 57 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 63 <GIC_SPI 58 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 64 <GIC_SPI 59 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 65 <GIC_SPI 60 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>; 66 interrupt-names = "eri 61 interrupt-names = "eri", "rxi", "txi", 67 "bri 62 "bri", "dri", "tei"; 68 clocks = <&cpg CPG_MOD 63 clocks = <&cpg CPG_MOD R9A08G045_SCIF0_CLK_PCK>; 69 clock-names = "fck"; 64 clock-names = "fck"; 70 power-domains = <&cpg> 65 power-domains = <&cpg>; 71 resets = <&cpg R9A08G0 66 resets = <&cpg R9A08G045_SCIF0_RST_SYSTEM_N>; 72 status = "disabled"; 67 status = "disabled"; 73 }; 68 }; 74 69 75 i2c0: i2c@10090000 { << 76 compatible = "renesas, << 77 reg = <0 0x10090000 0 << 78 interrupts = <GIC_SPI << 79 <GIC_SPI << 80 <GIC_SPI << 81 <GIC_SPI << 82 <GIC_SPI << 83 <GIC_SPI << 84 <GIC_SPI << 85 <GIC_SPI << 86 interrupt-names = "tei << 87 "nak << 88 clocks = <&cpg CPG_MOD << 89 clock-frequency = <100 << 90 resets = <&cpg R9A08G0 << 91 power-domains = <&cpg> << 92 #address-cells = <1>; << 93 #size-cells = <0>; << 94 status = "disabled"; << 95 }; << 96 << 97 i2c1: i2c@10090400 { << 98 compatible = "renesas, << 99 reg = <0 0x10090400 0 << 100 interrupts = <GIC_SPI << 101 <GIC_SPI << 102 <GIC_SPI << 103 <GIC_SPI << 104 <GIC_SPI << 105 <GIC_SPI << 106 <GIC_SPI << 107 <GIC_SPI << 108 interrupt-names = "tei << 109 "nak << 110 clocks = <&cpg CPG_MOD << 111 clock-frequency = <100 << 112 resets = <&cpg R9A08G0 << 113 power-domains = <&cpg> << 114 #address-cells = <1>; << 115 #size-cells = <0>; << 116 status = "disabled"; << 117 }; << 118 << 119 i2c2: i2c@10090800 { << 120 compatible = "renesas, << 121 reg = <0 0x10090800 0 << 122 interrupts = <GIC_SPI << 123 <GIC_SPI << 124 <GIC_SPI << 125 <GIC_SPI << 126 <GIC_SPI << 127 <GIC_SPI << 128 <GIC_SPI << 129 <GIC_SPI << 130 interrupt-names = "tei << 131 "nak << 132 clocks = <&cpg CPG_MOD << 133 clock-frequency = <100 << 134 resets = <&cpg R9A08G0 << 135 power-domains = <&cpg> << 136 #address-cells = <1>; << 137 #size-cells = <0>; << 138 status = "disabled"; << 139 }; << 140 << 141 i2c3: i2c@10090c00 { << 142 compatible = "renesas, << 143 reg = <0 0x10090c00 0 << 144 interrupts = <GIC_SPI << 145 <GIC_SPI << 146 <GIC_SPI << 147 <GIC_SPI << 148 <GIC_SPI << 149 <GIC_SPI << 150 <GIC_SPI << 151 <GIC_SPI << 152 interrupt-names = "tei << 153 "nak << 154 clocks = <&cpg CPG_MOD << 155 clock-frequency = <100 << 156 resets = <&cpg R9A08G0 << 157 power-domains = <&cpg> << 158 #address-cells = <1>; << 159 #size-cells = <0>; << 160 status = "disabled"; << 161 }; << 162 << 163 cpg: clock-controller@11010000 70 cpg: clock-controller@11010000 { 164 compatible = "renesas, 71 compatible = "renesas,r9a08g045-cpg"; 165 reg = <0 0x11010000 0 72 reg = <0 0x11010000 0 0x10000>; 166 clocks = <&extal_clk>; 73 clocks = <&extal_clk>; 167 clock-names = "extal"; 74 clock-names = "extal"; 168 #clock-cells = <2>; 75 #clock-cells = <2>; 169 #reset-cells = <1>; 76 #reset-cells = <1>; 170 #power-domain-cells = 77 #power-domain-cells = <0>; 171 }; 78 }; 172 79 173 sysc: system-controller@110200 80 sysc: system-controller@11020000 { 174 compatible = "renesas, 81 compatible = "renesas,r9a08g045-sysc"; 175 reg = <0 0x11020000 0 82 reg = <0 0x11020000 0 0x10000>; 176 interrupts = <GIC_SPI 83 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 177 <GIC_SPI 84 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 178 <GIC_SPI 85 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 179 <GIC_SPI 86 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 180 interrupt-names = "lpm 87 interrupt-names = "lpm_int", "ca55stbydone_int", 181 "cm3 88 "cm33stbyr_int", "ca55_deny"; 182 status = "disabled"; 89 status = "disabled"; 183 }; 90 }; 184 91 185 pinctrl: pinctrl@11030000 { 92 pinctrl: pinctrl@11030000 { 186 compatible = "renesas, 93 compatible = "renesas,r9a08g045-pinctrl"; 187 reg = <0 0x11030000 0 94 reg = <0 0x11030000 0 0x10000>; 188 gpio-controller; 95 gpio-controller; 189 #gpio-cells = <2>; 96 #gpio-cells = <2>; 190 interrupt-controller; 97 interrupt-controller; 191 #interrupt-cells = <2> 98 #interrupt-cells = <2>; 192 interrupt-parent = <&i 99 interrupt-parent = <&irqc>; 193 gpio-ranges = <&pinctr 100 gpio-ranges = <&pinctrl 0 0 152>; 194 clocks = <&cpg CPG_MOD 101 clocks = <&cpg CPG_MOD R9A08G045_GPIO_HCLK>; 195 power-domains = <&cpg> 102 power-domains = <&cpg>; 196 resets = <&cpg R9A08G0 103 resets = <&cpg R9A08G045_GPIO_RSTN>, 197 <&cpg R9A08G0 104 <&cpg R9A08G045_GPIO_PORT_RESETN>, 198 <&cpg R9A08G0 105 <&cpg R9A08G045_GPIO_SPARE_RESETN>; 199 }; 106 }; 200 107 201 irqc: interrupt-controller@110 108 irqc: interrupt-controller@11050000 { 202 compatible = "renesas, 109 compatible = "renesas,r9a08g045-irqc", "renesas,rzg2l-irqc"; 203 #interrupt-cells = <2> 110 #interrupt-cells = <2>; 204 #address-cells = <0>; 111 #address-cells = <0>; 205 interrupt-controller; 112 interrupt-controller; 206 reg = <0 0x11050000 0 113 reg = <0 0x11050000 0 0x10000>; 207 interrupts = <GIC_SPI 114 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 208 <GIC_SPI 115 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 209 <GIC_SPI 116 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 210 <GIC_SPI 117 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 211 <GIC_SPI 118 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 212 <GIC_SPI 119 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 213 <GIC_SPI 120 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 214 <GIC_SPI 121 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 215 <GIC_SPI 122 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 216 <GIC_SPI 123 <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>, 217 <GIC_SPI 124 <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>, 218 <GIC_SPI 125 <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH>, 219 <GIC_SPI 126 <GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>, 220 <GIC_SPI 127 <GIC_SPI 433 IRQ_TYPE_LEVEL_HIGH>, 221 <GIC_SPI 128 <GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>, 222 <GIC_SPI 129 <GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>, 223 <GIC_SPI 130 <GIC_SPI 436 IRQ_TYPE_LEVEL_HIGH>, 224 <GIC_SPI 131 <GIC_SPI 437 IRQ_TYPE_LEVEL_HIGH>, 225 <GIC_SPI 132 <GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>, 226 <GIC_SPI 133 <GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>, 227 <GIC_SPI 134 <GIC_SPI 440 IRQ_TYPE_LEVEL_HIGH>, 228 <GIC_SPI 135 <GIC_SPI 441 IRQ_TYPE_LEVEL_HIGH>, 229 <GIC_SPI 136 <GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>, 230 <GIC_SPI 137 <GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>, 231 <GIC_SPI 138 <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>, 232 <GIC_SPI 139 <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>, 233 <GIC_SPI 140 <GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>, 234 <GIC_SPI 141 <GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>, 235 <GIC_SPI 142 <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>, 236 <GIC_SPI 143 <GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>, 237 <GIC_SPI 144 <GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH>, 238 <GIC_SPI 145 <GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>, 239 <GIC_SPI 146 <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>, 240 <GIC_SPI 147 <GIC_SPI 453 IRQ_TYPE_LEVEL_HIGH>, 241 <GIC_SPI 148 <GIC_SPI 454 IRQ_TYPE_LEVEL_HIGH>, 242 <GIC_SPI 149 <GIC_SPI 455 IRQ_TYPE_LEVEL_HIGH>, 243 <GIC_SPI 150 <GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>, 244 <GIC_SPI 151 <GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>, 245 <GIC_SPI 152 <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>, 246 <GIC_SPI 153 <GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>, 247 <GIC_SPI 154 <GIC_SPI 460 IRQ_TYPE_LEVEL_HIGH>, 248 <GIC_SPI 155 <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 249 <GIC_SPI 156 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 250 <GIC_SPI 157 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 251 <GIC_SPI 158 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 252 interrupt-names = "nmi 159 interrupt-names = "nmi", 253 "irq 160 "irq0", "irq1", "irq2", "irq3", 254 "irq 161 "irq4", "irq5", "irq6", "irq7", 255 "tin 162 "tint0", "tint1", "tint2", "tint3", 256 "tin 163 "tint4", "tint5", "tint6", "tint7", 257 "tin 164 "tint8", "tint9", "tint10", "tint11", 258 "tin 165 "tint12", "tint13", "tint14", "tint15", 259 "tin 166 "tint16", "tint17", "tint18", "tint19", 260 "tin 167 "tint20", "tint21", "tint22", "tint23", 261 "tin 168 "tint24", "tint25", "tint26", "tint27", 262 "tin 169 "tint28", "tint29", "tint30", "tint31", 263 "bus 170 "bus-err", "ec7tie1-0", "ec7tie2-0", 264 "ec7 171 "ec7tiovf-0"; 265 clocks = <&cpg CPG_MOD 172 clocks = <&cpg CPG_MOD R9A08G045_IA55_CLK>, 266 <&cpg CPG_MOD 173 <&cpg CPG_MOD R9A08G045_IA55_PCLK>; 267 clock-names = "clk", " 174 clock-names = "clk", "pclk"; 268 power-domains = <&cpg> 175 power-domains = <&cpg>; 269 resets = <&cpg R9A08G0 176 resets = <&cpg R9A08G045_IA55_RESETN>; 270 }; 177 }; 271 178 272 dmac: dma-controller@11820000 << 273 compatible = "renesas, << 274 "renesas, << 275 reg = <0 0x11820000 0 << 276 <0 0x11830000 0 << 277 interrupts = <GIC_SPI << 278 <GIC_SPI << 279 <GIC_SPI << 280 <GIC_SPI << 281 <GIC_SPI << 282 <GIC_SPI << 283 <GIC_SPI << 284 <GIC_SPI << 285 <GIC_SPI << 286 <GIC_SPI << 287 <GIC_SPI << 288 <GIC_SPI << 289 <GIC_SPI << 290 <GIC_SPI << 291 <GIC_SPI << 292 <GIC_SPI << 293 <GIC_SPI << 294 interrupt-names = "err << 295 "ch0 << 296 "ch4 << 297 "ch8 << 298 "ch1 << 299 clocks = <&cpg CPG_MOD << 300 <&cpg CPG_MOD << 301 clock-names = "main", << 302 power-domains = <&cpg> << 303 resets = <&cpg R9A08G0 << 304 <&cpg R9A08G0 << 305 reset-names = "arst", << 306 #dma-cells = <1>; << 307 dma-channels = <16>; << 308 }; << 309 << 310 sdhi0: mmc@11c00000 { 179 sdhi0: mmc@11c00000 { 311 compatible = "renesas, !! 180 compatible = "renesas,sdhi-r9a08g045", "renesas,rcar-gen3-sdhi"; 312 reg = <0x0 0x11c00000 181 reg = <0x0 0x11c00000 0 0x10000>; 313 interrupts = <GIC_SPI 182 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 314 <GIC_SPI 183 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 315 clocks = <&cpg CPG_MOD 184 clocks = <&cpg CPG_MOD R9A08G045_SDHI0_IMCLK>, 316 <&cpg CPG_MOD 185 <&cpg CPG_MOD R9A08G045_SDHI0_CLK_HS>, 317 <&cpg CPG_MOD 186 <&cpg CPG_MOD R9A08G045_SDHI0_IMCLK2>, 318 <&cpg CPG_MOD 187 <&cpg CPG_MOD R9A08G045_SDHI0_ACLK>; 319 clock-names = "core", 188 clock-names = "core", "clkh", "cd", "aclk"; 320 resets = <&cpg R9A08G0 189 resets = <&cpg R9A08G045_SDHI0_IXRST>; 321 power-domains = <&cpg> 190 power-domains = <&cpg>; 322 status = "disabled"; 191 status = "disabled"; 323 }; 192 }; 324 193 325 sdhi1: mmc@11c10000 { 194 sdhi1: mmc@11c10000 { 326 compatible = "renesas, !! 195 compatible = "renesas,sdhi-r9a08g045", "renesas,rcar-gen3-sdhi"; 327 reg = <0x0 0x11c10000 196 reg = <0x0 0x11c10000 0 0x10000>; 328 interrupts = <GIC_SPI 197 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, 329 <GIC_SPI 198 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 330 clocks = <&cpg CPG_MOD 199 clocks = <&cpg CPG_MOD R9A08G045_SDHI1_IMCLK>, 331 <&cpg CPG_MOD 200 <&cpg CPG_MOD R9A08G045_SDHI1_CLK_HS>, 332 <&cpg CPG_MOD 201 <&cpg CPG_MOD R9A08G045_SDHI1_IMCLK2>, 333 <&cpg CPG_MOD 202 <&cpg CPG_MOD R9A08G045_SDHI1_ACLK>; 334 clock-names = "core", 203 clock-names = "core", "clkh", "cd", "aclk"; 335 resets = <&cpg R9A08G0 204 resets = <&cpg R9A08G045_SDHI1_IXRST>; 336 power-domains = <&cpg> 205 power-domains = <&cpg>; 337 status = "disabled"; 206 status = "disabled"; 338 }; 207 }; 339 208 340 sdhi2: mmc@11c20000 { 209 sdhi2: mmc@11c20000 { 341 compatible = "renesas, !! 210 compatible = "renesas,sdhi-r9a08g045", "renesas,rcar-gen3-sdhi"; 342 reg = <0x0 0x11c20000 211 reg = <0x0 0x11c20000 0 0x10000>; 343 interrupts = <GIC_SPI 212 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, 344 <GIC_SPI 213 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 345 clocks = <&cpg CPG_MOD 214 clocks = <&cpg CPG_MOD R9A08G045_SDHI2_IMCLK>, 346 <&cpg CPG_MOD 215 <&cpg CPG_MOD R9A08G045_SDHI2_CLK_HS>, 347 <&cpg CPG_MOD 216 <&cpg CPG_MOD R9A08G045_SDHI2_IMCLK2>, 348 <&cpg CPG_MOD 217 <&cpg CPG_MOD R9A08G045_SDHI2_ACLK>; 349 clock-names = "core", 218 clock-names = "core", "clkh", "cd", "aclk"; 350 resets = <&cpg R9A08G0 219 resets = <&cpg R9A08G045_SDHI2_IXRST>; 351 power-domains = <&cpg> 220 power-domains = <&cpg>; 352 status = "disabled"; 221 status = "disabled"; 353 }; 222 }; 354 223 355 eth0: ethernet@11c30000 { 224 eth0: ethernet@11c30000 { 356 compatible = "renesas, 225 compatible = "renesas,r9a08g045-gbeth", "renesas,rzg2l-gbeth"; 357 reg = <0 0x11c30000 0 226 reg = <0 0x11c30000 0 0x10000>; 358 interrupts = <GIC_SPI 227 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 359 <GIC_SPI 228 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, 360 <GIC_SPI 229 <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 361 interrupt-names = "mux 230 interrupt-names = "mux", "fil", "arp_ns"; 362 phy-mode = "rgmii"; 231 phy-mode = "rgmii"; 363 clocks = <&cpg CPG_MOD 232 clocks = <&cpg CPG_MOD R9A08G045_ETH0_CLK_AXI>, 364 <&cpg CPG_MOD 233 <&cpg CPG_MOD R9A08G045_ETH0_CLK_CHI>, 365 <&cpg CPG_MOD 234 <&cpg CPG_MOD R9A08G045_ETH0_REFCLK>; 366 clock-names = "axi", " 235 clock-names = "axi", "chi", "refclk"; 367 resets = <&cpg R9A08G0 236 resets = <&cpg R9A08G045_ETH0_RST_HW_N>; 368 power-domains = <&cpg> 237 power-domains = <&cpg>; 369 #address-cells = <1>; 238 #address-cells = <1>; 370 #size-cells = <0>; 239 #size-cells = <0>; 371 status = "disabled"; 240 status = "disabled"; 372 }; 241 }; 373 242 374 eth1: ethernet@11c40000 { 243 eth1: ethernet@11c40000 { 375 compatible = "renesas, 244 compatible = "renesas,r9a08g045-gbeth", "renesas,rzg2l-gbeth"; 376 reg = <0 0x11c40000 0 245 reg = <0 0x11c40000 0 0x10000>; 377 interrupts = <GIC_SPI 246 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>, 378 <GIC_SPI 247 <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 379 <GIC_SPI 248 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 380 interrupt-names = "mux 249 interrupt-names = "mux", "fil", "arp_ns"; 381 phy-mode = "rgmii"; 250 phy-mode = "rgmii"; 382 clocks = <&cpg CPG_MOD 251 clocks = <&cpg CPG_MOD R9A08G045_ETH1_CLK_AXI>, 383 <&cpg CPG_MOD 252 <&cpg CPG_MOD R9A08G045_ETH1_CLK_CHI>, 384 <&cpg CPG_MOD 253 <&cpg CPG_MOD R9A08G045_ETH1_REFCLK>; 385 clock-names = "axi", " 254 clock-names = "axi", "chi", "refclk"; 386 resets = <&cpg R9A08G0 255 resets = <&cpg R9A08G045_ETH1_RST_HW_N>; 387 power-domains = <&cpg> 256 power-domains = <&cpg>; 388 #address-cells = <1>; 257 #address-cells = <1>; 389 #size-cells = <0>; 258 #size-cells = <0>; 390 status = "disabled"; 259 status = "disabled"; 391 }; 260 }; 392 261 393 gic: interrupt-controller@1240 262 gic: interrupt-controller@12400000 { 394 compatible = "arm,gic- 263 compatible = "arm,gic-v3"; 395 #interrupt-cells = <3> 264 #interrupt-cells = <3>; 396 #address-cells = <0>; 265 #address-cells = <0>; 397 interrupt-controller; 266 interrupt-controller; 398 reg = <0x0 0x12400000 !! 267 reg = <0x0 0x12400000 0 0x40000>, 399 <0x0 0x12440000 !! 268 <0x0 0x12440000 0 0x60000>; 400 interrupts = <GIC_PPI 269 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; 401 }; 270 }; 402 << 403 wdt0: watchdog@12800800 { << 404 compatible = "renesas, << 405 reg = <0 0x12800800 0 << 406 clocks = <&cpg CPG_MOD << 407 <&cpg CPG_MOD << 408 clock-names = "pclk", << 409 interrupts = <GIC_SPI << 410 <GIC_SPI << 411 interrupt-names = "wdt << 412 resets = <&cpg R9A08G0 << 413 power-domains = <&cpg> << 414 status = "disabled"; << 415 }; << 416 }; 271 }; 417 272 418 timer { 273 timer { 419 compatible = "arm,armv8-timer" 274 compatible = "arm,armv8-timer"; 420 interrupts-extended = <&gic GI 275 interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 421 <&gic GI 276 <&gic GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 422 <&gic GI 277 <&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 423 <&gic GI !! 278 <&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 424 <&gic GI << 425 interrupt-names = "sec-phys", << 426 "hyp-virt"; << 427 }; 279 }; 428 }; 280 };

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Linux/scripts/dtc/include-prefixes/arm64/renesas/r9a08g045.dtsi