1 // SPDX-License-Identifier: (GPL-2.0-only OR B 1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 /* 2 /*
3 * Device Tree Source for the RZ/G3S SoC 3 * Device Tree Source for the RZ/G3S SoC
4 * 4 *
5 * Copyright (C) 2023 Renesas Electronics Corp 5 * Copyright (C) 2023 Renesas Electronics Corp.
6 */ 6 */
7 7
8 #include <dt-bindings/interrupt-controller/arm 8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/clock/r9a08g045-cpg.h> 9 #include <dt-bindings/clock/r9a08g045-cpg.h>
10 10
11 / { 11 / {
12 compatible = "renesas,r9a08g045"; 12 compatible = "renesas,r9a08g045";
13 #address-cells = <2>; 13 #address-cells = <2>;
14 #size-cells = <2>; 14 #size-cells = <2>;
15 15
16 cpus { 16 cpus {
17 #address-cells = <1>; 17 #address-cells = <1>;
18 #size-cells = <0>; 18 #size-cells = <0>;
19 19
20 cpu0: cpu@0 { 20 cpu0: cpu@0 {
21 compatible = "arm,cort 21 compatible = "arm,cortex-a55";
22 reg = <0>; 22 reg = <0>;
23 device_type = "cpu"; 23 device_type = "cpu";
24 #cooling-cells = <2>; 24 #cooling-cells = <2>;
25 next-level-cache = <&L 25 next-level-cache = <&L3_CA55>;
26 enable-method = "psci" 26 enable-method = "psci";
27 clocks = <&cpg CPG_COR 27 clocks = <&cpg CPG_CORE R9A08G045_CLK_I>;
28 }; 28 };
29 29
30 L3_CA55: cache-controller-0 { 30 L3_CA55: cache-controller-0 {
31 compatible = "cache"; 31 compatible = "cache";
32 cache-level = <3>; 32 cache-level = <3>;
33 cache-unified; 33 cache-unified;
34 cache-size = <0x40000> 34 cache-size = <0x40000>;
35 }; 35 };
36 }; 36 };
37 37
38 extal_clk: extal-clk { 38 extal_clk: extal-clk {
39 compatible = "fixed-clock"; 39 compatible = "fixed-clock";
40 #clock-cells = <0>; 40 #clock-cells = <0>;
41 /* This value must be overridd 41 /* This value must be overridden by the board. */
42 clock-frequency = <0>; 42 clock-frequency = <0>;
43 }; 43 };
44 44
45 psci { 45 psci {
46 compatible = "arm,psci-1.0", " 46 compatible = "arm,psci-1.0", "arm,psci-0.2";
47 method = "smc"; 47 method = "smc";
48 }; 48 };
49 49
50 soc: soc { 50 soc: soc {
51 compatible = "simple-bus"; 51 compatible = "simple-bus";
52 interrupt-parent = <&gic>; 52 interrupt-parent = <&gic>;
53 #address-cells = <2>; 53 #address-cells = <2>;
54 #size-cells = <2>; 54 #size-cells = <2>;
55 ranges; 55 ranges;
56 56
57 scif0: serial@1004b800 { 57 scif0: serial@1004b800 {
58 compatible = "renesas, 58 compatible = "renesas,scif-r9a08g045", "renesas,scif-r9a07g044";
59 reg = <0 0x1004b800 0 59 reg = <0 0x1004b800 0 0x400>;
60 interrupts = <GIC_SPI 60 interrupts = <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
61 <GIC_SPI 61 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
62 <GIC_SPI 62 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
63 <GIC_SPI 63 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
64 <GIC_SPI 64 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
65 <GIC_SPI 65 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>;
66 interrupt-names = "eri 66 interrupt-names = "eri", "rxi", "txi",
67 "bri 67 "bri", "dri", "tei";
68 clocks = <&cpg CPG_MOD 68 clocks = <&cpg CPG_MOD R9A08G045_SCIF0_CLK_PCK>;
69 clock-names = "fck"; 69 clock-names = "fck";
70 power-domains = <&cpg> 70 power-domains = <&cpg>;
71 resets = <&cpg R9A08G0 71 resets = <&cpg R9A08G045_SCIF0_RST_SYSTEM_N>;
72 status = "disabled"; 72 status = "disabled";
73 }; 73 };
74 74
75 i2c0: i2c@10090000 { <<
76 compatible = "renesas, <<
77 reg = <0 0x10090000 0 <<
78 interrupts = <GIC_SPI <<
79 <GIC_SPI <<
80 <GIC_SPI <<
81 <GIC_SPI <<
82 <GIC_SPI <<
83 <GIC_SPI <<
84 <GIC_SPI <<
85 <GIC_SPI <<
86 interrupt-names = "tei <<
87 "nak <<
88 clocks = <&cpg CPG_MOD <<
89 clock-frequency = <100 <<
90 resets = <&cpg R9A08G0 <<
91 power-domains = <&cpg> <<
92 #address-cells = <1>; <<
93 #size-cells = <0>; <<
94 status = "disabled"; <<
95 }; <<
96 <<
97 i2c1: i2c@10090400 { <<
98 compatible = "renesas, <<
99 reg = <0 0x10090400 0 <<
100 interrupts = <GIC_SPI <<
101 <GIC_SPI <<
102 <GIC_SPI <<
103 <GIC_SPI <<
104 <GIC_SPI <<
105 <GIC_SPI <<
106 <GIC_SPI <<
107 <GIC_SPI <<
108 interrupt-names = "tei <<
109 "nak <<
110 clocks = <&cpg CPG_MOD <<
111 clock-frequency = <100 <<
112 resets = <&cpg R9A08G0 <<
113 power-domains = <&cpg> <<
114 #address-cells = <1>; <<
115 #size-cells = <0>; <<
116 status = "disabled"; <<
117 }; <<
118 <<
119 i2c2: i2c@10090800 { <<
120 compatible = "renesas, <<
121 reg = <0 0x10090800 0 <<
122 interrupts = <GIC_SPI <<
123 <GIC_SPI <<
124 <GIC_SPI <<
125 <GIC_SPI <<
126 <GIC_SPI <<
127 <GIC_SPI <<
128 <GIC_SPI <<
129 <GIC_SPI <<
130 interrupt-names = "tei <<
131 "nak <<
132 clocks = <&cpg CPG_MOD <<
133 clock-frequency = <100 <<
134 resets = <&cpg R9A08G0 <<
135 power-domains = <&cpg> <<
136 #address-cells = <1>; <<
137 #size-cells = <0>; <<
138 status = "disabled"; <<
139 }; <<
140 <<
141 i2c3: i2c@10090c00 { <<
142 compatible = "renesas, <<
143 reg = <0 0x10090c00 0 <<
144 interrupts = <GIC_SPI <<
145 <GIC_SPI <<
146 <GIC_SPI <<
147 <GIC_SPI <<
148 <GIC_SPI <<
149 <GIC_SPI <<
150 <GIC_SPI <<
151 <GIC_SPI <<
152 interrupt-names = "tei <<
153 "nak <<
154 clocks = <&cpg CPG_MOD <<
155 clock-frequency = <100 <<
156 resets = <&cpg R9A08G0 <<
157 power-domains = <&cpg> <<
158 #address-cells = <1>; <<
159 #size-cells = <0>; <<
160 status = "disabled"; <<
161 }; <<
162 <<
163 cpg: clock-controller@11010000 75 cpg: clock-controller@11010000 {
164 compatible = "renesas, 76 compatible = "renesas,r9a08g045-cpg";
165 reg = <0 0x11010000 0 77 reg = <0 0x11010000 0 0x10000>;
166 clocks = <&extal_clk>; 78 clocks = <&extal_clk>;
167 clock-names = "extal"; 79 clock-names = "extal";
168 #clock-cells = <2>; 80 #clock-cells = <2>;
169 #reset-cells = <1>; 81 #reset-cells = <1>;
170 #power-domain-cells = 82 #power-domain-cells = <0>;
171 }; 83 };
172 84
173 sysc: system-controller@110200 85 sysc: system-controller@11020000 {
174 compatible = "renesas, 86 compatible = "renesas,r9a08g045-sysc";
175 reg = <0 0x11020000 0 87 reg = <0 0x11020000 0 0x10000>;
176 interrupts = <GIC_SPI 88 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
177 <GIC_SPI 89 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
178 <GIC_SPI 90 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
179 <GIC_SPI 91 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
180 interrupt-names = "lpm 92 interrupt-names = "lpm_int", "ca55stbydone_int",
181 "cm3 93 "cm33stbyr_int", "ca55_deny";
182 status = "disabled"; 94 status = "disabled";
183 }; 95 };
184 96
185 pinctrl: pinctrl@11030000 { 97 pinctrl: pinctrl@11030000 {
186 compatible = "renesas, 98 compatible = "renesas,r9a08g045-pinctrl";
187 reg = <0 0x11030000 0 99 reg = <0 0x11030000 0 0x10000>;
188 gpio-controller; 100 gpio-controller;
189 #gpio-cells = <2>; 101 #gpio-cells = <2>;
190 interrupt-controller; 102 interrupt-controller;
191 #interrupt-cells = <2> 103 #interrupt-cells = <2>;
192 interrupt-parent = <&i 104 interrupt-parent = <&irqc>;
193 gpio-ranges = <&pinctr 105 gpio-ranges = <&pinctrl 0 0 152>;
194 clocks = <&cpg CPG_MOD 106 clocks = <&cpg CPG_MOD R9A08G045_GPIO_HCLK>;
195 power-domains = <&cpg> 107 power-domains = <&cpg>;
196 resets = <&cpg R9A08G0 108 resets = <&cpg R9A08G045_GPIO_RSTN>,
197 <&cpg R9A08G0 109 <&cpg R9A08G045_GPIO_PORT_RESETN>,
198 <&cpg R9A08G0 110 <&cpg R9A08G045_GPIO_SPARE_RESETN>;
199 }; 111 };
200 112
201 irqc: interrupt-controller@110 113 irqc: interrupt-controller@11050000 {
202 compatible = "renesas, 114 compatible = "renesas,r9a08g045-irqc", "renesas,rzg2l-irqc";
203 #interrupt-cells = <2> 115 #interrupt-cells = <2>;
204 #address-cells = <0>; 116 #address-cells = <0>;
205 interrupt-controller; 117 interrupt-controller;
206 reg = <0 0x11050000 0 118 reg = <0 0x11050000 0 0x10000>;
207 interrupts = <GIC_SPI 119 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
208 <GIC_SPI 120 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
209 <GIC_SPI 121 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
210 <GIC_SPI 122 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
211 <GIC_SPI 123 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
212 <GIC_SPI 124 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
213 <GIC_SPI 125 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
214 <GIC_SPI 126 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
215 <GIC_SPI 127 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
216 <GIC_SPI 128 <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>,
217 <GIC_SPI 129 <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>,
218 <GIC_SPI 130 <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH>,
219 <GIC_SPI 131 <GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>,
220 <GIC_SPI 132 <GIC_SPI 433 IRQ_TYPE_LEVEL_HIGH>,
221 <GIC_SPI 133 <GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>,
222 <GIC_SPI 134 <GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>,
223 <GIC_SPI 135 <GIC_SPI 436 IRQ_TYPE_LEVEL_HIGH>,
224 <GIC_SPI 136 <GIC_SPI 437 IRQ_TYPE_LEVEL_HIGH>,
225 <GIC_SPI 137 <GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>,
226 <GIC_SPI 138 <GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>,
227 <GIC_SPI 139 <GIC_SPI 440 IRQ_TYPE_LEVEL_HIGH>,
228 <GIC_SPI 140 <GIC_SPI 441 IRQ_TYPE_LEVEL_HIGH>,
229 <GIC_SPI 141 <GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>,
230 <GIC_SPI 142 <GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>,
231 <GIC_SPI 143 <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>,
232 <GIC_SPI 144 <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>,
233 <GIC_SPI 145 <GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>,
234 <GIC_SPI 146 <GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>,
235 <GIC_SPI 147 <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>,
236 <GIC_SPI 148 <GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>,
237 <GIC_SPI 149 <GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH>,
238 <GIC_SPI 150 <GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>,
239 <GIC_SPI 151 <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>,
240 <GIC_SPI 152 <GIC_SPI 453 IRQ_TYPE_LEVEL_HIGH>,
241 <GIC_SPI 153 <GIC_SPI 454 IRQ_TYPE_LEVEL_HIGH>,
242 <GIC_SPI 154 <GIC_SPI 455 IRQ_TYPE_LEVEL_HIGH>,
243 <GIC_SPI 155 <GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>,
244 <GIC_SPI 156 <GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>,
245 <GIC_SPI 157 <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>,
246 <GIC_SPI 158 <GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>,
247 <GIC_SPI 159 <GIC_SPI 460 IRQ_TYPE_LEVEL_HIGH>,
248 <GIC_SPI 160 <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
249 <GIC_SPI 161 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
250 <GIC_SPI 162 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
251 <GIC_SPI 163 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
252 interrupt-names = "nmi 164 interrupt-names = "nmi",
253 "irq 165 "irq0", "irq1", "irq2", "irq3",
254 "irq 166 "irq4", "irq5", "irq6", "irq7",
255 "tin 167 "tint0", "tint1", "tint2", "tint3",
256 "tin 168 "tint4", "tint5", "tint6", "tint7",
257 "tin 169 "tint8", "tint9", "tint10", "tint11",
258 "tin 170 "tint12", "tint13", "tint14", "tint15",
259 "tin 171 "tint16", "tint17", "tint18", "tint19",
260 "tin 172 "tint20", "tint21", "tint22", "tint23",
261 "tin 173 "tint24", "tint25", "tint26", "tint27",
262 "tin 174 "tint28", "tint29", "tint30", "tint31",
263 "bus 175 "bus-err", "ec7tie1-0", "ec7tie2-0",
264 "ec7 176 "ec7tiovf-0";
265 clocks = <&cpg CPG_MOD 177 clocks = <&cpg CPG_MOD R9A08G045_IA55_CLK>,
266 <&cpg CPG_MOD 178 <&cpg CPG_MOD R9A08G045_IA55_PCLK>;
267 clock-names = "clk", " 179 clock-names = "clk", "pclk";
268 power-domains = <&cpg> 180 power-domains = <&cpg>;
269 resets = <&cpg R9A08G0 181 resets = <&cpg R9A08G045_IA55_RESETN>;
270 }; 182 };
271 183
272 dmac: dma-controller@11820000 <<
273 compatible = "renesas, <<
274 "renesas, <<
275 reg = <0 0x11820000 0 <<
276 <0 0x11830000 0 <<
277 interrupts = <GIC_SPI <<
278 <GIC_SPI <<
279 <GIC_SPI <<
280 <GIC_SPI <<
281 <GIC_SPI <<
282 <GIC_SPI <<
283 <GIC_SPI <<
284 <GIC_SPI <<
285 <GIC_SPI <<
286 <GIC_SPI <<
287 <GIC_SPI <<
288 <GIC_SPI <<
289 <GIC_SPI <<
290 <GIC_SPI <<
291 <GIC_SPI <<
292 <GIC_SPI <<
293 <GIC_SPI <<
294 interrupt-names = "err <<
295 "ch0 <<
296 "ch4 <<
297 "ch8 <<
298 "ch1 <<
299 clocks = <&cpg CPG_MOD <<
300 <&cpg CPG_MOD <<
301 clock-names = "main", <<
302 power-domains = <&cpg> <<
303 resets = <&cpg R9A08G0 <<
304 <&cpg R9A08G0 <<
305 reset-names = "arst", <<
306 #dma-cells = <1>; <<
307 dma-channels = <16>; <<
308 }; <<
309 <<
310 sdhi0: mmc@11c00000 { 184 sdhi0: mmc@11c00000 {
311 compatible = "renesas, !! 185 compatible = "renesas,sdhi-r9a08g045", "renesas,rcar-gen3-sdhi";
312 reg = <0x0 0x11c00000 186 reg = <0x0 0x11c00000 0 0x10000>;
313 interrupts = <GIC_SPI 187 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
314 <GIC_SPI 188 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
315 clocks = <&cpg CPG_MOD 189 clocks = <&cpg CPG_MOD R9A08G045_SDHI0_IMCLK>,
316 <&cpg CPG_MOD 190 <&cpg CPG_MOD R9A08G045_SDHI0_CLK_HS>,
317 <&cpg CPG_MOD 191 <&cpg CPG_MOD R9A08G045_SDHI0_IMCLK2>,
318 <&cpg CPG_MOD 192 <&cpg CPG_MOD R9A08G045_SDHI0_ACLK>;
319 clock-names = "core", 193 clock-names = "core", "clkh", "cd", "aclk";
320 resets = <&cpg R9A08G0 194 resets = <&cpg R9A08G045_SDHI0_IXRST>;
321 power-domains = <&cpg> 195 power-domains = <&cpg>;
322 status = "disabled"; 196 status = "disabled";
323 }; 197 };
324 198
325 sdhi1: mmc@11c10000 { 199 sdhi1: mmc@11c10000 {
326 compatible = "renesas, !! 200 compatible = "renesas,sdhi-r9a08g045", "renesas,rcar-gen3-sdhi";
327 reg = <0x0 0x11c10000 201 reg = <0x0 0x11c10000 0 0x10000>;
328 interrupts = <GIC_SPI 202 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
329 <GIC_SPI 203 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
330 clocks = <&cpg CPG_MOD 204 clocks = <&cpg CPG_MOD R9A08G045_SDHI1_IMCLK>,
331 <&cpg CPG_MOD 205 <&cpg CPG_MOD R9A08G045_SDHI1_CLK_HS>,
332 <&cpg CPG_MOD 206 <&cpg CPG_MOD R9A08G045_SDHI1_IMCLK2>,
333 <&cpg CPG_MOD 207 <&cpg CPG_MOD R9A08G045_SDHI1_ACLK>;
334 clock-names = "core", 208 clock-names = "core", "clkh", "cd", "aclk";
335 resets = <&cpg R9A08G0 209 resets = <&cpg R9A08G045_SDHI1_IXRST>;
336 power-domains = <&cpg> 210 power-domains = <&cpg>;
337 status = "disabled"; 211 status = "disabled";
338 }; 212 };
339 213
340 sdhi2: mmc@11c20000 { 214 sdhi2: mmc@11c20000 {
341 compatible = "renesas, !! 215 compatible = "renesas,sdhi-r9a08g045", "renesas,rcar-gen3-sdhi";
342 reg = <0x0 0x11c20000 216 reg = <0x0 0x11c20000 0 0x10000>;
343 interrupts = <GIC_SPI 217 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
344 <GIC_SPI 218 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
345 clocks = <&cpg CPG_MOD 219 clocks = <&cpg CPG_MOD R9A08G045_SDHI2_IMCLK>,
346 <&cpg CPG_MOD 220 <&cpg CPG_MOD R9A08G045_SDHI2_CLK_HS>,
347 <&cpg CPG_MOD 221 <&cpg CPG_MOD R9A08G045_SDHI2_IMCLK2>,
348 <&cpg CPG_MOD 222 <&cpg CPG_MOD R9A08G045_SDHI2_ACLK>;
349 clock-names = "core", 223 clock-names = "core", "clkh", "cd", "aclk";
350 resets = <&cpg R9A08G0 224 resets = <&cpg R9A08G045_SDHI2_IXRST>;
351 power-domains = <&cpg> 225 power-domains = <&cpg>;
352 status = "disabled"; 226 status = "disabled";
353 }; 227 };
354 228
355 eth0: ethernet@11c30000 { 229 eth0: ethernet@11c30000 {
356 compatible = "renesas, 230 compatible = "renesas,r9a08g045-gbeth", "renesas,rzg2l-gbeth";
357 reg = <0 0x11c30000 0 231 reg = <0 0x11c30000 0 0x10000>;
358 interrupts = <GIC_SPI 232 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
359 <GIC_SPI 233 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
360 <GIC_SPI 234 <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
361 interrupt-names = "mux 235 interrupt-names = "mux", "fil", "arp_ns";
362 phy-mode = "rgmii"; 236 phy-mode = "rgmii";
363 clocks = <&cpg CPG_MOD 237 clocks = <&cpg CPG_MOD R9A08G045_ETH0_CLK_AXI>,
364 <&cpg CPG_MOD 238 <&cpg CPG_MOD R9A08G045_ETH0_CLK_CHI>,
365 <&cpg CPG_MOD 239 <&cpg CPG_MOD R9A08G045_ETH0_REFCLK>;
366 clock-names = "axi", " 240 clock-names = "axi", "chi", "refclk";
367 resets = <&cpg R9A08G0 241 resets = <&cpg R9A08G045_ETH0_RST_HW_N>;
368 power-domains = <&cpg> 242 power-domains = <&cpg>;
369 #address-cells = <1>; 243 #address-cells = <1>;
370 #size-cells = <0>; 244 #size-cells = <0>;
371 status = "disabled"; 245 status = "disabled";
372 }; 246 };
373 247
374 eth1: ethernet@11c40000 { 248 eth1: ethernet@11c40000 {
375 compatible = "renesas, 249 compatible = "renesas,r9a08g045-gbeth", "renesas,rzg2l-gbeth";
376 reg = <0 0x11c40000 0 250 reg = <0 0x11c40000 0 0x10000>;
377 interrupts = <GIC_SPI 251 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
378 <GIC_SPI 252 <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
379 <GIC_SPI 253 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
380 interrupt-names = "mux 254 interrupt-names = "mux", "fil", "arp_ns";
381 phy-mode = "rgmii"; 255 phy-mode = "rgmii";
382 clocks = <&cpg CPG_MOD 256 clocks = <&cpg CPG_MOD R9A08G045_ETH1_CLK_AXI>,
383 <&cpg CPG_MOD 257 <&cpg CPG_MOD R9A08G045_ETH1_CLK_CHI>,
384 <&cpg CPG_MOD 258 <&cpg CPG_MOD R9A08G045_ETH1_REFCLK>;
385 clock-names = "axi", " 259 clock-names = "axi", "chi", "refclk";
386 resets = <&cpg R9A08G0 260 resets = <&cpg R9A08G045_ETH1_RST_HW_N>;
387 power-domains = <&cpg> 261 power-domains = <&cpg>;
388 #address-cells = <1>; 262 #address-cells = <1>;
389 #size-cells = <0>; 263 #size-cells = <0>;
390 status = "disabled"; 264 status = "disabled";
391 }; 265 };
392 266
393 gic: interrupt-controller@1240 267 gic: interrupt-controller@12400000 {
394 compatible = "arm,gic- 268 compatible = "arm,gic-v3";
395 #interrupt-cells = <3> 269 #interrupt-cells = <3>;
396 #address-cells = <0>; 270 #address-cells = <0>;
397 interrupt-controller; 271 interrupt-controller;
398 reg = <0x0 0x12400000 !! 272 reg = <0x0 0x12400000 0 0x40000>,
399 <0x0 0x12440000 !! 273 <0x0 0x12440000 0 0x60000>;
400 interrupts = <GIC_PPI 274 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
401 }; 275 };
402 276
403 wdt0: watchdog@12800800 { 277 wdt0: watchdog@12800800 {
404 compatible = "renesas, 278 compatible = "renesas,r9a08g045-wdt", "renesas,rzg2l-wdt";
405 reg = <0 0x12800800 0 279 reg = <0 0x12800800 0 0x400>;
406 clocks = <&cpg CPG_MOD 280 clocks = <&cpg CPG_MOD R9A08G045_WDT0_PCLK>,
407 <&cpg CPG_MOD 281 <&cpg CPG_MOD R9A08G045_WDT0_CLK>;
408 clock-names = "pclk", 282 clock-names = "pclk", "oscclk";
409 interrupts = <GIC_SPI 283 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
410 <GIC_SPI 284 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
411 interrupt-names = "wdt 285 interrupt-names = "wdt", "perrout";
412 resets = <&cpg R9A08G0 286 resets = <&cpg R9A08G045_WDT0_PRESETN>;
413 power-domains = <&cpg> 287 power-domains = <&cpg>;
414 status = "disabled"; 288 status = "disabled";
415 }; 289 };
416 }; 290 };
417 291
418 timer { 292 timer {
419 compatible = "arm,armv8-timer" 293 compatible = "arm,armv8-timer";
420 interrupts-extended = <&gic GI 294 interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
421 <&gic GI 295 <&gic GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
422 <&gic GI 296 <&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
423 <&gic GI !! 297 <&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
424 <&gic GI <<
425 interrupt-names = "sec-phys", <<
426 "hyp-virt"; <<
427 }; 298 };
428 }; 299 };
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