1 // SPDX-License-Identifier: (GPL-2.0-only OR B 1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 /* 2 /*
3 * Device Tree Source for the RZ/G3S SoC 3 * Device Tree Source for the RZ/G3S SoC
4 * 4 *
5 * Copyright (C) 2023 Renesas Electronics Corp 5 * Copyright (C) 2023 Renesas Electronics Corp.
6 */ 6 */
7 7
8 #include <dt-bindings/interrupt-controller/arm 8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/clock/r9a08g045-cpg.h> 9 #include <dt-bindings/clock/r9a08g045-cpg.h>
10 10
11 / { 11 / {
12 compatible = "renesas,r9a08g045"; 12 compatible = "renesas,r9a08g045";
13 #address-cells = <2>; 13 #address-cells = <2>;
14 #size-cells = <2>; 14 #size-cells = <2>;
15 15
16 cpus { 16 cpus {
17 #address-cells = <1>; 17 #address-cells = <1>;
18 #size-cells = <0>; 18 #size-cells = <0>;
19 19
20 cpu0: cpu@0 { 20 cpu0: cpu@0 {
21 compatible = "arm,cort 21 compatible = "arm,cortex-a55";
22 reg = <0>; 22 reg = <0>;
23 device_type = "cpu"; 23 device_type = "cpu";
24 #cooling-cells = <2>; 24 #cooling-cells = <2>;
25 next-level-cache = <&L 25 next-level-cache = <&L3_CA55>;
26 enable-method = "psci" 26 enable-method = "psci";
27 clocks = <&cpg CPG_COR 27 clocks = <&cpg CPG_CORE R9A08G045_CLK_I>;
28 }; 28 };
29 29
30 L3_CA55: cache-controller-0 { 30 L3_CA55: cache-controller-0 {
31 compatible = "cache"; 31 compatible = "cache";
32 cache-level = <3>; 32 cache-level = <3>;
33 cache-unified; 33 cache-unified;
34 cache-size = <0x40000> 34 cache-size = <0x40000>;
35 }; 35 };
36 }; 36 };
37 37
38 extal_clk: extal-clk { 38 extal_clk: extal-clk {
39 compatible = "fixed-clock"; 39 compatible = "fixed-clock";
40 #clock-cells = <0>; 40 #clock-cells = <0>;
41 /* This value must be overridd 41 /* This value must be overridden by the board. */
42 clock-frequency = <0>; 42 clock-frequency = <0>;
43 }; 43 };
44 44
45 psci { 45 psci {
46 compatible = "arm,psci-1.0", " 46 compatible = "arm,psci-1.0", "arm,psci-0.2";
47 method = "smc"; 47 method = "smc";
48 }; 48 };
49 49
50 soc: soc { 50 soc: soc {
51 compatible = "simple-bus"; 51 compatible = "simple-bus";
52 interrupt-parent = <&gic>; 52 interrupt-parent = <&gic>;
53 #address-cells = <2>; 53 #address-cells = <2>;
54 #size-cells = <2>; 54 #size-cells = <2>;
55 ranges; 55 ranges;
56 56
57 scif0: serial@1004b800 { 57 scif0: serial@1004b800 {
58 compatible = "renesas, 58 compatible = "renesas,scif-r9a08g045", "renesas,scif-r9a07g044";
59 reg = <0 0x1004b800 0 59 reg = <0 0x1004b800 0 0x400>;
60 interrupts = <GIC_SPI 60 interrupts = <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
61 <GIC_SPI 61 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
62 <GIC_SPI 62 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
63 <GIC_SPI 63 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
64 <GIC_SPI 64 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
65 <GIC_SPI 65 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>;
66 interrupt-names = "eri 66 interrupt-names = "eri", "rxi", "txi",
67 "bri 67 "bri", "dri", "tei";
68 clocks = <&cpg CPG_MOD 68 clocks = <&cpg CPG_MOD R9A08G045_SCIF0_CLK_PCK>;
69 clock-names = "fck"; 69 clock-names = "fck";
70 power-domains = <&cpg> 70 power-domains = <&cpg>;
71 resets = <&cpg R9A08G0 71 resets = <&cpg R9A08G045_SCIF0_RST_SYSTEM_N>;
72 status = "disabled"; 72 status = "disabled";
73 }; 73 };
74 74
75 i2c0: i2c@10090000 { 75 i2c0: i2c@10090000 {
76 compatible = "renesas, 76 compatible = "renesas,riic-r9a08g045", "renesas,riic-r9a09g057";
77 reg = <0 0x10090000 0 77 reg = <0 0x10090000 0 0x400>;
78 interrupts = <GIC_SPI 78 interrupts = <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
79 <GIC_SPI 79 <GIC_SPI 263 IRQ_TYPE_EDGE_RISING>,
80 <GIC_SPI 80 <GIC_SPI 264 IRQ_TYPE_EDGE_RISING>,
81 <GIC_SPI 81 <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>,
82 <GIC_SPI 82 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
83 <GIC_SPI 83 <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
84 <GIC_SPI 84 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
85 <GIC_SPI 85 <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>;
86 interrupt-names = "tei 86 interrupt-names = "tei", "ri", "ti", "spi", "sti",
87 "nak 87 "naki", "ali", "tmoi";
88 clocks = <&cpg CPG_MOD 88 clocks = <&cpg CPG_MOD R9A08G045_I2C0_PCLK>;
89 clock-frequency = <100 89 clock-frequency = <100000>;
90 resets = <&cpg R9A08G0 90 resets = <&cpg R9A08G045_I2C0_MRST>;
91 power-domains = <&cpg> 91 power-domains = <&cpg>;
92 #address-cells = <1>; 92 #address-cells = <1>;
93 #size-cells = <0>; 93 #size-cells = <0>;
94 status = "disabled"; 94 status = "disabled";
95 }; 95 };
96 96
97 i2c1: i2c@10090400 { 97 i2c1: i2c@10090400 {
98 compatible = "renesas, 98 compatible = "renesas,riic-r9a08g045", "renesas,riic-r9a09g057";
99 reg = <0 0x10090400 0 99 reg = <0 0x10090400 0 0x400>;
100 interrupts = <GIC_SPI 100 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
101 <GIC_SPI 101 <GIC_SPI 271 IRQ_TYPE_EDGE_RISING>,
102 <GIC_SPI 102 <GIC_SPI 272 IRQ_TYPE_EDGE_RISING>,
103 <GIC_SPI 103 <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>,
104 <GIC_SPI 104 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
105 <GIC_SPI 105 <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>,
106 <GIC_SPI 106 <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>,
107 <GIC_SPI 107 <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>;
108 interrupt-names = "tei 108 interrupt-names = "tei", "ri", "ti", "spi", "sti",
109 "nak 109 "naki", "ali", "tmoi";
110 clocks = <&cpg CPG_MOD 110 clocks = <&cpg CPG_MOD R9A08G045_I2C1_PCLK>;
111 clock-frequency = <100 111 clock-frequency = <100000>;
112 resets = <&cpg R9A08G0 112 resets = <&cpg R9A08G045_I2C1_MRST>;
113 power-domains = <&cpg> 113 power-domains = <&cpg>;
114 #address-cells = <1>; 114 #address-cells = <1>;
115 #size-cells = <0>; 115 #size-cells = <0>;
116 status = "disabled"; 116 status = "disabled";
117 }; 117 };
118 118
119 i2c2: i2c@10090800 { 119 i2c2: i2c@10090800 {
120 compatible = "renesas, 120 compatible = "renesas,riic-r9a08g045", "renesas,riic-r9a09g057";
121 reg = <0 0x10090800 0 121 reg = <0 0x10090800 0 0x400>;
122 interrupts = <GIC_SPI 122 interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>,
123 <GIC_SPI 123 <GIC_SPI 279 IRQ_TYPE_EDGE_RISING>,
124 <GIC_SPI 124 <GIC_SPI 280 IRQ_TYPE_EDGE_RISING>,
125 <GIC_SPI 125 <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>,
126 <GIC_SPI 126 <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>,
127 <GIC_SPI 127 <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>,
128 <GIC_SPI 128 <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>,
129 <GIC_SPI 129 <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>;
130 interrupt-names = "tei 130 interrupt-names = "tei", "ri", "ti", "spi", "sti",
131 "nak 131 "naki", "ali", "tmoi";
132 clocks = <&cpg CPG_MOD 132 clocks = <&cpg CPG_MOD R9A08G045_I2C2_PCLK>;
133 clock-frequency = <100 133 clock-frequency = <100000>;
134 resets = <&cpg R9A08G0 134 resets = <&cpg R9A08G045_I2C2_MRST>;
135 power-domains = <&cpg> 135 power-domains = <&cpg>;
136 #address-cells = <1>; 136 #address-cells = <1>;
137 #size-cells = <0>; 137 #size-cells = <0>;
138 status = "disabled"; 138 status = "disabled";
139 }; 139 };
140 140
141 i2c3: i2c@10090c00 { 141 i2c3: i2c@10090c00 {
142 compatible = "renesas, 142 compatible = "renesas,riic-r9a08g045", "renesas,riic-r9a09g057";
143 reg = <0 0x10090c00 0 143 reg = <0 0x10090c00 0 0x400>;
144 interrupts = <GIC_SPI 144 interrupts = <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
145 <GIC_SPI 145 <GIC_SPI 287 IRQ_TYPE_EDGE_RISING>,
146 <GIC_SPI 146 <GIC_SPI 288 IRQ_TYPE_EDGE_RISING>,
147 <GIC_SPI 147 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
148 <GIC_SPI 148 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
149 <GIC_SPI 149 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
150 <GIC_SPI 150 <GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>,
151 <GIC_SPI 151 <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
152 interrupt-names = "tei 152 interrupt-names = "tei", "ri", "ti", "spi", "sti",
153 "nak 153 "naki", "ali", "tmoi";
154 clocks = <&cpg CPG_MOD 154 clocks = <&cpg CPG_MOD R9A08G045_I2C3_PCLK>;
155 clock-frequency = <100 155 clock-frequency = <100000>;
156 resets = <&cpg R9A08G0 156 resets = <&cpg R9A08G045_I2C3_MRST>;
157 power-domains = <&cpg> 157 power-domains = <&cpg>;
158 #address-cells = <1>; 158 #address-cells = <1>;
159 #size-cells = <0>; 159 #size-cells = <0>;
160 status = "disabled"; 160 status = "disabled";
161 }; 161 };
162 162
163 cpg: clock-controller@11010000 163 cpg: clock-controller@11010000 {
164 compatible = "renesas, 164 compatible = "renesas,r9a08g045-cpg";
165 reg = <0 0x11010000 0 165 reg = <0 0x11010000 0 0x10000>;
166 clocks = <&extal_clk>; 166 clocks = <&extal_clk>;
167 clock-names = "extal"; 167 clock-names = "extal";
168 #clock-cells = <2>; 168 #clock-cells = <2>;
169 #reset-cells = <1>; 169 #reset-cells = <1>;
170 #power-domain-cells = 170 #power-domain-cells = <0>;
171 }; 171 };
172 172
173 sysc: system-controller@110200 173 sysc: system-controller@11020000 {
174 compatible = "renesas, 174 compatible = "renesas,r9a08g045-sysc";
175 reg = <0 0x11020000 0 175 reg = <0 0x11020000 0 0x10000>;
176 interrupts = <GIC_SPI 176 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
177 <GIC_SPI 177 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
178 <GIC_SPI 178 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
179 <GIC_SPI 179 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
180 interrupt-names = "lpm 180 interrupt-names = "lpm_int", "ca55stbydone_int",
181 "cm3 181 "cm33stbyr_int", "ca55_deny";
182 status = "disabled"; 182 status = "disabled";
183 }; 183 };
184 184
185 pinctrl: pinctrl@11030000 { 185 pinctrl: pinctrl@11030000 {
186 compatible = "renesas, 186 compatible = "renesas,r9a08g045-pinctrl";
187 reg = <0 0x11030000 0 187 reg = <0 0x11030000 0 0x10000>;
188 gpio-controller; 188 gpio-controller;
189 #gpio-cells = <2>; 189 #gpio-cells = <2>;
190 interrupt-controller; 190 interrupt-controller;
191 #interrupt-cells = <2> 191 #interrupt-cells = <2>;
192 interrupt-parent = <&i 192 interrupt-parent = <&irqc>;
193 gpio-ranges = <&pinctr 193 gpio-ranges = <&pinctrl 0 0 152>;
194 clocks = <&cpg CPG_MOD 194 clocks = <&cpg CPG_MOD R9A08G045_GPIO_HCLK>;
195 power-domains = <&cpg> 195 power-domains = <&cpg>;
196 resets = <&cpg R9A08G0 196 resets = <&cpg R9A08G045_GPIO_RSTN>,
197 <&cpg R9A08G0 197 <&cpg R9A08G045_GPIO_PORT_RESETN>,
198 <&cpg R9A08G0 198 <&cpg R9A08G045_GPIO_SPARE_RESETN>;
199 }; 199 };
200 200
201 irqc: interrupt-controller@110 201 irqc: interrupt-controller@11050000 {
202 compatible = "renesas, 202 compatible = "renesas,r9a08g045-irqc", "renesas,rzg2l-irqc";
203 #interrupt-cells = <2> 203 #interrupt-cells = <2>;
204 #address-cells = <0>; 204 #address-cells = <0>;
205 interrupt-controller; 205 interrupt-controller;
206 reg = <0 0x11050000 0 206 reg = <0 0x11050000 0 0x10000>;
207 interrupts = <GIC_SPI 207 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
208 <GIC_SPI 208 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
209 <GIC_SPI 209 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
210 <GIC_SPI 210 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
211 <GIC_SPI 211 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
212 <GIC_SPI 212 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
213 <GIC_SPI 213 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
214 <GIC_SPI 214 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
215 <GIC_SPI 215 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
216 <GIC_SPI 216 <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>,
217 <GIC_SPI 217 <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>,
218 <GIC_SPI 218 <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH>,
219 <GIC_SPI 219 <GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>,
220 <GIC_SPI 220 <GIC_SPI 433 IRQ_TYPE_LEVEL_HIGH>,
221 <GIC_SPI 221 <GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>,
222 <GIC_SPI 222 <GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>,
223 <GIC_SPI 223 <GIC_SPI 436 IRQ_TYPE_LEVEL_HIGH>,
224 <GIC_SPI 224 <GIC_SPI 437 IRQ_TYPE_LEVEL_HIGH>,
225 <GIC_SPI 225 <GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>,
226 <GIC_SPI 226 <GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>,
227 <GIC_SPI 227 <GIC_SPI 440 IRQ_TYPE_LEVEL_HIGH>,
228 <GIC_SPI 228 <GIC_SPI 441 IRQ_TYPE_LEVEL_HIGH>,
229 <GIC_SPI 229 <GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>,
230 <GIC_SPI 230 <GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>,
231 <GIC_SPI 231 <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>,
232 <GIC_SPI 232 <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>,
233 <GIC_SPI 233 <GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>,
234 <GIC_SPI 234 <GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>,
235 <GIC_SPI 235 <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>,
236 <GIC_SPI 236 <GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>,
237 <GIC_SPI 237 <GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH>,
238 <GIC_SPI 238 <GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>,
239 <GIC_SPI 239 <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>,
240 <GIC_SPI 240 <GIC_SPI 453 IRQ_TYPE_LEVEL_HIGH>,
241 <GIC_SPI 241 <GIC_SPI 454 IRQ_TYPE_LEVEL_HIGH>,
242 <GIC_SPI 242 <GIC_SPI 455 IRQ_TYPE_LEVEL_HIGH>,
243 <GIC_SPI 243 <GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>,
244 <GIC_SPI 244 <GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>,
245 <GIC_SPI 245 <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>,
246 <GIC_SPI 246 <GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>,
247 <GIC_SPI 247 <GIC_SPI 460 IRQ_TYPE_LEVEL_HIGH>,
248 <GIC_SPI 248 <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
249 <GIC_SPI 249 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
250 <GIC_SPI 250 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
251 <GIC_SPI 251 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
252 interrupt-names = "nmi 252 interrupt-names = "nmi",
253 "irq 253 "irq0", "irq1", "irq2", "irq3",
254 "irq 254 "irq4", "irq5", "irq6", "irq7",
255 "tin 255 "tint0", "tint1", "tint2", "tint3",
256 "tin 256 "tint4", "tint5", "tint6", "tint7",
257 "tin 257 "tint8", "tint9", "tint10", "tint11",
258 "tin 258 "tint12", "tint13", "tint14", "tint15",
259 "tin 259 "tint16", "tint17", "tint18", "tint19",
260 "tin 260 "tint20", "tint21", "tint22", "tint23",
261 "tin 261 "tint24", "tint25", "tint26", "tint27",
262 "tin 262 "tint28", "tint29", "tint30", "tint31",
263 "bus 263 "bus-err", "ec7tie1-0", "ec7tie2-0",
264 "ec7 264 "ec7tiovf-0";
265 clocks = <&cpg CPG_MOD 265 clocks = <&cpg CPG_MOD R9A08G045_IA55_CLK>,
266 <&cpg CPG_MOD 266 <&cpg CPG_MOD R9A08G045_IA55_PCLK>;
267 clock-names = "clk", " 267 clock-names = "clk", "pclk";
268 power-domains = <&cpg> 268 power-domains = <&cpg>;
269 resets = <&cpg R9A08G0 269 resets = <&cpg R9A08G045_IA55_RESETN>;
270 }; 270 };
271 271
272 dmac: dma-controller@11820000 272 dmac: dma-controller@11820000 {
273 compatible = "renesas, 273 compatible = "renesas,r9a08g045-dmac",
274 "renesas, 274 "renesas,rz-dmac";
275 reg = <0 0x11820000 0 275 reg = <0 0x11820000 0 0x10000>,
276 <0 0x11830000 0 276 <0 0x11830000 0 0x10000>;
277 interrupts = <GIC_SPI 277 interrupts = <GIC_SPI 111 IRQ_TYPE_EDGE_RISING>,
278 <GIC_SPI 278 <GIC_SPI 112 IRQ_TYPE_EDGE_RISING>,
279 <GIC_SPI 279 <GIC_SPI 113 IRQ_TYPE_EDGE_RISING>,
280 <GIC_SPI 280 <GIC_SPI 114 IRQ_TYPE_EDGE_RISING>,
281 <GIC_SPI 281 <GIC_SPI 115 IRQ_TYPE_EDGE_RISING>,
282 <GIC_SPI 282 <GIC_SPI 116 IRQ_TYPE_EDGE_RISING>,
283 <GIC_SPI 283 <GIC_SPI 117 IRQ_TYPE_EDGE_RISING>,
284 <GIC_SPI 284 <GIC_SPI 118 IRQ_TYPE_EDGE_RISING>,
285 <GIC_SPI 285 <GIC_SPI 119 IRQ_TYPE_EDGE_RISING>,
286 <GIC_SPI 286 <GIC_SPI 120 IRQ_TYPE_EDGE_RISING>,
287 <GIC_SPI 287 <GIC_SPI 121 IRQ_TYPE_EDGE_RISING>,
288 <GIC_SPI 288 <GIC_SPI 122 IRQ_TYPE_EDGE_RISING>,
289 <GIC_SPI 289 <GIC_SPI 123 IRQ_TYPE_EDGE_RISING>,
290 <GIC_SPI 290 <GIC_SPI 124 IRQ_TYPE_EDGE_RISING>,
291 <GIC_SPI 291 <GIC_SPI 125 IRQ_TYPE_EDGE_RISING>,
292 <GIC_SPI 292 <GIC_SPI 126 IRQ_TYPE_EDGE_RISING>,
293 <GIC_SPI 293 <GIC_SPI 127 IRQ_TYPE_EDGE_RISING>;
294 interrupt-names = "err 294 interrupt-names = "error",
295 "ch0 295 "ch0", "ch1", "ch2", "ch3",
296 "ch4 296 "ch4", "ch5", "ch6", "ch7",
297 "ch8 297 "ch8", "ch9", "ch10", "ch11",
298 "ch1 298 "ch12", "ch13", "ch14", "ch15";
299 clocks = <&cpg CPG_MOD 299 clocks = <&cpg CPG_MOD R9A08G045_DMAC_ACLK>,
300 <&cpg CPG_MOD 300 <&cpg CPG_MOD R9A08G045_DMAC_PCLK>;
301 clock-names = "main", 301 clock-names = "main", "register";
302 power-domains = <&cpg> 302 power-domains = <&cpg>;
303 resets = <&cpg R9A08G0 303 resets = <&cpg R9A08G045_DMAC_ARESETN>,
304 <&cpg R9A08G0 304 <&cpg R9A08G045_DMAC_RST_ASYNC>;
305 reset-names = "arst", 305 reset-names = "arst", "rst_async";
306 #dma-cells = <1>; 306 #dma-cells = <1>;
307 dma-channels = <16>; 307 dma-channels = <16>;
308 }; 308 };
309 309
310 sdhi0: mmc@11c00000 { 310 sdhi0: mmc@11c00000 {
311 compatible = "renesas, 311 compatible = "renesas,sdhi-r9a08g045", "renesas,rzg2l-sdhi";
312 reg = <0x0 0x11c00000 312 reg = <0x0 0x11c00000 0 0x10000>;
313 interrupts = <GIC_SPI 313 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
314 <GIC_SPI 314 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
315 clocks = <&cpg CPG_MOD 315 clocks = <&cpg CPG_MOD R9A08G045_SDHI0_IMCLK>,
316 <&cpg CPG_MOD 316 <&cpg CPG_MOD R9A08G045_SDHI0_CLK_HS>,
317 <&cpg CPG_MOD 317 <&cpg CPG_MOD R9A08G045_SDHI0_IMCLK2>,
318 <&cpg CPG_MOD 318 <&cpg CPG_MOD R9A08G045_SDHI0_ACLK>;
319 clock-names = "core", 319 clock-names = "core", "clkh", "cd", "aclk";
320 resets = <&cpg R9A08G0 320 resets = <&cpg R9A08G045_SDHI0_IXRST>;
321 power-domains = <&cpg> 321 power-domains = <&cpg>;
322 status = "disabled"; 322 status = "disabled";
323 }; 323 };
324 324
325 sdhi1: mmc@11c10000 { 325 sdhi1: mmc@11c10000 {
326 compatible = "renesas, 326 compatible = "renesas,sdhi-r9a08g045", "renesas,rzg2l-sdhi";
327 reg = <0x0 0x11c10000 327 reg = <0x0 0x11c10000 0 0x10000>;
328 interrupts = <GIC_SPI 328 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
329 <GIC_SPI 329 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
330 clocks = <&cpg CPG_MOD 330 clocks = <&cpg CPG_MOD R9A08G045_SDHI1_IMCLK>,
331 <&cpg CPG_MOD 331 <&cpg CPG_MOD R9A08G045_SDHI1_CLK_HS>,
332 <&cpg CPG_MOD 332 <&cpg CPG_MOD R9A08G045_SDHI1_IMCLK2>,
333 <&cpg CPG_MOD 333 <&cpg CPG_MOD R9A08G045_SDHI1_ACLK>;
334 clock-names = "core", 334 clock-names = "core", "clkh", "cd", "aclk";
335 resets = <&cpg R9A08G0 335 resets = <&cpg R9A08G045_SDHI1_IXRST>;
336 power-domains = <&cpg> 336 power-domains = <&cpg>;
337 status = "disabled"; 337 status = "disabled";
338 }; 338 };
339 339
340 sdhi2: mmc@11c20000 { 340 sdhi2: mmc@11c20000 {
341 compatible = "renesas, 341 compatible = "renesas,sdhi-r9a08g045", "renesas,rzg2l-sdhi";
342 reg = <0x0 0x11c20000 342 reg = <0x0 0x11c20000 0 0x10000>;
343 interrupts = <GIC_SPI 343 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
344 <GIC_SPI 344 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
345 clocks = <&cpg CPG_MOD 345 clocks = <&cpg CPG_MOD R9A08G045_SDHI2_IMCLK>,
346 <&cpg CPG_MOD 346 <&cpg CPG_MOD R9A08G045_SDHI2_CLK_HS>,
347 <&cpg CPG_MOD 347 <&cpg CPG_MOD R9A08G045_SDHI2_IMCLK2>,
348 <&cpg CPG_MOD 348 <&cpg CPG_MOD R9A08G045_SDHI2_ACLK>;
349 clock-names = "core", 349 clock-names = "core", "clkh", "cd", "aclk";
350 resets = <&cpg R9A08G0 350 resets = <&cpg R9A08G045_SDHI2_IXRST>;
351 power-domains = <&cpg> 351 power-domains = <&cpg>;
352 status = "disabled"; 352 status = "disabled";
353 }; 353 };
354 354
355 eth0: ethernet@11c30000 { 355 eth0: ethernet@11c30000 {
356 compatible = "renesas, 356 compatible = "renesas,r9a08g045-gbeth", "renesas,rzg2l-gbeth";
357 reg = <0 0x11c30000 0 357 reg = <0 0x11c30000 0 0x10000>;
358 interrupts = <GIC_SPI 358 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
359 <GIC_SPI 359 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
360 <GIC_SPI 360 <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
361 interrupt-names = "mux 361 interrupt-names = "mux", "fil", "arp_ns";
362 phy-mode = "rgmii"; 362 phy-mode = "rgmii";
363 clocks = <&cpg CPG_MOD 363 clocks = <&cpg CPG_MOD R9A08G045_ETH0_CLK_AXI>,
364 <&cpg CPG_MOD 364 <&cpg CPG_MOD R9A08G045_ETH0_CLK_CHI>,
365 <&cpg CPG_MOD 365 <&cpg CPG_MOD R9A08G045_ETH0_REFCLK>;
366 clock-names = "axi", " 366 clock-names = "axi", "chi", "refclk";
367 resets = <&cpg R9A08G0 367 resets = <&cpg R9A08G045_ETH0_RST_HW_N>;
368 power-domains = <&cpg> 368 power-domains = <&cpg>;
369 #address-cells = <1>; 369 #address-cells = <1>;
370 #size-cells = <0>; 370 #size-cells = <0>;
371 status = "disabled"; 371 status = "disabled";
372 }; 372 };
373 373
374 eth1: ethernet@11c40000 { 374 eth1: ethernet@11c40000 {
375 compatible = "renesas, 375 compatible = "renesas,r9a08g045-gbeth", "renesas,rzg2l-gbeth";
376 reg = <0 0x11c40000 0 376 reg = <0 0x11c40000 0 0x10000>;
377 interrupts = <GIC_SPI 377 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
378 <GIC_SPI 378 <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
379 <GIC_SPI 379 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
380 interrupt-names = "mux 380 interrupt-names = "mux", "fil", "arp_ns";
381 phy-mode = "rgmii"; 381 phy-mode = "rgmii";
382 clocks = <&cpg CPG_MOD 382 clocks = <&cpg CPG_MOD R9A08G045_ETH1_CLK_AXI>,
383 <&cpg CPG_MOD 383 <&cpg CPG_MOD R9A08G045_ETH1_CLK_CHI>,
384 <&cpg CPG_MOD 384 <&cpg CPG_MOD R9A08G045_ETH1_REFCLK>;
385 clock-names = "axi", " 385 clock-names = "axi", "chi", "refclk";
386 resets = <&cpg R9A08G0 386 resets = <&cpg R9A08G045_ETH1_RST_HW_N>;
387 power-domains = <&cpg> 387 power-domains = <&cpg>;
388 #address-cells = <1>; 388 #address-cells = <1>;
389 #size-cells = <0>; 389 #size-cells = <0>;
390 status = "disabled"; 390 status = "disabled";
391 }; 391 };
392 392
393 gic: interrupt-controller@1240 393 gic: interrupt-controller@12400000 {
394 compatible = "arm,gic- 394 compatible = "arm,gic-v3";
395 #interrupt-cells = <3> 395 #interrupt-cells = <3>;
396 #address-cells = <0>; 396 #address-cells = <0>;
397 interrupt-controller; 397 interrupt-controller;
398 reg = <0x0 0x12400000 398 reg = <0x0 0x12400000 0 0x20000>,
399 <0x0 0x12440000 399 <0x0 0x12440000 0 0x40000>;
400 interrupts = <GIC_PPI 400 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
401 }; 401 };
402 402
403 wdt0: watchdog@12800800 { 403 wdt0: watchdog@12800800 {
404 compatible = "renesas, 404 compatible = "renesas,r9a08g045-wdt", "renesas,rzg2l-wdt";
405 reg = <0 0x12800800 0 405 reg = <0 0x12800800 0 0x400>;
406 clocks = <&cpg CPG_MOD 406 clocks = <&cpg CPG_MOD R9A08G045_WDT0_PCLK>,
407 <&cpg CPG_MOD 407 <&cpg CPG_MOD R9A08G045_WDT0_CLK>;
408 clock-names = "pclk", 408 clock-names = "pclk", "oscclk";
409 interrupts = <GIC_SPI 409 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
410 <GIC_SPI 410 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
411 interrupt-names = "wdt 411 interrupt-names = "wdt", "perrout";
412 resets = <&cpg R9A08G0 412 resets = <&cpg R9A08G045_WDT0_PRESETN>;
413 power-domains = <&cpg> 413 power-domains = <&cpg>;
414 status = "disabled"; 414 status = "disabled";
415 }; 415 };
416 }; 416 };
417 417
418 timer { 418 timer {
419 compatible = "arm,armv8-timer" 419 compatible = "arm,armv8-timer";
420 interrupts-extended = <&gic GI 420 interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
421 <&gic GI 421 <&gic GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
422 <&gic GI 422 <&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
423 <&gic GI 423 <&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>,
424 <&gic GI 424 <&gic GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>;
425 interrupt-names = "sec-phys", 425 interrupt-names = "sec-phys", "phys", "virt", "hyp-phys",
426 "hyp-virt"; 426 "hyp-virt";
427 }; 427 };
428 }; 428 };
Linux® is a registered trademark of Linus Torvalds in the United States and other countries.
TOMOYO® is a registered trademark of NTT DATA CORPORATION.