1 // SPDX-License-Identifier: (GPL-2.0-only OR B 1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 /* 2 /*
3 * Device Tree Source for the RZ/{G2L,V2L} SMA 3 * Device Tree Source for the RZ/{G2L,V2L} SMARC SOM common parts
4 * 4 *
5 * Copyright (C) 2021 Renesas Electronics Corp 5 * Copyright (C) 2021 Renesas Electronics Corp.
6 */ 6 */
7 7
8 #include <dt-bindings/gpio/gpio.h> 8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/irq <<
10 #include <dt-bindings/pinctrl/rzg2l-pinctrl.h> 9 #include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
11 10
12 /* SW1[2] should be at position 2/OFF to enabl 11 /* SW1[2] should be at position 2/OFF to enable 64 GB eMMC */
13 #define EMMC 1 12 #define EMMC 1
14 13
15 /* 14 /*
16 * To enable uSD card on CN3, 15 * To enable uSD card on CN3,
17 * SW1[2] should be at position 3/ON. 16 * SW1[2] should be at position 3/ON.
18 * Disable eMMC by setting "#define EMMC 17 * Disable eMMC by setting "#define EMMC 0" above.
19 */ 18 */
20 #define SDHI (!EMMC) 19 #define SDHI (!EMMC)
21 20
22 / { 21 / {
23 aliases { 22 aliases {
24 ethernet0 = ð0; 23 ethernet0 = ð0;
25 ethernet1 = ð1; 24 ethernet1 = ð1;
26 }; 25 };
27 26
28 chosen { 27 chosen {
29 bootargs = "ignore_loglevel rw 28 bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
30 }; 29 };
31 30
32 memory@48000000 { 31 memory@48000000 {
33 device_type = "memory"; 32 device_type = "memory";
34 /* first 128MB is reserved for 33 /* first 128MB is reserved for secure area. */
35 reg = <0x0 0x48000000 0x0 0x78 34 reg = <0x0 0x48000000 0x0 0x78000000>;
36 }; 35 };
37 36
38 reg_1p8v: regulator-1p8v { !! 37 reg_1p8v: regulator0 {
39 compatible = "regulator-fixed" 38 compatible = "regulator-fixed";
40 regulator-name = "fixed-1.8V"; 39 regulator-name = "fixed-1.8V";
41 regulator-min-microvolt = <180 40 regulator-min-microvolt = <1800000>;
42 regulator-max-microvolt = <180 41 regulator-max-microvolt = <1800000>;
43 regulator-boot-on; 42 regulator-boot-on;
44 regulator-always-on; 43 regulator-always-on;
45 }; 44 };
46 45
47 reg_3p3v: regulator-3p3v { !! 46 reg_3p3v: regulator1 {
48 compatible = "regulator-fixed" 47 compatible = "regulator-fixed";
49 regulator-name = "fixed-3.3V"; 48 regulator-name = "fixed-3.3V";
50 regulator-min-microvolt = <330 49 regulator-min-microvolt = <3300000>;
51 regulator-max-microvolt = <330 50 regulator-max-microvolt = <3300000>;
52 regulator-boot-on; 51 regulator-boot-on;
53 regulator-always-on; 52 regulator-always-on;
54 }; 53 };
55 54
56 reg_1p1v: regulator-vdd-core { 55 reg_1p1v: regulator-vdd-core {
57 compatible = "regulator-fixed" 56 compatible = "regulator-fixed";
58 regulator-name = "fixed-1.1V"; 57 regulator-name = "fixed-1.1V";
59 regulator-min-microvolt = <110 58 regulator-min-microvolt = <1100000>;
60 regulator-max-microvolt = <110 59 regulator-max-microvolt = <1100000>;
61 regulator-boot-on; 60 regulator-boot-on;
62 regulator-always-on; 61 regulator-always-on;
63 }; 62 };
64 63
65 vccq_sdhi0: regulator-vccq-sdhi0 { 64 vccq_sdhi0: regulator-vccq-sdhi0 {
66 compatible = "regulator-gpio"; 65 compatible = "regulator-gpio";
67 66
68 regulator-name = "SDHI0 VccQ"; 67 regulator-name = "SDHI0 VccQ";
69 regulator-min-microvolt = <180 68 regulator-min-microvolt = <1800000>;
70 regulator-max-microvolt = <330 69 regulator-max-microvolt = <3300000>;
71 states = <3300000 1>, <1800000 70 states = <3300000 1>, <1800000 0>;
72 regulator-boot-on; 71 regulator-boot-on;
73 gpios = <&pinctrl RZG2L_GPIO(3 72 gpios = <&pinctrl RZG2L_GPIO(39, 0) GPIO_ACTIVE_HIGH>;
74 regulator-always-on; 73 regulator-always-on;
75 }; 74 };
76 <<
77 /* 32.768kHz crystal */ <<
78 x2: x2-clock { <<
79 compatible = "fixed-clock"; <<
80 #clock-cells = <0>; <<
81 clock-frequency = <32768>; <<
82 }; <<
83 }; 75 };
84 76
85 &adc { 77 &adc {
86 pinctrl-0 = <&adc_pins>; 78 pinctrl-0 = <&adc_pins>;
87 pinctrl-names = "default"; 79 pinctrl-names = "default";
88 status = "okay"; 80 status = "okay";
89 81
90 /delete-node/ channel@6; 82 /delete-node/ channel@6;
91 /delete-node/ channel@7; 83 /delete-node/ channel@7;
92 }; 84 };
93 85
94 ð0 { 86 ð0 {
95 pinctrl-0 = <ð0_pins>; 87 pinctrl-0 = <ð0_pins>;
96 pinctrl-names = "default"; 88 pinctrl-names = "default";
97 phy-handle = <&phy0>; 89 phy-handle = <&phy0>;
98 phy-mode = "rgmii-id"; 90 phy-mode = "rgmii-id";
99 status = "okay"; 91 status = "okay";
100 92
101 phy0: ethernet-phy@7 { 93 phy0: ethernet-phy@7 {
102 compatible = "ethernet-phy-id0 94 compatible = "ethernet-phy-id0022.1640",
103 "ethernet-phy-iee 95 "ethernet-phy-ieee802.3-c22";
104 reg = <7>; 96 reg = <7>;
105 interrupt-parent = <&irqc>; <<
106 interrupts = <RZG2L_IRQ2 IRQ_T <<
107 rxc-skew-psec = <2400>; 97 rxc-skew-psec = <2400>;
108 txc-skew-psec = <2400>; 98 txc-skew-psec = <2400>;
109 rxdv-skew-psec = <0>; 99 rxdv-skew-psec = <0>;
110 txen-skew-psec = <0>; !! 100 txdv-skew-psec = <0>;
111 rxd0-skew-psec = <0>; 101 rxd0-skew-psec = <0>;
112 rxd1-skew-psec = <0>; 102 rxd1-skew-psec = <0>;
113 rxd2-skew-psec = <0>; 103 rxd2-skew-psec = <0>;
114 rxd3-skew-psec = <0>; 104 rxd3-skew-psec = <0>;
115 txd0-skew-psec = <0>; 105 txd0-skew-psec = <0>;
116 txd1-skew-psec = <0>; 106 txd1-skew-psec = <0>;
117 txd2-skew-psec = <0>; 107 txd2-skew-psec = <0>;
118 txd3-skew-psec = <0>; 108 txd3-skew-psec = <0>;
119 }; 109 };
120 }; 110 };
121 111
122 ð1 { 112 ð1 {
123 pinctrl-0 = <ð1_pins>; 113 pinctrl-0 = <ð1_pins>;
124 pinctrl-names = "default"; 114 pinctrl-names = "default";
125 phy-handle = <&phy1>; 115 phy-handle = <&phy1>;
126 phy-mode = "rgmii-id"; 116 phy-mode = "rgmii-id";
127 status = "okay"; 117 status = "okay";
128 118
129 phy1: ethernet-phy@7 { 119 phy1: ethernet-phy@7 {
130 compatible = "ethernet-phy-id0 120 compatible = "ethernet-phy-id0022.1640",
131 "ethernet-phy-iee 121 "ethernet-phy-ieee802.3-c22";
132 reg = <7>; 122 reg = <7>;
133 interrupt-parent = <&irqc>; <<
134 interrupts = <RZG2L_IRQ3 IRQ_T <<
135 rxc-skew-psec = <2400>; 123 rxc-skew-psec = <2400>;
136 txc-skew-psec = <2400>; 124 txc-skew-psec = <2400>;
137 rxdv-skew-psec = <0>; 125 rxdv-skew-psec = <0>;
138 txen-skew-psec = <0>; !! 126 txdv-skew-psec = <0>;
139 rxd0-skew-psec = <0>; 127 rxd0-skew-psec = <0>;
140 rxd1-skew-psec = <0>; 128 rxd1-skew-psec = <0>;
141 rxd2-skew-psec = <0>; 129 rxd2-skew-psec = <0>;
142 rxd3-skew-psec = <0>; 130 rxd3-skew-psec = <0>;
143 txd0-skew-psec = <0>; 131 txd0-skew-psec = <0>;
144 txd1-skew-psec = <0>; 132 txd1-skew-psec = <0>;
145 txd2-skew-psec = <0>; 133 txd2-skew-psec = <0>;
146 txd3-skew-psec = <0>; 134 txd3-skew-psec = <0>;
147 }; 135 };
148 }; 136 };
149 137
150 &extal_clk { 138 &extal_clk {
151 clock-frequency = <24000000>; 139 clock-frequency = <24000000>;
152 }; 140 };
153 141
154 &gpu { 142 &gpu {
155 mali-supply = <®_1p1v>; 143 mali-supply = <®_1p1v>;
156 }; 144 };
157 145
158 &i2c3 { <<
159 raa215300: pmic@12 { <<
160 compatible = "renesas,raa21530 <<
161 reg = <0x12>, <0x6f>; <<
162 reg-names = "main", "rtc"; <<
163 <<
164 clocks = <&x2>; <<
165 clock-names = "xin"; <<
166 }; <<
167 }; <<
168 <<
169 &ostm1 { 146 &ostm1 {
170 status = "okay"; 147 status = "okay";
171 }; 148 };
172 149
173 &ostm2 { 150 &ostm2 {
174 status = "okay"; 151 status = "okay";
175 }; 152 };
176 153
177 &pinctrl { 154 &pinctrl {
178 adc_pins: adc { 155 adc_pins: adc {
179 pinmux = <RZG2L_PORT_PINMUX(9, 156 pinmux = <RZG2L_PORT_PINMUX(9, 0, 2)>; /* ADC_TRG */
180 }; 157 };
181 158
182 eth0_pins: eth0 { 159 eth0_pins: eth0 {
183 txc { !! 160 pinmux = <RZG2L_PORT_PINMUX(28, 1, 1)>, /* ET0_LINKSTA */
184 pinmux = <RZG2L_PORT_P !! 161 <RZG2L_PORT_PINMUX(27, 1, 1)>, /* ET0_MDC */
185 power-source = <1800>; !! 162 <RZG2L_PORT_PINMUX(28, 0, 1)>, /* ET0_MDIO */
186 output-enable; !! 163 <RZG2L_PORT_PINMUX(20, 0, 1)>, /* ET0_TXC */
187 }; !! 164 <RZG2L_PORT_PINMUX(20, 1, 1)>, /* ET0_TX_CTL */
188 !! 165 <RZG2L_PORT_PINMUX(20, 2, 1)>, /* ET0_TXD0 */
189 mux { !! 166 <RZG2L_PORT_PINMUX(21, 0, 1)>, /* ET0_TXD1 */
190 pinmux = <RZG2L_PORT_P !! 167 <RZG2L_PORT_PINMUX(21, 1, 1)>, /* ET0_TXD2 */
191 <RZG2L_PORT_P !! 168 <RZG2L_PORT_PINMUX(22, 0, 1)>, /* ET0_TXD3 */
192 <RZG2L_PORT_P !! 169 <RZG2L_PORT_PINMUX(24, 0, 1)>, /* ET0_RXC */
193 <RZG2L_PORT_P !! 170 <RZG2L_PORT_PINMUX(24, 1, 1)>, /* ET0_RX_CTL */
194 <RZG2L_PORT_P !! 171 <RZG2L_PORT_PINMUX(25, 0, 1)>, /* ET0_RXD0 */
195 <RZG2L_PORT_P !! 172 <RZG2L_PORT_PINMUX(25, 1, 1)>, /* ET0_RXD1 */
196 <RZG2L_PORT_P !! 173 <RZG2L_PORT_PINMUX(26, 0, 1)>, /* ET0_RXD2 */
197 <RZG2L_PORT_P !! 174 <RZG2L_PORT_PINMUX(26, 1, 1)>; /* ET0_RXD3 */
198 <RZG2L_PORT_P <<
199 <RZG2L_PORT_P <<
200 <RZG2L_PORT_P <<
201 <RZG2L_PORT_P <<
202 <RZG2L_PORT_P <<
203 <RZG2L_PORT_P <<
204 power-source = <1800>; <<
205 }; <<
206 <<
207 irq { <<
208 pinmux = <RZG2L_PORT_P <<
209 }; <<
210 }; 175 };
211 176
212 eth1_pins: eth1 { 177 eth1_pins: eth1 {
213 txc { !! 178 pinmux = <RZG2L_PORT_PINMUX(37, 2, 1)>, /* ET1_LINKSTA */
214 pinmux = <RZG2L_PORT_P !! 179 <RZG2L_PORT_PINMUX(37, 0, 1)>, /* ET1_MDC */
215 power-source = <1800>; !! 180 <RZG2L_PORT_PINMUX(37, 1, 1)>, /* ET1_MDIO */
216 output-enable; !! 181 <RZG2L_PORT_PINMUX(29, 0, 1)>, /* ET1_TXC */
217 }; !! 182 <RZG2L_PORT_PINMUX(29, 1, 1)>, /* ET1_TX_CTL */
218 !! 183 <RZG2L_PORT_PINMUX(30, 0, 1)>, /* ET1_TXD0 */
219 mux { !! 184 <RZG2L_PORT_PINMUX(30, 1, 1)>, /* ET1_TXD1 */
220 pinmux = <RZG2L_PORT_P !! 185 <RZG2L_PORT_PINMUX(31, 0, 1)>, /* ET1_TXD2 */
221 <RZG2L_PORT_P !! 186 <RZG2L_PORT_PINMUX(31, 1, 1)>, /* ET1_TXD3 */
222 <RZG2L_PORT_P !! 187 <RZG2L_PORT_PINMUX(33, 1, 1)>, /* ET1_RXC */
223 <RZG2L_PORT_P !! 188 <RZG2L_PORT_PINMUX(34, 0, 1)>, /* ET1_RX_CTL */
224 <RZG2L_PORT_P !! 189 <RZG2L_PORT_PINMUX(34, 1, 1)>, /* ET1_RXD0 */
225 <RZG2L_PORT_P !! 190 <RZG2L_PORT_PINMUX(35, 0, 1)>, /* ET1_RXD1 */
226 <RZG2L_PORT_P !! 191 <RZG2L_PORT_PINMUX(35, 1, 1)>, /* ET1_RXD2 */
227 <RZG2L_PORT_P !! 192 <RZG2L_PORT_PINMUX(36, 0, 1)>; /* ET1_RXD3 */
228 <RZG2L_PORT_P <<
229 <RZG2L_PORT_P <<
230 <RZG2L_PORT_P <<
231 <RZG2L_PORT_P <<
232 <RZG2L_PORT_P <<
233 <RZG2L_PORT_P <<
234 power-source = <1800>; <<
235 }; <<
236 <<
237 irq { <<
238 pinmux = <RZG2L_PORT_P <<
239 }; <<
240 }; 193 };
241 194
242 gpio-sd0-pwr-en-hog { 195 gpio-sd0-pwr-en-hog {
243 gpio-hog; 196 gpio-hog;
244 gpios = <RZG2L_GPIO(4, 1) GPIO 197 gpios = <RZG2L_GPIO(4, 1) GPIO_ACTIVE_HIGH>;
245 output-high; 198 output-high;
246 line-name = "gpio_sd0_pwr_en"; 199 line-name = "gpio_sd0_pwr_en";
247 }; 200 };
248 201
249 qspi0_pins: qspi0 { 202 qspi0_pins: qspi0 {
250 qspi0-data { 203 qspi0-data {
251 pins = "QSPI0_IO0", "Q 204 pins = "QSPI0_IO0", "QSPI0_IO1", "QSPI0_IO2", "QSPI0_IO3";
252 power-source = <1800>; 205 power-source = <1800>;
253 }; 206 };
254 207
255 qspi0-ctrl { 208 qspi0-ctrl {
256 pins = "QSPI0_SPCLK", 209 pins = "QSPI0_SPCLK", "QSPI0_SSL", "QSPI_RESET#";
257 power-source = <1800>; 210 power-source = <1800>;
258 }; 211 };
259 }; 212 };
260 213
261 /* 214 /*
262 * SD0 device selection is XOR between 215 * SD0 device selection is XOR between GPIO_SD0_DEV_SEL and SW1[2]
263 * The below switch logic can be used 216 * The below switch logic can be used to select the device between
264 * eMMC and microSD, after setting GPI 217 * eMMC and microSD, after setting GPIO_SD0_DEV_SEL to high in DT.
265 * SW1[2] should be at position 2/OFF 218 * SW1[2] should be at position 2/OFF to enable 64 GB eMMC
266 * SW1[2] should be at position 3/ON t 219 * SW1[2] should be at position 3/ON to enable uSD card CN3
267 */ 220 */
268 sd0-dev-sel-hog { 221 sd0-dev-sel-hog {
269 gpio-hog; 222 gpio-hog;
270 gpios = <RZG2L_GPIO(41, 1) GPI 223 gpios = <RZG2L_GPIO(41, 1) GPIO_ACTIVE_HIGH>;
271 output-high; 224 output-high;
272 line-name = "sd0_dev_sel"; 225 line-name = "sd0_dev_sel";
273 }; 226 };
274 227
275 sdhi0_emmc_pins: sd0emmc { 228 sdhi0_emmc_pins: sd0emmc {
276 sd0_emmc_data { 229 sd0_emmc_data {
277 pins = "SD0_DATA0", "S 230 pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3",
278 "SD0_DATA4", "S 231 "SD0_DATA4", "SD0_DATA5", "SD0_DATA6", "SD0_DATA7";
279 power-source = <1800>; 232 power-source = <1800>;
280 }; 233 };
281 234
282 sd0_emmc_ctrl { 235 sd0_emmc_ctrl {
283 pins = "SD0_CLK", "SD0 236 pins = "SD0_CLK", "SD0_CMD";
284 power-source = <1800>; 237 power-source = <1800>;
285 }; 238 };
286 239
287 sd0_emmc_rst { 240 sd0_emmc_rst {
288 pins = "SD0_RST#"; 241 pins = "SD0_RST#";
289 power-source = <1800>; 242 power-source = <1800>;
290 }; 243 };
291 }; 244 };
292 245
293 sdhi0_pins: sd0 { 246 sdhi0_pins: sd0 {
294 sd0_data { 247 sd0_data {
295 pins = "SD0_DATA0", "S 248 pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3";
296 power-source = <3300>; 249 power-source = <3300>;
297 }; 250 };
298 251
299 sd0_ctrl { 252 sd0_ctrl {
300 pins = "SD0_CLK", "SD0 253 pins = "SD0_CLK", "SD0_CMD";
301 power-source = <3300>; 254 power-source = <3300>;
302 }; 255 };
303 256
304 sd0_mux { 257 sd0_mux {
305 pinmux = <RZG2L_PORT_P 258 pinmux = <RZG2L_PORT_PINMUX(47, 0, 2)>; /* SD0_CD */
306 }; 259 };
307 }; 260 };
308 261
309 sdhi0_pins_uhs: sd0_uhs { 262 sdhi0_pins_uhs: sd0_uhs {
310 sd0_data_uhs { 263 sd0_data_uhs {
311 pins = "SD0_DATA0", "S 264 pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3";
312 power-source = <1800>; 265 power-source = <1800>;
313 }; 266 };
314 267
315 sd0_ctrl_uhs { 268 sd0_ctrl_uhs {
316 pins = "SD0_CLK", "SD0 269 pins = "SD0_CLK", "SD0_CMD";
317 power-source = <1800>; 270 power-source = <1800>;
318 }; 271 };
319 272
320 sd0_mux_uhs { 273 sd0_mux_uhs {
321 pinmux = <RZG2L_PORT_P 274 pinmux = <RZG2L_PORT_PINMUX(47, 0, 2)>; /* SD0_CD */
322 }; 275 };
323 }; 276 };
324 }; 277 };
325 278
326 &sbc { 279 &sbc {
327 pinctrl-0 = <&qspi0_pins>; 280 pinctrl-0 = <&qspi0_pins>;
328 pinctrl-names = "default"; 281 pinctrl-names = "default";
329 status = "okay"; 282 status = "okay";
330 283
331 flash@0 { 284 flash@0 {
332 compatible = "micron,mt25qu512 285 compatible = "micron,mt25qu512a", "jedec,spi-nor";
333 reg = <0>; 286 reg = <0>;
334 m25p,fast-read; 287 m25p,fast-read;
335 spi-max-frequency = <50000000> 288 spi-max-frequency = <50000000>;
336 spi-rx-bus-width = <4>; 289 spi-rx-bus-width = <4>;
337 spi-tx-bus-width = <4>; <<
338 290
339 partitions { 291 partitions {
340 compatible = "fixed-pa 292 compatible = "fixed-partitions";
341 #address-cells = <1>; 293 #address-cells = <1>;
342 #size-cells = <1>; 294 #size-cells = <1>;
343 295
344 boot@0 { 296 boot@0 {
345 reg = <0x00000 297 reg = <0x00000000 0x2000000>;
346 read-only; 298 read-only;
347 }; 299 };
348 user@2000000 { 300 user@2000000 {
349 reg = <0x20000 301 reg = <0x2000000 0x2000000>;
350 }; 302 };
351 }; 303 };
352 }; 304 };
353 }; 305 };
354 306
355 #if SDHI 307 #if SDHI
356 &sdhi0 { 308 &sdhi0 {
357 pinctrl-0 = <&sdhi0_pins>; 309 pinctrl-0 = <&sdhi0_pins>;
358 pinctrl-1 = <&sdhi0_pins_uhs>; 310 pinctrl-1 = <&sdhi0_pins_uhs>;
359 pinctrl-names = "default", "state_uhs" 311 pinctrl-names = "default", "state_uhs";
360 312
361 vmmc-supply = <®_3p3v>; 313 vmmc-supply = <®_3p3v>;
362 vqmmc-supply = <&vccq_sdhi0>; 314 vqmmc-supply = <&vccq_sdhi0>;
363 bus-width = <4>; 315 bus-width = <4>;
364 sd-uhs-sdr50; 316 sd-uhs-sdr50;
365 sd-uhs-sdr104; 317 sd-uhs-sdr104;
366 status = "okay"; 318 status = "okay";
367 }; 319 };
368 #endif 320 #endif
369 321
370 #if EMMC 322 #if EMMC
371 &sdhi0 { 323 &sdhi0 {
372 pinctrl-0 = <&sdhi0_emmc_pins>; 324 pinctrl-0 = <&sdhi0_emmc_pins>;
373 pinctrl-1 = <&sdhi0_emmc_pins>; 325 pinctrl-1 = <&sdhi0_emmc_pins>;
374 pinctrl-names = "default", "state_uhs" 326 pinctrl-names = "default", "state_uhs";
375 327
376 vmmc-supply = <®_3p3v>; 328 vmmc-supply = <®_3p3v>;
377 vqmmc-supply = <®_1p8v>; 329 vqmmc-supply = <®_1p8v>;
378 bus-width = <8>; 330 bus-width = <8>;
379 mmc-hs200-1_8v; 331 mmc-hs200-1_8v;
380 non-removable; 332 non-removable;
381 fixed-emmc-driver-type = <1>; 333 fixed-emmc-driver-type = <1>;
382 status = "okay"; 334 status = "okay";
383 }; 335 };
384 #endif 336 #endif
385 337
386 &wdt0 { 338 &wdt0 {
387 status = "okay"; 339 status = "okay";
388 timeout-sec = <60>; 340 timeout-sec = <60>;
389 }; 341 };
390 342
391 &wdt1 { 343 &wdt1 {
>> 344 status = "okay";
>> 345 timeout-sec = <60>;
>> 346 };
>> 347
>> 348 &wdt2 {
392 status = "okay"; 349 status = "okay";
393 timeout-sec = <60>; 350 timeout-sec = <60>;
394 }; 351 };
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