1 // SPDX-License-Identifier: (GPL-2.0-only OR B 1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 /* 2 /*
3 * Device Tree Source for the RZ/{G2L,V2L} SMA 3 * Device Tree Source for the RZ/{G2L,V2L} SMARC SOM common parts
4 * 4 *
5 * Copyright (C) 2021 Renesas Electronics Corp 5 * Copyright (C) 2021 Renesas Electronics Corp.
6 */ 6 */
7 7
8 #include <dt-bindings/gpio/gpio.h> 8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/irq 9 #include <dt-bindings/interrupt-controller/irqc-rzg2l.h>
10 #include <dt-bindings/pinctrl/rzg2l-pinctrl.h> 10 #include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
11 11
12 /* SW1[2] should be at position 2/OFF to enabl 12 /* SW1[2] should be at position 2/OFF to enable 64 GB eMMC */
13 #define EMMC 1 13 #define EMMC 1
14 14
15 /* 15 /*
16 * To enable uSD card on CN3, 16 * To enable uSD card on CN3,
17 * SW1[2] should be at position 3/ON. 17 * SW1[2] should be at position 3/ON.
18 * Disable eMMC by setting "#define EMMC 18 * Disable eMMC by setting "#define EMMC 0" above.
19 */ 19 */
20 #define SDHI (!EMMC) 20 #define SDHI (!EMMC)
21 21
22 / { 22 / {
23 aliases { 23 aliases {
24 ethernet0 = ð0; 24 ethernet0 = ð0;
25 ethernet1 = ð1; 25 ethernet1 = ð1;
26 }; 26 };
27 27
28 chosen { 28 chosen {
29 bootargs = "ignore_loglevel rw 29 bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
30 }; 30 };
31 31
32 memory@48000000 { 32 memory@48000000 {
33 device_type = "memory"; 33 device_type = "memory";
34 /* first 128MB is reserved for 34 /* first 128MB is reserved for secure area. */
35 reg = <0x0 0x48000000 0x0 0x78 35 reg = <0x0 0x48000000 0x0 0x78000000>;
36 }; 36 };
37 37
38 reg_1p8v: regulator-1p8v { 38 reg_1p8v: regulator-1p8v {
39 compatible = "regulator-fixed" 39 compatible = "regulator-fixed";
40 regulator-name = "fixed-1.8V"; 40 regulator-name = "fixed-1.8V";
41 regulator-min-microvolt = <180 41 regulator-min-microvolt = <1800000>;
42 regulator-max-microvolt = <180 42 regulator-max-microvolt = <1800000>;
43 regulator-boot-on; 43 regulator-boot-on;
44 regulator-always-on; 44 regulator-always-on;
45 }; 45 };
46 46
47 reg_3p3v: regulator-3p3v { 47 reg_3p3v: regulator-3p3v {
48 compatible = "regulator-fixed" 48 compatible = "regulator-fixed";
49 regulator-name = "fixed-3.3V"; 49 regulator-name = "fixed-3.3V";
50 regulator-min-microvolt = <330 50 regulator-min-microvolt = <3300000>;
51 regulator-max-microvolt = <330 51 regulator-max-microvolt = <3300000>;
52 regulator-boot-on; 52 regulator-boot-on;
53 regulator-always-on; 53 regulator-always-on;
54 }; 54 };
55 55
56 reg_1p1v: regulator-vdd-core { 56 reg_1p1v: regulator-vdd-core {
57 compatible = "regulator-fixed" 57 compatible = "regulator-fixed";
58 regulator-name = "fixed-1.1V"; 58 regulator-name = "fixed-1.1V";
59 regulator-min-microvolt = <110 59 regulator-min-microvolt = <1100000>;
60 regulator-max-microvolt = <110 60 regulator-max-microvolt = <1100000>;
61 regulator-boot-on; 61 regulator-boot-on;
62 regulator-always-on; 62 regulator-always-on;
63 }; 63 };
64 64
65 vccq_sdhi0: regulator-vccq-sdhi0 { 65 vccq_sdhi0: regulator-vccq-sdhi0 {
66 compatible = "regulator-gpio"; 66 compatible = "regulator-gpio";
67 67
68 regulator-name = "SDHI0 VccQ"; 68 regulator-name = "SDHI0 VccQ";
69 regulator-min-microvolt = <180 69 regulator-min-microvolt = <1800000>;
70 regulator-max-microvolt = <330 70 regulator-max-microvolt = <3300000>;
71 states = <3300000 1>, <1800000 71 states = <3300000 1>, <1800000 0>;
72 regulator-boot-on; 72 regulator-boot-on;
73 gpios = <&pinctrl RZG2L_GPIO(3 73 gpios = <&pinctrl RZG2L_GPIO(39, 0) GPIO_ACTIVE_HIGH>;
74 regulator-always-on; 74 regulator-always-on;
75 }; 75 };
76 76
77 /* 32.768kHz crystal */ 77 /* 32.768kHz crystal */
78 x2: x2-clock { 78 x2: x2-clock {
79 compatible = "fixed-clock"; 79 compatible = "fixed-clock";
80 #clock-cells = <0>; 80 #clock-cells = <0>;
81 clock-frequency = <32768>; 81 clock-frequency = <32768>;
82 }; 82 };
83 }; 83 };
84 84
85 &adc { 85 &adc {
86 pinctrl-0 = <&adc_pins>; 86 pinctrl-0 = <&adc_pins>;
87 pinctrl-names = "default"; 87 pinctrl-names = "default";
88 status = "okay"; 88 status = "okay";
89 89
90 /delete-node/ channel@6; 90 /delete-node/ channel@6;
91 /delete-node/ channel@7; 91 /delete-node/ channel@7;
92 }; 92 };
93 93
94 ð0 { 94 ð0 {
95 pinctrl-0 = <ð0_pins>; 95 pinctrl-0 = <ð0_pins>;
96 pinctrl-names = "default"; 96 pinctrl-names = "default";
97 phy-handle = <&phy0>; 97 phy-handle = <&phy0>;
98 phy-mode = "rgmii-id"; 98 phy-mode = "rgmii-id";
99 status = "okay"; 99 status = "okay";
100 100
101 phy0: ethernet-phy@7 { 101 phy0: ethernet-phy@7 {
102 compatible = "ethernet-phy-id0 102 compatible = "ethernet-phy-id0022.1640",
103 "ethernet-phy-iee 103 "ethernet-phy-ieee802.3-c22";
104 reg = <7>; 104 reg = <7>;
105 interrupt-parent = <&irqc>; 105 interrupt-parent = <&irqc>;
106 interrupts = <RZG2L_IRQ2 IRQ_T 106 interrupts = <RZG2L_IRQ2 IRQ_TYPE_LEVEL_LOW>;
107 rxc-skew-psec = <2400>; 107 rxc-skew-psec = <2400>;
108 txc-skew-psec = <2400>; 108 txc-skew-psec = <2400>;
109 rxdv-skew-psec = <0>; 109 rxdv-skew-psec = <0>;
110 txen-skew-psec = <0>; 110 txen-skew-psec = <0>;
111 rxd0-skew-psec = <0>; 111 rxd0-skew-psec = <0>;
112 rxd1-skew-psec = <0>; 112 rxd1-skew-psec = <0>;
113 rxd2-skew-psec = <0>; 113 rxd2-skew-psec = <0>;
114 rxd3-skew-psec = <0>; 114 rxd3-skew-psec = <0>;
115 txd0-skew-psec = <0>; 115 txd0-skew-psec = <0>;
116 txd1-skew-psec = <0>; 116 txd1-skew-psec = <0>;
117 txd2-skew-psec = <0>; 117 txd2-skew-psec = <0>;
118 txd3-skew-psec = <0>; 118 txd3-skew-psec = <0>;
119 }; 119 };
120 }; 120 };
121 121
122 ð1 { 122 ð1 {
123 pinctrl-0 = <ð1_pins>; 123 pinctrl-0 = <ð1_pins>;
124 pinctrl-names = "default"; 124 pinctrl-names = "default";
125 phy-handle = <&phy1>; 125 phy-handle = <&phy1>;
126 phy-mode = "rgmii-id"; 126 phy-mode = "rgmii-id";
127 status = "okay"; 127 status = "okay";
128 128
129 phy1: ethernet-phy@7 { 129 phy1: ethernet-phy@7 {
130 compatible = "ethernet-phy-id0 130 compatible = "ethernet-phy-id0022.1640",
131 "ethernet-phy-iee 131 "ethernet-phy-ieee802.3-c22";
132 reg = <7>; 132 reg = <7>;
133 interrupt-parent = <&irqc>; 133 interrupt-parent = <&irqc>;
134 interrupts = <RZG2L_IRQ3 IRQ_T 134 interrupts = <RZG2L_IRQ3 IRQ_TYPE_LEVEL_LOW>;
135 rxc-skew-psec = <2400>; 135 rxc-skew-psec = <2400>;
136 txc-skew-psec = <2400>; 136 txc-skew-psec = <2400>;
137 rxdv-skew-psec = <0>; 137 rxdv-skew-psec = <0>;
138 txen-skew-psec = <0>; 138 txen-skew-psec = <0>;
139 rxd0-skew-psec = <0>; 139 rxd0-skew-psec = <0>;
140 rxd1-skew-psec = <0>; 140 rxd1-skew-psec = <0>;
141 rxd2-skew-psec = <0>; 141 rxd2-skew-psec = <0>;
142 rxd3-skew-psec = <0>; 142 rxd3-skew-psec = <0>;
143 txd0-skew-psec = <0>; 143 txd0-skew-psec = <0>;
144 txd1-skew-psec = <0>; 144 txd1-skew-psec = <0>;
145 txd2-skew-psec = <0>; 145 txd2-skew-psec = <0>;
146 txd3-skew-psec = <0>; 146 txd3-skew-psec = <0>;
147 }; 147 };
148 }; 148 };
149 149
150 &extal_clk { 150 &extal_clk {
151 clock-frequency = <24000000>; 151 clock-frequency = <24000000>;
152 }; 152 };
153 153
154 &gpu { 154 &gpu {
155 mali-supply = <®_1p1v>; 155 mali-supply = <®_1p1v>;
156 }; 156 };
157 157
158 &i2c3 { 158 &i2c3 {
159 raa215300: pmic@12 { 159 raa215300: pmic@12 {
160 compatible = "renesas,raa21530 160 compatible = "renesas,raa215300";
161 reg = <0x12>, <0x6f>; 161 reg = <0x12>, <0x6f>;
162 reg-names = "main", "rtc"; 162 reg-names = "main", "rtc";
163 163
164 clocks = <&x2>; 164 clocks = <&x2>;
165 clock-names = "xin"; 165 clock-names = "xin";
166 }; 166 };
167 }; 167 };
168 168
169 &ostm1 { 169 &ostm1 {
170 status = "okay"; 170 status = "okay";
171 }; 171 };
172 172
173 &ostm2 { 173 &ostm2 {
174 status = "okay"; 174 status = "okay";
175 }; 175 };
176 176
177 &pinctrl { 177 &pinctrl {
178 adc_pins: adc { 178 adc_pins: adc {
179 pinmux = <RZG2L_PORT_PINMUX(9, 179 pinmux = <RZG2L_PORT_PINMUX(9, 0, 2)>; /* ADC_TRG */
180 }; 180 };
181 181
182 eth0_pins: eth0 { 182 eth0_pins: eth0 {
183 txc { !! 183 pinmux = <RZG2L_PORT_PINMUX(28, 1, 1)>, /* ET0_LINKSTA */
184 pinmux = <RZG2L_PORT_P !! 184 <RZG2L_PORT_PINMUX(27, 1, 1)>, /* ET0_MDC */
185 power-source = <1800>; !! 185 <RZG2L_PORT_PINMUX(28, 0, 1)>, /* ET0_MDIO */
186 output-enable; !! 186 <RZG2L_PORT_PINMUX(20, 0, 1)>, /* ET0_TXC */
187 }; !! 187 <RZG2L_PORT_PINMUX(20, 1, 1)>, /* ET0_TX_CTL */
188 !! 188 <RZG2L_PORT_PINMUX(20, 2, 1)>, /* ET0_TXD0 */
189 mux { !! 189 <RZG2L_PORT_PINMUX(21, 0, 1)>, /* ET0_TXD1 */
190 pinmux = <RZG2L_PORT_P !! 190 <RZG2L_PORT_PINMUX(21, 1, 1)>, /* ET0_TXD2 */
191 <RZG2L_PORT_P !! 191 <RZG2L_PORT_PINMUX(22, 0, 1)>, /* ET0_TXD3 */
192 <RZG2L_PORT_P !! 192 <RZG2L_PORT_PINMUX(24, 0, 1)>, /* ET0_RXC */
193 <RZG2L_PORT_P !! 193 <RZG2L_PORT_PINMUX(24, 1, 1)>, /* ET0_RX_CTL */
194 <RZG2L_PORT_P !! 194 <RZG2L_PORT_PINMUX(25, 0, 1)>, /* ET0_RXD0 */
195 <RZG2L_PORT_P !! 195 <RZG2L_PORT_PINMUX(25, 1, 1)>, /* ET0_RXD1 */
196 <RZG2L_PORT_P !! 196 <RZG2L_PORT_PINMUX(26, 0, 1)>, /* ET0_RXD2 */
197 <RZG2L_PORT_P !! 197 <RZG2L_PORT_PINMUX(26, 1, 1)>, /* ET0_RXD3 */
198 <RZG2L_PORT_P !! 198 <RZG2L_PORT_PINMUX(1, 0, 1)>; /* IRQ2 */
199 <RZG2L_PORT_P <<
200 <RZG2L_PORT_P <<
201 <RZG2L_PORT_P <<
202 <RZG2L_PORT_P <<
203 <RZG2L_PORT_P <<
204 power-source = <1800>; <<
205 }; <<
206 <<
207 irq { <<
208 pinmux = <RZG2L_PORT_P <<
209 }; <<
210 }; 199 };
211 200
212 eth1_pins: eth1 { 201 eth1_pins: eth1 {
213 txc { !! 202 pinmux = <RZG2L_PORT_PINMUX(37, 2, 1)>, /* ET1_LINKSTA */
214 pinmux = <RZG2L_PORT_P !! 203 <RZG2L_PORT_PINMUX(37, 0, 1)>, /* ET1_MDC */
215 power-source = <1800>; !! 204 <RZG2L_PORT_PINMUX(37, 1, 1)>, /* ET1_MDIO */
216 output-enable; !! 205 <RZG2L_PORT_PINMUX(29, 0, 1)>, /* ET1_TXC */
217 }; !! 206 <RZG2L_PORT_PINMUX(29, 1, 1)>, /* ET1_TX_CTL */
218 !! 207 <RZG2L_PORT_PINMUX(30, 0, 1)>, /* ET1_TXD0 */
219 mux { !! 208 <RZG2L_PORT_PINMUX(30, 1, 1)>, /* ET1_TXD1 */
220 pinmux = <RZG2L_PORT_P !! 209 <RZG2L_PORT_PINMUX(31, 0, 1)>, /* ET1_TXD2 */
221 <RZG2L_PORT_P !! 210 <RZG2L_PORT_PINMUX(31, 1, 1)>, /* ET1_TXD3 */
222 <RZG2L_PORT_P !! 211 <RZG2L_PORT_PINMUX(33, 1, 1)>, /* ET1_RXC */
223 <RZG2L_PORT_P !! 212 <RZG2L_PORT_PINMUX(34, 0, 1)>, /* ET1_RX_CTL */
224 <RZG2L_PORT_P !! 213 <RZG2L_PORT_PINMUX(34, 1, 1)>, /* ET1_RXD0 */
225 <RZG2L_PORT_P !! 214 <RZG2L_PORT_PINMUX(35, 0, 1)>, /* ET1_RXD1 */
226 <RZG2L_PORT_P !! 215 <RZG2L_PORT_PINMUX(35, 1, 1)>, /* ET1_RXD2 */
227 <RZG2L_PORT_P !! 216 <RZG2L_PORT_PINMUX(36, 0, 1)>, /* ET1_RXD3 */
228 <RZG2L_PORT_P !! 217 <RZG2L_PORT_PINMUX(1, 1, 1)>; /* IRQ3 */
229 <RZG2L_PORT_P <<
230 <RZG2L_PORT_P <<
231 <RZG2L_PORT_P <<
232 <RZG2L_PORT_P <<
233 <RZG2L_PORT_P <<
234 power-source = <1800>; <<
235 }; <<
236 <<
237 irq { <<
238 pinmux = <RZG2L_PORT_P <<
239 }; <<
240 }; 218 };
241 219
242 gpio-sd0-pwr-en-hog { 220 gpio-sd0-pwr-en-hog {
243 gpio-hog; 221 gpio-hog;
244 gpios = <RZG2L_GPIO(4, 1) GPIO 222 gpios = <RZG2L_GPIO(4, 1) GPIO_ACTIVE_HIGH>;
245 output-high; 223 output-high;
246 line-name = "gpio_sd0_pwr_en"; 224 line-name = "gpio_sd0_pwr_en";
247 }; 225 };
248 226
249 qspi0_pins: qspi0 { 227 qspi0_pins: qspi0 {
250 qspi0-data { 228 qspi0-data {
251 pins = "QSPI0_IO0", "Q 229 pins = "QSPI0_IO0", "QSPI0_IO1", "QSPI0_IO2", "QSPI0_IO3";
252 power-source = <1800>; 230 power-source = <1800>;
253 }; 231 };
254 232
255 qspi0-ctrl { 233 qspi0-ctrl {
256 pins = "QSPI0_SPCLK", 234 pins = "QSPI0_SPCLK", "QSPI0_SSL", "QSPI_RESET#";
257 power-source = <1800>; 235 power-source = <1800>;
258 }; 236 };
259 }; 237 };
260 238
261 /* 239 /*
262 * SD0 device selection is XOR between 240 * SD0 device selection is XOR between GPIO_SD0_DEV_SEL and SW1[2]
263 * The below switch logic can be used 241 * The below switch logic can be used to select the device between
264 * eMMC and microSD, after setting GPI 242 * eMMC and microSD, after setting GPIO_SD0_DEV_SEL to high in DT.
265 * SW1[2] should be at position 2/OFF 243 * SW1[2] should be at position 2/OFF to enable 64 GB eMMC
266 * SW1[2] should be at position 3/ON t 244 * SW1[2] should be at position 3/ON to enable uSD card CN3
267 */ 245 */
268 sd0-dev-sel-hog { 246 sd0-dev-sel-hog {
269 gpio-hog; 247 gpio-hog;
270 gpios = <RZG2L_GPIO(41, 1) GPI 248 gpios = <RZG2L_GPIO(41, 1) GPIO_ACTIVE_HIGH>;
271 output-high; 249 output-high;
272 line-name = "sd0_dev_sel"; 250 line-name = "sd0_dev_sel";
273 }; 251 };
274 252
275 sdhi0_emmc_pins: sd0emmc { 253 sdhi0_emmc_pins: sd0emmc {
276 sd0_emmc_data { 254 sd0_emmc_data {
277 pins = "SD0_DATA0", "S 255 pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3",
278 "SD0_DATA4", "S 256 "SD0_DATA4", "SD0_DATA5", "SD0_DATA6", "SD0_DATA7";
279 power-source = <1800>; 257 power-source = <1800>;
280 }; 258 };
281 259
282 sd0_emmc_ctrl { 260 sd0_emmc_ctrl {
283 pins = "SD0_CLK", "SD0 261 pins = "SD0_CLK", "SD0_CMD";
284 power-source = <1800>; 262 power-source = <1800>;
285 }; 263 };
286 264
287 sd0_emmc_rst { 265 sd0_emmc_rst {
288 pins = "SD0_RST#"; 266 pins = "SD0_RST#";
289 power-source = <1800>; 267 power-source = <1800>;
290 }; 268 };
291 }; 269 };
292 270
293 sdhi0_pins: sd0 { 271 sdhi0_pins: sd0 {
294 sd0_data { 272 sd0_data {
295 pins = "SD0_DATA0", "S 273 pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3";
296 power-source = <3300>; 274 power-source = <3300>;
297 }; 275 };
298 276
299 sd0_ctrl { 277 sd0_ctrl {
300 pins = "SD0_CLK", "SD0 278 pins = "SD0_CLK", "SD0_CMD";
301 power-source = <3300>; 279 power-source = <3300>;
302 }; 280 };
303 281
304 sd0_mux { 282 sd0_mux {
305 pinmux = <RZG2L_PORT_P 283 pinmux = <RZG2L_PORT_PINMUX(47, 0, 2)>; /* SD0_CD */
306 }; 284 };
307 }; 285 };
308 286
309 sdhi0_pins_uhs: sd0_uhs { 287 sdhi0_pins_uhs: sd0_uhs {
310 sd0_data_uhs { 288 sd0_data_uhs {
311 pins = "SD0_DATA0", "S 289 pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3";
312 power-source = <1800>; 290 power-source = <1800>;
313 }; 291 };
314 292
315 sd0_ctrl_uhs { 293 sd0_ctrl_uhs {
316 pins = "SD0_CLK", "SD0 294 pins = "SD0_CLK", "SD0_CMD";
317 power-source = <1800>; 295 power-source = <1800>;
318 }; 296 };
319 297
320 sd0_mux_uhs { 298 sd0_mux_uhs {
321 pinmux = <RZG2L_PORT_P 299 pinmux = <RZG2L_PORT_PINMUX(47, 0, 2)>; /* SD0_CD */
322 }; 300 };
323 }; 301 };
324 }; 302 };
325 303
326 &sbc { 304 &sbc {
327 pinctrl-0 = <&qspi0_pins>; 305 pinctrl-0 = <&qspi0_pins>;
328 pinctrl-names = "default"; 306 pinctrl-names = "default";
329 status = "okay"; 307 status = "okay";
330 308
331 flash@0 { 309 flash@0 {
332 compatible = "micron,mt25qu512 310 compatible = "micron,mt25qu512a", "jedec,spi-nor";
333 reg = <0>; 311 reg = <0>;
334 m25p,fast-read; 312 m25p,fast-read;
335 spi-max-frequency = <50000000> 313 spi-max-frequency = <50000000>;
336 spi-rx-bus-width = <4>; 314 spi-rx-bus-width = <4>;
337 spi-tx-bus-width = <4>; 315 spi-tx-bus-width = <4>;
338 316
339 partitions { 317 partitions {
340 compatible = "fixed-pa 318 compatible = "fixed-partitions";
341 #address-cells = <1>; 319 #address-cells = <1>;
342 #size-cells = <1>; 320 #size-cells = <1>;
343 321
344 boot@0 { 322 boot@0 {
345 reg = <0x00000 323 reg = <0x00000000 0x2000000>;
346 read-only; 324 read-only;
347 }; 325 };
348 user@2000000 { 326 user@2000000 {
349 reg = <0x20000 327 reg = <0x2000000 0x2000000>;
350 }; 328 };
351 }; 329 };
352 }; 330 };
353 }; 331 };
354 332
355 #if SDHI 333 #if SDHI
356 &sdhi0 { 334 &sdhi0 {
357 pinctrl-0 = <&sdhi0_pins>; 335 pinctrl-0 = <&sdhi0_pins>;
358 pinctrl-1 = <&sdhi0_pins_uhs>; 336 pinctrl-1 = <&sdhi0_pins_uhs>;
359 pinctrl-names = "default", "state_uhs" 337 pinctrl-names = "default", "state_uhs";
360 338
361 vmmc-supply = <®_3p3v>; 339 vmmc-supply = <®_3p3v>;
362 vqmmc-supply = <&vccq_sdhi0>; 340 vqmmc-supply = <&vccq_sdhi0>;
363 bus-width = <4>; 341 bus-width = <4>;
364 sd-uhs-sdr50; 342 sd-uhs-sdr50;
365 sd-uhs-sdr104; 343 sd-uhs-sdr104;
366 status = "okay"; 344 status = "okay";
367 }; 345 };
368 #endif 346 #endif
369 347
370 #if EMMC 348 #if EMMC
371 &sdhi0 { 349 &sdhi0 {
372 pinctrl-0 = <&sdhi0_emmc_pins>; 350 pinctrl-0 = <&sdhi0_emmc_pins>;
373 pinctrl-1 = <&sdhi0_emmc_pins>; 351 pinctrl-1 = <&sdhi0_emmc_pins>;
374 pinctrl-names = "default", "state_uhs" 352 pinctrl-names = "default", "state_uhs";
375 353
376 vmmc-supply = <®_3p3v>; 354 vmmc-supply = <®_3p3v>;
377 vqmmc-supply = <®_1p8v>; 355 vqmmc-supply = <®_1p8v>;
378 bus-width = <8>; 356 bus-width = <8>;
379 mmc-hs200-1_8v; 357 mmc-hs200-1_8v;
380 non-removable; 358 non-removable;
381 fixed-emmc-driver-type = <1>; 359 fixed-emmc-driver-type = <1>;
382 status = "okay"; 360 status = "okay";
383 }; 361 };
384 #endif 362 #endif
385 363
386 &wdt0 { 364 &wdt0 {
387 status = "okay"; 365 status = "okay";
388 timeout-sec = <60>; 366 timeout-sec = <60>;
389 }; 367 };
390 368
391 &wdt1 { 369 &wdt1 {
392 status = "okay"; 370 status = "okay";
393 timeout-sec = <60>; 371 timeout-sec = <60>;
394 }; 372 };
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