1 // SPDX-License-Identifier: (GPL-2.0-only OR B
2 /*
3 * Device Tree Source for the RZ/G2LC SMARC EV
4 *
5 * Copyright (C) 2022 Renesas Electronics Corp
6 */
7
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
10
11 #include "rzg2lc-smarc-pinfunction.dtsi"
12 #include "rz-smarc-common.dtsi"
13
14 / {
15 aliases {
16 serial1 = &scif1;
17 i2c2 = &i2c2;
18 };
19
20 osc1: cec-clock {
21 compatible = "fixed-clock";
22 #clock-cells = <0>;
23 clock-frequency = <12000000>;
24 };
25
26 hdmi-out {
27 compatible = "hdmi-connector";
28 type = "d";
29
30 port {
31 hdmi_con_out: endpoint
32 remote-endpoin
33 };
34 };
35 };
36
37 #if (SW_I2S0_I2S1)
38 /delete-node/ sound;
39
40 sound_card {
41 compatible = "audio-graph-card
42 label = "HDMI-Audio";
43 dais = <&i2s2_port>;
44 };
45 #endif
46 };
47
48 #if (SW_SCIF_CAN || SW_RSPI_CAN)
49 &canfd {
50 pinctrl-0 = <&can1_pins>;
51 /delete-node/ channel@0;
52 };
53 #else
54 &canfd {
55 /delete-property/ pinctrl-0;
56 /delete-property/ pinctrl-names;
57 status = "disabled";
58 };
59 #endif
60
61 #if (!SW_I2S0_I2S1)
62 &cpu_dai {
63 sound-dai = <&ssi0>;
64 };
65 #endif
66
67 &dsi {
68 status = "okay";
69
70 ports {
71 port@1 {
72 dsi0_out: endpoint {
73 data-lanes = <
74 remote-endpoin
75 };
76 };
77 };
78 };
79
80 &du {
81 status = "okay";
82 };
83
84 &i2c1 {
85 adv7535: hdmi@3d {
86 compatible = "adi,adv7535";
87 reg = <0x3d>;
88
89 interrupt-parent = <&pinctrl>;
90 interrupts = <RZG2L_GPIO(43, 1
91 clocks = <&osc1>;
92 clock-names = "cec";
93 avdd-supply = <®_1p8v>;
94 dvdd-supply = <®_1p8v>;
95 pvdd-supply = <®_1p8v>;
96 a2vdd-supply = <®_1p8v>;
97 v3p3-supply = <®_3p3v>;
98 v1p2-supply = <®_1p8v>;
99
100 adi,dsi-lanes = <4>;
101
102 ports {
103 #address-cells = <1>;
104 #size-cells = <0>;
105
106 port@0 {
107 reg = <0>;
108 adv7535_in: en
109 remote
110 };
111 };
112
113 port@1 {
114 reg = <1>;
115 adv7535_out: e
116 remote
117 };
118 };
119
120 #if (SW_I2S0_I2S1)
121 port@2 {
122 reg = <2>;
123 codec_endpoint
124 remote
125 };
126 };
127 #endif
128 };
129 };
130 };
131
132 &i2c2 {
133 pinctrl-0 = <&i2c2_pins>;
134 pinctrl-names = "default";
135 clock-frequency = <400000>;
136
137 status = "okay";
138
139 wm8978: codec@1a {
140 compatible = "wlf,wm8978";
141 #sound-dai-cells = <0>;
142 reg = <0x1a>;
143 };
144
145 versa3: clock-generator@68 {
146 compatible = "renesas,5p35023"
147 reg = <0x68>;
148 #clock-cells = <1>;
149 clocks = <&x1>;
150
151 renesas,settings = [
152 80 00 11 19 4c 02 23 7
153 00 14 7a e1 00 00 00 0
154 80 b0 45 c4 95
155 ];
156
157 assigned-clocks = <&versa3 0>,
158 <&versa3 2>,
159 <&versa3 4>,
160 assigned-clock-rates = <240000
161 <112896
162 <250000
163 };
164 };
165
166 #if PMOD_MTU3
167 &mtu3 {
168 pinctrl-0 = <&mtu3_pins>;
169 pinctrl-names = "default";
170
171 status = "okay";
172 };
173
174 &spi1 {
175 status = "disabled";
176 };
177 #endif
178
179 /*
180 * To enable SCIF1 (SER0) on PMOD1 (CN7), On c
181 * SW1 should be at position 2->3 so that SER0
182 * SW2 should be at position 2->3 so that SER0
183 * SW3 should be at position 2->3 so that SER0
184 * SW4 should be at position 2->3 so that SER0
185 */
186 #if (!SW_SCIF_CAN && PMOD1_SER0)
187 &scif1 {
188 pinctrl-0 = <&scif1_pins>;
189 pinctrl-names = "default";
190
191 uart-has-rtscts;
192 status = "okay";
193 };
194 #endif
195
196 &ssi0 {
197 pinctrl-0 = <&ssi0_pins>;
198 pinctrl-names = "default";
199
200 status = "okay";
201
202 #if (SW_I2S0_I2S1)
203 i2s2_port: port {
204 i2s2_cpu_endpoint: endpoint {
205 remote-endpoint = <&co
206 dai-format = "i2s";
207
208 bitclock-master = <&i2
209 frame-master = <&i2s2_
210 };
211 };
212 #endif
213 };
214
215 #if (SW_RSPI_CAN)
216 &spi1 {
217 /delete-property/ pinctrl-0;
218 /delete-property/ pinctrl-names;
219 status = "disabled";
220 };
221 #endif
222
223 &vccq_sdhi1 {
224 gpios = <&pinctrl RZG2L_GPIO(39, 1) GP
225 };
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