Linux/scripts/dtc/include-prefixes/arm64/renesas/rzg2lc-smarc.dtsi

Version: ~ [ linux-6.12-rc7 ] ~ [ linux-6.11.7 ] ~ [ linux-6.10.14 ] ~ [ linux-6.9.12 ] ~ [ linux-6.8.12 ] ~ [ linux-6.7.12 ] ~ [ linux-6.6.60 ] ~ [ linux-6.5.13 ] ~ [ linux-6.4.16 ] ~ [ linux-6.3.13 ] ~ [ linux-6.2.16 ] ~ [ linux-6.1.116 ] ~ [ linux-6.0.19 ] ~ [ linux-5.19.17 ] ~ [ linux-5.18.19 ] ~ [ linux-5.17.15 ] ~ [ linux-5.16.20 ] ~ [ linux-5.15.171 ] ~ [ linux-5.14.21 ] ~ [ linux-5.13.19 ] ~ [ linux-5.12.19 ] ~ [ linux-5.11.22 ] ~ [ linux-5.10.229 ] ~ [ linux-5.9.16 ] ~ [ linux-5.8.18 ] ~ [ linux-5.7.19 ] ~ [ linux-5.6.19 ] ~ [ linux-5.5.19 ] ~ [ linux-5.4.285 ] ~ [ linux-5.3.18 ] ~ [ linux-5.2.21 ] ~ [ linux-5.1.21 ] ~ [ linux-5.0.21 ] ~ [ linux-4.20.17 ] ~ [ linux-4.19.323 ] ~ [ linux-4.18.20 ] ~ [ linux-4.17.19 ] ~ [ linux-4.16.18 ] ~ [ linux-4.15.18 ] ~ [ linux-4.14.336 ] ~ [ linux-4.13.16 ] ~ [ linux-4.12.14 ] ~ [ linux-4.11.12 ] ~ [ linux-4.10.17 ] ~ [ linux-4.9.337 ] ~ [ linux-4.4.302 ] ~ [ linux-3.10.108 ] ~ [ linux-2.6.32.71 ] ~ [ linux-2.6.0 ] ~ [ linux-2.4.37.11 ] ~ [ unix-v6-master ] ~ [ ccs-tools-1.8.12 ] ~ [ policy-sample ] ~
Architecture: ~ [ i386 ] ~ [ alpha ] ~ [ m68k ] ~ [ mips ] ~ [ ppc ] ~ [ sparc ] ~ [ sparc64 ] ~

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1 // SPDX-License-Identifier: (GPL-2.0-only OR B 1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 /* 2 /* 3 * Device Tree Source for the RZ/G2LC SMARC EV 3 * Device Tree Source for the RZ/G2LC SMARC EVK parts 4 * 4 * 5 * Copyright (C) 2022 Renesas Electronics Corp 5 * Copyright (C) 2022 Renesas Electronics Corp. 6 */ 6 */ 7 7 8 #include <dt-bindings/gpio/gpio.h> 8 #include <dt-bindings/gpio/gpio.h> 9 #include <dt-bindings/pinctrl/rzg2l-pinctrl.h> 9 #include <dt-bindings/pinctrl/rzg2l-pinctrl.h> 10 10 >> 11 /* >> 12 * DIP-Switch SW1 setting on SoM >> 13 * 1 : High; 0: Low >> 14 * SW1-2 : SW_SD0_DEV_SEL (1: eMMC; 0: uSD) >> 15 * SW1-3 : SW_SCIF_CAN (1: CAN1; 0: SCIF1) >> 16 * SW1-4 : SW_RSPI_CAN (1: CAN1; 0: RSPI1) >> 17 * SW1-5 : SW_I2S0_I2S1 (1: I2S2 (HDMI audio); 0: I2S0) >> 18 * Please change below macros according to SW1 setting >> 19 */ >> 20 >> 21 #define SW_SD0_DEV_SEL 1 >> 22 >> 23 #define SW_SCIF_CAN 0 >> 24 #if (SW_SCIF_CAN) >> 25 /* Due to HW routing, SW_RSPI_CAN is always 0 when SW_SCIF_CAN is set to 1 */ >> 26 #define SW_RSPI_CAN 0 >> 27 #else >> 28 /* Please set SW_RSPI_CAN. Default value is 1 */ >> 29 #define SW_RSPI_CAN 1 >> 30 #endif >> 31 >> 32 #if (SW_SCIF_CAN && SW_RSPI_CAN) >> 33 #error "Can not set 1 to both SW_SCIF_CAN and SW_RSPI_CAN due to HW routing" >> 34 #endif >> 35 >> 36 #include "rzg2lc-smarc-som.dtsi" 11 #include "rzg2lc-smarc-pinfunction.dtsi" 37 #include "rzg2lc-smarc-pinfunction.dtsi" 12 #include "rz-smarc-common.dtsi" 38 #include "rz-smarc-common.dtsi" 13 39 >> 40 /* comment the #define statement to disable SCIF1 (SER0) on PMOD1 (CN7) */ >> 41 #define PMOD1_SER0 1 >> 42 14 / { 43 / { 15 aliases { 44 aliases { 16 serial1 = &scif1; 45 serial1 = &scif1; 17 i2c2 = &i2c2; 46 i2c2 = &i2c2; 18 }; 47 }; 19 << 20 osc1: cec-clock { << 21 compatible = "fixed-clock"; << 22 #clock-cells = <0>; << 23 clock-frequency = <12000000>; << 24 }; << 25 << 26 hdmi-out { << 27 compatible = "hdmi-connector"; << 28 type = "d"; << 29 << 30 port { << 31 hdmi_con_out: endpoint << 32 remote-endpoin << 33 }; << 34 }; << 35 }; << 36 << 37 #if (SW_I2S0_I2S1) << 38 /delete-node/ sound; << 39 << 40 sound_card { << 41 compatible = "audio-graph-card << 42 label = "HDMI-Audio"; << 43 dais = <&i2s2_port>; << 44 }; << 45 #endif << 46 }; 48 }; 47 49 48 #if (SW_SCIF_CAN || SW_RSPI_CAN) 50 #if (SW_SCIF_CAN || SW_RSPI_CAN) 49 &canfd { 51 &canfd { 50 pinctrl-0 = <&can1_pins>; 52 pinctrl-0 = <&can1_pins>; 51 /delete-node/ channel@0; 53 /delete-node/ channel@0; 52 }; 54 }; 53 #else 55 #else 54 &canfd { 56 &canfd { 55 /delete-property/ pinctrl-0; 57 /delete-property/ pinctrl-0; 56 /delete-property/ pinctrl-names; 58 /delete-property/ pinctrl-names; 57 status = "disabled"; 59 status = "disabled"; 58 }; 60 }; 59 #endif 61 #endif 60 62 61 #if (!SW_I2S0_I2S1) << 62 &cpu_dai { 63 &cpu_dai { 63 sound-dai = <&ssi0>; 64 sound-dai = <&ssi0>; 64 }; 65 }; 65 #endif << 66 << 67 &dsi { << 68 status = "okay"; << 69 << 70 ports { << 71 port@1 { << 72 dsi0_out: endpoint { << 73 data-lanes = < << 74 remote-endpoin << 75 }; << 76 }; << 77 }; << 78 }; << 79 << 80 &du { << 81 status = "okay"; << 82 }; << 83 << 84 &i2c1 { << 85 adv7535: hdmi@3d { << 86 compatible = "adi,adv7535"; << 87 reg = <0x3d>; << 88 << 89 interrupt-parent = <&pinctrl>; << 90 interrupts = <RZG2L_GPIO(43, 1 << 91 clocks = <&osc1>; << 92 clock-names = "cec"; << 93 avdd-supply = <&reg_1p8v>; << 94 dvdd-supply = <&reg_1p8v>; << 95 pvdd-supply = <&reg_1p8v>; << 96 a2vdd-supply = <&reg_1p8v>; << 97 v3p3-supply = <&reg_3p3v>; << 98 v1p2-supply = <&reg_1p8v>; << 99 << 100 adi,dsi-lanes = <4>; << 101 << 102 ports { << 103 #address-cells = <1>; << 104 #size-cells = <0>; << 105 << 106 port@0 { << 107 reg = <0>; << 108 adv7535_in: en << 109 remote << 110 }; << 111 }; << 112 << 113 port@1 { << 114 reg = <1>; << 115 adv7535_out: e << 116 remote << 117 }; << 118 }; << 119 << 120 #if (SW_I2S0_I2S1) << 121 port@2 { << 122 reg = <2>; << 123 codec_endpoint << 124 remote << 125 }; << 126 }; << 127 #endif << 128 }; << 129 }; << 130 }; << 131 66 132 &i2c2 { 67 &i2c2 { 133 pinctrl-0 = <&i2c2_pins>; 68 pinctrl-0 = <&i2c2_pins>; 134 pinctrl-names = "default"; 69 pinctrl-names = "default"; 135 clock-frequency = <400000>; 70 clock-frequency = <400000>; 136 71 137 status = "okay"; 72 status = "okay"; 138 73 139 wm8978: codec@1a { 74 wm8978: codec@1a { 140 compatible = "wlf,wm8978"; 75 compatible = "wlf,wm8978"; 141 #sound-dai-cells = <0>; 76 #sound-dai-cells = <0>; 142 reg = <0x1a>; 77 reg = <0x1a>; 143 }; 78 }; 144 << 145 versa3: clock-generator@68 { << 146 compatible = "renesas,5p35023" << 147 reg = <0x68>; << 148 #clock-cells = <1>; << 149 clocks = <&x1>; << 150 << 151 renesas,settings = [ << 152 80 00 11 19 4c 02 23 7 << 153 00 14 7a e1 00 00 00 0 << 154 80 b0 45 c4 95 << 155 ]; << 156 << 157 assigned-clocks = <&versa3 0>, << 158 <&versa3 2>, << 159 <&versa3 4>, << 160 assigned-clock-rates = <240000 << 161 <112896 << 162 <250000 << 163 }; << 164 }; << 165 << 166 #if PMOD_MTU3 << 167 &mtu3 { << 168 pinctrl-0 = <&mtu3_pins>; << 169 pinctrl-names = "default"; << 170 << 171 status = "okay"; << 172 }; 79 }; 173 80 174 &spi1 { << 175 status = "disabled"; << 176 }; << 177 #endif << 178 << 179 /* 81 /* 180 * To enable SCIF1 (SER0) on PMOD1 (CN7), On c 82 * To enable SCIF1 (SER0) on PMOD1 (CN7), On connector board 181 * SW1 should be at position 2->3 so that SER0 83 * SW1 should be at position 2->3 so that SER0_CTS# line is activated 182 * SW2 should be at position 2->3 so that SER0 84 * SW2 should be at position 2->3 so that SER0_TX line is activated 183 * SW3 should be at position 2->3 so that SER0 85 * SW3 should be at position 2->3 so that SER0_RX line is activated 184 * SW4 should be at position 2->3 so that SER0 86 * SW4 should be at position 2->3 so that SER0_RTS# line is activated 185 */ 87 */ 186 #if (!SW_SCIF_CAN && PMOD1_SER0) 88 #if (!SW_SCIF_CAN && PMOD1_SER0) 187 &scif1 { 89 &scif1 { 188 pinctrl-0 = <&scif1_pins>; 90 pinctrl-0 = <&scif1_pins>; 189 pinctrl-names = "default"; 91 pinctrl-names = "default"; 190 92 191 uart-has-rtscts; 93 uart-has-rtscts; 192 status = "okay"; 94 status = "okay"; 193 }; 95 }; 194 #endif 96 #endif 195 97 196 &ssi0 { 98 &ssi0 { 197 pinctrl-0 = <&ssi0_pins>; 99 pinctrl-0 = <&ssi0_pins>; 198 pinctrl-names = "default"; 100 pinctrl-names = "default"; 199 101 200 status = "okay"; 102 status = "okay"; 201 << 202 #if (SW_I2S0_I2S1) << 203 i2s2_port: port { << 204 i2s2_cpu_endpoint: endpoint { << 205 remote-endpoint = <&co << 206 dai-format = "i2s"; << 207 << 208 bitclock-master = <&i2 << 209 frame-master = <&i2s2_ << 210 }; << 211 }; << 212 #endif << 213 }; 103 }; 214 104 215 #if (SW_RSPI_CAN) 105 #if (SW_RSPI_CAN) 216 &spi1 { 106 &spi1 { 217 /delete-property/ pinctrl-0; 107 /delete-property/ pinctrl-0; 218 /delete-property/ pinctrl-names; 108 /delete-property/ pinctrl-names; 219 status = "disabled"; 109 status = "disabled"; 220 }; 110 }; 221 #endif 111 #endif 222 112 223 &vccq_sdhi1 { 113 &vccq_sdhi1 { 224 gpios = <&pinctrl RZG2L_GPIO(39, 1) GP 114 gpios = <&pinctrl RZG2L_GPIO(39, 1) GPIO_ACTIVE_HIGH>; 225 }; 115 };

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Linux/scripts/dtc/include-prefixes/arm64/renesas/rzg2lc-smarc.dtsi

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TOMOYO Linux Cross Reference
Linux/scripts/dtc/include-prefixes/arm64/renesas/rzg2lc-smarc.dtsi