1 // SPDX-License-Identifier: (GPL-2.0-only OR B 1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 /* 2 /*
3 * Device Tree Source for the RZ/G2LC SMARC EV 3 * Device Tree Source for the RZ/G2LC SMARC EVK parts
4 * 4 *
5 * Copyright (C) 2022 Renesas Electronics Corp 5 * Copyright (C) 2022 Renesas Electronics Corp.
6 */ 6 */
7 7
8 #include <dt-bindings/gpio/gpio.h> 8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/pinctrl/rzg2l-pinctrl.h> 9 #include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
10 10
11 #include "rzg2lc-smarc-pinfunction.dtsi" 11 #include "rzg2lc-smarc-pinfunction.dtsi"
12 #include "rz-smarc-common.dtsi" 12 #include "rz-smarc-common.dtsi"
13 13
>> 14
14 / { 15 / {
15 aliases { 16 aliases {
16 serial1 = &scif1; 17 serial1 = &scif1;
17 i2c2 = &i2c2; 18 i2c2 = &i2c2;
18 }; 19 };
19 20
20 osc1: cec-clock { 21 osc1: cec-clock {
21 compatible = "fixed-clock"; 22 compatible = "fixed-clock";
22 #clock-cells = <0>; 23 #clock-cells = <0>;
23 clock-frequency = <12000000>; 24 clock-frequency = <12000000>;
24 }; 25 };
25 26
26 hdmi-out { 27 hdmi-out {
27 compatible = "hdmi-connector"; 28 compatible = "hdmi-connector";
28 type = "d"; 29 type = "d";
29 30
30 port { 31 port {
31 hdmi_con_out: endpoint 32 hdmi_con_out: endpoint {
32 remote-endpoin 33 remote-endpoint = <&adv7535_out>;
33 }; 34 };
34 }; 35 };
35 }; 36 };
36 <<
37 #if (SW_I2S0_I2S1) <<
38 /delete-node/ sound; <<
39 <<
40 sound_card { <<
41 compatible = "audio-graph-card <<
42 label = "HDMI-Audio"; <<
43 dais = <&i2s2_port>; <<
44 }; <<
45 #endif <<
46 }; 37 };
47 38
48 #if (SW_SCIF_CAN || SW_RSPI_CAN) 39 #if (SW_SCIF_CAN || SW_RSPI_CAN)
49 &canfd { 40 &canfd {
50 pinctrl-0 = <&can1_pins>; 41 pinctrl-0 = <&can1_pins>;
51 /delete-node/ channel@0; 42 /delete-node/ channel@0;
52 }; 43 };
53 #else 44 #else
54 &canfd { 45 &canfd {
55 /delete-property/ pinctrl-0; 46 /delete-property/ pinctrl-0;
56 /delete-property/ pinctrl-names; 47 /delete-property/ pinctrl-names;
57 status = "disabled"; 48 status = "disabled";
58 }; 49 };
59 #endif 50 #endif
60 51
61 #if (!SW_I2S0_I2S1) <<
62 &cpu_dai { 52 &cpu_dai {
63 sound-dai = <&ssi0>; 53 sound-dai = <&ssi0>;
64 }; 54 };
65 #endif <<
66 55
67 &dsi { 56 &dsi {
68 status = "okay"; 57 status = "okay";
69 58
70 ports { 59 ports {
>> 60 #address-cells = <1>;
>> 61 #size-cells = <0>;
>> 62
>> 63 port@0 {
>> 64 reg = <0>;
>> 65 dsi0_in: endpoint {
>> 66 };
>> 67 };
>> 68
71 port@1 { 69 port@1 {
>> 70 reg = <1>;
72 dsi0_out: endpoint { 71 dsi0_out: endpoint {
73 data-lanes = < 72 data-lanes = <1 2 3 4>;
74 remote-endpoin 73 remote-endpoint = <&adv7535_in>;
75 }; 74 };
76 }; 75 };
77 }; 76 };
78 }; 77 };
79 78
80 &du { <<
81 status = "okay"; <<
82 }; <<
83 <<
84 &i2c1 { 79 &i2c1 {
85 adv7535: hdmi@3d { 80 adv7535: hdmi@3d {
86 compatible = "adi,adv7535"; 81 compatible = "adi,adv7535";
87 reg = <0x3d>; 82 reg = <0x3d>;
88 83
89 interrupt-parent = <&pinctrl>; 84 interrupt-parent = <&pinctrl>;
90 interrupts = <RZG2L_GPIO(43, 1 85 interrupts = <RZG2L_GPIO(43, 1) IRQ_TYPE_EDGE_FALLING>;
91 clocks = <&osc1>; 86 clocks = <&osc1>;
92 clock-names = "cec"; 87 clock-names = "cec";
93 avdd-supply = <®_1p8v>; 88 avdd-supply = <®_1p8v>;
94 dvdd-supply = <®_1p8v>; 89 dvdd-supply = <®_1p8v>;
95 pvdd-supply = <®_1p8v>; 90 pvdd-supply = <®_1p8v>;
96 a2vdd-supply = <®_1p8v>; 91 a2vdd-supply = <®_1p8v>;
97 v3p3-supply = <®_3p3v>; 92 v3p3-supply = <®_3p3v>;
98 v1p2-supply = <®_1p8v>; 93 v1p2-supply = <®_1p8v>;
99 94
100 adi,dsi-lanes = <4>; 95 adi,dsi-lanes = <4>;
101 96
102 ports { 97 ports {
103 #address-cells = <1>; 98 #address-cells = <1>;
104 #size-cells = <0>; 99 #size-cells = <0>;
105 100
106 port@0 { 101 port@0 {
107 reg = <0>; 102 reg = <0>;
108 adv7535_in: en 103 adv7535_in: endpoint {
109 remote 104 remote-endpoint = <&dsi0_out>;
110 }; 105 };
111 }; 106 };
112 107
113 port@1 { 108 port@1 {
114 reg = <1>; 109 reg = <1>;
115 adv7535_out: e 110 adv7535_out: endpoint {
116 remote 111 remote-endpoint = <&hdmi_con_out>;
117 }; 112 };
118 }; 113 };
119 <<
120 #if (SW_I2S0_I2S1) <<
121 port@2 { <<
122 reg = <2>; <<
123 codec_endpoint <<
124 remote <<
125 }; <<
126 }; <<
127 #endif <<
128 }; 114 };
129 }; 115 };
130 }; 116 };
131 117
132 &i2c2 { 118 &i2c2 {
133 pinctrl-0 = <&i2c2_pins>; 119 pinctrl-0 = <&i2c2_pins>;
134 pinctrl-names = "default"; 120 pinctrl-names = "default";
135 clock-frequency = <400000>; 121 clock-frequency = <400000>;
136 122
137 status = "okay"; 123 status = "okay";
138 124
139 wm8978: codec@1a { 125 wm8978: codec@1a {
140 compatible = "wlf,wm8978"; 126 compatible = "wlf,wm8978";
141 #sound-dai-cells = <0>; 127 #sound-dai-cells = <0>;
142 reg = <0x1a>; 128 reg = <0x1a>;
143 }; 129 };
144 <<
145 versa3: clock-generator@68 { <<
146 compatible = "renesas,5p35023" <<
147 reg = <0x68>; <<
148 #clock-cells = <1>; <<
149 clocks = <&x1>; <<
150 <<
151 renesas,settings = [ <<
152 80 00 11 19 4c 02 23 7 <<
153 00 14 7a e1 00 00 00 0 <<
154 80 b0 45 c4 95 <<
155 ]; <<
156 <<
157 assigned-clocks = <&versa3 0>, <<
158 <&versa3 2>, <<
159 <&versa3 4>, <<
160 assigned-clock-rates = <240000 <<
161 <112896 <<
162 <250000 <<
163 }; <<
164 }; <<
165 <<
166 #if PMOD_MTU3 <<
167 &mtu3 { <<
168 pinctrl-0 = <&mtu3_pins>; <<
169 pinctrl-names = "default"; <<
170 <<
171 status = "okay"; <<
172 }; <<
173 <<
174 &spi1 { <<
175 status = "disabled"; <<
176 }; 130 };
177 #endif <<
178 131
179 /* 132 /*
180 * To enable SCIF1 (SER0) on PMOD1 (CN7), On c 133 * To enable SCIF1 (SER0) on PMOD1 (CN7), On connector board
181 * SW1 should be at position 2->3 so that SER0 134 * SW1 should be at position 2->3 so that SER0_CTS# line is activated
182 * SW2 should be at position 2->3 so that SER0 135 * SW2 should be at position 2->3 so that SER0_TX line is activated
183 * SW3 should be at position 2->3 so that SER0 136 * SW3 should be at position 2->3 so that SER0_RX line is activated
184 * SW4 should be at position 2->3 so that SER0 137 * SW4 should be at position 2->3 so that SER0_RTS# line is activated
185 */ 138 */
186 #if (!SW_SCIF_CAN && PMOD1_SER0) 139 #if (!SW_SCIF_CAN && PMOD1_SER0)
187 &scif1 { 140 &scif1 {
188 pinctrl-0 = <&scif1_pins>; 141 pinctrl-0 = <&scif1_pins>;
189 pinctrl-names = "default"; 142 pinctrl-names = "default";
190 143
191 uart-has-rtscts; 144 uart-has-rtscts;
192 status = "okay"; 145 status = "okay";
193 }; 146 };
194 #endif 147 #endif
195 148
196 &ssi0 { 149 &ssi0 {
197 pinctrl-0 = <&ssi0_pins>; 150 pinctrl-0 = <&ssi0_pins>;
198 pinctrl-names = "default"; 151 pinctrl-names = "default";
199 152
200 status = "okay"; 153 status = "okay";
201 <<
202 #if (SW_I2S0_I2S1) <<
203 i2s2_port: port { <<
204 i2s2_cpu_endpoint: endpoint { <<
205 remote-endpoint = <&co <<
206 dai-format = "i2s"; <<
207 <<
208 bitclock-master = <&i2 <<
209 frame-master = <&i2s2_ <<
210 }; <<
211 }; <<
212 #endif <<
213 }; 154 };
214 155
215 #if (SW_RSPI_CAN) 156 #if (SW_RSPI_CAN)
216 &spi1 { 157 &spi1 {
217 /delete-property/ pinctrl-0; 158 /delete-property/ pinctrl-0;
218 /delete-property/ pinctrl-names; 159 /delete-property/ pinctrl-names;
219 status = "disabled"; 160 status = "disabled";
220 }; 161 };
221 #endif 162 #endif
222 163
223 &vccq_sdhi1 { 164 &vccq_sdhi1 {
224 gpios = <&pinctrl RZG2L_GPIO(39, 1) GP 165 gpios = <&pinctrl RZG2L_GPIO(39, 1) GPIO_ACTIVE_HIGH>;
225 }; 166 };
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