1 // SPDX-License-Identifier: (GPL-2.0-only OR B 1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 /* 2 /*
3 * Device Tree Source for the RZ/G2LC SMARC EV 3 * Device Tree Source for the RZ/G2LC SMARC EVK parts
4 * 4 *
5 * Copyright (C) 2022 Renesas Electronics Corp 5 * Copyright (C) 2022 Renesas Electronics Corp.
6 */ 6 */
7 7
8 #include <dt-bindings/gpio/gpio.h> 8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/pinctrl/rzg2l-pinctrl.h> 9 #include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
10 10
11 #include "rzg2lc-smarc-pinfunction.dtsi" 11 #include "rzg2lc-smarc-pinfunction.dtsi"
12 #include "rz-smarc-common.dtsi" 12 #include "rz-smarc-common.dtsi"
13 13
14 / { 14 / {
15 aliases { 15 aliases {
16 serial1 = &scif1; 16 serial1 = &scif1;
17 i2c2 = &i2c2; 17 i2c2 = &i2c2;
18 }; 18 };
19 19
20 osc1: cec-clock { 20 osc1: cec-clock {
21 compatible = "fixed-clock"; 21 compatible = "fixed-clock";
22 #clock-cells = <0>; 22 #clock-cells = <0>;
23 clock-frequency = <12000000>; 23 clock-frequency = <12000000>;
24 }; 24 };
25 25
26 hdmi-out { 26 hdmi-out {
27 compatible = "hdmi-connector"; 27 compatible = "hdmi-connector";
28 type = "d"; 28 type = "d";
29 29
30 port { 30 port {
31 hdmi_con_out: endpoint 31 hdmi_con_out: endpoint {
32 remote-endpoin 32 remote-endpoint = <&adv7535_out>;
33 }; 33 };
34 }; 34 };
35 }; 35 };
36 <<
37 #if (SW_I2S0_I2S1) <<
38 /delete-node/ sound; <<
39 <<
40 sound_card { <<
41 compatible = "audio-graph-card <<
42 label = "HDMI-Audio"; <<
43 dais = <&i2s2_port>; <<
44 }; <<
45 #endif <<
46 }; 36 };
47 37
48 #if (SW_SCIF_CAN || SW_RSPI_CAN) 38 #if (SW_SCIF_CAN || SW_RSPI_CAN)
49 &canfd { 39 &canfd {
50 pinctrl-0 = <&can1_pins>; 40 pinctrl-0 = <&can1_pins>;
51 /delete-node/ channel@0; 41 /delete-node/ channel@0;
52 }; 42 };
53 #else 43 #else
54 &canfd { 44 &canfd {
55 /delete-property/ pinctrl-0; 45 /delete-property/ pinctrl-0;
56 /delete-property/ pinctrl-names; 46 /delete-property/ pinctrl-names;
57 status = "disabled"; 47 status = "disabled";
58 }; 48 };
59 #endif 49 #endif
60 50
61 #if (!SW_I2S0_I2S1) <<
62 &cpu_dai { 51 &cpu_dai {
63 sound-dai = <&ssi0>; 52 sound-dai = <&ssi0>;
64 }; 53 };
65 #endif <<
66 54
67 &dsi { 55 &dsi {
68 status = "okay"; 56 status = "okay";
69 57
70 ports { 58 ports {
>> 59 #address-cells = <1>;
>> 60 #size-cells = <0>;
>> 61
>> 62 port@0 {
>> 63 reg = <0>;
>> 64 dsi0_in: endpoint {
>> 65 };
>> 66 };
>> 67
71 port@1 { 68 port@1 {
>> 69 reg = <1>;
72 dsi0_out: endpoint { 70 dsi0_out: endpoint {
73 data-lanes = < 71 data-lanes = <1 2 3 4>;
74 remote-endpoin 72 remote-endpoint = <&adv7535_in>;
75 }; 73 };
76 }; 74 };
77 }; 75 };
78 }; 76 };
79 77
80 &du { <<
81 status = "okay"; <<
82 }; <<
83 <<
84 &i2c1 { 78 &i2c1 {
85 adv7535: hdmi@3d { 79 adv7535: hdmi@3d {
86 compatible = "adi,adv7535"; 80 compatible = "adi,adv7535";
87 reg = <0x3d>; 81 reg = <0x3d>;
88 82
89 interrupt-parent = <&pinctrl>; 83 interrupt-parent = <&pinctrl>;
90 interrupts = <RZG2L_GPIO(43, 1 84 interrupts = <RZG2L_GPIO(43, 1) IRQ_TYPE_EDGE_FALLING>;
91 clocks = <&osc1>; 85 clocks = <&osc1>;
92 clock-names = "cec"; 86 clock-names = "cec";
93 avdd-supply = <®_1p8v>; 87 avdd-supply = <®_1p8v>;
94 dvdd-supply = <®_1p8v>; 88 dvdd-supply = <®_1p8v>;
95 pvdd-supply = <®_1p8v>; 89 pvdd-supply = <®_1p8v>;
96 a2vdd-supply = <®_1p8v>; 90 a2vdd-supply = <®_1p8v>;
97 v3p3-supply = <®_3p3v>; 91 v3p3-supply = <®_3p3v>;
98 v1p2-supply = <®_1p8v>; 92 v1p2-supply = <®_1p8v>;
99 93
100 adi,dsi-lanes = <4>; 94 adi,dsi-lanes = <4>;
101 95
102 ports { 96 ports {
103 #address-cells = <1>; 97 #address-cells = <1>;
104 #size-cells = <0>; 98 #size-cells = <0>;
105 99
106 port@0 { 100 port@0 {
107 reg = <0>; 101 reg = <0>;
108 adv7535_in: en 102 adv7535_in: endpoint {
109 remote 103 remote-endpoint = <&dsi0_out>;
110 }; 104 };
111 }; 105 };
112 106
113 port@1 { 107 port@1 {
114 reg = <1>; 108 reg = <1>;
115 adv7535_out: e 109 adv7535_out: endpoint {
116 remote 110 remote-endpoint = <&hdmi_con_out>;
117 }; 111 };
118 }; 112 };
119 <<
120 #if (SW_I2S0_I2S1) <<
121 port@2 { <<
122 reg = <2>; <<
123 codec_endpoint <<
124 remote <<
125 }; <<
126 }; <<
127 #endif <<
128 }; 113 };
129 }; 114 };
130 }; 115 };
131 116
132 &i2c2 { 117 &i2c2 {
133 pinctrl-0 = <&i2c2_pins>; 118 pinctrl-0 = <&i2c2_pins>;
134 pinctrl-names = "default"; 119 pinctrl-names = "default";
135 clock-frequency = <400000>; 120 clock-frequency = <400000>;
136 121
137 status = "okay"; 122 status = "okay";
138 123
139 wm8978: codec@1a { 124 wm8978: codec@1a {
140 compatible = "wlf,wm8978"; 125 compatible = "wlf,wm8978";
141 #sound-dai-cells = <0>; 126 #sound-dai-cells = <0>;
142 reg = <0x1a>; 127 reg = <0x1a>;
143 }; 128 };
144 129
145 versa3: clock-generator@68 { 130 versa3: clock-generator@68 {
146 compatible = "renesas,5p35023" 131 compatible = "renesas,5p35023";
147 reg = <0x68>; 132 reg = <0x68>;
148 #clock-cells = <1>; 133 #clock-cells = <1>;
149 clocks = <&x1>; 134 clocks = <&x1>;
150 135
151 renesas,settings = [ 136 renesas,settings = [
152 80 00 11 19 4c 02 23 7 137 80 00 11 19 4c 02 23 7f 83 19 08 a9 5f 25 24 bf
153 00 14 7a e1 00 00 00 0 138 00 14 7a e1 00 00 00 00 01 55 59 bb 3f 30 90 b6
154 80 b0 45 c4 95 139 80 b0 45 c4 95
155 ]; 140 ];
156 141
157 assigned-clocks = <&versa3 0>, 142 assigned-clocks = <&versa3 0>, <&versa3 1>,
158 <&versa3 2>, 143 <&versa3 2>, <&versa3 3>,
159 <&versa3 4>, 144 <&versa3 4>, <&versa3 5>;
160 assigned-clock-rates = <240000 145 assigned-clock-rates = <24000000>, <11289600>,
161 <112896 146 <11289600>, <12000000>,
162 <250000 147 <25000000>, <12288000>;
163 }; 148 };
164 }; 149 };
165 150
166 #if PMOD_MTU3 151 #if PMOD_MTU3
167 &mtu3 { 152 &mtu3 {
168 pinctrl-0 = <&mtu3_pins>; 153 pinctrl-0 = <&mtu3_pins>;
169 pinctrl-names = "default"; 154 pinctrl-names = "default";
170 155
171 status = "okay"; 156 status = "okay";
172 }; 157 };
173 158
174 &spi1 { 159 &spi1 {
175 status = "disabled"; 160 status = "disabled";
176 }; 161 };
177 #endif 162 #endif
178 163
179 /* 164 /*
180 * To enable SCIF1 (SER0) on PMOD1 (CN7), On c 165 * To enable SCIF1 (SER0) on PMOD1 (CN7), On connector board
181 * SW1 should be at position 2->3 so that SER0 166 * SW1 should be at position 2->3 so that SER0_CTS# line is activated
182 * SW2 should be at position 2->3 so that SER0 167 * SW2 should be at position 2->3 so that SER0_TX line is activated
183 * SW3 should be at position 2->3 so that SER0 168 * SW3 should be at position 2->3 so that SER0_RX line is activated
184 * SW4 should be at position 2->3 so that SER0 169 * SW4 should be at position 2->3 so that SER0_RTS# line is activated
185 */ 170 */
186 #if (!SW_SCIF_CAN && PMOD1_SER0) 171 #if (!SW_SCIF_CAN && PMOD1_SER0)
187 &scif1 { 172 &scif1 {
188 pinctrl-0 = <&scif1_pins>; 173 pinctrl-0 = <&scif1_pins>;
189 pinctrl-names = "default"; 174 pinctrl-names = "default";
190 175
191 uart-has-rtscts; 176 uart-has-rtscts;
192 status = "okay"; 177 status = "okay";
193 }; 178 };
194 #endif 179 #endif
195 180
196 &ssi0 { 181 &ssi0 {
197 pinctrl-0 = <&ssi0_pins>; 182 pinctrl-0 = <&ssi0_pins>;
198 pinctrl-names = "default"; 183 pinctrl-names = "default";
199 184
200 status = "okay"; 185 status = "okay";
201 <<
202 #if (SW_I2S0_I2S1) <<
203 i2s2_port: port { <<
204 i2s2_cpu_endpoint: endpoint { <<
205 remote-endpoint = <&co <<
206 dai-format = "i2s"; <<
207 <<
208 bitclock-master = <&i2 <<
209 frame-master = <&i2s2_ <<
210 }; <<
211 }; <<
212 #endif <<
213 }; 186 };
214 187
215 #if (SW_RSPI_CAN) 188 #if (SW_RSPI_CAN)
216 &spi1 { 189 &spi1 {
217 /delete-property/ pinctrl-0; 190 /delete-property/ pinctrl-0;
218 /delete-property/ pinctrl-names; 191 /delete-property/ pinctrl-names;
219 status = "disabled"; 192 status = "disabled";
220 }; 193 };
221 #endif 194 #endif
222 195
223 &vccq_sdhi1 { 196 &vccq_sdhi1 {
224 gpios = <&pinctrl RZG2L_GPIO(39, 1) GP 197 gpios = <&pinctrl RZG2L_GPIO(39, 1) GPIO_ACTIVE_HIGH>;
225 }; 198 };
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