1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /*
3 * Copyright (c) 2018 Fuzhou Rockchip Electron
4 */
5
6 /dts-v1/;
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/input/input.h>
9 #include <dt-bindings/pinctrl/rockchip.h>
10 #include "px30.dtsi"
11
12 / {
13 model = "Rockchip PX30 EVB";
14 compatible = "rockchip,px30-evb", "roc
15
16 aliases {
17 ethernet0 = &gmac;
18 mmc0 = &sdmmc;
19 mmc1 = &sdio;
20 mmc2 = &emmc;
21 };
22
23 chosen {
24 stdout-path = "serial5:115200n
25 };
26
27 adc-keys {
28 compatible = "adc-keys";
29 io-channels = <&saradc 2>;
30 io-channel-names = "buttons";
31 keyup-threshold-microvolt = <1
32 poll-interval = <100>;
33
34 button-esc {
35 label = "esc";
36 linux,code = <KEY_ESC>
37 press-threshold-microv
38 };
39
40 button-home {
41 label = "home";
42 linux,code = <KEY_HOME
43 press-threshold-microv
44 };
45
46 button-menu {
47 label = "menu";
48 linux,code = <KEY_MENU
49 press-threshold-microv
50 };
51
52 button-down {
53 label = "volume down";
54 linux,code = <KEY_VOLU
55 press-threshold-microv
56 };
57
58 button-up {
59 label = "volume up";
60 linux,code = <KEY_VOLU
61 press-threshold-microv
62 };
63 };
64
65 backlight: backlight {
66 compatible = "pwm-backlight";
67 pwms = <&pwm1 0 25000 0>;
68 power-supply = <&vcc3v3_lcd>;
69 };
70
71 emmc_pwrseq: emmc-pwrseq {
72 compatible = "mmc-pwrseq-emmc"
73 pinctrl-0 = <&emmc_reset>;
74 pinctrl-names = "default";
75 reset-gpios = <&gpio1 RK_PB3 G
76 };
77
78 sdio_pwrseq: sdio-pwrseq {
79 compatible = "mmc-pwrseq-simpl
80 pinctrl-names = "default";
81 pinctrl-0 = <&wifi_enable_h>;
82
83 /*
84 * On the module itself this i
85 * on the actual card populate
86 * - SDIO_RESET_L_WL_REG_ON
87 * - PDN (power down when low)
88 */
89 reset-gpios = <&gpio0 RK_PA2 G
90 };
91
92 vcc5v0_sys: vccsys {
93 compatible = "regulator-fixed"
94 regulator-name = "vcc5v0_sys";
95 regulator-always-on;
96 regulator-boot-on;
97 regulator-min-microvolt = <500
98 regulator-max-microvolt = <500
99 };
100 };
101
102 &cpu0 {
103 cpu-supply = <&vdd_arm>;
104 };
105
106 &cpu1 {
107 cpu-supply = <&vdd_arm>;
108 };
109
110 &cpu2 {
111 cpu-supply = <&vdd_arm>;
112 };
113
114 &cpu3 {
115 cpu-supply = <&vdd_arm>;
116 };
117
118 &csi_dphy {
119 status = "okay";
120 };
121
122 &display_subsystem {
123 status = "okay";
124 };
125
126 &dsi {
127 status = "okay";
128
129 ports {
130 mipi_out: port@1 {
131 reg = <1>;
132
133 mipi_out_panel: endpoi
134 remote-endpoin
135 };
136 };
137 };
138
139 panel@0 {
140 compatible = "xinpeng,xpp055c2
141 reg = <0>;
142 backlight = <&backlight>;
143 iovcc-supply = <&vcc_1v8>;
144 vci-supply = <&vcc3v3_lcd>;
145
146 port {
147 mipi_in_panel: endpoin
148 remote-endpoin
149 };
150 };
151 };
152 };
153
154 &dsi_dphy {
155 status = "okay";
156 };
157
158 &emmc {
159 cap-mmc-highspeed;
160 mmc-hs200-1_8v;
161 non-removable;
162 mmc-pwrseq = <&emmc_pwrseq>;
163 vmmc-supply = <&vcc_3v0>;
164 vqmmc-supply = <&vccio_flash>;
165 status = "okay";
166 };
167
168 &gmac {
169 clock_in_out = "output";
170 phy-supply = <&vcc_rmii>;
171 snps,reset-gpio = <&gpio2 13 GPIO_ACTI
172 snps,reset-active-low;
173 snps,reset-delays-us = <0 50000 50000>
174 status = "okay";
175 };
176
177 &gpu {
178 mali-supply = <&vdd_log>;
179 status = "okay";
180 };
181
182 &i2c0 {
183 status = "okay";
184
185 rk809: pmic@20 {
186 compatible = "rockchip,rk809";
187 reg = <0x20>;
188 interrupt-parent = <&gpio0>;
189 interrupts = <7 IRQ_TYPE_LEVEL
190 pinctrl-names = "default";
191 pinctrl-0 = <&pmic_int>;
192 rockchip,system-power-controll
193 wakeup-source;
194 #clock-cells = <0>;
195 clock-output-names = "xin32k";
196
197 vcc1-supply = <&vcc5v0_sys>;
198 vcc2-supply = <&vcc5v0_sys>;
199 vcc3-supply = <&vcc5v0_sys>;
200 vcc4-supply = <&vcc5v0_sys>;
201 vcc5-supply = <&vcc3v3_sys>;
202 vcc6-supply = <&vcc3v3_sys>;
203 vcc7-supply = <&vcc3v3_sys>;
204 vcc8-supply = <&vcc3v3_sys>;
205 vcc9-supply = <&vcc5v0_sys>;
206
207 regulators {
208 vdd_log: DCDC_REG1 {
209 regulator-name
210 regulator-min-
211 regulator-max-
212 regulator-ramp
213 regulator-alwa
214 regulator-boot
215
216 regulator-stat
217 regula
218 regula
219 };
220 };
221
222 vdd_arm: DCDC_REG2 {
223 regulator-name
224 regulator-min-
225 regulator-max-
226 regulator-ramp
227 regulator-alwa
228 regulator-boot
229
230 regulator-stat
231 regula
232 regula
233 };
234 };
235
236 vcc_ddr: DCDC_REG3 {
237 regulator-name
238 regulator-alwa
239 regulator-boot
240
241 regulator-stat
242 regula
243 };
244 };
245
246 vcc_3v0: vcc_rmii: DCD
247 regulator-name
248 regulator-min-
249 regulator-max-
250 regulator-alwa
251 regulator-boot
252
253 regulator-stat
254 regula
255 regula
256 };
257 };
258
259 vcc3v3_sys: DCDC_REG5
260 regulator-name
261 regulator-min-
262 regulator-max-
263 regulator-alwa
264 regulator-boot
265
266 regulator-stat
267 regula
268 regula
269 };
270 };
271
272 vcc_1v0: LDO_REG1 {
273 regulator-name
274 regulator-min-
275 regulator-max-
276 regulator-alwa
277 regulator-boot
278
279 regulator-stat
280 regula
281 regula
282 };
283 };
284
285 vcc_1v8: vccio_flash:
286 regulator-name
287 regulator-min-
288 regulator-max-
289 regulator-alwa
290 regulator-boot
291
292 regulator-stat
293 regula
294 regula
295 };
296 };
297
298 vdd_1v0: LDO_REG3 {
299 regulator-name
300 regulator-min-
301 regulator-max-
302 regulator-alwa
303 regulator-boot
304
305 regulator-stat
306 regula
307 regula
308 };
309 };
310
311 vcc3v0_pmu: LDO_REG4 {
312 regulator-name
313 regulator-min-
314 regulator-max-
315 regulator-alwa
316 regulator-boot
317
318 regulator-stat
319 regula
320 regula
321 };
322 };
323
324 vccio_sd: LDO_REG5 {
325 regulator-name
326 regulator-min-
327 regulator-max-
328 regulator-alwa
329 regulator-boot
330
331 regulator-stat
332 regula
333 regula
334 };
335 };
336
337 vcc_sd: LDO_REG6 {
338 regulator-name
339 regulator-min-
340 regulator-max-
341 regulator-boot
342
343 regulator-stat
344 regula
345 regula
346 };
347 };
348
349 vcc2v8_dvp: LDO_REG7 {
350 regulator-name
351 regulator-min-
352 regulator-max-
353 regulator-boot
354
355 regulator-stat
356 regula
357 regula
358 };
359 };
360
361 vcc1v8_dvp: LDO_REG8 {
362 regulator-name
363 regulator-min-
364 regulator-max-
365 regulator-boot
366
367 regulator-stat
368 regula
369 regula
370 };
371 };
372
373 vcc1v5_dvp: LDO_REG9 {
374 regulator-name
375 regulator-min-
376 regulator-max-
377 regulator-boot
378
379 regulator-stat
380 regula
381 regula
382 };
383 };
384
385 vcc3v3_lcd: SWITCH_REG
386 regulator-name
387 regulator-boot
388 };
389
390 vcc5v0_host: SWITCH_RE
391 regulator-name
392 regulator-alwa
393 regulator-boot
394 };
395 };
396 };
397 };
398
399 &i2c1 {
400 status = "okay";
401
402 sensor@d {
403 compatible = "asahi-kasei,ak89
404 reg = <0x0d>;
405 gpios = <&gpio0 RK_PB7 GPIO_AC
406 vdd-supply = <&vcc3v0_pmu>;
407 mount-matrix = "1", /* x0 */
408 "0", /* y0 */
409 "0", /* z0 */
410 "0", /* x1 */
411 "1", /* y1 */
412 "0", /* z1 */
413 "0", /* x2 */
414 "0", /* y2 */
415 "1"; /* z2 */
416 };
417
418 touchscreen@14 {
419 compatible = "goodix,gt1151";
420 reg = <0x14>;
421 interrupt-parent = <&gpio0>;
422 interrupts = <RK_PA5 IRQ_TYPE_
423 irq-gpios = <&gpio0 RK_PA5 GPI
424 reset-gpios = <&gpio0 RK_PB4 G
425 VDDIO-supply = <&vcc3v3_lcd>;
426 };
427
428 sensor@4c {
429 compatible = "fsl,mma7660";
430 reg = <0x4c>;
431 interrupt-parent = <&gpio0>;
432 interrupts = <RK_PB7 IRQ_TYPE_
433 };
434 };
435
436 &i2c2 {
437 status = "okay";
438
439 clock-frequency = <100000>;
440
441 /* These are relatively safe rise/fall
442 i2c-scl-falling-time-ns = <50>;
443 i2c-scl-rising-time-ns = <300>;
444
445 ov5695: ov5695@36 {
446 compatible = "ovti,ov5695";
447 reg = <0x36>;
448 avdd-supply = <&vcc2v8_dvp>;
449 clocks = <&cru SCLK_CIF_OUT>;
450 clock-names = "xvclk";
451 dvdd-supply = <&vcc1v5_dvp>;
452 dovdd-supply = <&vcc1v8_dvp>;
453 pinctrl-names = "default";
454 pinctrl-0 = <&cif_clkout_m0 &m
455 reset-gpios = <&gpio2 RK_PB6 G
456
457 port {
458 ucam_out: endpoint {
459 remote-endpoin
460 data-lanes = <
461 };
462 };
463 };
464 };
465
466 &i2s1_2ch {
467 status = "okay";
468 };
469
470 &io_domains {
471 status = "okay";
472
473 vccio1-supply = <&vccio_sdio>;
474 vccio2-supply = <&vccio_sd>;
475 vccio3-supply = <&vcc_3v0>;
476 vccio4-supply = <&vcc3v0_pmu>;
477 vccio5-supply = <&vcc_3v0>;
478 vccio6-supply = <&vccio_flash>;
479 };
480
481 &isp {
482 status = "okay";
483
484 ports {
485 port@0 {
486 mipi_in_ucam: endpoint
487 reg = <0>;
488 data-lanes = <
489 remote-endpoin
490 };
491 };
492 };
493 };
494
495 &isp_mmu {
496 status = "okay";
497 };
498
499 &pinctrl {
500 headphone {
501 hp_det: hp-det {
502 rockchip,pins =
503 <2 RK_PB0 RK_F
504 };
505 };
506
507 emmc {
508 emmc_reset: emmc-reset {
509 rockchip,pins = <1 RK_
510 };
511 };
512
513 pmic {
514 pmic_int: pmic_int {
515 rockchip,pins =
516 <0 RK_PA7 RK_F
517 };
518
519 soc_slppin_gpio: soc_slppin_gp
520 rockchip,pins =
521 <0 RK_PA4 RK_F
522 };
523
524 soc_slppin_slp: soc_slppin_slp
525 rockchip,pins =
526 <0 RK_PA4 1 &p
527 };
528
529 soc_slppin_rst: soc_slppin_rst
530 rockchip,pins =
531 <0 RK_PA4 2 &p
532 };
533 };
534
535 sdio-pwrseq {
536 wifi_enable_h: wifi-enable-h {
537 rockchip,pins =
538 <0 RK_PA2 RK_F
539 };
540 };
541
542 cif-m0 {
543 cif_clkout_m0: cif-clkout-m0 {
544 rockchip,pins =
545 <2 RK_PB3 1 &p
546 };
547 };
548
549 mipi {
550 mipi_pdn: mipi-pdn {
551 rockchip,pins = <2 RK_
552 };
553 };
554 };
555
556 &pmu_io_domains {
557 status = "okay";
558
559 pmuio1-supply = <&vcc3v0_pmu>;
560 pmuio2-supply = <&vcc3v0_pmu>;
561 };
562
563 &pwm1 {
564 status = "okay";
565 };
566
567 &saradc {
568 vref-supply = <&vcc_1v8>;
569 status = "okay";
570 };
571
572 &sdmmc {
573 cap-mmc-highspeed;
574 cap-sd-highspeed;
575 card-detect-delay = <800>;
576 sd-uhs-sdr12;
577 sd-uhs-sdr25;
578 sd-uhs-sdr50;
579 sd-uhs-sdr104;
580 vmmc-supply = <&vcc_sd>;
581 vqmmc-supply = <&vccio_sd>;
582 status = "okay";
583 };
584
585 &sdio {
586 cap-sd-highspeed;
587 keep-power-in-suspend;
588 non-removable;
589 mmc-pwrseq = <&sdio_pwrseq>;
590 sd-uhs-sdr104;
591 status = "okay";
592 };
593
594 &tsadc {
595 rockchip,hw-tshut-mode = <1>;
596 rockchip,hw-tshut-polarity = <1>;
597 status = "okay";
598 };
599
600 &u2phy {
601 status = "okay";
602
603 u2phy_host: host-port {
604 status = "okay";
605 };
606
607 u2phy_otg: otg-port {
608 status = "okay";
609 };
610 };
611
612 &uart1 {
613 pinctrl-names = "default";
614 pinctrl-0 = <&uart1_xfer &uart1_cts>;
615 status = "okay";
616 };
617
618 &uart5 {
619 status = "okay";
620 };
621
622 &usb20_otg {
623 status = "okay";
624 };
625
626 &usb_host0_ehci {
627 status = "okay";
628 };
629
630 &usb_host0_ohci {
631 status = "okay";
632 };
633
634 &vopb {
635 status = "okay";
636 };
637
638 &vopb_mmu {
639 status = "okay";
640 };
641
642 &vopl {
643 status = "okay";
644 };
645
646 &vopl_mmu {
647 status = "okay";
648 };
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