1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /*
3 * Copyright (c) 2018 Fuzhou Rockchip Electron
4 */
5
6 #include <dt-bindings/clock/px30-cru.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/interrupt-controller/arm
9 #include <dt-bindings/interrupt-controller/irq
10 #include <dt-bindings/pinctrl/rockchip.h>
11 #include <dt-bindings/power/px30-power.h>
12 #include <dt-bindings/soc/rockchip,boot-mode.h
13 #include <dt-bindings/thermal/thermal.h>
14
15 / {
16 compatible = "rockchip,px30";
17
18 interrupt-parent = <&gic>;
19 #address-cells = <2>;
20 #size-cells = <2>;
21
22 aliases {
23 i2c0 = &i2c0;
24 i2c1 = &i2c1;
25 i2c2 = &i2c2;
26 i2c3 = &i2c3;
27 serial0 = &uart0;
28 serial1 = &uart1;
29 serial2 = &uart2;
30 serial3 = &uart3;
31 serial4 = &uart4;
32 serial5 = &uart5;
33 spi0 = &spi0;
34 spi1 = &spi1;
35 };
36
37 cpus {
38 #address-cells = <2>;
39 #size-cells = <0>;
40
41 cpu0: cpu@0 {
42 device_type = "cpu";
43 compatible = "arm,cort
44 reg = <0x0 0x0>;
45 enable-method = "psci"
46 clocks = <&cru ARMCLK>
47 #cooling-cells = <2>;
48 cpu-idle-states = <&CP
49 dynamic-power-coeffici
50 operating-points-v2 =
51 };
52
53 cpu1: cpu@1 {
54 device_type = "cpu";
55 compatible = "arm,cort
56 reg = <0x0 0x1>;
57 enable-method = "psci"
58 clocks = <&cru ARMCLK>
59 #cooling-cells = <2>;
60 cpu-idle-states = <&CP
61 dynamic-power-coeffici
62 operating-points-v2 =
63 };
64
65 cpu2: cpu@2 {
66 device_type = "cpu";
67 compatible = "arm,cort
68 reg = <0x0 0x2>;
69 enable-method = "psci"
70 clocks = <&cru ARMCLK>
71 #cooling-cells = <2>;
72 cpu-idle-states = <&CP
73 dynamic-power-coeffici
74 operating-points-v2 =
75 };
76
77 cpu3: cpu@3 {
78 device_type = "cpu";
79 compatible = "arm,cort
80 reg = <0x0 0x3>;
81 enable-method = "psci"
82 clocks = <&cru ARMCLK>
83 #cooling-cells = <2>;
84 cpu-idle-states = <&CP
85 dynamic-power-coeffici
86 operating-points-v2 =
87 };
88
89 idle-states {
90 entry-method = "psci";
91
92 CPU_SLEEP: cpu-sleep {
93 compatible = "
94 local-timer-st
95 arm,psci-suspe
96 entry-latency-
97 exit-latency-u
98 min-residency-
99 };
100
101 CLUSTER_SLEEP: cluster
102 compatible = "
103 local-timer-st
104 arm,psci-suspe
105 entry-latency-
106 exit-latency-u
107 min-residency-
108 };
109 };
110 };
111
112 cpu0_opp_table: opp-table-0 {
113 compatible = "operating-points
114 opp-shared;
115
116 opp-600000000 {
117 opp-hz = /bits/ 64 <60
118 opp-microvolt = <95000
119 clock-latency-ns = <40
120 opp-suspend;
121 };
122 opp-816000000 {
123 opp-hz = /bits/ 64 <81
124 opp-microvolt = <10500
125 clock-latency-ns = <40
126 };
127 opp-1008000000 {
128 opp-hz = /bits/ 64 <10
129 opp-microvolt = <11750
130 clock-latency-ns = <40
131 };
132 opp-1200000000 {
133 opp-hz = /bits/ 64 <12
134 opp-microvolt = <13000
135 clock-latency-ns = <40
136 };
137 opp-1296000000 {
138 opp-hz = /bits/ 64 <12
139 opp-microvolt = <13500
140 clock-latency-ns = <40
141 };
142 };
143
144 arm-pmu {
145 compatible = "arm,cortex-a35-p
146 interrupts = <GIC_SPI 100 IRQ_
147 <GIC_SPI 101 IRQ_
148 <GIC_SPI 102 IRQ_
149 <GIC_SPI 103 IRQ_
150 interrupt-affinity = <&cpu0>,
151 };
152
153 display_subsystem: display-subsystem {
154 compatible = "rockchip,display
155 ports = <&vopb_out>, <&vopl_ou
156 status = "disabled";
157 };
158
159 gmac_clkin: external-gmac-clock {
160 compatible = "fixed-clock";
161 clock-frequency = <50000000>;
162 clock-output-names = "gmac_clk
163 #clock-cells = <0>;
164 };
165
166 psci {
167 compatible = "arm,psci-1.0";
168 method = "smc";
169 };
170
171 timer {
172 compatible = "arm,armv8-timer"
173 interrupts = <GIC_PPI 13 (GIC_
174 <GIC_PPI 14 (GIC_
175 <GIC_PPI 11 (GIC_
176 <GIC_PPI 10 (GIC_
177 };
178
179 thermal_zones: thermal-zones {
180 soc_thermal: soc-thermal {
181 polling-delay-passive
182 polling-delay = <1000>
183 sustainable-power = <7
184 thermal-sensors = <&ts
185
186 trips {
187 threshold: tri
188 temper
189 hyster
190 type =
191 };
192
193 target: trip-p
194 temper
195 hyster
196 type =
197 };
198
199 soc_crit: soc-
200 temper
201 hyster
202 type =
203 };
204 };
205
206 cooling-maps {
207 map0 {
208 trip =
209 coolin
210 contri
211 };
212 };
213 };
214
215 gpu_thermal: gpu-thermal {
216 polling-delay-passive
217 polling-delay = <1000>
218 thermal-sensors = <&ts
219
220 trips {
221 gpu_threshold:
222 temper
223 hyster
224 type =
225 };
226
227 gpu_target: gp
228 temper
229 hyster
230 type =
231 };
232
233 gpu_crit: gpu-
234 temper
235 hyster
236 type =
237 };
238 };
239
240 cooling-maps {
241 map0 {
242 trip =
243 coolin
244 };
245 };
246 };
247 };
248
249 xin24m: xin24m {
250 compatible = "fixed-clock";
251 #clock-cells = <0>;
252 clock-frequency = <24000000>;
253 clock-output-names = "xin24m";
254 };
255
256 pmu: power-management@ff000000 {
257 compatible = "rockchip,px30-pm
258 reg = <0x0 0xff000000 0x0 0x10
259
260 power: power-controller {
261 compatible = "rockchip
262 #power-domain-cells =
263 #address-cells = <1>;
264 #size-cells = <0>;
265
266 /* These power domains
267 power-domain@PX30_PD_U
268 reg = <PX30_PD
269 clocks = <&cru
270 <&cru
271 <&cru
272 pm_qos = <&qos
273 #power-domain-
274 };
275 power-domain@PX30_PD_S
276 reg = <PX30_PD
277 clocks = <&cru
278 <&cru
279 pm_qos = <&qos
280 #power-domain-
281 };
282 power-domain@PX30_PD_G
283 reg = <PX30_PD
284 clocks = <&cru
285 <&cru
286 <&cru
287 <&cru
288 pm_qos = <&qos
289 #power-domain-
290 };
291 power-domain@PX30_PD_M
292 reg = <PX30_PD
293 clocks = <&cru
294 <&cru
295 <&cru
296 <&cru
297 <&cru
298 <&cru
299 <&cru
300 <&cru
301 pm_qos = <&qos
302 <&qos
303 #power-domain-
304 };
305 power-domain@PX30_PD_V
306 reg = <PX30_PD
307 clocks = <&cru
308 <&cru
309 <&cru
310 pm_qos = <&qos
311 #power-domain-
312 };
313 power-domain@PX30_PD_V
314 reg = <PX30_PD
315 clocks = <&cru
316 <&cru
317 <&cru
318 <&cru
319 <&cru
320 <&cru
321 <&cru
322 <&cru
323 <&cru
324 <&cru
325 <&cru
326 pm_qos = <&qos
327 <&qos
328 #power-domain-
329 };
330 power-domain@PX30_PD_V
331 reg = <PX30_PD
332 clocks = <&cru
333 <&cru
334 <&cru
335 <&cru
336 <&cru
337 pm_qos = <&qos
338 <&qos
339 <&qos
340 #power-domain-
341 };
342 power-domain@PX30_PD_G
343 reg = <PX30_PD
344 clocks = <&cru
345 pm_qos = <&qos
346 #power-domain-
347 };
348 };
349 };
350
351 pmugrf: syscon@ff010000 {
352 compatible = "rockchip,px30-pm
353 reg = <0x0 0xff010000 0x0 0x10
354 #address-cells = <1>;
355 #size-cells = <1>;
356
357 pmu_io_domains: io-domains {
358 compatible = "rockchip
359 status = "disabled";
360 };
361
362 reboot-mode {
363 compatible = "syscon-r
364 offset = <0x200>;
365 mode-bootloader = <BOO
366 mode-fastboot = <BOOT_
367 mode-loader = <BOOT_BL
368 mode-normal = <BOOT_NO
369 mode-recovery = <BOOT_
370 };
371 };
372
373 uart0: serial@ff030000 {
374 compatible = "rockchip,px30-ua
375 reg = <0x0 0xff030000 0x0 0x10
376 interrupts = <GIC_SPI 15 IRQ_T
377 clocks = <&pmucru SCLK_UART0_P
378 clock-names = "baudclk", "apb_
379 dmas = <&dmac 0>, <&dmac 1>;
380 dma-names = "tx", "rx";
381 reg-shift = <2>;
382 reg-io-width = <4>;
383 pinctrl-names = "default";
384 pinctrl-0 = <&uart0_xfer &uart
385 status = "disabled";
386 };
387
388 i2s0_8ch: i2s@ff060000 {
389 compatible = "rockchip,px30-i2
390 reg = <0x0 0xff060000 0x0 0x10
391 interrupts = <GIC_SPI 12 IRQ_T
392 clocks = <&cru SCLK_I2S0_TX>,
393 clock-names = "mclk_tx", "mclk
394 dmas = <&dmac 16>, <&dmac 17>;
395 dma-names = "tx", "rx";
396 rockchip,grf = <&grf>;
397 resets = <&cru SRST_I2S0_TX>,
398 reset-names = "tx-m", "rx-m";
399 pinctrl-names = "default";
400 pinctrl-0 = <&i2s0_8ch_sclktx
401 &i2s0_8ch_lrcktx
402 &i2s0_8ch_sdo0 &i
403 &i2s0_8ch_sdo1 &i
404 &i2s0_8ch_sdo2 &i
405 &i2s0_8ch_sdo3 &i
406 #sound-dai-cells = <0>;
407 status = "disabled";
408 };
409
410 i2s1_2ch: i2s@ff070000 {
411 compatible = "rockchip,px30-i2
412 reg = <0x0 0xff070000 0x0 0x10
413 interrupts = <GIC_SPI 13 IRQ_T
414 clocks = <&cru SCLK_I2S1>, <&c
415 clock-names = "i2s_clk", "i2s_
416 dmas = <&dmac 18>, <&dmac 19>;
417 dma-names = "tx", "rx";
418 pinctrl-names = "default";
419 pinctrl-0 = <&i2s1_2ch_sclk &i
420 &i2s1_2ch_sdi &i2
421 #sound-dai-cells = <0>;
422 status = "disabled";
423 };
424
425 i2s2_2ch: i2s@ff080000 {
426 compatible = "rockchip,px30-i2
427 reg = <0x0 0xff080000 0x0 0x10
428 interrupts = <GIC_SPI 14 IRQ_T
429 clocks = <&cru SCLK_I2S2>, <&c
430 clock-names = "i2s_clk", "i2s_
431 dmas = <&dmac 20>, <&dmac 21>;
432 dma-names = "tx", "rx";
433 pinctrl-names = "default";
434 pinctrl-0 = <&i2s2_2ch_sclk &i
435 &i2s2_2ch_sdi &i2
436 #sound-dai-cells = <0>;
437 status = "disabled";
438 };
439
440 gic: interrupt-controller@ff131000 {
441 compatible = "arm,gic-400";
442 #interrupt-cells = <3>;
443 #address-cells = <0>;
444 interrupt-controller;
445 reg = <0x0 0xff131000 0 0x1000
446 <0x0 0xff132000 0 0x2000
447 <0x0 0xff134000 0 0x2000
448 <0x0 0xff136000 0 0x2000
449 interrupts = <GIC_PPI 9
450 (GIC_CPU_MASK_SIMPLE(4)
451 };
452
453 grf: syscon@ff140000 {
454 compatible = "rockchip,px30-gr
455 reg = <0x0 0xff140000 0x0 0x10
456 #address-cells = <1>;
457 #size-cells = <1>;
458
459 io_domains: io-domains {
460 compatible = "rockchip
461 status = "disabled";
462 };
463
464 lvds: lvds {
465 compatible = "rockchip
466 phys = <&dsi_dphy>;
467 phy-names = "dphy";
468 rockchip,grf = <&grf>;
469 rockchip,output = "lvd
470 status = "disabled";
471
472 ports {
473 #address-cells
474 #size-cells =
475
476 lvds_in: port@
477 reg =
478 #addre
479 #size-
480
481 lvds_v
482
483
484 };
485
486 lvds_v
487
488
489 };
490 };
491
492 lvds_out: port
493 reg =
494 };
495 };
496 };
497 };
498
499 uart1: serial@ff158000 {
500 compatible = "rockchip,px30-ua
501 reg = <0x0 0xff158000 0x0 0x10
502 interrupts = <GIC_SPI 16 IRQ_T
503 clocks = <&cru SCLK_UART1>, <&
504 clock-names = "baudclk", "apb_
505 dmas = <&dmac 2>, <&dmac 3>;
506 dma-names = "tx", "rx";
507 reg-shift = <2>;
508 reg-io-width = <4>;
509 pinctrl-names = "default";
510 pinctrl-0 = <&uart1_xfer &uart
511 status = "disabled";
512 };
513
514 uart2: serial@ff160000 {
515 compatible = "rockchip,px30-ua
516 reg = <0x0 0xff160000 0x0 0x10
517 interrupts = <GIC_SPI 17 IRQ_T
518 clocks = <&cru SCLK_UART2>, <&
519 clock-names = "baudclk", "apb_
520 dmas = <&dmac 4>, <&dmac 5>;
521 dma-names = "tx", "rx";
522 reg-shift = <2>;
523 reg-io-width = <4>;
524 pinctrl-names = "default";
525 pinctrl-0 = <&uart2m0_xfer>;
526 status = "disabled";
527 };
528
529 uart3: serial@ff168000 {
530 compatible = "rockchip,px30-ua
531 reg = <0x0 0xff168000 0x0 0x10
532 interrupts = <GIC_SPI 18 IRQ_T
533 clocks = <&cru SCLK_UART3>, <&
534 clock-names = "baudclk", "apb_
535 dmas = <&dmac 6>, <&dmac 7>;
536 dma-names = "tx", "rx";
537 reg-shift = <2>;
538 reg-io-width = <4>;
539 pinctrl-names = "default";
540 pinctrl-0 = <&uart3m1_xfer &ua
541 status = "disabled";
542 };
543
544 uart4: serial@ff170000 {
545 compatible = "rockchip,px30-ua
546 reg = <0x0 0xff170000 0x0 0x10
547 interrupts = <GIC_SPI 19 IRQ_T
548 clocks = <&cru SCLK_UART4>, <&
549 clock-names = "baudclk", "apb_
550 dmas = <&dmac 8>, <&dmac 9>;
551 dma-names = "tx", "rx";
552 reg-shift = <2>;
553 reg-io-width = <4>;
554 pinctrl-names = "default";
555 pinctrl-0 = <&uart4_xfer &uart
556 status = "disabled";
557 };
558
559 uart5: serial@ff178000 {
560 compatible = "rockchip,px30-ua
561 reg = <0x0 0xff178000 0x0 0x10
562 interrupts = <GIC_SPI 20 IRQ_T
563 clocks = <&cru SCLK_UART5>, <&
564 clock-names = "baudclk", "apb_
565 dmas = <&dmac 10>, <&dmac 11>;
566 dma-names = "tx", "rx";
567 reg-shift = <2>;
568 reg-io-width = <4>;
569 pinctrl-names = "default";
570 pinctrl-0 = <&uart5_xfer &uart
571 status = "disabled";
572 };
573
574 i2c0: i2c@ff180000 {
575 compatible = "rockchip,px30-i2
576 reg = <0x0 0xff180000 0x0 0x10
577 clocks = <&cru SCLK_I2C0>, <&c
578 clock-names = "i2c", "pclk";
579 interrupts = <GIC_SPI 7 IRQ_TY
580 pinctrl-names = "default";
581 pinctrl-0 = <&i2c0_xfer>;
582 #address-cells = <1>;
583 #size-cells = <0>;
584 status = "disabled";
585 };
586
587 i2c1: i2c@ff190000 {
588 compatible = "rockchip,px30-i2
589 reg = <0x0 0xff190000 0x0 0x10
590 clocks = <&cru SCLK_I2C1>, <&c
591 clock-names = "i2c", "pclk";
592 interrupts = <GIC_SPI 8 IRQ_TY
593 pinctrl-names = "default";
594 pinctrl-0 = <&i2c1_xfer>;
595 #address-cells = <1>;
596 #size-cells = <0>;
597 status = "disabled";
598 };
599
600 i2c2: i2c@ff1a0000 {
601 compatible = "rockchip,px30-i2
602 reg = <0x0 0xff1a0000 0x0 0x10
603 clocks = <&cru SCLK_I2C2>, <&c
604 clock-names = "i2c", "pclk";
605 interrupts = <GIC_SPI 9 IRQ_TY
606 pinctrl-names = "default";
607 pinctrl-0 = <&i2c2_xfer>;
608 #address-cells = <1>;
609 #size-cells = <0>;
610 status = "disabled";
611 };
612
613 i2c3: i2c@ff1b0000 {
614 compatible = "rockchip,px30-i2
615 reg = <0x0 0xff1b0000 0x0 0x10
616 clocks = <&cru SCLK_I2C3>, <&c
617 clock-names = "i2c", "pclk";
618 interrupts = <GIC_SPI 10 IRQ_T
619 pinctrl-names = "default";
620 pinctrl-0 = <&i2c3_xfer>;
621 #address-cells = <1>;
622 #size-cells = <0>;
623 status = "disabled";
624 };
625
626 spi0: spi@ff1d0000 {
627 compatible = "rockchip,px30-sp
628 reg = <0x0 0xff1d0000 0x0 0x10
629 interrupts = <GIC_SPI 26 IRQ_T
630 clocks = <&cru SCLK_SPI0>, <&c
631 clock-names = "spiclk", "apb_p
632 dmas = <&dmac 12>, <&dmac 13>;
633 dma-names = "tx", "rx";
634 num-cs = <2>;
635 pinctrl-names = "default";
636 pinctrl-0 = <&spi0_clk &spi0_c
637 #address-cells = <1>;
638 #size-cells = <0>;
639 status = "disabled";
640 };
641
642 spi1: spi@ff1d8000 {
643 compatible = "rockchip,px30-sp
644 reg = <0x0 0xff1d8000 0x0 0x10
645 interrupts = <GIC_SPI 27 IRQ_T
646 clocks = <&cru SCLK_SPI1>, <&c
647 clock-names = "spiclk", "apb_p
648 dmas = <&dmac 14>, <&dmac 15>;
649 dma-names = "tx", "rx";
650 num-cs = <2>;
651 pinctrl-names = "default";
652 pinctrl-0 = <&spi1_clk &spi1_c
653 #address-cells = <1>;
654 #size-cells = <0>;
655 status = "disabled";
656 };
657
658 wdt: watchdog@ff1e0000 {
659 compatible = "rockchip,px30-wd
660 reg = <0x0 0xff1e0000 0x0 0x10
661 clocks = <&cru PCLK_WDT_NS>;
662 interrupts = <GIC_SPI 37 IRQ_T
663 status = "disabled";
664 };
665
666 pwm0: pwm@ff200000 {
667 compatible = "rockchip,px30-pw
668 reg = <0x0 0xff200000 0x0 0x10
669 clocks = <&cru SCLK_PWM0>, <&c
670 clock-names = "pwm", "pclk";
671 pinctrl-names = "default";
672 pinctrl-0 = <&pwm0_pin>;
673 #pwm-cells = <3>;
674 status = "disabled";
675 };
676
677 pwm1: pwm@ff200010 {
678 compatible = "rockchip,px30-pw
679 reg = <0x0 0xff200010 0x0 0x10
680 clocks = <&cru SCLK_PWM0>, <&c
681 clock-names = "pwm", "pclk";
682 pinctrl-names = "default";
683 pinctrl-0 = <&pwm1_pin>;
684 #pwm-cells = <3>;
685 status = "disabled";
686 };
687
688 pwm2: pwm@ff200020 {
689 compatible = "rockchip,px30-pw
690 reg = <0x0 0xff200020 0x0 0x10
691 clocks = <&cru SCLK_PWM0>, <&c
692 clock-names = "pwm", "pclk";
693 pinctrl-names = "default";
694 pinctrl-0 = <&pwm2_pin>;
695 #pwm-cells = <3>;
696 status = "disabled";
697 };
698
699 pwm3: pwm@ff200030 {
700 compatible = "rockchip,px30-pw
701 reg = <0x0 0xff200030 0x0 0x10
702 clocks = <&cru SCLK_PWM0>, <&c
703 clock-names = "pwm", "pclk";
704 pinctrl-names = "default";
705 pinctrl-0 = <&pwm3_pin>;
706 #pwm-cells = <3>;
707 status = "disabled";
708 };
709
710 pwm4: pwm@ff208000 {
711 compatible = "rockchip,px30-pw
712 reg = <0x0 0xff208000 0x0 0x10
713 clocks = <&cru SCLK_PWM1>, <&c
714 clock-names = "pwm", "pclk";
715 pinctrl-names = "default";
716 pinctrl-0 = <&pwm4_pin>;
717 #pwm-cells = <3>;
718 status = "disabled";
719 };
720
721 pwm5: pwm@ff208010 {
722 compatible = "rockchip,px30-pw
723 reg = <0x0 0xff208010 0x0 0x10
724 clocks = <&cru SCLK_PWM1>, <&c
725 clock-names = "pwm", "pclk";
726 pinctrl-names = "default";
727 pinctrl-0 = <&pwm5_pin>;
728 #pwm-cells = <3>;
729 status = "disabled";
730 };
731
732 pwm6: pwm@ff208020 {
733 compatible = "rockchip,px30-pw
734 reg = <0x0 0xff208020 0x0 0x10
735 clocks = <&cru SCLK_PWM1>, <&c
736 clock-names = "pwm", "pclk";
737 pinctrl-names = "default";
738 pinctrl-0 = <&pwm6_pin>;
739 #pwm-cells = <3>;
740 status = "disabled";
741 };
742
743 pwm7: pwm@ff208030 {
744 compatible = "rockchip,px30-pw
745 reg = <0x0 0xff208030 0x0 0x10
746 clocks = <&cru SCLK_PWM1>, <&c
747 clock-names = "pwm", "pclk";
748 pinctrl-names = "default";
749 pinctrl-0 = <&pwm7_pin>;
750 #pwm-cells = <3>;
751 status = "disabled";
752 };
753
754 rktimer: timer@ff210000 {
755 compatible = "rockchip,px30-ti
756 reg = <0x0 0xff210000 0x0 0x10
757 interrupts = <GIC_SPI 30 IRQ_T
758 clocks = <&cru PCLK_TIMER>, <&
759 clock-names = "pclk", "timer";
760 };
761
762 dmac: dma-controller@ff240000 {
763 compatible = "arm,pl330", "arm
764 reg = <0x0 0xff240000 0x0 0x40
765 interrupts = <GIC_SPI 1 IRQ_TY
766 <GIC_SPI 2 IRQ_TY
767 arm,pl330-periph-burst;
768 clocks = <&cru ACLK_DMAC>;
769 clock-names = "apb_pclk";
770 #dma-cells = <1>;
771 };
772
773 tsadc: tsadc@ff280000 {
774 compatible = "rockchip,px30-ts
775 reg = <0x0 0xff280000 0x0 0x10
776 interrupts = <GIC_SPI 36 IRQ_T
777 assigned-clocks = <&cru SCLK_T
778 assigned-clock-rates = <50000>
779 clocks = <&cru SCLK_TSADC>, <&
780 clock-names = "tsadc", "apb_pc
781 resets = <&cru SRST_TSADC>;
782 reset-names = "tsadc-apb";
783 rockchip,grf = <&grf>;
784 rockchip,hw-tshut-temp = <1200
785 pinctrl-names = "init", "defau
786 pinctrl-0 = <&tsadc_otp_pin>;
787 pinctrl-1 = <&tsadc_otp_out>;
788 pinctrl-2 = <&tsadc_otp_pin>;
789 #thermal-sensor-cells = <1>;
790 status = "disabled";
791 };
792
793 saradc: saradc@ff288000 {
794 compatible = "rockchip,px30-sa
795 reg = <0x0 0xff288000 0x0 0x10
796 interrupts = <GIC_SPI 84 IRQ_T
797 #io-channel-cells = <1>;
798 clocks = <&cru SCLK_SARADC>, <
799 clock-names = "saradc", "apb_p
800 resets = <&cru SRST_SARADC_P>;
801 reset-names = "saradc-apb";
802 status = "disabled";
803 };
804
805 otp: nvmem@ff290000 {
806 compatible = "rockchip,px30-ot
807 reg = <0x0 0xff290000 0x0 0x40
808 clocks = <&cru SCLK_OTP_USR>,
809 <&cru PCLK_OTP_PHY>;
810 clock-names = "otp", "apb_pclk
811 resets = <&cru SRST_OTP_PHY>;
812 reset-names = "phy";
813 #address-cells = <1>;
814 #size-cells = <1>;
815
816 /* Data cells */
817 cpu_id: id@7 {
818 reg = <0x07 0x10>;
819 };
820 cpu_leakage: cpu-leakage@17 {
821 reg = <0x17 0x1>;
822 };
823 performance: performance@1e {
824 reg = <0x1e 0x1>;
825 bits = <4 3>;
826 };
827 };
828
829 cru: clock-controller@ff2b0000 {
830 compatible = "rockchip,px30-cr
831 reg = <0x0 0xff2b0000 0x0 0x10
832 clocks = <&xin24m>, <&pmucru P
833 clock-names = "xin24m", "gpll"
834 rockchip,grf = <&grf>;
835 #clock-cells = <1>;
836 #reset-cells = <1>;
837
838 assigned-clocks = <&cru PLL_NP
839 <&cru ACLK_BUS_PRE>, <
840 <&cru HCLK_BUS_PRE>, <
841 <&cru PCLK_BUS_PRE>, <
842
843 assigned-clock-rates = <118800
844 <200000000>, <20000000
845 <150000000>, <15000000
846 <100000000>, <20000000
847 };
848
849 pmucru: clock-controller@ff2bc000 {
850 compatible = "rockchip,px30-pm
851 reg = <0x0 0xff2bc000 0x0 0x10
852 clocks = <&xin24m>;
853 clock-names = "xin24m";
854 rockchip,grf = <&grf>;
855 #clock-cells = <1>;
856 #reset-cells = <1>;
857
858 assigned-clocks =
859 <&pmucru PLL_GPLL>, <&
860 <&pmucru SCLK_WIFI_PMU
861 assigned-clock-rates =
862 <1200000000>, <1000000
863 <26000000>;
864 };
865
866 usb2phy_grf: syscon@ff2c0000 {
867 compatible = "rockchip,px30-us
868 "simple-mfd";
869 reg = <0x0 0xff2c0000 0x0 0x10
870 #address-cells = <1>;
871 #size-cells = <1>;
872
873 u2phy: usb2phy@100 {
874 compatible = "rockchip
875 reg = <0x100 0x20>;
876 clocks = <&pmucru SCLK
877 clock-names = "phyclk"
878 #clock-cells = <0>;
879 assigned-clocks = <&cr
880 assigned-clock-parents
881 clock-output-names = "
882 status = "disabled";
883
884 u2phy_host: host-port
885 #phy-cells = <
886 interrupts = <
887 interrupt-name
888 status = "disa
889 };
890
891 u2phy_otg: otg-port {
892 #phy-cells = <
893 interrupts = <
894 <
895 <
896 interrupt-name
897
898 status = "disa
899 };
900 };
901 };
902
903 dsi_dphy: phy@ff2e0000 {
904 compatible = "rockchip,px30-ds
905 reg = <0x0 0xff2e0000 0x0 0x10
906 clocks = <&pmucru SCLK_MIPIDSI
907 clock-names = "ref", "pclk";
908 resets = <&cru SRST_MIPIDSIPHY
909 reset-names = "apb";
910 #phy-cells = <0>;
911 power-domains = <&power PX30_P
912 status = "disabled";
913 };
914
915 csi_dphy: phy@ff2f0000 {
916 compatible = "rockchip,px30-cs
917 reg = <0x0 0xff2f0000 0x0 0x40
918 clocks = <&cru PCLK_MIPICSIPHY
919 clock-names = "pclk";
920 #phy-cells = <0>;
921 power-domains = <&power PX30_P
922 resets = <&cru SRST_MIPICSIPHY
923 reset-names = "apb";
924 rockchip,grf = <&grf>;
925 status = "disabled";
926 };
927
928 usb20_otg: usb@ff300000 {
929 compatible = "rockchip,px30-us
930 "snps,dwc2";
931 reg = <0x0 0xff300000 0x0 0x40
932 interrupts = <GIC_SPI 62 IRQ_T
933 clocks = <&cru HCLK_OTG>;
934 clock-names = "otg";
935 dr_mode = "otg";
936 g-np-tx-fifo-size = <16>;
937 g-rx-fifo-size = <280>;
938 g-tx-fifo-size = <256 128 128
939 phys = <&u2phy_otg>;
940 phy-names = "usb2-phy";
941 power-domains = <&power PX30_P
942 status = "disabled";
943 };
944
945 usb_host0_ehci: usb@ff340000 {
946 compatible = "generic-ehci";
947 reg = <0x0 0xff340000 0x0 0x10
948 interrupts = <GIC_SPI 60 IRQ_T
949 clocks = <&cru HCLK_HOST>;
950 phys = <&u2phy_host>;
951 phy-names = "usb";
952 power-domains = <&power PX30_P
953 status = "disabled";
954 };
955
956 usb_host0_ohci: usb@ff350000 {
957 compatible = "generic-ohci";
958 reg = <0x0 0xff350000 0x0 0x10
959 interrupts = <GIC_SPI 61 IRQ_T
960 clocks = <&cru HCLK_HOST>;
961 phys = <&u2phy_host>;
962 phy-names = "usb";
963 power-domains = <&power PX30_P
964 status = "disabled";
965 };
966
967 gmac: ethernet@ff360000 {
968 compatible = "rockchip,px30-gm
969 reg = <0x0 0xff360000 0x0 0x10
970 interrupts = <GIC_SPI 43 IRQ_T
971 interrupt-names = "macirq";
972 clocks = <&cru SCLK_GMAC>, <&c
973 <&cru SCLK_GMAC_RX_TX
974 <&cru SCLK_MAC_REFOUT
975 <&cru PCLK_GMAC>, <&c
976 clock-names = "stmmaceth", "ma
977 "mac_clk_tx", "c
978 "clk_mac_refout"
979 "pclk_mac", "clk
980 rockchip,grf = <&grf>;
981 phy-mode = "rmii";
982 pinctrl-names = "default";
983 pinctrl-0 = <&rmii_pins &mac_r
984 power-domains = <&power PX30_P
985 resets = <&cru SRST_GMAC_A>;
986 reset-names = "stmmaceth";
987 status = "disabled";
988 };
989
990 sdmmc: mmc@ff370000 {
991 compatible = "rockchip,px30-dw
992 reg = <0x0 0xff370000 0x0 0x40
993 interrupts = <GIC_SPI 54 IRQ_T
994 clocks = <&cru HCLK_SDMMC>, <&
995 <&cru SCLK_SDMMC_DRV>
996 clock-names = "biu", "ciu", "c
997 bus-width = <4>;
998 fifo-depth = <0x100>;
999 max-frequency = <150000000>;
1000 pinctrl-names = "default";
1001 pinctrl-0 = <&sdmmc_clk &sdmm
1002 power-domains = <&power PX30_
1003 status = "disabled";
1004 };
1005
1006 sdio: mmc@ff380000 {
1007 compatible = "rockchip,px30-d
1008 reg = <0x0 0xff380000 0x0 0x4
1009 interrupts = <GIC_SPI 55 IRQ_
1010 clocks = <&cru HCLK_SDIO>, <&
1011 <&cru SCLK_SDIO_DRV>
1012 clock-names = "biu", "ciu", "
1013 bus-width = <4>;
1014 fifo-depth = <0x100>;
1015 max-frequency = <150000000>;
1016 pinctrl-names = "default";
1017 pinctrl-0 = <&sdio_bus4 &sdio
1018 power-domains = <&power PX30_
1019 status = "disabled";
1020 };
1021
1022 emmc: mmc@ff390000 {
1023 compatible = "rockchip,px30-d
1024 reg = <0x0 0xff390000 0x0 0x4
1025 interrupts = <GIC_SPI 53 IRQ_
1026 clocks = <&cru HCLK_EMMC>, <&
1027 <&cru SCLK_EMMC_DRV>
1028 clock-names = "biu", "ciu", "
1029 bus-width = <8>;
1030 fifo-depth = <0x100>;
1031 max-frequency = <150000000>;
1032 pinctrl-names = "default";
1033 pinctrl-0 = <&emmc_clk &emmc_
1034 power-domains = <&power PX30_
1035 status = "disabled";
1036 };
1037
1038 sfc: spi@ff3a0000 {
1039 compatible = "rockchip,sfc";
1040 reg = <0x0 0xff3a0000 0x0 0x4
1041 interrupts = <GIC_SPI 56 IRQ_
1042 clocks = <&cru SCLK_SFC>, <&c
1043 clock-names = "clk_sfc", "hcl
1044 pinctrl-0 = <&sfc_clk &sfc_cs
1045 pinctrl-names = "default";
1046 power-domains = <&power PX30_
1047 status = "disabled";
1048 };
1049
1050 nfc: nand-controller@ff3b0000 {
1051 compatible = "rockchip,px30-n
1052 reg = <0x0 0xff3b0000 0x0 0x4
1053 interrupts = <GIC_SPI 57 IRQ_
1054 clocks = <&cru HCLK_NANDC>, <
1055 clock-names = "ahb", "nfc";
1056 assigned-clocks = <&cru SCLK_
1057 assigned-clock-rates = <15000
1058 pinctrl-names = "default";
1059 pinctrl-0 = <&flash_ale &flas
1060 &flash_rdn &flas
1061 power-domains = <&power PX30_
1062 status = "disabled";
1063 };
1064
1065 gpu_opp_table: opp-table-1 {
1066 compatible = "operating-point
1067
1068 opp-200000000 {
1069 opp-hz = /bits/ 64 <2
1070 opp-microvolt = <9500
1071 };
1072 opp-300000000 {
1073 opp-hz = /bits/ 64 <3
1074 opp-microvolt = <9750
1075 };
1076 opp-400000000 {
1077 opp-hz = /bits/ 64 <4
1078 opp-microvolt = <1050
1079 };
1080 opp-480000000 {
1081 opp-hz = /bits/ 64 <4
1082 opp-microvolt = <1125
1083 };
1084 };
1085
1086 gpu: gpu@ff400000 {
1087 compatible = "rockchip,px30-m
1088 reg = <0x0 0xff400000 0x0 0x4
1089 interrupts = <GIC_SPI 47 IRQ_
1090 <GIC_SPI 46 IRQ_
1091 <GIC_SPI 45 IRQ_
1092 interrupt-names = "job", "mmu
1093 clocks = <&cru SCLK_GPU>;
1094 #cooling-cells = <2>;
1095 power-domains = <&power PX30_
1096 operating-points-v2 = <&gpu_o
1097 status = "disabled";
1098 };
1099
1100 vpu: video-codec@ff442000 {
1101 compatible = "rockchip,px30-v
1102 reg = <0x0 0xff442000 0x0 0x8
1103 interrupts = <GIC_SPI 80 IRQ_
1104 <GIC_SPI 79 IRQ_
1105 interrupt-names = "vepu", "vd
1106 clocks = <&cru ACLK_VPU>, <&c
1107 clock-names = "aclk", "hclk";
1108 iommus = <&vpu_mmu>;
1109 power-domains = <&power PX30_
1110 };
1111
1112 vpu_mmu: iommu@ff442800 {
1113 compatible = "rockchip,iommu"
1114 reg = <0x0 0xff442800 0x0 0x1
1115 interrupts = <GIC_SPI 81 IRQ_
1116 clocks = <&cru ACLK_VPU>, <&c
1117 clock-names = "aclk", "iface"
1118 #iommu-cells = <0>;
1119 power-domains = <&power PX30_
1120 };
1121
1122 dsi: dsi@ff450000 {
1123 compatible = "rockchip,px30-m
1124 reg = <0x0 0xff450000 0x0 0x1
1125 interrupts = <GIC_SPI 75 IRQ_
1126 clocks = <&cru PCLK_MIPI_DSI>
1127 clock-names = "pclk";
1128 phys = <&dsi_dphy>;
1129 phy-names = "dphy";
1130 power-domains = <&power PX30_
1131 resets = <&cru SRST_MIPIDSI_H
1132 reset-names = "apb";
1133 rockchip,grf = <&grf>;
1134 #address-cells = <1>;
1135 #size-cells = <0>;
1136 status = "disabled";
1137
1138 ports {
1139 #address-cells = <1>;
1140 #size-cells = <0>;
1141
1142 dsi_in: port@0 {
1143 reg = <0>;
1144 #address-cell
1145 #size-cells =
1146
1147 dsi_in_vopb:
1148 reg =
1149 remot
1150 };
1151
1152 dsi_in_vopl:
1153 reg =
1154 remot
1155 };
1156 };
1157
1158 dsi_out: port@1 {
1159 reg = <1>;
1160 };
1161 };
1162 };
1163
1164 vopb: vop@ff460000 {
1165 compatible = "rockchip,px30-v
1166 reg = <0x0 0xff460000 0x0 0xe
1167 interrupts = <GIC_SPI 77 IRQ_
1168 clocks = <&cru ACLK_VOPB>, <&
1169 <&cru HCLK_VOPB>;
1170 clock-names = "aclk_vop", "dc
1171 resets = <&cru SRST_VOPB_A>,
1172 reset-names = "axi", "ahb", "
1173 iommus = <&vopb_mmu>;
1174 power-domains = <&power PX30_
1175 status = "disabled";
1176
1177 vopb_out: port {
1178 #address-cells = <1>;
1179 #size-cells = <0>;
1180
1181 vopb_out_dsi: endpoin
1182 reg = <0>;
1183 remote-endpoi
1184 };
1185
1186 vopb_out_lvds: endpoi
1187 reg = <1>;
1188 remote-endpoi
1189 };
1190 };
1191 };
1192
1193 vopb_mmu: iommu@ff460f00 {
1194 compatible = "rockchip,iommu"
1195 reg = <0x0 0xff460f00 0x0 0x1
1196 interrupts = <GIC_SPI 77 IRQ_
1197 clocks = <&cru ACLK_VOPB>, <&
1198 clock-names = "aclk", "iface"
1199 power-domains = <&power PX30_
1200 #iommu-cells = <0>;
1201 status = "disabled";
1202 };
1203
1204 vopl: vop@ff470000 {
1205 compatible = "rockchip,px30-v
1206 reg = <0x0 0xff470000 0x0 0xe
1207 interrupts = <GIC_SPI 78 IRQ_
1208 clocks = <&cru ACLK_VOPL>, <&
1209 <&cru HCLK_VOPL>;
1210 clock-names = "aclk_vop", "dc
1211 resets = <&cru SRST_VOPL_A>,
1212 reset-names = "axi", "ahb", "
1213 iommus = <&vopl_mmu>;
1214 power-domains = <&power PX30_
1215 status = "disabled";
1216
1217 vopl_out: port {
1218 #address-cells = <1>;
1219 #size-cells = <0>;
1220
1221 vopl_out_dsi: endpoin
1222 reg = <0>;
1223 remote-endpoi
1224 };
1225
1226 vopl_out_lvds: endpoi
1227 reg = <1>;
1228 remote-endpoi
1229 };
1230 };
1231 };
1232
1233 vopl_mmu: iommu@ff470f00 {
1234 compatible = "rockchip,iommu"
1235 reg = <0x0 0xff470f00 0x0 0x1
1236 interrupts = <GIC_SPI 78 IRQ_
1237 clocks = <&cru ACLK_VOPL>, <&
1238 clock-names = "aclk", "iface"
1239 power-domains = <&power PX30_
1240 #iommu-cells = <0>;
1241 status = "disabled";
1242 };
1243
1244 isp: isp@ff4a0000 {
1245 compatible = "rockchip,px30-c
1246 reg = <0x0 0xff4a0000 0x0 0x8
1247 interrupts = <GIC_SPI 70 IRQ_
1248 <GIC_SPI 73 IRQ_
1249 <GIC_SPI 74 IRQ_
1250 interrupt-names = "isp", "mi"
1251 clocks = <&cru SCLK_ISP>,
1252 <&cru ACLK_ISP>,
1253 <&cru HCLK_ISP>,
1254 <&cru PCLK_ISP>;
1255 clock-names = "isp", "aclk",
1256 iommus = <&isp_mmu>;
1257 phys = <&csi_dphy>;
1258 phy-names = "dphy";
1259 power-domains = <&power PX30_
1260 status = "disabled";
1261
1262 ports {
1263 #address-cells = <1>;
1264 #size-cells = <0>;
1265
1266 port@0 {
1267 reg = <0>;
1268 #address-cell
1269 #size-cells =
1270 };
1271 };
1272 };
1273
1274 isp_mmu: iommu@ff4a8000 {
1275 compatible = "rockchip,iommu"
1276 reg = <0x0 0xff4a8000 0x0 0x1
1277 interrupts = <GIC_SPI 70 IRQ_
1278 clocks = <&cru ACLK_ISP>, <&c
1279 clock-names = "aclk", "iface"
1280 power-domains = <&power PX30_
1281 rockchip,disable-mmu-reset;
1282 #iommu-cells = <0>;
1283 };
1284
1285 qos_gmac: qos@ff518000 {
1286 compatible = "rockchip,px30-q
1287 reg = <0x0 0xff518000 0x0 0x2
1288 };
1289
1290 qos_gpu: qos@ff520000 {
1291 compatible = "rockchip,px30-q
1292 reg = <0x0 0xff520000 0x0 0x2
1293 };
1294
1295 qos_sdmmc: qos@ff52c000 {
1296 compatible = "rockchip,px30-q
1297 reg = <0x0 0xff52c000 0x0 0x2
1298 };
1299
1300 qos_emmc: qos@ff538000 {
1301 compatible = "rockchip,px30-q
1302 reg = <0x0 0xff538000 0x0 0x2
1303 };
1304
1305 qos_nand: qos@ff538080 {
1306 compatible = "rockchip,px30-q
1307 reg = <0x0 0xff538080 0x0 0x2
1308 };
1309
1310 qos_sdio: qos@ff538100 {
1311 compatible = "rockchip,px30-q
1312 reg = <0x0 0xff538100 0x0 0x2
1313 };
1314
1315 qos_sfc: qos@ff538180 {
1316 compatible = "rockchip,px30-q
1317 reg = <0x0 0xff538180 0x0 0x2
1318 };
1319
1320 qos_usb_host: qos@ff540000 {
1321 compatible = "rockchip,px30-q
1322 reg = <0x0 0xff540000 0x0 0x2
1323 };
1324
1325 qos_usb_otg: qos@ff540080 {
1326 compatible = "rockchip,px30-q
1327 reg = <0x0 0xff540080 0x0 0x2
1328 };
1329
1330 qos_isp_128: qos@ff548000 {
1331 compatible = "rockchip,px30-q
1332 reg = <0x0 0xff548000 0x0 0x2
1333 };
1334
1335 qos_isp_rd: qos@ff548080 {
1336 compatible = "rockchip,px30-q
1337 reg = <0x0 0xff548080 0x0 0x2
1338 };
1339
1340 qos_isp_wr: qos@ff548100 {
1341 compatible = "rockchip,px30-q
1342 reg = <0x0 0xff548100 0x0 0x2
1343 };
1344
1345 qos_isp_m1: qos@ff548180 {
1346 compatible = "rockchip,px30-q
1347 reg = <0x0 0xff548180 0x0 0x2
1348 };
1349
1350 qos_vip: qos@ff548200 {
1351 compatible = "rockchip,px30-q
1352 reg = <0x0 0xff548200 0x0 0x2
1353 };
1354
1355 qos_rga_rd: qos@ff550000 {
1356 compatible = "rockchip,px30-q
1357 reg = <0x0 0xff550000 0x0 0x2
1358 };
1359
1360 qos_rga_wr: qos@ff550080 {
1361 compatible = "rockchip,px30-q
1362 reg = <0x0 0xff550080 0x0 0x2
1363 };
1364
1365 qos_vop_m0: qos@ff550100 {
1366 compatible = "rockchip,px30-q
1367 reg = <0x0 0xff550100 0x0 0x2
1368 };
1369
1370 qos_vop_m1: qos@ff550180 {
1371 compatible = "rockchip,px30-q
1372 reg = <0x0 0xff550180 0x0 0x2
1373 };
1374
1375 qos_vpu: qos@ff558000 {
1376 compatible = "rockchip,px30-q
1377 reg = <0x0 0xff558000 0x0 0x2
1378 };
1379
1380 qos_vpu_r128: qos@ff558080 {
1381 compatible = "rockchip,px30-q
1382 reg = <0x0 0xff558080 0x0 0x2
1383 };
1384
1385 pinctrl: pinctrl {
1386 compatible = "rockchip,px30-p
1387 rockchip,grf = <&grf>;
1388 rockchip,pmu = <&pmugrf>;
1389 #address-cells = <2>;
1390 #size-cells = <2>;
1391 ranges;
1392
1393 gpio0: gpio@ff040000 {
1394 compatible = "rockchi
1395 reg = <0x0 0xff040000
1396 interrupts = <GIC_SPI
1397 clocks = <&pmucru PCL
1398 gpio-controller;
1399 #gpio-cells = <2>;
1400
1401 interrupt-controller;
1402 #interrupt-cells = <2
1403 };
1404
1405 gpio1: gpio@ff250000 {
1406 compatible = "rockchi
1407 reg = <0x0 0xff250000
1408 interrupts = <GIC_SPI
1409 clocks = <&cru PCLK_G
1410 gpio-controller;
1411 #gpio-cells = <2>;
1412
1413 interrupt-controller;
1414 #interrupt-cells = <2
1415 };
1416
1417 gpio2: gpio@ff260000 {
1418 compatible = "rockchi
1419 reg = <0x0 0xff260000
1420 interrupts = <GIC_SPI
1421 clocks = <&cru PCLK_G
1422 gpio-controller;
1423 #gpio-cells = <2>;
1424
1425 interrupt-controller;
1426 #interrupt-cells = <2
1427 };
1428
1429 gpio3: gpio@ff270000 {
1430 compatible = "rockchi
1431 reg = <0x0 0xff270000
1432 interrupts = <GIC_SPI
1433 clocks = <&cru PCLK_G
1434 gpio-controller;
1435 #gpio-cells = <2>;
1436
1437 interrupt-controller;
1438 #interrupt-cells = <2
1439 };
1440
1441 pcfg_pull_up: pcfg-pull-up {
1442 bias-pull-up;
1443 };
1444
1445 pcfg_pull_down: pcfg-pull-dow
1446 bias-pull-down;
1447 };
1448
1449 pcfg_pull_none: pcfg-pull-non
1450 bias-disable;
1451 };
1452
1453 pcfg_pull_none_2ma: pcfg-pull
1454 bias-disable;
1455 drive-strength = <2>;
1456 };
1457
1458 pcfg_pull_up_2ma: pcfg-pull-u
1459 bias-pull-up;
1460 drive-strength = <2>;
1461 };
1462
1463 pcfg_pull_up_4ma: pcfg-pull-u
1464 bias-pull-up;
1465 drive-strength = <4>;
1466 };
1467
1468 pcfg_pull_none_4ma: pcfg-pull
1469 bias-disable;
1470 drive-strength = <4>;
1471 };
1472
1473 pcfg_pull_down_4ma: pcfg-pull
1474 bias-pull-down;
1475 drive-strength = <4>;
1476 };
1477
1478 pcfg_pull_none_8ma: pcfg-pull
1479 bias-disable;
1480 drive-strength = <8>;
1481 };
1482
1483 pcfg_pull_up_8ma: pcfg-pull-u
1484 bias-pull-up;
1485 drive-strength = <8>;
1486 };
1487
1488 pcfg_pull_none_12ma: pcfg-pul
1489 bias-disable;
1490 drive-strength = <12>
1491 };
1492
1493 pcfg_pull_up_12ma: pcfg-pull-
1494 bias-pull-up;
1495 drive-strength = <12>
1496 };
1497
1498 pcfg_pull_none_smt: pcfg-pull
1499 bias-disable;
1500 input-schmitt-enable;
1501 };
1502
1503 pcfg_output_high: pcfg-output
1504 output-high;
1505 };
1506
1507 pcfg_output_low: pcfg-output-
1508 output-low;
1509 };
1510
1511 pcfg_input_high: pcfg-input-h
1512 bias-pull-up;
1513 input-enable;
1514 };
1515
1516 pcfg_input: pcfg-input {
1517 input-enable;
1518 };
1519
1520 i2c0 {
1521 i2c0_xfer: i2c0-xfer
1522 rockchip,pins
1523 <0 RK
1524 <0 RK
1525 };
1526 };
1527
1528 i2c1 {
1529 i2c1_xfer: i2c1-xfer
1530 rockchip,pins
1531 <0 RK
1532 <0 RK
1533 };
1534 };
1535
1536 i2c2 {
1537 i2c2_xfer: i2c2-xfer
1538 rockchip,pins
1539 <2 RK
1540 <2 RK
1541 };
1542 };
1543
1544 i2c3 {
1545 i2c3_xfer: i2c3-xfer
1546 rockchip,pins
1547 <1 RK
1548 <1 RK
1549 };
1550 };
1551
1552 tsadc {
1553 tsadc_otp_pin: tsadc-
1554 rockchip,pins
1555 <0 RK
1556 };
1557
1558 tsadc_otp_out: tsadc-
1559 rockchip,pins
1560 <0 RK
1561 };
1562 };
1563
1564 uart0 {
1565 uart0_xfer: uart0-xfe
1566 rockchip,pins
1567 <0 RK
1568 <0 RK
1569 };
1570
1571 uart0_cts: uart0-cts
1572 rockchip,pins
1573 <0 RK
1574 };
1575
1576 uart0_rts: uart0-rts
1577 rockchip,pins
1578 <0 RK
1579 };
1580 };
1581
1582 uart1 {
1583 uart1_xfer: uart1-xfe
1584 rockchip,pins
1585 <1 RK
1586 <1 RK
1587 };
1588
1589 uart1_cts: uart1-cts
1590 rockchip,pins
1591 <1 RK
1592 };
1593
1594 uart1_rts: uart1-rts
1595 rockchip,pins
1596 <1 RK
1597 };
1598 };
1599
1600 uart2-m0 {
1601 uart2m0_xfer: uart2m0
1602 rockchip,pins
1603 <1 RK
1604 <1 RK
1605 };
1606 };
1607
1608 uart2-m1 {
1609 uart2m1_xfer: uart2m1
1610 rockchip,pins
1611 <2 RK
1612 <2 RK
1613 };
1614 };
1615
1616 uart3-m0 {
1617 uart3m0_xfer: uart3m0
1618 rockchip,pins
1619 <0 RK
1620 <0 RK
1621 };
1622
1623 uart3m0_cts: uart3m0-
1624 rockchip,pins
1625 <0 RK
1626 };
1627
1628 uart3m0_rts: uart3m0-
1629 rockchip,pins
1630 <0 RK
1631 };
1632 };
1633
1634 uart3-m1 {
1635 uart3m1_xfer: uart3m1
1636 rockchip,pins
1637 <1 RK
1638 <1 RK
1639 };
1640
1641 uart3m1_cts: uart3m1-
1642 rockchip,pins
1643 <1 RK
1644 };
1645
1646 uart3m1_rts: uart3m1-
1647 rockchip,pins
1648 <1 RK
1649 };
1650 };
1651
1652 uart4 {
1653 uart4_xfer: uart4-xfe
1654 rockchip,pins
1655 <1 RK
1656 <1 RK
1657 };
1658
1659 uart4_cts: uart4-cts
1660 rockchip,pins
1661 <1 RK
1662 };
1663
1664 uart4_rts: uart4-rts
1665 rockchip,pins
1666 <1 RK
1667 };
1668 };
1669
1670 uart5 {
1671 uart5_xfer: uart5-xfe
1672 rockchip,pins
1673 <3 RK
1674 <3 RK
1675 };
1676
1677 uart5_cts: uart5-cts
1678 rockchip,pins
1679 <3 RK
1680 };
1681
1682 uart5_rts: uart5-rts
1683 rockchip,pins
1684 <3 RK
1685 };
1686 };
1687
1688 spi0 {
1689 spi0_clk: spi0-clk {
1690 rockchip,pins
1691 <1 RK
1692 };
1693
1694 spi0_csn: spi0-csn {
1695 rockchip,pins
1696 <1 RK
1697 };
1698
1699 spi0_miso: spi0-miso
1700 rockchip,pins
1701 <1 RK
1702 };
1703
1704 spi0_mosi: spi0-mosi
1705 rockchip,pins
1706 <1 RK
1707 };
1708
1709 spi0_clk_hs: spi0-clk
1710 rockchip,pins
1711 <1 RK
1712 };
1713
1714 spi0_miso_hs: spi0-mi
1715 rockchip,pins
1716 <1 RK
1717 };
1718
1719 spi0_mosi_hs: spi0-mo
1720 rockchip,pins
1721 <1 RK
1722 };
1723 };
1724
1725 spi1 {
1726 spi1_clk: spi1-clk {
1727 rockchip,pins
1728 <3 RK
1729 };
1730
1731 spi1_csn0: spi1-csn0
1732 rockchip,pins
1733 <3 RK
1734 };
1735
1736 spi1_csn1: spi1-csn1
1737 rockchip,pins
1738 <3 RK
1739 };
1740
1741 spi1_miso: spi1-miso
1742 rockchip,pins
1743 <3 RK
1744 };
1745
1746 spi1_mosi: spi1-mosi
1747 rockchip,pins
1748 <3 RK
1749 };
1750
1751 spi1_clk_hs: spi1-clk
1752 rockchip,pins
1753 <3 RK
1754 };
1755
1756 spi1_miso_hs: spi1-mi
1757 rockchip,pins
1758 <3 RK
1759 };
1760
1761 spi1_mosi_hs: spi1-mo
1762 rockchip,pins
1763 <3 RK
1764 };
1765 };
1766
1767 pdm {
1768 pdm_clk0m0: pdm-clk0m
1769 rockchip,pins
1770 <3 RK
1771 };
1772
1773 pdm_clk0m1: pdm-clk0m
1774 rockchip,pins
1775 <2 RK
1776 };
1777
1778 pdm_clk1: pdm-clk1 {
1779 rockchip,pins
1780 <3 RK
1781 };
1782
1783 pdm_sdi0m0: pdm-sdi0m
1784 rockchip,pins
1785 <3 RK
1786 };
1787
1788 pdm_sdi0m1: pdm-sdi0m
1789 rockchip,pins
1790 <2 RK
1791 };
1792
1793 pdm_sdi1: pdm-sdi1 {
1794 rockchip,pins
1795 <3 RK
1796 };
1797
1798 pdm_sdi2: pdm-sdi2 {
1799 rockchip,pins
1800 <3 RK
1801 };
1802
1803 pdm_sdi3: pdm-sdi3 {
1804 rockchip,pins
1805 <3 RK
1806 };
1807
1808 pdm_clk0m0_sleep: pdm
1809 rockchip,pins
1810 <3 RK
1811 };
1812
1813 pdm_clk0m_sleep1: pdm
1814 rockchip,pins
1815 <2 RK
1816 };
1817
1818 pdm_clk1_sleep: pdm-c
1819 rockchip,pins
1820 <3 RK
1821 };
1822
1823 pdm_sdi0m0_sleep: pdm
1824 rockchip,pins
1825 <3 RK
1826 };
1827
1828 pdm_sdi0m1_sleep: pdm
1829 rockchip,pins
1830 <2 RK
1831 };
1832
1833 pdm_sdi1_sleep: pdm-s
1834 rockchip,pins
1835 <3 RK
1836 };
1837
1838 pdm_sdi2_sleep: pdm-s
1839 rockchip,pins
1840 <3 RK
1841 };
1842
1843 pdm_sdi3_sleep: pdm-s
1844 rockchip,pins
1845 <3 RK
1846 };
1847 };
1848
1849 i2s0 {
1850 i2s0_8ch_mclk: i2s0-8
1851 rockchip,pins
1852 <3 RK
1853 };
1854
1855 i2s0_8ch_sclktx: i2s0
1856 rockchip,pins
1857 <3 RK
1858 };
1859
1860 i2s0_8ch_sclkrx: i2s0
1861 rockchip,pins
1862 <3 RK
1863 };
1864
1865 i2s0_8ch_lrcktx: i2s0
1866 rockchip,pins
1867 <3 RK
1868 };
1869
1870 i2s0_8ch_lrckrx: i2s0
1871 rockchip,pins
1872 <3 RK
1873 };
1874
1875 i2s0_8ch_sdo0: i2s0-8
1876 rockchip,pins
1877 <3 RK
1878 };
1879
1880 i2s0_8ch_sdo1: i2s0-8
1881 rockchip,pins
1882 <3 RK
1883 };
1884
1885 i2s0_8ch_sdo2: i2s0-8
1886 rockchip,pins
1887 <3 RK
1888 };
1889
1890 i2s0_8ch_sdo3: i2s0-8
1891 rockchip,pins
1892 <3 RK
1893 };
1894
1895 i2s0_8ch_sdi0: i2s0-8
1896 rockchip,pins
1897 <3 RK
1898 };
1899
1900 i2s0_8ch_sdi1: i2s0-8
1901 rockchip,pins
1902 <3 RK
1903 };
1904
1905 i2s0_8ch_sdi2: i2s0-8
1906 rockchip,pins
1907 <3 RK
1908 };
1909
1910 i2s0_8ch_sdi3: i2s0-8
1911 rockchip,pins
1912 <3 RK
1913 };
1914 };
1915
1916 i2s1 {
1917 i2s1_2ch_mclk: i2s1-2
1918 rockchip,pins
1919 <2 RK
1920 };
1921
1922 i2s1_2ch_sclk: i2s1-2
1923 rockchip,pins
1924 <2 RK
1925 };
1926
1927 i2s1_2ch_lrck: i2s1-2
1928 rockchip,pins
1929 <2 RK
1930 };
1931
1932 i2s1_2ch_sdi: i2s1-2c
1933 rockchip,pins
1934 <2 RK
1935 };
1936
1937 i2s1_2ch_sdo: i2s1-2c
1938 rockchip,pins
1939 <2 RK
1940 };
1941 };
1942
1943 i2s2 {
1944 i2s2_2ch_mclk: i2s2-2
1945 rockchip,pins
1946 <3 RK
1947 };
1948
1949 i2s2_2ch_sclk: i2s2-2
1950 rockchip,pins
1951 <3 RK
1952 };
1953
1954 i2s2_2ch_lrck: i2s2-2
1955 rockchip,pins
1956 <3 RK
1957 };
1958
1959 i2s2_2ch_sdi: i2s2-2c
1960 rockchip,pins
1961 <3 RK
1962 };
1963
1964 i2s2_2ch_sdo: i2s2-2c
1965 rockchip,pins
1966 <3 RK
1967 };
1968 };
1969
1970 sdmmc {
1971 sdmmc_clk: sdmmc-clk
1972 rockchip,pins
1973 <1 RK
1974 };
1975
1976 sdmmc_cmd: sdmmc-cmd
1977 rockchip,pins
1978 <1 RK
1979 };
1980
1981 sdmmc_det: sdmmc-det
1982 rockchip,pins
1983 <0 RK
1984 };
1985
1986 sdmmc_bus1: sdmmc-bus
1987 rockchip,pins
1988 <1 RK
1989 };
1990
1991 sdmmc_bus4: sdmmc-bus
1992 rockchip,pins
1993 <1 RK
1994 <1 RK
1995 <1 RK
1996 <1 RK
1997 };
1998 };
1999
2000 sdio {
2001 sdio_clk: sdio-clk {
2002 rockchip,pins
2003 <1 RK
2004 };
2005
2006 sdio_cmd: sdio-cmd {
2007 rockchip,pins
2008 <1 RK
2009 };
2010
2011 sdio_bus4: sdio-bus4
2012 rockchip,pins
2013 <1 RK
2014 <1 RK
2015 <1 RK
2016 <1 RK
2017 };
2018 };
2019
2020 emmc {
2021 emmc_clk: emmc-clk {
2022 rockchip,pins
2023 <1 RK
2024 };
2025
2026 emmc_cmd: emmc-cmd {
2027 rockchip,pins
2028 <1 RK
2029 };
2030
2031 emmc_rstnout: emmc-rs
2032 rockchip,pins
2033 <1 RK
2034 };
2035
2036 emmc_bus1: emmc-bus1
2037 rockchip,pins
2038 <1 RK
2039 };
2040
2041 emmc_bus4: emmc-bus4
2042 rockchip,pins
2043 <1 RK
2044 <1 RK
2045 <1 RK
2046 <1 RK
2047 };
2048
2049 emmc_bus8: emmc-bus8
2050 rockchip,pins
2051 <1 RK
2052 <1 RK
2053 <1 RK
2054 <1 RK
2055 <1 RK
2056 <1 RK
2057 <1 RK
2058 <1 RK
2059 };
2060 };
2061
2062 flash {
2063 flash_cs0: flash-cs0
2064 rockchip,pins
2065 <1 RK
2066 };
2067
2068 flash_rdy: flash-rdy
2069 rockchip,pins
2070 <1 RK
2071 };
2072
2073 flash_dqs: flash-dqs
2074 rockchip,pins
2075 <1 RK
2076 };
2077
2078 flash_ale: flash-ale
2079 rockchip,pins
2080 <1 RK
2081 };
2082
2083 flash_cle: flash-cle
2084 rockchip,pins
2085 <1 RK
2086 };
2087
2088 flash_wrn: flash-wrn
2089 rockchip,pins
2090 <1 RK
2091 };
2092
2093 flash_csl: flash-csl
2094 rockchip,pins
2095 <1 RK
2096 };
2097
2098 flash_rdn: flash-rdn
2099 rockchip,pins
2100 <1 RK
2101 };
2102
2103 flash_bus8: flash-bus
2104 rockchip,pins
2105 <1 RK
2106 <1 RK
2107 <1 RK
2108 <1 RK
2109 <1 RK
2110 <1 RK
2111 <1 RK
2112 <1 RK
2113 };
2114 };
2115
2116 sfc {
2117 sfc_bus4: sfc-bus4 {
2118 rockchip,pins
2119 <1 RK
2120 <1 RK
2121 <1 RK
2122 <1 RK
2123 };
2124
2125 sfc_bus2: sfc-bus2 {
2126 rockchip,pins
2127 <1 RK
2128 <1 RK
2129 };
2130
2131 sfc_cs0: sfc-cs0 {
2132 rockchip,pins
2133 <1 RK
2134 };
2135
2136 sfc_clk: sfc-clk {
2137 rockchip,pins
2138 <1 RK
2139 };
2140 };
2141
2142 lcdc {
2143 lcdc_rgb_dclk_pin: lc
2144 rockchip,pins
2145 <3 RK
2146 };
2147
2148 lcdc_rgb_m0_hsync_pin
2149 rockchip,pins
2150 <3 RK
2151 };
2152
2153 lcdc_rgb_m0_vsync_pin
2154 rockchip,pins
2155 <3 RK
2156 };
2157
2158 lcdc_rgb_m0_den_pin:
2159 rockchip,pins
2160 <3 RK
2161 };
2162
2163 lcdc_rgb888_m0_data_p
2164 rockchip,pins
2165 <3 RK
2166 <3 RK
2167 <3 RK
2168 <3 RK
2169 <3 RK
2170 <3 RK
2171 <3 RK
2172 <3 RK
2173 <3 RK
2174 <3 RK
2175 <3 RK
2176 <3 RK
2177 <3 RK
2178 <3 RK
2179 <3 RK
2180 <3 RK
2181 <3 RK
2182 <3 RK
2183 <3 RK
2184 <3 RK
2185 <3 RK
2186 <3 RK
2187 <3 RK
2188 <3 RK
2189 };
2190
2191 lcdc_rgb666_m0_data_p
2192 rockchip,pins
2193 <3 RK
2194 <3 RK
2195 <3 RK
2196 <3 RK
2197 <3 RK
2198 <3 RK
2199 <3 RK
2200 <3 RK
2201 <3 RK
2202 <3 RK
2203 <3 RK
2204 <3 RK
2205 <3 RK
2206 <3 RK
2207 <3 RK
2208 <3 RK
2209 <3 RK
2210 <3 RK
2211 };
2212
2213 lcdc_rgb565_m0_data_p
2214 rockchip,pins
2215 <3 RK
2216 <3 RK
2217 <3 RK
2218 <3 RK
2219 <3 RK
2220 <3 RK
2221 <3 RK
2222 <3 RK
2223 <3 RK
2224 <3 RK
2225 <3 RK
2226 <3 RK
2227 <3 RK
2228 <3 RK
2229 <3 RK
2230 <3 RK
2231 };
2232
2233 lcdc_rgb888_m1_data_p
2234 rockchip,pins
2235 <3 RK
2236 <3 RK
2237 <3 RK
2238 <3 RK
2239 <3 RK
2240 <3 RK
2241 <3 RK
2242 <3 RK
2243 <3 RK
2244 <3 RK
2245 <3 RK
2246 <3 RK
2247 <3 RK
2248 <3 RK
2249 <3 RK
2250 <3 RK
2251 <3 RK
2252 };
2253
2254 lcdc_rgb666_m1_data_p
2255 rockchip,pins
2256 <3 RK
2257 <3 RK
2258 <3 RK
2259 <3 RK
2260 <3 RK
2261 <3 RK
2262 <3 RK
2263 <3 RK
2264 <3 RK
2265 <3 RK
2266 <3 RK
2267 };
2268
2269 lcdc_rgb565_m1_data_p
2270 rockchip,pins
2271 <3 RK
2272 <3 RK
2273 <3 RK
2274 <3 RK
2275 <3 RK
2276 <3 RK
2277 <3 RK
2278 <3 RK
2279 <3 RK
2280 };
2281 };
2282
2283 pwm0 {
2284 pwm0_pin: pwm0-pin {
2285 rockchip,pins
2286 <0 RK
2287 };
2288 };
2289
2290 pwm1 {
2291 pwm1_pin: pwm1-pin {
2292 rockchip,pins
2293 <0 RK
2294 };
2295 };
2296
2297 pwm2 {
2298 pwm2_pin: pwm2-pin {
2299 rockchip,pins
2300 <2 RK
2301 };
2302 };
2303
2304 pwm3 {
2305 pwm3_pin: pwm3-pin {
2306 rockchip,pins
2307 <0 RK
2308 };
2309 };
2310
2311 pwm4 {
2312 pwm4_pin: pwm4-pin {
2313 rockchip,pins
2314 <3 RK
2315 };
2316 };
2317
2318 pwm5 {
2319 pwm5_pin: pwm5-pin {
2320 rockchip,pins
2321 <3 RK
2322 };
2323 };
2324
2325 pwm6 {
2326 pwm6_pin: pwm6-pin {
2327 rockchip,pins
2328 <3 RK
2329 };
2330 };
2331
2332 pwm7 {
2333 pwm7_pin: pwm7-pin {
2334 rockchip,pins
2335 <3 RK
2336 };
2337 };
2338
2339 gmac {
2340 rmii_pins: rmii-pins
2341 rockchip,pins
2342 <2 RK
2343 <2 RK
2344 <2 RK
2345 <2 RK
2346 <2 RK
2347 <2 RK
2348 <2 RK
2349 <2 RK
2350 <2 RK
2351 };
2352
2353 mac_refclk_12ma: mac-
2354 rockchip,pins
2355 <2 RK
2356 };
2357
2358 mac_refclk: mac-refcl
2359 rockchip,pins
2360 <2 RK
2361 };
2362 };
2363
2364 cif-m0 {
2365 cif_clkout_m0: cif-cl
2366 rockchip,pins
2367 <2 RK
2368 };
2369
2370 dvp_d2d9_m0: dvp-d2d9
2371 rockchip,pins
2372 <2 RK
2373 <2 RK
2374 <2 RK
2375 <2 RK
2376 <2 RK
2377 <2 RK
2378 <2 RK
2379 <2 RK
2380 <2 RK
2381 <2 RK
2382 <2 RK
2383 <2 RK
2384 };
2385
2386 dvp_d0d1_m0: dvp-d0d1
2387 rockchip,pins
2388 <2 RK
2389 <2 RK
2390 };
2391
2392 dvp_d10d11_m0:d10-d11
2393 rockchip,pins
2394 <2 RK
2395 <2 RK
2396 };
2397 };
2398
2399 cif-m1 {
2400 cif_clkout_m1: cif-cl
2401 rockchip,pins
2402 <3 RK
2403 };
2404
2405 dvp_d2d9_m1: dvp-d2d9
2406 rockchip,pins
2407 <3 RK
2408 <3 RK
2409 <3 RK
2410 <3 RK
2411 <3 RK
2412 <3 RK
2413 <3 RK
2414 <3 RK
2415 <3 RK
2416 <3 RK
2417 <3 RK
2418 <3 RK
2419 };
2420
2421 dvp_d0d1_m1: dvp-d0d1
2422 rockchip,pins
2423 <3 RK
2424 <3 RK
2425 };
2426
2427 dvp_d10d11_m1:d10-d11
2428 rockchip,pins
2429 <3 RK
2430 <3 RK
2431 };
2432 };
2433
2434 isp {
2435 isp_prelight: isp-pre
2436 rockchip,pins
2437 <3 RK
2438 };
2439 };
2440 };
2441 };
Linux® is a registered trademark of Linus Torvalds in the United States and other countries.
TOMOYO® is a registered trademark of NTT DATA CORPORATION.