1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /* 2 /*
3 * Copyright (c) 2018 Fuzhou Rockchip Electron 3 * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd
4 */ 4 */
5 5
6 #include <dt-bindings/clock/px30-cru.h> 6 #include <dt-bindings/clock/px30-cru.h>
7 #include <dt-bindings/gpio/gpio.h> 7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/interrupt-controller/arm 8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/interrupt-controller/irq 9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/pinctrl/rockchip.h> 10 #include <dt-bindings/pinctrl/rockchip.h>
11 #include <dt-bindings/power/px30-power.h> 11 #include <dt-bindings/power/px30-power.h>
12 #include <dt-bindings/soc/rockchip,boot-mode.h 12 #include <dt-bindings/soc/rockchip,boot-mode.h>
13 #include <dt-bindings/thermal/thermal.h> 13 #include <dt-bindings/thermal/thermal.h>
14 14
15 / { 15 / {
16 compatible = "rockchip,px30"; 16 compatible = "rockchip,px30";
17 17
18 interrupt-parent = <&gic>; 18 interrupt-parent = <&gic>;
19 #address-cells = <2>; 19 #address-cells = <2>;
20 #size-cells = <2>; 20 #size-cells = <2>;
21 21
22 aliases { 22 aliases {
>> 23 ethernet0 = &gmac;
23 i2c0 = &i2c0; 24 i2c0 = &i2c0;
24 i2c1 = &i2c1; 25 i2c1 = &i2c1;
25 i2c2 = &i2c2; 26 i2c2 = &i2c2;
26 i2c3 = &i2c3; 27 i2c3 = &i2c3;
>> 28 mmc0 = &sdmmc;
>> 29 mmc1 = &sdio;
>> 30 mmc2 = &emmc;
27 serial0 = &uart0; 31 serial0 = &uart0;
28 serial1 = &uart1; 32 serial1 = &uart1;
29 serial2 = &uart2; 33 serial2 = &uart2;
30 serial3 = &uart3; 34 serial3 = &uart3;
31 serial4 = &uart4; 35 serial4 = &uart4;
32 serial5 = &uart5; 36 serial5 = &uart5;
33 spi0 = &spi0; 37 spi0 = &spi0;
34 spi1 = &spi1; 38 spi1 = &spi1;
35 }; 39 };
36 40
37 cpus { 41 cpus {
38 #address-cells = <2>; 42 #address-cells = <2>;
39 #size-cells = <0>; 43 #size-cells = <0>;
40 44
41 cpu0: cpu@0 { 45 cpu0: cpu@0 {
42 device_type = "cpu"; 46 device_type = "cpu";
43 compatible = "arm,cort 47 compatible = "arm,cortex-a35";
44 reg = <0x0 0x0>; 48 reg = <0x0 0x0>;
45 enable-method = "psci" 49 enable-method = "psci";
46 clocks = <&cru ARMCLK> 50 clocks = <&cru ARMCLK>;
47 #cooling-cells = <2>; 51 #cooling-cells = <2>;
48 cpu-idle-states = <&CP 52 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
49 dynamic-power-coeffici 53 dynamic-power-coefficient = <90>;
50 operating-points-v2 = 54 operating-points-v2 = <&cpu0_opp_table>;
51 }; 55 };
52 56
53 cpu1: cpu@1 { 57 cpu1: cpu@1 {
54 device_type = "cpu"; 58 device_type = "cpu";
55 compatible = "arm,cort 59 compatible = "arm,cortex-a35";
56 reg = <0x0 0x1>; 60 reg = <0x0 0x1>;
57 enable-method = "psci" 61 enable-method = "psci";
58 clocks = <&cru ARMCLK> 62 clocks = <&cru ARMCLK>;
59 #cooling-cells = <2>; 63 #cooling-cells = <2>;
60 cpu-idle-states = <&CP 64 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
61 dynamic-power-coeffici 65 dynamic-power-coefficient = <90>;
62 operating-points-v2 = 66 operating-points-v2 = <&cpu0_opp_table>;
63 }; 67 };
64 68
65 cpu2: cpu@2 { 69 cpu2: cpu@2 {
66 device_type = "cpu"; 70 device_type = "cpu";
67 compatible = "arm,cort 71 compatible = "arm,cortex-a35";
68 reg = <0x0 0x2>; 72 reg = <0x0 0x2>;
69 enable-method = "psci" 73 enable-method = "psci";
70 clocks = <&cru ARMCLK> 74 clocks = <&cru ARMCLK>;
71 #cooling-cells = <2>; 75 #cooling-cells = <2>;
72 cpu-idle-states = <&CP 76 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
73 dynamic-power-coeffici 77 dynamic-power-coefficient = <90>;
74 operating-points-v2 = 78 operating-points-v2 = <&cpu0_opp_table>;
75 }; 79 };
76 80
77 cpu3: cpu@3 { 81 cpu3: cpu@3 {
78 device_type = "cpu"; 82 device_type = "cpu";
79 compatible = "arm,cort 83 compatible = "arm,cortex-a35";
80 reg = <0x0 0x3>; 84 reg = <0x0 0x3>;
81 enable-method = "psci" 85 enable-method = "psci";
82 clocks = <&cru ARMCLK> 86 clocks = <&cru ARMCLK>;
83 #cooling-cells = <2>; 87 #cooling-cells = <2>;
84 cpu-idle-states = <&CP 88 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
85 dynamic-power-coeffici 89 dynamic-power-coefficient = <90>;
86 operating-points-v2 = 90 operating-points-v2 = <&cpu0_opp_table>;
87 }; 91 };
88 92
89 idle-states { 93 idle-states {
90 entry-method = "psci"; 94 entry-method = "psci";
91 95
92 CPU_SLEEP: cpu-sleep { 96 CPU_SLEEP: cpu-sleep {
93 compatible = " 97 compatible = "arm,idle-state";
94 local-timer-st 98 local-timer-stop;
95 arm,psci-suspe 99 arm,psci-suspend-param = <0x0010000>;
96 entry-latency- 100 entry-latency-us = <120>;
97 exit-latency-u 101 exit-latency-us = <250>;
98 min-residency- 102 min-residency-us = <900>;
99 }; 103 };
100 104
101 CLUSTER_SLEEP: cluster 105 CLUSTER_SLEEP: cluster-sleep {
102 compatible = " 106 compatible = "arm,idle-state";
103 local-timer-st 107 local-timer-stop;
104 arm,psci-suspe 108 arm,psci-suspend-param = <0x1010000>;
105 entry-latency- 109 entry-latency-us = <400>;
106 exit-latency-u 110 exit-latency-us = <500>;
107 min-residency- 111 min-residency-us = <2000>;
108 }; 112 };
109 }; 113 };
110 }; 114 };
111 115
112 cpu0_opp_table: opp-table-0 { !! 116 cpu0_opp_table: cpu0-opp-table {
113 compatible = "operating-points 117 compatible = "operating-points-v2";
114 opp-shared; 118 opp-shared;
115 119
116 opp-600000000 { 120 opp-600000000 {
117 opp-hz = /bits/ 64 <60 121 opp-hz = /bits/ 64 <600000000>;
118 opp-microvolt = <95000 122 opp-microvolt = <950000 950000 1350000>;
119 clock-latency-ns = <40 123 clock-latency-ns = <40000>;
120 opp-suspend; 124 opp-suspend;
121 }; 125 };
122 opp-816000000 { 126 opp-816000000 {
123 opp-hz = /bits/ 64 <81 127 opp-hz = /bits/ 64 <816000000>;
124 opp-microvolt = <10500 128 opp-microvolt = <1050000 1050000 1350000>;
125 clock-latency-ns = <40 129 clock-latency-ns = <40000>;
126 }; 130 };
127 opp-1008000000 { 131 opp-1008000000 {
128 opp-hz = /bits/ 64 <10 132 opp-hz = /bits/ 64 <1008000000>;
129 opp-microvolt = <11750 133 opp-microvolt = <1175000 1175000 1350000>;
130 clock-latency-ns = <40 134 clock-latency-ns = <40000>;
131 }; 135 };
132 opp-1200000000 { 136 opp-1200000000 {
133 opp-hz = /bits/ 64 <12 137 opp-hz = /bits/ 64 <1200000000>;
134 opp-microvolt = <13000 138 opp-microvolt = <1300000 1300000 1350000>;
135 clock-latency-ns = <40 139 clock-latency-ns = <40000>;
136 }; 140 };
137 opp-1296000000 { 141 opp-1296000000 {
138 opp-hz = /bits/ 64 <12 142 opp-hz = /bits/ 64 <1296000000>;
139 opp-microvolt = <13500 143 opp-microvolt = <1350000 1350000 1350000>;
140 clock-latency-ns = <40 144 clock-latency-ns = <40000>;
141 }; 145 };
142 }; 146 };
143 147
144 arm-pmu { 148 arm-pmu {
145 compatible = "arm,cortex-a35-p 149 compatible = "arm,cortex-a35-pmu";
146 interrupts = <GIC_SPI 100 IRQ_ 150 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
147 <GIC_SPI 101 IRQ_ 151 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
148 <GIC_SPI 102 IRQ_ 152 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
149 <GIC_SPI 103 IRQ_ 153 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
150 interrupt-affinity = <&cpu0>, 154 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
151 }; 155 };
152 156
153 display_subsystem: display-subsystem { 157 display_subsystem: display-subsystem {
154 compatible = "rockchip,display 158 compatible = "rockchip,display-subsystem";
155 ports = <&vopb_out>, <&vopl_ou 159 ports = <&vopb_out>, <&vopl_out>;
156 status = "disabled"; 160 status = "disabled";
157 }; 161 };
158 162
159 gmac_clkin: external-gmac-clock { 163 gmac_clkin: external-gmac-clock {
160 compatible = "fixed-clock"; 164 compatible = "fixed-clock";
161 clock-frequency = <50000000>; 165 clock-frequency = <50000000>;
162 clock-output-names = "gmac_clk 166 clock-output-names = "gmac_clkin";
163 #clock-cells = <0>; 167 #clock-cells = <0>;
164 }; 168 };
165 169
166 psci { 170 psci {
167 compatible = "arm,psci-1.0"; 171 compatible = "arm,psci-1.0";
168 method = "smc"; 172 method = "smc";
169 }; 173 };
170 174
171 timer { 175 timer {
172 compatible = "arm,armv8-timer" 176 compatible = "arm,armv8-timer";
173 interrupts = <GIC_PPI 13 (GIC_ 177 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
174 <GIC_PPI 14 (GIC_ 178 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
175 <GIC_PPI 11 (GIC_ 179 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
176 <GIC_PPI 10 (GIC_ 180 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
177 }; 181 };
178 182
179 thermal_zones: thermal-zones { 183 thermal_zones: thermal-zones {
180 soc_thermal: soc-thermal { 184 soc_thermal: soc-thermal {
181 polling-delay-passive 185 polling-delay-passive = <20>;
182 polling-delay = <1000> 186 polling-delay = <1000>;
183 sustainable-power = <7 187 sustainable-power = <750>;
184 thermal-sensors = <&ts 188 thermal-sensors = <&tsadc 0>;
185 189
186 trips { 190 trips {
187 threshold: tri 191 threshold: trip-point-0 {
188 temper 192 temperature = <70000>;
189 hyster 193 hysteresis = <2000>;
190 type = 194 type = "passive";
191 }; 195 };
192 196
193 target: trip-p 197 target: trip-point-1 {
194 temper 198 temperature = <85000>;
195 hyster 199 hysteresis = <2000>;
196 type = 200 type = "passive";
197 }; 201 };
198 202
199 soc_crit: soc- 203 soc_crit: soc-crit {
200 temper 204 temperature = <115000>;
201 hyster 205 hysteresis = <2000>;
202 type = 206 type = "critical";
203 }; 207 };
204 }; 208 };
205 209
206 cooling-maps { 210 cooling-maps {
207 map0 { 211 map0 {
208 trip = 212 trip = <&target>;
209 coolin 213 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
210 contri 214 contribution = <4096>;
211 }; 215 };
>> 216
>> 217 map1 {
>> 218 trip = <&target>;
>> 219 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
>> 220 contribution = <4096>;
>> 221 };
212 }; 222 };
213 }; 223 };
214 224
215 gpu_thermal: gpu-thermal { 225 gpu_thermal: gpu-thermal {
216 polling-delay-passive 226 polling-delay-passive = <100>; /* milliseconds */
217 polling-delay = <1000> 227 polling-delay = <1000>; /* milliseconds */
218 thermal-sensors = <&ts 228 thermal-sensors = <&tsadc 1>;
219 <<
220 trips { <<
221 gpu_threshold: <<
222 temper <<
223 hyster <<
224 type = <<
225 }; <<
226 <<
227 gpu_target: gp <<
228 temper <<
229 hyster <<
230 type = <<
231 }; <<
232 <<
233 gpu_crit: gpu- <<
234 temper <<
235 hyster <<
236 type = <<
237 }; <<
238 }; <<
239 <<
240 cooling-maps { <<
241 map0 { <<
242 trip = <<
243 coolin <<
244 }; <<
245 }; <<
246 }; 229 };
247 }; 230 };
248 231
249 xin24m: xin24m { 232 xin24m: xin24m {
250 compatible = "fixed-clock"; 233 compatible = "fixed-clock";
251 #clock-cells = <0>; 234 #clock-cells = <0>;
252 clock-frequency = <24000000>; 235 clock-frequency = <24000000>;
253 clock-output-names = "xin24m"; 236 clock-output-names = "xin24m";
254 }; 237 };
255 238
256 pmu: power-management@ff000000 { 239 pmu: power-management@ff000000 {
257 compatible = "rockchip,px30-pm 240 compatible = "rockchip,px30-pmu", "syscon", "simple-mfd";
258 reg = <0x0 0xff000000 0x0 0x10 241 reg = <0x0 0xff000000 0x0 0x1000>;
259 242
260 power: power-controller { 243 power: power-controller {
261 compatible = "rockchip 244 compatible = "rockchip,px30-power-controller";
262 #power-domain-cells = 245 #power-domain-cells = <1>;
263 #address-cells = <1>; 246 #address-cells = <1>;
264 #size-cells = <0>; 247 #size-cells = <0>;
265 248
266 /* These power domains 249 /* These power domains are grouped by VD_LOGIC */
267 power-domain@PX30_PD_U !! 250 pd_usb@PX30_PD_USB {
268 reg = <PX30_PD 251 reg = <PX30_PD_USB>;
269 clocks = <&cru 252 clocks = <&cru HCLK_HOST>,
270 <&cru 253 <&cru HCLK_OTG>,
271 <&cru 254 <&cru SCLK_OTG_ADP>;
272 pm_qos = <&qos 255 pm_qos = <&qos_usb_host>, <&qos_usb_otg>;
273 #power-domain- <<
274 }; 256 };
275 power-domain@PX30_PD_S !! 257 pd_sdcard@PX30_PD_SDCARD {
276 reg = <PX30_PD 258 reg = <PX30_PD_SDCARD>;
277 clocks = <&cru 259 clocks = <&cru HCLK_SDMMC>,
278 <&cru 260 <&cru SCLK_SDMMC>;
279 pm_qos = <&qos 261 pm_qos = <&qos_sdmmc>;
280 #power-domain- <<
281 }; 262 };
282 power-domain@PX30_PD_G !! 263 pd_gmac@PX30_PD_GMAC {
283 reg = <PX30_PD 264 reg = <PX30_PD_GMAC>;
284 clocks = <&cru 265 clocks = <&cru ACLK_GMAC>,
285 <&cru 266 <&cru PCLK_GMAC>,
286 <&cru 267 <&cru SCLK_MAC_REF>,
287 <&cru 268 <&cru SCLK_GMAC_RX_TX>;
288 pm_qos = <&qos 269 pm_qos = <&qos_gmac>;
289 #power-domain- <<
290 }; 270 };
291 power-domain@PX30_PD_M !! 271 pd_mmc_nand@PX30_PD_MMC_NAND {
292 reg = <PX30_PD 272 reg = <PX30_PD_MMC_NAND>;
293 clocks = <&cru !! 273 clocks = <&cru HCLK_NANDC>,
294 <&cru !! 274 <&cru HCLK_EMMC>,
295 <&cru !! 275 <&cru HCLK_SDIO>,
296 <&cru !! 276 <&cru HCLK_SFC>,
297 <&cru !! 277 <&cru SCLK_EMMC>,
298 <&cru !! 278 <&cru SCLK_NANDC>,
299 <&cru !! 279 <&cru SCLK_SDIO>,
300 <&cru !! 280 <&cru SCLK_SFC>;
301 pm_qos = <&qos 281 pm_qos = <&qos_emmc>, <&qos_nand>,
302 <&qos 282 <&qos_sdio>, <&qos_sfc>;
303 #power-domain- <<
304 }; 283 };
305 power-domain@PX30_PD_V !! 284 pd_vpu@PX30_PD_VPU {
306 reg = <PX30_PD 285 reg = <PX30_PD_VPU>;
307 clocks = <&cru 286 clocks = <&cru ACLK_VPU>,
308 <&cru 287 <&cru HCLK_VPU>,
309 <&cru 288 <&cru SCLK_CORE_VPU>;
310 pm_qos = <&qos 289 pm_qos = <&qos_vpu>, <&qos_vpu_r128>;
311 #power-domain- <<
312 }; 290 };
313 power-domain@PX30_PD_V !! 291 pd_vo@PX30_PD_VO {
314 reg = <PX30_PD 292 reg = <PX30_PD_VO>;
315 clocks = <&cru 293 clocks = <&cru ACLK_RGA>,
316 <&cru 294 <&cru ACLK_VOPB>,
317 <&cru 295 <&cru ACLK_VOPL>,
318 <&cru 296 <&cru DCLK_VOPB>,
319 <&cru 297 <&cru DCLK_VOPL>,
320 <&cru 298 <&cru HCLK_RGA>,
321 <&cru 299 <&cru HCLK_VOPB>,
322 <&cru 300 <&cru HCLK_VOPL>,
323 <&cru 301 <&cru PCLK_MIPI_DSI>,
324 <&cru 302 <&cru SCLK_RGA_CORE>,
325 <&cru 303 <&cru SCLK_VOPB_PWM>;
326 pm_qos = <&qos 304 pm_qos = <&qos_rga_rd>, <&qos_rga_wr>,
327 <&qos 305 <&qos_vop_m0>, <&qos_vop_m1>;
328 #power-domain- <<
329 }; 306 };
330 power-domain@PX30_PD_V !! 307 pd_vi@PX30_PD_VI {
331 reg = <PX30_PD 308 reg = <PX30_PD_VI>;
332 clocks = <&cru 309 clocks = <&cru ACLK_CIF>,
333 <&cru 310 <&cru ACLK_ISP>,
334 <&cru 311 <&cru HCLK_CIF>,
335 <&cru 312 <&cru HCLK_ISP>,
336 <&cru 313 <&cru SCLK_ISP>;
337 pm_qos = <&qos 314 pm_qos = <&qos_isp_128>, <&qos_isp_rd>,
338 <&qos 315 <&qos_isp_wr>, <&qos_isp_m1>,
339 <&qos 316 <&qos_vip>;
340 #power-domain- <<
341 }; 317 };
342 power-domain@PX30_PD_G !! 318 pd_gpu@PX30_PD_GPU {
343 reg = <PX30_PD 319 reg = <PX30_PD_GPU>;
344 clocks = <&cru 320 clocks = <&cru SCLK_GPU>;
345 pm_qos = <&qos 321 pm_qos = <&qos_gpu>;
346 #power-domain- <<
347 }; 322 };
348 }; 323 };
349 }; 324 };
350 325
351 pmugrf: syscon@ff010000 { 326 pmugrf: syscon@ff010000 {
352 compatible = "rockchip,px30-pm 327 compatible = "rockchip,px30-pmugrf", "syscon", "simple-mfd";
353 reg = <0x0 0xff010000 0x0 0x10 328 reg = <0x0 0xff010000 0x0 0x1000>;
354 #address-cells = <1>; 329 #address-cells = <1>;
355 #size-cells = <1>; 330 #size-cells = <1>;
356 331
357 pmu_io_domains: io-domains { 332 pmu_io_domains: io-domains {
358 compatible = "rockchip 333 compatible = "rockchip,px30-pmu-io-voltage-domain";
359 status = "disabled"; 334 status = "disabled";
360 }; 335 };
361 336
362 reboot-mode { 337 reboot-mode {
363 compatible = "syscon-r 338 compatible = "syscon-reboot-mode";
364 offset = <0x200>; 339 offset = <0x200>;
365 mode-bootloader = <BOO 340 mode-bootloader = <BOOT_BL_DOWNLOAD>;
366 mode-fastboot = <BOOT_ 341 mode-fastboot = <BOOT_FASTBOOT>;
367 mode-loader = <BOOT_BL 342 mode-loader = <BOOT_BL_DOWNLOAD>;
368 mode-normal = <BOOT_NO 343 mode-normal = <BOOT_NORMAL>;
369 mode-recovery = <BOOT_ 344 mode-recovery = <BOOT_RECOVERY>;
370 }; 345 };
371 }; 346 };
372 347
373 uart0: serial@ff030000 { 348 uart0: serial@ff030000 {
374 compatible = "rockchip,px30-ua 349 compatible = "rockchip,px30-uart", "snps,dw-apb-uart";
375 reg = <0x0 0xff030000 0x0 0x10 350 reg = <0x0 0xff030000 0x0 0x100>;
376 interrupts = <GIC_SPI 15 IRQ_T 351 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
377 clocks = <&pmucru SCLK_UART0_P 352 clocks = <&pmucru SCLK_UART0_PMU>, <&pmucru PCLK_UART0_PMU>;
378 clock-names = "baudclk", "apb_ 353 clock-names = "baudclk", "apb_pclk";
379 dmas = <&dmac 0>, <&dmac 1>; 354 dmas = <&dmac 0>, <&dmac 1>;
380 dma-names = "tx", "rx"; 355 dma-names = "tx", "rx";
381 reg-shift = <2>; 356 reg-shift = <2>;
382 reg-io-width = <4>; 357 reg-io-width = <4>;
383 pinctrl-names = "default"; 358 pinctrl-names = "default";
384 pinctrl-0 = <&uart0_xfer &uart 359 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
385 status = "disabled"; 360 status = "disabled";
386 }; 361 };
387 362
388 i2s0_8ch: i2s@ff060000 { <<
389 compatible = "rockchip,px30-i2 <<
390 reg = <0x0 0xff060000 0x0 0x10 <<
391 interrupts = <GIC_SPI 12 IRQ_T <<
392 clocks = <&cru SCLK_I2S0_TX>, <<
393 clock-names = "mclk_tx", "mclk <<
394 dmas = <&dmac 16>, <&dmac 17>; <<
395 dma-names = "tx", "rx"; <<
396 rockchip,grf = <&grf>; <<
397 resets = <&cru SRST_I2S0_TX>, <<
398 reset-names = "tx-m", "rx-m"; <<
399 pinctrl-names = "default"; <<
400 pinctrl-0 = <&i2s0_8ch_sclktx <<
401 &i2s0_8ch_lrcktx <<
402 &i2s0_8ch_sdo0 &i <<
403 &i2s0_8ch_sdo1 &i <<
404 &i2s0_8ch_sdo2 &i <<
405 &i2s0_8ch_sdo3 &i <<
406 #sound-dai-cells = <0>; <<
407 status = "disabled"; <<
408 }; <<
409 <<
410 i2s1_2ch: i2s@ff070000 { 363 i2s1_2ch: i2s@ff070000 {
411 compatible = "rockchip,px30-i2 364 compatible = "rockchip,px30-i2s", "rockchip,rk3066-i2s";
412 reg = <0x0 0xff070000 0x0 0x10 365 reg = <0x0 0xff070000 0x0 0x1000>;
413 interrupts = <GIC_SPI 13 IRQ_T 366 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
414 clocks = <&cru SCLK_I2S1>, <&c 367 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1>;
415 clock-names = "i2s_clk", "i2s_ 368 clock-names = "i2s_clk", "i2s_hclk";
416 dmas = <&dmac 18>, <&dmac 19>; 369 dmas = <&dmac 18>, <&dmac 19>;
417 dma-names = "tx", "rx"; 370 dma-names = "tx", "rx";
418 pinctrl-names = "default"; 371 pinctrl-names = "default";
419 pinctrl-0 = <&i2s1_2ch_sclk &i 372 pinctrl-0 = <&i2s1_2ch_sclk &i2s1_2ch_lrck
420 &i2s1_2ch_sdi &i2 373 &i2s1_2ch_sdi &i2s1_2ch_sdo>;
421 #sound-dai-cells = <0>; 374 #sound-dai-cells = <0>;
422 status = "disabled"; 375 status = "disabled";
423 }; 376 };
424 377
425 i2s2_2ch: i2s@ff080000 { 378 i2s2_2ch: i2s@ff080000 {
426 compatible = "rockchip,px30-i2 379 compatible = "rockchip,px30-i2s", "rockchip,rk3066-i2s";
427 reg = <0x0 0xff080000 0x0 0x10 380 reg = <0x0 0xff080000 0x0 0x1000>;
428 interrupts = <GIC_SPI 14 IRQ_T 381 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
429 clocks = <&cru SCLK_I2S2>, <&c 382 clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2>;
430 clock-names = "i2s_clk", "i2s_ 383 clock-names = "i2s_clk", "i2s_hclk";
431 dmas = <&dmac 20>, <&dmac 21>; 384 dmas = <&dmac 20>, <&dmac 21>;
432 dma-names = "tx", "rx"; 385 dma-names = "tx", "rx";
433 pinctrl-names = "default"; 386 pinctrl-names = "default";
434 pinctrl-0 = <&i2s2_2ch_sclk &i 387 pinctrl-0 = <&i2s2_2ch_sclk &i2s2_2ch_lrck
435 &i2s2_2ch_sdi &i2 388 &i2s2_2ch_sdi &i2s2_2ch_sdo>;
436 #sound-dai-cells = <0>; 389 #sound-dai-cells = <0>;
437 status = "disabled"; 390 status = "disabled";
438 }; 391 };
439 392
440 gic: interrupt-controller@ff131000 { 393 gic: interrupt-controller@ff131000 {
441 compatible = "arm,gic-400"; 394 compatible = "arm,gic-400";
442 #interrupt-cells = <3>; 395 #interrupt-cells = <3>;
443 #address-cells = <0>; 396 #address-cells = <0>;
444 interrupt-controller; 397 interrupt-controller;
445 reg = <0x0 0xff131000 0 0x1000 398 reg = <0x0 0xff131000 0 0x1000>,
446 <0x0 0xff132000 0 0x2000 399 <0x0 0xff132000 0 0x2000>,
447 <0x0 0xff134000 0 0x2000 400 <0x0 0xff134000 0 0x2000>,
448 <0x0 0xff136000 0 0x2000 401 <0x0 0xff136000 0 0x2000>;
449 interrupts = <GIC_PPI 9 402 interrupts = <GIC_PPI 9
450 (GIC_CPU_MASK_SIMPLE(4) 403 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
451 }; 404 };
452 405
453 grf: syscon@ff140000 { 406 grf: syscon@ff140000 {
454 compatible = "rockchip,px30-gr 407 compatible = "rockchip,px30-grf", "syscon", "simple-mfd";
455 reg = <0x0 0xff140000 0x0 0x10 408 reg = <0x0 0xff140000 0x0 0x1000>;
456 #address-cells = <1>; 409 #address-cells = <1>;
457 #size-cells = <1>; 410 #size-cells = <1>;
458 411
459 io_domains: io-domains { 412 io_domains: io-domains {
460 compatible = "rockchip 413 compatible = "rockchip,px30-io-voltage-domain";
461 status = "disabled"; 414 status = "disabled";
462 }; 415 };
463 416
464 lvds: lvds { 417 lvds: lvds {
465 compatible = "rockchip 418 compatible = "rockchip,px30-lvds";
466 phys = <&dsi_dphy>; 419 phys = <&dsi_dphy>;
467 phy-names = "dphy"; 420 phy-names = "dphy";
468 rockchip,grf = <&grf>; 421 rockchip,grf = <&grf>;
469 rockchip,output = "lvd 422 rockchip,output = "lvds";
470 status = "disabled"; 423 status = "disabled";
471 424
472 ports { 425 ports {
473 #address-cells 426 #address-cells = <1>;
474 #size-cells = 427 #size-cells = <0>;
475 428
476 lvds_in: port@ !! 429 port@0 {
477 reg = 430 reg = <0>;
478 #addre 431 #address-cells = <1>;
479 #size- 432 #size-cells = <0>;
480 433
481 lvds_v 434 lvds_vopb_in: endpoint@0 {
482 435 reg = <0>;
483 436 remote-endpoint = <&vopb_out_lvds>;
484 }; 437 };
485 438
486 lvds_v 439 lvds_vopl_in: endpoint@1 {
487 440 reg = <1>;
488 441 remote-endpoint = <&vopl_out_lvds>;
489 }; 442 };
490 }; 443 };
491 <<
492 lvds_out: port <<
493 reg = <<
494 }; <<
495 }; 444 };
496 }; 445 };
497 }; 446 };
498 447
499 uart1: serial@ff158000 { 448 uart1: serial@ff158000 {
500 compatible = "rockchip,px30-ua 449 compatible = "rockchip,px30-uart", "snps,dw-apb-uart";
501 reg = <0x0 0xff158000 0x0 0x10 450 reg = <0x0 0xff158000 0x0 0x100>;
502 interrupts = <GIC_SPI 16 IRQ_T 451 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
503 clocks = <&cru SCLK_UART1>, <& 452 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
504 clock-names = "baudclk", "apb_ 453 clock-names = "baudclk", "apb_pclk";
505 dmas = <&dmac 2>, <&dmac 3>; 454 dmas = <&dmac 2>, <&dmac 3>;
506 dma-names = "tx", "rx"; 455 dma-names = "tx", "rx";
507 reg-shift = <2>; 456 reg-shift = <2>;
508 reg-io-width = <4>; 457 reg-io-width = <4>;
509 pinctrl-names = "default"; 458 pinctrl-names = "default";
510 pinctrl-0 = <&uart1_xfer &uart 459 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
511 status = "disabled"; 460 status = "disabled";
512 }; 461 };
513 462
514 uart2: serial@ff160000 { 463 uart2: serial@ff160000 {
515 compatible = "rockchip,px30-ua 464 compatible = "rockchip,px30-uart", "snps,dw-apb-uart";
516 reg = <0x0 0xff160000 0x0 0x10 465 reg = <0x0 0xff160000 0x0 0x100>;
517 interrupts = <GIC_SPI 17 IRQ_T 466 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
518 clocks = <&cru SCLK_UART2>, <& 467 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
519 clock-names = "baudclk", "apb_ 468 clock-names = "baudclk", "apb_pclk";
520 dmas = <&dmac 4>, <&dmac 5>; 469 dmas = <&dmac 4>, <&dmac 5>;
521 dma-names = "tx", "rx"; 470 dma-names = "tx", "rx";
522 reg-shift = <2>; 471 reg-shift = <2>;
523 reg-io-width = <4>; 472 reg-io-width = <4>;
524 pinctrl-names = "default"; 473 pinctrl-names = "default";
525 pinctrl-0 = <&uart2m0_xfer>; 474 pinctrl-0 = <&uart2m0_xfer>;
526 status = "disabled"; 475 status = "disabled";
527 }; 476 };
528 477
529 uart3: serial@ff168000 { 478 uart3: serial@ff168000 {
530 compatible = "rockchip,px30-ua 479 compatible = "rockchip,px30-uart", "snps,dw-apb-uart";
531 reg = <0x0 0xff168000 0x0 0x10 480 reg = <0x0 0xff168000 0x0 0x100>;
532 interrupts = <GIC_SPI 18 IRQ_T 481 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
533 clocks = <&cru SCLK_UART3>, <& 482 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
534 clock-names = "baudclk", "apb_ 483 clock-names = "baudclk", "apb_pclk";
535 dmas = <&dmac 6>, <&dmac 7>; 484 dmas = <&dmac 6>, <&dmac 7>;
536 dma-names = "tx", "rx"; 485 dma-names = "tx", "rx";
537 reg-shift = <2>; 486 reg-shift = <2>;
538 reg-io-width = <4>; 487 reg-io-width = <4>;
539 pinctrl-names = "default"; 488 pinctrl-names = "default";
540 pinctrl-0 = <&uart3m1_xfer &ua 489 pinctrl-0 = <&uart3m1_xfer &uart3m1_cts &uart3m1_rts>;
541 status = "disabled"; 490 status = "disabled";
542 }; 491 };
543 492
544 uart4: serial@ff170000 { 493 uart4: serial@ff170000 {
545 compatible = "rockchip,px30-ua 494 compatible = "rockchip,px30-uart", "snps,dw-apb-uart";
546 reg = <0x0 0xff170000 0x0 0x10 495 reg = <0x0 0xff170000 0x0 0x100>;
547 interrupts = <GIC_SPI 19 IRQ_T 496 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
548 clocks = <&cru SCLK_UART4>, <& 497 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
549 clock-names = "baudclk", "apb_ 498 clock-names = "baudclk", "apb_pclk";
550 dmas = <&dmac 8>, <&dmac 9>; 499 dmas = <&dmac 8>, <&dmac 9>;
551 dma-names = "tx", "rx"; 500 dma-names = "tx", "rx";
552 reg-shift = <2>; 501 reg-shift = <2>;
553 reg-io-width = <4>; 502 reg-io-width = <4>;
554 pinctrl-names = "default"; 503 pinctrl-names = "default";
555 pinctrl-0 = <&uart4_xfer &uart 504 pinctrl-0 = <&uart4_xfer &uart4_cts &uart4_rts>;
556 status = "disabled"; 505 status = "disabled";
557 }; 506 };
558 507
559 uart5: serial@ff178000 { 508 uart5: serial@ff178000 {
560 compatible = "rockchip,px30-ua 509 compatible = "rockchip,px30-uart", "snps,dw-apb-uart";
561 reg = <0x0 0xff178000 0x0 0x10 510 reg = <0x0 0xff178000 0x0 0x100>;
562 interrupts = <GIC_SPI 20 IRQ_T 511 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
563 clocks = <&cru SCLK_UART5>, <& 512 clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>;
564 clock-names = "baudclk", "apb_ 513 clock-names = "baudclk", "apb_pclk";
565 dmas = <&dmac 10>, <&dmac 11>; 514 dmas = <&dmac 10>, <&dmac 11>;
566 dma-names = "tx", "rx"; 515 dma-names = "tx", "rx";
567 reg-shift = <2>; 516 reg-shift = <2>;
568 reg-io-width = <4>; 517 reg-io-width = <4>;
569 pinctrl-names = "default"; 518 pinctrl-names = "default";
570 pinctrl-0 = <&uart5_xfer &uart 519 pinctrl-0 = <&uart5_xfer &uart5_cts &uart5_rts>;
571 status = "disabled"; 520 status = "disabled";
572 }; 521 };
573 522
574 i2c0: i2c@ff180000 { 523 i2c0: i2c@ff180000 {
575 compatible = "rockchip,px30-i2 524 compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c";
576 reg = <0x0 0xff180000 0x0 0x10 525 reg = <0x0 0xff180000 0x0 0x1000>;
577 clocks = <&cru SCLK_I2C0>, <&c !! 526 clocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>;
578 clock-names = "i2c", "pclk"; 527 clock-names = "i2c", "pclk";
579 interrupts = <GIC_SPI 7 IRQ_TY 528 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
580 pinctrl-names = "default"; 529 pinctrl-names = "default";
581 pinctrl-0 = <&i2c0_xfer>; 530 pinctrl-0 = <&i2c0_xfer>;
582 #address-cells = <1>; 531 #address-cells = <1>;
583 #size-cells = <0>; 532 #size-cells = <0>;
584 status = "disabled"; 533 status = "disabled";
585 }; 534 };
586 535
587 i2c1: i2c@ff190000 { 536 i2c1: i2c@ff190000 {
588 compatible = "rockchip,px30-i2 537 compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c";
589 reg = <0x0 0xff190000 0x0 0x10 538 reg = <0x0 0xff190000 0x0 0x1000>;
590 clocks = <&cru SCLK_I2C1>, <&c 539 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
591 clock-names = "i2c", "pclk"; 540 clock-names = "i2c", "pclk";
592 interrupts = <GIC_SPI 8 IRQ_TY 541 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
593 pinctrl-names = "default"; 542 pinctrl-names = "default";
594 pinctrl-0 = <&i2c1_xfer>; 543 pinctrl-0 = <&i2c1_xfer>;
595 #address-cells = <1>; 544 #address-cells = <1>;
596 #size-cells = <0>; 545 #size-cells = <0>;
597 status = "disabled"; 546 status = "disabled";
598 }; 547 };
599 548
600 i2c2: i2c@ff1a0000 { 549 i2c2: i2c@ff1a0000 {
601 compatible = "rockchip,px30-i2 550 compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c";
602 reg = <0x0 0xff1a0000 0x0 0x10 551 reg = <0x0 0xff1a0000 0x0 0x1000>;
603 clocks = <&cru SCLK_I2C2>, <&c 552 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
604 clock-names = "i2c", "pclk"; 553 clock-names = "i2c", "pclk";
605 interrupts = <GIC_SPI 9 IRQ_TY 554 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
606 pinctrl-names = "default"; 555 pinctrl-names = "default";
607 pinctrl-0 = <&i2c2_xfer>; 556 pinctrl-0 = <&i2c2_xfer>;
608 #address-cells = <1>; 557 #address-cells = <1>;
609 #size-cells = <0>; 558 #size-cells = <0>;
610 status = "disabled"; 559 status = "disabled";
611 }; 560 };
612 561
613 i2c3: i2c@ff1b0000 { 562 i2c3: i2c@ff1b0000 {
614 compatible = "rockchip,px30-i2 563 compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c";
615 reg = <0x0 0xff1b0000 0x0 0x10 564 reg = <0x0 0xff1b0000 0x0 0x1000>;
616 clocks = <&cru SCLK_I2C3>, <&c 565 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
617 clock-names = "i2c", "pclk"; 566 clock-names = "i2c", "pclk";
618 interrupts = <GIC_SPI 10 IRQ_T 567 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
619 pinctrl-names = "default"; 568 pinctrl-names = "default";
620 pinctrl-0 = <&i2c3_xfer>; 569 pinctrl-0 = <&i2c3_xfer>;
621 #address-cells = <1>; 570 #address-cells = <1>;
622 #size-cells = <0>; 571 #size-cells = <0>;
623 status = "disabled"; 572 status = "disabled";
624 }; 573 };
625 574
626 spi0: spi@ff1d0000 { 575 spi0: spi@ff1d0000 {
627 compatible = "rockchip,px30-sp 576 compatible = "rockchip,px30-spi", "rockchip,rk3066-spi";
628 reg = <0x0 0xff1d0000 0x0 0x10 577 reg = <0x0 0xff1d0000 0x0 0x1000>;
629 interrupts = <GIC_SPI 26 IRQ_T 578 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
630 clocks = <&cru SCLK_SPI0>, <&c 579 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
631 clock-names = "spiclk", "apb_p 580 clock-names = "spiclk", "apb_pclk";
632 dmas = <&dmac 12>, <&dmac 13>; 581 dmas = <&dmac 12>, <&dmac 13>;
633 dma-names = "tx", "rx"; 582 dma-names = "tx", "rx";
634 num-cs = <2>; <<
635 pinctrl-names = "default"; 583 pinctrl-names = "default";
636 pinctrl-0 = <&spi0_clk &spi0_c 584 pinctrl-0 = <&spi0_clk &spi0_csn &spi0_miso &spi0_mosi>;
637 #address-cells = <1>; 585 #address-cells = <1>;
638 #size-cells = <0>; 586 #size-cells = <0>;
639 status = "disabled"; 587 status = "disabled";
640 }; 588 };
641 589
642 spi1: spi@ff1d8000 { 590 spi1: spi@ff1d8000 {
643 compatible = "rockchip,px30-sp 591 compatible = "rockchip,px30-spi", "rockchip,rk3066-spi";
644 reg = <0x0 0xff1d8000 0x0 0x10 592 reg = <0x0 0xff1d8000 0x0 0x1000>;
645 interrupts = <GIC_SPI 27 IRQ_T 593 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
646 clocks = <&cru SCLK_SPI1>, <&c 594 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
647 clock-names = "spiclk", "apb_p 595 clock-names = "spiclk", "apb_pclk";
648 dmas = <&dmac 14>, <&dmac 15>; 596 dmas = <&dmac 14>, <&dmac 15>;
649 dma-names = "tx", "rx"; 597 dma-names = "tx", "rx";
650 num-cs = <2>; <<
651 pinctrl-names = "default"; 598 pinctrl-names = "default";
652 pinctrl-0 = <&spi1_clk &spi1_c 599 pinctrl-0 = <&spi1_clk &spi1_csn0 &spi1_csn1 &spi1_miso &spi1_mosi>;
653 #address-cells = <1>; 600 #address-cells = <1>;
654 #size-cells = <0>; 601 #size-cells = <0>;
655 status = "disabled"; 602 status = "disabled";
656 }; 603 };
657 604
658 wdt: watchdog@ff1e0000 { 605 wdt: watchdog@ff1e0000 {
659 compatible = "rockchip,px30-wd !! 606 compatible = "snps,dw-wdt";
660 reg = <0x0 0xff1e0000 0x0 0x10 607 reg = <0x0 0xff1e0000 0x0 0x100>;
661 clocks = <&cru PCLK_WDT_NS>; 608 clocks = <&cru PCLK_WDT_NS>;
662 interrupts = <GIC_SPI 37 IRQ_T 609 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
663 status = "disabled"; 610 status = "disabled";
664 }; 611 };
665 612
666 pwm0: pwm@ff200000 { 613 pwm0: pwm@ff200000 {
667 compatible = "rockchip,px30-pw 614 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
668 reg = <0x0 0xff200000 0x0 0x10 615 reg = <0x0 0xff200000 0x0 0x10>;
669 clocks = <&cru SCLK_PWM0>, <&c 616 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
670 clock-names = "pwm", "pclk"; 617 clock-names = "pwm", "pclk";
671 pinctrl-names = "default"; 618 pinctrl-names = "default";
672 pinctrl-0 = <&pwm0_pin>; 619 pinctrl-0 = <&pwm0_pin>;
673 #pwm-cells = <3>; 620 #pwm-cells = <3>;
674 status = "disabled"; 621 status = "disabled";
675 }; 622 };
676 623
677 pwm1: pwm@ff200010 { 624 pwm1: pwm@ff200010 {
678 compatible = "rockchip,px30-pw 625 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
679 reg = <0x0 0xff200010 0x0 0x10 626 reg = <0x0 0xff200010 0x0 0x10>;
680 clocks = <&cru SCLK_PWM0>, <&c 627 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
681 clock-names = "pwm", "pclk"; 628 clock-names = "pwm", "pclk";
682 pinctrl-names = "default"; 629 pinctrl-names = "default";
683 pinctrl-0 = <&pwm1_pin>; 630 pinctrl-0 = <&pwm1_pin>;
684 #pwm-cells = <3>; 631 #pwm-cells = <3>;
685 status = "disabled"; 632 status = "disabled";
686 }; 633 };
687 634
688 pwm2: pwm@ff200020 { 635 pwm2: pwm@ff200020 {
689 compatible = "rockchip,px30-pw 636 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
690 reg = <0x0 0xff200020 0x0 0x10 637 reg = <0x0 0xff200020 0x0 0x10>;
691 clocks = <&cru SCLK_PWM0>, <&c 638 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
692 clock-names = "pwm", "pclk"; 639 clock-names = "pwm", "pclk";
693 pinctrl-names = "default"; 640 pinctrl-names = "default";
694 pinctrl-0 = <&pwm2_pin>; 641 pinctrl-0 = <&pwm2_pin>;
695 #pwm-cells = <3>; 642 #pwm-cells = <3>;
696 status = "disabled"; 643 status = "disabled";
697 }; 644 };
698 645
699 pwm3: pwm@ff200030 { 646 pwm3: pwm@ff200030 {
700 compatible = "rockchip,px30-pw 647 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
701 reg = <0x0 0xff200030 0x0 0x10 648 reg = <0x0 0xff200030 0x0 0x10>;
702 clocks = <&cru SCLK_PWM0>, <&c 649 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
703 clock-names = "pwm", "pclk"; 650 clock-names = "pwm", "pclk";
704 pinctrl-names = "default"; 651 pinctrl-names = "default";
705 pinctrl-0 = <&pwm3_pin>; 652 pinctrl-0 = <&pwm3_pin>;
706 #pwm-cells = <3>; 653 #pwm-cells = <3>;
707 status = "disabled"; 654 status = "disabled";
708 }; 655 };
709 656
710 pwm4: pwm@ff208000 { 657 pwm4: pwm@ff208000 {
711 compatible = "rockchip,px30-pw 658 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
712 reg = <0x0 0xff208000 0x0 0x10 659 reg = <0x0 0xff208000 0x0 0x10>;
713 clocks = <&cru SCLK_PWM1>, <&c 660 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>;
714 clock-names = "pwm", "pclk"; 661 clock-names = "pwm", "pclk";
715 pinctrl-names = "default"; 662 pinctrl-names = "default";
716 pinctrl-0 = <&pwm4_pin>; 663 pinctrl-0 = <&pwm4_pin>;
717 #pwm-cells = <3>; 664 #pwm-cells = <3>;
718 status = "disabled"; 665 status = "disabled";
719 }; 666 };
720 667
721 pwm5: pwm@ff208010 { 668 pwm5: pwm@ff208010 {
722 compatible = "rockchip,px30-pw 669 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
723 reg = <0x0 0xff208010 0x0 0x10 670 reg = <0x0 0xff208010 0x0 0x10>;
724 clocks = <&cru SCLK_PWM1>, <&c 671 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>;
725 clock-names = "pwm", "pclk"; 672 clock-names = "pwm", "pclk";
726 pinctrl-names = "default"; 673 pinctrl-names = "default";
727 pinctrl-0 = <&pwm5_pin>; 674 pinctrl-0 = <&pwm5_pin>;
728 #pwm-cells = <3>; 675 #pwm-cells = <3>;
729 status = "disabled"; 676 status = "disabled";
730 }; 677 };
731 678
732 pwm6: pwm@ff208020 { 679 pwm6: pwm@ff208020 {
733 compatible = "rockchip,px30-pw 680 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
734 reg = <0x0 0xff208020 0x0 0x10 681 reg = <0x0 0xff208020 0x0 0x10>;
735 clocks = <&cru SCLK_PWM1>, <&c 682 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>;
736 clock-names = "pwm", "pclk"; 683 clock-names = "pwm", "pclk";
737 pinctrl-names = "default"; 684 pinctrl-names = "default";
738 pinctrl-0 = <&pwm6_pin>; 685 pinctrl-0 = <&pwm6_pin>;
739 #pwm-cells = <3>; 686 #pwm-cells = <3>;
740 status = "disabled"; 687 status = "disabled";
741 }; 688 };
742 689
743 pwm7: pwm@ff208030 { 690 pwm7: pwm@ff208030 {
744 compatible = "rockchip,px30-pw 691 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
745 reg = <0x0 0xff208030 0x0 0x10 692 reg = <0x0 0xff208030 0x0 0x10>;
746 clocks = <&cru SCLK_PWM1>, <&c 693 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>;
747 clock-names = "pwm", "pclk"; 694 clock-names = "pwm", "pclk";
748 pinctrl-names = "default"; 695 pinctrl-names = "default";
749 pinctrl-0 = <&pwm7_pin>; 696 pinctrl-0 = <&pwm7_pin>;
750 #pwm-cells = <3>; 697 #pwm-cells = <3>;
751 status = "disabled"; 698 status = "disabled";
752 }; 699 };
753 700
754 rktimer: timer@ff210000 { 701 rktimer: timer@ff210000 {
755 compatible = "rockchip,px30-ti 702 compatible = "rockchip,px30-timer", "rockchip,rk3288-timer";
756 reg = <0x0 0xff210000 0x0 0x10 703 reg = <0x0 0xff210000 0x0 0x1000>;
757 interrupts = <GIC_SPI 30 IRQ_T 704 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
758 clocks = <&cru PCLK_TIMER>, <& 705 clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER0>;
759 clock-names = "pclk", "timer"; 706 clock-names = "pclk", "timer";
760 }; 707 };
761 708
762 dmac: dma-controller@ff240000 { !! 709 dmac: dmac@ff240000 {
763 compatible = "arm,pl330", "arm 710 compatible = "arm,pl330", "arm,primecell";
764 reg = <0x0 0xff240000 0x0 0x40 711 reg = <0x0 0xff240000 0x0 0x4000>;
765 interrupts = <GIC_SPI 1 IRQ_TY 712 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
766 <GIC_SPI 2 IRQ_TY 713 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
767 arm,pl330-periph-burst; 714 arm,pl330-periph-burst;
768 clocks = <&cru ACLK_DMAC>; 715 clocks = <&cru ACLK_DMAC>;
769 clock-names = "apb_pclk"; 716 clock-names = "apb_pclk";
770 #dma-cells = <1>; 717 #dma-cells = <1>;
771 }; 718 };
772 719
773 tsadc: tsadc@ff280000 { 720 tsadc: tsadc@ff280000 {
774 compatible = "rockchip,px30-ts 721 compatible = "rockchip,px30-tsadc";
775 reg = <0x0 0xff280000 0x0 0x10 722 reg = <0x0 0xff280000 0x0 0x100>;
776 interrupts = <GIC_SPI 36 IRQ_T 723 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
777 assigned-clocks = <&cru SCLK_T 724 assigned-clocks = <&cru SCLK_TSADC>;
778 assigned-clock-rates = <50000> 725 assigned-clock-rates = <50000>;
779 clocks = <&cru SCLK_TSADC>, <& 726 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
780 clock-names = "tsadc", "apb_pc 727 clock-names = "tsadc", "apb_pclk";
781 resets = <&cru SRST_TSADC>; 728 resets = <&cru SRST_TSADC>;
782 reset-names = "tsadc-apb"; 729 reset-names = "tsadc-apb";
783 rockchip,grf = <&grf>; 730 rockchip,grf = <&grf>;
784 rockchip,hw-tshut-temp = <1200 731 rockchip,hw-tshut-temp = <120000>;
785 pinctrl-names = "init", "defau 732 pinctrl-names = "init", "default", "sleep";
786 pinctrl-0 = <&tsadc_otp_pin>; 733 pinctrl-0 = <&tsadc_otp_pin>;
787 pinctrl-1 = <&tsadc_otp_out>; 734 pinctrl-1 = <&tsadc_otp_out>;
788 pinctrl-2 = <&tsadc_otp_pin>; 735 pinctrl-2 = <&tsadc_otp_pin>;
789 #thermal-sensor-cells = <1>; 736 #thermal-sensor-cells = <1>;
790 status = "disabled"; 737 status = "disabled";
791 }; 738 };
792 739
793 saradc: saradc@ff288000 { 740 saradc: saradc@ff288000 {
794 compatible = "rockchip,px30-sa 741 compatible = "rockchip,px30-saradc", "rockchip,rk3399-saradc";
795 reg = <0x0 0xff288000 0x0 0x10 742 reg = <0x0 0xff288000 0x0 0x100>;
796 interrupts = <GIC_SPI 84 IRQ_T 743 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
797 #io-channel-cells = <1>; 744 #io-channel-cells = <1>;
798 clocks = <&cru SCLK_SARADC>, < 745 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
799 clock-names = "saradc", "apb_p 746 clock-names = "saradc", "apb_pclk";
800 resets = <&cru SRST_SARADC_P>; 747 resets = <&cru SRST_SARADC_P>;
801 reset-names = "saradc-apb"; 748 reset-names = "saradc-apb";
802 status = "disabled"; 749 status = "disabled";
803 }; 750 };
804 751
805 otp: nvmem@ff290000 { 752 otp: nvmem@ff290000 {
806 compatible = "rockchip,px30-ot 753 compatible = "rockchip,px30-otp";
807 reg = <0x0 0xff290000 0x0 0x40 754 reg = <0x0 0xff290000 0x0 0x4000>;
808 clocks = <&cru SCLK_OTP_USR>, 755 clocks = <&cru SCLK_OTP_USR>, <&cru PCLK_OTP_NS>,
809 <&cru PCLK_OTP_PHY>; 756 <&cru PCLK_OTP_PHY>;
810 clock-names = "otp", "apb_pclk 757 clock-names = "otp", "apb_pclk", "phy";
811 resets = <&cru SRST_OTP_PHY>; 758 resets = <&cru SRST_OTP_PHY>;
812 reset-names = "phy"; 759 reset-names = "phy";
813 #address-cells = <1>; 760 #address-cells = <1>;
814 #size-cells = <1>; 761 #size-cells = <1>;
815 762
816 /* Data cells */ 763 /* Data cells */
817 cpu_id: id@7 { 764 cpu_id: id@7 {
818 reg = <0x07 0x10>; 765 reg = <0x07 0x10>;
819 }; 766 };
820 cpu_leakage: cpu-leakage@17 { 767 cpu_leakage: cpu-leakage@17 {
821 reg = <0x17 0x1>; 768 reg = <0x17 0x1>;
822 }; 769 };
823 performance: performance@1e { 770 performance: performance@1e {
824 reg = <0x1e 0x1>; 771 reg = <0x1e 0x1>;
825 bits = <4 3>; 772 bits = <4 3>;
826 }; 773 };
827 }; 774 };
828 775
829 cru: clock-controller@ff2b0000 { 776 cru: clock-controller@ff2b0000 {
830 compatible = "rockchip,px30-cr 777 compatible = "rockchip,px30-cru";
831 reg = <0x0 0xff2b0000 0x0 0x10 778 reg = <0x0 0xff2b0000 0x0 0x1000>;
832 clocks = <&xin24m>, <&pmucru P 779 clocks = <&xin24m>, <&pmucru PLL_GPLL>;
833 clock-names = "xin24m", "gpll" 780 clock-names = "xin24m", "gpll";
834 rockchip,grf = <&grf>; 781 rockchip,grf = <&grf>;
835 #clock-cells = <1>; 782 #clock-cells = <1>;
836 #reset-cells = <1>; 783 #reset-cells = <1>;
837 784
838 assigned-clocks = <&cru PLL_NP 785 assigned-clocks = <&cru PLL_NPLL>,
839 <&cru ACLK_BUS_PRE>, < 786 <&cru ACLK_BUS_PRE>, <&cru ACLK_PERI_PRE>,
840 <&cru HCLK_BUS_PRE>, < 787 <&cru HCLK_BUS_PRE>, <&cru HCLK_PERI_PRE>,
841 <&cru PCLK_BUS_PRE>, < 788 <&cru PCLK_BUS_PRE>, <&cru SCLK_GPU>;
842 789
843 assigned-clock-rates = <118800 790 assigned-clock-rates = <1188000000>,
844 <200000000>, <20000000 791 <200000000>, <200000000>,
845 <150000000>, <15000000 792 <150000000>, <150000000>,
846 <100000000>, <20000000 793 <100000000>, <200000000>;
847 }; 794 };
848 795
849 pmucru: clock-controller@ff2bc000 { 796 pmucru: clock-controller@ff2bc000 {
850 compatible = "rockchip,px30-pm 797 compatible = "rockchip,px30-pmucru";
851 reg = <0x0 0xff2bc000 0x0 0x10 798 reg = <0x0 0xff2bc000 0x0 0x1000>;
852 clocks = <&xin24m>; 799 clocks = <&xin24m>;
853 clock-names = "xin24m"; 800 clock-names = "xin24m";
854 rockchip,grf = <&grf>; 801 rockchip,grf = <&grf>;
855 #clock-cells = <1>; 802 #clock-cells = <1>;
856 #reset-cells = <1>; 803 #reset-cells = <1>;
857 804
858 assigned-clocks = 805 assigned-clocks =
859 <&pmucru PLL_GPLL>, <& 806 <&pmucru PLL_GPLL>, <&pmucru PCLK_PMU_PRE>,
860 <&pmucru SCLK_WIFI_PMU 807 <&pmucru SCLK_WIFI_PMU>;
861 assigned-clock-rates = 808 assigned-clock-rates =
862 <1200000000>, <1000000 809 <1200000000>, <100000000>,
863 <26000000>; 810 <26000000>;
864 }; 811 };
865 812
866 usb2phy_grf: syscon@ff2c0000 { 813 usb2phy_grf: syscon@ff2c0000 {
867 compatible = "rockchip,px30-us 814 compatible = "rockchip,px30-usb2phy-grf", "syscon",
868 "simple-mfd"; 815 "simple-mfd";
869 reg = <0x0 0xff2c0000 0x0 0x10 816 reg = <0x0 0xff2c0000 0x0 0x10000>;
870 #address-cells = <1>; 817 #address-cells = <1>;
871 #size-cells = <1>; 818 #size-cells = <1>;
872 819
873 u2phy: usb2phy@100 { !! 820 u2phy: usb2-phy@100 {
874 compatible = "rockchip 821 compatible = "rockchip,px30-usb2phy";
875 reg = <0x100 0x20>; 822 reg = <0x100 0x20>;
876 clocks = <&pmucru SCLK 823 clocks = <&pmucru SCLK_USBPHY_REF>;
877 clock-names = "phyclk" 824 clock-names = "phyclk";
878 #clock-cells = <0>; 825 #clock-cells = <0>;
879 assigned-clocks = <&cr 826 assigned-clocks = <&cru USB480M>;
880 assigned-clock-parents 827 assigned-clock-parents = <&u2phy>;
881 clock-output-names = " 828 clock-output-names = "usb480m_phy";
882 status = "disabled"; 829 status = "disabled";
883 830
884 u2phy_host: host-port 831 u2phy_host: host-port {
885 #phy-cells = < 832 #phy-cells = <0>;
886 interrupts = < 833 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
887 interrupt-name 834 interrupt-names = "linestate";
888 status = "disa 835 status = "disabled";
889 }; 836 };
890 837
891 u2phy_otg: otg-port { 838 u2phy_otg: otg-port {
892 #phy-cells = < 839 #phy-cells = <0>;
893 interrupts = < 840 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
894 < 841 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
895 < 842 <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
896 interrupt-name 843 interrupt-names = "otg-bvalid", "otg-id",
897 844 "linestate";
898 status = "disa 845 status = "disabled";
899 }; 846 };
900 }; 847 };
901 }; 848 };
902 849
903 dsi_dphy: phy@ff2e0000 { 850 dsi_dphy: phy@ff2e0000 {
904 compatible = "rockchip,px30-ds 851 compatible = "rockchip,px30-dsi-dphy";
905 reg = <0x0 0xff2e0000 0x0 0x10 852 reg = <0x0 0xff2e0000 0x0 0x10000>;
906 clocks = <&pmucru SCLK_MIPIDSI 853 clocks = <&pmucru SCLK_MIPIDSIPHY_REF>, <&cru PCLK_MIPIDSIPHY>;
907 clock-names = "ref", "pclk"; 854 clock-names = "ref", "pclk";
908 resets = <&cru SRST_MIPIDSIPHY 855 resets = <&cru SRST_MIPIDSIPHY_P>;
909 reset-names = "apb"; 856 reset-names = "apb";
910 #phy-cells = <0>; 857 #phy-cells = <0>;
911 power-domains = <&power PX30_P 858 power-domains = <&power PX30_PD_VO>;
912 status = "disabled"; 859 status = "disabled";
913 }; 860 };
914 861
915 csi_dphy: phy@ff2f0000 { <<
916 compatible = "rockchip,px30-cs <<
917 reg = <0x0 0xff2f0000 0x0 0x40 <<
918 clocks = <&cru PCLK_MIPICSIPHY <<
919 clock-names = "pclk"; <<
920 #phy-cells = <0>; <<
921 power-domains = <&power PX30_P <<
922 resets = <&cru SRST_MIPICSIPHY <<
923 reset-names = "apb"; <<
924 rockchip,grf = <&grf>; <<
925 status = "disabled"; <<
926 }; <<
927 <<
928 usb20_otg: usb@ff300000 { 862 usb20_otg: usb@ff300000 {
929 compatible = "rockchip,px30-us 863 compatible = "rockchip,px30-usb", "rockchip,rk3066-usb",
930 "snps,dwc2"; 864 "snps,dwc2";
931 reg = <0x0 0xff300000 0x0 0x40 865 reg = <0x0 0xff300000 0x0 0x40000>;
932 interrupts = <GIC_SPI 62 IRQ_T 866 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
933 clocks = <&cru HCLK_OTG>; 867 clocks = <&cru HCLK_OTG>;
934 clock-names = "otg"; 868 clock-names = "otg";
935 dr_mode = "otg"; 869 dr_mode = "otg";
936 g-np-tx-fifo-size = <16>; 870 g-np-tx-fifo-size = <16>;
937 g-rx-fifo-size = <280>; 871 g-rx-fifo-size = <280>;
938 g-tx-fifo-size = <256 128 128 872 g-tx-fifo-size = <256 128 128 64 32 16>;
939 phys = <&u2phy_otg>; 873 phys = <&u2phy_otg>;
940 phy-names = "usb2-phy"; 874 phy-names = "usb2-phy";
941 power-domains = <&power PX30_P 875 power-domains = <&power PX30_PD_USB>;
942 status = "disabled"; 876 status = "disabled";
943 }; 877 };
944 878
945 usb_host0_ehci: usb@ff340000 { 879 usb_host0_ehci: usb@ff340000 {
946 compatible = "generic-ehci"; 880 compatible = "generic-ehci";
947 reg = <0x0 0xff340000 0x0 0x10 881 reg = <0x0 0xff340000 0x0 0x10000>;
948 interrupts = <GIC_SPI 60 IRQ_T 882 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
949 clocks = <&cru HCLK_HOST>; 883 clocks = <&cru HCLK_HOST>;
950 phys = <&u2phy_host>; 884 phys = <&u2phy_host>;
951 phy-names = "usb"; 885 phy-names = "usb";
952 power-domains = <&power PX30_P 886 power-domains = <&power PX30_PD_USB>;
953 status = "disabled"; 887 status = "disabled";
954 }; 888 };
955 889
956 usb_host0_ohci: usb@ff350000 { 890 usb_host0_ohci: usb@ff350000 {
957 compatible = "generic-ohci"; 891 compatible = "generic-ohci";
958 reg = <0x0 0xff350000 0x0 0x10 892 reg = <0x0 0xff350000 0x0 0x10000>;
959 interrupts = <GIC_SPI 61 IRQ_T 893 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
960 clocks = <&cru HCLK_HOST>; 894 clocks = <&cru HCLK_HOST>;
961 phys = <&u2phy_host>; 895 phys = <&u2phy_host>;
962 phy-names = "usb"; 896 phy-names = "usb";
963 power-domains = <&power PX30_P 897 power-domains = <&power PX30_PD_USB>;
964 status = "disabled"; 898 status = "disabled";
965 }; 899 };
966 900
967 gmac: ethernet@ff360000 { 901 gmac: ethernet@ff360000 {
968 compatible = "rockchip,px30-gm 902 compatible = "rockchip,px30-gmac";
969 reg = <0x0 0xff360000 0x0 0x10 903 reg = <0x0 0xff360000 0x0 0x10000>;
970 interrupts = <GIC_SPI 43 IRQ_T 904 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
971 interrupt-names = "macirq"; 905 interrupt-names = "macirq";
972 clocks = <&cru SCLK_GMAC>, <&c 906 clocks = <&cru SCLK_GMAC>, <&cru SCLK_GMAC_RX_TX>,
973 <&cru SCLK_GMAC_RX_TX 907 <&cru SCLK_GMAC_RX_TX>, <&cru SCLK_MAC_REF>,
974 <&cru SCLK_MAC_REFOUT 908 <&cru SCLK_MAC_REFOUT>, <&cru ACLK_GMAC>,
975 <&cru PCLK_GMAC>, <&c 909 <&cru PCLK_GMAC>, <&cru SCLK_GMAC_RMII>;
976 clock-names = "stmmaceth", "ma 910 clock-names = "stmmaceth", "mac_clk_rx",
977 "mac_clk_tx", "c 911 "mac_clk_tx", "clk_mac_ref",
978 "clk_mac_refout" 912 "clk_mac_refout", "aclk_mac",
979 "pclk_mac", "clk 913 "pclk_mac", "clk_mac_speed";
980 rockchip,grf = <&grf>; 914 rockchip,grf = <&grf>;
981 phy-mode = "rmii"; 915 phy-mode = "rmii";
982 pinctrl-names = "default"; 916 pinctrl-names = "default";
983 pinctrl-0 = <&rmii_pins &mac_r 917 pinctrl-0 = <&rmii_pins &mac_refclk_12ma>;
984 power-domains = <&power PX30_P 918 power-domains = <&power PX30_PD_GMAC>;
985 resets = <&cru SRST_GMAC_A>; 919 resets = <&cru SRST_GMAC_A>;
986 reset-names = "stmmaceth"; 920 reset-names = "stmmaceth";
987 status = "disabled"; 921 status = "disabled";
988 }; 922 };
989 923
990 sdmmc: mmc@ff370000 { 924 sdmmc: mmc@ff370000 {
991 compatible = "rockchip,px30-dw 925 compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc";
992 reg = <0x0 0xff370000 0x0 0x40 926 reg = <0x0 0xff370000 0x0 0x4000>;
993 interrupts = <GIC_SPI 54 IRQ_T 927 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
994 clocks = <&cru HCLK_SDMMC>, <& 928 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
995 <&cru SCLK_SDMMC_DRV> 929 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
996 clock-names = "biu", "ciu", "c 930 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
997 bus-width = <4>; 931 bus-width = <4>;
998 fifo-depth = <0x100>; 932 fifo-depth = <0x100>;
999 max-frequency = <150000000>; 933 max-frequency = <150000000>;
1000 pinctrl-names = "default"; 934 pinctrl-names = "default";
1001 pinctrl-0 = <&sdmmc_clk &sdmm 935 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_det &sdmmc_bus4>;
1002 power-domains = <&power PX30_ 936 power-domains = <&power PX30_PD_SDCARD>;
1003 status = "disabled"; 937 status = "disabled";
1004 }; 938 };
1005 939
1006 sdio: mmc@ff380000 { 940 sdio: mmc@ff380000 {
1007 compatible = "rockchip,px30-d 941 compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc";
1008 reg = <0x0 0xff380000 0x0 0x4 942 reg = <0x0 0xff380000 0x0 0x4000>;
1009 interrupts = <GIC_SPI 55 IRQ_ 943 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
1010 clocks = <&cru HCLK_SDIO>, <& 944 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
1011 <&cru SCLK_SDIO_DRV> 945 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
1012 clock-names = "biu", "ciu", " 946 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
1013 bus-width = <4>; 947 bus-width = <4>;
1014 fifo-depth = <0x100>; 948 fifo-depth = <0x100>;
1015 max-frequency = <150000000>; 949 max-frequency = <150000000>;
1016 pinctrl-names = "default"; 950 pinctrl-names = "default";
1017 pinctrl-0 = <&sdio_bus4 &sdio 951 pinctrl-0 = <&sdio_bus4 &sdio_cmd &sdio_clk>;
1018 power-domains = <&power PX30_ 952 power-domains = <&power PX30_PD_MMC_NAND>;
1019 status = "disabled"; 953 status = "disabled";
1020 }; 954 };
1021 955
1022 emmc: mmc@ff390000 { 956 emmc: mmc@ff390000 {
1023 compatible = "rockchip,px30-d 957 compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc";
1024 reg = <0x0 0xff390000 0x0 0x4 958 reg = <0x0 0xff390000 0x0 0x4000>;
1025 interrupts = <GIC_SPI 53 IRQ_ 959 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
1026 clocks = <&cru HCLK_EMMC>, <& 960 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
1027 <&cru SCLK_EMMC_DRV> 961 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
1028 clock-names = "biu", "ciu", " 962 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
1029 bus-width = <8>; 963 bus-width = <8>;
1030 fifo-depth = <0x100>; 964 fifo-depth = <0x100>;
1031 max-frequency = <150000000>; 965 max-frequency = <150000000>;
1032 pinctrl-names = "default"; 966 pinctrl-names = "default";
1033 pinctrl-0 = <&emmc_clk &emmc_ 967 pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
1034 power-domains = <&power PX30_ 968 power-domains = <&power PX30_PD_MMC_NAND>;
1035 status = "disabled"; 969 status = "disabled";
1036 }; 970 };
1037 971
1038 sfc: spi@ff3a0000 { <<
1039 compatible = "rockchip,sfc"; <<
1040 reg = <0x0 0xff3a0000 0x0 0x4 <<
1041 interrupts = <GIC_SPI 56 IRQ_ <<
1042 clocks = <&cru SCLK_SFC>, <&c <<
1043 clock-names = "clk_sfc", "hcl <<
1044 pinctrl-0 = <&sfc_clk &sfc_cs <<
1045 pinctrl-names = "default"; <<
1046 power-domains = <&power PX30_ <<
1047 status = "disabled"; <<
1048 }; <<
1049 <<
1050 nfc: nand-controller@ff3b0000 { 972 nfc: nand-controller@ff3b0000 {
1051 compatible = "rockchip,px30-n 973 compatible = "rockchip,px30-nfc";
1052 reg = <0x0 0xff3b0000 0x0 0x4 974 reg = <0x0 0xff3b0000 0x0 0x4000>;
1053 interrupts = <GIC_SPI 57 IRQ_ 975 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
1054 clocks = <&cru HCLK_NANDC>, < 976 clocks = <&cru HCLK_NANDC>, <&cru SCLK_NANDC>;
1055 clock-names = "ahb", "nfc"; 977 clock-names = "ahb", "nfc";
1056 assigned-clocks = <&cru SCLK_ 978 assigned-clocks = <&cru SCLK_NANDC>;
1057 assigned-clock-rates = <15000 979 assigned-clock-rates = <150000000>;
1058 pinctrl-names = "default"; 980 pinctrl-names = "default";
1059 pinctrl-0 = <&flash_ale &flas 981 pinctrl-0 = <&flash_ale &flash_bus8 &flash_cle &flash_cs0
1060 &flash_rdn &flas 982 &flash_rdn &flash_rdy &flash_wrn &flash_dqs>;
1061 power-domains = <&power PX30_ 983 power-domains = <&power PX30_PD_MMC_NAND>;
1062 status = "disabled"; 984 status = "disabled";
1063 }; 985 };
1064 986
1065 gpu_opp_table: opp-table-1 { <<
1066 compatible = "operating-point <<
1067 <<
1068 opp-200000000 { <<
1069 opp-hz = /bits/ 64 <2 <<
1070 opp-microvolt = <9500 <<
1071 }; <<
1072 opp-300000000 { <<
1073 opp-hz = /bits/ 64 <3 <<
1074 opp-microvolt = <9750 <<
1075 }; <<
1076 opp-400000000 { <<
1077 opp-hz = /bits/ 64 <4 <<
1078 opp-microvolt = <1050 <<
1079 }; <<
1080 opp-480000000 { <<
1081 opp-hz = /bits/ 64 <4 <<
1082 opp-microvolt = <1125 <<
1083 }; <<
1084 }; <<
1085 <<
1086 gpu: gpu@ff400000 { 987 gpu: gpu@ff400000 {
1087 compatible = "rockchip,px30-m 988 compatible = "rockchip,px30-mali", "arm,mali-bifrost";
1088 reg = <0x0 0xff400000 0x0 0x4 989 reg = <0x0 0xff400000 0x0 0x4000>;
1089 interrupts = <GIC_SPI 47 IRQ_ 990 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
1090 <GIC_SPI 46 IRQ_ 991 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
1091 <GIC_SPI 45 IRQ_ 992 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
1092 interrupt-names = "job", "mmu 993 interrupt-names = "job", "mmu", "gpu";
1093 clocks = <&cru SCLK_GPU>; 994 clocks = <&cru SCLK_GPU>;
1094 #cooling-cells = <2>; 995 #cooling-cells = <2>;
1095 power-domains = <&power PX30_ 996 power-domains = <&power PX30_PD_GPU>;
1096 operating-points-v2 = <&gpu_o <<
1097 status = "disabled"; 997 status = "disabled";
1098 }; 998 };
1099 999
1100 vpu: video-codec@ff442000 { <<
1101 compatible = "rockchip,px30-v <<
1102 reg = <0x0 0xff442000 0x0 0x8 <<
1103 interrupts = <GIC_SPI 80 IRQ_ <<
1104 <GIC_SPI 79 IRQ_ <<
1105 interrupt-names = "vepu", "vd <<
1106 clocks = <&cru ACLK_VPU>, <&c <<
1107 clock-names = "aclk", "hclk"; <<
1108 iommus = <&vpu_mmu>; <<
1109 power-domains = <&power PX30_ <<
1110 }; <<
1111 <<
1112 vpu_mmu: iommu@ff442800 { <<
1113 compatible = "rockchip,iommu" <<
1114 reg = <0x0 0xff442800 0x0 0x1 <<
1115 interrupts = <GIC_SPI 81 IRQ_ <<
1116 clocks = <&cru ACLK_VPU>, <&c <<
1117 clock-names = "aclk", "iface" <<
1118 #iommu-cells = <0>; <<
1119 power-domains = <&power PX30_ <<
1120 }; <<
1121 <<
1122 dsi: dsi@ff450000 { 1000 dsi: dsi@ff450000 {
1123 compatible = "rockchip,px30-m !! 1001 compatible = "rockchip,px30-mipi-dsi";
1124 reg = <0x0 0xff450000 0x0 0x1 1002 reg = <0x0 0xff450000 0x0 0x10000>;
1125 interrupts = <GIC_SPI 75 IRQ_ 1003 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
1126 clocks = <&cru PCLK_MIPI_DSI> 1004 clocks = <&cru PCLK_MIPI_DSI>;
1127 clock-names = "pclk"; 1005 clock-names = "pclk";
1128 phys = <&dsi_dphy>; 1006 phys = <&dsi_dphy>;
1129 phy-names = "dphy"; 1007 phy-names = "dphy";
1130 power-domains = <&power PX30_ 1008 power-domains = <&power PX30_PD_VO>;
1131 resets = <&cru SRST_MIPIDSI_H 1009 resets = <&cru SRST_MIPIDSI_HOST_P>;
1132 reset-names = "apb"; 1010 reset-names = "apb";
1133 rockchip,grf = <&grf>; 1011 rockchip,grf = <&grf>;
1134 #address-cells = <1>; 1012 #address-cells = <1>;
1135 #size-cells = <0>; 1013 #size-cells = <0>;
1136 status = "disabled"; 1014 status = "disabled";
1137 1015
1138 ports { 1016 ports {
1139 #address-cells = <1>; 1017 #address-cells = <1>;
1140 #size-cells = <0>; 1018 #size-cells = <0>;
1141 1019
1142 dsi_in: port@0 { !! 1020 port@0 {
1143 reg = <0>; 1021 reg = <0>;
1144 #address-cell 1022 #address-cells = <1>;
1145 #size-cells = 1023 #size-cells = <0>;
1146 1024
1147 dsi_in_vopb: 1025 dsi_in_vopb: endpoint@0 {
1148 reg = 1026 reg = <0>;
1149 remot 1027 remote-endpoint = <&vopb_out_dsi>;
1150 }; 1028 };
1151 1029
1152 dsi_in_vopl: 1030 dsi_in_vopl: endpoint@1 {
1153 reg = 1031 reg = <1>;
1154 remot 1032 remote-endpoint = <&vopl_out_dsi>;
1155 }; 1033 };
1156 }; 1034 };
1157 <<
1158 dsi_out: port@1 { <<
1159 reg = <1>; <<
1160 }; <<
1161 }; 1035 };
1162 }; 1036 };
1163 1037
1164 vopb: vop@ff460000 { 1038 vopb: vop@ff460000 {
1165 compatible = "rockchip,px30-v 1039 compatible = "rockchip,px30-vop-big";
1166 reg = <0x0 0xff460000 0x0 0xe 1040 reg = <0x0 0xff460000 0x0 0xefc>;
1167 interrupts = <GIC_SPI 77 IRQ_ 1041 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
1168 clocks = <&cru ACLK_VOPB>, <& 1042 clocks = <&cru ACLK_VOPB>, <&cru DCLK_VOPB>,
1169 <&cru HCLK_VOPB>; 1043 <&cru HCLK_VOPB>;
1170 clock-names = "aclk_vop", "dc 1044 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1171 resets = <&cru SRST_VOPB_A>, 1045 resets = <&cru SRST_VOPB_A>, <&cru SRST_VOPB_H>, <&cru SRST_VOPB>;
1172 reset-names = "axi", "ahb", " 1046 reset-names = "axi", "ahb", "dclk";
1173 iommus = <&vopb_mmu>; 1047 iommus = <&vopb_mmu>;
1174 power-domains = <&power PX30_ 1048 power-domains = <&power PX30_PD_VO>;
1175 status = "disabled"; 1049 status = "disabled";
1176 1050
1177 vopb_out: port { 1051 vopb_out: port {
1178 #address-cells = <1>; 1052 #address-cells = <1>;
1179 #size-cells = <0>; 1053 #size-cells = <0>;
1180 1054
1181 vopb_out_dsi: endpoin 1055 vopb_out_dsi: endpoint@0 {
1182 reg = <0>; 1056 reg = <0>;
1183 remote-endpoi 1057 remote-endpoint = <&dsi_in_vopb>;
1184 }; 1058 };
1185 1059
1186 vopb_out_lvds: endpoi 1060 vopb_out_lvds: endpoint@1 {
1187 reg = <1>; 1061 reg = <1>;
1188 remote-endpoi 1062 remote-endpoint = <&lvds_vopb_in>;
1189 }; 1063 };
1190 }; 1064 };
1191 }; 1065 };
1192 1066
1193 vopb_mmu: iommu@ff460f00 { 1067 vopb_mmu: iommu@ff460f00 {
1194 compatible = "rockchip,iommu" 1068 compatible = "rockchip,iommu";
1195 reg = <0x0 0xff460f00 0x0 0x1 1069 reg = <0x0 0xff460f00 0x0 0x100>;
1196 interrupts = <GIC_SPI 77 IRQ_ 1070 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
>> 1071 interrupt-names = "vopb_mmu";
1197 clocks = <&cru ACLK_VOPB>, <& 1072 clocks = <&cru ACLK_VOPB>, <&cru HCLK_VOPB>;
1198 clock-names = "aclk", "iface" 1073 clock-names = "aclk", "iface";
1199 power-domains = <&power PX30_ 1074 power-domains = <&power PX30_PD_VO>;
1200 #iommu-cells = <0>; 1075 #iommu-cells = <0>;
1201 status = "disabled"; 1076 status = "disabled";
1202 }; 1077 };
1203 1078
1204 vopl: vop@ff470000 { 1079 vopl: vop@ff470000 {
1205 compatible = "rockchip,px30-v 1080 compatible = "rockchip,px30-vop-lit";
1206 reg = <0x0 0xff470000 0x0 0xe 1081 reg = <0x0 0xff470000 0x0 0xefc>;
1207 interrupts = <GIC_SPI 78 IRQ_ 1082 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
1208 clocks = <&cru ACLK_VOPL>, <& 1083 clocks = <&cru ACLK_VOPL>, <&cru DCLK_VOPL>,
1209 <&cru HCLK_VOPL>; 1084 <&cru HCLK_VOPL>;
1210 clock-names = "aclk_vop", "dc 1085 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1211 resets = <&cru SRST_VOPL_A>, 1086 resets = <&cru SRST_VOPL_A>, <&cru SRST_VOPL_H>, <&cru SRST_VOPL>;
1212 reset-names = "axi", "ahb", " 1087 reset-names = "axi", "ahb", "dclk";
1213 iommus = <&vopl_mmu>; 1088 iommus = <&vopl_mmu>;
1214 power-domains = <&power PX30_ 1089 power-domains = <&power PX30_PD_VO>;
1215 status = "disabled"; 1090 status = "disabled";
1216 1091
1217 vopl_out: port { 1092 vopl_out: port {
1218 #address-cells = <1>; 1093 #address-cells = <1>;
1219 #size-cells = <0>; 1094 #size-cells = <0>;
1220 1095
1221 vopl_out_dsi: endpoin 1096 vopl_out_dsi: endpoint@0 {
1222 reg = <0>; 1097 reg = <0>;
1223 remote-endpoi 1098 remote-endpoint = <&dsi_in_vopl>;
1224 }; 1099 };
1225 1100
1226 vopl_out_lvds: endpoi 1101 vopl_out_lvds: endpoint@1 {
1227 reg = <1>; 1102 reg = <1>;
1228 remote-endpoi 1103 remote-endpoint = <&lvds_vopl_in>;
1229 }; 1104 };
1230 }; 1105 };
1231 }; 1106 };
1232 1107
1233 vopl_mmu: iommu@ff470f00 { 1108 vopl_mmu: iommu@ff470f00 {
1234 compatible = "rockchip,iommu" 1109 compatible = "rockchip,iommu";
1235 reg = <0x0 0xff470f00 0x0 0x1 1110 reg = <0x0 0xff470f00 0x0 0x100>;
1236 interrupts = <GIC_SPI 78 IRQ_ 1111 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
>> 1112 interrupt-names = "vopl_mmu";
1237 clocks = <&cru ACLK_VOPL>, <& 1113 clocks = <&cru ACLK_VOPL>, <&cru HCLK_VOPL>;
1238 clock-names = "aclk", "iface" 1114 clock-names = "aclk", "iface";
1239 power-domains = <&power PX30_ 1115 power-domains = <&power PX30_PD_VO>;
1240 #iommu-cells = <0>; 1116 #iommu-cells = <0>;
1241 status = "disabled"; 1117 status = "disabled";
1242 }; 1118 };
1243 1119
1244 isp: isp@ff4a0000 { <<
1245 compatible = "rockchip,px30-c <<
1246 reg = <0x0 0xff4a0000 0x0 0x8 <<
1247 interrupts = <GIC_SPI 70 IRQ_ <<
1248 <GIC_SPI 73 IRQ_ <<
1249 <GIC_SPI 74 IRQ_ <<
1250 interrupt-names = "isp", "mi" <<
1251 clocks = <&cru SCLK_ISP>, <<
1252 <&cru ACLK_ISP>, <<
1253 <&cru HCLK_ISP>, <<
1254 <&cru PCLK_ISP>; <<
1255 clock-names = "isp", "aclk", <<
1256 iommus = <&isp_mmu>; <<
1257 phys = <&csi_dphy>; <<
1258 phy-names = "dphy"; <<
1259 power-domains = <&power PX30_ <<
1260 status = "disabled"; <<
1261 <<
1262 ports { <<
1263 #address-cells = <1>; <<
1264 #size-cells = <0>; <<
1265 <<
1266 port@0 { <<
1267 reg = <0>; <<
1268 #address-cell <<
1269 #size-cells = <<
1270 }; <<
1271 }; <<
1272 }; <<
1273 <<
1274 isp_mmu: iommu@ff4a8000 { <<
1275 compatible = "rockchip,iommu" <<
1276 reg = <0x0 0xff4a8000 0x0 0x1 <<
1277 interrupts = <GIC_SPI 70 IRQ_ <<
1278 clocks = <&cru ACLK_ISP>, <&c <<
1279 clock-names = "aclk", "iface" <<
1280 power-domains = <&power PX30_ <<
1281 rockchip,disable-mmu-reset; <<
1282 #iommu-cells = <0>; <<
1283 }; <<
1284 <<
1285 qos_gmac: qos@ff518000 { 1120 qos_gmac: qos@ff518000 {
1286 compatible = "rockchip,px30-q 1121 compatible = "rockchip,px30-qos", "syscon";
1287 reg = <0x0 0xff518000 0x0 0x2 1122 reg = <0x0 0xff518000 0x0 0x20>;
1288 }; 1123 };
1289 1124
1290 qos_gpu: qos@ff520000 { 1125 qos_gpu: qos@ff520000 {
1291 compatible = "rockchip,px30-q 1126 compatible = "rockchip,px30-qos", "syscon";
1292 reg = <0x0 0xff520000 0x0 0x2 1127 reg = <0x0 0xff520000 0x0 0x20>;
1293 }; 1128 };
1294 1129
1295 qos_sdmmc: qos@ff52c000 { 1130 qos_sdmmc: qos@ff52c000 {
1296 compatible = "rockchip,px30-q 1131 compatible = "rockchip,px30-qos", "syscon";
1297 reg = <0x0 0xff52c000 0x0 0x2 1132 reg = <0x0 0xff52c000 0x0 0x20>;
1298 }; 1133 };
1299 1134
1300 qos_emmc: qos@ff538000 { 1135 qos_emmc: qos@ff538000 {
1301 compatible = "rockchip,px30-q 1136 compatible = "rockchip,px30-qos", "syscon";
1302 reg = <0x0 0xff538000 0x0 0x2 1137 reg = <0x0 0xff538000 0x0 0x20>;
1303 }; 1138 };
1304 1139
1305 qos_nand: qos@ff538080 { 1140 qos_nand: qos@ff538080 {
1306 compatible = "rockchip,px30-q 1141 compatible = "rockchip,px30-qos", "syscon";
1307 reg = <0x0 0xff538080 0x0 0x2 1142 reg = <0x0 0xff538080 0x0 0x20>;
1308 }; 1143 };
1309 1144
1310 qos_sdio: qos@ff538100 { 1145 qos_sdio: qos@ff538100 {
1311 compatible = "rockchip,px30-q 1146 compatible = "rockchip,px30-qos", "syscon";
1312 reg = <0x0 0xff538100 0x0 0x2 1147 reg = <0x0 0xff538100 0x0 0x20>;
1313 }; 1148 };
1314 1149
1315 qos_sfc: qos@ff538180 { 1150 qos_sfc: qos@ff538180 {
1316 compatible = "rockchip,px30-q 1151 compatible = "rockchip,px30-qos", "syscon";
1317 reg = <0x0 0xff538180 0x0 0x2 1152 reg = <0x0 0xff538180 0x0 0x20>;
1318 }; 1153 };
1319 1154
1320 qos_usb_host: qos@ff540000 { 1155 qos_usb_host: qos@ff540000 {
1321 compatible = "rockchip,px30-q 1156 compatible = "rockchip,px30-qos", "syscon";
1322 reg = <0x0 0xff540000 0x0 0x2 1157 reg = <0x0 0xff540000 0x0 0x20>;
1323 }; 1158 };
1324 1159
1325 qos_usb_otg: qos@ff540080 { 1160 qos_usb_otg: qos@ff540080 {
1326 compatible = "rockchip,px30-q 1161 compatible = "rockchip,px30-qos", "syscon";
1327 reg = <0x0 0xff540080 0x0 0x2 1162 reg = <0x0 0xff540080 0x0 0x20>;
1328 }; 1163 };
1329 1164
1330 qos_isp_128: qos@ff548000 { 1165 qos_isp_128: qos@ff548000 {
1331 compatible = "rockchip,px30-q 1166 compatible = "rockchip,px30-qos", "syscon";
1332 reg = <0x0 0xff548000 0x0 0x2 1167 reg = <0x0 0xff548000 0x0 0x20>;
1333 }; 1168 };
1334 1169
1335 qos_isp_rd: qos@ff548080 { 1170 qos_isp_rd: qos@ff548080 {
1336 compatible = "rockchip,px30-q 1171 compatible = "rockchip,px30-qos", "syscon";
1337 reg = <0x0 0xff548080 0x0 0x2 1172 reg = <0x0 0xff548080 0x0 0x20>;
1338 }; 1173 };
1339 1174
1340 qos_isp_wr: qos@ff548100 { 1175 qos_isp_wr: qos@ff548100 {
1341 compatible = "rockchip,px30-q 1176 compatible = "rockchip,px30-qos", "syscon";
1342 reg = <0x0 0xff548100 0x0 0x2 1177 reg = <0x0 0xff548100 0x0 0x20>;
1343 }; 1178 };
1344 1179
1345 qos_isp_m1: qos@ff548180 { 1180 qos_isp_m1: qos@ff548180 {
1346 compatible = "rockchip,px30-q 1181 compatible = "rockchip,px30-qos", "syscon";
1347 reg = <0x0 0xff548180 0x0 0x2 1182 reg = <0x0 0xff548180 0x0 0x20>;
1348 }; 1183 };
1349 1184
1350 qos_vip: qos@ff548200 { 1185 qos_vip: qos@ff548200 {
1351 compatible = "rockchip,px30-q 1186 compatible = "rockchip,px30-qos", "syscon";
1352 reg = <0x0 0xff548200 0x0 0x2 1187 reg = <0x0 0xff548200 0x0 0x20>;
1353 }; 1188 };
1354 1189
1355 qos_rga_rd: qos@ff550000 { 1190 qos_rga_rd: qos@ff550000 {
1356 compatible = "rockchip,px30-q 1191 compatible = "rockchip,px30-qos", "syscon";
1357 reg = <0x0 0xff550000 0x0 0x2 1192 reg = <0x0 0xff550000 0x0 0x20>;
1358 }; 1193 };
1359 1194
1360 qos_rga_wr: qos@ff550080 { 1195 qos_rga_wr: qos@ff550080 {
1361 compatible = "rockchip,px30-q 1196 compatible = "rockchip,px30-qos", "syscon";
1362 reg = <0x0 0xff550080 0x0 0x2 1197 reg = <0x0 0xff550080 0x0 0x20>;
1363 }; 1198 };
1364 1199
1365 qos_vop_m0: qos@ff550100 { 1200 qos_vop_m0: qos@ff550100 {
1366 compatible = "rockchip,px30-q 1201 compatible = "rockchip,px30-qos", "syscon";
1367 reg = <0x0 0xff550100 0x0 0x2 1202 reg = <0x0 0xff550100 0x0 0x20>;
1368 }; 1203 };
1369 1204
1370 qos_vop_m1: qos@ff550180 { 1205 qos_vop_m1: qos@ff550180 {
1371 compatible = "rockchip,px30-q 1206 compatible = "rockchip,px30-qos", "syscon";
1372 reg = <0x0 0xff550180 0x0 0x2 1207 reg = <0x0 0xff550180 0x0 0x20>;
1373 }; 1208 };
1374 1209
1375 qos_vpu: qos@ff558000 { 1210 qos_vpu: qos@ff558000 {
1376 compatible = "rockchip,px30-q 1211 compatible = "rockchip,px30-qos", "syscon";
1377 reg = <0x0 0xff558000 0x0 0x2 1212 reg = <0x0 0xff558000 0x0 0x20>;
1378 }; 1213 };
1379 1214
1380 qos_vpu_r128: qos@ff558080 { 1215 qos_vpu_r128: qos@ff558080 {
1381 compatible = "rockchip,px30-q 1216 compatible = "rockchip,px30-qos", "syscon";
1382 reg = <0x0 0xff558080 0x0 0x2 1217 reg = <0x0 0xff558080 0x0 0x20>;
1383 }; 1218 };
1384 1219
1385 pinctrl: pinctrl { 1220 pinctrl: pinctrl {
1386 compatible = "rockchip,px30-p 1221 compatible = "rockchip,px30-pinctrl";
1387 rockchip,grf = <&grf>; 1222 rockchip,grf = <&grf>;
1388 rockchip,pmu = <&pmugrf>; 1223 rockchip,pmu = <&pmugrf>;
1389 #address-cells = <2>; 1224 #address-cells = <2>;
1390 #size-cells = <2>; 1225 #size-cells = <2>;
1391 ranges; 1226 ranges;
1392 1227
1393 gpio0: gpio@ff040000 { !! 1228 gpio0: gpio0@ff040000 {
1394 compatible = "rockchi 1229 compatible = "rockchip,gpio-bank";
1395 reg = <0x0 0xff040000 1230 reg = <0x0 0xff040000 0x0 0x100>;
1396 interrupts = <GIC_SPI 1231 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
1397 clocks = <&pmucru PCL 1232 clocks = <&pmucru PCLK_GPIO0_PMU>;
1398 gpio-controller; 1233 gpio-controller;
1399 #gpio-cells = <2>; 1234 #gpio-cells = <2>;
1400 1235
1401 interrupt-controller; 1236 interrupt-controller;
1402 #interrupt-cells = <2 1237 #interrupt-cells = <2>;
1403 }; 1238 };
1404 1239
1405 gpio1: gpio@ff250000 { !! 1240 gpio1: gpio1@ff250000 {
1406 compatible = "rockchi 1241 compatible = "rockchip,gpio-bank";
1407 reg = <0x0 0xff250000 1242 reg = <0x0 0xff250000 0x0 0x100>;
1408 interrupts = <GIC_SPI 1243 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
1409 clocks = <&cru PCLK_G 1244 clocks = <&cru PCLK_GPIO1>;
1410 gpio-controller; 1245 gpio-controller;
1411 #gpio-cells = <2>; 1246 #gpio-cells = <2>;
1412 1247
1413 interrupt-controller; 1248 interrupt-controller;
1414 #interrupt-cells = <2 1249 #interrupt-cells = <2>;
1415 }; 1250 };
1416 1251
1417 gpio2: gpio@ff260000 { !! 1252 gpio2: gpio2@ff260000 {
1418 compatible = "rockchi 1253 compatible = "rockchip,gpio-bank";
1419 reg = <0x0 0xff260000 1254 reg = <0x0 0xff260000 0x0 0x100>;
1420 interrupts = <GIC_SPI 1255 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
1421 clocks = <&cru PCLK_G 1256 clocks = <&cru PCLK_GPIO2>;
1422 gpio-controller; 1257 gpio-controller;
1423 #gpio-cells = <2>; 1258 #gpio-cells = <2>;
1424 1259
1425 interrupt-controller; 1260 interrupt-controller;
1426 #interrupt-cells = <2 1261 #interrupt-cells = <2>;
1427 }; 1262 };
1428 1263
1429 gpio3: gpio@ff270000 { !! 1264 gpio3: gpio3@ff270000 {
1430 compatible = "rockchi 1265 compatible = "rockchip,gpio-bank";
1431 reg = <0x0 0xff270000 1266 reg = <0x0 0xff270000 0x0 0x100>;
1432 interrupts = <GIC_SPI 1267 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
1433 clocks = <&cru PCLK_G 1268 clocks = <&cru PCLK_GPIO3>;
1434 gpio-controller; 1269 gpio-controller;
1435 #gpio-cells = <2>; 1270 #gpio-cells = <2>;
1436 1271
1437 interrupt-controller; 1272 interrupt-controller;
1438 #interrupt-cells = <2 1273 #interrupt-cells = <2>;
1439 }; 1274 };
1440 1275
1441 pcfg_pull_up: pcfg-pull-up { 1276 pcfg_pull_up: pcfg-pull-up {
1442 bias-pull-up; 1277 bias-pull-up;
1443 }; 1278 };
1444 1279
1445 pcfg_pull_down: pcfg-pull-dow 1280 pcfg_pull_down: pcfg-pull-down {
1446 bias-pull-down; 1281 bias-pull-down;
1447 }; 1282 };
1448 1283
1449 pcfg_pull_none: pcfg-pull-non 1284 pcfg_pull_none: pcfg-pull-none {
1450 bias-disable; 1285 bias-disable;
1451 }; 1286 };
1452 1287
1453 pcfg_pull_none_2ma: pcfg-pull 1288 pcfg_pull_none_2ma: pcfg-pull-none-2ma {
1454 bias-disable; 1289 bias-disable;
1455 drive-strength = <2>; 1290 drive-strength = <2>;
1456 }; 1291 };
1457 1292
1458 pcfg_pull_up_2ma: pcfg-pull-u 1293 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
1459 bias-pull-up; 1294 bias-pull-up;
1460 drive-strength = <2>; 1295 drive-strength = <2>;
1461 }; 1296 };
1462 1297
1463 pcfg_pull_up_4ma: pcfg-pull-u 1298 pcfg_pull_up_4ma: pcfg-pull-up-4ma {
1464 bias-pull-up; 1299 bias-pull-up;
1465 drive-strength = <4>; 1300 drive-strength = <4>;
1466 }; 1301 };
1467 1302
1468 pcfg_pull_none_4ma: pcfg-pull 1303 pcfg_pull_none_4ma: pcfg-pull-none-4ma {
1469 bias-disable; 1304 bias-disable;
1470 drive-strength = <4>; 1305 drive-strength = <4>;
1471 }; 1306 };
1472 1307
1473 pcfg_pull_down_4ma: pcfg-pull 1308 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
1474 bias-pull-down; 1309 bias-pull-down;
1475 drive-strength = <4>; 1310 drive-strength = <4>;
1476 }; 1311 };
1477 1312
1478 pcfg_pull_none_8ma: pcfg-pull 1313 pcfg_pull_none_8ma: pcfg-pull-none-8ma {
1479 bias-disable; 1314 bias-disable;
1480 drive-strength = <8>; 1315 drive-strength = <8>;
1481 }; 1316 };
1482 1317
1483 pcfg_pull_up_8ma: pcfg-pull-u 1318 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
1484 bias-pull-up; 1319 bias-pull-up;
1485 drive-strength = <8>; 1320 drive-strength = <8>;
1486 }; 1321 };
1487 1322
1488 pcfg_pull_none_12ma: pcfg-pul 1323 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1489 bias-disable; 1324 bias-disable;
1490 drive-strength = <12> 1325 drive-strength = <12>;
1491 }; 1326 };
1492 1327
1493 pcfg_pull_up_12ma: pcfg-pull- 1328 pcfg_pull_up_12ma: pcfg-pull-up-12ma {
1494 bias-pull-up; 1329 bias-pull-up;
1495 drive-strength = <12> 1330 drive-strength = <12>;
1496 }; 1331 };
1497 1332
1498 pcfg_pull_none_smt: pcfg-pull 1333 pcfg_pull_none_smt: pcfg-pull-none-smt {
1499 bias-disable; 1334 bias-disable;
1500 input-schmitt-enable; 1335 input-schmitt-enable;
1501 }; 1336 };
1502 1337
1503 pcfg_output_high: pcfg-output 1338 pcfg_output_high: pcfg-output-high {
1504 output-high; 1339 output-high;
1505 }; 1340 };
1506 1341
1507 pcfg_output_low: pcfg-output- 1342 pcfg_output_low: pcfg-output-low {
1508 output-low; 1343 output-low;
1509 }; 1344 };
1510 1345
1511 pcfg_input_high: pcfg-input-h 1346 pcfg_input_high: pcfg-input-high {
1512 bias-pull-up; 1347 bias-pull-up;
1513 input-enable; 1348 input-enable;
1514 }; 1349 };
1515 1350
1516 pcfg_input: pcfg-input { 1351 pcfg_input: pcfg-input {
1517 input-enable; 1352 input-enable;
1518 }; 1353 };
1519 1354
1520 i2c0 { 1355 i2c0 {
1521 i2c0_xfer: i2c0-xfer 1356 i2c0_xfer: i2c0-xfer {
1522 rockchip,pins 1357 rockchip,pins =
1523 <0 RK 1358 <0 RK_PB0 1 &pcfg_pull_none_smt>,
1524 <0 RK 1359 <0 RK_PB1 1 &pcfg_pull_none_smt>;
1525 }; 1360 };
1526 }; 1361 };
1527 1362
1528 i2c1 { 1363 i2c1 {
1529 i2c1_xfer: i2c1-xfer 1364 i2c1_xfer: i2c1-xfer {
1530 rockchip,pins 1365 rockchip,pins =
1531 <0 RK 1366 <0 RK_PC2 1 &pcfg_pull_none_smt>,
1532 <0 RK 1367 <0 RK_PC3 1 &pcfg_pull_none_smt>;
1533 }; 1368 };
1534 }; 1369 };
1535 1370
1536 i2c2 { 1371 i2c2 {
1537 i2c2_xfer: i2c2-xfer 1372 i2c2_xfer: i2c2-xfer {
1538 rockchip,pins 1373 rockchip,pins =
1539 <2 RK 1374 <2 RK_PB7 2 &pcfg_pull_none_smt>,
1540 <2 RK 1375 <2 RK_PC0 2 &pcfg_pull_none_smt>;
1541 }; 1376 };
1542 }; 1377 };
1543 1378
1544 i2c3 { 1379 i2c3 {
1545 i2c3_xfer: i2c3-xfer 1380 i2c3_xfer: i2c3-xfer {
1546 rockchip,pins 1381 rockchip,pins =
1547 <1 RK 1382 <1 RK_PB4 4 &pcfg_pull_none_smt>,
1548 <1 RK 1383 <1 RK_PB5 4 &pcfg_pull_none_smt>;
1549 }; 1384 };
1550 }; 1385 };
1551 1386
1552 tsadc { 1387 tsadc {
1553 tsadc_otp_pin: tsadc- 1388 tsadc_otp_pin: tsadc-otp-pin {
1554 rockchip,pins 1389 rockchip,pins =
1555 <0 RK 1390 <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
1556 }; 1391 };
1557 1392
1558 tsadc_otp_out: tsadc- 1393 tsadc_otp_out: tsadc-otp-out {
1559 rockchip,pins 1394 rockchip,pins =
1560 <0 RK 1395 <0 RK_PA6 1 &pcfg_pull_none>;
1561 }; 1396 };
1562 }; 1397 };
1563 1398
1564 uart0 { 1399 uart0 {
1565 uart0_xfer: uart0-xfe 1400 uart0_xfer: uart0-xfer {
1566 rockchip,pins 1401 rockchip,pins =
1567 <0 RK 1402 <0 RK_PB2 1 &pcfg_pull_up>,
1568 <0 RK 1403 <0 RK_PB3 1 &pcfg_pull_up>;
1569 }; 1404 };
1570 1405
1571 uart0_cts: uart0-cts 1406 uart0_cts: uart0-cts {
1572 rockchip,pins 1407 rockchip,pins =
1573 <0 RK 1408 <0 RK_PB4 1 &pcfg_pull_none>;
1574 }; 1409 };
1575 1410
1576 uart0_rts: uart0-rts 1411 uart0_rts: uart0-rts {
1577 rockchip,pins 1412 rockchip,pins =
1578 <0 RK 1413 <0 RK_PB5 1 &pcfg_pull_none>;
1579 }; 1414 };
1580 }; 1415 };
1581 1416
1582 uart1 { 1417 uart1 {
1583 uart1_xfer: uart1-xfe 1418 uart1_xfer: uart1-xfer {
1584 rockchip,pins 1419 rockchip,pins =
1585 <1 RK 1420 <1 RK_PC1 1 &pcfg_pull_up>,
1586 <1 RK 1421 <1 RK_PC0 1 &pcfg_pull_up>;
1587 }; 1422 };
1588 1423
1589 uart1_cts: uart1-cts 1424 uart1_cts: uart1-cts {
1590 rockchip,pins 1425 rockchip,pins =
1591 <1 RK 1426 <1 RK_PC2 1 &pcfg_pull_none>;
1592 }; 1427 };
1593 1428
1594 uart1_rts: uart1-rts 1429 uart1_rts: uart1-rts {
1595 rockchip,pins 1430 rockchip,pins =
1596 <1 RK 1431 <1 RK_PC3 1 &pcfg_pull_none>;
1597 }; 1432 };
1598 }; 1433 };
1599 1434
1600 uart2-m0 { 1435 uart2-m0 {
1601 uart2m0_xfer: uart2m0 1436 uart2m0_xfer: uart2m0-xfer {
1602 rockchip,pins 1437 rockchip,pins =
1603 <1 RK 1438 <1 RK_PD2 2 &pcfg_pull_up>,
1604 <1 RK 1439 <1 RK_PD3 2 &pcfg_pull_up>;
1605 }; 1440 };
1606 }; 1441 };
1607 1442
1608 uart2-m1 { 1443 uart2-m1 {
1609 uart2m1_xfer: uart2m1 1444 uart2m1_xfer: uart2m1-xfer {
1610 rockchip,pins 1445 rockchip,pins =
1611 <2 RK 1446 <2 RK_PB4 2 &pcfg_pull_up>,
1612 <2 RK 1447 <2 RK_PB6 2 &pcfg_pull_up>;
1613 }; 1448 };
1614 }; 1449 };
1615 1450
1616 uart3-m0 { 1451 uart3-m0 {
1617 uart3m0_xfer: uart3m0 1452 uart3m0_xfer: uart3m0-xfer {
1618 rockchip,pins 1453 rockchip,pins =
1619 <0 RK 1454 <0 RK_PC0 2 &pcfg_pull_up>,
1620 <0 RK 1455 <0 RK_PC1 2 &pcfg_pull_up>;
1621 }; 1456 };
1622 1457
1623 uart3m0_cts: uart3m0- 1458 uart3m0_cts: uart3m0-cts {
1624 rockchip,pins 1459 rockchip,pins =
1625 <0 RK 1460 <0 RK_PC2 2 &pcfg_pull_none>;
1626 }; 1461 };
1627 1462
1628 uart3m0_rts: uart3m0- 1463 uart3m0_rts: uart3m0-rts {
1629 rockchip,pins 1464 rockchip,pins =
1630 <0 RK 1465 <0 RK_PC3 2 &pcfg_pull_none>;
1631 }; 1466 };
1632 }; 1467 };
1633 1468
1634 uart3-m1 { 1469 uart3-m1 {
1635 uart3m1_xfer: uart3m1 1470 uart3m1_xfer: uart3m1-xfer {
1636 rockchip,pins 1471 rockchip,pins =
1637 <1 RK 1472 <1 RK_PB6 2 &pcfg_pull_up>,
1638 <1 RK 1473 <1 RK_PB7 2 &pcfg_pull_up>;
1639 }; 1474 };
1640 1475
1641 uart3m1_cts: uart3m1- 1476 uart3m1_cts: uart3m1-cts {
1642 rockchip,pins 1477 rockchip,pins =
1643 <1 RK 1478 <1 RK_PB4 2 &pcfg_pull_none>;
1644 }; 1479 };
1645 1480
1646 uart3m1_rts: uart3m1- 1481 uart3m1_rts: uart3m1-rts {
1647 rockchip,pins 1482 rockchip,pins =
1648 <1 RK 1483 <1 RK_PB5 2 &pcfg_pull_none>;
1649 }; 1484 };
1650 }; 1485 };
1651 1486
1652 uart4 { 1487 uart4 {
1653 uart4_xfer: uart4-xfe 1488 uart4_xfer: uart4-xfer {
1654 rockchip,pins 1489 rockchip,pins =
1655 <1 RK 1490 <1 RK_PD4 2 &pcfg_pull_up>,
1656 <1 RK 1491 <1 RK_PD5 2 &pcfg_pull_up>;
1657 }; 1492 };
1658 1493
1659 uart4_cts: uart4-cts 1494 uart4_cts: uart4-cts {
1660 rockchip,pins 1495 rockchip,pins =
1661 <1 RK 1496 <1 RK_PD6 2 &pcfg_pull_none>;
1662 }; 1497 };
1663 1498
1664 uart4_rts: uart4-rts 1499 uart4_rts: uart4-rts {
1665 rockchip,pins 1500 rockchip,pins =
1666 <1 RK 1501 <1 RK_PD7 2 &pcfg_pull_none>;
1667 }; 1502 };
1668 }; 1503 };
1669 1504
1670 uart5 { 1505 uart5 {
1671 uart5_xfer: uart5-xfe 1506 uart5_xfer: uart5-xfer {
1672 rockchip,pins 1507 rockchip,pins =
1673 <3 RK 1508 <3 RK_PA2 4 &pcfg_pull_up>,
1674 <3 RK 1509 <3 RK_PA1 4 &pcfg_pull_up>;
1675 }; 1510 };
1676 1511
1677 uart5_cts: uart5-cts 1512 uart5_cts: uart5-cts {
1678 rockchip,pins 1513 rockchip,pins =
1679 <3 RK 1514 <3 RK_PA3 4 &pcfg_pull_none>;
1680 }; 1515 };
1681 1516
1682 uart5_rts: uart5-rts 1517 uart5_rts: uart5-rts {
1683 rockchip,pins 1518 rockchip,pins =
1684 <3 RK 1519 <3 RK_PA5 4 &pcfg_pull_none>;
1685 }; 1520 };
1686 }; 1521 };
1687 1522
1688 spi0 { 1523 spi0 {
1689 spi0_clk: spi0-clk { 1524 spi0_clk: spi0-clk {
1690 rockchip,pins 1525 rockchip,pins =
1691 <1 RK 1526 <1 RK_PB7 3 &pcfg_pull_up_4ma>;
1692 }; 1527 };
1693 1528
1694 spi0_csn: spi0-csn { 1529 spi0_csn: spi0-csn {
1695 rockchip,pins 1530 rockchip,pins =
1696 <1 RK 1531 <1 RK_PB6 3 &pcfg_pull_up_4ma>;
1697 }; 1532 };
1698 1533
1699 spi0_miso: spi0-miso 1534 spi0_miso: spi0-miso {
1700 rockchip,pins 1535 rockchip,pins =
1701 <1 RK 1536 <1 RK_PB5 3 &pcfg_pull_up_4ma>;
1702 }; 1537 };
1703 1538
1704 spi0_mosi: spi0-mosi 1539 spi0_mosi: spi0-mosi {
1705 rockchip,pins 1540 rockchip,pins =
1706 <1 RK 1541 <1 RK_PB4 3 &pcfg_pull_up_4ma>;
1707 }; 1542 };
1708 1543
1709 spi0_clk_hs: spi0-clk 1544 spi0_clk_hs: spi0-clk-hs {
1710 rockchip,pins 1545 rockchip,pins =
1711 <1 RK 1546 <1 RK_PB7 3 &pcfg_pull_up_8ma>;
1712 }; 1547 };
1713 1548
1714 spi0_miso_hs: spi0-mi 1549 spi0_miso_hs: spi0-miso-hs {
1715 rockchip,pins 1550 rockchip,pins =
1716 <1 RK 1551 <1 RK_PB5 3 &pcfg_pull_up_8ma>;
1717 }; 1552 };
1718 1553
1719 spi0_mosi_hs: spi0-mo 1554 spi0_mosi_hs: spi0-mosi-hs {
1720 rockchip,pins 1555 rockchip,pins =
1721 <1 RK 1556 <1 RK_PB4 3 &pcfg_pull_up_8ma>;
1722 }; 1557 };
1723 }; 1558 };
1724 1559
1725 spi1 { 1560 spi1 {
1726 spi1_clk: spi1-clk { 1561 spi1_clk: spi1-clk {
1727 rockchip,pins 1562 rockchip,pins =
1728 <3 RK 1563 <3 RK_PB7 4 &pcfg_pull_up_4ma>;
1729 }; 1564 };
1730 1565
1731 spi1_csn0: spi1-csn0 1566 spi1_csn0: spi1-csn0 {
1732 rockchip,pins 1567 rockchip,pins =
1733 <3 RK 1568 <3 RK_PB1 4 &pcfg_pull_up_4ma>;
1734 }; 1569 };
1735 1570
1736 spi1_csn1: spi1-csn1 1571 spi1_csn1: spi1-csn1 {
1737 rockchip,pins 1572 rockchip,pins =
1738 <3 RK 1573 <3 RK_PB2 2 &pcfg_pull_up_4ma>;
1739 }; 1574 };
1740 1575
1741 spi1_miso: spi1-miso 1576 spi1_miso: spi1-miso {
1742 rockchip,pins 1577 rockchip,pins =
1743 <3 RK 1578 <3 RK_PB6 4 &pcfg_pull_up_4ma>;
1744 }; 1579 };
1745 1580
1746 spi1_mosi: spi1-mosi 1581 spi1_mosi: spi1-mosi {
1747 rockchip,pins 1582 rockchip,pins =
1748 <3 RK 1583 <3 RK_PB4 4 &pcfg_pull_up_4ma>;
1749 }; 1584 };
1750 1585
1751 spi1_clk_hs: spi1-clk 1586 spi1_clk_hs: spi1-clk-hs {
1752 rockchip,pins 1587 rockchip,pins =
1753 <3 RK 1588 <3 RK_PB7 4 &pcfg_pull_up_8ma>;
1754 }; 1589 };
1755 1590
1756 spi1_miso_hs: spi1-mi 1591 spi1_miso_hs: spi1-miso-hs {
1757 rockchip,pins 1592 rockchip,pins =
1758 <3 RK 1593 <3 RK_PB6 4 &pcfg_pull_up_8ma>;
1759 }; 1594 };
1760 1595
1761 spi1_mosi_hs: spi1-mo 1596 spi1_mosi_hs: spi1-mosi-hs {
1762 rockchip,pins 1597 rockchip,pins =
1763 <3 RK 1598 <3 RK_PB4 4 &pcfg_pull_up_8ma>;
1764 }; 1599 };
1765 }; 1600 };
1766 1601
1767 pdm { 1602 pdm {
1768 pdm_clk0m0: pdm-clk0m 1603 pdm_clk0m0: pdm-clk0m0 {
1769 rockchip,pins 1604 rockchip,pins =
1770 <3 RK 1605 <3 RK_PC6 2 &pcfg_pull_none>;
1771 }; 1606 };
1772 1607
1773 pdm_clk0m1: pdm-clk0m 1608 pdm_clk0m1: pdm-clk0m1 {
1774 rockchip,pins 1609 rockchip,pins =
1775 <2 RK 1610 <2 RK_PC6 1 &pcfg_pull_none>;
1776 }; 1611 };
1777 1612
1778 pdm_clk1: pdm-clk1 { 1613 pdm_clk1: pdm-clk1 {
1779 rockchip,pins 1614 rockchip,pins =
1780 <3 RK 1615 <3 RK_PC7 2 &pcfg_pull_none>;
1781 }; 1616 };
1782 1617
1783 pdm_sdi0m0: pdm-sdi0m 1618 pdm_sdi0m0: pdm-sdi0m0 {
1784 rockchip,pins 1619 rockchip,pins =
1785 <3 RK 1620 <3 RK_PD3 2 &pcfg_pull_none>;
1786 }; 1621 };
1787 1622
1788 pdm_sdi0m1: pdm-sdi0m 1623 pdm_sdi0m1: pdm-sdi0m1 {
1789 rockchip,pins 1624 rockchip,pins =
1790 <2 RK 1625 <2 RK_PC5 2 &pcfg_pull_none>;
1791 }; 1626 };
1792 1627
1793 pdm_sdi1: pdm-sdi1 { 1628 pdm_sdi1: pdm-sdi1 {
1794 rockchip,pins 1629 rockchip,pins =
1795 <3 RK 1630 <3 RK_PD0 2 &pcfg_pull_none>;
1796 }; 1631 };
1797 1632
1798 pdm_sdi2: pdm-sdi2 { 1633 pdm_sdi2: pdm-sdi2 {
1799 rockchip,pins 1634 rockchip,pins =
1800 <3 RK 1635 <3 RK_PD1 2 &pcfg_pull_none>;
1801 }; 1636 };
1802 1637
1803 pdm_sdi3: pdm-sdi3 { 1638 pdm_sdi3: pdm-sdi3 {
1804 rockchip,pins 1639 rockchip,pins =
1805 <3 RK 1640 <3 RK_PD2 2 &pcfg_pull_none>;
1806 }; 1641 };
1807 1642
1808 pdm_clk0m0_sleep: pdm 1643 pdm_clk0m0_sleep: pdm-clk0m0-sleep {
1809 rockchip,pins 1644 rockchip,pins =
1810 <3 RK 1645 <3 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>;
1811 }; 1646 };
1812 1647
1813 pdm_clk0m_sleep1: pdm 1648 pdm_clk0m_sleep1: pdm-clk0m1-sleep {
1814 rockchip,pins 1649 rockchip,pins =
1815 <2 RK 1650 <2 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>;
1816 }; 1651 };
1817 1652
1818 pdm_clk1_sleep: pdm-c 1653 pdm_clk1_sleep: pdm-clk1-sleep {
1819 rockchip,pins 1654 rockchip,pins =
1820 <3 RK 1655 <3 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>;
1821 }; 1656 };
1822 1657
1823 pdm_sdi0m0_sleep: pdm 1658 pdm_sdi0m0_sleep: pdm-sdi0m0-sleep {
1824 rockchip,pins 1659 rockchip,pins =
1825 <3 RK 1660 <3 RK_PD3 RK_FUNC_GPIO &pcfg_input_high>;
1826 }; 1661 };
1827 1662
1828 pdm_sdi0m1_sleep: pdm 1663 pdm_sdi0m1_sleep: pdm-sdi0m1-sleep {
1829 rockchip,pins 1664 rockchip,pins =
1830 <2 RK 1665 <2 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>;
1831 }; 1666 };
1832 1667
1833 pdm_sdi1_sleep: pdm-s 1668 pdm_sdi1_sleep: pdm-sdi1-sleep {
1834 rockchip,pins 1669 rockchip,pins =
1835 <3 RK 1670 <3 RK_PD0 RK_FUNC_GPIO &pcfg_input_high>;
1836 }; 1671 };
1837 1672
1838 pdm_sdi2_sleep: pdm-s 1673 pdm_sdi2_sleep: pdm-sdi2-sleep {
1839 rockchip,pins 1674 rockchip,pins =
1840 <3 RK 1675 <3 RK_PD1 RK_FUNC_GPIO &pcfg_input_high>;
1841 }; 1676 };
1842 1677
1843 pdm_sdi3_sleep: pdm-s 1678 pdm_sdi3_sleep: pdm-sdi3-sleep {
1844 rockchip,pins 1679 rockchip,pins =
1845 <3 RK 1680 <3 RK_PD2 RK_FUNC_GPIO &pcfg_input_high>;
1846 }; 1681 };
1847 }; 1682 };
1848 1683
1849 i2s0 { 1684 i2s0 {
1850 i2s0_8ch_mclk: i2s0-8 1685 i2s0_8ch_mclk: i2s0-8ch-mclk {
1851 rockchip,pins 1686 rockchip,pins =
1852 <3 RK 1687 <3 RK_PC1 2 &pcfg_pull_none>;
1853 }; 1688 };
1854 1689
1855 i2s0_8ch_sclktx: i2s0 1690 i2s0_8ch_sclktx: i2s0-8ch-sclktx {
1856 rockchip,pins 1691 rockchip,pins =
1857 <3 RK 1692 <3 RK_PC3 2 &pcfg_pull_none>;
1858 }; 1693 };
1859 1694
1860 i2s0_8ch_sclkrx: i2s0 1695 i2s0_8ch_sclkrx: i2s0-8ch-sclkrx {
1861 rockchip,pins 1696 rockchip,pins =
1862 <3 RK 1697 <3 RK_PB4 2 &pcfg_pull_none>;
1863 }; 1698 };
1864 1699
1865 i2s0_8ch_lrcktx: i2s0 1700 i2s0_8ch_lrcktx: i2s0-8ch-lrcktx {
1866 rockchip,pins 1701 rockchip,pins =
1867 <3 RK 1702 <3 RK_PC2 2 &pcfg_pull_none>;
1868 }; 1703 };
1869 1704
1870 i2s0_8ch_lrckrx: i2s0 1705 i2s0_8ch_lrckrx: i2s0-8ch-lrckrx {
1871 rockchip,pins 1706 rockchip,pins =
1872 <3 RK 1707 <3 RK_PB5 2 &pcfg_pull_none>;
1873 }; 1708 };
1874 1709
1875 i2s0_8ch_sdo0: i2s0-8 1710 i2s0_8ch_sdo0: i2s0-8ch-sdo0 {
1876 rockchip,pins 1711 rockchip,pins =
1877 <3 RK 1712 <3 RK_PC4 2 &pcfg_pull_none>;
1878 }; 1713 };
1879 1714
1880 i2s0_8ch_sdo1: i2s0-8 1715 i2s0_8ch_sdo1: i2s0-8ch-sdo1 {
1881 rockchip,pins 1716 rockchip,pins =
1882 <3 RK 1717 <3 RK_PC0 2 &pcfg_pull_none>;
1883 }; 1718 };
1884 1719
1885 i2s0_8ch_sdo2: i2s0-8 1720 i2s0_8ch_sdo2: i2s0-8ch-sdo2 {
1886 rockchip,pins 1721 rockchip,pins =
1887 <3 RK 1722 <3 RK_PB7 2 &pcfg_pull_none>;
1888 }; 1723 };
1889 1724
1890 i2s0_8ch_sdo3: i2s0-8 1725 i2s0_8ch_sdo3: i2s0-8ch-sdo3 {
1891 rockchip,pins 1726 rockchip,pins =
1892 <3 RK 1727 <3 RK_PB6 2 &pcfg_pull_none>;
1893 }; 1728 };
1894 1729
1895 i2s0_8ch_sdi0: i2s0-8 1730 i2s0_8ch_sdi0: i2s0-8ch-sdi0 {
1896 rockchip,pins 1731 rockchip,pins =
1897 <3 RK 1732 <3 RK_PC5 2 &pcfg_pull_none>;
1898 }; 1733 };
1899 1734
1900 i2s0_8ch_sdi1: i2s0-8 1735 i2s0_8ch_sdi1: i2s0-8ch-sdi1 {
1901 rockchip,pins 1736 rockchip,pins =
1902 <3 RK 1737 <3 RK_PB3 2 &pcfg_pull_none>;
1903 }; 1738 };
1904 1739
1905 i2s0_8ch_sdi2: i2s0-8 1740 i2s0_8ch_sdi2: i2s0-8ch-sdi2 {
1906 rockchip,pins 1741 rockchip,pins =
1907 <3 RK 1742 <3 RK_PB1 2 &pcfg_pull_none>;
1908 }; 1743 };
1909 1744
1910 i2s0_8ch_sdi3: i2s0-8 1745 i2s0_8ch_sdi3: i2s0-8ch-sdi3 {
1911 rockchip,pins 1746 rockchip,pins =
1912 <3 RK 1747 <3 RK_PB0 2 &pcfg_pull_none>;
1913 }; 1748 };
1914 }; 1749 };
1915 1750
1916 i2s1 { 1751 i2s1 {
1917 i2s1_2ch_mclk: i2s1-2 1752 i2s1_2ch_mclk: i2s1-2ch-mclk {
1918 rockchip,pins 1753 rockchip,pins =
1919 <2 RK 1754 <2 RK_PC3 1 &pcfg_pull_none>;
1920 }; 1755 };
1921 1756
1922 i2s1_2ch_sclk: i2s1-2 1757 i2s1_2ch_sclk: i2s1-2ch-sclk {
1923 rockchip,pins 1758 rockchip,pins =
1924 <2 RK 1759 <2 RK_PC2 1 &pcfg_pull_none>;
1925 }; 1760 };
1926 1761
1927 i2s1_2ch_lrck: i2s1-2 1762 i2s1_2ch_lrck: i2s1-2ch-lrck {
1928 rockchip,pins 1763 rockchip,pins =
1929 <2 RK 1764 <2 RK_PC1 1 &pcfg_pull_none>;
1930 }; 1765 };
1931 1766
1932 i2s1_2ch_sdi: i2s1-2c 1767 i2s1_2ch_sdi: i2s1-2ch-sdi {
1933 rockchip,pins 1768 rockchip,pins =
1934 <2 RK 1769 <2 RK_PC5 1 &pcfg_pull_none>;
1935 }; 1770 };
1936 1771
1937 i2s1_2ch_sdo: i2s1-2c 1772 i2s1_2ch_sdo: i2s1-2ch-sdo {
1938 rockchip,pins 1773 rockchip,pins =
1939 <2 RK 1774 <2 RK_PC4 1 &pcfg_pull_none>;
1940 }; 1775 };
1941 }; 1776 };
1942 1777
1943 i2s2 { 1778 i2s2 {
1944 i2s2_2ch_mclk: i2s2-2 1779 i2s2_2ch_mclk: i2s2-2ch-mclk {
1945 rockchip,pins 1780 rockchip,pins =
1946 <3 RK 1781 <3 RK_PA1 2 &pcfg_pull_none>;
1947 }; 1782 };
1948 1783
1949 i2s2_2ch_sclk: i2s2-2 1784 i2s2_2ch_sclk: i2s2-2ch-sclk {
1950 rockchip,pins 1785 rockchip,pins =
1951 <3 RK 1786 <3 RK_PA2 2 &pcfg_pull_none>;
1952 }; 1787 };
1953 1788
1954 i2s2_2ch_lrck: i2s2-2 1789 i2s2_2ch_lrck: i2s2-2ch-lrck {
1955 rockchip,pins 1790 rockchip,pins =
1956 <3 RK 1791 <3 RK_PA3 2 &pcfg_pull_none>;
1957 }; 1792 };
1958 1793
1959 i2s2_2ch_sdi: i2s2-2c 1794 i2s2_2ch_sdi: i2s2-2ch-sdi {
1960 rockchip,pins 1795 rockchip,pins =
1961 <3 RK 1796 <3 RK_PA5 2 &pcfg_pull_none>;
1962 }; 1797 };
1963 1798
1964 i2s2_2ch_sdo: i2s2-2c 1799 i2s2_2ch_sdo: i2s2-2ch-sdo {
1965 rockchip,pins 1800 rockchip,pins =
1966 <3 RK 1801 <3 RK_PA7 2 &pcfg_pull_none>;
1967 }; 1802 };
1968 }; 1803 };
1969 1804
1970 sdmmc { 1805 sdmmc {
1971 sdmmc_clk: sdmmc-clk 1806 sdmmc_clk: sdmmc-clk {
1972 rockchip,pins 1807 rockchip,pins =
1973 <1 RK 1808 <1 RK_PD6 1 &pcfg_pull_none_8ma>;
1974 }; 1809 };
1975 1810
1976 sdmmc_cmd: sdmmc-cmd 1811 sdmmc_cmd: sdmmc-cmd {
1977 rockchip,pins 1812 rockchip,pins =
1978 <1 RK 1813 <1 RK_PD7 1 &pcfg_pull_up_8ma>;
1979 }; 1814 };
1980 1815
1981 sdmmc_det: sdmmc-det 1816 sdmmc_det: sdmmc-det {
1982 rockchip,pins 1817 rockchip,pins =
1983 <0 RK 1818 <0 RK_PA3 1 &pcfg_pull_up_8ma>;
1984 }; 1819 };
1985 1820
1986 sdmmc_bus1: sdmmc-bus 1821 sdmmc_bus1: sdmmc-bus1 {
1987 rockchip,pins 1822 rockchip,pins =
1988 <1 RK 1823 <1 RK_PD2 1 &pcfg_pull_up_8ma>;
1989 }; 1824 };
1990 1825
1991 sdmmc_bus4: sdmmc-bus 1826 sdmmc_bus4: sdmmc-bus4 {
1992 rockchip,pins 1827 rockchip,pins =
1993 <1 RK 1828 <1 RK_PD2 1 &pcfg_pull_up_8ma>,
1994 <1 RK 1829 <1 RK_PD3 1 &pcfg_pull_up_8ma>,
1995 <1 RK 1830 <1 RK_PD4 1 &pcfg_pull_up_8ma>,
1996 <1 RK 1831 <1 RK_PD5 1 &pcfg_pull_up_8ma>;
1997 }; 1832 };
1998 }; 1833 };
1999 1834
2000 sdio { 1835 sdio {
2001 sdio_clk: sdio-clk { 1836 sdio_clk: sdio-clk {
2002 rockchip,pins 1837 rockchip,pins =
2003 <1 RK 1838 <1 RK_PC5 1 &pcfg_pull_none>;
2004 }; 1839 };
2005 1840
2006 sdio_cmd: sdio-cmd { 1841 sdio_cmd: sdio-cmd {
2007 rockchip,pins 1842 rockchip,pins =
2008 <1 RK 1843 <1 RK_PC4 1 &pcfg_pull_up>;
2009 }; 1844 };
2010 1845
2011 sdio_bus4: sdio-bus4 1846 sdio_bus4: sdio-bus4 {
2012 rockchip,pins 1847 rockchip,pins =
2013 <1 RK 1848 <1 RK_PC6 1 &pcfg_pull_up>,
2014 <1 RK 1849 <1 RK_PC7 1 &pcfg_pull_up>,
2015 <1 RK 1850 <1 RK_PD0 1 &pcfg_pull_up>,
2016 <1 RK 1851 <1 RK_PD1 1 &pcfg_pull_up>;
2017 }; 1852 };
2018 }; 1853 };
2019 1854
2020 emmc { 1855 emmc {
2021 emmc_clk: emmc-clk { 1856 emmc_clk: emmc-clk {
2022 rockchip,pins 1857 rockchip,pins =
2023 <1 RK 1858 <1 RK_PB1 2 &pcfg_pull_none_8ma>;
2024 }; 1859 };
2025 1860
2026 emmc_cmd: emmc-cmd { 1861 emmc_cmd: emmc-cmd {
2027 rockchip,pins 1862 rockchip,pins =
2028 <1 RK 1863 <1 RK_PB2 2 &pcfg_pull_up_8ma>;
2029 }; 1864 };
2030 1865
2031 emmc_rstnout: emmc-rs 1866 emmc_rstnout: emmc-rstnout {
2032 rockchip,pins 1867 rockchip,pins =
2033 <1 RK 1868 <1 RK_PB3 2 &pcfg_pull_none>;
2034 }; 1869 };
2035 1870
2036 emmc_bus1: emmc-bus1 1871 emmc_bus1: emmc-bus1 {
2037 rockchip,pins 1872 rockchip,pins =
2038 <1 RK 1873 <1 RK_PA0 2 &pcfg_pull_up_8ma>;
2039 }; 1874 };
2040 1875
2041 emmc_bus4: emmc-bus4 1876 emmc_bus4: emmc-bus4 {
2042 rockchip,pins 1877 rockchip,pins =
2043 <1 RK 1878 <1 RK_PA0 2 &pcfg_pull_up_8ma>,
2044 <1 RK 1879 <1 RK_PA1 2 &pcfg_pull_up_8ma>,
2045 <1 RK 1880 <1 RK_PA2 2 &pcfg_pull_up_8ma>,
2046 <1 RK 1881 <1 RK_PA3 2 &pcfg_pull_up_8ma>;
2047 }; 1882 };
2048 1883
2049 emmc_bus8: emmc-bus8 1884 emmc_bus8: emmc-bus8 {
2050 rockchip,pins 1885 rockchip,pins =
2051 <1 RK 1886 <1 RK_PA0 2 &pcfg_pull_up_8ma>,
2052 <1 RK 1887 <1 RK_PA1 2 &pcfg_pull_up_8ma>,
2053 <1 RK 1888 <1 RK_PA2 2 &pcfg_pull_up_8ma>,
2054 <1 RK 1889 <1 RK_PA3 2 &pcfg_pull_up_8ma>,
2055 <1 RK 1890 <1 RK_PA4 2 &pcfg_pull_up_8ma>,
2056 <1 RK 1891 <1 RK_PA5 2 &pcfg_pull_up_8ma>,
2057 <1 RK 1892 <1 RK_PA6 2 &pcfg_pull_up_8ma>,
2058 <1 RK 1893 <1 RK_PA7 2 &pcfg_pull_up_8ma>;
2059 }; 1894 };
2060 }; 1895 };
2061 1896
2062 flash { 1897 flash {
2063 flash_cs0: flash-cs0 1898 flash_cs0: flash-cs0 {
2064 rockchip,pins 1899 rockchip,pins =
2065 <1 RK 1900 <1 RK_PB0 1 &pcfg_pull_none>;
2066 }; 1901 };
2067 1902
2068 flash_rdy: flash-rdy 1903 flash_rdy: flash-rdy {
2069 rockchip,pins 1904 rockchip,pins =
2070 <1 RK 1905 <1 RK_PB1 1 &pcfg_pull_none>;
2071 }; 1906 };
2072 1907
2073 flash_dqs: flash-dqs 1908 flash_dqs: flash-dqs {
2074 rockchip,pins 1909 rockchip,pins =
2075 <1 RK 1910 <1 RK_PB2 1 &pcfg_pull_none>;
2076 }; 1911 };
2077 1912
2078 flash_ale: flash-ale 1913 flash_ale: flash-ale {
2079 rockchip,pins 1914 rockchip,pins =
2080 <1 RK 1915 <1 RK_PB3 1 &pcfg_pull_none>;
2081 }; 1916 };
2082 1917
2083 flash_cle: flash-cle 1918 flash_cle: flash-cle {
2084 rockchip,pins 1919 rockchip,pins =
2085 <1 RK 1920 <1 RK_PB4 1 &pcfg_pull_none>;
2086 }; 1921 };
2087 1922
2088 flash_wrn: flash-wrn 1923 flash_wrn: flash-wrn {
2089 rockchip,pins 1924 rockchip,pins =
2090 <1 RK 1925 <1 RK_PB5 1 &pcfg_pull_none>;
2091 }; 1926 };
2092 1927
2093 flash_csl: flash-csl 1928 flash_csl: flash-csl {
2094 rockchip,pins 1929 rockchip,pins =
2095 <1 RK 1930 <1 RK_PB6 1 &pcfg_pull_none>;
2096 }; 1931 };
2097 1932
2098 flash_rdn: flash-rdn 1933 flash_rdn: flash-rdn {
2099 rockchip,pins 1934 rockchip,pins =
2100 <1 RK 1935 <1 RK_PB7 1 &pcfg_pull_none>;
2101 }; 1936 };
2102 1937
2103 flash_bus8: flash-bus 1938 flash_bus8: flash-bus8 {
2104 rockchip,pins 1939 rockchip,pins =
2105 <1 RK 1940 <1 RK_PA0 1 &pcfg_pull_up_12ma>,
2106 <1 RK 1941 <1 RK_PA1 1 &pcfg_pull_up_12ma>,
2107 <1 RK 1942 <1 RK_PA2 1 &pcfg_pull_up_12ma>,
2108 <1 RK 1943 <1 RK_PA3 1 &pcfg_pull_up_12ma>,
2109 <1 RK 1944 <1 RK_PA4 1 &pcfg_pull_up_12ma>,
2110 <1 RK 1945 <1 RK_PA5 1 &pcfg_pull_up_12ma>,
2111 <1 RK 1946 <1 RK_PA6 1 &pcfg_pull_up_12ma>,
2112 <1 RK 1947 <1 RK_PA7 1 &pcfg_pull_up_12ma>;
2113 }; <<
2114 }; <<
2115 <<
2116 sfc { <<
2117 sfc_bus4: sfc-bus4 { <<
2118 rockchip,pins <<
2119 <1 RK <<
2120 <1 RK <<
2121 <1 RK <<
2122 <1 RK <<
2123 }; <<
2124 <<
2125 sfc_bus2: sfc-bus2 { <<
2126 rockchip,pins <<
2127 <1 RK <<
2128 <1 RK <<
2129 }; <<
2130 <<
2131 sfc_cs0: sfc-cs0 { <<
2132 rockchip,pins <<
2133 <1 RK <<
2134 }; <<
2135 <<
2136 sfc_clk: sfc-clk { <<
2137 rockchip,pins <<
2138 <1 RK <<
2139 }; 1948 };
2140 }; 1949 };
2141 1950
2142 lcdc { 1951 lcdc {
2143 lcdc_rgb_dclk_pin: lc 1952 lcdc_rgb_dclk_pin: lcdc-rgb-dclk-pin {
2144 rockchip,pins 1953 rockchip,pins =
2145 <3 RK 1954 <3 RK_PA0 1 &pcfg_pull_none_12ma>;
2146 }; 1955 };
2147 1956
2148 lcdc_rgb_m0_hsync_pin 1957 lcdc_rgb_m0_hsync_pin: lcdc-rgb-m0-hsync-pin {
2149 rockchip,pins 1958 rockchip,pins =
2150 <3 RK 1959 <3 RK_PA1 1 &pcfg_pull_none_12ma>;
2151 }; 1960 };
2152 1961
2153 lcdc_rgb_m0_vsync_pin 1962 lcdc_rgb_m0_vsync_pin: lcdc-rgb-m0-vsync-pin {
2154 rockchip,pins 1963 rockchip,pins =
2155 <3 RK 1964 <3 RK_PA2 1 &pcfg_pull_none_12ma>;
2156 }; 1965 };
2157 1966
2158 lcdc_rgb_m0_den_pin: 1967 lcdc_rgb_m0_den_pin: lcdc-rgb-m0-den-pin {
2159 rockchip,pins 1968 rockchip,pins =
2160 <3 RK 1969 <3 RK_PA3 1 &pcfg_pull_none_12ma>;
2161 }; 1970 };
2162 1971
2163 lcdc_rgb888_m0_data_p 1972 lcdc_rgb888_m0_data_pins: lcdc-rgb888-m0-data-pins {
2164 rockchip,pins 1973 rockchip,pins =
2165 <3 RK 1974 <3 RK_PA7 1 &pcfg_pull_none_8ma>, /* lcdc_d3 */
2166 <3 RK 1975 <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */
2167 <3 RK 1976 <3 RK_PA5 1 &pcfg_pull_none_8ma>, /* lcdc_d1 */
2168 <3 RK 1977 <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */
2169 <3 RK 1978 <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */
2170 <3 RK 1979 <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */
2171 <3 RK 1980 <3 RK_PB1 1 &pcfg_pull_none_8ma>, /* lcdc_d5 */
2172 <3 RK 1981 <3 RK_PB0 1 &pcfg_pull_none_8ma>, /* lcdc_d4 */
2173 <3 RK 1982 <3 RK_PB7 1 &pcfg_pull_none_8ma>, /* lcdc_d11 */
2174 <3 RK 1983 <3 RK_PB6 1 &pcfg_pull_none_8ma>, /* lcdc_d10 */
2175 <3 RK 1984 <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */
2176 <3 RK 1985 <3 RK_PB4 1 &pcfg_pull_none_8ma>, /* lcdc_d8 */
2177 <3 RK 1986 <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */
2178 <3 RK 1987 <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */
2179 <3 RK 1988 <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */
2180 <3 RK 1989 <3 RK_PC0 1 &pcfg_pull_none_8ma>, /* lcdc_d12 */
2181 <3 RK 1990 <3 RK_PC7 1 &pcfg_pull_none_8ma>, /* lcdc_d19 */
2182 <3 RK 1991 <3 RK_PC6 1 &pcfg_pull_none_8ma>, /* lcdc_d18 */
2183 <3 RK 1992 <3 RK_PC5 1 &pcfg_pull_none_8ma>, /* lcdc_d17 */
2184 <3 RK 1993 <3 RK_PC4 1 &pcfg_pull_none_8ma>, /* lcdc_d16 */
2185 <3 RK 1994 <3 RK_PD3 1 &pcfg_pull_none_8ma>, /* lcdc_d23 */
2186 <3 RK 1995 <3 RK_PD2 1 &pcfg_pull_none_8ma>, /* lcdc_d22 */
2187 <3 RK 1996 <3 RK_PD1 1 &pcfg_pull_none_8ma>, /* lcdc_d21 */
2188 <3 RK 1997 <3 RK_PD0 1 &pcfg_pull_none_8ma>; /* lcdc_d20 */
2189 }; 1998 };
2190 1999
2191 lcdc_rgb666_m0_data_p 2000 lcdc_rgb666_m0_data_pins: lcdc-rgb666-m0-data-pins {
2192 rockchip,pins 2001 rockchip,pins =
2193 <3 RK 2002 <3 RK_PA7 1 &pcfg_pull_none_8ma>, /* lcdc_d3 */
2194 <3 RK 2003 <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */
2195 <3 RK 2004 <3 RK_PA5 1 &pcfg_pull_none_8ma>, /* lcdc_d1 */
2196 <3 RK 2005 <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */
2197 <3 RK 2006 <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */
2198 <3 RK 2007 <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */
2199 <3 RK 2008 <3 RK_PB1 1 &pcfg_pull_none_8ma>, /* lcdc_d5 */
2200 <3 RK 2009 <3 RK_PB0 1 &pcfg_pull_none_8ma>, /* lcdc_d4 */
2201 <3 RK 2010 <3 RK_PB7 1 &pcfg_pull_none_8ma>, /* lcdc_d11 */
2202 <3 RK 2011 <3 RK_PB6 1 &pcfg_pull_none_8ma>, /* lcdc_d10 */
2203 <3 RK 2012 <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */
2204 <3 RK 2013 <3 RK_PB4 1 &pcfg_pull_none_8ma>, /* lcdc_d8 */
2205 <3 RK 2014 <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */
2206 <3 RK 2015 <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */
2207 <3 RK 2016 <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */
2208 <3 RK 2017 <3 RK_PC0 1 &pcfg_pull_none_8ma>, /* lcdc_d12 */
2209 <3 RK 2018 <3 RK_PC5 1 &pcfg_pull_none_8ma>, /* lcdc_d17 */
2210 <3 RK 2019 <3 RK_PC4 1 &pcfg_pull_none_8ma>; /* lcdc_d16 */
2211 }; 2020 };
2212 2021
2213 lcdc_rgb565_m0_data_p 2022 lcdc_rgb565_m0_data_pins: lcdc-rgb565-m0-data-pins {
2214 rockchip,pins 2023 rockchip,pins =
2215 <3 RK 2024 <3 RK_PA7 1 &pcfg_pull_none_8ma>, /* lcdc_d3 */
2216 <3 RK 2025 <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */
2217 <3 RK 2026 <3 RK_PA5 1 &pcfg_pull_none_8ma>, /* lcdc_d1 */
2218 <3 RK 2027 <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */
2219 <3 RK 2028 <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */
2220 <3 RK 2029 <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */
2221 <3 RK 2030 <3 RK_PB1 1 &pcfg_pull_none_8ma>, /* lcdc_d5 */
2222 <3 RK 2031 <3 RK_PB0 1 &pcfg_pull_none_8ma>, /* lcdc_d4 */
2223 <3 RK 2032 <3 RK_PB7 1 &pcfg_pull_none_8ma>, /* lcdc_d11 */
2224 <3 RK 2033 <3 RK_PB6 1 &pcfg_pull_none_8ma>, /* lcdc_d10 */
2225 <3 RK 2034 <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */
2226 <3 RK 2035 <3 RK_PB4 1 &pcfg_pull_none_8ma>, /* lcdc_d8 */
2227 <3 RK 2036 <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */
2228 <3 RK 2037 <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */
2229 <3 RK 2038 <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */
2230 <3 RK 2039 <3 RK_PC0 1 &pcfg_pull_none_8ma>; /* lcdc_d12 */
2231 }; 2040 };
2232 2041
2233 lcdc_rgb888_m1_data_p 2042 lcdc_rgb888_m1_data_pins: lcdc-rgb888-m1-data-pins {
2234 rockchip,pins 2043 rockchip,pins =
2235 <3 RK 2044 <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */
2236 <3 RK 2045 <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */
2237 <3 RK 2046 <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */
2238 <3 RK 2047 <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */
2239 <3 RK 2048 <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */
2240 <3 RK 2049 <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */
2241 <3 RK 2050 <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */
2242 <3 RK 2051 <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */
2243 <3 RK 2052 <3 RK_PC0 1 &pcfg_pull_none_8ma>, /* lcdc_d12 */
2244 <3 RK 2053 <3 RK_PC7 1 &pcfg_pull_none_8ma>, /* lcdc_d19 */
2245 <3 RK 2054 <3 RK_PC6 1 &pcfg_pull_none_8ma>, /* lcdc_d18 */
2246 <3 RK 2055 <3 RK_PC5 1 &pcfg_pull_none_8ma>, /* lcdc_d17 */
2247 <3 RK 2056 <3 RK_PC4 1 &pcfg_pull_none_8ma>, /* lcdc_d16 */
2248 <3 RK 2057 <3 RK_PD3 1 &pcfg_pull_none_8ma>, /* lcdc_d23 */
2249 <3 RK 2058 <3 RK_PD2 1 &pcfg_pull_none_8ma>, /* lcdc_d22 */
2250 <3 RK 2059 <3 RK_PD1 1 &pcfg_pull_none_8ma>, /* lcdc_d21 */
2251 <3 RK 2060 <3 RK_PD0 1 &pcfg_pull_none_8ma>; /* lcdc_d20 */
2252 }; 2061 };
2253 2062
2254 lcdc_rgb666_m1_data_p 2063 lcdc_rgb666_m1_data_pins: lcdc-rgb666-m1-data-pins {
2255 rockchip,pins 2064 rockchip,pins =
2256 <3 RK 2065 <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */
2257 <3 RK 2066 <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */
2258 <3 RK 2067 <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */
2259 <3 RK 2068 <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */
2260 <3 RK 2069 <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */
2261 <3 RK 2070 <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */
2262 <3 RK 2071 <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */
2263 <3 RK 2072 <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */
2264 <3 RK 2073 <3 RK_PC0 1 &pcfg_pull_none_8ma>, /* lcdc_d12 */
2265 <3 RK 2074 <3 RK_PC5 1 &pcfg_pull_none_8ma>, /* lcdc_d17 */
2266 <3 RK 2075 <3 RK_PC4 1 &pcfg_pull_none_8ma>; /* lcdc_d16 */
2267 }; 2076 };
2268 2077
2269 lcdc_rgb565_m1_data_p 2078 lcdc_rgb565_m1_data_pins: lcdc-rgb565-m1-data-pins {
2270 rockchip,pins 2079 rockchip,pins =
2271 <3 RK 2080 <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */
2272 <3 RK 2081 <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */
2273 <3 RK 2082 <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */
2274 <3 RK 2083 <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */
2275 <3 RK 2084 <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */
2276 <3 RK 2085 <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */
2277 <3 RK 2086 <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */
2278 <3 RK 2087 <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */
2279 <3 RK 2088 <3 RK_PC0 1 &pcfg_pull_none_8ma>; /* lcdc_d12 */
2280 }; 2089 };
2281 }; 2090 };
2282 2091
2283 pwm0 { 2092 pwm0 {
2284 pwm0_pin: pwm0-pin { 2093 pwm0_pin: pwm0-pin {
2285 rockchip,pins 2094 rockchip,pins =
2286 <0 RK 2095 <0 RK_PB7 1 &pcfg_pull_none>;
2287 }; 2096 };
2288 }; 2097 };
2289 2098
2290 pwm1 { 2099 pwm1 {
2291 pwm1_pin: pwm1-pin { 2100 pwm1_pin: pwm1-pin {
2292 rockchip,pins 2101 rockchip,pins =
2293 <0 RK 2102 <0 RK_PC0 1 &pcfg_pull_none>;
2294 }; 2103 };
2295 }; 2104 };
2296 2105
2297 pwm2 { 2106 pwm2 {
2298 pwm2_pin: pwm2-pin { 2107 pwm2_pin: pwm2-pin {
2299 rockchip,pins 2108 rockchip,pins =
2300 <2 RK 2109 <2 RK_PB5 1 &pcfg_pull_none>;
2301 }; 2110 };
2302 }; 2111 };
2303 2112
2304 pwm3 { 2113 pwm3 {
2305 pwm3_pin: pwm3-pin { 2114 pwm3_pin: pwm3-pin {
2306 rockchip,pins 2115 rockchip,pins =
2307 <0 RK 2116 <0 RK_PC1 1 &pcfg_pull_none>;
2308 }; 2117 };
2309 }; 2118 };
2310 2119
2311 pwm4 { 2120 pwm4 {
2312 pwm4_pin: pwm4-pin { 2121 pwm4_pin: pwm4-pin {
2313 rockchip,pins 2122 rockchip,pins =
2314 <3 RK 2123 <3 RK_PC2 3 &pcfg_pull_none>;
2315 }; 2124 };
2316 }; 2125 };
2317 2126
2318 pwm5 { 2127 pwm5 {
2319 pwm5_pin: pwm5-pin { 2128 pwm5_pin: pwm5-pin {
2320 rockchip,pins 2129 rockchip,pins =
2321 <3 RK 2130 <3 RK_PC3 3 &pcfg_pull_none>;
2322 }; 2131 };
2323 }; 2132 };
2324 2133
2325 pwm6 { 2134 pwm6 {
2326 pwm6_pin: pwm6-pin { 2135 pwm6_pin: pwm6-pin {
2327 rockchip,pins 2136 rockchip,pins =
2328 <3 RK 2137 <3 RK_PC4 3 &pcfg_pull_none>;
2329 }; 2138 };
2330 }; 2139 };
2331 2140
2332 pwm7 { 2141 pwm7 {
2333 pwm7_pin: pwm7-pin { 2142 pwm7_pin: pwm7-pin {
2334 rockchip,pins 2143 rockchip,pins =
2335 <3 RK 2144 <3 RK_PC5 3 &pcfg_pull_none>;
2336 }; 2145 };
2337 }; 2146 };
2338 2147
2339 gmac { 2148 gmac {
2340 rmii_pins: rmii-pins 2149 rmii_pins: rmii-pins {
2341 rockchip,pins 2150 rockchip,pins =
2342 <2 RK 2151 <2 RK_PA0 2 &pcfg_pull_none_12ma>, /* mac_txen */
2343 <2 RK 2152 <2 RK_PA1 2 &pcfg_pull_none_12ma>, /* mac_txd1 */
2344 <2 RK 2153 <2 RK_PA2 2 &pcfg_pull_none_12ma>, /* mac_txd0 */
2345 <2 RK 2154 <2 RK_PA3 2 &pcfg_pull_none>, /* mac_rxd0 */
2346 <2 RK 2155 <2 RK_PA4 2 &pcfg_pull_none>, /* mac_rxd1 */
2347 <2 RK 2156 <2 RK_PA5 2 &pcfg_pull_none>, /* mac_rxer */
2348 <2 RK 2157 <2 RK_PA6 2 &pcfg_pull_none>, /* mac_rxdv */
2349 <2 RK 2158 <2 RK_PA7 2 &pcfg_pull_none>, /* mac_mdio */
2350 <2 RK 2159 <2 RK_PB1 2 &pcfg_pull_none>; /* mac_mdc */
2351 }; 2160 };
2352 2161
2353 mac_refclk_12ma: mac- 2162 mac_refclk_12ma: mac-refclk-12ma {
2354 rockchip,pins 2163 rockchip,pins =
2355 <2 RK 2164 <2 RK_PB2 2 &pcfg_pull_none_12ma>;
2356 }; 2165 };
2357 2166
2358 mac_refclk: mac-refcl 2167 mac_refclk: mac-refclk {
2359 rockchip,pins 2168 rockchip,pins =
2360 <2 RK 2169 <2 RK_PB2 2 &pcfg_pull_none>;
2361 }; 2170 };
2362 }; 2171 };
2363 2172
2364 cif-m0 { 2173 cif-m0 {
2365 cif_clkout_m0: cif-cl 2174 cif_clkout_m0: cif-clkout-m0 {
2366 rockchip,pins 2175 rockchip,pins =
2367 <2 RK 2176 <2 RK_PB3 1 &pcfg_pull_none>;
2368 }; 2177 };
2369 2178
2370 dvp_d2d9_m0: dvp-d2d9 2179 dvp_d2d9_m0: dvp-d2d9-m0 {
2371 rockchip,pins 2180 rockchip,pins =
2372 <2 RK 2181 <2 RK_PA0 1 &pcfg_pull_none>, /* cif_data2 */
2373 <2 RK 2182 <2 RK_PA1 1 &pcfg_pull_none>, /* cif_data3 */
2374 <2 RK 2183 <2 RK_PA2 1 &pcfg_pull_none>, /* cif_data4 */
2375 <2 RK 2184 <2 RK_PA3 1 &pcfg_pull_none>, /* cif_data5 */
2376 <2 RK 2185 <2 RK_PA4 1 &pcfg_pull_none>, /* cif_data6 */
2377 <2 RK 2186 <2 RK_PA5 1 &pcfg_pull_none>, /* cif_data7 */
2378 <2 RK 2187 <2 RK_PA6 1 &pcfg_pull_none>, /* cif_data8 */
2379 <2 RK 2188 <2 RK_PA7 1 &pcfg_pull_none>, /* cif_data9 */
2380 <2 RK 2189 <2 RK_PB0 1 &pcfg_pull_none>, /* cif_sync */
2381 <2 RK 2190 <2 RK_PB1 1 &pcfg_pull_none>, /* cif_href */
2382 <2 RK 2191 <2 RK_PB2 1 &pcfg_pull_none>, /* cif_clkin */
2383 <2 RK 2192 <2 RK_PB3 1 &pcfg_pull_none>; /* cif_clkout */
2384 }; 2193 };
2385 2194
2386 dvp_d0d1_m0: dvp-d0d1 2195 dvp_d0d1_m0: dvp-d0d1-m0 {
2387 rockchip,pins 2196 rockchip,pins =
2388 <2 RK 2197 <2 RK_PB4 1 &pcfg_pull_none>, /* cif_data0 */
2389 <2 RK 2198 <2 RK_PB6 1 &pcfg_pull_none>; /* cif_data1 */
2390 }; 2199 };
2391 2200
2392 dvp_d10d11_m0:d10-d11 2201 dvp_d10d11_m0:d10-d11-m0 {
2393 rockchip,pins 2202 rockchip,pins =
2394 <2 RK 2203 <2 RK_PB7 1 &pcfg_pull_none>, /* cif_data10 */
2395 <2 RK 2204 <2 RK_PC0 1 &pcfg_pull_none>; /* cif_data11 */
2396 }; 2205 };
2397 }; 2206 };
2398 2207
2399 cif-m1 { 2208 cif-m1 {
2400 cif_clkout_m1: cif-cl 2209 cif_clkout_m1: cif-clkout-m1 {
2401 rockchip,pins 2210 rockchip,pins =
2402 <3 RK 2211 <3 RK_PD0 3 &pcfg_pull_none>;
2403 }; 2212 };
2404 2213
2405 dvp_d2d9_m1: dvp-d2d9 2214 dvp_d2d9_m1: dvp-d2d9-m1 {
2406 rockchip,pins 2215 rockchip,pins =
2407 <3 RK 2216 <3 RK_PA3 3 &pcfg_pull_none>, /* cif_data2 */
2408 <3 RK 2217 <3 RK_PA5 3 &pcfg_pull_none>, /* cif_data3 */
2409 <3 RK 2218 <3 RK_PA7 3 &pcfg_pull_none>, /* cif_data4 */
2410 <3 RK 2219 <3 RK_PB0 3 &pcfg_pull_none>, /* cif_data5 */
2411 <3 RK 2220 <3 RK_PB1 3 &pcfg_pull_none>, /* cif_data6 */
2412 <3 RK 2221 <3 RK_PB4 3 &pcfg_pull_none>, /* cif_data7 */
2413 <3 RK 2222 <3 RK_PB6 3 &pcfg_pull_none>, /* cif_data8 */
2414 <3 RK 2223 <3 RK_PB7 3 &pcfg_pull_none>, /* cif_data9 */
2415 <3 RK 2224 <3 RK_PD1 3 &pcfg_pull_none>, /* cif_sync */
2416 <3 RK 2225 <3 RK_PD2 3 &pcfg_pull_none>, /* cif_href */
2417 <3 RK 2226 <3 RK_PD3 3 &pcfg_pull_none>, /* cif_clkin */
2418 <3 RK 2227 <3 RK_PD0 3 &pcfg_pull_none>; /* cif_clkout */
2419 }; 2228 };
2420 2229
2421 dvp_d0d1_m1: dvp-d0d1 2230 dvp_d0d1_m1: dvp-d0d1-m1 {
2422 rockchip,pins 2231 rockchip,pins =
2423 <3 RK 2232 <3 RK_PA1 3 &pcfg_pull_none>, /* cif_data0 */
2424 <3 RK 2233 <3 RK_PA2 3 &pcfg_pull_none>; /* cif_data1 */
2425 }; 2234 };
2426 2235
2427 dvp_d10d11_m1:d10-d11 2236 dvp_d10d11_m1:d10-d11-m1 {
2428 rockchip,pins 2237 rockchip,pins =
2429 <3 RK 2238 <3 RK_PC6 3 &pcfg_pull_none>, /* cif_data10 */
2430 <3 RK 2239 <3 RK_PC7 3 &pcfg_pull_none>; /* cif_data11 */
2431 }; 2240 };
2432 }; 2241 };
2433 2242
2434 isp { 2243 isp {
2435 isp_prelight: isp-pre 2244 isp_prelight: isp-prelight {
2436 rockchip,pins 2245 rockchip,pins =
2437 <3 RK 2246 <3 RK_PD1 4 &pcfg_pull_none>;
2438 }; 2247 };
2439 }; 2248 };
2440 }; 2249 };
2441 }; 2250 };
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