1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /* 2 /*
3 * Copyright (c) 2018 Fuzhou Rockchip Electron 3 * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd
4 */ 4 */
5 5
6 #include <dt-bindings/clock/px30-cru.h> 6 #include <dt-bindings/clock/px30-cru.h>
7 #include <dt-bindings/gpio/gpio.h> 7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/interrupt-controller/arm 8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/interrupt-controller/irq 9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/pinctrl/rockchip.h> 10 #include <dt-bindings/pinctrl/rockchip.h>
11 #include <dt-bindings/power/px30-power.h> 11 #include <dt-bindings/power/px30-power.h>
12 #include <dt-bindings/soc/rockchip,boot-mode.h 12 #include <dt-bindings/soc/rockchip,boot-mode.h>
13 #include <dt-bindings/thermal/thermal.h> 13 #include <dt-bindings/thermal/thermal.h>
14 14
15 / { 15 / {
16 compatible = "rockchip,px30"; 16 compatible = "rockchip,px30";
17 17
18 interrupt-parent = <&gic>; 18 interrupt-parent = <&gic>;
19 #address-cells = <2>; 19 #address-cells = <2>;
20 #size-cells = <2>; 20 #size-cells = <2>;
21 21
22 aliases { 22 aliases {
>> 23 ethernet0 = &gmac;
23 i2c0 = &i2c0; 24 i2c0 = &i2c0;
24 i2c1 = &i2c1; 25 i2c1 = &i2c1;
25 i2c2 = &i2c2; 26 i2c2 = &i2c2;
26 i2c3 = &i2c3; 27 i2c3 = &i2c3;
27 serial0 = &uart0; 28 serial0 = &uart0;
28 serial1 = &uart1; 29 serial1 = &uart1;
29 serial2 = &uart2; 30 serial2 = &uart2;
30 serial3 = &uart3; 31 serial3 = &uart3;
31 serial4 = &uart4; 32 serial4 = &uart4;
32 serial5 = &uart5; 33 serial5 = &uart5;
33 spi0 = &spi0; 34 spi0 = &spi0;
34 spi1 = &spi1; 35 spi1 = &spi1;
35 }; 36 };
36 37
37 cpus { 38 cpus {
38 #address-cells = <2>; 39 #address-cells = <2>;
39 #size-cells = <0>; 40 #size-cells = <0>;
40 41
41 cpu0: cpu@0 { 42 cpu0: cpu@0 {
42 device_type = "cpu"; 43 device_type = "cpu";
43 compatible = "arm,cort 44 compatible = "arm,cortex-a35";
44 reg = <0x0 0x0>; 45 reg = <0x0 0x0>;
45 enable-method = "psci" 46 enable-method = "psci";
46 clocks = <&cru ARMCLK> 47 clocks = <&cru ARMCLK>;
47 #cooling-cells = <2>; 48 #cooling-cells = <2>;
48 cpu-idle-states = <&CP 49 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
49 dynamic-power-coeffici 50 dynamic-power-coefficient = <90>;
50 operating-points-v2 = 51 operating-points-v2 = <&cpu0_opp_table>;
51 }; 52 };
52 53
53 cpu1: cpu@1 { 54 cpu1: cpu@1 {
54 device_type = "cpu"; 55 device_type = "cpu";
55 compatible = "arm,cort 56 compatible = "arm,cortex-a35";
56 reg = <0x0 0x1>; 57 reg = <0x0 0x1>;
57 enable-method = "psci" 58 enable-method = "psci";
58 clocks = <&cru ARMCLK> 59 clocks = <&cru ARMCLK>;
59 #cooling-cells = <2>; 60 #cooling-cells = <2>;
60 cpu-idle-states = <&CP 61 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
61 dynamic-power-coeffici 62 dynamic-power-coefficient = <90>;
62 operating-points-v2 = 63 operating-points-v2 = <&cpu0_opp_table>;
63 }; 64 };
64 65
65 cpu2: cpu@2 { 66 cpu2: cpu@2 {
66 device_type = "cpu"; 67 device_type = "cpu";
67 compatible = "arm,cort 68 compatible = "arm,cortex-a35";
68 reg = <0x0 0x2>; 69 reg = <0x0 0x2>;
69 enable-method = "psci" 70 enable-method = "psci";
70 clocks = <&cru ARMCLK> 71 clocks = <&cru ARMCLK>;
71 #cooling-cells = <2>; 72 #cooling-cells = <2>;
72 cpu-idle-states = <&CP 73 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
73 dynamic-power-coeffici 74 dynamic-power-coefficient = <90>;
74 operating-points-v2 = 75 operating-points-v2 = <&cpu0_opp_table>;
75 }; 76 };
76 77
77 cpu3: cpu@3 { 78 cpu3: cpu@3 {
78 device_type = "cpu"; 79 device_type = "cpu";
79 compatible = "arm,cort 80 compatible = "arm,cortex-a35";
80 reg = <0x0 0x3>; 81 reg = <0x0 0x3>;
81 enable-method = "psci" 82 enable-method = "psci";
82 clocks = <&cru ARMCLK> 83 clocks = <&cru ARMCLK>;
83 #cooling-cells = <2>; 84 #cooling-cells = <2>;
84 cpu-idle-states = <&CP 85 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
85 dynamic-power-coeffici 86 dynamic-power-coefficient = <90>;
86 operating-points-v2 = 87 operating-points-v2 = <&cpu0_opp_table>;
87 }; 88 };
88 89
89 idle-states { 90 idle-states {
90 entry-method = "psci"; 91 entry-method = "psci";
91 92
92 CPU_SLEEP: cpu-sleep { 93 CPU_SLEEP: cpu-sleep {
93 compatible = " 94 compatible = "arm,idle-state";
94 local-timer-st 95 local-timer-stop;
95 arm,psci-suspe 96 arm,psci-suspend-param = <0x0010000>;
96 entry-latency- 97 entry-latency-us = <120>;
97 exit-latency-u 98 exit-latency-us = <250>;
98 min-residency- 99 min-residency-us = <900>;
99 }; 100 };
100 101
101 CLUSTER_SLEEP: cluster 102 CLUSTER_SLEEP: cluster-sleep {
102 compatible = " 103 compatible = "arm,idle-state";
103 local-timer-st 104 local-timer-stop;
104 arm,psci-suspe 105 arm,psci-suspend-param = <0x1010000>;
105 entry-latency- 106 entry-latency-us = <400>;
106 exit-latency-u 107 exit-latency-us = <500>;
107 min-residency- 108 min-residency-us = <2000>;
108 }; 109 };
109 }; 110 };
110 }; 111 };
111 112
112 cpu0_opp_table: opp-table-0 { !! 113 cpu0_opp_table: cpu0-opp-table {
113 compatible = "operating-points 114 compatible = "operating-points-v2";
114 opp-shared; 115 opp-shared;
115 116
116 opp-600000000 { 117 opp-600000000 {
117 opp-hz = /bits/ 64 <60 118 opp-hz = /bits/ 64 <600000000>;
118 opp-microvolt = <95000 119 opp-microvolt = <950000 950000 1350000>;
119 clock-latency-ns = <40 120 clock-latency-ns = <40000>;
120 opp-suspend; 121 opp-suspend;
121 }; 122 };
122 opp-816000000 { 123 opp-816000000 {
123 opp-hz = /bits/ 64 <81 124 opp-hz = /bits/ 64 <816000000>;
124 opp-microvolt = <10500 125 opp-microvolt = <1050000 1050000 1350000>;
125 clock-latency-ns = <40 126 clock-latency-ns = <40000>;
126 }; 127 };
127 opp-1008000000 { 128 opp-1008000000 {
128 opp-hz = /bits/ 64 <10 129 opp-hz = /bits/ 64 <1008000000>;
129 opp-microvolt = <11750 130 opp-microvolt = <1175000 1175000 1350000>;
130 clock-latency-ns = <40 131 clock-latency-ns = <40000>;
131 }; 132 };
132 opp-1200000000 { 133 opp-1200000000 {
133 opp-hz = /bits/ 64 <12 134 opp-hz = /bits/ 64 <1200000000>;
134 opp-microvolt = <13000 135 opp-microvolt = <1300000 1300000 1350000>;
135 clock-latency-ns = <40 136 clock-latency-ns = <40000>;
136 }; 137 };
137 opp-1296000000 { 138 opp-1296000000 {
138 opp-hz = /bits/ 64 <12 139 opp-hz = /bits/ 64 <1296000000>;
139 opp-microvolt = <13500 140 opp-microvolt = <1350000 1350000 1350000>;
140 clock-latency-ns = <40 141 clock-latency-ns = <40000>;
141 }; 142 };
142 }; 143 };
143 144
144 arm-pmu { 145 arm-pmu {
145 compatible = "arm,cortex-a35-p 146 compatible = "arm,cortex-a35-pmu";
146 interrupts = <GIC_SPI 100 IRQ_ 147 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
147 <GIC_SPI 101 IRQ_ 148 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
148 <GIC_SPI 102 IRQ_ 149 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
149 <GIC_SPI 103 IRQ_ 150 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
150 interrupt-affinity = <&cpu0>, 151 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
151 }; 152 };
152 153
153 display_subsystem: display-subsystem { 154 display_subsystem: display-subsystem {
154 compatible = "rockchip,display 155 compatible = "rockchip,display-subsystem";
155 ports = <&vopb_out>, <&vopl_ou 156 ports = <&vopb_out>, <&vopl_out>;
156 status = "disabled"; 157 status = "disabled";
157 }; 158 };
158 159
159 gmac_clkin: external-gmac-clock { 160 gmac_clkin: external-gmac-clock {
160 compatible = "fixed-clock"; 161 compatible = "fixed-clock";
161 clock-frequency = <50000000>; 162 clock-frequency = <50000000>;
162 clock-output-names = "gmac_clk 163 clock-output-names = "gmac_clkin";
163 #clock-cells = <0>; 164 #clock-cells = <0>;
164 }; 165 };
165 166
166 psci { 167 psci {
167 compatible = "arm,psci-1.0"; 168 compatible = "arm,psci-1.0";
168 method = "smc"; 169 method = "smc";
169 }; 170 };
170 171
171 timer { 172 timer {
172 compatible = "arm,armv8-timer" 173 compatible = "arm,armv8-timer";
173 interrupts = <GIC_PPI 13 (GIC_ 174 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
174 <GIC_PPI 14 (GIC_ 175 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
175 <GIC_PPI 11 (GIC_ 176 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
176 <GIC_PPI 10 (GIC_ 177 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
177 }; 178 };
178 179
179 thermal_zones: thermal-zones { 180 thermal_zones: thermal-zones {
180 soc_thermal: soc-thermal { 181 soc_thermal: soc-thermal {
181 polling-delay-passive 182 polling-delay-passive = <20>;
182 polling-delay = <1000> 183 polling-delay = <1000>;
183 sustainable-power = <7 184 sustainable-power = <750>;
184 thermal-sensors = <&ts 185 thermal-sensors = <&tsadc 0>;
185 186
186 trips { 187 trips {
187 threshold: tri 188 threshold: trip-point-0 {
188 temper 189 temperature = <70000>;
189 hyster 190 hysteresis = <2000>;
190 type = 191 type = "passive";
191 }; 192 };
192 193
193 target: trip-p 194 target: trip-point-1 {
194 temper 195 temperature = <85000>;
195 hyster 196 hysteresis = <2000>;
196 type = 197 type = "passive";
197 }; 198 };
198 199
199 soc_crit: soc- 200 soc_crit: soc-crit {
200 temper 201 temperature = <115000>;
201 hyster 202 hysteresis = <2000>;
202 type = 203 type = "critical";
203 }; 204 };
204 }; 205 };
205 206
206 cooling-maps { 207 cooling-maps {
207 map0 { 208 map0 {
208 trip = 209 trip = <&target>;
209 coolin 210 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
210 contri 211 contribution = <4096>;
211 }; 212 };
>> 213
>> 214 map1 {
>> 215 trip = <&target>;
>> 216 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
>> 217 contribution = <4096>;
>> 218 };
212 }; 219 };
213 }; 220 };
214 221
215 gpu_thermal: gpu-thermal { 222 gpu_thermal: gpu-thermal {
216 polling-delay-passive 223 polling-delay-passive = <100>; /* milliseconds */
217 polling-delay = <1000> 224 polling-delay = <1000>; /* milliseconds */
218 thermal-sensors = <&ts 225 thermal-sensors = <&tsadc 1>;
219 <<
220 trips { <<
221 gpu_threshold: <<
222 temper <<
223 hyster <<
224 type = <<
225 }; <<
226 <<
227 gpu_target: gp <<
228 temper <<
229 hyster <<
230 type = <<
231 }; <<
232 <<
233 gpu_crit: gpu- <<
234 temper <<
235 hyster <<
236 type = <<
237 }; <<
238 }; <<
239 <<
240 cooling-maps { <<
241 map0 { <<
242 trip = <<
243 coolin <<
244 }; <<
245 }; <<
246 }; 226 };
247 }; 227 };
248 228
249 xin24m: xin24m { 229 xin24m: xin24m {
250 compatible = "fixed-clock"; 230 compatible = "fixed-clock";
251 #clock-cells = <0>; 231 #clock-cells = <0>;
252 clock-frequency = <24000000>; 232 clock-frequency = <24000000>;
253 clock-output-names = "xin24m"; 233 clock-output-names = "xin24m";
254 }; 234 };
255 235
256 pmu: power-management@ff000000 { 236 pmu: power-management@ff000000 {
257 compatible = "rockchip,px30-pm 237 compatible = "rockchip,px30-pmu", "syscon", "simple-mfd";
258 reg = <0x0 0xff000000 0x0 0x10 238 reg = <0x0 0xff000000 0x0 0x1000>;
259 239
260 power: power-controller { 240 power: power-controller {
261 compatible = "rockchip 241 compatible = "rockchip,px30-power-controller";
262 #power-domain-cells = 242 #power-domain-cells = <1>;
263 #address-cells = <1>; 243 #address-cells = <1>;
264 #size-cells = <0>; 244 #size-cells = <0>;
265 245
266 /* These power domains 246 /* These power domains are grouped by VD_LOGIC */
267 power-domain@PX30_PD_U 247 power-domain@PX30_PD_USB {
268 reg = <PX30_PD 248 reg = <PX30_PD_USB>;
269 clocks = <&cru 249 clocks = <&cru HCLK_HOST>,
270 <&cru 250 <&cru HCLK_OTG>,
271 <&cru 251 <&cru SCLK_OTG_ADP>;
272 pm_qos = <&qos 252 pm_qos = <&qos_usb_host>, <&qos_usb_otg>;
273 #power-domain- <<
274 }; 253 };
275 power-domain@PX30_PD_S 254 power-domain@PX30_PD_SDCARD {
276 reg = <PX30_PD 255 reg = <PX30_PD_SDCARD>;
277 clocks = <&cru 256 clocks = <&cru HCLK_SDMMC>,
278 <&cru 257 <&cru SCLK_SDMMC>;
279 pm_qos = <&qos 258 pm_qos = <&qos_sdmmc>;
280 #power-domain- <<
281 }; 259 };
282 power-domain@PX30_PD_G 260 power-domain@PX30_PD_GMAC {
283 reg = <PX30_PD 261 reg = <PX30_PD_GMAC>;
284 clocks = <&cru 262 clocks = <&cru ACLK_GMAC>,
285 <&cru 263 <&cru PCLK_GMAC>,
286 <&cru 264 <&cru SCLK_MAC_REF>,
287 <&cru 265 <&cru SCLK_GMAC_RX_TX>;
288 pm_qos = <&qos 266 pm_qos = <&qos_gmac>;
289 #power-domain- <<
290 }; 267 };
291 power-domain@PX30_PD_M 268 power-domain@PX30_PD_MMC_NAND {
292 reg = <PX30_PD 269 reg = <PX30_PD_MMC_NAND>;
293 clocks = <&cru !! 270 clocks = <&cru HCLK_NANDC>,
294 <&cru !! 271 <&cru HCLK_EMMC>,
295 <&cru !! 272 <&cru HCLK_SDIO>,
296 <&cru !! 273 <&cru HCLK_SFC>,
297 <&cru !! 274 <&cru SCLK_EMMC>,
298 <&cru !! 275 <&cru SCLK_NANDC>,
299 <&cru !! 276 <&cru SCLK_SDIO>,
300 <&cru !! 277 <&cru SCLK_SFC>;
301 pm_qos = <&qos 278 pm_qos = <&qos_emmc>, <&qos_nand>,
302 <&qos 279 <&qos_sdio>, <&qos_sfc>;
303 #power-domain- <<
304 }; 280 };
305 power-domain@PX30_PD_V 281 power-domain@PX30_PD_VPU {
306 reg = <PX30_PD 282 reg = <PX30_PD_VPU>;
307 clocks = <&cru 283 clocks = <&cru ACLK_VPU>,
308 <&cru 284 <&cru HCLK_VPU>,
309 <&cru 285 <&cru SCLK_CORE_VPU>;
310 pm_qos = <&qos 286 pm_qos = <&qos_vpu>, <&qos_vpu_r128>;
311 #power-domain- <<
312 }; 287 };
313 power-domain@PX30_PD_V 288 power-domain@PX30_PD_VO {
314 reg = <PX30_PD 289 reg = <PX30_PD_VO>;
315 clocks = <&cru 290 clocks = <&cru ACLK_RGA>,
316 <&cru 291 <&cru ACLK_VOPB>,
317 <&cru 292 <&cru ACLK_VOPL>,
318 <&cru 293 <&cru DCLK_VOPB>,
319 <&cru 294 <&cru DCLK_VOPL>,
320 <&cru 295 <&cru HCLK_RGA>,
321 <&cru 296 <&cru HCLK_VOPB>,
322 <&cru 297 <&cru HCLK_VOPL>,
323 <&cru 298 <&cru PCLK_MIPI_DSI>,
324 <&cru 299 <&cru SCLK_RGA_CORE>,
325 <&cru 300 <&cru SCLK_VOPB_PWM>;
326 pm_qos = <&qos 301 pm_qos = <&qos_rga_rd>, <&qos_rga_wr>,
327 <&qos 302 <&qos_vop_m0>, <&qos_vop_m1>;
328 #power-domain- <<
329 }; 303 };
330 power-domain@PX30_PD_V 304 power-domain@PX30_PD_VI {
331 reg = <PX30_PD 305 reg = <PX30_PD_VI>;
332 clocks = <&cru 306 clocks = <&cru ACLK_CIF>,
333 <&cru 307 <&cru ACLK_ISP>,
334 <&cru 308 <&cru HCLK_CIF>,
335 <&cru 309 <&cru HCLK_ISP>,
336 <&cru 310 <&cru SCLK_ISP>;
337 pm_qos = <&qos 311 pm_qos = <&qos_isp_128>, <&qos_isp_rd>,
338 <&qos 312 <&qos_isp_wr>, <&qos_isp_m1>,
339 <&qos 313 <&qos_vip>;
340 #power-domain- <<
341 }; 314 };
342 power-domain@PX30_PD_G 315 power-domain@PX30_PD_GPU {
343 reg = <PX30_PD 316 reg = <PX30_PD_GPU>;
344 clocks = <&cru 317 clocks = <&cru SCLK_GPU>;
345 pm_qos = <&qos 318 pm_qos = <&qos_gpu>;
346 #power-domain- <<
347 }; 319 };
348 }; 320 };
349 }; 321 };
350 322
351 pmugrf: syscon@ff010000 { 323 pmugrf: syscon@ff010000 {
352 compatible = "rockchip,px30-pm 324 compatible = "rockchip,px30-pmugrf", "syscon", "simple-mfd";
353 reg = <0x0 0xff010000 0x0 0x10 325 reg = <0x0 0xff010000 0x0 0x1000>;
354 #address-cells = <1>; 326 #address-cells = <1>;
355 #size-cells = <1>; 327 #size-cells = <1>;
356 328
357 pmu_io_domains: io-domains { 329 pmu_io_domains: io-domains {
358 compatible = "rockchip 330 compatible = "rockchip,px30-pmu-io-voltage-domain";
359 status = "disabled"; 331 status = "disabled";
360 }; 332 };
361 333
362 reboot-mode { 334 reboot-mode {
363 compatible = "syscon-r 335 compatible = "syscon-reboot-mode";
364 offset = <0x200>; 336 offset = <0x200>;
365 mode-bootloader = <BOO 337 mode-bootloader = <BOOT_BL_DOWNLOAD>;
366 mode-fastboot = <BOOT_ 338 mode-fastboot = <BOOT_FASTBOOT>;
367 mode-loader = <BOOT_BL 339 mode-loader = <BOOT_BL_DOWNLOAD>;
368 mode-normal = <BOOT_NO 340 mode-normal = <BOOT_NORMAL>;
369 mode-recovery = <BOOT_ 341 mode-recovery = <BOOT_RECOVERY>;
370 }; 342 };
371 }; 343 };
372 344
373 uart0: serial@ff030000 { 345 uart0: serial@ff030000 {
374 compatible = "rockchip,px30-ua 346 compatible = "rockchip,px30-uart", "snps,dw-apb-uart";
375 reg = <0x0 0xff030000 0x0 0x10 347 reg = <0x0 0xff030000 0x0 0x100>;
376 interrupts = <GIC_SPI 15 IRQ_T 348 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
377 clocks = <&pmucru SCLK_UART0_P 349 clocks = <&pmucru SCLK_UART0_PMU>, <&pmucru PCLK_UART0_PMU>;
378 clock-names = "baudclk", "apb_ 350 clock-names = "baudclk", "apb_pclk";
379 dmas = <&dmac 0>, <&dmac 1>; 351 dmas = <&dmac 0>, <&dmac 1>;
380 dma-names = "tx", "rx"; 352 dma-names = "tx", "rx";
381 reg-shift = <2>; 353 reg-shift = <2>;
382 reg-io-width = <4>; 354 reg-io-width = <4>;
383 pinctrl-names = "default"; 355 pinctrl-names = "default";
384 pinctrl-0 = <&uart0_xfer &uart 356 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
385 status = "disabled"; 357 status = "disabled";
386 }; 358 };
387 359
388 i2s0_8ch: i2s@ff060000 { <<
389 compatible = "rockchip,px30-i2 <<
390 reg = <0x0 0xff060000 0x0 0x10 <<
391 interrupts = <GIC_SPI 12 IRQ_T <<
392 clocks = <&cru SCLK_I2S0_TX>, <<
393 clock-names = "mclk_tx", "mclk <<
394 dmas = <&dmac 16>, <&dmac 17>; <<
395 dma-names = "tx", "rx"; <<
396 rockchip,grf = <&grf>; <<
397 resets = <&cru SRST_I2S0_TX>, <<
398 reset-names = "tx-m", "rx-m"; <<
399 pinctrl-names = "default"; <<
400 pinctrl-0 = <&i2s0_8ch_sclktx <<
401 &i2s0_8ch_lrcktx <<
402 &i2s0_8ch_sdo0 &i <<
403 &i2s0_8ch_sdo1 &i <<
404 &i2s0_8ch_sdo2 &i <<
405 &i2s0_8ch_sdo3 &i <<
406 #sound-dai-cells = <0>; <<
407 status = "disabled"; <<
408 }; <<
409 <<
410 i2s1_2ch: i2s@ff070000 { 360 i2s1_2ch: i2s@ff070000 {
411 compatible = "rockchip,px30-i2 361 compatible = "rockchip,px30-i2s", "rockchip,rk3066-i2s";
412 reg = <0x0 0xff070000 0x0 0x10 362 reg = <0x0 0xff070000 0x0 0x1000>;
413 interrupts = <GIC_SPI 13 IRQ_T 363 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
414 clocks = <&cru SCLK_I2S1>, <&c 364 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1>;
415 clock-names = "i2s_clk", "i2s_ 365 clock-names = "i2s_clk", "i2s_hclk";
416 dmas = <&dmac 18>, <&dmac 19>; 366 dmas = <&dmac 18>, <&dmac 19>;
417 dma-names = "tx", "rx"; 367 dma-names = "tx", "rx";
418 pinctrl-names = "default"; 368 pinctrl-names = "default";
419 pinctrl-0 = <&i2s1_2ch_sclk &i 369 pinctrl-0 = <&i2s1_2ch_sclk &i2s1_2ch_lrck
420 &i2s1_2ch_sdi &i2 370 &i2s1_2ch_sdi &i2s1_2ch_sdo>;
421 #sound-dai-cells = <0>; 371 #sound-dai-cells = <0>;
422 status = "disabled"; 372 status = "disabled";
423 }; 373 };
424 374
425 i2s2_2ch: i2s@ff080000 { 375 i2s2_2ch: i2s@ff080000 {
426 compatible = "rockchip,px30-i2 376 compatible = "rockchip,px30-i2s", "rockchip,rk3066-i2s";
427 reg = <0x0 0xff080000 0x0 0x10 377 reg = <0x0 0xff080000 0x0 0x1000>;
428 interrupts = <GIC_SPI 14 IRQ_T 378 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
429 clocks = <&cru SCLK_I2S2>, <&c 379 clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2>;
430 clock-names = "i2s_clk", "i2s_ 380 clock-names = "i2s_clk", "i2s_hclk";
431 dmas = <&dmac 20>, <&dmac 21>; 381 dmas = <&dmac 20>, <&dmac 21>;
432 dma-names = "tx", "rx"; 382 dma-names = "tx", "rx";
433 pinctrl-names = "default"; 383 pinctrl-names = "default";
434 pinctrl-0 = <&i2s2_2ch_sclk &i 384 pinctrl-0 = <&i2s2_2ch_sclk &i2s2_2ch_lrck
435 &i2s2_2ch_sdi &i2 385 &i2s2_2ch_sdi &i2s2_2ch_sdo>;
436 #sound-dai-cells = <0>; 386 #sound-dai-cells = <0>;
437 status = "disabled"; 387 status = "disabled";
438 }; 388 };
439 389
440 gic: interrupt-controller@ff131000 { 390 gic: interrupt-controller@ff131000 {
441 compatible = "arm,gic-400"; 391 compatible = "arm,gic-400";
442 #interrupt-cells = <3>; 392 #interrupt-cells = <3>;
443 #address-cells = <0>; 393 #address-cells = <0>;
444 interrupt-controller; 394 interrupt-controller;
445 reg = <0x0 0xff131000 0 0x1000 395 reg = <0x0 0xff131000 0 0x1000>,
446 <0x0 0xff132000 0 0x2000 396 <0x0 0xff132000 0 0x2000>,
447 <0x0 0xff134000 0 0x2000 397 <0x0 0xff134000 0 0x2000>,
448 <0x0 0xff136000 0 0x2000 398 <0x0 0xff136000 0 0x2000>;
449 interrupts = <GIC_PPI 9 399 interrupts = <GIC_PPI 9
450 (GIC_CPU_MASK_SIMPLE(4) 400 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
451 }; 401 };
452 402
453 grf: syscon@ff140000 { 403 grf: syscon@ff140000 {
454 compatible = "rockchip,px30-gr 404 compatible = "rockchip,px30-grf", "syscon", "simple-mfd";
455 reg = <0x0 0xff140000 0x0 0x10 405 reg = <0x0 0xff140000 0x0 0x1000>;
456 #address-cells = <1>; 406 #address-cells = <1>;
457 #size-cells = <1>; 407 #size-cells = <1>;
458 408
459 io_domains: io-domains { 409 io_domains: io-domains {
460 compatible = "rockchip 410 compatible = "rockchip,px30-io-voltage-domain";
461 status = "disabled"; 411 status = "disabled";
462 }; 412 };
463 413
464 lvds: lvds { 414 lvds: lvds {
465 compatible = "rockchip 415 compatible = "rockchip,px30-lvds";
466 phys = <&dsi_dphy>; 416 phys = <&dsi_dphy>;
467 phy-names = "dphy"; 417 phy-names = "dphy";
468 rockchip,grf = <&grf>; 418 rockchip,grf = <&grf>;
469 rockchip,output = "lvd 419 rockchip,output = "lvds";
470 status = "disabled"; 420 status = "disabled";
471 421
472 ports { 422 ports {
473 #address-cells 423 #address-cells = <1>;
474 #size-cells = 424 #size-cells = <0>;
475 425
476 lvds_in: port@ !! 426 port@0 {
477 reg = 427 reg = <0>;
478 #addre 428 #address-cells = <1>;
479 #size- 429 #size-cells = <0>;
480 430
481 lvds_v 431 lvds_vopb_in: endpoint@0 {
482 432 reg = <0>;
483 433 remote-endpoint = <&vopb_out_lvds>;
484 }; 434 };
485 435
486 lvds_v 436 lvds_vopl_in: endpoint@1 {
487 437 reg = <1>;
488 438 remote-endpoint = <&vopl_out_lvds>;
489 }; 439 };
490 }; 440 };
491 <<
492 lvds_out: port <<
493 reg = <<
494 }; <<
495 }; 441 };
496 }; 442 };
497 }; 443 };
498 444
499 uart1: serial@ff158000 { 445 uart1: serial@ff158000 {
500 compatible = "rockchip,px30-ua 446 compatible = "rockchip,px30-uart", "snps,dw-apb-uart";
501 reg = <0x0 0xff158000 0x0 0x10 447 reg = <0x0 0xff158000 0x0 0x100>;
502 interrupts = <GIC_SPI 16 IRQ_T 448 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
503 clocks = <&cru SCLK_UART1>, <& 449 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
504 clock-names = "baudclk", "apb_ 450 clock-names = "baudclk", "apb_pclk";
505 dmas = <&dmac 2>, <&dmac 3>; 451 dmas = <&dmac 2>, <&dmac 3>;
506 dma-names = "tx", "rx"; 452 dma-names = "tx", "rx";
507 reg-shift = <2>; 453 reg-shift = <2>;
508 reg-io-width = <4>; 454 reg-io-width = <4>;
509 pinctrl-names = "default"; 455 pinctrl-names = "default";
510 pinctrl-0 = <&uart1_xfer &uart 456 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
511 status = "disabled"; 457 status = "disabled";
512 }; 458 };
513 459
514 uart2: serial@ff160000 { 460 uart2: serial@ff160000 {
515 compatible = "rockchip,px30-ua 461 compatible = "rockchip,px30-uart", "snps,dw-apb-uart";
516 reg = <0x0 0xff160000 0x0 0x10 462 reg = <0x0 0xff160000 0x0 0x100>;
517 interrupts = <GIC_SPI 17 IRQ_T 463 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
518 clocks = <&cru SCLK_UART2>, <& 464 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
519 clock-names = "baudclk", "apb_ 465 clock-names = "baudclk", "apb_pclk";
520 dmas = <&dmac 4>, <&dmac 5>; 466 dmas = <&dmac 4>, <&dmac 5>;
521 dma-names = "tx", "rx"; 467 dma-names = "tx", "rx";
522 reg-shift = <2>; 468 reg-shift = <2>;
523 reg-io-width = <4>; 469 reg-io-width = <4>;
524 pinctrl-names = "default"; 470 pinctrl-names = "default";
525 pinctrl-0 = <&uart2m0_xfer>; 471 pinctrl-0 = <&uart2m0_xfer>;
526 status = "disabled"; 472 status = "disabled";
527 }; 473 };
528 474
529 uart3: serial@ff168000 { 475 uart3: serial@ff168000 {
530 compatible = "rockchip,px30-ua 476 compatible = "rockchip,px30-uart", "snps,dw-apb-uart";
531 reg = <0x0 0xff168000 0x0 0x10 477 reg = <0x0 0xff168000 0x0 0x100>;
532 interrupts = <GIC_SPI 18 IRQ_T 478 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
533 clocks = <&cru SCLK_UART3>, <& 479 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
534 clock-names = "baudclk", "apb_ 480 clock-names = "baudclk", "apb_pclk";
535 dmas = <&dmac 6>, <&dmac 7>; 481 dmas = <&dmac 6>, <&dmac 7>;
536 dma-names = "tx", "rx"; 482 dma-names = "tx", "rx";
537 reg-shift = <2>; 483 reg-shift = <2>;
538 reg-io-width = <4>; 484 reg-io-width = <4>;
539 pinctrl-names = "default"; 485 pinctrl-names = "default";
540 pinctrl-0 = <&uart3m1_xfer &ua 486 pinctrl-0 = <&uart3m1_xfer &uart3m1_cts &uart3m1_rts>;
541 status = "disabled"; 487 status = "disabled";
542 }; 488 };
543 489
544 uart4: serial@ff170000 { 490 uart4: serial@ff170000 {
545 compatible = "rockchip,px30-ua 491 compatible = "rockchip,px30-uart", "snps,dw-apb-uart";
546 reg = <0x0 0xff170000 0x0 0x10 492 reg = <0x0 0xff170000 0x0 0x100>;
547 interrupts = <GIC_SPI 19 IRQ_T 493 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
548 clocks = <&cru SCLK_UART4>, <& 494 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
549 clock-names = "baudclk", "apb_ 495 clock-names = "baudclk", "apb_pclk";
550 dmas = <&dmac 8>, <&dmac 9>; 496 dmas = <&dmac 8>, <&dmac 9>;
551 dma-names = "tx", "rx"; 497 dma-names = "tx", "rx";
552 reg-shift = <2>; 498 reg-shift = <2>;
553 reg-io-width = <4>; 499 reg-io-width = <4>;
554 pinctrl-names = "default"; 500 pinctrl-names = "default";
555 pinctrl-0 = <&uart4_xfer &uart 501 pinctrl-0 = <&uart4_xfer &uart4_cts &uart4_rts>;
556 status = "disabled"; 502 status = "disabled";
557 }; 503 };
558 504
559 uart5: serial@ff178000 { 505 uart5: serial@ff178000 {
560 compatible = "rockchip,px30-ua 506 compatible = "rockchip,px30-uart", "snps,dw-apb-uart";
561 reg = <0x0 0xff178000 0x0 0x10 507 reg = <0x0 0xff178000 0x0 0x100>;
562 interrupts = <GIC_SPI 20 IRQ_T 508 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
563 clocks = <&cru SCLK_UART5>, <& 509 clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>;
564 clock-names = "baudclk", "apb_ 510 clock-names = "baudclk", "apb_pclk";
565 dmas = <&dmac 10>, <&dmac 11>; 511 dmas = <&dmac 10>, <&dmac 11>;
566 dma-names = "tx", "rx"; 512 dma-names = "tx", "rx";
567 reg-shift = <2>; 513 reg-shift = <2>;
568 reg-io-width = <4>; 514 reg-io-width = <4>;
569 pinctrl-names = "default"; 515 pinctrl-names = "default";
570 pinctrl-0 = <&uart5_xfer &uart 516 pinctrl-0 = <&uart5_xfer &uart5_cts &uart5_rts>;
571 status = "disabled"; 517 status = "disabled";
572 }; 518 };
573 519
574 i2c0: i2c@ff180000 { 520 i2c0: i2c@ff180000 {
575 compatible = "rockchip,px30-i2 521 compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c";
576 reg = <0x0 0xff180000 0x0 0x10 522 reg = <0x0 0xff180000 0x0 0x1000>;
577 clocks = <&cru SCLK_I2C0>, <&c !! 523 clocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>;
578 clock-names = "i2c", "pclk"; 524 clock-names = "i2c", "pclk";
579 interrupts = <GIC_SPI 7 IRQ_TY 525 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
580 pinctrl-names = "default"; 526 pinctrl-names = "default";
581 pinctrl-0 = <&i2c0_xfer>; 527 pinctrl-0 = <&i2c0_xfer>;
582 #address-cells = <1>; 528 #address-cells = <1>;
583 #size-cells = <0>; 529 #size-cells = <0>;
584 status = "disabled"; 530 status = "disabled";
585 }; 531 };
586 532
587 i2c1: i2c@ff190000 { 533 i2c1: i2c@ff190000 {
588 compatible = "rockchip,px30-i2 534 compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c";
589 reg = <0x0 0xff190000 0x0 0x10 535 reg = <0x0 0xff190000 0x0 0x1000>;
590 clocks = <&cru SCLK_I2C1>, <&c 536 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
591 clock-names = "i2c", "pclk"; 537 clock-names = "i2c", "pclk";
592 interrupts = <GIC_SPI 8 IRQ_TY 538 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
593 pinctrl-names = "default"; 539 pinctrl-names = "default";
594 pinctrl-0 = <&i2c1_xfer>; 540 pinctrl-0 = <&i2c1_xfer>;
595 #address-cells = <1>; 541 #address-cells = <1>;
596 #size-cells = <0>; 542 #size-cells = <0>;
597 status = "disabled"; 543 status = "disabled";
598 }; 544 };
599 545
600 i2c2: i2c@ff1a0000 { 546 i2c2: i2c@ff1a0000 {
601 compatible = "rockchip,px30-i2 547 compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c";
602 reg = <0x0 0xff1a0000 0x0 0x10 548 reg = <0x0 0xff1a0000 0x0 0x1000>;
603 clocks = <&cru SCLK_I2C2>, <&c 549 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
604 clock-names = "i2c", "pclk"; 550 clock-names = "i2c", "pclk";
605 interrupts = <GIC_SPI 9 IRQ_TY 551 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
606 pinctrl-names = "default"; 552 pinctrl-names = "default";
607 pinctrl-0 = <&i2c2_xfer>; 553 pinctrl-0 = <&i2c2_xfer>;
608 #address-cells = <1>; 554 #address-cells = <1>;
609 #size-cells = <0>; 555 #size-cells = <0>;
610 status = "disabled"; 556 status = "disabled";
611 }; 557 };
612 558
613 i2c3: i2c@ff1b0000 { 559 i2c3: i2c@ff1b0000 {
614 compatible = "rockchip,px30-i2 560 compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c";
615 reg = <0x0 0xff1b0000 0x0 0x10 561 reg = <0x0 0xff1b0000 0x0 0x1000>;
616 clocks = <&cru SCLK_I2C3>, <&c 562 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
617 clock-names = "i2c", "pclk"; 563 clock-names = "i2c", "pclk";
618 interrupts = <GIC_SPI 10 IRQ_T 564 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
619 pinctrl-names = "default"; 565 pinctrl-names = "default";
620 pinctrl-0 = <&i2c3_xfer>; 566 pinctrl-0 = <&i2c3_xfer>;
621 #address-cells = <1>; 567 #address-cells = <1>;
622 #size-cells = <0>; 568 #size-cells = <0>;
623 status = "disabled"; 569 status = "disabled";
624 }; 570 };
625 571
626 spi0: spi@ff1d0000 { 572 spi0: spi@ff1d0000 {
627 compatible = "rockchip,px30-sp 573 compatible = "rockchip,px30-spi", "rockchip,rk3066-spi";
628 reg = <0x0 0xff1d0000 0x0 0x10 574 reg = <0x0 0xff1d0000 0x0 0x1000>;
629 interrupts = <GIC_SPI 26 IRQ_T 575 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
630 clocks = <&cru SCLK_SPI0>, <&c 576 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
631 clock-names = "spiclk", "apb_p 577 clock-names = "spiclk", "apb_pclk";
632 dmas = <&dmac 12>, <&dmac 13>; 578 dmas = <&dmac 12>, <&dmac 13>;
633 dma-names = "tx", "rx"; 579 dma-names = "tx", "rx";
634 num-cs = <2>; <<
635 pinctrl-names = "default"; 580 pinctrl-names = "default";
636 pinctrl-0 = <&spi0_clk &spi0_c 581 pinctrl-0 = <&spi0_clk &spi0_csn &spi0_miso &spi0_mosi>;
637 #address-cells = <1>; 582 #address-cells = <1>;
638 #size-cells = <0>; 583 #size-cells = <0>;
639 status = "disabled"; 584 status = "disabled";
640 }; 585 };
641 586
642 spi1: spi@ff1d8000 { 587 spi1: spi@ff1d8000 {
643 compatible = "rockchip,px30-sp 588 compatible = "rockchip,px30-spi", "rockchip,rk3066-spi";
644 reg = <0x0 0xff1d8000 0x0 0x10 589 reg = <0x0 0xff1d8000 0x0 0x1000>;
645 interrupts = <GIC_SPI 27 IRQ_T 590 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
646 clocks = <&cru SCLK_SPI1>, <&c 591 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
647 clock-names = "spiclk", "apb_p 592 clock-names = "spiclk", "apb_pclk";
648 dmas = <&dmac 14>, <&dmac 15>; 593 dmas = <&dmac 14>, <&dmac 15>;
649 dma-names = "tx", "rx"; 594 dma-names = "tx", "rx";
650 num-cs = <2>; <<
651 pinctrl-names = "default"; 595 pinctrl-names = "default";
652 pinctrl-0 = <&spi1_clk &spi1_c 596 pinctrl-0 = <&spi1_clk &spi1_csn0 &spi1_csn1 &spi1_miso &spi1_mosi>;
653 #address-cells = <1>; 597 #address-cells = <1>;
654 #size-cells = <0>; 598 #size-cells = <0>;
655 status = "disabled"; 599 status = "disabled";
656 }; 600 };
657 601
658 wdt: watchdog@ff1e0000 { 602 wdt: watchdog@ff1e0000 {
659 compatible = "rockchip,px30-wd 603 compatible = "rockchip,px30-wdt", "snps,dw-wdt";
660 reg = <0x0 0xff1e0000 0x0 0x10 604 reg = <0x0 0xff1e0000 0x0 0x100>;
661 clocks = <&cru PCLK_WDT_NS>; 605 clocks = <&cru PCLK_WDT_NS>;
662 interrupts = <GIC_SPI 37 IRQ_T 606 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
663 status = "disabled"; 607 status = "disabled";
664 }; 608 };
665 609
666 pwm0: pwm@ff200000 { 610 pwm0: pwm@ff200000 {
667 compatible = "rockchip,px30-pw 611 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
668 reg = <0x0 0xff200000 0x0 0x10 612 reg = <0x0 0xff200000 0x0 0x10>;
669 clocks = <&cru SCLK_PWM0>, <&c 613 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
670 clock-names = "pwm", "pclk"; 614 clock-names = "pwm", "pclk";
671 pinctrl-names = "default"; 615 pinctrl-names = "default";
672 pinctrl-0 = <&pwm0_pin>; 616 pinctrl-0 = <&pwm0_pin>;
673 #pwm-cells = <3>; 617 #pwm-cells = <3>;
674 status = "disabled"; 618 status = "disabled";
675 }; 619 };
676 620
677 pwm1: pwm@ff200010 { 621 pwm1: pwm@ff200010 {
678 compatible = "rockchip,px30-pw 622 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
679 reg = <0x0 0xff200010 0x0 0x10 623 reg = <0x0 0xff200010 0x0 0x10>;
680 clocks = <&cru SCLK_PWM0>, <&c 624 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
681 clock-names = "pwm", "pclk"; 625 clock-names = "pwm", "pclk";
682 pinctrl-names = "default"; 626 pinctrl-names = "default";
683 pinctrl-0 = <&pwm1_pin>; 627 pinctrl-0 = <&pwm1_pin>;
684 #pwm-cells = <3>; 628 #pwm-cells = <3>;
685 status = "disabled"; 629 status = "disabled";
686 }; 630 };
687 631
688 pwm2: pwm@ff200020 { 632 pwm2: pwm@ff200020 {
689 compatible = "rockchip,px30-pw 633 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
690 reg = <0x0 0xff200020 0x0 0x10 634 reg = <0x0 0xff200020 0x0 0x10>;
691 clocks = <&cru SCLK_PWM0>, <&c 635 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
692 clock-names = "pwm", "pclk"; 636 clock-names = "pwm", "pclk";
693 pinctrl-names = "default"; 637 pinctrl-names = "default";
694 pinctrl-0 = <&pwm2_pin>; 638 pinctrl-0 = <&pwm2_pin>;
695 #pwm-cells = <3>; 639 #pwm-cells = <3>;
696 status = "disabled"; 640 status = "disabled";
697 }; 641 };
698 642
699 pwm3: pwm@ff200030 { 643 pwm3: pwm@ff200030 {
700 compatible = "rockchip,px30-pw 644 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
701 reg = <0x0 0xff200030 0x0 0x10 645 reg = <0x0 0xff200030 0x0 0x10>;
702 clocks = <&cru SCLK_PWM0>, <&c 646 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
703 clock-names = "pwm", "pclk"; 647 clock-names = "pwm", "pclk";
704 pinctrl-names = "default"; 648 pinctrl-names = "default";
705 pinctrl-0 = <&pwm3_pin>; 649 pinctrl-0 = <&pwm3_pin>;
706 #pwm-cells = <3>; 650 #pwm-cells = <3>;
707 status = "disabled"; 651 status = "disabled";
708 }; 652 };
709 653
710 pwm4: pwm@ff208000 { 654 pwm4: pwm@ff208000 {
711 compatible = "rockchip,px30-pw 655 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
712 reg = <0x0 0xff208000 0x0 0x10 656 reg = <0x0 0xff208000 0x0 0x10>;
713 clocks = <&cru SCLK_PWM1>, <&c 657 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>;
714 clock-names = "pwm", "pclk"; 658 clock-names = "pwm", "pclk";
715 pinctrl-names = "default"; 659 pinctrl-names = "default";
716 pinctrl-0 = <&pwm4_pin>; 660 pinctrl-0 = <&pwm4_pin>;
717 #pwm-cells = <3>; 661 #pwm-cells = <3>;
718 status = "disabled"; 662 status = "disabled";
719 }; 663 };
720 664
721 pwm5: pwm@ff208010 { 665 pwm5: pwm@ff208010 {
722 compatible = "rockchip,px30-pw 666 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
723 reg = <0x0 0xff208010 0x0 0x10 667 reg = <0x0 0xff208010 0x0 0x10>;
724 clocks = <&cru SCLK_PWM1>, <&c 668 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>;
725 clock-names = "pwm", "pclk"; 669 clock-names = "pwm", "pclk";
726 pinctrl-names = "default"; 670 pinctrl-names = "default";
727 pinctrl-0 = <&pwm5_pin>; 671 pinctrl-0 = <&pwm5_pin>;
728 #pwm-cells = <3>; 672 #pwm-cells = <3>;
729 status = "disabled"; 673 status = "disabled";
730 }; 674 };
731 675
732 pwm6: pwm@ff208020 { 676 pwm6: pwm@ff208020 {
733 compatible = "rockchip,px30-pw 677 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
734 reg = <0x0 0xff208020 0x0 0x10 678 reg = <0x0 0xff208020 0x0 0x10>;
735 clocks = <&cru SCLK_PWM1>, <&c 679 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>;
736 clock-names = "pwm", "pclk"; 680 clock-names = "pwm", "pclk";
737 pinctrl-names = "default"; 681 pinctrl-names = "default";
738 pinctrl-0 = <&pwm6_pin>; 682 pinctrl-0 = <&pwm6_pin>;
739 #pwm-cells = <3>; 683 #pwm-cells = <3>;
740 status = "disabled"; 684 status = "disabled";
741 }; 685 };
742 686
743 pwm7: pwm@ff208030 { 687 pwm7: pwm@ff208030 {
744 compatible = "rockchip,px30-pw 688 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
745 reg = <0x0 0xff208030 0x0 0x10 689 reg = <0x0 0xff208030 0x0 0x10>;
746 clocks = <&cru SCLK_PWM1>, <&c 690 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>;
747 clock-names = "pwm", "pclk"; 691 clock-names = "pwm", "pclk";
748 pinctrl-names = "default"; 692 pinctrl-names = "default";
749 pinctrl-0 = <&pwm7_pin>; 693 pinctrl-0 = <&pwm7_pin>;
750 #pwm-cells = <3>; 694 #pwm-cells = <3>;
751 status = "disabled"; 695 status = "disabled";
752 }; 696 };
753 697
754 rktimer: timer@ff210000 { 698 rktimer: timer@ff210000 {
755 compatible = "rockchip,px30-ti 699 compatible = "rockchip,px30-timer", "rockchip,rk3288-timer";
756 reg = <0x0 0xff210000 0x0 0x10 700 reg = <0x0 0xff210000 0x0 0x1000>;
757 interrupts = <GIC_SPI 30 IRQ_T 701 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
758 clocks = <&cru PCLK_TIMER>, <& 702 clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER0>;
759 clock-names = "pclk", "timer"; 703 clock-names = "pclk", "timer";
760 }; 704 };
761 705
762 dmac: dma-controller@ff240000 { !! 706 dmac: dmac@ff240000 {
763 compatible = "arm,pl330", "arm 707 compatible = "arm,pl330", "arm,primecell";
764 reg = <0x0 0xff240000 0x0 0x40 708 reg = <0x0 0xff240000 0x0 0x4000>;
765 interrupts = <GIC_SPI 1 IRQ_TY 709 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
766 <GIC_SPI 2 IRQ_TY 710 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
767 arm,pl330-periph-burst; 711 arm,pl330-periph-burst;
768 clocks = <&cru ACLK_DMAC>; 712 clocks = <&cru ACLK_DMAC>;
769 clock-names = "apb_pclk"; 713 clock-names = "apb_pclk";
770 #dma-cells = <1>; 714 #dma-cells = <1>;
771 }; 715 };
772 716
773 tsadc: tsadc@ff280000 { 717 tsadc: tsadc@ff280000 {
774 compatible = "rockchip,px30-ts 718 compatible = "rockchip,px30-tsadc";
775 reg = <0x0 0xff280000 0x0 0x10 719 reg = <0x0 0xff280000 0x0 0x100>;
776 interrupts = <GIC_SPI 36 IRQ_T 720 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
777 assigned-clocks = <&cru SCLK_T 721 assigned-clocks = <&cru SCLK_TSADC>;
778 assigned-clock-rates = <50000> 722 assigned-clock-rates = <50000>;
779 clocks = <&cru SCLK_TSADC>, <& 723 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
780 clock-names = "tsadc", "apb_pc 724 clock-names = "tsadc", "apb_pclk";
781 resets = <&cru SRST_TSADC>; 725 resets = <&cru SRST_TSADC>;
782 reset-names = "tsadc-apb"; 726 reset-names = "tsadc-apb";
783 rockchip,grf = <&grf>; 727 rockchip,grf = <&grf>;
784 rockchip,hw-tshut-temp = <1200 728 rockchip,hw-tshut-temp = <120000>;
785 pinctrl-names = "init", "defau 729 pinctrl-names = "init", "default", "sleep";
786 pinctrl-0 = <&tsadc_otp_pin>; 730 pinctrl-0 = <&tsadc_otp_pin>;
787 pinctrl-1 = <&tsadc_otp_out>; 731 pinctrl-1 = <&tsadc_otp_out>;
788 pinctrl-2 = <&tsadc_otp_pin>; 732 pinctrl-2 = <&tsadc_otp_pin>;
789 #thermal-sensor-cells = <1>; 733 #thermal-sensor-cells = <1>;
790 status = "disabled"; 734 status = "disabled";
791 }; 735 };
792 736
793 saradc: saradc@ff288000 { 737 saradc: saradc@ff288000 {
794 compatible = "rockchip,px30-sa 738 compatible = "rockchip,px30-saradc", "rockchip,rk3399-saradc";
795 reg = <0x0 0xff288000 0x0 0x10 739 reg = <0x0 0xff288000 0x0 0x100>;
796 interrupts = <GIC_SPI 84 IRQ_T 740 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
797 #io-channel-cells = <1>; 741 #io-channel-cells = <1>;
798 clocks = <&cru SCLK_SARADC>, < 742 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
799 clock-names = "saradc", "apb_p 743 clock-names = "saradc", "apb_pclk";
800 resets = <&cru SRST_SARADC_P>; 744 resets = <&cru SRST_SARADC_P>;
801 reset-names = "saradc-apb"; 745 reset-names = "saradc-apb";
802 status = "disabled"; 746 status = "disabled";
803 }; 747 };
804 748
805 otp: nvmem@ff290000 { 749 otp: nvmem@ff290000 {
806 compatible = "rockchip,px30-ot 750 compatible = "rockchip,px30-otp";
807 reg = <0x0 0xff290000 0x0 0x40 751 reg = <0x0 0xff290000 0x0 0x4000>;
808 clocks = <&cru SCLK_OTP_USR>, 752 clocks = <&cru SCLK_OTP_USR>, <&cru PCLK_OTP_NS>,
809 <&cru PCLK_OTP_PHY>; 753 <&cru PCLK_OTP_PHY>;
810 clock-names = "otp", "apb_pclk 754 clock-names = "otp", "apb_pclk", "phy";
811 resets = <&cru SRST_OTP_PHY>; 755 resets = <&cru SRST_OTP_PHY>;
812 reset-names = "phy"; 756 reset-names = "phy";
813 #address-cells = <1>; 757 #address-cells = <1>;
814 #size-cells = <1>; 758 #size-cells = <1>;
815 759
816 /* Data cells */ 760 /* Data cells */
817 cpu_id: id@7 { 761 cpu_id: id@7 {
818 reg = <0x07 0x10>; 762 reg = <0x07 0x10>;
819 }; 763 };
820 cpu_leakage: cpu-leakage@17 { 764 cpu_leakage: cpu-leakage@17 {
821 reg = <0x17 0x1>; 765 reg = <0x17 0x1>;
822 }; 766 };
823 performance: performance@1e { 767 performance: performance@1e {
824 reg = <0x1e 0x1>; 768 reg = <0x1e 0x1>;
825 bits = <4 3>; 769 bits = <4 3>;
826 }; 770 };
827 }; 771 };
828 772
829 cru: clock-controller@ff2b0000 { 773 cru: clock-controller@ff2b0000 {
830 compatible = "rockchip,px30-cr 774 compatible = "rockchip,px30-cru";
831 reg = <0x0 0xff2b0000 0x0 0x10 775 reg = <0x0 0xff2b0000 0x0 0x1000>;
832 clocks = <&xin24m>, <&pmucru P 776 clocks = <&xin24m>, <&pmucru PLL_GPLL>;
833 clock-names = "xin24m", "gpll" 777 clock-names = "xin24m", "gpll";
834 rockchip,grf = <&grf>; 778 rockchip,grf = <&grf>;
835 #clock-cells = <1>; 779 #clock-cells = <1>;
836 #reset-cells = <1>; 780 #reset-cells = <1>;
837 781
838 assigned-clocks = <&cru PLL_NP 782 assigned-clocks = <&cru PLL_NPLL>,
839 <&cru ACLK_BUS_PRE>, < 783 <&cru ACLK_BUS_PRE>, <&cru ACLK_PERI_PRE>,
840 <&cru HCLK_BUS_PRE>, < 784 <&cru HCLK_BUS_PRE>, <&cru HCLK_PERI_PRE>,
841 <&cru PCLK_BUS_PRE>, < 785 <&cru PCLK_BUS_PRE>, <&cru SCLK_GPU>;
842 786
843 assigned-clock-rates = <118800 787 assigned-clock-rates = <1188000000>,
844 <200000000>, <20000000 788 <200000000>, <200000000>,
845 <150000000>, <15000000 789 <150000000>, <150000000>,
846 <100000000>, <20000000 790 <100000000>, <200000000>;
847 }; 791 };
848 792
849 pmucru: clock-controller@ff2bc000 { 793 pmucru: clock-controller@ff2bc000 {
850 compatible = "rockchip,px30-pm 794 compatible = "rockchip,px30-pmucru";
851 reg = <0x0 0xff2bc000 0x0 0x10 795 reg = <0x0 0xff2bc000 0x0 0x1000>;
852 clocks = <&xin24m>; 796 clocks = <&xin24m>;
853 clock-names = "xin24m"; 797 clock-names = "xin24m";
854 rockchip,grf = <&grf>; 798 rockchip,grf = <&grf>;
855 #clock-cells = <1>; 799 #clock-cells = <1>;
856 #reset-cells = <1>; 800 #reset-cells = <1>;
857 801
858 assigned-clocks = 802 assigned-clocks =
859 <&pmucru PLL_GPLL>, <& 803 <&pmucru PLL_GPLL>, <&pmucru PCLK_PMU_PRE>,
860 <&pmucru SCLK_WIFI_PMU 804 <&pmucru SCLK_WIFI_PMU>;
861 assigned-clock-rates = 805 assigned-clock-rates =
862 <1200000000>, <1000000 806 <1200000000>, <100000000>,
863 <26000000>; 807 <26000000>;
864 }; 808 };
865 809
866 usb2phy_grf: syscon@ff2c0000 { 810 usb2phy_grf: syscon@ff2c0000 {
867 compatible = "rockchip,px30-us 811 compatible = "rockchip,px30-usb2phy-grf", "syscon",
868 "simple-mfd"; 812 "simple-mfd";
869 reg = <0x0 0xff2c0000 0x0 0x10 813 reg = <0x0 0xff2c0000 0x0 0x10000>;
870 #address-cells = <1>; 814 #address-cells = <1>;
871 #size-cells = <1>; 815 #size-cells = <1>;
872 816
873 u2phy: usb2phy@100 { !! 817 u2phy: usb2-phy@100 {
874 compatible = "rockchip 818 compatible = "rockchip,px30-usb2phy";
875 reg = <0x100 0x20>; 819 reg = <0x100 0x20>;
876 clocks = <&pmucru SCLK 820 clocks = <&pmucru SCLK_USBPHY_REF>;
877 clock-names = "phyclk" 821 clock-names = "phyclk";
878 #clock-cells = <0>; 822 #clock-cells = <0>;
879 assigned-clocks = <&cr 823 assigned-clocks = <&cru USB480M>;
880 assigned-clock-parents 824 assigned-clock-parents = <&u2phy>;
881 clock-output-names = " 825 clock-output-names = "usb480m_phy";
882 status = "disabled"; 826 status = "disabled";
883 827
884 u2phy_host: host-port 828 u2phy_host: host-port {
885 #phy-cells = < 829 #phy-cells = <0>;
886 interrupts = < 830 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
887 interrupt-name 831 interrupt-names = "linestate";
888 status = "disa 832 status = "disabled";
889 }; 833 };
890 834
891 u2phy_otg: otg-port { 835 u2phy_otg: otg-port {
892 #phy-cells = < 836 #phy-cells = <0>;
893 interrupts = < 837 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
894 < 838 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
895 < 839 <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
896 interrupt-name 840 interrupt-names = "otg-bvalid", "otg-id",
897 841 "linestate";
898 status = "disa 842 status = "disabled";
899 }; 843 };
900 }; 844 };
901 }; 845 };
902 846
903 dsi_dphy: phy@ff2e0000 { 847 dsi_dphy: phy@ff2e0000 {
904 compatible = "rockchip,px30-ds 848 compatible = "rockchip,px30-dsi-dphy";
905 reg = <0x0 0xff2e0000 0x0 0x10 849 reg = <0x0 0xff2e0000 0x0 0x10000>;
906 clocks = <&pmucru SCLK_MIPIDSI 850 clocks = <&pmucru SCLK_MIPIDSIPHY_REF>, <&cru PCLK_MIPIDSIPHY>;
907 clock-names = "ref", "pclk"; 851 clock-names = "ref", "pclk";
908 resets = <&cru SRST_MIPIDSIPHY 852 resets = <&cru SRST_MIPIDSIPHY_P>;
909 reset-names = "apb"; 853 reset-names = "apb";
910 #phy-cells = <0>; 854 #phy-cells = <0>;
911 power-domains = <&power PX30_P 855 power-domains = <&power PX30_PD_VO>;
912 status = "disabled"; 856 status = "disabled";
913 }; 857 };
914 858
915 csi_dphy: phy@ff2f0000 { <<
916 compatible = "rockchip,px30-cs <<
917 reg = <0x0 0xff2f0000 0x0 0x40 <<
918 clocks = <&cru PCLK_MIPICSIPHY <<
919 clock-names = "pclk"; <<
920 #phy-cells = <0>; <<
921 power-domains = <&power PX30_P <<
922 resets = <&cru SRST_MIPICSIPHY <<
923 reset-names = "apb"; <<
924 rockchip,grf = <&grf>; <<
925 status = "disabled"; <<
926 }; <<
927 <<
928 usb20_otg: usb@ff300000 { 859 usb20_otg: usb@ff300000 {
929 compatible = "rockchip,px30-us 860 compatible = "rockchip,px30-usb", "rockchip,rk3066-usb",
930 "snps,dwc2"; 861 "snps,dwc2";
931 reg = <0x0 0xff300000 0x0 0x40 862 reg = <0x0 0xff300000 0x0 0x40000>;
932 interrupts = <GIC_SPI 62 IRQ_T 863 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
933 clocks = <&cru HCLK_OTG>; 864 clocks = <&cru HCLK_OTG>;
934 clock-names = "otg"; 865 clock-names = "otg";
935 dr_mode = "otg"; 866 dr_mode = "otg";
936 g-np-tx-fifo-size = <16>; 867 g-np-tx-fifo-size = <16>;
937 g-rx-fifo-size = <280>; 868 g-rx-fifo-size = <280>;
938 g-tx-fifo-size = <256 128 128 869 g-tx-fifo-size = <256 128 128 64 32 16>;
939 phys = <&u2phy_otg>; 870 phys = <&u2phy_otg>;
940 phy-names = "usb2-phy"; 871 phy-names = "usb2-phy";
941 power-domains = <&power PX30_P 872 power-domains = <&power PX30_PD_USB>;
942 status = "disabled"; 873 status = "disabled";
943 }; 874 };
944 875
945 usb_host0_ehci: usb@ff340000 { 876 usb_host0_ehci: usb@ff340000 {
946 compatible = "generic-ehci"; 877 compatible = "generic-ehci";
947 reg = <0x0 0xff340000 0x0 0x10 878 reg = <0x0 0xff340000 0x0 0x10000>;
948 interrupts = <GIC_SPI 60 IRQ_T 879 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
949 clocks = <&cru HCLK_HOST>; 880 clocks = <&cru HCLK_HOST>;
950 phys = <&u2phy_host>; 881 phys = <&u2phy_host>;
951 phy-names = "usb"; 882 phy-names = "usb";
952 power-domains = <&power PX30_P 883 power-domains = <&power PX30_PD_USB>;
953 status = "disabled"; 884 status = "disabled";
954 }; 885 };
955 886
956 usb_host0_ohci: usb@ff350000 { 887 usb_host0_ohci: usb@ff350000 {
957 compatible = "generic-ohci"; 888 compatible = "generic-ohci";
958 reg = <0x0 0xff350000 0x0 0x10 889 reg = <0x0 0xff350000 0x0 0x10000>;
959 interrupts = <GIC_SPI 61 IRQ_T 890 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
960 clocks = <&cru HCLK_HOST>; 891 clocks = <&cru HCLK_HOST>;
961 phys = <&u2phy_host>; 892 phys = <&u2phy_host>;
962 phy-names = "usb"; 893 phy-names = "usb";
963 power-domains = <&power PX30_P 894 power-domains = <&power PX30_PD_USB>;
964 status = "disabled"; 895 status = "disabled";
965 }; 896 };
966 897
967 gmac: ethernet@ff360000 { 898 gmac: ethernet@ff360000 {
968 compatible = "rockchip,px30-gm 899 compatible = "rockchip,px30-gmac";
969 reg = <0x0 0xff360000 0x0 0x10 900 reg = <0x0 0xff360000 0x0 0x10000>;
970 interrupts = <GIC_SPI 43 IRQ_T 901 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
971 interrupt-names = "macirq"; 902 interrupt-names = "macirq";
972 clocks = <&cru SCLK_GMAC>, <&c 903 clocks = <&cru SCLK_GMAC>, <&cru SCLK_GMAC_RX_TX>,
973 <&cru SCLK_GMAC_RX_TX 904 <&cru SCLK_GMAC_RX_TX>, <&cru SCLK_MAC_REF>,
974 <&cru SCLK_MAC_REFOUT 905 <&cru SCLK_MAC_REFOUT>, <&cru ACLK_GMAC>,
975 <&cru PCLK_GMAC>, <&c 906 <&cru PCLK_GMAC>, <&cru SCLK_GMAC_RMII>;
976 clock-names = "stmmaceth", "ma 907 clock-names = "stmmaceth", "mac_clk_rx",
977 "mac_clk_tx", "c 908 "mac_clk_tx", "clk_mac_ref",
978 "clk_mac_refout" 909 "clk_mac_refout", "aclk_mac",
979 "pclk_mac", "clk 910 "pclk_mac", "clk_mac_speed";
980 rockchip,grf = <&grf>; 911 rockchip,grf = <&grf>;
981 phy-mode = "rmii"; 912 phy-mode = "rmii";
982 pinctrl-names = "default"; 913 pinctrl-names = "default";
983 pinctrl-0 = <&rmii_pins &mac_r 914 pinctrl-0 = <&rmii_pins &mac_refclk_12ma>;
984 power-domains = <&power PX30_P 915 power-domains = <&power PX30_PD_GMAC>;
985 resets = <&cru SRST_GMAC_A>; 916 resets = <&cru SRST_GMAC_A>;
986 reset-names = "stmmaceth"; 917 reset-names = "stmmaceth";
987 status = "disabled"; 918 status = "disabled";
988 }; 919 };
989 920
990 sdmmc: mmc@ff370000 { 921 sdmmc: mmc@ff370000 {
991 compatible = "rockchip,px30-dw 922 compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc";
992 reg = <0x0 0xff370000 0x0 0x40 923 reg = <0x0 0xff370000 0x0 0x4000>;
993 interrupts = <GIC_SPI 54 IRQ_T 924 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
994 clocks = <&cru HCLK_SDMMC>, <& 925 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
995 <&cru SCLK_SDMMC_DRV> 926 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
996 clock-names = "biu", "ciu", "c 927 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
997 bus-width = <4>; 928 bus-width = <4>;
998 fifo-depth = <0x100>; 929 fifo-depth = <0x100>;
999 max-frequency = <150000000>; 930 max-frequency = <150000000>;
1000 pinctrl-names = "default"; 931 pinctrl-names = "default";
1001 pinctrl-0 = <&sdmmc_clk &sdmm 932 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_det &sdmmc_bus4>;
1002 power-domains = <&power PX30_ 933 power-domains = <&power PX30_PD_SDCARD>;
1003 status = "disabled"; 934 status = "disabled";
1004 }; 935 };
1005 936
1006 sdio: mmc@ff380000 { 937 sdio: mmc@ff380000 {
1007 compatible = "rockchip,px30-d 938 compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc";
1008 reg = <0x0 0xff380000 0x0 0x4 939 reg = <0x0 0xff380000 0x0 0x4000>;
1009 interrupts = <GIC_SPI 55 IRQ_ 940 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
1010 clocks = <&cru HCLK_SDIO>, <& 941 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
1011 <&cru SCLK_SDIO_DRV> 942 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
1012 clock-names = "biu", "ciu", " 943 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
1013 bus-width = <4>; 944 bus-width = <4>;
1014 fifo-depth = <0x100>; 945 fifo-depth = <0x100>;
1015 max-frequency = <150000000>; 946 max-frequency = <150000000>;
1016 pinctrl-names = "default"; 947 pinctrl-names = "default";
1017 pinctrl-0 = <&sdio_bus4 &sdio 948 pinctrl-0 = <&sdio_bus4 &sdio_cmd &sdio_clk>;
1018 power-domains = <&power PX30_ 949 power-domains = <&power PX30_PD_MMC_NAND>;
1019 status = "disabled"; 950 status = "disabled";
1020 }; 951 };
1021 952
1022 emmc: mmc@ff390000 { 953 emmc: mmc@ff390000 {
1023 compatible = "rockchip,px30-d 954 compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc";
1024 reg = <0x0 0xff390000 0x0 0x4 955 reg = <0x0 0xff390000 0x0 0x4000>;
1025 interrupts = <GIC_SPI 53 IRQ_ 956 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
1026 clocks = <&cru HCLK_EMMC>, <& 957 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
1027 <&cru SCLK_EMMC_DRV> 958 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
1028 clock-names = "biu", "ciu", " 959 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
1029 bus-width = <8>; 960 bus-width = <8>;
1030 fifo-depth = <0x100>; 961 fifo-depth = <0x100>;
1031 max-frequency = <150000000>; 962 max-frequency = <150000000>;
1032 pinctrl-names = "default"; 963 pinctrl-names = "default";
1033 pinctrl-0 = <&emmc_clk &emmc_ 964 pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
1034 power-domains = <&power PX30_ 965 power-domains = <&power PX30_PD_MMC_NAND>;
1035 status = "disabled"; 966 status = "disabled";
1036 }; 967 };
1037 968
1038 sfc: spi@ff3a0000 { <<
1039 compatible = "rockchip,sfc"; <<
1040 reg = <0x0 0xff3a0000 0x0 0x4 <<
1041 interrupts = <GIC_SPI 56 IRQ_ <<
1042 clocks = <&cru SCLK_SFC>, <&c <<
1043 clock-names = "clk_sfc", "hcl <<
1044 pinctrl-0 = <&sfc_clk &sfc_cs <<
1045 pinctrl-names = "default"; <<
1046 power-domains = <&power PX30_ <<
1047 status = "disabled"; <<
1048 }; <<
1049 <<
1050 nfc: nand-controller@ff3b0000 { 969 nfc: nand-controller@ff3b0000 {
1051 compatible = "rockchip,px30-n 970 compatible = "rockchip,px30-nfc";
1052 reg = <0x0 0xff3b0000 0x0 0x4 971 reg = <0x0 0xff3b0000 0x0 0x4000>;
1053 interrupts = <GIC_SPI 57 IRQ_ 972 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
1054 clocks = <&cru HCLK_NANDC>, < 973 clocks = <&cru HCLK_NANDC>, <&cru SCLK_NANDC>;
1055 clock-names = "ahb", "nfc"; 974 clock-names = "ahb", "nfc";
1056 assigned-clocks = <&cru SCLK_ 975 assigned-clocks = <&cru SCLK_NANDC>;
1057 assigned-clock-rates = <15000 976 assigned-clock-rates = <150000000>;
1058 pinctrl-names = "default"; 977 pinctrl-names = "default";
1059 pinctrl-0 = <&flash_ale &flas 978 pinctrl-0 = <&flash_ale &flash_bus8 &flash_cle &flash_cs0
1060 &flash_rdn &flas 979 &flash_rdn &flash_rdy &flash_wrn &flash_dqs>;
1061 power-domains = <&power PX30_ 980 power-domains = <&power PX30_PD_MMC_NAND>;
1062 status = "disabled"; 981 status = "disabled";
1063 }; 982 };
1064 983
1065 gpu_opp_table: opp-table-1 { !! 984 gpu_opp_table: opp-table2 {
1066 compatible = "operating-point 985 compatible = "operating-points-v2";
1067 986
1068 opp-200000000 { 987 opp-200000000 {
1069 opp-hz = /bits/ 64 <2 988 opp-hz = /bits/ 64 <200000000>;
1070 opp-microvolt = <9500 989 opp-microvolt = <950000>;
1071 }; 990 };
1072 opp-300000000 { 991 opp-300000000 {
1073 opp-hz = /bits/ 64 <3 992 opp-hz = /bits/ 64 <300000000>;
1074 opp-microvolt = <9750 993 opp-microvolt = <975000>;
1075 }; 994 };
1076 opp-400000000 { 995 opp-400000000 {
1077 opp-hz = /bits/ 64 <4 996 opp-hz = /bits/ 64 <400000000>;
1078 opp-microvolt = <1050 997 opp-microvolt = <1050000>;
1079 }; 998 };
1080 opp-480000000 { 999 opp-480000000 {
1081 opp-hz = /bits/ 64 <4 1000 opp-hz = /bits/ 64 <480000000>;
1082 opp-microvolt = <1125 1001 opp-microvolt = <1125000>;
1083 }; 1002 };
1084 }; 1003 };
1085 1004
1086 gpu: gpu@ff400000 { 1005 gpu: gpu@ff400000 {
1087 compatible = "rockchip,px30-m 1006 compatible = "rockchip,px30-mali", "arm,mali-bifrost";
1088 reg = <0x0 0xff400000 0x0 0x4 1007 reg = <0x0 0xff400000 0x0 0x4000>;
1089 interrupts = <GIC_SPI 47 IRQ_ 1008 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
1090 <GIC_SPI 46 IRQ_ 1009 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
1091 <GIC_SPI 45 IRQ_ 1010 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
1092 interrupt-names = "job", "mmu 1011 interrupt-names = "job", "mmu", "gpu";
1093 clocks = <&cru SCLK_GPU>; 1012 clocks = <&cru SCLK_GPU>;
1094 #cooling-cells = <2>; 1013 #cooling-cells = <2>;
1095 power-domains = <&power PX30_ 1014 power-domains = <&power PX30_PD_GPU>;
1096 operating-points-v2 = <&gpu_o 1015 operating-points-v2 = <&gpu_opp_table>;
1097 status = "disabled"; 1016 status = "disabled";
1098 }; 1017 };
1099 1018
1100 vpu: video-codec@ff442000 { <<
1101 compatible = "rockchip,px30-v <<
1102 reg = <0x0 0xff442000 0x0 0x8 <<
1103 interrupts = <GIC_SPI 80 IRQ_ <<
1104 <GIC_SPI 79 IRQ_ <<
1105 interrupt-names = "vepu", "vd <<
1106 clocks = <&cru ACLK_VPU>, <&c <<
1107 clock-names = "aclk", "hclk"; <<
1108 iommus = <&vpu_mmu>; <<
1109 power-domains = <&power PX30_ <<
1110 }; <<
1111 <<
1112 vpu_mmu: iommu@ff442800 { <<
1113 compatible = "rockchip,iommu" <<
1114 reg = <0x0 0xff442800 0x0 0x1 <<
1115 interrupts = <GIC_SPI 81 IRQ_ <<
1116 clocks = <&cru ACLK_VPU>, <&c <<
1117 clock-names = "aclk", "iface" <<
1118 #iommu-cells = <0>; <<
1119 power-domains = <&power PX30_ <<
1120 }; <<
1121 <<
1122 dsi: dsi@ff450000 { 1019 dsi: dsi@ff450000 {
1123 compatible = "rockchip,px30-m !! 1020 compatible = "rockchip,px30-mipi-dsi";
1124 reg = <0x0 0xff450000 0x0 0x1 1021 reg = <0x0 0xff450000 0x0 0x10000>;
1125 interrupts = <GIC_SPI 75 IRQ_ 1022 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
1126 clocks = <&cru PCLK_MIPI_DSI> 1023 clocks = <&cru PCLK_MIPI_DSI>;
1127 clock-names = "pclk"; 1024 clock-names = "pclk";
1128 phys = <&dsi_dphy>; 1025 phys = <&dsi_dphy>;
1129 phy-names = "dphy"; 1026 phy-names = "dphy";
1130 power-domains = <&power PX30_ 1027 power-domains = <&power PX30_PD_VO>;
1131 resets = <&cru SRST_MIPIDSI_H 1028 resets = <&cru SRST_MIPIDSI_HOST_P>;
1132 reset-names = "apb"; 1029 reset-names = "apb";
1133 rockchip,grf = <&grf>; 1030 rockchip,grf = <&grf>;
1134 #address-cells = <1>; 1031 #address-cells = <1>;
1135 #size-cells = <0>; 1032 #size-cells = <0>;
1136 status = "disabled"; 1033 status = "disabled";
1137 1034
1138 ports { 1035 ports {
1139 #address-cells = <1>; 1036 #address-cells = <1>;
1140 #size-cells = <0>; 1037 #size-cells = <0>;
1141 1038
1142 dsi_in: port@0 { !! 1039 port@0 {
1143 reg = <0>; 1040 reg = <0>;
1144 #address-cell 1041 #address-cells = <1>;
1145 #size-cells = 1042 #size-cells = <0>;
1146 1043
1147 dsi_in_vopb: 1044 dsi_in_vopb: endpoint@0 {
1148 reg = 1045 reg = <0>;
1149 remot 1046 remote-endpoint = <&vopb_out_dsi>;
1150 }; 1047 };
1151 1048
1152 dsi_in_vopl: 1049 dsi_in_vopl: endpoint@1 {
1153 reg = 1050 reg = <1>;
1154 remot 1051 remote-endpoint = <&vopl_out_dsi>;
1155 }; 1052 };
1156 }; 1053 };
1157 <<
1158 dsi_out: port@1 { <<
1159 reg = <1>; <<
1160 }; <<
1161 }; 1054 };
1162 }; 1055 };
1163 1056
1164 vopb: vop@ff460000 { 1057 vopb: vop@ff460000 {
1165 compatible = "rockchip,px30-v 1058 compatible = "rockchip,px30-vop-big";
1166 reg = <0x0 0xff460000 0x0 0xe 1059 reg = <0x0 0xff460000 0x0 0xefc>;
1167 interrupts = <GIC_SPI 77 IRQ_ 1060 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
1168 clocks = <&cru ACLK_VOPB>, <& 1061 clocks = <&cru ACLK_VOPB>, <&cru DCLK_VOPB>,
1169 <&cru HCLK_VOPB>; 1062 <&cru HCLK_VOPB>;
1170 clock-names = "aclk_vop", "dc 1063 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1171 resets = <&cru SRST_VOPB_A>, 1064 resets = <&cru SRST_VOPB_A>, <&cru SRST_VOPB_H>, <&cru SRST_VOPB>;
1172 reset-names = "axi", "ahb", " 1065 reset-names = "axi", "ahb", "dclk";
1173 iommus = <&vopb_mmu>; 1066 iommus = <&vopb_mmu>;
1174 power-domains = <&power PX30_ 1067 power-domains = <&power PX30_PD_VO>;
1175 status = "disabled"; 1068 status = "disabled";
1176 1069
1177 vopb_out: port { 1070 vopb_out: port {
1178 #address-cells = <1>; 1071 #address-cells = <1>;
1179 #size-cells = <0>; 1072 #size-cells = <0>;
1180 1073
1181 vopb_out_dsi: endpoin 1074 vopb_out_dsi: endpoint@0 {
1182 reg = <0>; 1075 reg = <0>;
1183 remote-endpoi 1076 remote-endpoint = <&dsi_in_vopb>;
1184 }; 1077 };
1185 1078
1186 vopb_out_lvds: endpoi 1079 vopb_out_lvds: endpoint@1 {
1187 reg = <1>; 1080 reg = <1>;
1188 remote-endpoi 1081 remote-endpoint = <&lvds_vopb_in>;
1189 }; 1082 };
1190 }; 1083 };
1191 }; 1084 };
1192 1085
1193 vopb_mmu: iommu@ff460f00 { 1086 vopb_mmu: iommu@ff460f00 {
1194 compatible = "rockchip,iommu" 1087 compatible = "rockchip,iommu";
1195 reg = <0x0 0xff460f00 0x0 0x1 1088 reg = <0x0 0xff460f00 0x0 0x100>;
1196 interrupts = <GIC_SPI 77 IRQ_ 1089 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
>> 1090 interrupt-names = "vopb_mmu";
1197 clocks = <&cru ACLK_VOPB>, <& 1091 clocks = <&cru ACLK_VOPB>, <&cru HCLK_VOPB>;
1198 clock-names = "aclk", "iface" 1092 clock-names = "aclk", "iface";
1199 power-domains = <&power PX30_ 1093 power-domains = <&power PX30_PD_VO>;
1200 #iommu-cells = <0>; 1094 #iommu-cells = <0>;
1201 status = "disabled"; 1095 status = "disabled";
1202 }; 1096 };
1203 1097
1204 vopl: vop@ff470000 { 1098 vopl: vop@ff470000 {
1205 compatible = "rockchip,px30-v 1099 compatible = "rockchip,px30-vop-lit";
1206 reg = <0x0 0xff470000 0x0 0xe 1100 reg = <0x0 0xff470000 0x0 0xefc>;
1207 interrupts = <GIC_SPI 78 IRQ_ 1101 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
1208 clocks = <&cru ACLK_VOPL>, <& 1102 clocks = <&cru ACLK_VOPL>, <&cru DCLK_VOPL>,
1209 <&cru HCLK_VOPL>; 1103 <&cru HCLK_VOPL>;
1210 clock-names = "aclk_vop", "dc 1104 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1211 resets = <&cru SRST_VOPL_A>, 1105 resets = <&cru SRST_VOPL_A>, <&cru SRST_VOPL_H>, <&cru SRST_VOPL>;
1212 reset-names = "axi", "ahb", " 1106 reset-names = "axi", "ahb", "dclk";
1213 iommus = <&vopl_mmu>; 1107 iommus = <&vopl_mmu>;
1214 power-domains = <&power PX30_ 1108 power-domains = <&power PX30_PD_VO>;
1215 status = "disabled"; 1109 status = "disabled";
1216 1110
1217 vopl_out: port { 1111 vopl_out: port {
1218 #address-cells = <1>; 1112 #address-cells = <1>;
1219 #size-cells = <0>; 1113 #size-cells = <0>;
1220 1114
1221 vopl_out_dsi: endpoin 1115 vopl_out_dsi: endpoint@0 {
1222 reg = <0>; 1116 reg = <0>;
1223 remote-endpoi 1117 remote-endpoint = <&dsi_in_vopl>;
1224 }; 1118 };
1225 1119
1226 vopl_out_lvds: endpoi 1120 vopl_out_lvds: endpoint@1 {
1227 reg = <1>; 1121 reg = <1>;
1228 remote-endpoi 1122 remote-endpoint = <&lvds_vopl_in>;
1229 }; 1123 };
1230 }; 1124 };
1231 }; 1125 };
1232 1126
1233 vopl_mmu: iommu@ff470f00 { 1127 vopl_mmu: iommu@ff470f00 {
1234 compatible = "rockchip,iommu" 1128 compatible = "rockchip,iommu";
1235 reg = <0x0 0xff470f00 0x0 0x1 1129 reg = <0x0 0xff470f00 0x0 0x100>;
1236 interrupts = <GIC_SPI 78 IRQ_ 1130 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
>> 1131 interrupt-names = "vopl_mmu";
1237 clocks = <&cru ACLK_VOPL>, <& 1132 clocks = <&cru ACLK_VOPL>, <&cru HCLK_VOPL>;
1238 clock-names = "aclk", "iface" 1133 clock-names = "aclk", "iface";
1239 power-domains = <&power PX30_ 1134 power-domains = <&power PX30_PD_VO>;
1240 #iommu-cells = <0>; 1135 #iommu-cells = <0>;
1241 status = "disabled"; 1136 status = "disabled";
1242 }; 1137 };
1243 1138
1244 isp: isp@ff4a0000 { <<
1245 compatible = "rockchip,px30-c <<
1246 reg = <0x0 0xff4a0000 0x0 0x8 <<
1247 interrupts = <GIC_SPI 70 IRQ_ <<
1248 <GIC_SPI 73 IRQ_ <<
1249 <GIC_SPI 74 IRQ_ <<
1250 interrupt-names = "isp", "mi" <<
1251 clocks = <&cru SCLK_ISP>, <<
1252 <&cru ACLK_ISP>, <<
1253 <&cru HCLK_ISP>, <<
1254 <&cru PCLK_ISP>; <<
1255 clock-names = "isp", "aclk", <<
1256 iommus = <&isp_mmu>; <<
1257 phys = <&csi_dphy>; <<
1258 phy-names = "dphy"; <<
1259 power-domains = <&power PX30_ <<
1260 status = "disabled"; <<
1261 <<
1262 ports { <<
1263 #address-cells = <1>; <<
1264 #size-cells = <0>; <<
1265 <<
1266 port@0 { <<
1267 reg = <0>; <<
1268 #address-cell <<
1269 #size-cells = <<
1270 }; <<
1271 }; <<
1272 }; <<
1273 <<
1274 isp_mmu: iommu@ff4a8000 { <<
1275 compatible = "rockchip,iommu" <<
1276 reg = <0x0 0xff4a8000 0x0 0x1 <<
1277 interrupts = <GIC_SPI 70 IRQ_ <<
1278 clocks = <&cru ACLK_ISP>, <&c <<
1279 clock-names = "aclk", "iface" <<
1280 power-domains = <&power PX30_ <<
1281 rockchip,disable-mmu-reset; <<
1282 #iommu-cells = <0>; <<
1283 }; <<
1284 <<
1285 qos_gmac: qos@ff518000 { 1139 qos_gmac: qos@ff518000 {
1286 compatible = "rockchip,px30-q 1140 compatible = "rockchip,px30-qos", "syscon";
1287 reg = <0x0 0xff518000 0x0 0x2 1141 reg = <0x0 0xff518000 0x0 0x20>;
1288 }; 1142 };
1289 1143
1290 qos_gpu: qos@ff520000 { 1144 qos_gpu: qos@ff520000 {
1291 compatible = "rockchip,px30-q 1145 compatible = "rockchip,px30-qos", "syscon";
1292 reg = <0x0 0xff520000 0x0 0x2 1146 reg = <0x0 0xff520000 0x0 0x20>;
1293 }; 1147 };
1294 1148
1295 qos_sdmmc: qos@ff52c000 { 1149 qos_sdmmc: qos@ff52c000 {
1296 compatible = "rockchip,px30-q 1150 compatible = "rockchip,px30-qos", "syscon";
1297 reg = <0x0 0xff52c000 0x0 0x2 1151 reg = <0x0 0xff52c000 0x0 0x20>;
1298 }; 1152 };
1299 1153
1300 qos_emmc: qos@ff538000 { 1154 qos_emmc: qos@ff538000 {
1301 compatible = "rockchip,px30-q 1155 compatible = "rockchip,px30-qos", "syscon";
1302 reg = <0x0 0xff538000 0x0 0x2 1156 reg = <0x0 0xff538000 0x0 0x20>;
1303 }; 1157 };
1304 1158
1305 qos_nand: qos@ff538080 { 1159 qos_nand: qos@ff538080 {
1306 compatible = "rockchip,px30-q 1160 compatible = "rockchip,px30-qos", "syscon";
1307 reg = <0x0 0xff538080 0x0 0x2 1161 reg = <0x0 0xff538080 0x0 0x20>;
1308 }; 1162 };
1309 1163
1310 qos_sdio: qos@ff538100 { 1164 qos_sdio: qos@ff538100 {
1311 compatible = "rockchip,px30-q 1165 compatible = "rockchip,px30-qos", "syscon";
1312 reg = <0x0 0xff538100 0x0 0x2 1166 reg = <0x0 0xff538100 0x0 0x20>;
1313 }; 1167 };
1314 1168
1315 qos_sfc: qos@ff538180 { 1169 qos_sfc: qos@ff538180 {
1316 compatible = "rockchip,px30-q 1170 compatible = "rockchip,px30-qos", "syscon";
1317 reg = <0x0 0xff538180 0x0 0x2 1171 reg = <0x0 0xff538180 0x0 0x20>;
1318 }; 1172 };
1319 1173
1320 qos_usb_host: qos@ff540000 { 1174 qos_usb_host: qos@ff540000 {
1321 compatible = "rockchip,px30-q 1175 compatible = "rockchip,px30-qos", "syscon";
1322 reg = <0x0 0xff540000 0x0 0x2 1176 reg = <0x0 0xff540000 0x0 0x20>;
1323 }; 1177 };
1324 1178
1325 qos_usb_otg: qos@ff540080 { 1179 qos_usb_otg: qos@ff540080 {
1326 compatible = "rockchip,px30-q 1180 compatible = "rockchip,px30-qos", "syscon";
1327 reg = <0x0 0xff540080 0x0 0x2 1181 reg = <0x0 0xff540080 0x0 0x20>;
1328 }; 1182 };
1329 1183
1330 qos_isp_128: qos@ff548000 { 1184 qos_isp_128: qos@ff548000 {
1331 compatible = "rockchip,px30-q 1185 compatible = "rockchip,px30-qos", "syscon";
1332 reg = <0x0 0xff548000 0x0 0x2 1186 reg = <0x0 0xff548000 0x0 0x20>;
1333 }; 1187 };
1334 1188
1335 qos_isp_rd: qos@ff548080 { 1189 qos_isp_rd: qos@ff548080 {
1336 compatible = "rockchip,px30-q 1190 compatible = "rockchip,px30-qos", "syscon";
1337 reg = <0x0 0xff548080 0x0 0x2 1191 reg = <0x0 0xff548080 0x0 0x20>;
1338 }; 1192 };
1339 1193
1340 qos_isp_wr: qos@ff548100 { 1194 qos_isp_wr: qos@ff548100 {
1341 compatible = "rockchip,px30-q 1195 compatible = "rockchip,px30-qos", "syscon";
1342 reg = <0x0 0xff548100 0x0 0x2 1196 reg = <0x0 0xff548100 0x0 0x20>;
1343 }; 1197 };
1344 1198
1345 qos_isp_m1: qos@ff548180 { 1199 qos_isp_m1: qos@ff548180 {
1346 compatible = "rockchip,px30-q 1200 compatible = "rockchip,px30-qos", "syscon";
1347 reg = <0x0 0xff548180 0x0 0x2 1201 reg = <0x0 0xff548180 0x0 0x20>;
1348 }; 1202 };
1349 1203
1350 qos_vip: qos@ff548200 { 1204 qos_vip: qos@ff548200 {
1351 compatible = "rockchip,px30-q 1205 compatible = "rockchip,px30-qos", "syscon";
1352 reg = <0x0 0xff548200 0x0 0x2 1206 reg = <0x0 0xff548200 0x0 0x20>;
1353 }; 1207 };
1354 1208
1355 qos_rga_rd: qos@ff550000 { 1209 qos_rga_rd: qos@ff550000 {
1356 compatible = "rockchip,px30-q 1210 compatible = "rockchip,px30-qos", "syscon";
1357 reg = <0x0 0xff550000 0x0 0x2 1211 reg = <0x0 0xff550000 0x0 0x20>;
1358 }; 1212 };
1359 1213
1360 qos_rga_wr: qos@ff550080 { 1214 qos_rga_wr: qos@ff550080 {
1361 compatible = "rockchip,px30-q 1215 compatible = "rockchip,px30-qos", "syscon";
1362 reg = <0x0 0xff550080 0x0 0x2 1216 reg = <0x0 0xff550080 0x0 0x20>;
1363 }; 1217 };
1364 1218
1365 qos_vop_m0: qos@ff550100 { 1219 qos_vop_m0: qos@ff550100 {
1366 compatible = "rockchip,px30-q 1220 compatible = "rockchip,px30-qos", "syscon";
1367 reg = <0x0 0xff550100 0x0 0x2 1221 reg = <0x0 0xff550100 0x0 0x20>;
1368 }; 1222 };
1369 1223
1370 qos_vop_m1: qos@ff550180 { 1224 qos_vop_m1: qos@ff550180 {
1371 compatible = "rockchip,px30-q 1225 compatible = "rockchip,px30-qos", "syscon";
1372 reg = <0x0 0xff550180 0x0 0x2 1226 reg = <0x0 0xff550180 0x0 0x20>;
1373 }; 1227 };
1374 1228
1375 qos_vpu: qos@ff558000 { 1229 qos_vpu: qos@ff558000 {
1376 compatible = "rockchip,px30-q 1230 compatible = "rockchip,px30-qos", "syscon";
1377 reg = <0x0 0xff558000 0x0 0x2 1231 reg = <0x0 0xff558000 0x0 0x20>;
1378 }; 1232 };
1379 1233
1380 qos_vpu_r128: qos@ff558080 { 1234 qos_vpu_r128: qos@ff558080 {
1381 compatible = "rockchip,px30-q 1235 compatible = "rockchip,px30-qos", "syscon";
1382 reg = <0x0 0xff558080 0x0 0x2 1236 reg = <0x0 0xff558080 0x0 0x20>;
1383 }; 1237 };
1384 1238
1385 pinctrl: pinctrl { 1239 pinctrl: pinctrl {
1386 compatible = "rockchip,px30-p 1240 compatible = "rockchip,px30-pinctrl";
1387 rockchip,grf = <&grf>; 1241 rockchip,grf = <&grf>;
1388 rockchip,pmu = <&pmugrf>; 1242 rockchip,pmu = <&pmugrf>;
1389 #address-cells = <2>; 1243 #address-cells = <2>;
1390 #size-cells = <2>; 1244 #size-cells = <2>;
1391 ranges; 1245 ranges;
1392 1246
1393 gpio0: gpio@ff040000 { !! 1247 gpio0: gpio0@ff040000 {
1394 compatible = "rockchi 1248 compatible = "rockchip,gpio-bank";
1395 reg = <0x0 0xff040000 1249 reg = <0x0 0xff040000 0x0 0x100>;
1396 interrupts = <GIC_SPI 1250 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
1397 clocks = <&pmucru PCL 1251 clocks = <&pmucru PCLK_GPIO0_PMU>;
1398 gpio-controller; 1252 gpio-controller;
1399 #gpio-cells = <2>; 1253 #gpio-cells = <2>;
1400 1254
1401 interrupt-controller; 1255 interrupt-controller;
1402 #interrupt-cells = <2 1256 #interrupt-cells = <2>;
1403 }; 1257 };
1404 1258
1405 gpio1: gpio@ff250000 { !! 1259 gpio1: gpio1@ff250000 {
1406 compatible = "rockchi 1260 compatible = "rockchip,gpio-bank";
1407 reg = <0x0 0xff250000 1261 reg = <0x0 0xff250000 0x0 0x100>;
1408 interrupts = <GIC_SPI 1262 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
1409 clocks = <&cru PCLK_G 1263 clocks = <&cru PCLK_GPIO1>;
1410 gpio-controller; 1264 gpio-controller;
1411 #gpio-cells = <2>; 1265 #gpio-cells = <2>;
1412 1266
1413 interrupt-controller; 1267 interrupt-controller;
1414 #interrupt-cells = <2 1268 #interrupt-cells = <2>;
1415 }; 1269 };
1416 1270
1417 gpio2: gpio@ff260000 { !! 1271 gpio2: gpio2@ff260000 {
1418 compatible = "rockchi 1272 compatible = "rockchip,gpio-bank";
1419 reg = <0x0 0xff260000 1273 reg = <0x0 0xff260000 0x0 0x100>;
1420 interrupts = <GIC_SPI 1274 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
1421 clocks = <&cru PCLK_G 1275 clocks = <&cru PCLK_GPIO2>;
1422 gpio-controller; 1276 gpio-controller;
1423 #gpio-cells = <2>; 1277 #gpio-cells = <2>;
1424 1278
1425 interrupt-controller; 1279 interrupt-controller;
1426 #interrupt-cells = <2 1280 #interrupt-cells = <2>;
1427 }; 1281 };
1428 1282
1429 gpio3: gpio@ff270000 { !! 1283 gpio3: gpio3@ff270000 {
1430 compatible = "rockchi 1284 compatible = "rockchip,gpio-bank";
1431 reg = <0x0 0xff270000 1285 reg = <0x0 0xff270000 0x0 0x100>;
1432 interrupts = <GIC_SPI 1286 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
1433 clocks = <&cru PCLK_G 1287 clocks = <&cru PCLK_GPIO3>;
1434 gpio-controller; 1288 gpio-controller;
1435 #gpio-cells = <2>; 1289 #gpio-cells = <2>;
1436 1290
1437 interrupt-controller; 1291 interrupt-controller;
1438 #interrupt-cells = <2 1292 #interrupt-cells = <2>;
1439 }; 1293 };
1440 1294
1441 pcfg_pull_up: pcfg-pull-up { 1295 pcfg_pull_up: pcfg-pull-up {
1442 bias-pull-up; 1296 bias-pull-up;
1443 }; 1297 };
1444 1298
1445 pcfg_pull_down: pcfg-pull-dow 1299 pcfg_pull_down: pcfg-pull-down {
1446 bias-pull-down; 1300 bias-pull-down;
1447 }; 1301 };
1448 1302
1449 pcfg_pull_none: pcfg-pull-non 1303 pcfg_pull_none: pcfg-pull-none {
1450 bias-disable; 1304 bias-disable;
1451 }; 1305 };
1452 1306
1453 pcfg_pull_none_2ma: pcfg-pull 1307 pcfg_pull_none_2ma: pcfg-pull-none-2ma {
1454 bias-disable; 1308 bias-disable;
1455 drive-strength = <2>; 1309 drive-strength = <2>;
1456 }; 1310 };
1457 1311
1458 pcfg_pull_up_2ma: pcfg-pull-u 1312 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
1459 bias-pull-up; 1313 bias-pull-up;
1460 drive-strength = <2>; 1314 drive-strength = <2>;
1461 }; 1315 };
1462 1316
1463 pcfg_pull_up_4ma: pcfg-pull-u 1317 pcfg_pull_up_4ma: pcfg-pull-up-4ma {
1464 bias-pull-up; 1318 bias-pull-up;
1465 drive-strength = <4>; 1319 drive-strength = <4>;
1466 }; 1320 };
1467 1321
1468 pcfg_pull_none_4ma: pcfg-pull 1322 pcfg_pull_none_4ma: pcfg-pull-none-4ma {
1469 bias-disable; 1323 bias-disable;
1470 drive-strength = <4>; 1324 drive-strength = <4>;
1471 }; 1325 };
1472 1326
1473 pcfg_pull_down_4ma: pcfg-pull 1327 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
1474 bias-pull-down; 1328 bias-pull-down;
1475 drive-strength = <4>; 1329 drive-strength = <4>;
1476 }; 1330 };
1477 1331
1478 pcfg_pull_none_8ma: pcfg-pull 1332 pcfg_pull_none_8ma: pcfg-pull-none-8ma {
1479 bias-disable; 1333 bias-disable;
1480 drive-strength = <8>; 1334 drive-strength = <8>;
1481 }; 1335 };
1482 1336
1483 pcfg_pull_up_8ma: pcfg-pull-u 1337 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
1484 bias-pull-up; 1338 bias-pull-up;
1485 drive-strength = <8>; 1339 drive-strength = <8>;
1486 }; 1340 };
1487 1341
1488 pcfg_pull_none_12ma: pcfg-pul 1342 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1489 bias-disable; 1343 bias-disable;
1490 drive-strength = <12> 1344 drive-strength = <12>;
1491 }; 1345 };
1492 1346
1493 pcfg_pull_up_12ma: pcfg-pull- 1347 pcfg_pull_up_12ma: pcfg-pull-up-12ma {
1494 bias-pull-up; 1348 bias-pull-up;
1495 drive-strength = <12> 1349 drive-strength = <12>;
1496 }; 1350 };
1497 1351
1498 pcfg_pull_none_smt: pcfg-pull 1352 pcfg_pull_none_smt: pcfg-pull-none-smt {
1499 bias-disable; 1353 bias-disable;
1500 input-schmitt-enable; 1354 input-schmitt-enable;
1501 }; 1355 };
1502 1356
1503 pcfg_output_high: pcfg-output 1357 pcfg_output_high: pcfg-output-high {
1504 output-high; 1358 output-high;
1505 }; 1359 };
1506 1360
1507 pcfg_output_low: pcfg-output- 1361 pcfg_output_low: pcfg-output-low {
1508 output-low; 1362 output-low;
1509 }; 1363 };
1510 1364
1511 pcfg_input_high: pcfg-input-h 1365 pcfg_input_high: pcfg-input-high {
1512 bias-pull-up; 1366 bias-pull-up;
1513 input-enable; 1367 input-enable;
1514 }; 1368 };
1515 1369
1516 pcfg_input: pcfg-input { 1370 pcfg_input: pcfg-input {
1517 input-enable; 1371 input-enable;
1518 }; 1372 };
1519 1373
1520 i2c0 { 1374 i2c0 {
1521 i2c0_xfer: i2c0-xfer 1375 i2c0_xfer: i2c0-xfer {
1522 rockchip,pins 1376 rockchip,pins =
1523 <0 RK 1377 <0 RK_PB0 1 &pcfg_pull_none_smt>,
1524 <0 RK 1378 <0 RK_PB1 1 &pcfg_pull_none_smt>;
1525 }; 1379 };
1526 }; 1380 };
1527 1381
1528 i2c1 { 1382 i2c1 {
1529 i2c1_xfer: i2c1-xfer 1383 i2c1_xfer: i2c1-xfer {
1530 rockchip,pins 1384 rockchip,pins =
1531 <0 RK 1385 <0 RK_PC2 1 &pcfg_pull_none_smt>,
1532 <0 RK 1386 <0 RK_PC3 1 &pcfg_pull_none_smt>;
1533 }; 1387 };
1534 }; 1388 };
1535 1389
1536 i2c2 { 1390 i2c2 {
1537 i2c2_xfer: i2c2-xfer 1391 i2c2_xfer: i2c2-xfer {
1538 rockchip,pins 1392 rockchip,pins =
1539 <2 RK 1393 <2 RK_PB7 2 &pcfg_pull_none_smt>,
1540 <2 RK 1394 <2 RK_PC0 2 &pcfg_pull_none_smt>;
1541 }; 1395 };
1542 }; 1396 };
1543 1397
1544 i2c3 { 1398 i2c3 {
1545 i2c3_xfer: i2c3-xfer 1399 i2c3_xfer: i2c3-xfer {
1546 rockchip,pins 1400 rockchip,pins =
1547 <1 RK 1401 <1 RK_PB4 4 &pcfg_pull_none_smt>,
1548 <1 RK 1402 <1 RK_PB5 4 &pcfg_pull_none_smt>;
1549 }; 1403 };
1550 }; 1404 };
1551 1405
1552 tsadc { 1406 tsadc {
1553 tsadc_otp_pin: tsadc- 1407 tsadc_otp_pin: tsadc-otp-pin {
1554 rockchip,pins 1408 rockchip,pins =
1555 <0 RK 1409 <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
1556 }; 1410 };
1557 1411
1558 tsadc_otp_out: tsadc- 1412 tsadc_otp_out: tsadc-otp-out {
1559 rockchip,pins 1413 rockchip,pins =
1560 <0 RK 1414 <0 RK_PA6 1 &pcfg_pull_none>;
1561 }; 1415 };
1562 }; 1416 };
1563 1417
1564 uart0 { 1418 uart0 {
1565 uart0_xfer: uart0-xfe 1419 uart0_xfer: uart0-xfer {
1566 rockchip,pins 1420 rockchip,pins =
1567 <0 RK 1421 <0 RK_PB2 1 &pcfg_pull_up>,
1568 <0 RK 1422 <0 RK_PB3 1 &pcfg_pull_up>;
1569 }; 1423 };
1570 1424
1571 uart0_cts: uart0-cts 1425 uart0_cts: uart0-cts {
1572 rockchip,pins 1426 rockchip,pins =
1573 <0 RK 1427 <0 RK_PB4 1 &pcfg_pull_none>;
1574 }; 1428 };
1575 1429
1576 uart0_rts: uart0-rts 1430 uart0_rts: uart0-rts {
1577 rockchip,pins 1431 rockchip,pins =
1578 <0 RK 1432 <0 RK_PB5 1 &pcfg_pull_none>;
1579 }; 1433 };
1580 }; 1434 };
1581 1435
1582 uart1 { 1436 uart1 {
1583 uart1_xfer: uart1-xfe 1437 uart1_xfer: uart1-xfer {
1584 rockchip,pins 1438 rockchip,pins =
1585 <1 RK 1439 <1 RK_PC1 1 &pcfg_pull_up>,
1586 <1 RK 1440 <1 RK_PC0 1 &pcfg_pull_up>;
1587 }; 1441 };
1588 1442
1589 uart1_cts: uart1-cts 1443 uart1_cts: uart1-cts {
1590 rockchip,pins 1444 rockchip,pins =
1591 <1 RK 1445 <1 RK_PC2 1 &pcfg_pull_none>;
1592 }; 1446 };
1593 1447
1594 uart1_rts: uart1-rts 1448 uart1_rts: uart1-rts {
1595 rockchip,pins 1449 rockchip,pins =
1596 <1 RK 1450 <1 RK_PC3 1 &pcfg_pull_none>;
1597 }; 1451 };
1598 }; 1452 };
1599 1453
1600 uart2-m0 { 1454 uart2-m0 {
1601 uart2m0_xfer: uart2m0 1455 uart2m0_xfer: uart2m0-xfer {
1602 rockchip,pins 1456 rockchip,pins =
1603 <1 RK 1457 <1 RK_PD2 2 &pcfg_pull_up>,
1604 <1 RK 1458 <1 RK_PD3 2 &pcfg_pull_up>;
1605 }; 1459 };
1606 }; 1460 };
1607 1461
1608 uart2-m1 { 1462 uart2-m1 {
1609 uart2m1_xfer: uart2m1 1463 uart2m1_xfer: uart2m1-xfer {
1610 rockchip,pins 1464 rockchip,pins =
1611 <2 RK 1465 <2 RK_PB4 2 &pcfg_pull_up>,
1612 <2 RK 1466 <2 RK_PB6 2 &pcfg_pull_up>;
1613 }; 1467 };
1614 }; 1468 };
1615 1469
1616 uart3-m0 { 1470 uart3-m0 {
1617 uart3m0_xfer: uart3m0 1471 uart3m0_xfer: uart3m0-xfer {
1618 rockchip,pins 1472 rockchip,pins =
1619 <0 RK 1473 <0 RK_PC0 2 &pcfg_pull_up>,
1620 <0 RK 1474 <0 RK_PC1 2 &pcfg_pull_up>;
1621 }; 1475 };
1622 1476
1623 uart3m0_cts: uart3m0- 1477 uart3m0_cts: uart3m0-cts {
1624 rockchip,pins 1478 rockchip,pins =
1625 <0 RK 1479 <0 RK_PC2 2 &pcfg_pull_none>;
1626 }; 1480 };
1627 1481
1628 uart3m0_rts: uart3m0- 1482 uart3m0_rts: uart3m0-rts {
1629 rockchip,pins 1483 rockchip,pins =
1630 <0 RK 1484 <0 RK_PC3 2 &pcfg_pull_none>;
1631 }; 1485 };
1632 }; 1486 };
1633 1487
1634 uart3-m1 { 1488 uart3-m1 {
1635 uart3m1_xfer: uart3m1 1489 uart3m1_xfer: uart3m1-xfer {
1636 rockchip,pins 1490 rockchip,pins =
1637 <1 RK 1491 <1 RK_PB6 2 &pcfg_pull_up>,
1638 <1 RK 1492 <1 RK_PB7 2 &pcfg_pull_up>;
1639 }; 1493 };
1640 1494
1641 uart3m1_cts: uart3m1- 1495 uart3m1_cts: uart3m1-cts {
1642 rockchip,pins 1496 rockchip,pins =
1643 <1 RK 1497 <1 RK_PB4 2 &pcfg_pull_none>;
1644 }; 1498 };
1645 1499
1646 uart3m1_rts: uart3m1- 1500 uart3m1_rts: uart3m1-rts {
1647 rockchip,pins 1501 rockchip,pins =
1648 <1 RK 1502 <1 RK_PB5 2 &pcfg_pull_none>;
1649 }; 1503 };
1650 }; 1504 };
1651 1505
1652 uart4 { 1506 uart4 {
1653 uart4_xfer: uart4-xfe 1507 uart4_xfer: uart4-xfer {
1654 rockchip,pins 1508 rockchip,pins =
1655 <1 RK 1509 <1 RK_PD4 2 &pcfg_pull_up>,
1656 <1 RK 1510 <1 RK_PD5 2 &pcfg_pull_up>;
1657 }; 1511 };
1658 1512
1659 uart4_cts: uart4-cts 1513 uart4_cts: uart4-cts {
1660 rockchip,pins 1514 rockchip,pins =
1661 <1 RK 1515 <1 RK_PD6 2 &pcfg_pull_none>;
1662 }; 1516 };
1663 1517
1664 uart4_rts: uart4-rts 1518 uart4_rts: uart4-rts {
1665 rockchip,pins 1519 rockchip,pins =
1666 <1 RK 1520 <1 RK_PD7 2 &pcfg_pull_none>;
1667 }; 1521 };
1668 }; 1522 };
1669 1523
1670 uart5 { 1524 uart5 {
1671 uart5_xfer: uart5-xfe 1525 uart5_xfer: uart5-xfer {
1672 rockchip,pins 1526 rockchip,pins =
1673 <3 RK 1527 <3 RK_PA2 4 &pcfg_pull_up>,
1674 <3 RK 1528 <3 RK_PA1 4 &pcfg_pull_up>;
1675 }; 1529 };
1676 1530
1677 uart5_cts: uart5-cts 1531 uart5_cts: uart5-cts {
1678 rockchip,pins 1532 rockchip,pins =
1679 <3 RK 1533 <3 RK_PA3 4 &pcfg_pull_none>;
1680 }; 1534 };
1681 1535
1682 uart5_rts: uart5-rts 1536 uart5_rts: uart5-rts {
1683 rockchip,pins 1537 rockchip,pins =
1684 <3 RK 1538 <3 RK_PA5 4 &pcfg_pull_none>;
1685 }; 1539 };
1686 }; 1540 };
1687 1541
1688 spi0 { 1542 spi0 {
1689 spi0_clk: spi0-clk { 1543 spi0_clk: spi0-clk {
1690 rockchip,pins 1544 rockchip,pins =
1691 <1 RK 1545 <1 RK_PB7 3 &pcfg_pull_up_4ma>;
1692 }; 1546 };
1693 1547
1694 spi0_csn: spi0-csn { 1548 spi0_csn: spi0-csn {
1695 rockchip,pins 1549 rockchip,pins =
1696 <1 RK 1550 <1 RK_PB6 3 &pcfg_pull_up_4ma>;
1697 }; 1551 };
1698 1552
1699 spi0_miso: spi0-miso 1553 spi0_miso: spi0-miso {
1700 rockchip,pins 1554 rockchip,pins =
1701 <1 RK 1555 <1 RK_PB5 3 &pcfg_pull_up_4ma>;
1702 }; 1556 };
1703 1557
1704 spi0_mosi: spi0-mosi 1558 spi0_mosi: spi0-mosi {
1705 rockchip,pins 1559 rockchip,pins =
1706 <1 RK 1560 <1 RK_PB4 3 &pcfg_pull_up_4ma>;
1707 }; 1561 };
1708 1562
1709 spi0_clk_hs: spi0-clk 1563 spi0_clk_hs: spi0-clk-hs {
1710 rockchip,pins 1564 rockchip,pins =
1711 <1 RK 1565 <1 RK_PB7 3 &pcfg_pull_up_8ma>;
1712 }; 1566 };
1713 1567
1714 spi0_miso_hs: spi0-mi 1568 spi0_miso_hs: spi0-miso-hs {
1715 rockchip,pins 1569 rockchip,pins =
1716 <1 RK 1570 <1 RK_PB5 3 &pcfg_pull_up_8ma>;
1717 }; 1571 };
1718 1572
1719 spi0_mosi_hs: spi0-mo 1573 spi0_mosi_hs: spi0-mosi-hs {
1720 rockchip,pins 1574 rockchip,pins =
1721 <1 RK 1575 <1 RK_PB4 3 &pcfg_pull_up_8ma>;
1722 }; 1576 };
1723 }; 1577 };
1724 1578
1725 spi1 { 1579 spi1 {
1726 spi1_clk: spi1-clk { 1580 spi1_clk: spi1-clk {
1727 rockchip,pins 1581 rockchip,pins =
1728 <3 RK 1582 <3 RK_PB7 4 &pcfg_pull_up_4ma>;
1729 }; 1583 };
1730 1584
1731 spi1_csn0: spi1-csn0 1585 spi1_csn0: spi1-csn0 {
1732 rockchip,pins 1586 rockchip,pins =
1733 <3 RK 1587 <3 RK_PB1 4 &pcfg_pull_up_4ma>;
1734 }; 1588 };
1735 1589
1736 spi1_csn1: spi1-csn1 1590 spi1_csn1: spi1-csn1 {
1737 rockchip,pins 1591 rockchip,pins =
1738 <3 RK 1592 <3 RK_PB2 2 &pcfg_pull_up_4ma>;
1739 }; 1593 };
1740 1594
1741 spi1_miso: spi1-miso 1595 spi1_miso: spi1-miso {
1742 rockchip,pins 1596 rockchip,pins =
1743 <3 RK 1597 <3 RK_PB6 4 &pcfg_pull_up_4ma>;
1744 }; 1598 };
1745 1599
1746 spi1_mosi: spi1-mosi 1600 spi1_mosi: spi1-mosi {
1747 rockchip,pins 1601 rockchip,pins =
1748 <3 RK 1602 <3 RK_PB4 4 &pcfg_pull_up_4ma>;
1749 }; 1603 };
1750 1604
1751 spi1_clk_hs: spi1-clk 1605 spi1_clk_hs: spi1-clk-hs {
1752 rockchip,pins 1606 rockchip,pins =
1753 <3 RK 1607 <3 RK_PB7 4 &pcfg_pull_up_8ma>;
1754 }; 1608 };
1755 1609
1756 spi1_miso_hs: spi1-mi 1610 spi1_miso_hs: spi1-miso-hs {
1757 rockchip,pins 1611 rockchip,pins =
1758 <3 RK 1612 <3 RK_PB6 4 &pcfg_pull_up_8ma>;
1759 }; 1613 };
1760 1614
1761 spi1_mosi_hs: spi1-mo 1615 spi1_mosi_hs: spi1-mosi-hs {
1762 rockchip,pins 1616 rockchip,pins =
1763 <3 RK 1617 <3 RK_PB4 4 &pcfg_pull_up_8ma>;
1764 }; 1618 };
1765 }; 1619 };
1766 1620
1767 pdm { 1621 pdm {
1768 pdm_clk0m0: pdm-clk0m 1622 pdm_clk0m0: pdm-clk0m0 {
1769 rockchip,pins 1623 rockchip,pins =
1770 <3 RK 1624 <3 RK_PC6 2 &pcfg_pull_none>;
1771 }; 1625 };
1772 1626
1773 pdm_clk0m1: pdm-clk0m 1627 pdm_clk0m1: pdm-clk0m1 {
1774 rockchip,pins 1628 rockchip,pins =
1775 <2 RK 1629 <2 RK_PC6 1 &pcfg_pull_none>;
1776 }; 1630 };
1777 1631
1778 pdm_clk1: pdm-clk1 { 1632 pdm_clk1: pdm-clk1 {
1779 rockchip,pins 1633 rockchip,pins =
1780 <3 RK 1634 <3 RK_PC7 2 &pcfg_pull_none>;
1781 }; 1635 };
1782 1636
1783 pdm_sdi0m0: pdm-sdi0m 1637 pdm_sdi0m0: pdm-sdi0m0 {
1784 rockchip,pins 1638 rockchip,pins =
1785 <3 RK 1639 <3 RK_PD3 2 &pcfg_pull_none>;
1786 }; 1640 };
1787 1641
1788 pdm_sdi0m1: pdm-sdi0m 1642 pdm_sdi0m1: pdm-sdi0m1 {
1789 rockchip,pins 1643 rockchip,pins =
1790 <2 RK 1644 <2 RK_PC5 2 &pcfg_pull_none>;
1791 }; 1645 };
1792 1646
1793 pdm_sdi1: pdm-sdi1 { 1647 pdm_sdi1: pdm-sdi1 {
1794 rockchip,pins 1648 rockchip,pins =
1795 <3 RK 1649 <3 RK_PD0 2 &pcfg_pull_none>;
1796 }; 1650 };
1797 1651
1798 pdm_sdi2: pdm-sdi2 { 1652 pdm_sdi2: pdm-sdi2 {
1799 rockchip,pins 1653 rockchip,pins =
1800 <3 RK 1654 <3 RK_PD1 2 &pcfg_pull_none>;
1801 }; 1655 };
1802 1656
1803 pdm_sdi3: pdm-sdi3 { 1657 pdm_sdi3: pdm-sdi3 {
1804 rockchip,pins 1658 rockchip,pins =
1805 <3 RK 1659 <3 RK_PD2 2 &pcfg_pull_none>;
1806 }; 1660 };
1807 1661
1808 pdm_clk0m0_sleep: pdm 1662 pdm_clk0m0_sleep: pdm-clk0m0-sleep {
1809 rockchip,pins 1663 rockchip,pins =
1810 <3 RK 1664 <3 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>;
1811 }; 1665 };
1812 1666
1813 pdm_clk0m_sleep1: pdm 1667 pdm_clk0m_sleep1: pdm-clk0m1-sleep {
1814 rockchip,pins 1668 rockchip,pins =
1815 <2 RK 1669 <2 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>;
1816 }; 1670 };
1817 1671
1818 pdm_clk1_sleep: pdm-c 1672 pdm_clk1_sleep: pdm-clk1-sleep {
1819 rockchip,pins 1673 rockchip,pins =
1820 <3 RK 1674 <3 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>;
1821 }; 1675 };
1822 1676
1823 pdm_sdi0m0_sleep: pdm 1677 pdm_sdi0m0_sleep: pdm-sdi0m0-sleep {
1824 rockchip,pins 1678 rockchip,pins =
1825 <3 RK 1679 <3 RK_PD3 RK_FUNC_GPIO &pcfg_input_high>;
1826 }; 1680 };
1827 1681
1828 pdm_sdi0m1_sleep: pdm 1682 pdm_sdi0m1_sleep: pdm-sdi0m1-sleep {
1829 rockchip,pins 1683 rockchip,pins =
1830 <2 RK 1684 <2 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>;
1831 }; 1685 };
1832 1686
1833 pdm_sdi1_sleep: pdm-s 1687 pdm_sdi1_sleep: pdm-sdi1-sleep {
1834 rockchip,pins 1688 rockchip,pins =
1835 <3 RK 1689 <3 RK_PD0 RK_FUNC_GPIO &pcfg_input_high>;
1836 }; 1690 };
1837 1691
1838 pdm_sdi2_sleep: pdm-s 1692 pdm_sdi2_sleep: pdm-sdi2-sleep {
1839 rockchip,pins 1693 rockchip,pins =
1840 <3 RK 1694 <3 RK_PD1 RK_FUNC_GPIO &pcfg_input_high>;
1841 }; 1695 };
1842 1696
1843 pdm_sdi3_sleep: pdm-s 1697 pdm_sdi3_sleep: pdm-sdi3-sleep {
1844 rockchip,pins 1698 rockchip,pins =
1845 <3 RK 1699 <3 RK_PD2 RK_FUNC_GPIO &pcfg_input_high>;
1846 }; 1700 };
1847 }; 1701 };
1848 1702
1849 i2s0 { 1703 i2s0 {
1850 i2s0_8ch_mclk: i2s0-8 1704 i2s0_8ch_mclk: i2s0-8ch-mclk {
1851 rockchip,pins 1705 rockchip,pins =
1852 <3 RK 1706 <3 RK_PC1 2 &pcfg_pull_none>;
1853 }; 1707 };
1854 1708
1855 i2s0_8ch_sclktx: i2s0 1709 i2s0_8ch_sclktx: i2s0-8ch-sclktx {
1856 rockchip,pins 1710 rockchip,pins =
1857 <3 RK 1711 <3 RK_PC3 2 &pcfg_pull_none>;
1858 }; 1712 };
1859 1713
1860 i2s0_8ch_sclkrx: i2s0 1714 i2s0_8ch_sclkrx: i2s0-8ch-sclkrx {
1861 rockchip,pins 1715 rockchip,pins =
1862 <3 RK 1716 <3 RK_PB4 2 &pcfg_pull_none>;
1863 }; 1717 };
1864 1718
1865 i2s0_8ch_lrcktx: i2s0 1719 i2s0_8ch_lrcktx: i2s0-8ch-lrcktx {
1866 rockchip,pins 1720 rockchip,pins =
1867 <3 RK 1721 <3 RK_PC2 2 &pcfg_pull_none>;
1868 }; 1722 };
1869 1723
1870 i2s0_8ch_lrckrx: i2s0 1724 i2s0_8ch_lrckrx: i2s0-8ch-lrckrx {
1871 rockchip,pins 1725 rockchip,pins =
1872 <3 RK 1726 <3 RK_PB5 2 &pcfg_pull_none>;
1873 }; 1727 };
1874 1728
1875 i2s0_8ch_sdo0: i2s0-8 1729 i2s0_8ch_sdo0: i2s0-8ch-sdo0 {
1876 rockchip,pins 1730 rockchip,pins =
1877 <3 RK 1731 <3 RK_PC4 2 &pcfg_pull_none>;
1878 }; 1732 };
1879 1733
1880 i2s0_8ch_sdo1: i2s0-8 1734 i2s0_8ch_sdo1: i2s0-8ch-sdo1 {
1881 rockchip,pins 1735 rockchip,pins =
1882 <3 RK 1736 <3 RK_PC0 2 &pcfg_pull_none>;
1883 }; 1737 };
1884 1738
1885 i2s0_8ch_sdo2: i2s0-8 1739 i2s0_8ch_sdo2: i2s0-8ch-sdo2 {
1886 rockchip,pins 1740 rockchip,pins =
1887 <3 RK 1741 <3 RK_PB7 2 &pcfg_pull_none>;
1888 }; 1742 };
1889 1743
1890 i2s0_8ch_sdo3: i2s0-8 1744 i2s0_8ch_sdo3: i2s0-8ch-sdo3 {
1891 rockchip,pins 1745 rockchip,pins =
1892 <3 RK 1746 <3 RK_PB6 2 &pcfg_pull_none>;
1893 }; 1747 };
1894 1748
1895 i2s0_8ch_sdi0: i2s0-8 1749 i2s0_8ch_sdi0: i2s0-8ch-sdi0 {
1896 rockchip,pins 1750 rockchip,pins =
1897 <3 RK 1751 <3 RK_PC5 2 &pcfg_pull_none>;
1898 }; 1752 };
1899 1753
1900 i2s0_8ch_sdi1: i2s0-8 1754 i2s0_8ch_sdi1: i2s0-8ch-sdi1 {
1901 rockchip,pins 1755 rockchip,pins =
1902 <3 RK 1756 <3 RK_PB3 2 &pcfg_pull_none>;
1903 }; 1757 };
1904 1758
1905 i2s0_8ch_sdi2: i2s0-8 1759 i2s0_8ch_sdi2: i2s0-8ch-sdi2 {
1906 rockchip,pins 1760 rockchip,pins =
1907 <3 RK 1761 <3 RK_PB1 2 &pcfg_pull_none>;
1908 }; 1762 };
1909 1763
1910 i2s0_8ch_sdi3: i2s0-8 1764 i2s0_8ch_sdi3: i2s0-8ch-sdi3 {
1911 rockchip,pins 1765 rockchip,pins =
1912 <3 RK 1766 <3 RK_PB0 2 &pcfg_pull_none>;
1913 }; 1767 };
1914 }; 1768 };
1915 1769
1916 i2s1 { 1770 i2s1 {
1917 i2s1_2ch_mclk: i2s1-2 1771 i2s1_2ch_mclk: i2s1-2ch-mclk {
1918 rockchip,pins 1772 rockchip,pins =
1919 <2 RK 1773 <2 RK_PC3 1 &pcfg_pull_none>;
1920 }; 1774 };
1921 1775
1922 i2s1_2ch_sclk: i2s1-2 1776 i2s1_2ch_sclk: i2s1-2ch-sclk {
1923 rockchip,pins 1777 rockchip,pins =
1924 <2 RK 1778 <2 RK_PC2 1 &pcfg_pull_none>;
1925 }; 1779 };
1926 1780
1927 i2s1_2ch_lrck: i2s1-2 1781 i2s1_2ch_lrck: i2s1-2ch-lrck {
1928 rockchip,pins 1782 rockchip,pins =
1929 <2 RK 1783 <2 RK_PC1 1 &pcfg_pull_none>;
1930 }; 1784 };
1931 1785
1932 i2s1_2ch_sdi: i2s1-2c 1786 i2s1_2ch_sdi: i2s1-2ch-sdi {
1933 rockchip,pins 1787 rockchip,pins =
1934 <2 RK 1788 <2 RK_PC5 1 &pcfg_pull_none>;
1935 }; 1789 };
1936 1790
1937 i2s1_2ch_sdo: i2s1-2c 1791 i2s1_2ch_sdo: i2s1-2ch-sdo {
1938 rockchip,pins 1792 rockchip,pins =
1939 <2 RK 1793 <2 RK_PC4 1 &pcfg_pull_none>;
1940 }; 1794 };
1941 }; 1795 };
1942 1796
1943 i2s2 { 1797 i2s2 {
1944 i2s2_2ch_mclk: i2s2-2 1798 i2s2_2ch_mclk: i2s2-2ch-mclk {
1945 rockchip,pins 1799 rockchip,pins =
1946 <3 RK 1800 <3 RK_PA1 2 &pcfg_pull_none>;
1947 }; 1801 };
1948 1802
1949 i2s2_2ch_sclk: i2s2-2 1803 i2s2_2ch_sclk: i2s2-2ch-sclk {
1950 rockchip,pins 1804 rockchip,pins =
1951 <3 RK 1805 <3 RK_PA2 2 &pcfg_pull_none>;
1952 }; 1806 };
1953 1807
1954 i2s2_2ch_lrck: i2s2-2 1808 i2s2_2ch_lrck: i2s2-2ch-lrck {
1955 rockchip,pins 1809 rockchip,pins =
1956 <3 RK 1810 <3 RK_PA3 2 &pcfg_pull_none>;
1957 }; 1811 };
1958 1812
1959 i2s2_2ch_sdi: i2s2-2c 1813 i2s2_2ch_sdi: i2s2-2ch-sdi {
1960 rockchip,pins 1814 rockchip,pins =
1961 <3 RK 1815 <3 RK_PA5 2 &pcfg_pull_none>;
1962 }; 1816 };
1963 1817
1964 i2s2_2ch_sdo: i2s2-2c 1818 i2s2_2ch_sdo: i2s2-2ch-sdo {
1965 rockchip,pins 1819 rockchip,pins =
1966 <3 RK 1820 <3 RK_PA7 2 &pcfg_pull_none>;
1967 }; 1821 };
1968 }; 1822 };
1969 1823
1970 sdmmc { 1824 sdmmc {
1971 sdmmc_clk: sdmmc-clk 1825 sdmmc_clk: sdmmc-clk {
1972 rockchip,pins 1826 rockchip,pins =
1973 <1 RK 1827 <1 RK_PD6 1 &pcfg_pull_none_8ma>;
1974 }; 1828 };
1975 1829
1976 sdmmc_cmd: sdmmc-cmd 1830 sdmmc_cmd: sdmmc-cmd {
1977 rockchip,pins 1831 rockchip,pins =
1978 <1 RK 1832 <1 RK_PD7 1 &pcfg_pull_up_8ma>;
1979 }; 1833 };
1980 1834
1981 sdmmc_det: sdmmc-det 1835 sdmmc_det: sdmmc-det {
1982 rockchip,pins 1836 rockchip,pins =
1983 <0 RK 1837 <0 RK_PA3 1 &pcfg_pull_up_8ma>;
1984 }; 1838 };
1985 1839
1986 sdmmc_bus1: sdmmc-bus 1840 sdmmc_bus1: sdmmc-bus1 {
1987 rockchip,pins 1841 rockchip,pins =
1988 <1 RK 1842 <1 RK_PD2 1 &pcfg_pull_up_8ma>;
1989 }; 1843 };
1990 1844
1991 sdmmc_bus4: sdmmc-bus 1845 sdmmc_bus4: sdmmc-bus4 {
1992 rockchip,pins 1846 rockchip,pins =
1993 <1 RK 1847 <1 RK_PD2 1 &pcfg_pull_up_8ma>,
1994 <1 RK 1848 <1 RK_PD3 1 &pcfg_pull_up_8ma>,
1995 <1 RK 1849 <1 RK_PD4 1 &pcfg_pull_up_8ma>,
1996 <1 RK 1850 <1 RK_PD5 1 &pcfg_pull_up_8ma>;
1997 }; 1851 };
1998 }; 1852 };
1999 1853
2000 sdio { 1854 sdio {
2001 sdio_clk: sdio-clk { 1855 sdio_clk: sdio-clk {
2002 rockchip,pins 1856 rockchip,pins =
2003 <1 RK 1857 <1 RK_PC5 1 &pcfg_pull_none>;
2004 }; 1858 };
2005 1859
2006 sdio_cmd: sdio-cmd { 1860 sdio_cmd: sdio-cmd {
2007 rockchip,pins 1861 rockchip,pins =
2008 <1 RK 1862 <1 RK_PC4 1 &pcfg_pull_up>;
2009 }; 1863 };
2010 1864
2011 sdio_bus4: sdio-bus4 1865 sdio_bus4: sdio-bus4 {
2012 rockchip,pins 1866 rockchip,pins =
2013 <1 RK 1867 <1 RK_PC6 1 &pcfg_pull_up>,
2014 <1 RK 1868 <1 RK_PC7 1 &pcfg_pull_up>,
2015 <1 RK 1869 <1 RK_PD0 1 &pcfg_pull_up>,
2016 <1 RK 1870 <1 RK_PD1 1 &pcfg_pull_up>;
2017 }; 1871 };
2018 }; 1872 };
2019 1873
2020 emmc { 1874 emmc {
2021 emmc_clk: emmc-clk { 1875 emmc_clk: emmc-clk {
2022 rockchip,pins 1876 rockchip,pins =
2023 <1 RK 1877 <1 RK_PB1 2 &pcfg_pull_none_8ma>;
2024 }; 1878 };
2025 1879
2026 emmc_cmd: emmc-cmd { 1880 emmc_cmd: emmc-cmd {
2027 rockchip,pins 1881 rockchip,pins =
2028 <1 RK 1882 <1 RK_PB2 2 &pcfg_pull_up_8ma>;
2029 }; 1883 };
2030 1884
2031 emmc_rstnout: emmc-rs 1885 emmc_rstnout: emmc-rstnout {
2032 rockchip,pins 1886 rockchip,pins =
2033 <1 RK 1887 <1 RK_PB3 2 &pcfg_pull_none>;
2034 }; 1888 };
2035 1889
2036 emmc_bus1: emmc-bus1 1890 emmc_bus1: emmc-bus1 {
2037 rockchip,pins 1891 rockchip,pins =
2038 <1 RK 1892 <1 RK_PA0 2 &pcfg_pull_up_8ma>;
2039 }; 1893 };
2040 1894
2041 emmc_bus4: emmc-bus4 1895 emmc_bus4: emmc-bus4 {
2042 rockchip,pins 1896 rockchip,pins =
2043 <1 RK 1897 <1 RK_PA0 2 &pcfg_pull_up_8ma>,
2044 <1 RK 1898 <1 RK_PA1 2 &pcfg_pull_up_8ma>,
2045 <1 RK 1899 <1 RK_PA2 2 &pcfg_pull_up_8ma>,
2046 <1 RK 1900 <1 RK_PA3 2 &pcfg_pull_up_8ma>;
2047 }; 1901 };
2048 1902
2049 emmc_bus8: emmc-bus8 1903 emmc_bus8: emmc-bus8 {
2050 rockchip,pins 1904 rockchip,pins =
2051 <1 RK 1905 <1 RK_PA0 2 &pcfg_pull_up_8ma>,
2052 <1 RK 1906 <1 RK_PA1 2 &pcfg_pull_up_8ma>,
2053 <1 RK 1907 <1 RK_PA2 2 &pcfg_pull_up_8ma>,
2054 <1 RK 1908 <1 RK_PA3 2 &pcfg_pull_up_8ma>,
2055 <1 RK 1909 <1 RK_PA4 2 &pcfg_pull_up_8ma>,
2056 <1 RK 1910 <1 RK_PA5 2 &pcfg_pull_up_8ma>,
2057 <1 RK 1911 <1 RK_PA6 2 &pcfg_pull_up_8ma>,
2058 <1 RK 1912 <1 RK_PA7 2 &pcfg_pull_up_8ma>;
2059 }; 1913 };
2060 }; 1914 };
2061 1915
2062 flash { 1916 flash {
2063 flash_cs0: flash-cs0 1917 flash_cs0: flash-cs0 {
2064 rockchip,pins 1918 rockchip,pins =
2065 <1 RK 1919 <1 RK_PB0 1 &pcfg_pull_none>;
2066 }; 1920 };
2067 1921
2068 flash_rdy: flash-rdy 1922 flash_rdy: flash-rdy {
2069 rockchip,pins 1923 rockchip,pins =
2070 <1 RK 1924 <1 RK_PB1 1 &pcfg_pull_none>;
2071 }; 1925 };
2072 1926
2073 flash_dqs: flash-dqs 1927 flash_dqs: flash-dqs {
2074 rockchip,pins 1928 rockchip,pins =
2075 <1 RK 1929 <1 RK_PB2 1 &pcfg_pull_none>;
2076 }; 1930 };
2077 1931
2078 flash_ale: flash-ale 1932 flash_ale: flash-ale {
2079 rockchip,pins 1933 rockchip,pins =
2080 <1 RK 1934 <1 RK_PB3 1 &pcfg_pull_none>;
2081 }; 1935 };
2082 1936
2083 flash_cle: flash-cle 1937 flash_cle: flash-cle {
2084 rockchip,pins 1938 rockchip,pins =
2085 <1 RK 1939 <1 RK_PB4 1 &pcfg_pull_none>;
2086 }; 1940 };
2087 1941
2088 flash_wrn: flash-wrn 1942 flash_wrn: flash-wrn {
2089 rockchip,pins 1943 rockchip,pins =
2090 <1 RK 1944 <1 RK_PB5 1 &pcfg_pull_none>;
2091 }; 1945 };
2092 1946
2093 flash_csl: flash-csl 1947 flash_csl: flash-csl {
2094 rockchip,pins 1948 rockchip,pins =
2095 <1 RK 1949 <1 RK_PB6 1 &pcfg_pull_none>;
2096 }; 1950 };
2097 1951
2098 flash_rdn: flash-rdn 1952 flash_rdn: flash-rdn {
2099 rockchip,pins 1953 rockchip,pins =
2100 <1 RK 1954 <1 RK_PB7 1 &pcfg_pull_none>;
2101 }; 1955 };
2102 1956
2103 flash_bus8: flash-bus 1957 flash_bus8: flash-bus8 {
2104 rockchip,pins 1958 rockchip,pins =
2105 <1 RK 1959 <1 RK_PA0 1 &pcfg_pull_up_12ma>,
2106 <1 RK 1960 <1 RK_PA1 1 &pcfg_pull_up_12ma>,
2107 <1 RK 1961 <1 RK_PA2 1 &pcfg_pull_up_12ma>,
2108 <1 RK 1962 <1 RK_PA3 1 &pcfg_pull_up_12ma>,
2109 <1 RK 1963 <1 RK_PA4 1 &pcfg_pull_up_12ma>,
2110 <1 RK 1964 <1 RK_PA5 1 &pcfg_pull_up_12ma>,
2111 <1 RK 1965 <1 RK_PA6 1 &pcfg_pull_up_12ma>,
2112 <1 RK 1966 <1 RK_PA7 1 &pcfg_pull_up_12ma>;
2113 }; <<
2114 }; <<
2115 <<
2116 sfc { <<
2117 sfc_bus4: sfc-bus4 { <<
2118 rockchip,pins <<
2119 <1 RK <<
2120 <1 RK <<
2121 <1 RK <<
2122 <1 RK <<
2123 }; <<
2124 <<
2125 sfc_bus2: sfc-bus2 { <<
2126 rockchip,pins <<
2127 <1 RK <<
2128 <1 RK <<
2129 }; <<
2130 <<
2131 sfc_cs0: sfc-cs0 { <<
2132 rockchip,pins <<
2133 <1 RK <<
2134 }; <<
2135 <<
2136 sfc_clk: sfc-clk { <<
2137 rockchip,pins <<
2138 <1 RK <<
2139 }; 1967 };
2140 }; 1968 };
2141 1969
2142 lcdc { 1970 lcdc {
2143 lcdc_rgb_dclk_pin: lc 1971 lcdc_rgb_dclk_pin: lcdc-rgb-dclk-pin {
2144 rockchip,pins 1972 rockchip,pins =
2145 <3 RK 1973 <3 RK_PA0 1 &pcfg_pull_none_12ma>;
2146 }; 1974 };
2147 1975
2148 lcdc_rgb_m0_hsync_pin 1976 lcdc_rgb_m0_hsync_pin: lcdc-rgb-m0-hsync-pin {
2149 rockchip,pins 1977 rockchip,pins =
2150 <3 RK 1978 <3 RK_PA1 1 &pcfg_pull_none_12ma>;
2151 }; 1979 };
2152 1980
2153 lcdc_rgb_m0_vsync_pin 1981 lcdc_rgb_m0_vsync_pin: lcdc-rgb-m0-vsync-pin {
2154 rockchip,pins 1982 rockchip,pins =
2155 <3 RK 1983 <3 RK_PA2 1 &pcfg_pull_none_12ma>;
2156 }; 1984 };
2157 1985
2158 lcdc_rgb_m0_den_pin: 1986 lcdc_rgb_m0_den_pin: lcdc-rgb-m0-den-pin {
2159 rockchip,pins 1987 rockchip,pins =
2160 <3 RK 1988 <3 RK_PA3 1 &pcfg_pull_none_12ma>;
2161 }; 1989 };
2162 1990
2163 lcdc_rgb888_m0_data_p 1991 lcdc_rgb888_m0_data_pins: lcdc-rgb888-m0-data-pins {
2164 rockchip,pins 1992 rockchip,pins =
2165 <3 RK 1993 <3 RK_PA7 1 &pcfg_pull_none_8ma>, /* lcdc_d3 */
2166 <3 RK 1994 <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */
2167 <3 RK 1995 <3 RK_PA5 1 &pcfg_pull_none_8ma>, /* lcdc_d1 */
2168 <3 RK 1996 <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */
2169 <3 RK 1997 <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */
2170 <3 RK 1998 <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */
2171 <3 RK 1999 <3 RK_PB1 1 &pcfg_pull_none_8ma>, /* lcdc_d5 */
2172 <3 RK 2000 <3 RK_PB0 1 &pcfg_pull_none_8ma>, /* lcdc_d4 */
2173 <3 RK 2001 <3 RK_PB7 1 &pcfg_pull_none_8ma>, /* lcdc_d11 */
2174 <3 RK 2002 <3 RK_PB6 1 &pcfg_pull_none_8ma>, /* lcdc_d10 */
2175 <3 RK 2003 <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */
2176 <3 RK 2004 <3 RK_PB4 1 &pcfg_pull_none_8ma>, /* lcdc_d8 */
2177 <3 RK 2005 <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */
2178 <3 RK 2006 <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */
2179 <3 RK 2007 <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */
2180 <3 RK 2008 <3 RK_PC0 1 &pcfg_pull_none_8ma>, /* lcdc_d12 */
2181 <3 RK 2009 <3 RK_PC7 1 &pcfg_pull_none_8ma>, /* lcdc_d19 */
2182 <3 RK 2010 <3 RK_PC6 1 &pcfg_pull_none_8ma>, /* lcdc_d18 */
2183 <3 RK 2011 <3 RK_PC5 1 &pcfg_pull_none_8ma>, /* lcdc_d17 */
2184 <3 RK 2012 <3 RK_PC4 1 &pcfg_pull_none_8ma>, /* lcdc_d16 */
2185 <3 RK 2013 <3 RK_PD3 1 &pcfg_pull_none_8ma>, /* lcdc_d23 */
2186 <3 RK 2014 <3 RK_PD2 1 &pcfg_pull_none_8ma>, /* lcdc_d22 */
2187 <3 RK 2015 <3 RK_PD1 1 &pcfg_pull_none_8ma>, /* lcdc_d21 */
2188 <3 RK 2016 <3 RK_PD0 1 &pcfg_pull_none_8ma>; /* lcdc_d20 */
2189 }; 2017 };
2190 2018
2191 lcdc_rgb666_m0_data_p 2019 lcdc_rgb666_m0_data_pins: lcdc-rgb666-m0-data-pins {
2192 rockchip,pins 2020 rockchip,pins =
2193 <3 RK 2021 <3 RK_PA7 1 &pcfg_pull_none_8ma>, /* lcdc_d3 */
2194 <3 RK 2022 <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */
2195 <3 RK 2023 <3 RK_PA5 1 &pcfg_pull_none_8ma>, /* lcdc_d1 */
2196 <3 RK 2024 <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */
2197 <3 RK 2025 <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */
2198 <3 RK 2026 <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */
2199 <3 RK 2027 <3 RK_PB1 1 &pcfg_pull_none_8ma>, /* lcdc_d5 */
2200 <3 RK 2028 <3 RK_PB0 1 &pcfg_pull_none_8ma>, /* lcdc_d4 */
2201 <3 RK 2029 <3 RK_PB7 1 &pcfg_pull_none_8ma>, /* lcdc_d11 */
2202 <3 RK 2030 <3 RK_PB6 1 &pcfg_pull_none_8ma>, /* lcdc_d10 */
2203 <3 RK 2031 <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */
2204 <3 RK 2032 <3 RK_PB4 1 &pcfg_pull_none_8ma>, /* lcdc_d8 */
2205 <3 RK 2033 <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */
2206 <3 RK 2034 <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */
2207 <3 RK 2035 <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */
2208 <3 RK 2036 <3 RK_PC0 1 &pcfg_pull_none_8ma>, /* lcdc_d12 */
2209 <3 RK 2037 <3 RK_PC5 1 &pcfg_pull_none_8ma>, /* lcdc_d17 */
2210 <3 RK 2038 <3 RK_PC4 1 &pcfg_pull_none_8ma>; /* lcdc_d16 */
2211 }; 2039 };
2212 2040
2213 lcdc_rgb565_m0_data_p 2041 lcdc_rgb565_m0_data_pins: lcdc-rgb565-m0-data-pins {
2214 rockchip,pins 2042 rockchip,pins =
2215 <3 RK 2043 <3 RK_PA7 1 &pcfg_pull_none_8ma>, /* lcdc_d3 */
2216 <3 RK 2044 <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */
2217 <3 RK 2045 <3 RK_PA5 1 &pcfg_pull_none_8ma>, /* lcdc_d1 */
2218 <3 RK 2046 <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */
2219 <3 RK 2047 <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */
2220 <3 RK 2048 <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */
2221 <3 RK 2049 <3 RK_PB1 1 &pcfg_pull_none_8ma>, /* lcdc_d5 */
2222 <3 RK 2050 <3 RK_PB0 1 &pcfg_pull_none_8ma>, /* lcdc_d4 */
2223 <3 RK 2051 <3 RK_PB7 1 &pcfg_pull_none_8ma>, /* lcdc_d11 */
2224 <3 RK 2052 <3 RK_PB6 1 &pcfg_pull_none_8ma>, /* lcdc_d10 */
2225 <3 RK 2053 <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */
2226 <3 RK 2054 <3 RK_PB4 1 &pcfg_pull_none_8ma>, /* lcdc_d8 */
2227 <3 RK 2055 <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */
2228 <3 RK 2056 <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */
2229 <3 RK 2057 <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */
2230 <3 RK 2058 <3 RK_PC0 1 &pcfg_pull_none_8ma>; /* lcdc_d12 */
2231 }; 2059 };
2232 2060
2233 lcdc_rgb888_m1_data_p 2061 lcdc_rgb888_m1_data_pins: lcdc-rgb888-m1-data-pins {
2234 rockchip,pins 2062 rockchip,pins =
2235 <3 RK 2063 <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */
2236 <3 RK 2064 <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */
2237 <3 RK 2065 <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */
2238 <3 RK 2066 <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */
2239 <3 RK 2067 <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */
2240 <3 RK 2068 <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */
2241 <3 RK 2069 <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */
2242 <3 RK 2070 <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */
2243 <3 RK 2071 <3 RK_PC0 1 &pcfg_pull_none_8ma>, /* lcdc_d12 */
2244 <3 RK 2072 <3 RK_PC7 1 &pcfg_pull_none_8ma>, /* lcdc_d19 */
2245 <3 RK 2073 <3 RK_PC6 1 &pcfg_pull_none_8ma>, /* lcdc_d18 */
2246 <3 RK 2074 <3 RK_PC5 1 &pcfg_pull_none_8ma>, /* lcdc_d17 */
2247 <3 RK 2075 <3 RK_PC4 1 &pcfg_pull_none_8ma>, /* lcdc_d16 */
2248 <3 RK 2076 <3 RK_PD3 1 &pcfg_pull_none_8ma>, /* lcdc_d23 */
2249 <3 RK 2077 <3 RK_PD2 1 &pcfg_pull_none_8ma>, /* lcdc_d22 */
2250 <3 RK 2078 <3 RK_PD1 1 &pcfg_pull_none_8ma>, /* lcdc_d21 */
2251 <3 RK 2079 <3 RK_PD0 1 &pcfg_pull_none_8ma>; /* lcdc_d20 */
2252 }; 2080 };
2253 2081
2254 lcdc_rgb666_m1_data_p 2082 lcdc_rgb666_m1_data_pins: lcdc-rgb666-m1-data-pins {
2255 rockchip,pins 2083 rockchip,pins =
2256 <3 RK 2084 <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */
2257 <3 RK 2085 <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */
2258 <3 RK 2086 <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */
2259 <3 RK 2087 <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */
2260 <3 RK 2088 <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */
2261 <3 RK 2089 <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */
2262 <3 RK 2090 <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */
2263 <3 RK 2091 <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */
2264 <3 RK 2092 <3 RK_PC0 1 &pcfg_pull_none_8ma>, /* lcdc_d12 */
2265 <3 RK 2093 <3 RK_PC5 1 &pcfg_pull_none_8ma>, /* lcdc_d17 */
2266 <3 RK 2094 <3 RK_PC4 1 &pcfg_pull_none_8ma>; /* lcdc_d16 */
2267 }; 2095 };
2268 2096
2269 lcdc_rgb565_m1_data_p 2097 lcdc_rgb565_m1_data_pins: lcdc-rgb565-m1-data-pins {
2270 rockchip,pins 2098 rockchip,pins =
2271 <3 RK 2099 <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */
2272 <3 RK 2100 <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */
2273 <3 RK 2101 <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */
2274 <3 RK 2102 <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */
2275 <3 RK 2103 <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */
2276 <3 RK 2104 <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */
2277 <3 RK 2105 <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */
2278 <3 RK 2106 <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */
2279 <3 RK 2107 <3 RK_PC0 1 &pcfg_pull_none_8ma>; /* lcdc_d12 */
2280 }; 2108 };
2281 }; 2109 };
2282 2110
2283 pwm0 { 2111 pwm0 {
2284 pwm0_pin: pwm0-pin { 2112 pwm0_pin: pwm0-pin {
2285 rockchip,pins 2113 rockchip,pins =
2286 <0 RK 2114 <0 RK_PB7 1 &pcfg_pull_none>;
2287 }; 2115 };
2288 }; 2116 };
2289 2117
2290 pwm1 { 2118 pwm1 {
2291 pwm1_pin: pwm1-pin { 2119 pwm1_pin: pwm1-pin {
2292 rockchip,pins 2120 rockchip,pins =
2293 <0 RK 2121 <0 RK_PC0 1 &pcfg_pull_none>;
2294 }; 2122 };
2295 }; 2123 };
2296 2124
2297 pwm2 { 2125 pwm2 {
2298 pwm2_pin: pwm2-pin { 2126 pwm2_pin: pwm2-pin {
2299 rockchip,pins 2127 rockchip,pins =
2300 <2 RK 2128 <2 RK_PB5 1 &pcfg_pull_none>;
2301 }; 2129 };
2302 }; 2130 };
2303 2131
2304 pwm3 { 2132 pwm3 {
2305 pwm3_pin: pwm3-pin { 2133 pwm3_pin: pwm3-pin {
2306 rockchip,pins 2134 rockchip,pins =
2307 <0 RK 2135 <0 RK_PC1 1 &pcfg_pull_none>;
2308 }; 2136 };
2309 }; 2137 };
2310 2138
2311 pwm4 { 2139 pwm4 {
2312 pwm4_pin: pwm4-pin { 2140 pwm4_pin: pwm4-pin {
2313 rockchip,pins 2141 rockchip,pins =
2314 <3 RK 2142 <3 RK_PC2 3 &pcfg_pull_none>;
2315 }; 2143 };
2316 }; 2144 };
2317 2145
2318 pwm5 { 2146 pwm5 {
2319 pwm5_pin: pwm5-pin { 2147 pwm5_pin: pwm5-pin {
2320 rockchip,pins 2148 rockchip,pins =
2321 <3 RK 2149 <3 RK_PC3 3 &pcfg_pull_none>;
2322 }; 2150 };
2323 }; 2151 };
2324 2152
2325 pwm6 { 2153 pwm6 {
2326 pwm6_pin: pwm6-pin { 2154 pwm6_pin: pwm6-pin {
2327 rockchip,pins 2155 rockchip,pins =
2328 <3 RK 2156 <3 RK_PC4 3 &pcfg_pull_none>;
2329 }; 2157 };
2330 }; 2158 };
2331 2159
2332 pwm7 { 2160 pwm7 {
2333 pwm7_pin: pwm7-pin { 2161 pwm7_pin: pwm7-pin {
2334 rockchip,pins 2162 rockchip,pins =
2335 <3 RK 2163 <3 RK_PC5 3 &pcfg_pull_none>;
2336 }; 2164 };
2337 }; 2165 };
2338 2166
2339 gmac { 2167 gmac {
2340 rmii_pins: rmii-pins 2168 rmii_pins: rmii-pins {
2341 rockchip,pins 2169 rockchip,pins =
2342 <2 RK 2170 <2 RK_PA0 2 &pcfg_pull_none_12ma>, /* mac_txen */
2343 <2 RK 2171 <2 RK_PA1 2 &pcfg_pull_none_12ma>, /* mac_txd1 */
2344 <2 RK 2172 <2 RK_PA2 2 &pcfg_pull_none_12ma>, /* mac_txd0 */
2345 <2 RK 2173 <2 RK_PA3 2 &pcfg_pull_none>, /* mac_rxd0 */
2346 <2 RK 2174 <2 RK_PA4 2 &pcfg_pull_none>, /* mac_rxd1 */
2347 <2 RK 2175 <2 RK_PA5 2 &pcfg_pull_none>, /* mac_rxer */
2348 <2 RK 2176 <2 RK_PA6 2 &pcfg_pull_none>, /* mac_rxdv */
2349 <2 RK 2177 <2 RK_PA7 2 &pcfg_pull_none>, /* mac_mdio */
2350 <2 RK 2178 <2 RK_PB1 2 &pcfg_pull_none>; /* mac_mdc */
2351 }; 2179 };
2352 2180
2353 mac_refclk_12ma: mac- 2181 mac_refclk_12ma: mac-refclk-12ma {
2354 rockchip,pins 2182 rockchip,pins =
2355 <2 RK 2183 <2 RK_PB2 2 &pcfg_pull_none_12ma>;
2356 }; 2184 };
2357 2185
2358 mac_refclk: mac-refcl 2186 mac_refclk: mac-refclk {
2359 rockchip,pins 2187 rockchip,pins =
2360 <2 RK 2188 <2 RK_PB2 2 &pcfg_pull_none>;
2361 }; 2189 };
2362 }; 2190 };
2363 2191
2364 cif-m0 { 2192 cif-m0 {
2365 cif_clkout_m0: cif-cl 2193 cif_clkout_m0: cif-clkout-m0 {
2366 rockchip,pins 2194 rockchip,pins =
2367 <2 RK 2195 <2 RK_PB3 1 &pcfg_pull_none>;
2368 }; 2196 };
2369 2197
2370 dvp_d2d9_m0: dvp-d2d9 2198 dvp_d2d9_m0: dvp-d2d9-m0 {
2371 rockchip,pins 2199 rockchip,pins =
2372 <2 RK 2200 <2 RK_PA0 1 &pcfg_pull_none>, /* cif_data2 */
2373 <2 RK 2201 <2 RK_PA1 1 &pcfg_pull_none>, /* cif_data3 */
2374 <2 RK 2202 <2 RK_PA2 1 &pcfg_pull_none>, /* cif_data4 */
2375 <2 RK 2203 <2 RK_PA3 1 &pcfg_pull_none>, /* cif_data5 */
2376 <2 RK 2204 <2 RK_PA4 1 &pcfg_pull_none>, /* cif_data6 */
2377 <2 RK 2205 <2 RK_PA5 1 &pcfg_pull_none>, /* cif_data7 */
2378 <2 RK 2206 <2 RK_PA6 1 &pcfg_pull_none>, /* cif_data8 */
2379 <2 RK 2207 <2 RK_PA7 1 &pcfg_pull_none>, /* cif_data9 */
2380 <2 RK 2208 <2 RK_PB0 1 &pcfg_pull_none>, /* cif_sync */
2381 <2 RK 2209 <2 RK_PB1 1 &pcfg_pull_none>, /* cif_href */
2382 <2 RK 2210 <2 RK_PB2 1 &pcfg_pull_none>, /* cif_clkin */
2383 <2 RK 2211 <2 RK_PB3 1 &pcfg_pull_none>; /* cif_clkout */
2384 }; 2212 };
2385 2213
2386 dvp_d0d1_m0: dvp-d0d1 2214 dvp_d0d1_m0: dvp-d0d1-m0 {
2387 rockchip,pins 2215 rockchip,pins =
2388 <2 RK 2216 <2 RK_PB4 1 &pcfg_pull_none>, /* cif_data0 */
2389 <2 RK 2217 <2 RK_PB6 1 &pcfg_pull_none>; /* cif_data1 */
2390 }; 2218 };
2391 2219
2392 dvp_d10d11_m0:d10-d11 2220 dvp_d10d11_m0:d10-d11-m0 {
2393 rockchip,pins 2221 rockchip,pins =
2394 <2 RK 2222 <2 RK_PB7 1 &pcfg_pull_none>, /* cif_data10 */
2395 <2 RK 2223 <2 RK_PC0 1 &pcfg_pull_none>; /* cif_data11 */
2396 }; 2224 };
2397 }; 2225 };
2398 2226
2399 cif-m1 { 2227 cif-m1 {
2400 cif_clkout_m1: cif-cl 2228 cif_clkout_m1: cif-clkout-m1 {
2401 rockchip,pins 2229 rockchip,pins =
2402 <3 RK 2230 <3 RK_PD0 3 &pcfg_pull_none>;
2403 }; 2231 };
2404 2232
2405 dvp_d2d9_m1: dvp-d2d9 2233 dvp_d2d9_m1: dvp-d2d9-m1 {
2406 rockchip,pins 2234 rockchip,pins =
2407 <3 RK 2235 <3 RK_PA3 3 &pcfg_pull_none>, /* cif_data2 */
2408 <3 RK 2236 <3 RK_PA5 3 &pcfg_pull_none>, /* cif_data3 */
2409 <3 RK 2237 <3 RK_PA7 3 &pcfg_pull_none>, /* cif_data4 */
2410 <3 RK 2238 <3 RK_PB0 3 &pcfg_pull_none>, /* cif_data5 */
2411 <3 RK 2239 <3 RK_PB1 3 &pcfg_pull_none>, /* cif_data6 */
2412 <3 RK 2240 <3 RK_PB4 3 &pcfg_pull_none>, /* cif_data7 */
2413 <3 RK 2241 <3 RK_PB6 3 &pcfg_pull_none>, /* cif_data8 */
2414 <3 RK 2242 <3 RK_PB7 3 &pcfg_pull_none>, /* cif_data9 */
2415 <3 RK 2243 <3 RK_PD1 3 &pcfg_pull_none>, /* cif_sync */
2416 <3 RK 2244 <3 RK_PD2 3 &pcfg_pull_none>, /* cif_href */
2417 <3 RK 2245 <3 RK_PD3 3 &pcfg_pull_none>, /* cif_clkin */
2418 <3 RK 2246 <3 RK_PD0 3 &pcfg_pull_none>; /* cif_clkout */
2419 }; 2247 };
2420 2248
2421 dvp_d0d1_m1: dvp-d0d1 2249 dvp_d0d1_m1: dvp-d0d1-m1 {
2422 rockchip,pins 2250 rockchip,pins =
2423 <3 RK 2251 <3 RK_PA1 3 &pcfg_pull_none>, /* cif_data0 */
2424 <3 RK 2252 <3 RK_PA2 3 &pcfg_pull_none>; /* cif_data1 */
2425 }; 2253 };
2426 2254
2427 dvp_d10d11_m1:d10-d11 2255 dvp_d10d11_m1:d10-d11-m1 {
2428 rockchip,pins 2256 rockchip,pins =
2429 <3 RK 2257 <3 RK_PC6 3 &pcfg_pull_none>, /* cif_data10 */
2430 <3 RK 2258 <3 RK_PC7 3 &pcfg_pull_none>; /* cif_data11 */
2431 }; 2259 };
2432 }; 2260 };
2433 2261
2434 isp { 2262 isp {
2435 isp_prelight: isp-pre 2263 isp_prelight: isp-prelight {
2436 rockchip,pins 2264 rockchip,pins =
2437 <3 RK 2265 <3 RK_PD1 4 &pcfg_pull_none>;
2438 }; 2266 };
2439 }; 2267 };
2440 }; 2268 };
2441 }; 2269 };
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