1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /* 2 /*
3 * Copyright (c) 2018 Fuzhou Rockchip Electron 3 * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd
4 */ 4 */
5 5
6 #include <dt-bindings/clock/px30-cru.h> 6 #include <dt-bindings/clock/px30-cru.h>
7 #include <dt-bindings/gpio/gpio.h> 7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/interrupt-controller/arm 8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/interrupt-controller/irq 9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/pinctrl/rockchip.h> 10 #include <dt-bindings/pinctrl/rockchip.h>
11 #include <dt-bindings/power/px30-power.h> 11 #include <dt-bindings/power/px30-power.h>
12 #include <dt-bindings/soc/rockchip,boot-mode.h 12 #include <dt-bindings/soc/rockchip,boot-mode.h>
13 #include <dt-bindings/thermal/thermal.h> 13 #include <dt-bindings/thermal/thermal.h>
14 14
15 / { 15 / {
16 compatible = "rockchip,px30"; 16 compatible = "rockchip,px30";
17 17
18 interrupt-parent = <&gic>; 18 interrupt-parent = <&gic>;
19 #address-cells = <2>; 19 #address-cells = <2>;
20 #size-cells = <2>; 20 #size-cells = <2>;
21 21
22 aliases { 22 aliases {
>> 23 ethernet0 = &gmac;
23 i2c0 = &i2c0; 24 i2c0 = &i2c0;
24 i2c1 = &i2c1; 25 i2c1 = &i2c1;
25 i2c2 = &i2c2; 26 i2c2 = &i2c2;
26 i2c3 = &i2c3; 27 i2c3 = &i2c3;
27 serial0 = &uart0; 28 serial0 = &uart0;
28 serial1 = &uart1; 29 serial1 = &uart1;
29 serial2 = &uart2; 30 serial2 = &uart2;
30 serial3 = &uart3; 31 serial3 = &uart3;
31 serial4 = &uart4; 32 serial4 = &uart4;
32 serial5 = &uart5; 33 serial5 = &uart5;
33 spi0 = &spi0; 34 spi0 = &spi0;
34 spi1 = &spi1; 35 spi1 = &spi1;
35 }; 36 };
36 37
37 cpus { 38 cpus {
38 #address-cells = <2>; 39 #address-cells = <2>;
39 #size-cells = <0>; 40 #size-cells = <0>;
40 41
41 cpu0: cpu@0 { 42 cpu0: cpu@0 {
42 device_type = "cpu"; 43 device_type = "cpu";
43 compatible = "arm,cort 44 compatible = "arm,cortex-a35";
44 reg = <0x0 0x0>; 45 reg = <0x0 0x0>;
45 enable-method = "psci" 46 enable-method = "psci";
46 clocks = <&cru ARMCLK> 47 clocks = <&cru ARMCLK>;
47 #cooling-cells = <2>; 48 #cooling-cells = <2>;
48 cpu-idle-states = <&CP 49 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
49 dynamic-power-coeffici 50 dynamic-power-coefficient = <90>;
50 operating-points-v2 = 51 operating-points-v2 = <&cpu0_opp_table>;
51 }; 52 };
52 53
53 cpu1: cpu@1 { 54 cpu1: cpu@1 {
54 device_type = "cpu"; 55 device_type = "cpu";
55 compatible = "arm,cort 56 compatible = "arm,cortex-a35";
56 reg = <0x0 0x1>; 57 reg = <0x0 0x1>;
57 enable-method = "psci" 58 enable-method = "psci";
58 clocks = <&cru ARMCLK> 59 clocks = <&cru ARMCLK>;
59 #cooling-cells = <2>; 60 #cooling-cells = <2>;
60 cpu-idle-states = <&CP 61 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
61 dynamic-power-coeffici 62 dynamic-power-coefficient = <90>;
62 operating-points-v2 = 63 operating-points-v2 = <&cpu0_opp_table>;
63 }; 64 };
64 65
65 cpu2: cpu@2 { 66 cpu2: cpu@2 {
66 device_type = "cpu"; 67 device_type = "cpu";
67 compatible = "arm,cort 68 compatible = "arm,cortex-a35";
68 reg = <0x0 0x2>; 69 reg = <0x0 0x2>;
69 enable-method = "psci" 70 enable-method = "psci";
70 clocks = <&cru ARMCLK> 71 clocks = <&cru ARMCLK>;
71 #cooling-cells = <2>; 72 #cooling-cells = <2>;
72 cpu-idle-states = <&CP 73 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
73 dynamic-power-coeffici 74 dynamic-power-coefficient = <90>;
74 operating-points-v2 = 75 operating-points-v2 = <&cpu0_opp_table>;
75 }; 76 };
76 77
77 cpu3: cpu@3 { 78 cpu3: cpu@3 {
78 device_type = "cpu"; 79 device_type = "cpu";
79 compatible = "arm,cort 80 compatible = "arm,cortex-a35";
80 reg = <0x0 0x3>; 81 reg = <0x0 0x3>;
81 enable-method = "psci" 82 enable-method = "psci";
82 clocks = <&cru ARMCLK> 83 clocks = <&cru ARMCLK>;
83 #cooling-cells = <2>; 84 #cooling-cells = <2>;
84 cpu-idle-states = <&CP 85 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
85 dynamic-power-coeffici 86 dynamic-power-coefficient = <90>;
86 operating-points-v2 = 87 operating-points-v2 = <&cpu0_opp_table>;
87 }; 88 };
88 89
89 idle-states { 90 idle-states {
90 entry-method = "psci"; 91 entry-method = "psci";
91 92
92 CPU_SLEEP: cpu-sleep { 93 CPU_SLEEP: cpu-sleep {
93 compatible = " 94 compatible = "arm,idle-state";
94 local-timer-st 95 local-timer-stop;
95 arm,psci-suspe 96 arm,psci-suspend-param = <0x0010000>;
96 entry-latency- 97 entry-latency-us = <120>;
97 exit-latency-u 98 exit-latency-us = <250>;
98 min-residency- 99 min-residency-us = <900>;
99 }; 100 };
100 101
101 CLUSTER_SLEEP: cluster 102 CLUSTER_SLEEP: cluster-sleep {
102 compatible = " 103 compatible = "arm,idle-state";
103 local-timer-st 104 local-timer-stop;
104 arm,psci-suspe 105 arm,psci-suspend-param = <0x1010000>;
105 entry-latency- 106 entry-latency-us = <400>;
106 exit-latency-u 107 exit-latency-us = <500>;
107 min-residency- 108 min-residency-us = <2000>;
108 }; 109 };
109 }; 110 };
110 }; 111 };
111 112
112 cpu0_opp_table: opp-table-0 { !! 113 cpu0_opp_table: cpu0-opp-table {
113 compatible = "operating-points 114 compatible = "operating-points-v2";
114 opp-shared; 115 opp-shared;
115 116
116 opp-600000000 { 117 opp-600000000 {
117 opp-hz = /bits/ 64 <60 118 opp-hz = /bits/ 64 <600000000>;
118 opp-microvolt = <95000 119 opp-microvolt = <950000 950000 1350000>;
119 clock-latency-ns = <40 120 clock-latency-ns = <40000>;
120 opp-suspend; 121 opp-suspend;
121 }; 122 };
122 opp-816000000 { 123 opp-816000000 {
123 opp-hz = /bits/ 64 <81 124 opp-hz = /bits/ 64 <816000000>;
124 opp-microvolt = <10500 125 opp-microvolt = <1050000 1050000 1350000>;
125 clock-latency-ns = <40 126 clock-latency-ns = <40000>;
126 }; 127 };
127 opp-1008000000 { 128 opp-1008000000 {
128 opp-hz = /bits/ 64 <10 129 opp-hz = /bits/ 64 <1008000000>;
129 opp-microvolt = <11750 130 opp-microvolt = <1175000 1175000 1350000>;
130 clock-latency-ns = <40 131 clock-latency-ns = <40000>;
131 }; 132 };
132 opp-1200000000 { 133 opp-1200000000 {
133 opp-hz = /bits/ 64 <12 134 opp-hz = /bits/ 64 <1200000000>;
134 opp-microvolt = <13000 135 opp-microvolt = <1300000 1300000 1350000>;
135 clock-latency-ns = <40 136 clock-latency-ns = <40000>;
136 }; 137 };
137 opp-1296000000 { 138 opp-1296000000 {
138 opp-hz = /bits/ 64 <12 139 opp-hz = /bits/ 64 <1296000000>;
139 opp-microvolt = <13500 140 opp-microvolt = <1350000 1350000 1350000>;
140 clock-latency-ns = <40 141 clock-latency-ns = <40000>;
141 }; 142 };
142 }; 143 };
143 144
144 arm-pmu { 145 arm-pmu {
145 compatible = "arm,cortex-a35-p 146 compatible = "arm,cortex-a35-pmu";
146 interrupts = <GIC_SPI 100 IRQ_ 147 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
147 <GIC_SPI 101 IRQ_ 148 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
148 <GIC_SPI 102 IRQ_ 149 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
149 <GIC_SPI 103 IRQ_ 150 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
150 interrupt-affinity = <&cpu0>, 151 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
151 }; 152 };
152 153
153 display_subsystem: display-subsystem { 154 display_subsystem: display-subsystem {
154 compatible = "rockchip,display 155 compatible = "rockchip,display-subsystem";
155 ports = <&vopb_out>, <&vopl_ou 156 ports = <&vopb_out>, <&vopl_out>;
156 status = "disabled"; 157 status = "disabled";
157 }; 158 };
158 159
159 gmac_clkin: external-gmac-clock { 160 gmac_clkin: external-gmac-clock {
160 compatible = "fixed-clock"; 161 compatible = "fixed-clock";
161 clock-frequency = <50000000>; 162 clock-frequency = <50000000>;
162 clock-output-names = "gmac_clk 163 clock-output-names = "gmac_clkin";
163 #clock-cells = <0>; 164 #clock-cells = <0>;
164 }; 165 };
165 166
166 psci { 167 psci {
167 compatible = "arm,psci-1.0"; 168 compatible = "arm,psci-1.0";
168 method = "smc"; 169 method = "smc";
169 }; 170 };
170 171
171 timer { 172 timer {
172 compatible = "arm,armv8-timer" 173 compatible = "arm,armv8-timer";
173 interrupts = <GIC_PPI 13 (GIC_ 174 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
174 <GIC_PPI 14 (GIC_ 175 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
175 <GIC_PPI 11 (GIC_ 176 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
176 <GIC_PPI 10 (GIC_ 177 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
177 }; 178 };
178 179
179 thermal_zones: thermal-zones { 180 thermal_zones: thermal-zones {
180 soc_thermal: soc-thermal { 181 soc_thermal: soc-thermal {
181 polling-delay-passive 182 polling-delay-passive = <20>;
182 polling-delay = <1000> 183 polling-delay = <1000>;
183 sustainable-power = <7 184 sustainable-power = <750>;
184 thermal-sensors = <&ts 185 thermal-sensors = <&tsadc 0>;
185 186
186 trips { 187 trips {
187 threshold: tri 188 threshold: trip-point-0 {
188 temper 189 temperature = <70000>;
189 hyster 190 hysteresis = <2000>;
190 type = 191 type = "passive";
191 }; 192 };
192 193
193 target: trip-p 194 target: trip-point-1 {
194 temper 195 temperature = <85000>;
195 hyster 196 hysteresis = <2000>;
196 type = 197 type = "passive";
197 }; 198 };
198 199
199 soc_crit: soc- 200 soc_crit: soc-crit {
200 temper 201 temperature = <115000>;
201 hyster 202 hysteresis = <2000>;
202 type = 203 type = "critical";
203 }; 204 };
204 }; 205 };
205 206
206 cooling-maps { 207 cooling-maps {
207 map0 { 208 map0 {
208 trip = 209 trip = <&target>;
209 coolin 210 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
210 contri 211 contribution = <4096>;
211 }; 212 };
>> 213
>> 214 map1 {
>> 215 trip = <&target>;
>> 216 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
>> 217 contribution = <4096>;
>> 218 };
212 }; 219 };
213 }; 220 };
214 221
215 gpu_thermal: gpu-thermal { 222 gpu_thermal: gpu-thermal {
216 polling-delay-passive 223 polling-delay-passive = <100>; /* milliseconds */
217 polling-delay = <1000> 224 polling-delay = <1000>; /* milliseconds */
218 thermal-sensors = <&ts 225 thermal-sensors = <&tsadc 1>;
219 <<
220 trips { <<
221 gpu_threshold: <<
222 temper <<
223 hyster <<
224 type = <<
225 }; <<
226 <<
227 gpu_target: gp <<
228 temper <<
229 hyster <<
230 type = <<
231 }; <<
232 <<
233 gpu_crit: gpu- <<
234 temper <<
235 hyster <<
236 type = <<
237 }; <<
238 }; <<
239 <<
240 cooling-maps { <<
241 map0 { <<
242 trip = <<
243 coolin <<
244 }; <<
245 }; <<
246 }; 226 };
247 }; 227 };
248 228
249 xin24m: xin24m { 229 xin24m: xin24m {
250 compatible = "fixed-clock"; 230 compatible = "fixed-clock";
251 #clock-cells = <0>; 231 #clock-cells = <0>;
252 clock-frequency = <24000000>; 232 clock-frequency = <24000000>;
253 clock-output-names = "xin24m"; 233 clock-output-names = "xin24m";
254 }; 234 };
255 235
256 pmu: power-management@ff000000 { 236 pmu: power-management@ff000000 {
257 compatible = "rockchip,px30-pm 237 compatible = "rockchip,px30-pmu", "syscon", "simple-mfd";
258 reg = <0x0 0xff000000 0x0 0x10 238 reg = <0x0 0xff000000 0x0 0x1000>;
259 239
260 power: power-controller { 240 power: power-controller {
261 compatible = "rockchip 241 compatible = "rockchip,px30-power-controller";
262 #power-domain-cells = 242 #power-domain-cells = <1>;
263 #address-cells = <1>; 243 #address-cells = <1>;
264 #size-cells = <0>; 244 #size-cells = <0>;
265 245
266 /* These power domains 246 /* These power domains are grouped by VD_LOGIC */
267 power-domain@PX30_PD_U 247 power-domain@PX30_PD_USB {
268 reg = <PX30_PD 248 reg = <PX30_PD_USB>;
269 clocks = <&cru 249 clocks = <&cru HCLK_HOST>,
270 <&cru 250 <&cru HCLK_OTG>,
271 <&cru 251 <&cru SCLK_OTG_ADP>;
272 pm_qos = <&qos 252 pm_qos = <&qos_usb_host>, <&qos_usb_otg>;
273 #power-domain- 253 #power-domain-cells = <0>;
274 }; 254 };
275 power-domain@PX30_PD_S 255 power-domain@PX30_PD_SDCARD {
276 reg = <PX30_PD 256 reg = <PX30_PD_SDCARD>;
277 clocks = <&cru 257 clocks = <&cru HCLK_SDMMC>,
278 <&cru 258 <&cru SCLK_SDMMC>;
279 pm_qos = <&qos 259 pm_qos = <&qos_sdmmc>;
280 #power-domain- 260 #power-domain-cells = <0>;
281 }; 261 };
282 power-domain@PX30_PD_G 262 power-domain@PX30_PD_GMAC {
283 reg = <PX30_PD 263 reg = <PX30_PD_GMAC>;
284 clocks = <&cru 264 clocks = <&cru ACLK_GMAC>,
285 <&cru 265 <&cru PCLK_GMAC>,
286 <&cru 266 <&cru SCLK_MAC_REF>,
287 <&cru 267 <&cru SCLK_GMAC_RX_TX>;
288 pm_qos = <&qos 268 pm_qos = <&qos_gmac>;
289 #power-domain- 269 #power-domain-cells = <0>;
290 }; 270 };
291 power-domain@PX30_PD_M 271 power-domain@PX30_PD_MMC_NAND {
292 reg = <PX30_PD 272 reg = <PX30_PD_MMC_NAND>;
293 clocks = <&cru !! 273 clocks = <&cru HCLK_NANDC>,
294 <&cru !! 274 <&cru HCLK_EMMC>,
295 <&cru !! 275 <&cru HCLK_SDIO>,
296 <&cru !! 276 <&cru HCLK_SFC>,
297 <&cru !! 277 <&cru SCLK_EMMC>,
298 <&cru !! 278 <&cru SCLK_NANDC>,
299 <&cru !! 279 <&cru SCLK_SDIO>,
300 <&cru !! 280 <&cru SCLK_SFC>;
301 pm_qos = <&qos 281 pm_qos = <&qos_emmc>, <&qos_nand>,
302 <&qos 282 <&qos_sdio>, <&qos_sfc>;
303 #power-domain- 283 #power-domain-cells = <0>;
304 }; 284 };
305 power-domain@PX30_PD_V 285 power-domain@PX30_PD_VPU {
306 reg = <PX30_PD 286 reg = <PX30_PD_VPU>;
307 clocks = <&cru 287 clocks = <&cru ACLK_VPU>,
308 <&cru 288 <&cru HCLK_VPU>,
309 <&cru 289 <&cru SCLK_CORE_VPU>;
310 pm_qos = <&qos 290 pm_qos = <&qos_vpu>, <&qos_vpu_r128>;
311 #power-domain- 291 #power-domain-cells = <0>;
312 }; 292 };
313 power-domain@PX30_PD_V 293 power-domain@PX30_PD_VO {
314 reg = <PX30_PD 294 reg = <PX30_PD_VO>;
315 clocks = <&cru 295 clocks = <&cru ACLK_RGA>,
316 <&cru 296 <&cru ACLK_VOPB>,
317 <&cru 297 <&cru ACLK_VOPL>,
318 <&cru 298 <&cru DCLK_VOPB>,
319 <&cru 299 <&cru DCLK_VOPL>,
320 <&cru 300 <&cru HCLK_RGA>,
321 <&cru 301 <&cru HCLK_VOPB>,
322 <&cru 302 <&cru HCLK_VOPL>,
323 <&cru 303 <&cru PCLK_MIPI_DSI>,
324 <&cru 304 <&cru SCLK_RGA_CORE>,
325 <&cru 305 <&cru SCLK_VOPB_PWM>;
326 pm_qos = <&qos 306 pm_qos = <&qos_rga_rd>, <&qos_rga_wr>,
327 <&qos 307 <&qos_vop_m0>, <&qos_vop_m1>;
328 #power-domain- 308 #power-domain-cells = <0>;
329 }; 309 };
330 power-domain@PX30_PD_V 310 power-domain@PX30_PD_VI {
331 reg = <PX30_PD 311 reg = <PX30_PD_VI>;
332 clocks = <&cru 312 clocks = <&cru ACLK_CIF>,
333 <&cru 313 <&cru ACLK_ISP>,
334 <&cru 314 <&cru HCLK_CIF>,
335 <&cru 315 <&cru HCLK_ISP>,
336 <&cru 316 <&cru SCLK_ISP>;
337 pm_qos = <&qos 317 pm_qos = <&qos_isp_128>, <&qos_isp_rd>,
338 <&qos 318 <&qos_isp_wr>, <&qos_isp_m1>,
339 <&qos 319 <&qos_vip>;
340 #power-domain- 320 #power-domain-cells = <0>;
341 }; 321 };
342 power-domain@PX30_PD_G 322 power-domain@PX30_PD_GPU {
343 reg = <PX30_PD 323 reg = <PX30_PD_GPU>;
344 clocks = <&cru 324 clocks = <&cru SCLK_GPU>;
345 pm_qos = <&qos 325 pm_qos = <&qos_gpu>;
346 #power-domain- 326 #power-domain-cells = <0>;
347 }; 327 };
348 }; 328 };
349 }; 329 };
350 330
351 pmugrf: syscon@ff010000 { 331 pmugrf: syscon@ff010000 {
352 compatible = "rockchip,px30-pm 332 compatible = "rockchip,px30-pmugrf", "syscon", "simple-mfd";
353 reg = <0x0 0xff010000 0x0 0x10 333 reg = <0x0 0xff010000 0x0 0x1000>;
354 #address-cells = <1>; 334 #address-cells = <1>;
355 #size-cells = <1>; 335 #size-cells = <1>;
356 336
357 pmu_io_domains: io-domains { 337 pmu_io_domains: io-domains {
358 compatible = "rockchip 338 compatible = "rockchip,px30-pmu-io-voltage-domain";
359 status = "disabled"; 339 status = "disabled";
360 }; 340 };
361 341
362 reboot-mode { 342 reboot-mode {
363 compatible = "syscon-r 343 compatible = "syscon-reboot-mode";
364 offset = <0x200>; 344 offset = <0x200>;
365 mode-bootloader = <BOO 345 mode-bootloader = <BOOT_BL_DOWNLOAD>;
366 mode-fastboot = <BOOT_ 346 mode-fastboot = <BOOT_FASTBOOT>;
367 mode-loader = <BOOT_BL 347 mode-loader = <BOOT_BL_DOWNLOAD>;
368 mode-normal = <BOOT_NO 348 mode-normal = <BOOT_NORMAL>;
369 mode-recovery = <BOOT_ 349 mode-recovery = <BOOT_RECOVERY>;
370 }; 350 };
371 }; 351 };
372 352
373 uart0: serial@ff030000 { 353 uart0: serial@ff030000 {
374 compatible = "rockchip,px30-ua 354 compatible = "rockchip,px30-uart", "snps,dw-apb-uart";
375 reg = <0x0 0xff030000 0x0 0x10 355 reg = <0x0 0xff030000 0x0 0x100>;
376 interrupts = <GIC_SPI 15 IRQ_T 356 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
377 clocks = <&pmucru SCLK_UART0_P 357 clocks = <&pmucru SCLK_UART0_PMU>, <&pmucru PCLK_UART0_PMU>;
378 clock-names = "baudclk", "apb_ 358 clock-names = "baudclk", "apb_pclk";
379 dmas = <&dmac 0>, <&dmac 1>; 359 dmas = <&dmac 0>, <&dmac 1>;
380 dma-names = "tx", "rx"; 360 dma-names = "tx", "rx";
381 reg-shift = <2>; 361 reg-shift = <2>;
382 reg-io-width = <4>; 362 reg-io-width = <4>;
383 pinctrl-names = "default"; 363 pinctrl-names = "default";
384 pinctrl-0 = <&uart0_xfer &uart 364 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
385 status = "disabled"; 365 status = "disabled";
386 }; 366 };
387 367
388 i2s0_8ch: i2s@ff060000 { <<
389 compatible = "rockchip,px30-i2 <<
390 reg = <0x0 0xff060000 0x0 0x10 <<
391 interrupts = <GIC_SPI 12 IRQ_T <<
392 clocks = <&cru SCLK_I2S0_TX>, <<
393 clock-names = "mclk_tx", "mclk <<
394 dmas = <&dmac 16>, <&dmac 17>; <<
395 dma-names = "tx", "rx"; <<
396 rockchip,grf = <&grf>; <<
397 resets = <&cru SRST_I2S0_TX>, <<
398 reset-names = "tx-m", "rx-m"; <<
399 pinctrl-names = "default"; <<
400 pinctrl-0 = <&i2s0_8ch_sclktx <<
401 &i2s0_8ch_lrcktx <<
402 &i2s0_8ch_sdo0 &i <<
403 &i2s0_8ch_sdo1 &i <<
404 &i2s0_8ch_sdo2 &i <<
405 &i2s0_8ch_sdo3 &i <<
406 #sound-dai-cells = <0>; <<
407 status = "disabled"; <<
408 }; <<
409 <<
410 i2s1_2ch: i2s@ff070000 { 368 i2s1_2ch: i2s@ff070000 {
411 compatible = "rockchip,px30-i2 369 compatible = "rockchip,px30-i2s", "rockchip,rk3066-i2s";
412 reg = <0x0 0xff070000 0x0 0x10 370 reg = <0x0 0xff070000 0x0 0x1000>;
413 interrupts = <GIC_SPI 13 IRQ_T 371 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
414 clocks = <&cru SCLK_I2S1>, <&c 372 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1>;
415 clock-names = "i2s_clk", "i2s_ 373 clock-names = "i2s_clk", "i2s_hclk";
416 dmas = <&dmac 18>, <&dmac 19>; 374 dmas = <&dmac 18>, <&dmac 19>;
417 dma-names = "tx", "rx"; 375 dma-names = "tx", "rx";
418 pinctrl-names = "default"; 376 pinctrl-names = "default";
419 pinctrl-0 = <&i2s1_2ch_sclk &i 377 pinctrl-0 = <&i2s1_2ch_sclk &i2s1_2ch_lrck
420 &i2s1_2ch_sdi &i2 378 &i2s1_2ch_sdi &i2s1_2ch_sdo>;
421 #sound-dai-cells = <0>; 379 #sound-dai-cells = <0>;
422 status = "disabled"; 380 status = "disabled";
423 }; 381 };
424 382
425 i2s2_2ch: i2s@ff080000 { 383 i2s2_2ch: i2s@ff080000 {
426 compatible = "rockchip,px30-i2 384 compatible = "rockchip,px30-i2s", "rockchip,rk3066-i2s";
427 reg = <0x0 0xff080000 0x0 0x10 385 reg = <0x0 0xff080000 0x0 0x1000>;
428 interrupts = <GIC_SPI 14 IRQ_T 386 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
429 clocks = <&cru SCLK_I2S2>, <&c 387 clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2>;
430 clock-names = "i2s_clk", "i2s_ 388 clock-names = "i2s_clk", "i2s_hclk";
431 dmas = <&dmac 20>, <&dmac 21>; 389 dmas = <&dmac 20>, <&dmac 21>;
432 dma-names = "tx", "rx"; 390 dma-names = "tx", "rx";
433 pinctrl-names = "default"; 391 pinctrl-names = "default";
434 pinctrl-0 = <&i2s2_2ch_sclk &i 392 pinctrl-0 = <&i2s2_2ch_sclk &i2s2_2ch_lrck
435 &i2s2_2ch_sdi &i2 393 &i2s2_2ch_sdi &i2s2_2ch_sdo>;
436 #sound-dai-cells = <0>; 394 #sound-dai-cells = <0>;
437 status = "disabled"; 395 status = "disabled";
438 }; 396 };
439 397
440 gic: interrupt-controller@ff131000 { 398 gic: interrupt-controller@ff131000 {
441 compatible = "arm,gic-400"; 399 compatible = "arm,gic-400";
442 #interrupt-cells = <3>; 400 #interrupt-cells = <3>;
443 #address-cells = <0>; 401 #address-cells = <0>;
444 interrupt-controller; 402 interrupt-controller;
445 reg = <0x0 0xff131000 0 0x1000 403 reg = <0x0 0xff131000 0 0x1000>,
446 <0x0 0xff132000 0 0x2000 404 <0x0 0xff132000 0 0x2000>,
447 <0x0 0xff134000 0 0x2000 405 <0x0 0xff134000 0 0x2000>,
448 <0x0 0xff136000 0 0x2000 406 <0x0 0xff136000 0 0x2000>;
449 interrupts = <GIC_PPI 9 407 interrupts = <GIC_PPI 9
450 (GIC_CPU_MASK_SIMPLE(4) 408 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
451 }; 409 };
452 410
453 grf: syscon@ff140000 { 411 grf: syscon@ff140000 {
454 compatible = "rockchip,px30-gr 412 compatible = "rockchip,px30-grf", "syscon", "simple-mfd";
455 reg = <0x0 0xff140000 0x0 0x10 413 reg = <0x0 0xff140000 0x0 0x1000>;
456 #address-cells = <1>; 414 #address-cells = <1>;
457 #size-cells = <1>; 415 #size-cells = <1>;
458 416
459 io_domains: io-domains { 417 io_domains: io-domains {
460 compatible = "rockchip 418 compatible = "rockchip,px30-io-voltage-domain";
461 status = "disabled"; 419 status = "disabled";
462 }; 420 };
463 421
464 lvds: lvds { 422 lvds: lvds {
465 compatible = "rockchip 423 compatible = "rockchip,px30-lvds";
466 phys = <&dsi_dphy>; 424 phys = <&dsi_dphy>;
467 phy-names = "dphy"; 425 phy-names = "dphy";
468 rockchip,grf = <&grf>; 426 rockchip,grf = <&grf>;
469 rockchip,output = "lvd 427 rockchip,output = "lvds";
470 status = "disabled"; 428 status = "disabled";
471 429
472 ports { 430 ports {
473 #address-cells 431 #address-cells = <1>;
474 #size-cells = 432 #size-cells = <0>;
475 433
476 lvds_in: port@ !! 434 port@0 {
477 reg = 435 reg = <0>;
478 #addre 436 #address-cells = <1>;
479 #size- 437 #size-cells = <0>;
480 438
481 lvds_v 439 lvds_vopb_in: endpoint@0 {
482 440 reg = <0>;
483 441 remote-endpoint = <&vopb_out_lvds>;
484 }; 442 };
485 443
486 lvds_v 444 lvds_vopl_in: endpoint@1 {
487 445 reg = <1>;
488 446 remote-endpoint = <&vopl_out_lvds>;
489 }; 447 };
490 }; 448 };
491 <<
492 lvds_out: port <<
493 reg = <<
494 }; <<
495 }; 449 };
496 }; 450 };
497 }; 451 };
498 452
499 uart1: serial@ff158000 { 453 uart1: serial@ff158000 {
500 compatible = "rockchip,px30-ua 454 compatible = "rockchip,px30-uart", "snps,dw-apb-uart";
501 reg = <0x0 0xff158000 0x0 0x10 455 reg = <0x0 0xff158000 0x0 0x100>;
502 interrupts = <GIC_SPI 16 IRQ_T 456 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
503 clocks = <&cru SCLK_UART1>, <& 457 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
504 clock-names = "baudclk", "apb_ 458 clock-names = "baudclk", "apb_pclk";
505 dmas = <&dmac 2>, <&dmac 3>; 459 dmas = <&dmac 2>, <&dmac 3>;
506 dma-names = "tx", "rx"; 460 dma-names = "tx", "rx";
507 reg-shift = <2>; 461 reg-shift = <2>;
508 reg-io-width = <4>; 462 reg-io-width = <4>;
509 pinctrl-names = "default"; 463 pinctrl-names = "default";
510 pinctrl-0 = <&uart1_xfer &uart 464 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
511 status = "disabled"; 465 status = "disabled";
512 }; 466 };
513 467
514 uart2: serial@ff160000 { 468 uart2: serial@ff160000 {
515 compatible = "rockchip,px30-ua 469 compatible = "rockchip,px30-uart", "snps,dw-apb-uart";
516 reg = <0x0 0xff160000 0x0 0x10 470 reg = <0x0 0xff160000 0x0 0x100>;
517 interrupts = <GIC_SPI 17 IRQ_T 471 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
518 clocks = <&cru SCLK_UART2>, <& 472 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
519 clock-names = "baudclk", "apb_ 473 clock-names = "baudclk", "apb_pclk";
520 dmas = <&dmac 4>, <&dmac 5>; 474 dmas = <&dmac 4>, <&dmac 5>;
521 dma-names = "tx", "rx"; 475 dma-names = "tx", "rx";
522 reg-shift = <2>; 476 reg-shift = <2>;
523 reg-io-width = <4>; 477 reg-io-width = <4>;
524 pinctrl-names = "default"; 478 pinctrl-names = "default";
525 pinctrl-0 = <&uart2m0_xfer>; 479 pinctrl-0 = <&uart2m0_xfer>;
526 status = "disabled"; 480 status = "disabled";
527 }; 481 };
528 482
529 uart3: serial@ff168000 { 483 uart3: serial@ff168000 {
530 compatible = "rockchip,px30-ua 484 compatible = "rockchip,px30-uart", "snps,dw-apb-uart";
531 reg = <0x0 0xff168000 0x0 0x10 485 reg = <0x0 0xff168000 0x0 0x100>;
532 interrupts = <GIC_SPI 18 IRQ_T 486 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
533 clocks = <&cru SCLK_UART3>, <& 487 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
534 clock-names = "baudclk", "apb_ 488 clock-names = "baudclk", "apb_pclk";
535 dmas = <&dmac 6>, <&dmac 7>; 489 dmas = <&dmac 6>, <&dmac 7>;
536 dma-names = "tx", "rx"; 490 dma-names = "tx", "rx";
537 reg-shift = <2>; 491 reg-shift = <2>;
538 reg-io-width = <4>; 492 reg-io-width = <4>;
539 pinctrl-names = "default"; 493 pinctrl-names = "default";
540 pinctrl-0 = <&uart3m1_xfer &ua 494 pinctrl-0 = <&uart3m1_xfer &uart3m1_cts &uart3m1_rts>;
541 status = "disabled"; 495 status = "disabled";
542 }; 496 };
543 497
544 uart4: serial@ff170000 { 498 uart4: serial@ff170000 {
545 compatible = "rockchip,px30-ua 499 compatible = "rockchip,px30-uart", "snps,dw-apb-uart";
546 reg = <0x0 0xff170000 0x0 0x10 500 reg = <0x0 0xff170000 0x0 0x100>;
547 interrupts = <GIC_SPI 19 IRQ_T 501 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
548 clocks = <&cru SCLK_UART4>, <& 502 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
549 clock-names = "baudclk", "apb_ 503 clock-names = "baudclk", "apb_pclk";
550 dmas = <&dmac 8>, <&dmac 9>; 504 dmas = <&dmac 8>, <&dmac 9>;
551 dma-names = "tx", "rx"; 505 dma-names = "tx", "rx";
552 reg-shift = <2>; 506 reg-shift = <2>;
553 reg-io-width = <4>; 507 reg-io-width = <4>;
554 pinctrl-names = "default"; 508 pinctrl-names = "default";
555 pinctrl-0 = <&uart4_xfer &uart 509 pinctrl-0 = <&uart4_xfer &uart4_cts &uart4_rts>;
556 status = "disabled"; 510 status = "disabled";
557 }; 511 };
558 512
559 uart5: serial@ff178000 { 513 uart5: serial@ff178000 {
560 compatible = "rockchip,px30-ua 514 compatible = "rockchip,px30-uart", "snps,dw-apb-uart";
561 reg = <0x0 0xff178000 0x0 0x10 515 reg = <0x0 0xff178000 0x0 0x100>;
562 interrupts = <GIC_SPI 20 IRQ_T 516 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
563 clocks = <&cru SCLK_UART5>, <& 517 clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>;
564 clock-names = "baudclk", "apb_ 518 clock-names = "baudclk", "apb_pclk";
565 dmas = <&dmac 10>, <&dmac 11>; 519 dmas = <&dmac 10>, <&dmac 11>;
566 dma-names = "tx", "rx"; 520 dma-names = "tx", "rx";
567 reg-shift = <2>; 521 reg-shift = <2>;
568 reg-io-width = <4>; 522 reg-io-width = <4>;
569 pinctrl-names = "default"; 523 pinctrl-names = "default";
570 pinctrl-0 = <&uart5_xfer &uart 524 pinctrl-0 = <&uart5_xfer &uart5_cts &uart5_rts>;
571 status = "disabled"; 525 status = "disabled";
572 }; 526 };
573 527
574 i2c0: i2c@ff180000 { 528 i2c0: i2c@ff180000 {
575 compatible = "rockchip,px30-i2 529 compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c";
576 reg = <0x0 0xff180000 0x0 0x10 530 reg = <0x0 0xff180000 0x0 0x1000>;
577 clocks = <&cru SCLK_I2C0>, <&c !! 531 clocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>;
578 clock-names = "i2c", "pclk"; 532 clock-names = "i2c", "pclk";
579 interrupts = <GIC_SPI 7 IRQ_TY 533 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
580 pinctrl-names = "default"; 534 pinctrl-names = "default";
581 pinctrl-0 = <&i2c0_xfer>; 535 pinctrl-0 = <&i2c0_xfer>;
582 #address-cells = <1>; 536 #address-cells = <1>;
583 #size-cells = <0>; 537 #size-cells = <0>;
584 status = "disabled"; 538 status = "disabled";
585 }; 539 };
586 540
587 i2c1: i2c@ff190000 { 541 i2c1: i2c@ff190000 {
588 compatible = "rockchip,px30-i2 542 compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c";
589 reg = <0x0 0xff190000 0x0 0x10 543 reg = <0x0 0xff190000 0x0 0x1000>;
590 clocks = <&cru SCLK_I2C1>, <&c 544 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
591 clock-names = "i2c", "pclk"; 545 clock-names = "i2c", "pclk";
592 interrupts = <GIC_SPI 8 IRQ_TY 546 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
593 pinctrl-names = "default"; 547 pinctrl-names = "default";
594 pinctrl-0 = <&i2c1_xfer>; 548 pinctrl-0 = <&i2c1_xfer>;
595 #address-cells = <1>; 549 #address-cells = <1>;
596 #size-cells = <0>; 550 #size-cells = <0>;
597 status = "disabled"; 551 status = "disabled";
598 }; 552 };
599 553
600 i2c2: i2c@ff1a0000 { 554 i2c2: i2c@ff1a0000 {
601 compatible = "rockchip,px30-i2 555 compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c";
602 reg = <0x0 0xff1a0000 0x0 0x10 556 reg = <0x0 0xff1a0000 0x0 0x1000>;
603 clocks = <&cru SCLK_I2C2>, <&c 557 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
604 clock-names = "i2c", "pclk"; 558 clock-names = "i2c", "pclk";
605 interrupts = <GIC_SPI 9 IRQ_TY 559 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
606 pinctrl-names = "default"; 560 pinctrl-names = "default";
607 pinctrl-0 = <&i2c2_xfer>; 561 pinctrl-0 = <&i2c2_xfer>;
608 #address-cells = <1>; 562 #address-cells = <1>;
609 #size-cells = <0>; 563 #size-cells = <0>;
610 status = "disabled"; 564 status = "disabled";
611 }; 565 };
612 566
613 i2c3: i2c@ff1b0000 { 567 i2c3: i2c@ff1b0000 {
614 compatible = "rockchip,px30-i2 568 compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c";
615 reg = <0x0 0xff1b0000 0x0 0x10 569 reg = <0x0 0xff1b0000 0x0 0x1000>;
616 clocks = <&cru SCLK_I2C3>, <&c 570 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
617 clock-names = "i2c", "pclk"; 571 clock-names = "i2c", "pclk";
618 interrupts = <GIC_SPI 10 IRQ_T 572 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
619 pinctrl-names = "default"; 573 pinctrl-names = "default";
620 pinctrl-0 = <&i2c3_xfer>; 574 pinctrl-0 = <&i2c3_xfer>;
621 #address-cells = <1>; 575 #address-cells = <1>;
622 #size-cells = <0>; 576 #size-cells = <0>;
623 status = "disabled"; 577 status = "disabled";
624 }; 578 };
625 579
626 spi0: spi@ff1d0000 { 580 spi0: spi@ff1d0000 {
627 compatible = "rockchip,px30-sp 581 compatible = "rockchip,px30-spi", "rockchip,rk3066-spi";
628 reg = <0x0 0xff1d0000 0x0 0x10 582 reg = <0x0 0xff1d0000 0x0 0x1000>;
629 interrupts = <GIC_SPI 26 IRQ_T 583 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
630 clocks = <&cru SCLK_SPI0>, <&c 584 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
631 clock-names = "spiclk", "apb_p 585 clock-names = "spiclk", "apb_pclk";
632 dmas = <&dmac 12>, <&dmac 13>; 586 dmas = <&dmac 12>, <&dmac 13>;
633 dma-names = "tx", "rx"; 587 dma-names = "tx", "rx";
634 num-cs = <2>; <<
635 pinctrl-names = "default"; 588 pinctrl-names = "default";
636 pinctrl-0 = <&spi0_clk &spi0_c 589 pinctrl-0 = <&spi0_clk &spi0_csn &spi0_miso &spi0_mosi>;
637 #address-cells = <1>; 590 #address-cells = <1>;
638 #size-cells = <0>; 591 #size-cells = <0>;
639 status = "disabled"; 592 status = "disabled";
640 }; 593 };
641 594
642 spi1: spi@ff1d8000 { 595 spi1: spi@ff1d8000 {
643 compatible = "rockchip,px30-sp 596 compatible = "rockchip,px30-spi", "rockchip,rk3066-spi";
644 reg = <0x0 0xff1d8000 0x0 0x10 597 reg = <0x0 0xff1d8000 0x0 0x1000>;
645 interrupts = <GIC_SPI 27 IRQ_T 598 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
646 clocks = <&cru SCLK_SPI1>, <&c 599 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
647 clock-names = "spiclk", "apb_p 600 clock-names = "spiclk", "apb_pclk";
648 dmas = <&dmac 14>, <&dmac 15>; 601 dmas = <&dmac 14>, <&dmac 15>;
649 dma-names = "tx", "rx"; 602 dma-names = "tx", "rx";
650 num-cs = <2>; <<
651 pinctrl-names = "default"; 603 pinctrl-names = "default";
652 pinctrl-0 = <&spi1_clk &spi1_c 604 pinctrl-0 = <&spi1_clk &spi1_csn0 &spi1_csn1 &spi1_miso &spi1_mosi>;
653 #address-cells = <1>; 605 #address-cells = <1>;
654 #size-cells = <0>; 606 #size-cells = <0>;
655 status = "disabled"; 607 status = "disabled";
656 }; 608 };
657 609
658 wdt: watchdog@ff1e0000 { 610 wdt: watchdog@ff1e0000 {
659 compatible = "rockchip,px30-wd 611 compatible = "rockchip,px30-wdt", "snps,dw-wdt";
660 reg = <0x0 0xff1e0000 0x0 0x10 612 reg = <0x0 0xff1e0000 0x0 0x100>;
661 clocks = <&cru PCLK_WDT_NS>; 613 clocks = <&cru PCLK_WDT_NS>;
662 interrupts = <GIC_SPI 37 IRQ_T 614 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
663 status = "disabled"; 615 status = "disabled";
664 }; 616 };
665 617
666 pwm0: pwm@ff200000 { 618 pwm0: pwm@ff200000 {
667 compatible = "rockchip,px30-pw 619 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
668 reg = <0x0 0xff200000 0x0 0x10 620 reg = <0x0 0xff200000 0x0 0x10>;
669 clocks = <&cru SCLK_PWM0>, <&c 621 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
670 clock-names = "pwm", "pclk"; 622 clock-names = "pwm", "pclk";
671 pinctrl-names = "default"; 623 pinctrl-names = "default";
672 pinctrl-0 = <&pwm0_pin>; 624 pinctrl-0 = <&pwm0_pin>;
673 #pwm-cells = <3>; 625 #pwm-cells = <3>;
674 status = "disabled"; 626 status = "disabled";
675 }; 627 };
676 628
677 pwm1: pwm@ff200010 { 629 pwm1: pwm@ff200010 {
678 compatible = "rockchip,px30-pw 630 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
679 reg = <0x0 0xff200010 0x0 0x10 631 reg = <0x0 0xff200010 0x0 0x10>;
680 clocks = <&cru SCLK_PWM0>, <&c 632 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
681 clock-names = "pwm", "pclk"; 633 clock-names = "pwm", "pclk";
682 pinctrl-names = "default"; 634 pinctrl-names = "default";
683 pinctrl-0 = <&pwm1_pin>; 635 pinctrl-0 = <&pwm1_pin>;
684 #pwm-cells = <3>; 636 #pwm-cells = <3>;
685 status = "disabled"; 637 status = "disabled";
686 }; 638 };
687 639
688 pwm2: pwm@ff200020 { 640 pwm2: pwm@ff200020 {
689 compatible = "rockchip,px30-pw 641 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
690 reg = <0x0 0xff200020 0x0 0x10 642 reg = <0x0 0xff200020 0x0 0x10>;
691 clocks = <&cru SCLK_PWM0>, <&c 643 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
692 clock-names = "pwm", "pclk"; 644 clock-names = "pwm", "pclk";
693 pinctrl-names = "default"; 645 pinctrl-names = "default";
694 pinctrl-0 = <&pwm2_pin>; 646 pinctrl-0 = <&pwm2_pin>;
695 #pwm-cells = <3>; 647 #pwm-cells = <3>;
696 status = "disabled"; 648 status = "disabled";
697 }; 649 };
698 650
699 pwm3: pwm@ff200030 { 651 pwm3: pwm@ff200030 {
700 compatible = "rockchip,px30-pw 652 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
701 reg = <0x0 0xff200030 0x0 0x10 653 reg = <0x0 0xff200030 0x0 0x10>;
702 clocks = <&cru SCLK_PWM0>, <&c 654 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
703 clock-names = "pwm", "pclk"; 655 clock-names = "pwm", "pclk";
704 pinctrl-names = "default"; 656 pinctrl-names = "default";
705 pinctrl-0 = <&pwm3_pin>; 657 pinctrl-0 = <&pwm3_pin>;
706 #pwm-cells = <3>; 658 #pwm-cells = <3>;
707 status = "disabled"; 659 status = "disabled";
708 }; 660 };
709 661
710 pwm4: pwm@ff208000 { 662 pwm4: pwm@ff208000 {
711 compatible = "rockchip,px30-pw 663 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
712 reg = <0x0 0xff208000 0x0 0x10 664 reg = <0x0 0xff208000 0x0 0x10>;
713 clocks = <&cru SCLK_PWM1>, <&c 665 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>;
714 clock-names = "pwm", "pclk"; 666 clock-names = "pwm", "pclk";
715 pinctrl-names = "default"; 667 pinctrl-names = "default";
716 pinctrl-0 = <&pwm4_pin>; 668 pinctrl-0 = <&pwm4_pin>;
717 #pwm-cells = <3>; 669 #pwm-cells = <3>;
718 status = "disabled"; 670 status = "disabled";
719 }; 671 };
720 672
721 pwm5: pwm@ff208010 { 673 pwm5: pwm@ff208010 {
722 compatible = "rockchip,px30-pw 674 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
723 reg = <0x0 0xff208010 0x0 0x10 675 reg = <0x0 0xff208010 0x0 0x10>;
724 clocks = <&cru SCLK_PWM1>, <&c 676 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>;
725 clock-names = "pwm", "pclk"; 677 clock-names = "pwm", "pclk";
726 pinctrl-names = "default"; 678 pinctrl-names = "default";
727 pinctrl-0 = <&pwm5_pin>; 679 pinctrl-0 = <&pwm5_pin>;
728 #pwm-cells = <3>; 680 #pwm-cells = <3>;
729 status = "disabled"; 681 status = "disabled";
730 }; 682 };
731 683
732 pwm6: pwm@ff208020 { 684 pwm6: pwm@ff208020 {
733 compatible = "rockchip,px30-pw 685 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
734 reg = <0x0 0xff208020 0x0 0x10 686 reg = <0x0 0xff208020 0x0 0x10>;
735 clocks = <&cru SCLK_PWM1>, <&c 687 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>;
736 clock-names = "pwm", "pclk"; 688 clock-names = "pwm", "pclk";
737 pinctrl-names = "default"; 689 pinctrl-names = "default";
738 pinctrl-0 = <&pwm6_pin>; 690 pinctrl-0 = <&pwm6_pin>;
739 #pwm-cells = <3>; 691 #pwm-cells = <3>;
740 status = "disabled"; 692 status = "disabled";
741 }; 693 };
742 694
743 pwm7: pwm@ff208030 { 695 pwm7: pwm@ff208030 {
744 compatible = "rockchip,px30-pw 696 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
745 reg = <0x0 0xff208030 0x0 0x10 697 reg = <0x0 0xff208030 0x0 0x10>;
746 clocks = <&cru SCLK_PWM1>, <&c 698 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>;
747 clock-names = "pwm", "pclk"; 699 clock-names = "pwm", "pclk";
748 pinctrl-names = "default"; 700 pinctrl-names = "default";
749 pinctrl-0 = <&pwm7_pin>; 701 pinctrl-0 = <&pwm7_pin>;
750 #pwm-cells = <3>; 702 #pwm-cells = <3>;
751 status = "disabled"; 703 status = "disabled";
752 }; 704 };
753 705
754 rktimer: timer@ff210000 { 706 rktimer: timer@ff210000 {
755 compatible = "rockchip,px30-ti 707 compatible = "rockchip,px30-timer", "rockchip,rk3288-timer";
756 reg = <0x0 0xff210000 0x0 0x10 708 reg = <0x0 0xff210000 0x0 0x1000>;
757 interrupts = <GIC_SPI 30 IRQ_T 709 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
758 clocks = <&cru PCLK_TIMER>, <& 710 clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER0>;
759 clock-names = "pclk", "timer"; 711 clock-names = "pclk", "timer";
760 }; 712 };
761 713
762 dmac: dma-controller@ff240000 { !! 714 dmac: dmac@ff240000 {
763 compatible = "arm,pl330", "arm 715 compatible = "arm,pl330", "arm,primecell";
764 reg = <0x0 0xff240000 0x0 0x40 716 reg = <0x0 0xff240000 0x0 0x4000>;
765 interrupts = <GIC_SPI 1 IRQ_TY 717 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
766 <GIC_SPI 2 IRQ_TY 718 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
767 arm,pl330-periph-burst; 719 arm,pl330-periph-burst;
768 clocks = <&cru ACLK_DMAC>; 720 clocks = <&cru ACLK_DMAC>;
769 clock-names = "apb_pclk"; 721 clock-names = "apb_pclk";
770 #dma-cells = <1>; 722 #dma-cells = <1>;
771 }; 723 };
772 724
773 tsadc: tsadc@ff280000 { 725 tsadc: tsadc@ff280000 {
774 compatible = "rockchip,px30-ts 726 compatible = "rockchip,px30-tsadc";
775 reg = <0x0 0xff280000 0x0 0x10 727 reg = <0x0 0xff280000 0x0 0x100>;
776 interrupts = <GIC_SPI 36 IRQ_T 728 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
777 assigned-clocks = <&cru SCLK_T 729 assigned-clocks = <&cru SCLK_TSADC>;
778 assigned-clock-rates = <50000> 730 assigned-clock-rates = <50000>;
779 clocks = <&cru SCLK_TSADC>, <& 731 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
780 clock-names = "tsadc", "apb_pc 732 clock-names = "tsadc", "apb_pclk";
781 resets = <&cru SRST_TSADC>; 733 resets = <&cru SRST_TSADC>;
782 reset-names = "tsadc-apb"; 734 reset-names = "tsadc-apb";
783 rockchip,grf = <&grf>; 735 rockchip,grf = <&grf>;
784 rockchip,hw-tshut-temp = <1200 736 rockchip,hw-tshut-temp = <120000>;
785 pinctrl-names = "init", "defau 737 pinctrl-names = "init", "default", "sleep";
786 pinctrl-0 = <&tsadc_otp_pin>; 738 pinctrl-0 = <&tsadc_otp_pin>;
787 pinctrl-1 = <&tsadc_otp_out>; 739 pinctrl-1 = <&tsadc_otp_out>;
788 pinctrl-2 = <&tsadc_otp_pin>; 740 pinctrl-2 = <&tsadc_otp_pin>;
789 #thermal-sensor-cells = <1>; 741 #thermal-sensor-cells = <1>;
790 status = "disabled"; 742 status = "disabled";
791 }; 743 };
792 744
793 saradc: saradc@ff288000 { 745 saradc: saradc@ff288000 {
794 compatible = "rockchip,px30-sa 746 compatible = "rockchip,px30-saradc", "rockchip,rk3399-saradc";
795 reg = <0x0 0xff288000 0x0 0x10 747 reg = <0x0 0xff288000 0x0 0x100>;
796 interrupts = <GIC_SPI 84 IRQ_T 748 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
797 #io-channel-cells = <1>; 749 #io-channel-cells = <1>;
798 clocks = <&cru SCLK_SARADC>, < 750 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
799 clock-names = "saradc", "apb_p 751 clock-names = "saradc", "apb_pclk";
800 resets = <&cru SRST_SARADC_P>; 752 resets = <&cru SRST_SARADC_P>;
801 reset-names = "saradc-apb"; 753 reset-names = "saradc-apb";
802 status = "disabled"; 754 status = "disabled";
803 }; 755 };
804 756
805 otp: nvmem@ff290000 { 757 otp: nvmem@ff290000 {
806 compatible = "rockchip,px30-ot 758 compatible = "rockchip,px30-otp";
807 reg = <0x0 0xff290000 0x0 0x40 759 reg = <0x0 0xff290000 0x0 0x4000>;
808 clocks = <&cru SCLK_OTP_USR>, 760 clocks = <&cru SCLK_OTP_USR>, <&cru PCLK_OTP_NS>,
809 <&cru PCLK_OTP_PHY>; 761 <&cru PCLK_OTP_PHY>;
810 clock-names = "otp", "apb_pclk 762 clock-names = "otp", "apb_pclk", "phy";
811 resets = <&cru SRST_OTP_PHY>; 763 resets = <&cru SRST_OTP_PHY>;
812 reset-names = "phy"; 764 reset-names = "phy";
813 #address-cells = <1>; 765 #address-cells = <1>;
814 #size-cells = <1>; 766 #size-cells = <1>;
815 767
816 /* Data cells */ 768 /* Data cells */
817 cpu_id: id@7 { 769 cpu_id: id@7 {
818 reg = <0x07 0x10>; 770 reg = <0x07 0x10>;
819 }; 771 };
820 cpu_leakage: cpu-leakage@17 { 772 cpu_leakage: cpu-leakage@17 {
821 reg = <0x17 0x1>; 773 reg = <0x17 0x1>;
822 }; 774 };
823 performance: performance@1e { 775 performance: performance@1e {
824 reg = <0x1e 0x1>; 776 reg = <0x1e 0x1>;
825 bits = <4 3>; 777 bits = <4 3>;
826 }; 778 };
827 }; 779 };
828 780
829 cru: clock-controller@ff2b0000 { 781 cru: clock-controller@ff2b0000 {
830 compatible = "rockchip,px30-cr 782 compatible = "rockchip,px30-cru";
831 reg = <0x0 0xff2b0000 0x0 0x10 783 reg = <0x0 0xff2b0000 0x0 0x1000>;
832 clocks = <&xin24m>, <&pmucru P 784 clocks = <&xin24m>, <&pmucru PLL_GPLL>;
833 clock-names = "xin24m", "gpll" 785 clock-names = "xin24m", "gpll";
834 rockchip,grf = <&grf>; 786 rockchip,grf = <&grf>;
835 #clock-cells = <1>; 787 #clock-cells = <1>;
836 #reset-cells = <1>; 788 #reset-cells = <1>;
837 789
838 assigned-clocks = <&cru PLL_NP 790 assigned-clocks = <&cru PLL_NPLL>,
839 <&cru ACLK_BUS_PRE>, < 791 <&cru ACLK_BUS_PRE>, <&cru ACLK_PERI_PRE>,
840 <&cru HCLK_BUS_PRE>, < 792 <&cru HCLK_BUS_PRE>, <&cru HCLK_PERI_PRE>,
841 <&cru PCLK_BUS_PRE>, < 793 <&cru PCLK_BUS_PRE>, <&cru SCLK_GPU>;
842 794
843 assigned-clock-rates = <118800 795 assigned-clock-rates = <1188000000>,
844 <200000000>, <20000000 796 <200000000>, <200000000>,
845 <150000000>, <15000000 797 <150000000>, <150000000>,
846 <100000000>, <20000000 798 <100000000>, <200000000>;
847 }; 799 };
848 800
849 pmucru: clock-controller@ff2bc000 { 801 pmucru: clock-controller@ff2bc000 {
850 compatible = "rockchip,px30-pm 802 compatible = "rockchip,px30-pmucru";
851 reg = <0x0 0xff2bc000 0x0 0x10 803 reg = <0x0 0xff2bc000 0x0 0x1000>;
852 clocks = <&xin24m>; 804 clocks = <&xin24m>;
853 clock-names = "xin24m"; 805 clock-names = "xin24m";
854 rockchip,grf = <&grf>; 806 rockchip,grf = <&grf>;
855 #clock-cells = <1>; 807 #clock-cells = <1>;
856 #reset-cells = <1>; 808 #reset-cells = <1>;
857 809
858 assigned-clocks = 810 assigned-clocks =
859 <&pmucru PLL_GPLL>, <& 811 <&pmucru PLL_GPLL>, <&pmucru PCLK_PMU_PRE>,
860 <&pmucru SCLK_WIFI_PMU 812 <&pmucru SCLK_WIFI_PMU>;
861 assigned-clock-rates = 813 assigned-clock-rates =
862 <1200000000>, <1000000 814 <1200000000>, <100000000>,
863 <26000000>; 815 <26000000>;
864 }; 816 };
865 817
866 usb2phy_grf: syscon@ff2c0000 { 818 usb2phy_grf: syscon@ff2c0000 {
867 compatible = "rockchip,px30-us 819 compatible = "rockchip,px30-usb2phy-grf", "syscon",
868 "simple-mfd"; 820 "simple-mfd";
869 reg = <0x0 0xff2c0000 0x0 0x10 821 reg = <0x0 0xff2c0000 0x0 0x10000>;
870 #address-cells = <1>; 822 #address-cells = <1>;
871 #size-cells = <1>; 823 #size-cells = <1>;
872 824
873 u2phy: usb2phy@100 { 825 u2phy: usb2phy@100 {
874 compatible = "rockchip 826 compatible = "rockchip,px30-usb2phy";
875 reg = <0x100 0x20>; 827 reg = <0x100 0x20>;
876 clocks = <&pmucru SCLK 828 clocks = <&pmucru SCLK_USBPHY_REF>;
877 clock-names = "phyclk" 829 clock-names = "phyclk";
878 #clock-cells = <0>; 830 #clock-cells = <0>;
879 assigned-clocks = <&cr 831 assigned-clocks = <&cru USB480M>;
880 assigned-clock-parents 832 assigned-clock-parents = <&u2phy>;
881 clock-output-names = " 833 clock-output-names = "usb480m_phy";
882 status = "disabled"; 834 status = "disabled";
883 835
884 u2phy_host: host-port 836 u2phy_host: host-port {
885 #phy-cells = < 837 #phy-cells = <0>;
886 interrupts = < 838 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
887 interrupt-name 839 interrupt-names = "linestate";
888 status = "disa 840 status = "disabled";
889 }; 841 };
890 842
891 u2phy_otg: otg-port { 843 u2phy_otg: otg-port {
892 #phy-cells = < 844 #phy-cells = <0>;
893 interrupts = < 845 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
894 < 846 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
895 < 847 <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
896 interrupt-name 848 interrupt-names = "otg-bvalid", "otg-id",
897 849 "linestate";
898 status = "disa 850 status = "disabled";
899 }; 851 };
900 }; 852 };
901 }; 853 };
902 854
903 dsi_dphy: phy@ff2e0000 { 855 dsi_dphy: phy@ff2e0000 {
904 compatible = "rockchip,px30-ds 856 compatible = "rockchip,px30-dsi-dphy";
905 reg = <0x0 0xff2e0000 0x0 0x10 857 reg = <0x0 0xff2e0000 0x0 0x10000>;
906 clocks = <&pmucru SCLK_MIPIDSI 858 clocks = <&pmucru SCLK_MIPIDSIPHY_REF>, <&cru PCLK_MIPIDSIPHY>;
907 clock-names = "ref", "pclk"; 859 clock-names = "ref", "pclk";
908 resets = <&cru SRST_MIPIDSIPHY 860 resets = <&cru SRST_MIPIDSIPHY_P>;
909 reset-names = "apb"; 861 reset-names = "apb";
910 #phy-cells = <0>; 862 #phy-cells = <0>;
911 power-domains = <&power PX30_P 863 power-domains = <&power PX30_PD_VO>;
912 status = "disabled"; 864 status = "disabled";
913 }; 865 };
914 866
915 csi_dphy: phy@ff2f0000 { <<
916 compatible = "rockchip,px30-cs <<
917 reg = <0x0 0xff2f0000 0x0 0x40 <<
918 clocks = <&cru PCLK_MIPICSIPHY <<
919 clock-names = "pclk"; <<
920 #phy-cells = <0>; <<
921 power-domains = <&power PX30_P <<
922 resets = <&cru SRST_MIPICSIPHY <<
923 reset-names = "apb"; <<
924 rockchip,grf = <&grf>; <<
925 status = "disabled"; <<
926 }; <<
927 <<
928 usb20_otg: usb@ff300000 { 867 usb20_otg: usb@ff300000 {
929 compatible = "rockchip,px30-us 868 compatible = "rockchip,px30-usb", "rockchip,rk3066-usb",
930 "snps,dwc2"; 869 "snps,dwc2";
931 reg = <0x0 0xff300000 0x0 0x40 870 reg = <0x0 0xff300000 0x0 0x40000>;
932 interrupts = <GIC_SPI 62 IRQ_T 871 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
933 clocks = <&cru HCLK_OTG>; 872 clocks = <&cru HCLK_OTG>;
934 clock-names = "otg"; 873 clock-names = "otg";
935 dr_mode = "otg"; 874 dr_mode = "otg";
936 g-np-tx-fifo-size = <16>; 875 g-np-tx-fifo-size = <16>;
937 g-rx-fifo-size = <280>; 876 g-rx-fifo-size = <280>;
938 g-tx-fifo-size = <256 128 128 877 g-tx-fifo-size = <256 128 128 64 32 16>;
939 phys = <&u2phy_otg>; 878 phys = <&u2phy_otg>;
940 phy-names = "usb2-phy"; 879 phy-names = "usb2-phy";
941 power-domains = <&power PX30_P 880 power-domains = <&power PX30_PD_USB>;
942 status = "disabled"; 881 status = "disabled";
943 }; 882 };
944 883
945 usb_host0_ehci: usb@ff340000 { 884 usb_host0_ehci: usb@ff340000 {
946 compatible = "generic-ehci"; 885 compatible = "generic-ehci";
947 reg = <0x0 0xff340000 0x0 0x10 886 reg = <0x0 0xff340000 0x0 0x10000>;
948 interrupts = <GIC_SPI 60 IRQ_T 887 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
949 clocks = <&cru HCLK_HOST>; 888 clocks = <&cru HCLK_HOST>;
950 phys = <&u2phy_host>; 889 phys = <&u2phy_host>;
951 phy-names = "usb"; 890 phy-names = "usb";
952 power-domains = <&power PX30_P 891 power-domains = <&power PX30_PD_USB>;
953 status = "disabled"; 892 status = "disabled";
954 }; 893 };
955 894
956 usb_host0_ohci: usb@ff350000 { 895 usb_host0_ohci: usb@ff350000 {
957 compatible = "generic-ohci"; 896 compatible = "generic-ohci";
958 reg = <0x0 0xff350000 0x0 0x10 897 reg = <0x0 0xff350000 0x0 0x10000>;
959 interrupts = <GIC_SPI 61 IRQ_T 898 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
960 clocks = <&cru HCLK_HOST>; 899 clocks = <&cru HCLK_HOST>;
961 phys = <&u2phy_host>; 900 phys = <&u2phy_host>;
962 phy-names = "usb"; 901 phy-names = "usb";
963 power-domains = <&power PX30_P 902 power-domains = <&power PX30_PD_USB>;
964 status = "disabled"; 903 status = "disabled";
965 }; 904 };
966 905
967 gmac: ethernet@ff360000 { 906 gmac: ethernet@ff360000 {
968 compatible = "rockchip,px30-gm 907 compatible = "rockchip,px30-gmac";
969 reg = <0x0 0xff360000 0x0 0x10 908 reg = <0x0 0xff360000 0x0 0x10000>;
970 interrupts = <GIC_SPI 43 IRQ_T 909 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
971 interrupt-names = "macirq"; 910 interrupt-names = "macirq";
972 clocks = <&cru SCLK_GMAC>, <&c 911 clocks = <&cru SCLK_GMAC>, <&cru SCLK_GMAC_RX_TX>,
973 <&cru SCLK_GMAC_RX_TX 912 <&cru SCLK_GMAC_RX_TX>, <&cru SCLK_MAC_REF>,
974 <&cru SCLK_MAC_REFOUT 913 <&cru SCLK_MAC_REFOUT>, <&cru ACLK_GMAC>,
975 <&cru PCLK_GMAC>, <&c 914 <&cru PCLK_GMAC>, <&cru SCLK_GMAC_RMII>;
976 clock-names = "stmmaceth", "ma 915 clock-names = "stmmaceth", "mac_clk_rx",
977 "mac_clk_tx", "c 916 "mac_clk_tx", "clk_mac_ref",
978 "clk_mac_refout" 917 "clk_mac_refout", "aclk_mac",
979 "pclk_mac", "clk 918 "pclk_mac", "clk_mac_speed";
980 rockchip,grf = <&grf>; 919 rockchip,grf = <&grf>;
981 phy-mode = "rmii"; 920 phy-mode = "rmii";
982 pinctrl-names = "default"; 921 pinctrl-names = "default";
983 pinctrl-0 = <&rmii_pins &mac_r 922 pinctrl-0 = <&rmii_pins &mac_refclk_12ma>;
984 power-domains = <&power PX30_P 923 power-domains = <&power PX30_PD_GMAC>;
985 resets = <&cru SRST_GMAC_A>; 924 resets = <&cru SRST_GMAC_A>;
986 reset-names = "stmmaceth"; 925 reset-names = "stmmaceth";
987 status = "disabled"; 926 status = "disabled";
988 }; 927 };
989 928
990 sdmmc: mmc@ff370000 { 929 sdmmc: mmc@ff370000 {
991 compatible = "rockchip,px30-dw 930 compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc";
992 reg = <0x0 0xff370000 0x0 0x40 931 reg = <0x0 0xff370000 0x0 0x4000>;
993 interrupts = <GIC_SPI 54 IRQ_T 932 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
994 clocks = <&cru HCLK_SDMMC>, <& 933 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
995 <&cru SCLK_SDMMC_DRV> 934 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
996 clock-names = "biu", "ciu", "c 935 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
997 bus-width = <4>; 936 bus-width = <4>;
998 fifo-depth = <0x100>; 937 fifo-depth = <0x100>;
999 max-frequency = <150000000>; 938 max-frequency = <150000000>;
1000 pinctrl-names = "default"; 939 pinctrl-names = "default";
1001 pinctrl-0 = <&sdmmc_clk &sdmm 940 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_det &sdmmc_bus4>;
1002 power-domains = <&power PX30_ 941 power-domains = <&power PX30_PD_SDCARD>;
1003 status = "disabled"; 942 status = "disabled";
1004 }; 943 };
1005 944
1006 sdio: mmc@ff380000 { 945 sdio: mmc@ff380000 {
1007 compatible = "rockchip,px30-d 946 compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc";
1008 reg = <0x0 0xff380000 0x0 0x4 947 reg = <0x0 0xff380000 0x0 0x4000>;
1009 interrupts = <GIC_SPI 55 IRQ_ 948 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
1010 clocks = <&cru HCLK_SDIO>, <& 949 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
1011 <&cru SCLK_SDIO_DRV> 950 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
1012 clock-names = "biu", "ciu", " 951 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
1013 bus-width = <4>; 952 bus-width = <4>;
1014 fifo-depth = <0x100>; 953 fifo-depth = <0x100>;
1015 max-frequency = <150000000>; 954 max-frequency = <150000000>;
1016 pinctrl-names = "default"; 955 pinctrl-names = "default";
1017 pinctrl-0 = <&sdio_bus4 &sdio 956 pinctrl-0 = <&sdio_bus4 &sdio_cmd &sdio_clk>;
1018 power-domains = <&power PX30_ 957 power-domains = <&power PX30_PD_MMC_NAND>;
1019 status = "disabled"; 958 status = "disabled";
1020 }; 959 };
1021 960
1022 emmc: mmc@ff390000 { 961 emmc: mmc@ff390000 {
1023 compatible = "rockchip,px30-d 962 compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc";
1024 reg = <0x0 0xff390000 0x0 0x4 963 reg = <0x0 0xff390000 0x0 0x4000>;
1025 interrupts = <GIC_SPI 53 IRQ_ 964 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
1026 clocks = <&cru HCLK_EMMC>, <& 965 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
1027 <&cru SCLK_EMMC_DRV> 966 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
1028 clock-names = "biu", "ciu", " 967 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
1029 bus-width = <8>; 968 bus-width = <8>;
1030 fifo-depth = <0x100>; 969 fifo-depth = <0x100>;
1031 max-frequency = <150000000>; 970 max-frequency = <150000000>;
1032 pinctrl-names = "default"; 971 pinctrl-names = "default";
1033 pinctrl-0 = <&emmc_clk &emmc_ 972 pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
1034 power-domains = <&power PX30_ 973 power-domains = <&power PX30_PD_MMC_NAND>;
1035 status = "disabled"; 974 status = "disabled";
1036 }; 975 };
1037 976
1038 sfc: spi@ff3a0000 { <<
1039 compatible = "rockchip,sfc"; <<
1040 reg = <0x0 0xff3a0000 0x0 0x4 <<
1041 interrupts = <GIC_SPI 56 IRQ_ <<
1042 clocks = <&cru SCLK_SFC>, <&c <<
1043 clock-names = "clk_sfc", "hcl <<
1044 pinctrl-0 = <&sfc_clk &sfc_cs <<
1045 pinctrl-names = "default"; <<
1046 power-domains = <&power PX30_ <<
1047 status = "disabled"; <<
1048 }; <<
1049 <<
1050 nfc: nand-controller@ff3b0000 { 977 nfc: nand-controller@ff3b0000 {
1051 compatible = "rockchip,px30-n 978 compatible = "rockchip,px30-nfc";
1052 reg = <0x0 0xff3b0000 0x0 0x4 979 reg = <0x0 0xff3b0000 0x0 0x4000>;
1053 interrupts = <GIC_SPI 57 IRQ_ 980 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
1054 clocks = <&cru HCLK_NANDC>, < 981 clocks = <&cru HCLK_NANDC>, <&cru SCLK_NANDC>;
1055 clock-names = "ahb", "nfc"; 982 clock-names = "ahb", "nfc";
1056 assigned-clocks = <&cru SCLK_ 983 assigned-clocks = <&cru SCLK_NANDC>;
1057 assigned-clock-rates = <15000 984 assigned-clock-rates = <150000000>;
1058 pinctrl-names = "default"; 985 pinctrl-names = "default";
1059 pinctrl-0 = <&flash_ale &flas 986 pinctrl-0 = <&flash_ale &flash_bus8 &flash_cle &flash_cs0
1060 &flash_rdn &flas 987 &flash_rdn &flash_rdy &flash_wrn &flash_dqs>;
1061 power-domains = <&power PX30_ 988 power-domains = <&power PX30_PD_MMC_NAND>;
1062 status = "disabled"; 989 status = "disabled";
1063 }; 990 };
1064 991
1065 gpu_opp_table: opp-table-1 { !! 992 gpu_opp_table: opp-table2 {
1066 compatible = "operating-point 993 compatible = "operating-points-v2";
1067 994
1068 opp-200000000 { 995 opp-200000000 {
1069 opp-hz = /bits/ 64 <2 996 opp-hz = /bits/ 64 <200000000>;
1070 opp-microvolt = <9500 997 opp-microvolt = <950000>;
1071 }; 998 };
1072 opp-300000000 { 999 opp-300000000 {
1073 opp-hz = /bits/ 64 <3 1000 opp-hz = /bits/ 64 <300000000>;
1074 opp-microvolt = <9750 1001 opp-microvolt = <975000>;
1075 }; 1002 };
1076 opp-400000000 { 1003 opp-400000000 {
1077 opp-hz = /bits/ 64 <4 1004 opp-hz = /bits/ 64 <400000000>;
1078 opp-microvolt = <1050 1005 opp-microvolt = <1050000>;
1079 }; 1006 };
1080 opp-480000000 { 1007 opp-480000000 {
1081 opp-hz = /bits/ 64 <4 1008 opp-hz = /bits/ 64 <480000000>;
1082 opp-microvolt = <1125 1009 opp-microvolt = <1125000>;
1083 }; 1010 };
1084 }; 1011 };
1085 1012
1086 gpu: gpu@ff400000 { 1013 gpu: gpu@ff400000 {
1087 compatible = "rockchip,px30-m 1014 compatible = "rockchip,px30-mali", "arm,mali-bifrost";
1088 reg = <0x0 0xff400000 0x0 0x4 1015 reg = <0x0 0xff400000 0x0 0x4000>;
1089 interrupts = <GIC_SPI 47 IRQ_ 1016 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
1090 <GIC_SPI 46 IRQ_ 1017 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
1091 <GIC_SPI 45 IRQ_ 1018 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
1092 interrupt-names = "job", "mmu 1019 interrupt-names = "job", "mmu", "gpu";
1093 clocks = <&cru SCLK_GPU>; 1020 clocks = <&cru SCLK_GPU>;
1094 #cooling-cells = <2>; 1021 #cooling-cells = <2>;
1095 power-domains = <&power PX30_ 1022 power-domains = <&power PX30_PD_GPU>;
1096 operating-points-v2 = <&gpu_o 1023 operating-points-v2 = <&gpu_opp_table>;
1097 status = "disabled"; 1024 status = "disabled";
1098 }; 1025 };
1099 1026
1100 vpu: video-codec@ff442000 { <<
1101 compatible = "rockchip,px30-v <<
1102 reg = <0x0 0xff442000 0x0 0x8 <<
1103 interrupts = <GIC_SPI 80 IRQ_ <<
1104 <GIC_SPI 79 IRQ_ <<
1105 interrupt-names = "vepu", "vd <<
1106 clocks = <&cru ACLK_VPU>, <&c <<
1107 clock-names = "aclk", "hclk"; <<
1108 iommus = <&vpu_mmu>; <<
1109 power-domains = <&power PX30_ <<
1110 }; <<
1111 <<
1112 vpu_mmu: iommu@ff442800 { <<
1113 compatible = "rockchip,iommu" <<
1114 reg = <0x0 0xff442800 0x0 0x1 <<
1115 interrupts = <GIC_SPI 81 IRQ_ <<
1116 clocks = <&cru ACLK_VPU>, <&c <<
1117 clock-names = "aclk", "iface" <<
1118 #iommu-cells = <0>; <<
1119 power-domains = <&power PX30_ <<
1120 }; <<
1121 <<
1122 dsi: dsi@ff450000 { 1027 dsi: dsi@ff450000 {
1123 compatible = "rockchip,px30-m !! 1028 compatible = "rockchip,px30-mipi-dsi";
1124 reg = <0x0 0xff450000 0x0 0x1 1029 reg = <0x0 0xff450000 0x0 0x10000>;
1125 interrupts = <GIC_SPI 75 IRQ_ 1030 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
1126 clocks = <&cru PCLK_MIPI_DSI> 1031 clocks = <&cru PCLK_MIPI_DSI>;
1127 clock-names = "pclk"; 1032 clock-names = "pclk";
1128 phys = <&dsi_dphy>; 1033 phys = <&dsi_dphy>;
1129 phy-names = "dphy"; 1034 phy-names = "dphy";
1130 power-domains = <&power PX30_ 1035 power-domains = <&power PX30_PD_VO>;
1131 resets = <&cru SRST_MIPIDSI_H 1036 resets = <&cru SRST_MIPIDSI_HOST_P>;
1132 reset-names = "apb"; 1037 reset-names = "apb";
1133 rockchip,grf = <&grf>; 1038 rockchip,grf = <&grf>;
1134 #address-cells = <1>; 1039 #address-cells = <1>;
1135 #size-cells = <0>; 1040 #size-cells = <0>;
1136 status = "disabled"; 1041 status = "disabled";
1137 1042
1138 ports { 1043 ports {
1139 #address-cells = <1>; 1044 #address-cells = <1>;
1140 #size-cells = <0>; 1045 #size-cells = <0>;
1141 1046
1142 dsi_in: port@0 { !! 1047 port@0 {
1143 reg = <0>; 1048 reg = <0>;
1144 #address-cell 1049 #address-cells = <1>;
1145 #size-cells = 1050 #size-cells = <0>;
1146 1051
1147 dsi_in_vopb: 1052 dsi_in_vopb: endpoint@0 {
1148 reg = 1053 reg = <0>;
1149 remot 1054 remote-endpoint = <&vopb_out_dsi>;
1150 }; 1055 };
1151 1056
1152 dsi_in_vopl: 1057 dsi_in_vopl: endpoint@1 {
1153 reg = 1058 reg = <1>;
1154 remot 1059 remote-endpoint = <&vopl_out_dsi>;
1155 }; 1060 };
1156 }; 1061 };
1157 <<
1158 dsi_out: port@1 { <<
1159 reg = <1>; <<
1160 }; <<
1161 }; 1062 };
1162 }; 1063 };
1163 1064
1164 vopb: vop@ff460000 { 1065 vopb: vop@ff460000 {
1165 compatible = "rockchip,px30-v 1066 compatible = "rockchip,px30-vop-big";
1166 reg = <0x0 0xff460000 0x0 0xe 1067 reg = <0x0 0xff460000 0x0 0xefc>;
1167 interrupts = <GIC_SPI 77 IRQ_ 1068 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
1168 clocks = <&cru ACLK_VOPB>, <& 1069 clocks = <&cru ACLK_VOPB>, <&cru DCLK_VOPB>,
1169 <&cru HCLK_VOPB>; 1070 <&cru HCLK_VOPB>;
1170 clock-names = "aclk_vop", "dc 1071 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1171 resets = <&cru SRST_VOPB_A>, 1072 resets = <&cru SRST_VOPB_A>, <&cru SRST_VOPB_H>, <&cru SRST_VOPB>;
1172 reset-names = "axi", "ahb", " 1073 reset-names = "axi", "ahb", "dclk";
1173 iommus = <&vopb_mmu>; 1074 iommus = <&vopb_mmu>;
1174 power-domains = <&power PX30_ 1075 power-domains = <&power PX30_PD_VO>;
1175 status = "disabled"; 1076 status = "disabled";
1176 1077
1177 vopb_out: port { 1078 vopb_out: port {
1178 #address-cells = <1>; 1079 #address-cells = <1>;
1179 #size-cells = <0>; 1080 #size-cells = <0>;
1180 1081
1181 vopb_out_dsi: endpoin 1082 vopb_out_dsi: endpoint@0 {
1182 reg = <0>; 1083 reg = <0>;
1183 remote-endpoi 1084 remote-endpoint = <&dsi_in_vopb>;
1184 }; 1085 };
1185 1086
1186 vopb_out_lvds: endpoi 1087 vopb_out_lvds: endpoint@1 {
1187 reg = <1>; 1088 reg = <1>;
1188 remote-endpoi 1089 remote-endpoint = <&lvds_vopb_in>;
1189 }; 1090 };
1190 }; 1091 };
1191 }; 1092 };
1192 1093
1193 vopb_mmu: iommu@ff460f00 { 1094 vopb_mmu: iommu@ff460f00 {
1194 compatible = "rockchip,iommu" 1095 compatible = "rockchip,iommu";
1195 reg = <0x0 0xff460f00 0x0 0x1 1096 reg = <0x0 0xff460f00 0x0 0x100>;
1196 interrupts = <GIC_SPI 77 IRQ_ 1097 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
1197 clocks = <&cru ACLK_VOPB>, <& 1098 clocks = <&cru ACLK_VOPB>, <&cru HCLK_VOPB>;
1198 clock-names = "aclk", "iface" 1099 clock-names = "aclk", "iface";
1199 power-domains = <&power PX30_ 1100 power-domains = <&power PX30_PD_VO>;
1200 #iommu-cells = <0>; 1101 #iommu-cells = <0>;
1201 status = "disabled"; 1102 status = "disabled";
1202 }; 1103 };
1203 1104
1204 vopl: vop@ff470000 { 1105 vopl: vop@ff470000 {
1205 compatible = "rockchip,px30-v 1106 compatible = "rockchip,px30-vop-lit";
1206 reg = <0x0 0xff470000 0x0 0xe 1107 reg = <0x0 0xff470000 0x0 0xefc>;
1207 interrupts = <GIC_SPI 78 IRQ_ 1108 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
1208 clocks = <&cru ACLK_VOPL>, <& 1109 clocks = <&cru ACLK_VOPL>, <&cru DCLK_VOPL>,
1209 <&cru HCLK_VOPL>; 1110 <&cru HCLK_VOPL>;
1210 clock-names = "aclk_vop", "dc 1111 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1211 resets = <&cru SRST_VOPL_A>, 1112 resets = <&cru SRST_VOPL_A>, <&cru SRST_VOPL_H>, <&cru SRST_VOPL>;
1212 reset-names = "axi", "ahb", " 1113 reset-names = "axi", "ahb", "dclk";
1213 iommus = <&vopl_mmu>; 1114 iommus = <&vopl_mmu>;
1214 power-domains = <&power PX30_ 1115 power-domains = <&power PX30_PD_VO>;
1215 status = "disabled"; 1116 status = "disabled";
1216 1117
1217 vopl_out: port { 1118 vopl_out: port {
1218 #address-cells = <1>; 1119 #address-cells = <1>;
1219 #size-cells = <0>; 1120 #size-cells = <0>;
1220 1121
1221 vopl_out_dsi: endpoin 1122 vopl_out_dsi: endpoint@0 {
1222 reg = <0>; 1123 reg = <0>;
1223 remote-endpoi 1124 remote-endpoint = <&dsi_in_vopl>;
1224 }; 1125 };
1225 1126
1226 vopl_out_lvds: endpoi 1127 vopl_out_lvds: endpoint@1 {
1227 reg = <1>; 1128 reg = <1>;
1228 remote-endpoi 1129 remote-endpoint = <&lvds_vopl_in>;
1229 }; 1130 };
1230 }; 1131 };
1231 }; 1132 };
1232 1133
1233 vopl_mmu: iommu@ff470f00 { 1134 vopl_mmu: iommu@ff470f00 {
1234 compatible = "rockchip,iommu" 1135 compatible = "rockchip,iommu";
1235 reg = <0x0 0xff470f00 0x0 0x1 1136 reg = <0x0 0xff470f00 0x0 0x100>;
1236 interrupts = <GIC_SPI 78 IRQ_ 1137 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
1237 clocks = <&cru ACLK_VOPL>, <& 1138 clocks = <&cru ACLK_VOPL>, <&cru HCLK_VOPL>;
1238 clock-names = "aclk", "iface" 1139 clock-names = "aclk", "iface";
1239 power-domains = <&power PX30_ 1140 power-domains = <&power PX30_PD_VO>;
1240 #iommu-cells = <0>; 1141 #iommu-cells = <0>;
1241 status = "disabled"; 1142 status = "disabled";
1242 }; 1143 };
1243 1144
1244 isp: isp@ff4a0000 { <<
1245 compatible = "rockchip,px30-c <<
1246 reg = <0x0 0xff4a0000 0x0 0x8 <<
1247 interrupts = <GIC_SPI 70 IRQ_ <<
1248 <GIC_SPI 73 IRQ_ <<
1249 <GIC_SPI 74 IRQ_ <<
1250 interrupt-names = "isp", "mi" <<
1251 clocks = <&cru SCLK_ISP>, <<
1252 <&cru ACLK_ISP>, <<
1253 <&cru HCLK_ISP>, <<
1254 <&cru PCLK_ISP>; <<
1255 clock-names = "isp", "aclk", <<
1256 iommus = <&isp_mmu>; <<
1257 phys = <&csi_dphy>; <<
1258 phy-names = "dphy"; <<
1259 power-domains = <&power PX30_ <<
1260 status = "disabled"; <<
1261 <<
1262 ports { <<
1263 #address-cells = <1>; <<
1264 #size-cells = <0>; <<
1265 <<
1266 port@0 { <<
1267 reg = <0>; <<
1268 #address-cell <<
1269 #size-cells = <<
1270 }; <<
1271 }; <<
1272 }; <<
1273 <<
1274 isp_mmu: iommu@ff4a8000 { <<
1275 compatible = "rockchip,iommu" <<
1276 reg = <0x0 0xff4a8000 0x0 0x1 <<
1277 interrupts = <GIC_SPI 70 IRQ_ <<
1278 clocks = <&cru ACLK_ISP>, <&c <<
1279 clock-names = "aclk", "iface" <<
1280 power-domains = <&power PX30_ <<
1281 rockchip,disable-mmu-reset; <<
1282 #iommu-cells = <0>; <<
1283 }; <<
1284 <<
1285 qos_gmac: qos@ff518000 { 1145 qos_gmac: qos@ff518000 {
1286 compatible = "rockchip,px30-q 1146 compatible = "rockchip,px30-qos", "syscon";
1287 reg = <0x0 0xff518000 0x0 0x2 1147 reg = <0x0 0xff518000 0x0 0x20>;
1288 }; 1148 };
1289 1149
1290 qos_gpu: qos@ff520000 { 1150 qos_gpu: qos@ff520000 {
1291 compatible = "rockchip,px30-q 1151 compatible = "rockchip,px30-qos", "syscon";
1292 reg = <0x0 0xff520000 0x0 0x2 1152 reg = <0x0 0xff520000 0x0 0x20>;
1293 }; 1153 };
1294 1154
1295 qos_sdmmc: qos@ff52c000 { 1155 qos_sdmmc: qos@ff52c000 {
1296 compatible = "rockchip,px30-q 1156 compatible = "rockchip,px30-qos", "syscon";
1297 reg = <0x0 0xff52c000 0x0 0x2 1157 reg = <0x0 0xff52c000 0x0 0x20>;
1298 }; 1158 };
1299 1159
1300 qos_emmc: qos@ff538000 { 1160 qos_emmc: qos@ff538000 {
1301 compatible = "rockchip,px30-q 1161 compatible = "rockchip,px30-qos", "syscon";
1302 reg = <0x0 0xff538000 0x0 0x2 1162 reg = <0x0 0xff538000 0x0 0x20>;
1303 }; 1163 };
1304 1164
1305 qos_nand: qos@ff538080 { 1165 qos_nand: qos@ff538080 {
1306 compatible = "rockchip,px30-q 1166 compatible = "rockchip,px30-qos", "syscon";
1307 reg = <0x0 0xff538080 0x0 0x2 1167 reg = <0x0 0xff538080 0x0 0x20>;
1308 }; 1168 };
1309 1169
1310 qos_sdio: qos@ff538100 { 1170 qos_sdio: qos@ff538100 {
1311 compatible = "rockchip,px30-q 1171 compatible = "rockchip,px30-qos", "syscon";
1312 reg = <0x0 0xff538100 0x0 0x2 1172 reg = <0x0 0xff538100 0x0 0x20>;
1313 }; 1173 };
1314 1174
1315 qos_sfc: qos@ff538180 { 1175 qos_sfc: qos@ff538180 {
1316 compatible = "rockchip,px30-q 1176 compatible = "rockchip,px30-qos", "syscon";
1317 reg = <0x0 0xff538180 0x0 0x2 1177 reg = <0x0 0xff538180 0x0 0x20>;
1318 }; 1178 };
1319 1179
1320 qos_usb_host: qos@ff540000 { 1180 qos_usb_host: qos@ff540000 {
1321 compatible = "rockchip,px30-q 1181 compatible = "rockchip,px30-qos", "syscon";
1322 reg = <0x0 0xff540000 0x0 0x2 1182 reg = <0x0 0xff540000 0x0 0x20>;
1323 }; 1183 };
1324 1184
1325 qos_usb_otg: qos@ff540080 { 1185 qos_usb_otg: qos@ff540080 {
1326 compatible = "rockchip,px30-q 1186 compatible = "rockchip,px30-qos", "syscon";
1327 reg = <0x0 0xff540080 0x0 0x2 1187 reg = <0x0 0xff540080 0x0 0x20>;
1328 }; 1188 };
1329 1189
1330 qos_isp_128: qos@ff548000 { 1190 qos_isp_128: qos@ff548000 {
1331 compatible = "rockchip,px30-q 1191 compatible = "rockchip,px30-qos", "syscon";
1332 reg = <0x0 0xff548000 0x0 0x2 1192 reg = <0x0 0xff548000 0x0 0x20>;
1333 }; 1193 };
1334 1194
1335 qos_isp_rd: qos@ff548080 { 1195 qos_isp_rd: qos@ff548080 {
1336 compatible = "rockchip,px30-q 1196 compatible = "rockchip,px30-qos", "syscon";
1337 reg = <0x0 0xff548080 0x0 0x2 1197 reg = <0x0 0xff548080 0x0 0x20>;
1338 }; 1198 };
1339 1199
1340 qos_isp_wr: qos@ff548100 { 1200 qos_isp_wr: qos@ff548100 {
1341 compatible = "rockchip,px30-q 1201 compatible = "rockchip,px30-qos", "syscon";
1342 reg = <0x0 0xff548100 0x0 0x2 1202 reg = <0x0 0xff548100 0x0 0x20>;
1343 }; 1203 };
1344 1204
1345 qos_isp_m1: qos@ff548180 { 1205 qos_isp_m1: qos@ff548180 {
1346 compatible = "rockchip,px30-q 1206 compatible = "rockchip,px30-qos", "syscon";
1347 reg = <0x0 0xff548180 0x0 0x2 1207 reg = <0x0 0xff548180 0x0 0x20>;
1348 }; 1208 };
1349 1209
1350 qos_vip: qos@ff548200 { 1210 qos_vip: qos@ff548200 {
1351 compatible = "rockchip,px30-q 1211 compatible = "rockchip,px30-qos", "syscon";
1352 reg = <0x0 0xff548200 0x0 0x2 1212 reg = <0x0 0xff548200 0x0 0x20>;
1353 }; 1213 };
1354 1214
1355 qos_rga_rd: qos@ff550000 { 1215 qos_rga_rd: qos@ff550000 {
1356 compatible = "rockchip,px30-q 1216 compatible = "rockchip,px30-qos", "syscon";
1357 reg = <0x0 0xff550000 0x0 0x2 1217 reg = <0x0 0xff550000 0x0 0x20>;
1358 }; 1218 };
1359 1219
1360 qos_rga_wr: qos@ff550080 { 1220 qos_rga_wr: qos@ff550080 {
1361 compatible = "rockchip,px30-q 1221 compatible = "rockchip,px30-qos", "syscon";
1362 reg = <0x0 0xff550080 0x0 0x2 1222 reg = <0x0 0xff550080 0x0 0x20>;
1363 }; 1223 };
1364 1224
1365 qos_vop_m0: qos@ff550100 { 1225 qos_vop_m0: qos@ff550100 {
1366 compatible = "rockchip,px30-q 1226 compatible = "rockchip,px30-qos", "syscon";
1367 reg = <0x0 0xff550100 0x0 0x2 1227 reg = <0x0 0xff550100 0x0 0x20>;
1368 }; 1228 };
1369 1229
1370 qos_vop_m1: qos@ff550180 { 1230 qos_vop_m1: qos@ff550180 {
1371 compatible = "rockchip,px30-q 1231 compatible = "rockchip,px30-qos", "syscon";
1372 reg = <0x0 0xff550180 0x0 0x2 1232 reg = <0x0 0xff550180 0x0 0x20>;
1373 }; 1233 };
1374 1234
1375 qos_vpu: qos@ff558000 { 1235 qos_vpu: qos@ff558000 {
1376 compatible = "rockchip,px30-q 1236 compatible = "rockchip,px30-qos", "syscon";
1377 reg = <0x0 0xff558000 0x0 0x2 1237 reg = <0x0 0xff558000 0x0 0x20>;
1378 }; 1238 };
1379 1239
1380 qos_vpu_r128: qos@ff558080 { 1240 qos_vpu_r128: qos@ff558080 {
1381 compatible = "rockchip,px30-q 1241 compatible = "rockchip,px30-qos", "syscon";
1382 reg = <0x0 0xff558080 0x0 0x2 1242 reg = <0x0 0xff558080 0x0 0x20>;
1383 }; 1243 };
1384 1244
1385 pinctrl: pinctrl { 1245 pinctrl: pinctrl {
1386 compatible = "rockchip,px30-p 1246 compatible = "rockchip,px30-pinctrl";
1387 rockchip,grf = <&grf>; 1247 rockchip,grf = <&grf>;
1388 rockchip,pmu = <&pmugrf>; 1248 rockchip,pmu = <&pmugrf>;
1389 #address-cells = <2>; 1249 #address-cells = <2>;
1390 #size-cells = <2>; 1250 #size-cells = <2>;
1391 ranges; 1251 ranges;
1392 1252
1393 gpio0: gpio@ff040000 { !! 1253 gpio0: gpio0@ff040000 {
1394 compatible = "rockchi 1254 compatible = "rockchip,gpio-bank";
1395 reg = <0x0 0xff040000 1255 reg = <0x0 0xff040000 0x0 0x100>;
1396 interrupts = <GIC_SPI 1256 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
1397 clocks = <&pmucru PCL 1257 clocks = <&pmucru PCLK_GPIO0_PMU>;
1398 gpio-controller; 1258 gpio-controller;
1399 #gpio-cells = <2>; 1259 #gpio-cells = <2>;
1400 1260
1401 interrupt-controller; 1261 interrupt-controller;
1402 #interrupt-cells = <2 1262 #interrupt-cells = <2>;
1403 }; 1263 };
1404 1264
1405 gpio1: gpio@ff250000 { !! 1265 gpio1: gpio1@ff250000 {
1406 compatible = "rockchi 1266 compatible = "rockchip,gpio-bank";
1407 reg = <0x0 0xff250000 1267 reg = <0x0 0xff250000 0x0 0x100>;
1408 interrupts = <GIC_SPI 1268 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
1409 clocks = <&cru PCLK_G 1269 clocks = <&cru PCLK_GPIO1>;
1410 gpio-controller; 1270 gpio-controller;
1411 #gpio-cells = <2>; 1271 #gpio-cells = <2>;
1412 1272
1413 interrupt-controller; 1273 interrupt-controller;
1414 #interrupt-cells = <2 1274 #interrupt-cells = <2>;
1415 }; 1275 };
1416 1276
1417 gpio2: gpio@ff260000 { !! 1277 gpio2: gpio2@ff260000 {
1418 compatible = "rockchi 1278 compatible = "rockchip,gpio-bank";
1419 reg = <0x0 0xff260000 1279 reg = <0x0 0xff260000 0x0 0x100>;
1420 interrupts = <GIC_SPI 1280 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
1421 clocks = <&cru PCLK_G 1281 clocks = <&cru PCLK_GPIO2>;
1422 gpio-controller; 1282 gpio-controller;
1423 #gpio-cells = <2>; 1283 #gpio-cells = <2>;
1424 1284
1425 interrupt-controller; 1285 interrupt-controller;
1426 #interrupt-cells = <2 1286 #interrupt-cells = <2>;
1427 }; 1287 };
1428 1288
1429 gpio3: gpio@ff270000 { !! 1289 gpio3: gpio3@ff270000 {
1430 compatible = "rockchi 1290 compatible = "rockchip,gpio-bank";
1431 reg = <0x0 0xff270000 1291 reg = <0x0 0xff270000 0x0 0x100>;
1432 interrupts = <GIC_SPI 1292 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
1433 clocks = <&cru PCLK_G 1293 clocks = <&cru PCLK_GPIO3>;
1434 gpio-controller; 1294 gpio-controller;
1435 #gpio-cells = <2>; 1295 #gpio-cells = <2>;
1436 1296
1437 interrupt-controller; 1297 interrupt-controller;
1438 #interrupt-cells = <2 1298 #interrupt-cells = <2>;
1439 }; 1299 };
1440 1300
1441 pcfg_pull_up: pcfg-pull-up { 1301 pcfg_pull_up: pcfg-pull-up {
1442 bias-pull-up; 1302 bias-pull-up;
1443 }; 1303 };
1444 1304
1445 pcfg_pull_down: pcfg-pull-dow 1305 pcfg_pull_down: pcfg-pull-down {
1446 bias-pull-down; 1306 bias-pull-down;
1447 }; 1307 };
1448 1308
1449 pcfg_pull_none: pcfg-pull-non 1309 pcfg_pull_none: pcfg-pull-none {
1450 bias-disable; 1310 bias-disable;
1451 }; 1311 };
1452 1312
1453 pcfg_pull_none_2ma: pcfg-pull 1313 pcfg_pull_none_2ma: pcfg-pull-none-2ma {
1454 bias-disable; 1314 bias-disable;
1455 drive-strength = <2>; 1315 drive-strength = <2>;
1456 }; 1316 };
1457 1317
1458 pcfg_pull_up_2ma: pcfg-pull-u 1318 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
1459 bias-pull-up; 1319 bias-pull-up;
1460 drive-strength = <2>; 1320 drive-strength = <2>;
1461 }; 1321 };
1462 1322
1463 pcfg_pull_up_4ma: pcfg-pull-u 1323 pcfg_pull_up_4ma: pcfg-pull-up-4ma {
1464 bias-pull-up; 1324 bias-pull-up;
1465 drive-strength = <4>; 1325 drive-strength = <4>;
1466 }; 1326 };
1467 1327
1468 pcfg_pull_none_4ma: pcfg-pull 1328 pcfg_pull_none_4ma: pcfg-pull-none-4ma {
1469 bias-disable; 1329 bias-disable;
1470 drive-strength = <4>; 1330 drive-strength = <4>;
1471 }; 1331 };
1472 1332
1473 pcfg_pull_down_4ma: pcfg-pull 1333 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
1474 bias-pull-down; 1334 bias-pull-down;
1475 drive-strength = <4>; 1335 drive-strength = <4>;
1476 }; 1336 };
1477 1337
1478 pcfg_pull_none_8ma: pcfg-pull 1338 pcfg_pull_none_8ma: pcfg-pull-none-8ma {
1479 bias-disable; 1339 bias-disable;
1480 drive-strength = <8>; 1340 drive-strength = <8>;
1481 }; 1341 };
1482 1342
1483 pcfg_pull_up_8ma: pcfg-pull-u 1343 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
1484 bias-pull-up; 1344 bias-pull-up;
1485 drive-strength = <8>; 1345 drive-strength = <8>;
1486 }; 1346 };
1487 1347
1488 pcfg_pull_none_12ma: pcfg-pul 1348 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1489 bias-disable; 1349 bias-disable;
1490 drive-strength = <12> 1350 drive-strength = <12>;
1491 }; 1351 };
1492 1352
1493 pcfg_pull_up_12ma: pcfg-pull- 1353 pcfg_pull_up_12ma: pcfg-pull-up-12ma {
1494 bias-pull-up; 1354 bias-pull-up;
1495 drive-strength = <12> 1355 drive-strength = <12>;
1496 }; 1356 };
1497 1357
1498 pcfg_pull_none_smt: pcfg-pull 1358 pcfg_pull_none_smt: pcfg-pull-none-smt {
1499 bias-disable; 1359 bias-disable;
1500 input-schmitt-enable; 1360 input-schmitt-enable;
1501 }; 1361 };
1502 1362
1503 pcfg_output_high: pcfg-output 1363 pcfg_output_high: pcfg-output-high {
1504 output-high; 1364 output-high;
1505 }; 1365 };
1506 1366
1507 pcfg_output_low: pcfg-output- 1367 pcfg_output_low: pcfg-output-low {
1508 output-low; 1368 output-low;
1509 }; 1369 };
1510 1370
1511 pcfg_input_high: pcfg-input-h 1371 pcfg_input_high: pcfg-input-high {
1512 bias-pull-up; 1372 bias-pull-up;
1513 input-enable; 1373 input-enable;
1514 }; 1374 };
1515 1375
1516 pcfg_input: pcfg-input { 1376 pcfg_input: pcfg-input {
1517 input-enable; 1377 input-enable;
1518 }; 1378 };
1519 1379
1520 i2c0 { 1380 i2c0 {
1521 i2c0_xfer: i2c0-xfer 1381 i2c0_xfer: i2c0-xfer {
1522 rockchip,pins 1382 rockchip,pins =
1523 <0 RK 1383 <0 RK_PB0 1 &pcfg_pull_none_smt>,
1524 <0 RK 1384 <0 RK_PB1 1 &pcfg_pull_none_smt>;
1525 }; 1385 };
1526 }; 1386 };
1527 1387
1528 i2c1 { 1388 i2c1 {
1529 i2c1_xfer: i2c1-xfer 1389 i2c1_xfer: i2c1-xfer {
1530 rockchip,pins 1390 rockchip,pins =
1531 <0 RK 1391 <0 RK_PC2 1 &pcfg_pull_none_smt>,
1532 <0 RK 1392 <0 RK_PC3 1 &pcfg_pull_none_smt>;
1533 }; 1393 };
1534 }; 1394 };
1535 1395
1536 i2c2 { 1396 i2c2 {
1537 i2c2_xfer: i2c2-xfer 1397 i2c2_xfer: i2c2-xfer {
1538 rockchip,pins 1398 rockchip,pins =
1539 <2 RK 1399 <2 RK_PB7 2 &pcfg_pull_none_smt>,
1540 <2 RK 1400 <2 RK_PC0 2 &pcfg_pull_none_smt>;
1541 }; 1401 };
1542 }; 1402 };
1543 1403
1544 i2c3 { 1404 i2c3 {
1545 i2c3_xfer: i2c3-xfer 1405 i2c3_xfer: i2c3-xfer {
1546 rockchip,pins 1406 rockchip,pins =
1547 <1 RK 1407 <1 RK_PB4 4 &pcfg_pull_none_smt>,
1548 <1 RK 1408 <1 RK_PB5 4 &pcfg_pull_none_smt>;
1549 }; 1409 };
1550 }; 1410 };
1551 1411
1552 tsadc { 1412 tsadc {
1553 tsadc_otp_pin: tsadc- 1413 tsadc_otp_pin: tsadc-otp-pin {
1554 rockchip,pins 1414 rockchip,pins =
1555 <0 RK 1415 <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
1556 }; 1416 };
1557 1417
1558 tsadc_otp_out: tsadc- 1418 tsadc_otp_out: tsadc-otp-out {
1559 rockchip,pins 1419 rockchip,pins =
1560 <0 RK 1420 <0 RK_PA6 1 &pcfg_pull_none>;
1561 }; 1421 };
1562 }; 1422 };
1563 1423
1564 uart0 { 1424 uart0 {
1565 uart0_xfer: uart0-xfe 1425 uart0_xfer: uart0-xfer {
1566 rockchip,pins 1426 rockchip,pins =
1567 <0 RK 1427 <0 RK_PB2 1 &pcfg_pull_up>,
1568 <0 RK 1428 <0 RK_PB3 1 &pcfg_pull_up>;
1569 }; 1429 };
1570 1430
1571 uart0_cts: uart0-cts 1431 uart0_cts: uart0-cts {
1572 rockchip,pins 1432 rockchip,pins =
1573 <0 RK 1433 <0 RK_PB4 1 &pcfg_pull_none>;
1574 }; 1434 };
1575 1435
1576 uart0_rts: uart0-rts 1436 uart0_rts: uart0-rts {
1577 rockchip,pins 1437 rockchip,pins =
1578 <0 RK 1438 <0 RK_PB5 1 &pcfg_pull_none>;
1579 }; 1439 };
1580 }; 1440 };
1581 1441
1582 uart1 { 1442 uart1 {
1583 uart1_xfer: uart1-xfe 1443 uart1_xfer: uart1-xfer {
1584 rockchip,pins 1444 rockchip,pins =
1585 <1 RK 1445 <1 RK_PC1 1 &pcfg_pull_up>,
1586 <1 RK 1446 <1 RK_PC0 1 &pcfg_pull_up>;
1587 }; 1447 };
1588 1448
1589 uart1_cts: uart1-cts 1449 uart1_cts: uart1-cts {
1590 rockchip,pins 1450 rockchip,pins =
1591 <1 RK 1451 <1 RK_PC2 1 &pcfg_pull_none>;
1592 }; 1452 };
1593 1453
1594 uart1_rts: uart1-rts 1454 uart1_rts: uart1-rts {
1595 rockchip,pins 1455 rockchip,pins =
1596 <1 RK 1456 <1 RK_PC3 1 &pcfg_pull_none>;
1597 }; 1457 };
1598 }; 1458 };
1599 1459
1600 uart2-m0 { 1460 uart2-m0 {
1601 uart2m0_xfer: uart2m0 1461 uart2m0_xfer: uart2m0-xfer {
1602 rockchip,pins 1462 rockchip,pins =
1603 <1 RK 1463 <1 RK_PD2 2 &pcfg_pull_up>,
1604 <1 RK 1464 <1 RK_PD3 2 &pcfg_pull_up>;
1605 }; 1465 };
1606 }; 1466 };
1607 1467
1608 uart2-m1 { 1468 uart2-m1 {
1609 uart2m1_xfer: uart2m1 1469 uart2m1_xfer: uart2m1-xfer {
1610 rockchip,pins 1470 rockchip,pins =
1611 <2 RK 1471 <2 RK_PB4 2 &pcfg_pull_up>,
1612 <2 RK 1472 <2 RK_PB6 2 &pcfg_pull_up>;
1613 }; 1473 };
1614 }; 1474 };
1615 1475
1616 uart3-m0 { 1476 uart3-m0 {
1617 uart3m0_xfer: uart3m0 1477 uart3m0_xfer: uart3m0-xfer {
1618 rockchip,pins 1478 rockchip,pins =
1619 <0 RK 1479 <0 RK_PC0 2 &pcfg_pull_up>,
1620 <0 RK 1480 <0 RK_PC1 2 &pcfg_pull_up>;
1621 }; 1481 };
1622 1482
1623 uart3m0_cts: uart3m0- 1483 uart3m0_cts: uart3m0-cts {
1624 rockchip,pins 1484 rockchip,pins =
1625 <0 RK 1485 <0 RK_PC2 2 &pcfg_pull_none>;
1626 }; 1486 };
1627 1487
1628 uart3m0_rts: uart3m0- 1488 uart3m0_rts: uart3m0-rts {
1629 rockchip,pins 1489 rockchip,pins =
1630 <0 RK 1490 <0 RK_PC3 2 &pcfg_pull_none>;
1631 }; 1491 };
1632 }; 1492 };
1633 1493
1634 uart3-m1 { 1494 uart3-m1 {
1635 uart3m1_xfer: uart3m1 1495 uart3m1_xfer: uart3m1-xfer {
1636 rockchip,pins 1496 rockchip,pins =
1637 <1 RK 1497 <1 RK_PB6 2 &pcfg_pull_up>,
1638 <1 RK 1498 <1 RK_PB7 2 &pcfg_pull_up>;
1639 }; 1499 };
1640 1500
1641 uart3m1_cts: uart3m1- 1501 uart3m1_cts: uart3m1-cts {
1642 rockchip,pins 1502 rockchip,pins =
1643 <1 RK 1503 <1 RK_PB4 2 &pcfg_pull_none>;
1644 }; 1504 };
1645 1505
1646 uart3m1_rts: uart3m1- 1506 uart3m1_rts: uart3m1-rts {
1647 rockchip,pins 1507 rockchip,pins =
1648 <1 RK 1508 <1 RK_PB5 2 &pcfg_pull_none>;
1649 }; 1509 };
1650 }; 1510 };
1651 1511
1652 uart4 { 1512 uart4 {
1653 uart4_xfer: uart4-xfe 1513 uart4_xfer: uart4-xfer {
1654 rockchip,pins 1514 rockchip,pins =
1655 <1 RK 1515 <1 RK_PD4 2 &pcfg_pull_up>,
1656 <1 RK 1516 <1 RK_PD5 2 &pcfg_pull_up>;
1657 }; 1517 };
1658 1518
1659 uart4_cts: uart4-cts 1519 uart4_cts: uart4-cts {
1660 rockchip,pins 1520 rockchip,pins =
1661 <1 RK 1521 <1 RK_PD6 2 &pcfg_pull_none>;
1662 }; 1522 };
1663 1523
1664 uart4_rts: uart4-rts 1524 uart4_rts: uart4-rts {
1665 rockchip,pins 1525 rockchip,pins =
1666 <1 RK 1526 <1 RK_PD7 2 &pcfg_pull_none>;
1667 }; 1527 };
1668 }; 1528 };
1669 1529
1670 uart5 { 1530 uart5 {
1671 uart5_xfer: uart5-xfe 1531 uart5_xfer: uart5-xfer {
1672 rockchip,pins 1532 rockchip,pins =
1673 <3 RK 1533 <3 RK_PA2 4 &pcfg_pull_up>,
1674 <3 RK 1534 <3 RK_PA1 4 &pcfg_pull_up>;
1675 }; 1535 };
1676 1536
1677 uart5_cts: uart5-cts 1537 uart5_cts: uart5-cts {
1678 rockchip,pins 1538 rockchip,pins =
1679 <3 RK 1539 <3 RK_PA3 4 &pcfg_pull_none>;
1680 }; 1540 };
1681 1541
1682 uart5_rts: uart5-rts 1542 uart5_rts: uart5-rts {
1683 rockchip,pins 1543 rockchip,pins =
1684 <3 RK 1544 <3 RK_PA5 4 &pcfg_pull_none>;
1685 }; 1545 };
1686 }; 1546 };
1687 1547
1688 spi0 { 1548 spi0 {
1689 spi0_clk: spi0-clk { 1549 spi0_clk: spi0-clk {
1690 rockchip,pins 1550 rockchip,pins =
1691 <1 RK 1551 <1 RK_PB7 3 &pcfg_pull_up_4ma>;
1692 }; 1552 };
1693 1553
1694 spi0_csn: spi0-csn { 1554 spi0_csn: spi0-csn {
1695 rockchip,pins 1555 rockchip,pins =
1696 <1 RK 1556 <1 RK_PB6 3 &pcfg_pull_up_4ma>;
1697 }; 1557 };
1698 1558
1699 spi0_miso: spi0-miso 1559 spi0_miso: spi0-miso {
1700 rockchip,pins 1560 rockchip,pins =
1701 <1 RK 1561 <1 RK_PB5 3 &pcfg_pull_up_4ma>;
1702 }; 1562 };
1703 1563
1704 spi0_mosi: spi0-mosi 1564 spi0_mosi: spi0-mosi {
1705 rockchip,pins 1565 rockchip,pins =
1706 <1 RK 1566 <1 RK_PB4 3 &pcfg_pull_up_4ma>;
1707 }; 1567 };
1708 1568
1709 spi0_clk_hs: spi0-clk 1569 spi0_clk_hs: spi0-clk-hs {
1710 rockchip,pins 1570 rockchip,pins =
1711 <1 RK 1571 <1 RK_PB7 3 &pcfg_pull_up_8ma>;
1712 }; 1572 };
1713 1573
1714 spi0_miso_hs: spi0-mi 1574 spi0_miso_hs: spi0-miso-hs {
1715 rockchip,pins 1575 rockchip,pins =
1716 <1 RK 1576 <1 RK_PB5 3 &pcfg_pull_up_8ma>;
1717 }; 1577 };
1718 1578
1719 spi0_mosi_hs: spi0-mo 1579 spi0_mosi_hs: spi0-mosi-hs {
1720 rockchip,pins 1580 rockchip,pins =
1721 <1 RK 1581 <1 RK_PB4 3 &pcfg_pull_up_8ma>;
1722 }; 1582 };
1723 }; 1583 };
1724 1584
1725 spi1 { 1585 spi1 {
1726 spi1_clk: spi1-clk { 1586 spi1_clk: spi1-clk {
1727 rockchip,pins 1587 rockchip,pins =
1728 <3 RK 1588 <3 RK_PB7 4 &pcfg_pull_up_4ma>;
1729 }; 1589 };
1730 1590
1731 spi1_csn0: spi1-csn0 1591 spi1_csn0: spi1-csn0 {
1732 rockchip,pins 1592 rockchip,pins =
1733 <3 RK 1593 <3 RK_PB1 4 &pcfg_pull_up_4ma>;
1734 }; 1594 };
1735 1595
1736 spi1_csn1: spi1-csn1 1596 spi1_csn1: spi1-csn1 {
1737 rockchip,pins 1597 rockchip,pins =
1738 <3 RK 1598 <3 RK_PB2 2 &pcfg_pull_up_4ma>;
1739 }; 1599 };
1740 1600
1741 spi1_miso: spi1-miso 1601 spi1_miso: spi1-miso {
1742 rockchip,pins 1602 rockchip,pins =
1743 <3 RK 1603 <3 RK_PB6 4 &pcfg_pull_up_4ma>;
1744 }; 1604 };
1745 1605
1746 spi1_mosi: spi1-mosi 1606 spi1_mosi: spi1-mosi {
1747 rockchip,pins 1607 rockchip,pins =
1748 <3 RK 1608 <3 RK_PB4 4 &pcfg_pull_up_4ma>;
1749 }; 1609 };
1750 1610
1751 spi1_clk_hs: spi1-clk 1611 spi1_clk_hs: spi1-clk-hs {
1752 rockchip,pins 1612 rockchip,pins =
1753 <3 RK 1613 <3 RK_PB7 4 &pcfg_pull_up_8ma>;
1754 }; 1614 };
1755 1615
1756 spi1_miso_hs: spi1-mi 1616 spi1_miso_hs: spi1-miso-hs {
1757 rockchip,pins 1617 rockchip,pins =
1758 <3 RK 1618 <3 RK_PB6 4 &pcfg_pull_up_8ma>;
1759 }; 1619 };
1760 1620
1761 spi1_mosi_hs: spi1-mo 1621 spi1_mosi_hs: spi1-mosi-hs {
1762 rockchip,pins 1622 rockchip,pins =
1763 <3 RK 1623 <3 RK_PB4 4 &pcfg_pull_up_8ma>;
1764 }; 1624 };
1765 }; 1625 };
1766 1626
1767 pdm { 1627 pdm {
1768 pdm_clk0m0: pdm-clk0m 1628 pdm_clk0m0: pdm-clk0m0 {
1769 rockchip,pins 1629 rockchip,pins =
1770 <3 RK 1630 <3 RK_PC6 2 &pcfg_pull_none>;
1771 }; 1631 };
1772 1632
1773 pdm_clk0m1: pdm-clk0m 1633 pdm_clk0m1: pdm-clk0m1 {
1774 rockchip,pins 1634 rockchip,pins =
1775 <2 RK 1635 <2 RK_PC6 1 &pcfg_pull_none>;
1776 }; 1636 };
1777 1637
1778 pdm_clk1: pdm-clk1 { 1638 pdm_clk1: pdm-clk1 {
1779 rockchip,pins 1639 rockchip,pins =
1780 <3 RK 1640 <3 RK_PC7 2 &pcfg_pull_none>;
1781 }; 1641 };
1782 1642
1783 pdm_sdi0m0: pdm-sdi0m 1643 pdm_sdi0m0: pdm-sdi0m0 {
1784 rockchip,pins 1644 rockchip,pins =
1785 <3 RK 1645 <3 RK_PD3 2 &pcfg_pull_none>;
1786 }; 1646 };
1787 1647
1788 pdm_sdi0m1: pdm-sdi0m 1648 pdm_sdi0m1: pdm-sdi0m1 {
1789 rockchip,pins 1649 rockchip,pins =
1790 <2 RK 1650 <2 RK_PC5 2 &pcfg_pull_none>;
1791 }; 1651 };
1792 1652
1793 pdm_sdi1: pdm-sdi1 { 1653 pdm_sdi1: pdm-sdi1 {
1794 rockchip,pins 1654 rockchip,pins =
1795 <3 RK 1655 <3 RK_PD0 2 &pcfg_pull_none>;
1796 }; 1656 };
1797 1657
1798 pdm_sdi2: pdm-sdi2 { 1658 pdm_sdi2: pdm-sdi2 {
1799 rockchip,pins 1659 rockchip,pins =
1800 <3 RK 1660 <3 RK_PD1 2 &pcfg_pull_none>;
1801 }; 1661 };
1802 1662
1803 pdm_sdi3: pdm-sdi3 { 1663 pdm_sdi3: pdm-sdi3 {
1804 rockchip,pins 1664 rockchip,pins =
1805 <3 RK 1665 <3 RK_PD2 2 &pcfg_pull_none>;
1806 }; 1666 };
1807 1667
1808 pdm_clk0m0_sleep: pdm 1668 pdm_clk0m0_sleep: pdm-clk0m0-sleep {
1809 rockchip,pins 1669 rockchip,pins =
1810 <3 RK 1670 <3 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>;
1811 }; 1671 };
1812 1672
1813 pdm_clk0m_sleep1: pdm 1673 pdm_clk0m_sleep1: pdm-clk0m1-sleep {
1814 rockchip,pins 1674 rockchip,pins =
1815 <2 RK 1675 <2 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>;
1816 }; 1676 };
1817 1677
1818 pdm_clk1_sleep: pdm-c 1678 pdm_clk1_sleep: pdm-clk1-sleep {
1819 rockchip,pins 1679 rockchip,pins =
1820 <3 RK 1680 <3 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>;
1821 }; 1681 };
1822 1682
1823 pdm_sdi0m0_sleep: pdm 1683 pdm_sdi0m0_sleep: pdm-sdi0m0-sleep {
1824 rockchip,pins 1684 rockchip,pins =
1825 <3 RK 1685 <3 RK_PD3 RK_FUNC_GPIO &pcfg_input_high>;
1826 }; 1686 };
1827 1687
1828 pdm_sdi0m1_sleep: pdm 1688 pdm_sdi0m1_sleep: pdm-sdi0m1-sleep {
1829 rockchip,pins 1689 rockchip,pins =
1830 <2 RK 1690 <2 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>;
1831 }; 1691 };
1832 1692
1833 pdm_sdi1_sleep: pdm-s 1693 pdm_sdi1_sleep: pdm-sdi1-sleep {
1834 rockchip,pins 1694 rockchip,pins =
1835 <3 RK 1695 <3 RK_PD0 RK_FUNC_GPIO &pcfg_input_high>;
1836 }; 1696 };
1837 1697
1838 pdm_sdi2_sleep: pdm-s 1698 pdm_sdi2_sleep: pdm-sdi2-sleep {
1839 rockchip,pins 1699 rockchip,pins =
1840 <3 RK 1700 <3 RK_PD1 RK_FUNC_GPIO &pcfg_input_high>;
1841 }; 1701 };
1842 1702
1843 pdm_sdi3_sleep: pdm-s 1703 pdm_sdi3_sleep: pdm-sdi3-sleep {
1844 rockchip,pins 1704 rockchip,pins =
1845 <3 RK 1705 <3 RK_PD2 RK_FUNC_GPIO &pcfg_input_high>;
1846 }; 1706 };
1847 }; 1707 };
1848 1708
1849 i2s0 { 1709 i2s0 {
1850 i2s0_8ch_mclk: i2s0-8 1710 i2s0_8ch_mclk: i2s0-8ch-mclk {
1851 rockchip,pins 1711 rockchip,pins =
1852 <3 RK 1712 <3 RK_PC1 2 &pcfg_pull_none>;
1853 }; 1713 };
1854 1714
1855 i2s0_8ch_sclktx: i2s0 1715 i2s0_8ch_sclktx: i2s0-8ch-sclktx {
1856 rockchip,pins 1716 rockchip,pins =
1857 <3 RK 1717 <3 RK_PC3 2 &pcfg_pull_none>;
1858 }; 1718 };
1859 1719
1860 i2s0_8ch_sclkrx: i2s0 1720 i2s0_8ch_sclkrx: i2s0-8ch-sclkrx {
1861 rockchip,pins 1721 rockchip,pins =
1862 <3 RK 1722 <3 RK_PB4 2 &pcfg_pull_none>;
1863 }; 1723 };
1864 1724
1865 i2s0_8ch_lrcktx: i2s0 1725 i2s0_8ch_lrcktx: i2s0-8ch-lrcktx {
1866 rockchip,pins 1726 rockchip,pins =
1867 <3 RK 1727 <3 RK_PC2 2 &pcfg_pull_none>;
1868 }; 1728 };
1869 1729
1870 i2s0_8ch_lrckrx: i2s0 1730 i2s0_8ch_lrckrx: i2s0-8ch-lrckrx {
1871 rockchip,pins 1731 rockchip,pins =
1872 <3 RK 1732 <3 RK_PB5 2 &pcfg_pull_none>;
1873 }; 1733 };
1874 1734
1875 i2s0_8ch_sdo0: i2s0-8 1735 i2s0_8ch_sdo0: i2s0-8ch-sdo0 {
1876 rockchip,pins 1736 rockchip,pins =
1877 <3 RK 1737 <3 RK_PC4 2 &pcfg_pull_none>;
1878 }; 1738 };
1879 1739
1880 i2s0_8ch_sdo1: i2s0-8 1740 i2s0_8ch_sdo1: i2s0-8ch-sdo1 {
1881 rockchip,pins 1741 rockchip,pins =
1882 <3 RK 1742 <3 RK_PC0 2 &pcfg_pull_none>;
1883 }; 1743 };
1884 1744
1885 i2s0_8ch_sdo2: i2s0-8 1745 i2s0_8ch_sdo2: i2s0-8ch-sdo2 {
1886 rockchip,pins 1746 rockchip,pins =
1887 <3 RK 1747 <3 RK_PB7 2 &pcfg_pull_none>;
1888 }; 1748 };
1889 1749
1890 i2s0_8ch_sdo3: i2s0-8 1750 i2s0_8ch_sdo3: i2s0-8ch-sdo3 {
1891 rockchip,pins 1751 rockchip,pins =
1892 <3 RK 1752 <3 RK_PB6 2 &pcfg_pull_none>;
1893 }; 1753 };
1894 1754
1895 i2s0_8ch_sdi0: i2s0-8 1755 i2s0_8ch_sdi0: i2s0-8ch-sdi0 {
1896 rockchip,pins 1756 rockchip,pins =
1897 <3 RK 1757 <3 RK_PC5 2 &pcfg_pull_none>;
1898 }; 1758 };
1899 1759
1900 i2s0_8ch_sdi1: i2s0-8 1760 i2s0_8ch_sdi1: i2s0-8ch-sdi1 {
1901 rockchip,pins 1761 rockchip,pins =
1902 <3 RK 1762 <3 RK_PB3 2 &pcfg_pull_none>;
1903 }; 1763 };
1904 1764
1905 i2s0_8ch_sdi2: i2s0-8 1765 i2s0_8ch_sdi2: i2s0-8ch-sdi2 {
1906 rockchip,pins 1766 rockchip,pins =
1907 <3 RK 1767 <3 RK_PB1 2 &pcfg_pull_none>;
1908 }; 1768 };
1909 1769
1910 i2s0_8ch_sdi3: i2s0-8 1770 i2s0_8ch_sdi3: i2s0-8ch-sdi3 {
1911 rockchip,pins 1771 rockchip,pins =
1912 <3 RK 1772 <3 RK_PB0 2 &pcfg_pull_none>;
1913 }; 1773 };
1914 }; 1774 };
1915 1775
1916 i2s1 { 1776 i2s1 {
1917 i2s1_2ch_mclk: i2s1-2 1777 i2s1_2ch_mclk: i2s1-2ch-mclk {
1918 rockchip,pins 1778 rockchip,pins =
1919 <2 RK 1779 <2 RK_PC3 1 &pcfg_pull_none>;
1920 }; 1780 };
1921 1781
1922 i2s1_2ch_sclk: i2s1-2 1782 i2s1_2ch_sclk: i2s1-2ch-sclk {
1923 rockchip,pins 1783 rockchip,pins =
1924 <2 RK 1784 <2 RK_PC2 1 &pcfg_pull_none>;
1925 }; 1785 };
1926 1786
1927 i2s1_2ch_lrck: i2s1-2 1787 i2s1_2ch_lrck: i2s1-2ch-lrck {
1928 rockchip,pins 1788 rockchip,pins =
1929 <2 RK 1789 <2 RK_PC1 1 &pcfg_pull_none>;
1930 }; 1790 };
1931 1791
1932 i2s1_2ch_sdi: i2s1-2c 1792 i2s1_2ch_sdi: i2s1-2ch-sdi {
1933 rockchip,pins 1793 rockchip,pins =
1934 <2 RK 1794 <2 RK_PC5 1 &pcfg_pull_none>;
1935 }; 1795 };
1936 1796
1937 i2s1_2ch_sdo: i2s1-2c 1797 i2s1_2ch_sdo: i2s1-2ch-sdo {
1938 rockchip,pins 1798 rockchip,pins =
1939 <2 RK 1799 <2 RK_PC4 1 &pcfg_pull_none>;
1940 }; 1800 };
1941 }; 1801 };
1942 1802
1943 i2s2 { 1803 i2s2 {
1944 i2s2_2ch_mclk: i2s2-2 1804 i2s2_2ch_mclk: i2s2-2ch-mclk {
1945 rockchip,pins 1805 rockchip,pins =
1946 <3 RK 1806 <3 RK_PA1 2 &pcfg_pull_none>;
1947 }; 1807 };
1948 1808
1949 i2s2_2ch_sclk: i2s2-2 1809 i2s2_2ch_sclk: i2s2-2ch-sclk {
1950 rockchip,pins 1810 rockchip,pins =
1951 <3 RK 1811 <3 RK_PA2 2 &pcfg_pull_none>;
1952 }; 1812 };
1953 1813
1954 i2s2_2ch_lrck: i2s2-2 1814 i2s2_2ch_lrck: i2s2-2ch-lrck {
1955 rockchip,pins 1815 rockchip,pins =
1956 <3 RK 1816 <3 RK_PA3 2 &pcfg_pull_none>;
1957 }; 1817 };
1958 1818
1959 i2s2_2ch_sdi: i2s2-2c 1819 i2s2_2ch_sdi: i2s2-2ch-sdi {
1960 rockchip,pins 1820 rockchip,pins =
1961 <3 RK 1821 <3 RK_PA5 2 &pcfg_pull_none>;
1962 }; 1822 };
1963 1823
1964 i2s2_2ch_sdo: i2s2-2c 1824 i2s2_2ch_sdo: i2s2-2ch-sdo {
1965 rockchip,pins 1825 rockchip,pins =
1966 <3 RK 1826 <3 RK_PA7 2 &pcfg_pull_none>;
1967 }; 1827 };
1968 }; 1828 };
1969 1829
1970 sdmmc { 1830 sdmmc {
1971 sdmmc_clk: sdmmc-clk 1831 sdmmc_clk: sdmmc-clk {
1972 rockchip,pins 1832 rockchip,pins =
1973 <1 RK 1833 <1 RK_PD6 1 &pcfg_pull_none_8ma>;
1974 }; 1834 };
1975 1835
1976 sdmmc_cmd: sdmmc-cmd 1836 sdmmc_cmd: sdmmc-cmd {
1977 rockchip,pins 1837 rockchip,pins =
1978 <1 RK 1838 <1 RK_PD7 1 &pcfg_pull_up_8ma>;
1979 }; 1839 };
1980 1840
1981 sdmmc_det: sdmmc-det 1841 sdmmc_det: sdmmc-det {
1982 rockchip,pins 1842 rockchip,pins =
1983 <0 RK 1843 <0 RK_PA3 1 &pcfg_pull_up_8ma>;
1984 }; 1844 };
1985 1845
1986 sdmmc_bus1: sdmmc-bus 1846 sdmmc_bus1: sdmmc-bus1 {
1987 rockchip,pins 1847 rockchip,pins =
1988 <1 RK 1848 <1 RK_PD2 1 &pcfg_pull_up_8ma>;
1989 }; 1849 };
1990 1850
1991 sdmmc_bus4: sdmmc-bus 1851 sdmmc_bus4: sdmmc-bus4 {
1992 rockchip,pins 1852 rockchip,pins =
1993 <1 RK 1853 <1 RK_PD2 1 &pcfg_pull_up_8ma>,
1994 <1 RK 1854 <1 RK_PD3 1 &pcfg_pull_up_8ma>,
1995 <1 RK 1855 <1 RK_PD4 1 &pcfg_pull_up_8ma>,
1996 <1 RK 1856 <1 RK_PD5 1 &pcfg_pull_up_8ma>;
1997 }; 1857 };
1998 }; 1858 };
1999 1859
2000 sdio { 1860 sdio {
2001 sdio_clk: sdio-clk { 1861 sdio_clk: sdio-clk {
2002 rockchip,pins 1862 rockchip,pins =
2003 <1 RK 1863 <1 RK_PC5 1 &pcfg_pull_none>;
2004 }; 1864 };
2005 1865
2006 sdio_cmd: sdio-cmd { 1866 sdio_cmd: sdio-cmd {
2007 rockchip,pins 1867 rockchip,pins =
2008 <1 RK 1868 <1 RK_PC4 1 &pcfg_pull_up>;
2009 }; 1869 };
2010 1870
2011 sdio_bus4: sdio-bus4 1871 sdio_bus4: sdio-bus4 {
2012 rockchip,pins 1872 rockchip,pins =
2013 <1 RK 1873 <1 RK_PC6 1 &pcfg_pull_up>,
2014 <1 RK 1874 <1 RK_PC7 1 &pcfg_pull_up>,
2015 <1 RK 1875 <1 RK_PD0 1 &pcfg_pull_up>,
2016 <1 RK 1876 <1 RK_PD1 1 &pcfg_pull_up>;
2017 }; 1877 };
2018 }; 1878 };
2019 1879
2020 emmc { 1880 emmc {
2021 emmc_clk: emmc-clk { 1881 emmc_clk: emmc-clk {
2022 rockchip,pins 1882 rockchip,pins =
2023 <1 RK 1883 <1 RK_PB1 2 &pcfg_pull_none_8ma>;
2024 }; 1884 };
2025 1885
2026 emmc_cmd: emmc-cmd { 1886 emmc_cmd: emmc-cmd {
2027 rockchip,pins 1887 rockchip,pins =
2028 <1 RK 1888 <1 RK_PB2 2 &pcfg_pull_up_8ma>;
2029 }; 1889 };
2030 1890
2031 emmc_rstnout: emmc-rs 1891 emmc_rstnout: emmc-rstnout {
2032 rockchip,pins 1892 rockchip,pins =
2033 <1 RK 1893 <1 RK_PB3 2 &pcfg_pull_none>;
2034 }; 1894 };
2035 1895
2036 emmc_bus1: emmc-bus1 1896 emmc_bus1: emmc-bus1 {
2037 rockchip,pins 1897 rockchip,pins =
2038 <1 RK 1898 <1 RK_PA0 2 &pcfg_pull_up_8ma>;
2039 }; 1899 };
2040 1900
2041 emmc_bus4: emmc-bus4 1901 emmc_bus4: emmc-bus4 {
2042 rockchip,pins 1902 rockchip,pins =
2043 <1 RK 1903 <1 RK_PA0 2 &pcfg_pull_up_8ma>,
2044 <1 RK 1904 <1 RK_PA1 2 &pcfg_pull_up_8ma>,
2045 <1 RK 1905 <1 RK_PA2 2 &pcfg_pull_up_8ma>,
2046 <1 RK 1906 <1 RK_PA3 2 &pcfg_pull_up_8ma>;
2047 }; 1907 };
2048 1908
2049 emmc_bus8: emmc-bus8 1909 emmc_bus8: emmc-bus8 {
2050 rockchip,pins 1910 rockchip,pins =
2051 <1 RK 1911 <1 RK_PA0 2 &pcfg_pull_up_8ma>,
2052 <1 RK 1912 <1 RK_PA1 2 &pcfg_pull_up_8ma>,
2053 <1 RK 1913 <1 RK_PA2 2 &pcfg_pull_up_8ma>,
2054 <1 RK 1914 <1 RK_PA3 2 &pcfg_pull_up_8ma>,
2055 <1 RK 1915 <1 RK_PA4 2 &pcfg_pull_up_8ma>,
2056 <1 RK 1916 <1 RK_PA5 2 &pcfg_pull_up_8ma>,
2057 <1 RK 1917 <1 RK_PA6 2 &pcfg_pull_up_8ma>,
2058 <1 RK 1918 <1 RK_PA7 2 &pcfg_pull_up_8ma>;
2059 }; 1919 };
2060 }; 1920 };
2061 1921
2062 flash { 1922 flash {
2063 flash_cs0: flash-cs0 1923 flash_cs0: flash-cs0 {
2064 rockchip,pins 1924 rockchip,pins =
2065 <1 RK 1925 <1 RK_PB0 1 &pcfg_pull_none>;
2066 }; 1926 };
2067 1927
2068 flash_rdy: flash-rdy 1928 flash_rdy: flash-rdy {
2069 rockchip,pins 1929 rockchip,pins =
2070 <1 RK 1930 <1 RK_PB1 1 &pcfg_pull_none>;
2071 }; 1931 };
2072 1932
2073 flash_dqs: flash-dqs 1933 flash_dqs: flash-dqs {
2074 rockchip,pins 1934 rockchip,pins =
2075 <1 RK 1935 <1 RK_PB2 1 &pcfg_pull_none>;
2076 }; 1936 };
2077 1937
2078 flash_ale: flash-ale 1938 flash_ale: flash-ale {
2079 rockchip,pins 1939 rockchip,pins =
2080 <1 RK 1940 <1 RK_PB3 1 &pcfg_pull_none>;
2081 }; 1941 };
2082 1942
2083 flash_cle: flash-cle 1943 flash_cle: flash-cle {
2084 rockchip,pins 1944 rockchip,pins =
2085 <1 RK 1945 <1 RK_PB4 1 &pcfg_pull_none>;
2086 }; 1946 };
2087 1947
2088 flash_wrn: flash-wrn 1948 flash_wrn: flash-wrn {
2089 rockchip,pins 1949 rockchip,pins =
2090 <1 RK 1950 <1 RK_PB5 1 &pcfg_pull_none>;
2091 }; 1951 };
2092 1952
2093 flash_csl: flash-csl 1953 flash_csl: flash-csl {
2094 rockchip,pins 1954 rockchip,pins =
2095 <1 RK 1955 <1 RK_PB6 1 &pcfg_pull_none>;
2096 }; 1956 };
2097 1957
2098 flash_rdn: flash-rdn 1958 flash_rdn: flash-rdn {
2099 rockchip,pins 1959 rockchip,pins =
2100 <1 RK 1960 <1 RK_PB7 1 &pcfg_pull_none>;
2101 }; 1961 };
2102 1962
2103 flash_bus8: flash-bus 1963 flash_bus8: flash-bus8 {
2104 rockchip,pins 1964 rockchip,pins =
2105 <1 RK 1965 <1 RK_PA0 1 &pcfg_pull_up_12ma>,
2106 <1 RK 1966 <1 RK_PA1 1 &pcfg_pull_up_12ma>,
2107 <1 RK 1967 <1 RK_PA2 1 &pcfg_pull_up_12ma>,
2108 <1 RK 1968 <1 RK_PA3 1 &pcfg_pull_up_12ma>,
2109 <1 RK 1969 <1 RK_PA4 1 &pcfg_pull_up_12ma>,
2110 <1 RK 1970 <1 RK_PA5 1 &pcfg_pull_up_12ma>,
2111 <1 RK 1971 <1 RK_PA6 1 &pcfg_pull_up_12ma>,
2112 <1 RK 1972 <1 RK_PA7 1 &pcfg_pull_up_12ma>;
2113 }; <<
2114 }; <<
2115 <<
2116 sfc { <<
2117 sfc_bus4: sfc-bus4 { <<
2118 rockchip,pins <<
2119 <1 RK <<
2120 <1 RK <<
2121 <1 RK <<
2122 <1 RK <<
2123 }; <<
2124 <<
2125 sfc_bus2: sfc-bus2 { <<
2126 rockchip,pins <<
2127 <1 RK <<
2128 <1 RK <<
2129 }; <<
2130 <<
2131 sfc_cs0: sfc-cs0 { <<
2132 rockchip,pins <<
2133 <1 RK <<
2134 }; <<
2135 <<
2136 sfc_clk: sfc-clk { <<
2137 rockchip,pins <<
2138 <1 RK <<
2139 }; 1973 };
2140 }; 1974 };
2141 1975
2142 lcdc { 1976 lcdc {
2143 lcdc_rgb_dclk_pin: lc 1977 lcdc_rgb_dclk_pin: lcdc-rgb-dclk-pin {
2144 rockchip,pins 1978 rockchip,pins =
2145 <3 RK 1979 <3 RK_PA0 1 &pcfg_pull_none_12ma>;
2146 }; 1980 };
2147 1981
2148 lcdc_rgb_m0_hsync_pin 1982 lcdc_rgb_m0_hsync_pin: lcdc-rgb-m0-hsync-pin {
2149 rockchip,pins 1983 rockchip,pins =
2150 <3 RK 1984 <3 RK_PA1 1 &pcfg_pull_none_12ma>;
2151 }; 1985 };
2152 1986
2153 lcdc_rgb_m0_vsync_pin 1987 lcdc_rgb_m0_vsync_pin: lcdc-rgb-m0-vsync-pin {
2154 rockchip,pins 1988 rockchip,pins =
2155 <3 RK 1989 <3 RK_PA2 1 &pcfg_pull_none_12ma>;
2156 }; 1990 };
2157 1991
2158 lcdc_rgb_m0_den_pin: 1992 lcdc_rgb_m0_den_pin: lcdc-rgb-m0-den-pin {
2159 rockchip,pins 1993 rockchip,pins =
2160 <3 RK 1994 <3 RK_PA3 1 &pcfg_pull_none_12ma>;
2161 }; 1995 };
2162 1996
2163 lcdc_rgb888_m0_data_p 1997 lcdc_rgb888_m0_data_pins: lcdc-rgb888-m0-data-pins {
2164 rockchip,pins 1998 rockchip,pins =
2165 <3 RK 1999 <3 RK_PA7 1 &pcfg_pull_none_8ma>, /* lcdc_d3 */
2166 <3 RK 2000 <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */
2167 <3 RK 2001 <3 RK_PA5 1 &pcfg_pull_none_8ma>, /* lcdc_d1 */
2168 <3 RK 2002 <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */
2169 <3 RK 2003 <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */
2170 <3 RK 2004 <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */
2171 <3 RK 2005 <3 RK_PB1 1 &pcfg_pull_none_8ma>, /* lcdc_d5 */
2172 <3 RK 2006 <3 RK_PB0 1 &pcfg_pull_none_8ma>, /* lcdc_d4 */
2173 <3 RK 2007 <3 RK_PB7 1 &pcfg_pull_none_8ma>, /* lcdc_d11 */
2174 <3 RK 2008 <3 RK_PB6 1 &pcfg_pull_none_8ma>, /* lcdc_d10 */
2175 <3 RK 2009 <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */
2176 <3 RK 2010 <3 RK_PB4 1 &pcfg_pull_none_8ma>, /* lcdc_d8 */
2177 <3 RK 2011 <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */
2178 <3 RK 2012 <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */
2179 <3 RK 2013 <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */
2180 <3 RK 2014 <3 RK_PC0 1 &pcfg_pull_none_8ma>, /* lcdc_d12 */
2181 <3 RK 2015 <3 RK_PC7 1 &pcfg_pull_none_8ma>, /* lcdc_d19 */
2182 <3 RK 2016 <3 RK_PC6 1 &pcfg_pull_none_8ma>, /* lcdc_d18 */
2183 <3 RK 2017 <3 RK_PC5 1 &pcfg_pull_none_8ma>, /* lcdc_d17 */
2184 <3 RK 2018 <3 RK_PC4 1 &pcfg_pull_none_8ma>, /* lcdc_d16 */
2185 <3 RK 2019 <3 RK_PD3 1 &pcfg_pull_none_8ma>, /* lcdc_d23 */
2186 <3 RK 2020 <3 RK_PD2 1 &pcfg_pull_none_8ma>, /* lcdc_d22 */
2187 <3 RK 2021 <3 RK_PD1 1 &pcfg_pull_none_8ma>, /* lcdc_d21 */
2188 <3 RK 2022 <3 RK_PD0 1 &pcfg_pull_none_8ma>; /* lcdc_d20 */
2189 }; 2023 };
2190 2024
2191 lcdc_rgb666_m0_data_p 2025 lcdc_rgb666_m0_data_pins: lcdc-rgb666-m0-data-pins {
2192 rockchip,pins 2026 rockchip,pins =
2193 <3 RK 2027 <3 RK_PA7 1 &pcfg_pull_none_8ma>, /* lcdc_d3 */
2194 <3 RK 2028 <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */
2195 <3 RK 2029 <3 RK_PA5 1 &pcfg_pull_none_8ma>, /* lcdc_d1 */
2196 <3 RK 2030 <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */
2197 <3 RK 2031 <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */
2198 <3 RK 2032 <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */
2199 <3 RK 2033 <3 RK_PB1 1 &pcfg_pull_none_8ma>, /* lcdc_d5 */
2200 <3 RK 2034 <3 RK_PB0 1 &pcfg_pull_none_8ma>, /* lcdc_d4 */
2201 <3 RK 2035 <3 RK_PB7 1 &pcfg_pull_none_8ma>, /* lcdc_d11 */
2202 <3 RK 2036 <3 RK_PB6 1 &pcfg_pull_none_8ma>, /* lcdc_d10 */
2203 <3 RK 2037 <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */
2204 <3 RK 2038 <3 RK_PB4 1 &pcfg_pull_none_8ma>, /* lcdc_d8 */
2205 <3 RK 2039 <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */
2206 <3 RK 2040 <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */
2207 <3 RK 2041 <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */
2208 <3 RK 2042 <3 RK_PC0 1 &pcfg_pull_none_8ma>, /* lcdc_d12 */
2209 <3 RK 2043 <3 RK_PC5 1 &pcfg_pull_none_8ma>, /* lcdc_d17 */
2210 <3 RK 2044 <3 RK_PC4 1 &pcfg_pull_none_8ma>; /* lcdc_d16 */
2211 }; 2045 };
2212 2046
2213 lcdc_rgb565_m0_data_p 2047 lcdc_rgb565_m0_data_pins: lcdc-rgb565-m0-data-pins {
2214 rockchip,pins 2048 rockchip,pins =
2215 <3 RK 2049 <3 RK_PA7 1 &pcfg_pull_none_8ma>, /* lcdc_d3 */
2216 <3 RK 2050 <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */
2217 <3 RK 2051 <3 RK_PA5 1 &pcfg_pull_none_8ma>, /* lcdc_d1 */
2218 <3 RK 2052 <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */
2219 <3 RK 2053 <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */
2220 <3 RK 2054 <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */
2221 <3 RK 2055 <3 RK_PB1 1 &pcfg_pull_none_8ma>, /* lcdc_d5 */
2222 <3 RK 2056 <3 RK_PB0 1 &pcfg_pull_none_8ma>, /* lcdc_d4 */
2223 <3 RK 2057 <3 RK_PB7 1 &pcfg_pull_none_8ma>, /* lcdc_d11 */
2224 <3 RK 2058 <3 RK_PB6 1 &pcfg_pull_none_8ma>, /* lcdc_d10 */
2225 <3 RK 2059 <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */
2226 <3 RK 2060 <3 RK_PB4 1 &pcfg_pull_none_8ma>, /* lcdc_d8 */
2227 <3 RK 2061 <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */
2228 <3 RK 2062 <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */
2229 <3 RK 2063 <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */
2230 <3 RK 2064 <3 RK_PC0 1 &pcfg_pull_none_8ma>; /* lcdc_d12 */
2231 }; 2065 };
2232 2066
2233 lcdc_rgb888_m1_data_p 2067 lcdc_rgb888_m1_data_pins: lcdc-rgb888-m1-data-pins {
2234 rockchip,pins 2068 rockchip,pins =
2235 <3 RK 2069 <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */
2236 <3 RK 2070 <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */
2237 <3 RK 2071 <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */
2238 <3 RK 2072 <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */
2239 <3 RK 2073 <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */
2240 <3 RK 2074 <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */
2241 <3 RK 2075 <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */
2242 <3 RK 2076 <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */
2243 <3 RK 2077 <3 RK_PC0 1 &pcfg_pull_none_8ma>, /* lcdc_d12 */
2244 <3 RK 2078 <3 RK_PC7 1 &pcfg_pull_none_8ma>, /* lcdc_d19 */
2245 <3 RK 2079 <3 RK_PC6 1 &pcfg_pull_none_8ma>, /* lcdc_d18 */
2246 <3 RK 2080 <3 RK_PC5 1 &pcfg_pull_none_8ma>, /* lcdc_d17 */
2247 <3 RK 2081 <3 RK_PC4 1 &pcfg_pull_none_8ma>, /* lcdc_d16 */
2248 <3 RK 2082 <3 RK_PD3 1 &pcfg_pull_none_8ma>, /* lcdc_d23 */
2249 <3 RK 2083 <3 RK_PD2 1 &pcfg_pull_none_8ma>, /* lcdc_d22 */
2250 <3 RK 2084 <3 RK_PD1 1 &pcfg_pull_none_8ma>, /* lcdc_d21 */
2251 <3 RK 2085 <3 RK_PD0 1 &pcfg_pull_none_8ma>; /* lcdc_d20 */
2252 }; 2086 };
2253 2087
2254 lcdc_rgb666_m1_data_p 2088 lcdc_rgb666_m1_data_pins: lcdc-rgb666-m1-data-pins {
2255 rockchip,pins 2089 rockchip,pins =
2256 <3 RK 2090 <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */
2257 <3 RK 2091 <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */
2258 <3 RK 2092 <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */
2259 <3 RK 2093 <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */
2260 <3 RK 2094 <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */
2261 <3 RK 2095 <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */
2262 <3 RK 2096 <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */
2263 <3 RK 2097 <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */
2264 <3 RK 2098 <3 RK_PC0 1 &pcfg_pull_none_8ma>, /* lcdc_d12 */
2265 <3 RK 2099 <3 RK_PC5 1 &pcfg_pull_none_8ma>, /* lcdc_d17 */
2266 <3 RK 2100 <3 RK_PC4 1 &pcfg_pull_none_8ma>; /* lcdc_d16 */
2267 }; 2101 };
2268 2102
2269 lcdc_rgb565_m1_data_p 2103 lcdc_rgb565_m1_data_pins: lcdc-rgb565-m1-data-pins {
2270 rockchip,pins 2104 rockchip,pins =
2271 <3 RK 2105 <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */
2272 <3 RK 2106 <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */
2273 <3 RK 2107 <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */
2274 <3 RK 2108 <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */
2275 <3 RK 2109 <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */
2276 <3 RK 2110 <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */
2277 <3 RK 2111 <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */
2278 <3 RK 2112 <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */
2279 <3 RK 2113 <3 RK_PC0 1 &pcfg_pull_none_8ma>; /* lcdc_d12 */
2280 }; 2114 };
2281 }; 2115 };
2282 2116
2283 pwm0 { 2117 pwm0 {
2284 pwm0_pin: pwm0-pin { 2118 pwm0_pin: pwm0-pin {
2285 rockchip,pins 2119 rockchip,pins =
2286 <0 RK 2120 <0 RK_PB7 1 &pcfg_pull_none>;
2287 }; 2121 };
2288 }; 2122 };
2289 2123
2290 pwm1 { 2124 pwm1 {
2291 pwm1_pin: pwm1-pin { 2125 pwm1_pin: pwm1-pin {
2292 rockchip,pins 2126 rockchip,pins =
2293 <0 RK 2127 <0 RK_PC0 1 &pcfg_pull_none>;
2294 }; 2128 };
2295 }; 2129 };
2296 2130
2297 pwm2 { 2131 pwm2 {
2298 pwm2_pin: pwm2-pin { 2132 pwm2_pin: pwm2-pin {
2299 rockchip,pins 2133 rockchip,pins =
2300 <2 RK 2134 <2 RK_PB5 1 &pcfg_pull_none>;
2301 }; 2135 };
2302 }; 2136 };
2303 2137
2304 pwm3 { 2138 pwm3 {
2305 pwm3_pin: pwm3-pin { 2139 pwm3_pin: pwm3-pin {
2306 rockchip,pins 2140 rockchip,pins =
2307 <0 RK 2141 <0 RK_PC1 1 &pcfg_pull_none>;
2308 }; 2142 };
2309 }; 2143 };
2310 2144
2311 pwm4 { 2145 pwm4 {
2312 pwm4_pin: pwm4-pin { 2146 pwm4_pin: pwm4-pin {
2313 rockchip,pins 2147 rockchip,pins =
2314 <3 RK 2148 <3 RK_PC2 3 &pcfg_pull_none>;
2315 }; 2149 };
2316 }; 2150 };
2317 2151
2318 pwm5 { 2152 pwm5 {
2319 pwm5_pin: pwm5-pin { 2153 pwm5_pin: pwm5-pin {
2320 rockchip,pins 2154 rockchip,pins =
2321 <3 RK 2155 <3 RK_PC3 3 &pcfg_pull_none>;
2322 }; 2156 };
2323 }; 2157 };
2324 2158
2325 pwm6 { 2159 pwm6 {
2326 pwm6_pin: pwm6-pin { 2160 pwm6_pin: pwm6-pin {
2327 rockchip,pins 2161 rockchip,pins =
2328 <3 RK 2162 <3 RK_PC4 3 &pcfg_pull_none>;
2329 }; 2163 };
2330 }; 2164 };
2331 2165
2332 pwm7 { 2166 pwm7 {
2333 pwm7_pin: pwm7-pin { 2167 pwm7_pin: pwm7-pin {
2334 rockchip,pins 2168 rockchip,pins =
2335 <3 RK 2169 <3 RK_PC5 3 &pcfg_pull_none>;
2336 }; 2170 };
2337 }; 2171 };
2338 2172
2339 gmac { 2173 gmac {
2340 rmii_pins: rmii-pins 2174 rmii_pins: rmii-pins {
2341 rockchip,pins 2175 rockchip,pins =
2342 <2 RK 2176 <2 RK_PA0 2 &pcfg_pull_none_12ma>, /* mac_txen */
2343 <2 RK 2177 <2 RK_PA1 2 &pcfg_pull_none_12ma>, /* mac_txd1 */
2344 <2 RK 2178 <2 RK_PA2 2 &pcfg_pull_none_12ma>, /* mac_txd0 */
2345 <2 RK 2179 <2 RK_PA3 2 &pcfg_pull_none>, /* mac_rxd0 */
2346 <2 RK 2180 <2 RK_PA4 2 &pcfg_pull_none>, /* mac_rxd1 */
2347 <2 RK 2181 <2 RK_PA5 2 &pcfg_pull_none>, /* mac_rxer */
2348 <2 RK 2182 <2 RK_PA6 2 &pcfg_pull_none>, /* mac_rxdv */
2349 <2 RK 2183 <2 RK_PA7 2 &pcfg_pull_none>, /* mac_mdio */
2350 <2 RK 2184 <2 RK_PB1 2 &pcfg_pull_none>; /* mac_mdc */
2351 }; 2185 };
2352 2186
2353 mac_refclk_12ma: mac- 2187 mac_refclk_12ma: mac-refclk-12ma {
2354 rockchip,pins 2188 rockchip,pins =
2355 <2 RK 2189 <2 RK_PB2 2 &pcfg_pull_none_12ma>;
2356 }; 2190 };
2357 2191
2358 mac_refclk: mac-refcl 2192 mac_refclk: mac-refclk {
2359 rockchip,pins 2193 rockchip,pins =
2360 <2 RK 2194 <2 RK_PB2 2 &pcfg_pull_none>;
2361 }; 2195 };
2362 }; 2196 };
2363 2197
2364 cif-m0 { 2198 cif-m0 {
2365 cif_clkout_m0: cif-cl 2199 cif_clkout_m0: cif-clkout-m0 {
2366 rockchip,pins 2200 rockchip,pins =
2367 <2 RK 2201 <2 RK_PB3 1 &pcfg_pull_none>;
2368 }; 2202 };
2369 2203
2370 dvp_d2d9_m0: dvp-d2d9 2204 dvp_d2d9_m0: dvp-d2d9-m0 {
2371 rockchip,pins 2205 rockchip,pins =
2372 <2 RK 2206 <2 RK_PA0 1 &pcfg_pull_none>, /* cif_data2 */
2373 <2 RK 2207 <2 RK_PA1 1 &pcfg_pull_none>, /* cif_data3 */
2374 <2 RK 2208 <2 RK_PA2 1 &pcfg_pull_none>, /* cif_data4 */
2375 <2 RK 2209 <2 RK_PA3 1 &pcfg_pull_none>, /* cif_data5 */
2376 <2 RK 2210 <2 RK_PA4 1 &pcfg_pull_none>, /* cif_data6 */
2377 <2 RK 2211 <2 RK_PA5 1 &pcfg_pull_none>, /* cif_data7 */
2378 <2 RK 2212 <2 RK_PA6 1 &pcfg_pull_none>, /* cif_data8 */
2379 <2 RK 2213 <2 RK_PA7 1 &pcfg_pull_none>, /* cif_data9 */
2380 <2 RK 2214 <2 RK_PB0 1 &pcfg_pull_none>, /* cif_sync */
2381 <2 RK 2215 <2 RK_PB1 1 &pcfg_pull_none>, /* cif_href */
2382 <2 RK 2216 <2 RK_PB2 1 &pcfg_pull_none>, /* cif_clkin */
2383 <2 RK 2217 <2 RK_PB3 1 &pcfg_pull_none>; /* cif_clkout */
2384 }; 2218 };
2385 2219
2386 dvp_d0d1_m0: dvp-d0d1 2220 dvp_d0d1_m0: dvp-d0d1-m0 {
2387 rockchip,pins 2221 rockchip,pins =
2388 <2 RK 2222 <2 RK_PB4 1 &pcfg_pull_none>, /* cif_data0 */
2389 <2 RK 2223 <2 RK_PB6 1 &pcfg_pull_none>; /* cif_data1 */
2390 }; 2224 };
2391 2225
2392 dvp_d10d11_m0:d10-d11 2226 dvp_d10d11_m0:d10-d11-m0 {
2393 rockchip,pins 2227 rockchip,pins =
2394 <2 RK 2228 <2 RK_PB7 1 &pcfg_pull_none>, /* cif_data10 */
2395 <2 RK 2229 <2 RK_PC0 1 &pcfg_pull_none>; /* cif_data11 */
2396 }; 2230 };
2397 }; 2231 };
2398 2232
2399 cif-m1 { 2233 cif-m1 {
2400 cif_clkout_m1: cif-cl 2234 cif_clkout_m1: cif-clkout-m1 {
2401 rockchip,pins 2235 rockchip,pins =
2402 <3 RK 2236 <3 RK_PD0 3 &pcfg_pull_none>;
2403 }; 2237 };
2404 2238
2405 dvp_d2d9_m1: dvp-d2d9 2239 dvp_d2d9_m1: dvp-d2d9-m1 {
2406 rockchip,pins 2240 rockchip,pins =
2407 <3 RK 2241 <3 RK_PA3 3 &pcfg_pull_none>, /* cif_data2 */
2408 <3 RK 2242 <3 RK_PA5 3 &pcfg_pull_none>, /* cif_data3 */
2409 <3 RK 2243 <3 RK_PA7 3 &pcfg_pull_none>, /* cif_data4 */
2410 <3 RK 2244 <3 RK_PB0 3 &pcfg_pull_none>, /* cif_data5 */
2411 <3 RK 2245 <3 RK_PB1 3 &pcfg_pull_none>, /* cif_data6 */
2412 <3 RK 2246 <3 RK_PB4 3 &pcfg_pull_none>, /* cif_data7 */
2413 <3 RK 2247 <3 RK_PB6 3 &pcfg_pull_none>, /* cif_data8 */
2414 <3 RK 2248 <3 RK_PB7 3 &pcfg_pull_none>, /* cif_data9 */
2415 <3 RK 2249 <3 RK_PD1 3 &pcfg_pull_none>, /* cif_sync */
2416 <3 RK 2250 <3 RK_PD2 3 &pcfg_pull_none>, /* cif_href */
2417 <3 RK 2251 <3 RK_PD3 3 &pcfg_pull_none>, /* cif_clkin */
2418 <3 RK 2252 <3 RK_PD0 3 &pcfg_pull_none>; /* cif_clkout */
2419 }; 2253 };
2420 2254
2421 dvp_d0d1_m1: dvp-d0d1 2255 dvp_d0d1_m1: dvp-d0d1-m1 {
2422 rockchip,pins 2256 rockchip,pins =
2423 <3 RK 2257 <3 RK_PA1 3 &pcfg_pull_none>, /* cif_data0 */
2424 <3 RK 2258 <3 RK_PA2 3 &pcfg_pull_none>; /* cif_data1 */
2425 }; 2259 };
2426 2260
2427 dvp_d10d11_m1:d10-d11 2261 dvp_d10d11_m1:d10-d11-m1 {
2428 rockchip,pins 2262 rockchip,pins =
2429 <3 RK 2263 <3 RK_PC6 3 &pcfg_pull_none>, /* cif_data10 */
2430 <3 RK 2264 <3 RK_PC7 3 &pcfg_pull_none>; /* cif_data11 */
2431 }; 2265 };
2432 }; 2266 };
2433 2267
2434 isp { 2268 isp {
2435 isp_prelight: isp-pre 2269 isp_prelight: isp-prelight {
2436 rockchip,pins 2270 rockchip,pins =
2437 <3 RK 2271 <3 RK_PD1 4 &pcfg_pull_none>;
2438 }; 2272 };
2439 }; 2273 };
2440 }; 2274 };
2441 }; 2275 };
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