1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /* 2 /*
3 * Copyright (c) 2018 Fuzhou Rockchip Electron 3 * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd
4 */ 4 */
5 5
6 #include <dt-bindings/clock/px30-cru.h> 6 #include <dt-bindings/clock/px30-cru.h>
7 #include <dt-bindings/gpio/gpio.h> 7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/interrupt-controller/arm 8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/interrupt-controller/irq 9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/pinctrl/rockchip.h> 10 #include <dt-bindings/pinctrl/rockchip.h>
11 #include <dt-bindings/power/px30-power.h> 11 #include <dt-bindings/power/px30-power.h>
12 #include <dt-bindings/soc/rockchip,boot-mode.h 12 #include <dt-bindings/soc/rockchip,boot-mode.h>
13 #include <dt-bindings/thermal/thermal.h> 13 #include <dt-bindings/thermal/thermal.h>
14 14
15 / { 15 / {
16 compatible = "rockchip,px30"; 16 compatible = "rockchip,px30";
17 17
18 interrupt-parent = <&gic>; 18 interrupt-parent = <&gic>;
19 #address-cells = <2>; 19 #address-cells = <2>;
20 #size-cells = <2>; 20 #size-cells = <2>;
21 21
22 aliases { 22 aliases {
>> 23 ethernet0 = &gmac;
23 i2c0 = &i2c0; 24 i2c0 = &i2c0;
24 i2c1 = &i2c1; 25 i2c1 = &i2c1;
25 i2c2 = &i2c2; 26 i2c2 = &i2c2;
26 i2c3 = &i2c3; 27 i2c3 = &i2c3;
27 serial0 = &uart0; 28 serial0 = &uart0;
28 serial1 = &uart1; 29 serial1 = &uart1;
29 serial2 = &uart2; 30 serial2 = &uart2;
30 serial3 = &uart3; 31 serial3 = &uart3;
31 serial4 = &uart4; 32 serial4 = &uart4;
32 serial5 = &uart5; 33 serial5 = &uart5;
33 spi0 = &spi0; 34 spi0 = &spi0;
34 spi1 = &spi1; 35 spi1 = &spi1;
35 }; 36 };
36 37
37 cpus { 38 cpus {
38 #address-cells = <2>; 39 #address-cells = <2>;
39 #size-cells = <0>; 40 #size-cells = <0>;
40 41
41 cpu0: cpu@0 { 42 cpu0: cpu@0 {
42 device_type = "cpu"; 43 device_type = "cpu";
43 compatible = "arm,cort 44 compatible = "arm,cortex-a35";
44 reg = <0x0 0x0>; 45 reg = <0x0 0x0>;
45 enable-method = "psci" 46 enable-method = "psci";
46 clocks = <&cru ARMCLK> 47 clocks = <&cru ARMCLK>;
47 #cooling-cells = <2>; 48 #cooling-cells = <2>;
48 cpu-idle-states = <&CP 49 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
49 dynamic-power-coeffici 50 dynamic-power-coefficient = <90>;
50 operating-points-v2 = 51 operating-points-v2 = <&cpu0_opp_table>;
51 }; 52 };
52 53
53 cpu1: cpu@1 { 54 cpu1: cpu@1 {
54 device_type = "cpu"; 55 device_type = "cpu";
55 compatible = "arm,cort 56 compatible = "arm,cortex-a35";
56 reg = <0x0 0x1>; 57 reg = <0x0 0x1>;
57 enable-method = "psci" 58 enable-method = "psci";
58 clocks = <&cru ARMCLK> 59 clocks = <&cru ARMCLK>;
59 #cooling-cells = <2>; 60 #cooling-cells = <2>;
60 cpu-idle-states = <&CP 61 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
61 dynamic-power-coeffici 62 dynamic-power-coefficient = <90>;
62 operating-points-v2 = 63 operating-points-v2 = <&cpu0_opp_table>;
63 }; 64 };
64 65
65 cpu2: cpu@2 { 66 cpu2: cpu@2 {
66 device_type = "cpu"; 67 device_type = "cpu";
67 compatible = "arm,cort 68 compatible = "arm,cortex-a35";
68 reg = <0x0 0x2>; 69 reg = <0x0 0x2>;
69 enable-method = "psci" 70 enable-method = "psci";
70 clocks = <&cru ARMCLK> 71 clocks = <&cru ARMCLK>;
71 #cooling-cells = <2>; 72 #cooling-cells = <2>;
72 cpu-idle-states = <&CP 73 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
73 dynamic-power-coeffici 74 dynamic-power-coefficient = <90>;
74 operating-points-v2 = 75 operating-points-v2 = <&cpu0_opp_table>;
75 }; 76 };
76 77
77 cpu3: cpu@3 { 78 cpu3: cpu@3 {
78 device_type = "cpu"; 79 device_type = "cpu";
79 compatible = "arm,cort 80 compatible = "arm,cortex-a35";
80 reg = <0x0 0x3>; 81 reg = <0x0 0x3>;
81 enable-method = "psci" 82 enable-method = "psci";
82 clocks = <&cru ARMCLK> 83 clocks = <&cru ARMCLK>;
83 #cooling-cells = <2>; 84 #cooling-cells = <2>;
84 cpu-idle-states = <&CP 85 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
85 dynamic-power-coeffici 86 dynamic-power-coefficient = <90>;
86 operating-points-v2 = 87 operating-points-v2 = <&cpu0_opp_table>;
87 }; 88 };
88 89
89 idle-states { 90 idle-states {
90 entry-method = "psci"; 91 entry-method = "psci";
91 92
92 CPU_SLEEP: cpu-sleep { 93 CPU_SLEEP: cpu-sleep {
93 compatible = " 94 compatible = "arm,idle-state";
94 local-timer-st 95 local-timer-stop;
95 arm,psci-suspe 96 arm,psci-suspend-param = <0x0010000>;
96 entry-latency- 97 entry-latency-us = <120>;
97 exit-latency-u 98 exit-latency-us = <250>;
98 min-residency- 99 min-residency-us = <900>;
99 }; 100 };
100 101
101 CLUSTER_SLEEP: cluster 102 CLUSTER_SLEEP: cluster-sleep {
102 compatible = " 103 compatible = "arm,idle-state";
103 local-timer-st 104 local-timer-stop;
104 arm,psci-suspe 105 arm,psci-suspend-param = <0x1010000>;
105 entry-latency- 106 entry-latency-us = <400>;
106 exit-latency-u 107 exit-latency-us = <500>;
107 min-residency- 108 min-residency-us = <2000>;
108 }; 109 };
109 }; 110 };
110 }; 111 };
111 112
112 cpu0_opp_table: opp-table-0 { 113 cpu0_opp_table: opp-table-0 {
113 compatible = "operating-points 114 compatible = "operating-points-v2";
114 opp-shared; 115 opp-shared;
115 116
116 opp-600000000 { 117 opp-600000000 {
117 opp-hz = /bits/ 64 <60 118 opp-hz = /bits/ 64 <600000000>;
118 opp-microvolt = <95000 119 opp-microvolt = <950000 950000 1350000>;
119 clock-latency-ns = <40 120 clock-latency-ns = <40000>;
120 opp-suspend; 121 opp-suspend;
121 }; 122 };
122 opp-816000000 { 123 opp-816000000 {
123 opp-hz = /bits/ 64 <81 124 opp-hz = /bits/ 64 <816000000>;
124 opp-microvolt = <10500 125 opp-microvolt = <1050000 1050000 1350000>;
125 clock-latency-ns = <40 126 clock-latency-ns = <40000>;
126 }; 127 };
127 opp-1008000000 { 128 opp-1008000000 {
128 opp-hz = /bits/ 64 <10 129 opp-hz = /bits/ 64 <1008000000>;
129 opp-microvolt = <11750 130 opp-microvolt = <1175000 1175000 1350000>;
130 clock-latency-ns = <40 131 clock-latency-ns = <40000>;
131 }; 132 };
132 opp-1200000000 { 133 opp-1200000000 {
133 opp-hz = /bits/ 64 <12 134 opp-hz = /bits/ 64 <1200000000>;
134 opp-microvolt = <13000 135 opp-microvolt = <1300000 1300000 1350000>;
135 clock-latency-ns = <40 136 clock-latency-ns = <40000>;
136 }; 137 };
137 opp-1296000000 { 138 opp-1296000000 {
138 opp-hz = /bits/ 64 <12 139 opp-hz = /bits/ 64 <1296000000>;
139 opp-microvolt = <13500 140 opp-microvolt = <1350000 1350000 1350000>;
140 clock-latency-ns = <40 141 clock-latency-ns = <40000>;
141 }; 142 };
142 }; 143 };
143 144
144 arm-pmu { 145 arm-pmu {
145 compatible = "arm,cortex-a35-p 146 compatible = "arm,cortex-a35-pmu";
146 interrupts = <GIC_SPI 100 IRQ_ 147 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
147 <GIC_SPI 101 IRQ_ 148 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
148 <GIC_SPI 102 IRQ_ 149 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
149 <GIC_SPI 103 IRQ_ 150 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
150 interrupt-affinity = <&cpu0>, 151 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
151 }; 152 };
152 153
153 display_subsystem: display-subsystem { 154 display_subsystem: display-subsystem {
154 compatible = "rockchip,display 155 compatible = "rockchip,display-subsystem";
155 ports = <&vopb_out>, <&vopl_ou 156 ports = <&vopb_out>, <&vopl_out>;
156 status = "disabled"; 157 status = "disabled";
157 }; 158 };
158 159
159 gmac_clkin: external-gmac-clock { 160 gmac_clkin: external-gmac-clock {
160 compatible = "fixed-clock"; 161 compatible = "fixed-clock";
161 clock-frequency = <50000000>; 162 clock-frequency = <50000000>;
162 clock-output-names = "gmac_clk 163 clock-output-names = "gmac_clkin";
163 #clock-cells = <0>; 164 #clock-cells = <0>;
164 }; 165 };
165 166
166 psci { 167 psci {
167 compatible = "arm,psci-1.0"; 168 compatible = "arm,psci-1.0";
168 method = "smc"; 169 method = "smc";
169 }; 170 };
170 171
171 timer { 172 timer {
172 compatible = "arm,armv8-timer" 173 compatible = "arm,armv8-timer";
173 interrupts = <GIC_PPI 13 (GIC_ 174 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
174 <GIC_PPI 14 (GIC_ 175 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
175 <GIC_PPI 11 (GIC_ 176 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
176 <GIC_PPI 10 (GIC_ 177 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
177 }; 178 };
178 179
179 thermal_zones: thermal-zones { 180 thermal_zones: thermal-zones {
180 soc_thermal: soc-thermal { 181 soc_thermal: soc-thermal {
181 polling-delay-passive 182 polling-delay-passive = <20>;
182 polling-delay = <1000> 183 polling-delay = <1000>;
183 sustainable-power = <7 184 sustainable-power = <750>;
184 thermal-sensors = <&ts 185 thermal-sensors = <&tsadc 0>;
185 186
186 trips { 187 trips {
187 threshold: tri 188 threshold: trip-point-0 {
188 temper 189 temperature = <70000>;
189 hyster 190 hysteresis = <2000>;
190 type = 191 type = "passive";
191 }; 192 };
192 193
193 target: trip-p 194 target: trip-point-1 {
194 temper 195 temperature = <85000>;
195 hyster 196 hysteresis = <2000>;
196 type = 197 type = "passive";
197 }; 198 };
198 199
199 soc_crit: soc- 200 soc_crit: soc-crit {
200 temper 201 temperature = <115000>;
201 hyster 202 hysteresis = <2000>;
202 type = 203 type = "critical";
203 }; 204 };
204 }; 205 };
205 206
206 cooling-maps { 207 cooling-maps {
207 map0 { 208 map0 {
208 trip = 209 trip = <&target>;
209 coolin 210 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
210 contri 211 contribution = <4096>;
211 }; 212 };
>> 213
>> 214 map1 {
>> 215 trip = <&target>;
>> 216 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
>> 217 contribution = <4096>;
>> 218 };
212 }; 219 };
213 }; 220 };
214 221
215 gpu_thermal: gpu-thermal { 222 gpu_thermal: gpu-thermal {
216 polling-delay-passive 223 polling-delay-passive = <100>; /* milliseconds */
217 polling-delay = <1000> 224 polling-delay = <1000>; /* milliseconds */
218 thermal-sensors = <&ts 225 thermal-sensors = <&tsadc 1>;
219 <<
220 trips { <<
221 gpu_threshold: <<
222 temper <<
223 hyster <<
224 type = <<
225 }; <<
226 <<
227 gpu_target: gp <<
228 temper <<
229 hyster <<
230 type = <<
231 }; <<
232 <<
233 gpu_crit: gpu- <<
234 temper <<
235 hyster <<
236 type = <<
237 }; <<
238 }; <<
239 <<
240 cooling-maps { <<
241 map0 { <<
242 trip = <<
243 coolin <<
244 }; <<
245 }; <<
246 }; 226 };
247 }; 227 };
248 228
249 xin24m: xin24m { 229 xin24m: xin24m {
250 compatible = "fixed-clock"; 230 compatible = "fixed-clock";
251 #clock-cells = <0>; 231 #clock-cells = <0>;
252 clock-frequency = <24000000>; 232 clock-frequency = <24000000>;
253 clock-output-names = "xin24m"; 233 clock-output-names = "xin24m";
254 }; 234 };
255 235
256 pmu: power-management@ff000000 { 236 pmu: power-management@ff000000 {
257 compatible = "rockchip,px30-pm 237 compatible = "rockchip,px30-pmu", "syscon", "simple-mfd";
258 reg = <0x0 0xff000000 0x0 0x10 238 reg = <0x0 0xff000000 0x0 0x1000>;
259 239
260 power: power-controller { 240 power: power-controller {
261 compatible = "rockchip 241 compatible = "rockchip,px30-power-controller";
262 #power-domain-cells = 242 #power-domain-cells = <1>;
263 #address-cells = <1>; 243 #address-cells = <1>;
264 #size-cells = <0>; 244 #size-cells = <0>;
265 245
266 /* These power domains 246 /* These power domains are grouped by VD_LOGIC */
267 power-domain@PX30_PD_U 247 power-domain@PX30_PD_USB {
268 reg = <PX30_PD 248 reg = <PX30_PD_USB>;
269 clocks = <&cru 249 clocks = <&cru HCLK_HOST>,
270 <&cru 250 <&cru HCLK_OTG>,
271 <&cru 251 <&cru SCLK_OTG_ADP>;
272 pm_qos = <&qos 252 pm_qos = <&qos_usb_host>, <&qos_usb_otg>;
273 #power-domain- 253 #power-domain-cells = <0>;
274 }; 254 };
275 power-domain@PX30_PD_S 255 power-domain@PX30_PD_SDCARD {
276 reg = <PX30_PD 256 reg = <PX30_PD_SDCARD>;
277 clocks = <&cru 257 clocks = <&cru HCLK_SDMMC>,
278 <&cru 258 <&cru SCLK_SDMMC>;
279 pm_qos = <&qos 259 pm_qos = <&qos_sdmmc>;
280 #power-domain- 260 #power-domain-cells = <0>;
281 }; 261 };
282 power-domain@PX30_PD_G 262 power-domain@PX30_PD_GMAC {
283 reg = <PX30_PD 263 reg = <PX30_PD_GMAC>;
284 clocks = <&cru 264 clocks = <&cru ACLK_GMAC>,
285 <&cru 265 <&cru PCLK_GMAC>,
286 <&cru 266 <&cru SCLK_MAC_REF>,
287 <&cru 267 <&cru SCLK_GMAC_RX_TX>;
288 pm_qos = <&qos 268 pm_qos = <&qos_gmac>;
289 #power-domain- 269 #power-domain-cells = <0>;
290 }; 270 };
291 power-domain@PX30_PD_M 271 power-domain@PX30_PD_MMC_NAND {
292 reg = <PX30_PD 272 reg = <PX30_PD_MMC_NAND>;
293 clocks = <&cru !! 273 clocks = <&cru HCLK_NANDC>,
294 <&cru !! 274 <&cru HCLK_EMMC>,
295 <&cru !! 275 <&cru HCLK_SDIO>,
296 <&cru !! 276 <&cru HCLK_SFC>,
297 <&cru !! 277 <&cru SCLK_EMMC>,
298 <&cru !! 278 <&cru SCLK_NANDC>,
299 <&cru !! 279 <&cru SCLK_SDIO>,
300 <&cru !! 280 <&cru SCLK_SFC>;
301 pm_qos = <&qos 281 pm_qos = <&qos_emmc>, <&qos_nand>,
302 <&qos 282 <&qos_sdio>, <&qos_sfc>;
303 #power-domain- 283 #power-domain-cells = <0>;
304 }; 284 };
305 power-domain@PX30_PD_V 285 power-domain@PX30_PD_VPU {
306 reg = <PX30_PD 286 reg = <PX30_PD_VPU>;
307 clocks = <&cru 287 clocks = <&cru ACLK_VPU>,
308 <&cru 288 <&cru HCLK_VPU>,
309 <&cru 289 <&cru SCLK_CORE_VPU>;
310 pm_qos = <&qos 290 pm_qos = <&qos_vpu>, <&qos_vpu_r128>;
311 #power-domain- 291 #power-domain-cells = <0>;
312 }; 292 };
313 power-domain@PX30_PD_V 293 power-domain@PX30_PD_VO {
314 reg = <PX30_PD 294 reg = <PX30_PD_VO>;
315 clocks = <&cru 295 clocks = <&cru ACLK_RGA>,
316 <&cru 296 <&cru ACLK_VOPB>,
317 <&cru 297 <&cru ACLK_VOPL>,
318 <&cru 298 <&cru DCLK_VOPB>,
319 <&cru 299 <&cru DCLK_VOPL>,
320 <&cru 300 <&cru HCLK_RGA>,
321 <&cru 301 <&cru HCLK_VOPB>,
322 <&cru 302 <&cru HCLK_VOPL>,
323 <&cru 303 <&cru PCLK_MIPI_DSI>,
324 <&cru 304 <&cru SCLK_RGA_CORE>,
325 <&cru 305 <&cru SCLK_VOPB_PWM>;
326 pm_qos = <&qos 306 pm_qos = <&qos_rga_rd>, <&qos_rga_wr>,
327 <&qos 307 <&qos_vop_m0>, <&qos_vop_m1>;
328 #power-domain- 308 #power-domain-cells = <0>;
329 }; 309 };
330 power-domain@PX30_PD_V 310 power-domain@PX30_PD_VI {
331 reg = <PX30_PD 311 reg = <PX30_PD_VI>;
332 clocks = <&cru 312 clocks = <&cru ACLK_CIF>,
333 <&cru 313 <&cru ACLK_ISP>,
334 <&cru 314 <&cru HCLK_CIF>,
335 <&cru 315 <&cru HCLK_ISP>,
336 <&cru 316 <&cru SCLK_ISP>;
337 pm_qos = <&qos 317 pm_qos = <&qos_isp_128>, <&qos_isp_rd>,
338 <&qos 318 <&qos_isp_wr>, <&qos_isp_m1>,
339 <&qos 319 <&qos_vip>;
340 #power-domain- 320 #power-domain-cells = <0>;
341 }; 321 };
342 power-domain@PX30_PD_G 322 power-domain@PX30_PD_GPU {
343 reg = <PX30_PD 323 reg = <PX30_PD_GPU>;
344 clocks = <&cru 324 clocks = <&cru SCLK_GPU>;
345 pm_qos = <&qos 325 pm_qos = <&qos_gpu>;
346 #power-domain- 326 #power-domain-cells = <0>;
347 }; 327 };
348 }; 328 };
349 }; 329 };
350 330
351 pmugrf: syscon@ff010000 { 331 pmugrf: syscon@ff010000 {
352 compatible = "rockchip,px30-pm 332 compatible = "rockchip,px30-pmugrf", "syscon", "simple-mfd";
353 reg = <0x0 0xff010000 0x0 0x10 333 reg = <0x0 0xff010000 0x0 0x1000>;
354 #address-cells = <1>; 334 #address-cells = <1>;
355 #size-cells = <1>; 335 #size-cells = <1>;
356 336
357 pmu_io_domains: io-domains { 337 pmu_io_domains: io-domains {
358 compatible = "rockchip 338 compatible = "rockchip,px30-pmu-io-voltage-domain";
359 status = "disabled"; 339 status = "disabled";
360 }; 340 };
361 341
362 reboot-mode { 342 reboot-mode {
363 compatible = "syscon-r 343 compatible = "syscon-reboot-mode";
364 offset = <0x200>; 344 offset = <0x200>;
365 mode-bootloader = <BOO 345 mode-bootloader = <BOOT_BL_DOWNLOAD>;
366 mode-fastboot = <BOOT_ 346 mode-fastboot = <BOOT_FASTBOOT>;
367 mode-loader = <BOOT_BL 347 mode-loader = <BOOT_BL_DOWNLOAD>;
368 mode-normal = <BOOT_NO 348 mode-normal = <BOOT_NORMAL>;
369 mode-recovery = <BOOT_ 349 mode-recovery = <BOOT_RECOVERY>;
370 }; 350 };
371 }; 351 };
372 352
373 uart0: serial@ff030000 { 353 uart0: serial@ff030000 {
374 compatible = "rockchip,px30-ua 354 compatible = "rockchip,px30-uart", "snps,dw-apb-uart";
375 reg = <0x0 0xff030000 0x0 0x10 355 reg = <0x0 0xff030000 0x0 0x100>;
376 interrupts = <GIC_SPI 15 IRQ_T 356 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
377 clocks = <&pmucru SCLK_UART0_P 357 clocks = <&pmucru SCLK_UART0_PMU>, <&pmucru PCLK_UART0_PMU>;
378 clock-names = "baudclk", "apb_ 358 clock-names = "baudclk", "apb_pclk";
379 dmas = <&dmac 0>, <&dmac 1>; 359 dmas = <&dmac 0>, <&dmac 1>;
380 dma-names = "tx", "rx"; 360 dma-names = "tx", "rx";
381 reg-shift = <2>; 361 reg-shift = <2>;
382 reg-io-width = <4>; 362 reg-io-width = <4>;
383 pinctrl-names = "default"; 363 pinctrl-names = "default";
384 pinctrl-0 = <&uart0_xfer &uart 364 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
385 status = "disabled"; 365 status = "disabled";
386 }; 366 };
387 367
388 i2s0_8ch: i2s@ff060000 { <<
389 compatible = "rockchip,px30-i2 <<
390 reg = <0x0 0xff060000 0x0 0x10 <<
391 interrupts = <GIC_SPI 12 IRQ_T <<
392 clocks = <&cru SCLK_I2S0_TX>, <<
393 clock-names = "mclk_tx", "mclk <<
394 dmas = <&dmac 16>, <&dmac 17>; <<
395 dma-names = "tx", "rx"; <<
396 rockchip,grf = <&grf>; <<
397 resets = <&cru SRST_I2S0_TX>, <<
398 reset-names = "tx-m", "rx-m"; <<
399 pinctrl-names = "default"; <<
400 pinctrl-0 = <&i2s0_8ch_sclktx <<
401 &i2s0_8ch_lrcktx <<
402 &i2s0_8ch_sdo0 &i <<
403 &i2s0_8ch_sdo1 &i <<
404 &i2s0_8ch_sdo2 &i <<
405 &i2s0_8ch_sdo3 &i <<
406 #sound-dai-cells = <0>; <<
407 status = "disabled"; <<
408 }; <<
409 <<
410 i2s1_2ch: i2s@ff070000 { 368 i2s1_2ch: i2s@ff070000 {
411 compatible = "rockchip,px30-i2 369 compatible = "rockchip,px30-i2s", "rockchip,rk3066-i2s";
412 reg = <0x0 0xff070000 0x0 0x10 370 reg = <0x0 0xff070000 0x0 0x1000>;
413 interrupts = <GIC_SPI 13 IRQ_T 371 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
414 clocks = <&cru SCLK_I2S1>, <&c 372 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1>;
415 clock-names = "i2s_clk", "i2s_ 373 clock-names = "i2s_clk", "i2s_hclk";
416 dmas = <&dmac 18>, <&dmac 19>; 374 dmas = <&dmac 18>, <&dmac 19>;
417 dma-names = "tx", "rx"; 375 dma-names = "tx", "rx";
418 pinctrl-names = "default"; 376 pinctrl-names = "default";
419 pinctrl-0 = <&i2s1_2ch_sclk &i 377 pinctrl-0 = <&i2s1_2ch_sclk &i2s1_2ch_lrck
420 &i2s1_2ch_sdi &i2 378 &i2s1_2ch_sdi &i2s1_2ch_sdo>;
421 #sound-dai-cells = <0>; 379 #sound-dai-cells = <0>;
422 status = "disabled"; 380 status = "disabled";
423 }; 381 };
424 382
425 i2s2_2ch: i2s@ff080000 { 383 i2s2_2ch: i2s@ff080000 {
426 compatible = "rockchip,px30-i2 384 compatible = "rockchip,px30-i2s", "rockchip,rk3066-i2s";
427 reg = <0x0 0xff080000 0x0 0x10 385 reg = <0x0 0xff080000 0x0 0x1000>;
428 interrupts = <GIC_SPI 14 IRQ_T 386 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
429 clocks = <&cru SCLK_I2S2>, <&c 387 clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2>;
430 clock-names = "i2s_clk", "i2s_ 388 clock-names = "i2s_clk", "i2s_hclk";
431 dmas = <&dmac 20>, <&dmac 21>; 389 dmas = <&dmac 20>, <&dmac 21>;
432 dma-names = "tx", "rx"; 390 dma-names = "tx", "rx";
433 pinctrl-names = "default"; 391 pinctrl-names = "default";
434 pinctrl-0 = <&i2s2_2ch_sclk &i 392 pinctrl-0 = <&i2s2_2ch_sclk &i2s2_2ch_lrck
435 &i2s2_2ch_sdi &i2 393 &i2s2_2ch_sdi &i2s2_2ch_sdo>;
436 #sound-dai-cells = <0>; 394 #sound-dai-cells = <0>;
437 status = "disabled"; 395 status = "disabled";
438 }; 396 };
439 397
440 gic: interrupt-controller@ff131000 { 398 gic: interrupt-controller@ff131000 {
441 compatible = "arm,gic-400"; 399 compatible = "arm,gic-400";
442 #interrupt-cells = <3>; 400 #interrupt-cells = <3>;
443 #address-cells = <0>; 401 #address-cells = <0>;
444 interrupt-controller; 402 interrupt-controller;
445 reg = <0x0 0xff131000 0 0x1000 403 reg = <0x0 0xff131000 0 0x1000>,
446 <0x0 0xff132000 0 0x2000 404 <0x0 0xff132000 0 0x2000>,
447 <0x0 0xff134000 0 0x2000 405 <0x0 0xff134000 0 0x2000>,
448 <0x0 0xff136000 0 0x2000 406 <0x0 0xff136000 0 0x2000>;
449 interrupts = <GIC_PPI 9 407 interrupts = <GIC_PPI 9
450 (GIC_CPU_MASK_SIMPLE(4) 408 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
451 }; 409 };
452 410
453 grf: syscon@ff140000 { 411 grf: syscon@ff140000 {
454 compatible = "rockchip,px30-gr 412 compatible = "rockchip,px30-grf", "syscon", "simple-mfd";
455 reg = <0x0 0xff140000 0x0 0x10 413 reg = <0x0 0xff140000 0x0 0x1000>;
456 #address-cells = <1>; 414 #address-cells = <1>;
457 #size-cells = <1>; 415 #size-cells = <1>;
458 416
459 io_domains: io-domains { 417 io_domains: io-domains {
460 compatible = "rockchip 418 compatible = "rockchip,px30-io-voltage-domain";
461 status = "disabled"; 419 status = "disabled";
462 }; 420 };
463 421
464 lvds: lvds { 422 lvds: lvds {
465 compatible = "rockchip 423 compatible = "rockchip,px30-lvds";
466 phys = <&dsi_dphy>; 424 phys = <&dsi_dphy>;
467 phy-names = "dphy"; 425 phy-names = "dphy";
468 rockchip,grf = <&grf>; 426 rockchip,grf = <&grf>;
469 rockchip,output = "lvd 427 rockchip,output = "lvds";
470 status = "disabled"; 428 status = "disabled";
471 429
472 ports { 430 ports {
473 #address-cells 431 #address-cells = <1>;
474 #size-cells = 432 #size-cells = <0>;
475 433
476 lvds_in: port@ !! 434 port@0 {
477 reg = 435 reg = <0>;
478 #addre 436 #address-cells = <1>;
479 #size- 437 #size-cells = <0>;
480 438
481 lvds_v 439 lvds_vopb_in: endpoint@0 {
482 440 reg = <0>;
483 441 remote-endpoint = <&vopb_out_lvds>;
484 }; 442 };
485 443
486 lvds_v 444 lvds_vopl_in: endpoint@1 {
487 445 reg = <1>;
488 446 remote-endpoint = <&vopl_out_lvds>;
489 }; 447 };
490 }; 448 };
491 <<
492 lvds_out: port <<
493 reg = <<
494 }; <<
495 }; 449 };
496 }; 450 };
497 }; 451 };
498 452
499 uart1: serial@ff158000 { 453 uart1: serial@ff158000 {
500 compatible = "rockchip,px30-ua 454 compatible = "rockchip,px30-uart", "snps,dw-apb-uart";
501 reg = <0x0 0xff158000 0x0 0x10 455 reg = <0x0 0xff158000 0x0 0x100>;
502 interrupts = <GIC_SPI 16 IRQ_T 456 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
503 clocks = <&cru SCLK_UART1>, <& 457 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
504 clock-names = "baudclk", "apb_ 458 clock-names = "baudclk", "apb_pclk";
505 dmas = <&dmac 2>, <&dmac 3>; 459 dmas = <&dmac 2>, <&dmac 3>;
506 dma-names = "tx", "rx"; 460 dma-names = "tx", "rx";
507 reg-shift = <2>; 461 reg-shift = <2>;
508 reg-io-width = <4>; 462 reg-io-width = <4>;
509 pinctrl-names = "default"; 463 pinctrl-names = "default";
510 pinctrl-0 = <&uart1_xfer &uart 464 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
511 status = "disabled"; 465 status = "disabled";
512 }; 466 };
513 467
514 uart2: serial@ff160000 { 468 uart2: serial@ff160000 {
515 compatible = "rockchip,px30-ua 469 compatible = "rockchip,px30-uart", "snps,dw-apb-uart";
516 reg = <0x0 0xff160000 0x0 0x10 470 reg = <0x0 0xff160000 0x0 0x100>;
517 interrupts = <GIC_SPI 17 IRQ_T 471 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
518 clocks = <&cru SCLK_UART2>, <& 472 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
519 clock-names = "baudclk", "apb_ 473 clock-names = "baudclk", "apb_pclk";
520 dmas = <&dmac 4>, <&dmac 5>; 474 dmas = <&dmac 4>, <&dmac 5>;
521 dma-names = "tx", "rx"; 475 dma-names = "tx", "rx";
522 reg-shift = <2>; 476 reg-shift = <2>;
523 reg-io-width = <4>; 477 reg-io-width = <4>;
524 pinctrl-names = "default"; 478 pinctrl-names = "default";
525 pinctrl-0 = <&uart2m0_xfer>; 479 pinctrl-0 = <&uart2m0_xfer>;
526 status = "disabled"; 480 status = "disabled";
527 }; 481 };
528 482
529 uart3: serial@ff168000 { 483 uart3: serial@ff168000 {
530 compatible = "rockchip,px30-ua 484 compatible = "rockchip,px30-uart", "snps,dw-apb-uart";
531 reg = <0x0 0xff168000 0x0 0x10 485 reg = <0x0 0xff168000 0x0 0x100>;
532 interrupts = <GIC_SPI 18 IRQ_T 486 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
533 clocks = <&cru SCLK_UART3>, <& 487 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
534 clock-names = "baudclk", "apb_ 488 clock-names = "baudclk", "apb_pclk";
535 dmas = <&dmac 6>, <&dmac 7>; 489 dmas = <&dmac 6>, <&dmac 7>;
536 dma-names = "tx", "rx"; 490 dma-names = "tx", "rx";
537 reg-shift = <2>; 491 reg-shift = <2>;
538 reg-io-width = <4>; 492 reg-io-width = <4>;
539 pinctrl-names = "default"; 493 pinctrl-names = "default";
540 pinctrl-0 = <&uart3m1_xfer &ua 494 pinctrl-0 = <&uart3m1_xfer &uart3m1_cts &uart3m1_rts>;
541 status = "disabled"; 495 status = "disabled";
542 }; 496 };
543 497
544 uart4: serial@ff170000 { 498 uart4: serial@ff170000 {
545 compatible = "rockchip,px30-ua 499 compatible = "rockchip,px30-uart", "snps,dw-apb-uart";
546 reg = <0x0 0xff170000 0x0 0x10 500 reg = <0x0 0xff170000 0x0 0x100>;
547 interrupts = <GIC_SPI 19 IRQ_T 501 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
548 clocks = <&cru SCLK_UART4>, <& 502 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
549 clock-names = "baudclk", "apb_ 503 clock-names = "baudclk", "apb_pclk";
550 dmas = <&dmac 8>, <&dmac 9>; 504 dmas = <&dmac 8>, <&dmac 9>;
551 dma-names = "tx", "rx"; 505 dma-names = "tx", "rx";
552 reg-shift = <2>; 506 reg-shift = <2>;
553 reg-io-width = <4>; 507 reg-io-width = <4>;
554 pinctrl-names = "default"; 508 pinctrl-names = "default";
555 pinctrl-0 = <&uart4_xfer &uart 509 pinctrl-0 = <&uart4_xfer &uart4_cts &uart4_rts>;
556 status = "disabled"; 510 status = "disabled";
557 }; 511 };
558 512
559 uart5: serial@ff178000 { 513 uart5: serial@ff178000 {
560 compatible = "rockchip,px30-ua 514 compatible = "rockchip,px30-uart", "snps,dw-apb-uart";
561 reg = <0x0 0xff178000 0x0 0x10 515 reg = <0x0 0xff178000 0x0 0x100>;
562 interrupts = <GIC_SPI 20 IRQ_T 516 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
563 clocks = <&cru SCLK_UART5>, <& 517 clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>;
564 clock-names = "baudclk", "apb_ 518 clock-names = "baudclk", "apb_pclk";
565 dmas = <&dmac 10>, <&dmac 11>; 519 dmas = <&dmac 10>, <&dmac 11>;
566 dma-names = "tx", "rx"; 520 dma-names = "tx", "rx";
567 reg-shift = <2>; 521 reg-shift = <2>;
568 reg-io-width = <4>; 522 reg-io-width = <4>;
569 pinctrl-names = "default"; 523 pinctrl-names = "default";
570 pinctrl-0 = <&uart5_xfer &uart 524 pinctrl-0 = <&uart5_xfer &uart5_cts &uart5_rts>;
571 status = "disabled"; 525 status = "disabled";
572 }; 526 };
573 527
574 i2c0: i2c@ff180000 { 528 i2c0: i2c@ff180000 {
575 compatible = "rockchip,px30-i2 529 compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c";
576 reg = <0x0 0xff180000 0x0 0x10 530 reg = <0x0 0xff180000 0x0 0x1000>;
577 clocks = <&cru SCLK_I2C0>, <&c !! 531 clocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>;
578 clock-names = "i2c", "pclk"; 532 clock-names = "i2c", "pclk";
579 interrupts = <GIC_SPI 7 IRQ_TY 533 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
580 pinctrl-names = "default"; 534 pinctrl-names = "default";
581 pinctrl-0 = <&i2c0_xfer>; 535 pinctrl-0 = <&i2c0_xfer>;
582 #address-cells = <1>; 536 #address-cells = <1>;
583 #size-cells = <0>; 537 #size-cells = <0>;
584 status = "disabled"; 538 status = "disabled";
585 }; 539 };
586 540
587 i2c1: i2c@ff190000 { 541 i2c1: i2c@ff190000 {
588 compatible = "rockchip,px30-i2 542 compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c";
589 reg = <0x0 0xff190000 0x0 0x10 543 reg = <0x0 0xff190000 0x0 0x1000>;
590 clocks = <&cru SCLK_I2C1>, <&c 544 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
591 clock-names = "i2c", "pclk"; 545 clock-names = "i2c", "pclk";
592 interrupts = <GIC_SPI 8 IRQ_TY 546 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
593 pinctrl-names = "default"; 547 pinctrl-names = "default";
594 pinctrl-0 = <&i2c1_xfer>; 548 pinctrl-0 = <&i2c1_xfer>;
595 #address-cells = <1>; 549 #address-cells = <1>;
596 #size-cells = <0>; 550 #size-cells = <0>;
597 status = "disabled"; 551 status = "disabled";
598 }; 552 };
599 553
600 i2c2: i2c@ff1a0000 { 554 i2c2: i2c@ff1a0000 {
601 compatible = "rockchip,px30-i2 555 compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c";
602 reg = <0x0 0xff1a0000 0x0 0x10 556 reg = <0x0 0xff1a0000 0x0 0x1000>;
603 clocks = <&cru SCLK_I2C2>, <&c 557 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
604 clock-names = "i2c", "pclk"; 558 clock-names = "i2c", "pclk";
605 interrupts = <GIC_SPI 9 IRQ_TY 559 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
606 pinctrl-names = "default"; 560 pinctrl-names = "default";
607 pinctrl-0 = <&i2c2_xfer>; 561 pinctrl-0 = <&i2c2_xfer>;
608 #address-cells = <1>; 562 #address-cells = <1>;
609 #size-cells = <0>; 563 #size-cells = <0>;
610 status = "disabled"; 564 status = "disabled";
611 }; 565 };
612 566
613 i2c3: i2c@ff1b0000 { 567 i2c3: i2c@ff1b0000 {
614 compatible = "rockchip,px30-i2 568 compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c";
615 reg = <0x0 0xff1b0000 0x0 0x10 569 reg = <0x0 0xff1b0000 0x0 0x1000>;
616 clocks = <&cru SCLK_I2C3>, <&c 570 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
617 clock-names = "i2c", "pclk"; 571 clock-names = "i2c", "pclk";
618 interrupts = <GIC_SPI 10 IRQ_T 572 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
619 pinctrl-names = "default"; 573 pinctrl-names = "default";
620 pinctrl-0 = <&i2c3_xfer>; 574 pinctrl-0 = <&i2c3_xfer>;
621 #address-cells = <1>; 575 #address-cells = <1>;
622 #size-cells = <0>; 576 #size-cells = <0>;
623 status = "disabled"; 577 status = "disabled";
624 }; 578 };
625 579
626 spi0: spi@ff1d0000 { 580 spi0: spi@ff1d0000 {
627 compatible = "rockchip,px30-sp 581 compatible = "rockchip,px30-spi", "rockchip,rk3066-spi";
628 reg = <0x0 0xff1d0000 0x0 0x10 582 reg = <0x0 0xff1d0000 0x0 0x1000>;
629 interrupts = <GIC_SPI 26 IRQ_T 583 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
630 clocks = <&cru SCLK_SPI0>, <&c 584 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
631 clock-names = "spiclk", "apb_p 585 clock-names = "spiclk", "apb_pclk";
632 dmas = <&dmac 12>, <&dmac 13>; 586 dmas = <&dmac 12>, <&dmac 13>;
633 dma-names = "tx", "rx"; 587 dma-names = "tx", "rx";
634 num-cs = <2>; <<
635 pinctrl-names = "default"; 588 pinctrl-names = "default";
636 pinctrl-0 = <&spi0_clk &spi0_c 589 pinctrl-0 = <&spi0_clk &spi0_csn &spi0_miso &spi0_mosi>;
637 #address-cells = <1>; 590 #address-cells = <1>;
638 #size-cells = <0>; 591 #size-cells = <0>;
639 status = "disabled"; 592 status = "disabled";
640 }; 593 };
641 594
642 spi1: spi@ff1d8000 { 595 spi1: spi@ff1d8000 {
643 compatible = "rockchip,px30-sp 596 compatible = "rockchip,px30-spi", "rockchip,rk3066-spi";
644 reg = <0x0 0xff1d8000 0x0 0x10 597 reg = <0x0 0xff1d8000 0x0 0x1000>;
645 interrupts = <GIC_SPI 27 IRQ_T 598 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
646 clocks = <&cru SCLK_SPI1>, <&c 599 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
647 clock-names = "spiclk", "apb_p 600 clock-names = "spiclk", "apb_pclk";
648 dmas = <&dmac 14>, <&dmac 15>; 601 dmas = <&dmac 14>, <&dmac 15>;
649 dma-names = "tx", "rx"; 602 dma-names = "tx", "rx";
650 num-cs = <2>; <<
651 pinctrl-names = "default"; 603 pinctrl-names = "default";
652 pinctrl-0 = <&spi1_clk &spi1_c 604 pinctrl-0 = <&spi1_clk &spi1_csn0 &spi1_csn1 &spi1_miso &spi1_mosi>;
653 #address-cells = <1>; 605 #address-cells = <1>;
654 #size-cells = <0>; 606 #size-cells = <0>;
655 status = "disabled"; 607 status = "disabled";
656 }; 608 };
657 609
658 wdt: watchdog@ff1e0000 { 610 wdt: watchdog@ff1e0000 {
659 compatible = "rockchip,px30-wd 611 compatible = "rockchip,px30-wdt", "snps,dw-wdt";
660 reg = <0x0 0xff1e0000 0x0 0x10 612 reg = <0x0 0xff1e0000 0x0 0x100>;
661 clocks = <&cru PCLK_WDT_NS>; 613 clocks = <&cru PCLK_WDT_NS>;
662 interrupts = <GIC_SPI 37 IRQ_T 614 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
663 status = "disabled"; 615 status = "disabled";
664 }; 616 };
665 617
666 pwm0: pwm@ff200000 { 618 pwm0: pwm@ff200000 {
667 compatible = "rockchip,px30-pw 619 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
668 reg = <0x0 0xff200000 0x0 0x10 620 reg = <0x0 0xff200000 0x0 0x10>;
669 clocks = <&cru SCLK_PWM0>, <&c 621 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
670 clock-names = "pwm", "pclk"; 622 clock-names = "pwm", "pclk";
671 pinctrl-names = "default"; 623 pinctrl-names = "default";
672 pinctrl-0 = <&pwm0_pin>; 624 pinctrl-0 = <&pwm0_pin>;
673 #pwm-cells = <3>; 625 #pwm-cells = <3>;
674 status = "disabled"; 626 status = "disabled";
675 }; 627 };
676 628
677 pwm1: pwm@ff200010 { 629 pwm1: pwm@ff200010 {
678 compatible = "rockchip,px30-pw 630 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
679 reg = <0x0 0xff200010 0x0 0x10 631 reg = <0x0 0xff200010 0x0 0x10>;
680 clocks = <&cru SCLK_PWM0>, <&c 632 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
681 clock-names = "pwm", "pclk"; 633 clock-names = "pwm", "pclk";
682 pinctrl-names = "default"; 634 pinctrl-names = "default";
683 pinctrl-0 = <&pwm1_pin>; 635 pinctrl-0 = <&pwm1_pin>;
684 #pwm-cells = <3>; 636 #pwm-cells = <3>;
685 status = "disabled"; 637 status = "disabled";
686 }; 638 };
687 639
688 pwm2: pwm@ff200020 { 640 pwm2: pwm@ff200020 {
689 compatible = "rockchip,px30-pw 641 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
690 reg = <0x0 0xff200020 0x0 0x10 642 reg = <0x0 0xff200020 0x0 0x10>;
691 clocks = <&cru SCLK_PWM0>, <&c 643 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
692 clock-names = "pwm", "pclk"; 644 clock-names = "pwm", "pclk";
693 pinctrl-names = "default"; 645 pinctrl-names = "default";
694 pinctrl-0 = <&pwm2_pin>; 646 pinctrl-0 = <&pwm2_pin>;
695 #pwm-cells = <3>; 647 #pwm-cells = <3>;
696 status = "disabled"; 648 status = "disabled";
697 }; 649 };
698 650
699 pwm3: pwm@ff200030 { 651 pwm3: pwm@ff200030 {
700 compatible = "rockchip,px30-pw 652 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
701 reg = <0x0 0xff200030 0x0 0x10 653 reg = <0x0 0xff200030 0x0 0x10>;
702 clocks = <&cru SCLK_PWM0>, <&c 654 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
703 clock-names = "pwm", "pclk"; 655 clock-names = "pwm", "pclk";
704 pinctrl-names = "default"; 656 pinctrl-names = "default";
705 pinctrl-0 = <&pwm3_pin>; 657 pinctrl-0 = <&pwm3_pin>;
706 #pwm-cells = <3>; 658 #pwm-cells = <3>;
707 status = "disabled"; 659 status = "disabled";
708 }; 660 };
709 661
710 pwm4: pwm@ff208000 { 662 pwm4: pwm@ff208000 {
711 compatible = "rockchip,px30-pw 663 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
712 reg = <0x0 0xff208000 0x0 0x10 664 reg = <0x0 0xff208000 0x0 0x10>;
713 clocks = <&cru SCLK_PWM1>, <&c 665 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>;
714 clock-names = "pwm", "pclk"; 666 clock-names = "pwm", "pclk";
715 pinctrl-names = "default"; 667 pinctrl-names = "default";
716 pinctrl-0 = <&pwm4_pin>; 668 pinctrl-0 = <&pwm4_pin>;
717 #pwm-cells = <3>; 669 #pwm-cells = <3>;
718 status = "disabled"; 670 status = "disabled";
719 }; 671 };
720 672
721 pwm5: pwm@ff208010 { 673 pwm5: pwm@ff208010 {
722 compatible = "rockchip,px30-pw 674 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
723 reg = <0x0 0xff208010 0x0 0x10 675 reg = <0x0 0xff208010 0x0 0x10>;
724 clocks = <&cru SCLK_PWM1>, <&c 676 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>;
725 clock-names = "pwm", "pclk"; 677 clock-names = "pwm", "pclk";
726 pinctrl-names = "default"; 678 pinctrl-names = "default";
727 pinctrl-0 = <&pwm5_pin>; 679 pinctrl-0 = <&pwm5_pin>;
728 #pwm-cells = <3>; 680 #pwm-cells = <3>;
729 status = "disabled"; 681 status = "disabled";
730 }; 682 };
731 683
732 pwm6: pwm@ff208020 { 684 pwm6: pwm@ff208020 {
733 compatible = "rockchip,px30-pw 685 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
734 reg = <0x0 0xff208020 0x0 0x10 686 reg = <0x0 0xff208020 0x0 0x10>;
735 clocks = <&cru SCLK_PWM1>, <&c 687 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>;
736 clock-names = "pwm", "pclk"; 688 clock-names = "pwm", "pclk";
737 pinctrl-names = "default"; 689 pinctrl-names = "default";
738 pinctrl-0 = <&pwm6_pin>; 690 pinctrl-0 = <&pwm6_pin>;
739 #pwm-cells = <3>; 691 #pwm-cells = <3>;
740 status = "disabled"; 692 status = "disabled";
741 }; 693 };
742 694
743 pwm7: pwm@ff208030 { 695 pwm7: pwm@ff208030 {
744 compatible = "rockchip,px30-pw 696 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
745 reg = <0x0 0xff208030 0x0 0x10 697 reg = <0x0 0xff208030 0x0 0x10>;
746 clocks = <&cru SCLK_PWM1>, <&c 698 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>;
747 clock-names = "pwm", "pclk"; 699 clock-names = "pwm", "pclk";
748 pinctrl-names = "default"; 700 pinctrl-names = "default";
749 pinctrl-0 = <&pwm7_pin>; 701 pinctrl-0 = <&pwm7_pin>;
750 #pwm-cells = <3>; 702 #pwm-cells = <3>;
751 status = "disabled"; 703 status = "disabled";
752 }; 704 };
753 705
754 rktimer: timer@ff210000 { 706 rktimer: timer@ff210000 {
755 compatible = "rockchip,px30-ti 707 compatible = "rockchip,px30-timer", "rockchip,rk3288-timer";
756 reg = <0x0 0xff210000 0x0 0x10 708 reg = <0x0 0xff210000 0x0 0x1000>;
757 interrupts = <GIC_SPI 30 IRQ_T 709 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
758 clocks = <&cru PCLK_TIMER>, <& 710 clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER0>;
759 clock-names = "pclk", "timer"; 711 clock-names = "pclk", "timer";
760 }; 712 };
761 713
762 dmac: dma-controller@ff240000 { 714 dmac: dma-controller@ff240000 {
763 compatible = "arm,pl330", "arm 715 compatible = "arm,pl330", "arm,primecell";
764 reg = <0x0 0xff240000 0x0 0x40 716 reg = <0x0 0xff240000 0x0 0x4000>;
765 interrupts = <GIC_SPI 1 IRQ_TY 717 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
766 <GIC_SPI 2 IRQ_TY 718 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
767 arm,pl330-periph-burst; 719 arm,pl330-periph-burst;
768 clocks = <&cru ACLK_DMAC>; 720 clocks = <&cru ACLK_DMAC>;
769 clock-names = "apb_pclk"; 721 clock-names = "apb_pclk";
770 #dma-cells = <1>; 722 #dma-cells = <1>;
771 }; 723 };
772 724
773 tsadc: tsadc@ff280000 { 725 tsadc: tsadc@ff280000 {
774 compatible = "rockchip,px30-ts 726 compatible = "rockchip,px30-tsadc";
775 reg = <0x0 0xff280000 0x0 0x10 727 reg = <0x0 0xff280000 0x0 0x100>;
776 interrupts = <GIC_SPI 36 IRQ_T 728 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
777 assigned-clocks = <&cru SCLK_T 729 assigned-clocks = <&cru SCLK_TSADC>;
778 assigned-clock-rates = <50000> 730 assigned-clock-rates = <50000>;
779 clocks = <&cru SCLK_TSADC>, <& 731 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
780 clock-names = "tsadc", "apb_pc 732 clock-names = "tsadc", "apb_pclk";
781 resets = <&cru SRST_TSADC>; 733 resets = <&cru SRST_TSADC>;
782 reset-names = "tsadc-apb"; 734 reset-names = "tsadc-apb";
783 rockchip,grf = <&grf>; 735 rockchip,grf = <&grf>;
784 rockchip,hw-tshut-temp = <1200 736 rockchip,hw-tshut-temp = <120000>;
785 pinctrl-names = "init", "defau 737 pinctrl-names = "init", "default", "sleep";
786 pinctrl-0 = <&tsadc_otp_pin>; 738 pinctrl-0 = <&tsadc_otp_pin>;
787 pinctrl-1 = <&tsadc_otp_out>; 739 pinctrl-1 = <&tsadc_otp_out>;
788 pinctrl-2 = <&tsadc_otp_pin>; 740 pinctrl-2 = <&tsadc_otp_pin>;
789 #thermal-sensor-cells = <1>; 741 #thermal-sensor-cells = <1>;
790 status = "disabled"; 742 status = "disabled";
791 }; 743 };
792 744
793 saradc: saradc@ff288000 { 745 saradc: saradc@ff288000 {
794 compatible = "rockchip,px30-sa 746 compatible = "rockchip,px30-saradc", "rockchip,rk3399-saradc";
795 reg = <0x0 0xff288000 0x0 0x10 747 reg = <0x0 0xff288000 0x0 0x100>;
796 interrupts = <GIC_SPI 84 IRQ_T 748 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
797 #io-channel-cells = <1>; 749 #io-channel-cells = <1>;
798 clocks = <&cru SCLK_SARADC>, < 750 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
799 clock-names = "saradc", "apb_p 751 clock-names = "saradc", "apb_pclk";
800 resets = <&cru SRST_SARADC_P>; 752 resets = <&cru SRST_SARADC_P>;
801 reset-names = "saradc-apb"; 753 reset-names = "saradc-apb";
802 status = "disabled"; 754 status = "disabled";
803 }; 755 };
804 756
805 otp: nvmem@ff290000 { 757 otp: nvmem@ff290000 {
806 compatible = "rockchip,px30-ot 758 compatible = "rockchip,px30-otp";
807 reg = <0x0 0xff290000 0x0 0x40 759 reg = <0x0 0xff290000 0x0 0x4000>;
808 clocks = <&cru SCLK_OTP_USR>, 760 clocks = <&cru SCLK_OTP_USR>, <&cru PCLK_OTP_NS>,
809 <&cru PCLK_OTP_PHY>; 761 <&cru PCLK_OTP_PHY>;
810 clock-names = "otp", "apb_pclk 762 clock-names = "otp", "apb_pclk", "phy";
811 resets = <&cru SRST_OTP_PHY>; 763 resets = <&cru SRST_OTP_PHY>;
812 reset-names = "phy"; 764 reset-names = "phy";
813 #address-cells = <1>; 765 #address-cells = <1>;
814 #size-cells = <1>; 766 #size-cells = <1>;
815 767
816 /* Data cells */ 768 /* Data cells */
817 cpu_id: id@7 { 769 cpu_id: id@7 {
818 reg = <0x07 0x10>; 770 reg = <0x07 0x10>;
819 }; 771 };
820 cpu_leakage: cpu-leakage@17 { 772 cpu_leakage: cpu-leakage@17 {
821 reg = <0x17 0x1>; 773 reg = <0x17 0x1>;
822 }; 774 };
823 performance: performance@1e { 775 performance: performance@1e {
824 reg = <0x1e 0x1>; 776 reg = <0x1e 0x1>;
825 bits = <4 3>; 777 bits = <4 3>;
826 }; 778 };
827 }; 779 };
828 780
829 cru: clock-controller@ff2b0000 { 781 cru: clock-controller@ff2b0000 {
830 compatible = "rockchip,px30-cr 782 compatible = "rockchip,px30-cru";
831 reg = <0x0 0xff2b0000 0x0 0x10 783 reg = <0x0 0xff2b0000 0x0 0x1000>;
832 clocks = <&xin24m>, <&pmucru P 784 clocks = <&xin24m>, <&pmucru PLL_GPLL>;
833 clock-names = "xin24m", "gpll" 785 clock-names = "xin24m", "gpll";
834 rockchip,grf = <&grf>; 786 rockchip,grf = <&grf>;
835 #clock-cells = <1>; 787 #clock-cells = <1>;
836 #reset-cells = <1>; 788 #reset-cells = <1>;
837 789
838 assigned-clocks = <&cru PLL_NP 790 assigned-clocks = <&cru PLL_NPLL>,
839 <&cru ACLK_BUS_PRE>, < 791 <&cru ACLK_BUS_PRE>, <&cru ACLK_PERI_PRE>,
840 <&cru HCLK_BUS_PRE>, < 792 <&cru HCLK_BUS_PRE>, <&cru HCLK_PERI_PRE>,
841 <&cru PCLK_BUS_PRE>, < 793 <&cru PCLK_BUS_PRE>, <&cru SCLK_GPU>;
842 794
843 assigned-clock-rates = <118800 795 assigned-clock-rates = <1188000000>,
844 <200000000>, <20000000 796 <200000000>, <200000000>,
845 <150000000>, <15000000 797 <150000000>, <150000000>,
846 <100000000>, <20000000 798 <100000000>, <200000000>;
847 }; 799 };
848 800
849 pmucru: clock-controller@ff2bc000 { 801 pmucru: clock-controller@ff2bc000 {
850 compatible = "rockchip,px30-pm 802 compatible = "rockchip,px30-pmucru";
851 reg = <0x0 0xff2bc000 0x0 0x10 803 reg = <0x0 0xff2bc000 0x0 0x1000>;
852 clocks = <&xin24m>; 804 clocks = <&xin24m>;
853 clock-names = "xin24m"; 805 clock-names = "xin24m";
854 rockchip,grf = <&grf>; 806 rockchip,grf = <&grf>;
855 #clock-cells = <1>; 807 #clock-cells = <1>;
856 #reset-cells = <1>; 808 #reset-cells = <1>;
857 809
858 assigned-clocks = 810 assigned-clocks =
859 <&pmucru PLL_GPLL>, <& 811 <&pmucru PLL_GPLL>, <&pmucru PCLK_PMU_PRE>,
860 <&pmucru SCLK_WIFI_PMU 812 <&pmucru SCLK_WIFI_PMU>;
861 assigned-clock-rates = 813 assigned-clock-rates =
862 <1200000000>, <1000000 814 <1200000000>, <100000000>,
863 <26000000>; 815 <26000000>;
864 }; 816 };
865 817
866 usb2phy_grf: syscon@ff2c0000 { 818 usb2phy_grf: syscon@ff2c0000 {
867 compatible = "rockchip,px30-us 819 compatible = "rockchip,px30-usb2phy-grf", "syscon",
868 "simple-mfd"; 820 "simple-mfd";
869 reg = <0x0 0xff2c0000 0x0 0x10 821 reg = <0x0 0xff2c0000 0x0 0x10000>;
870 #address-cells = <1>; 822 #address-cells = <1>;
871 #size-cells = <1>; 823 #size-cells = <1>;
872 824
873 u2phy: usb2phy@100 { 825 u2phy: usb2phy@100 {
874 compatible = "rockchip 826 compatible = "rockchip,px30-usb2phy";
875 reg = <0x100 0x20>; 827 reg = <0x100 0x20>;
876 clocks = <&pmucru SCLK 828 clocks = <&pmucru SCLK_USBPHY_REF>;
877 clock-names = "phyclk" 829 clock-names = "phyclk";
878 #clock-cells = <0>; 830 #clock-cells = <0>;
879 assigned-clocks = <&cr 831 assigned-clocks = <&cru USB480M>;
880 assigned-clock-parents 832 assigned-clock-parents = <&u2phy>;
881 clock-output-names = " 833 clock-output-names = "usb480m_phy";
882 status = "disabled"; 834 status = "disabled";
883 835
884 u2phy_host: host-port 836 u2phy_host: host-port {
885 #phy-cells = < 837 #phy-cells = <0>;
886 interrupts = < 838 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
887 interrupt-name 839 interrupt-names = "linestate";
888 status = "disa 840 status = "disabled";
889 }; 841 };
890 842
891 u2phy_otg: otg-port { 843 u2phy_otg: otg-port {
892 #phy-cells = < 844 #phy-cells = <0>;
893 interrupts = < 845 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
894 < 846 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
895 < 847 <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
896 interrupt-name 848 interrupt-names = "otg-bvalid", "otg-id",
897 849 "linestate";
898 status = "disa 850 status = "disabled";
899 }; 851 };
900 }; 852 };
901 }; 853 };
902 854
903 dsi_dphy: phy@ff2e0000 { 855 dsi_dphy: phy@ff2e0000 {
904 compatible = "rockchip,px30-ds 856 compatible = "rockchip,px30-dsi-dphy";
905 reg = <0x0 0xff2e0000 0x0 0x10 857 reg = <0x0 0xff2e0000 0x0 0x10000>;
906 clocks = <&pmucru SCLK_MIPIDSI 858 clocks = <&pmucru SCLK_MIPIDSIPHY_REF>, <&cru PCLK_MIPIDSIPHY>;
907 clock-names = "ref", "pclk"; 859 clock-names = "ref", "pclk";
908 resets = <&cru SRST_MIPIDSIPHY 860 resets = <&cru SRST_MIPIDSIPHY_P>;
909 reset-names = "apb"; 861 reset-names = "apb";
910 #phy-cells = <0>; 862 #phy-cells = <0>;
911 power-domains = <&power PX30_P 863 power-domains = <&power PX30_PD_VO>;
912 status = "disabled"; 864 status = "disabled";
913 }; 865 };
914 866
915 csi_dphy: phy@ff2f0000 { 867 csi_dphy: phy@ff2f0000 {
916 compatible = "rockchip,px30-cs 868 compatible = "rockchip,px30-csi-dphy";
917 reg = <0x0 0xff2f0000 0x0 0x40 869 reg = <0x0 0xff2f0000 0x0 0x4000>;
918 clocks = <&cru PCLK_MIPICSIPHY 870 clocks = <&cru PCLK_MIPICSIPHY>;
919 clock-names = "pclk"; 871 clock-names = "pclk";
920 #phy-cells = <0>; 872 #phy-cells = <0>;
921 power-domains = <&power PX30_P 873 power-domains = <&power PX30_PD_VI>;
922 resets = <&cru SRST_MIPICSIPHY 874 resets = <&cru SRST_MIPICSIPHY_P>;
923 reset-names = "apb"; 875 reset-names = "apb";
924 rockchip,grf = <&grf>; 876 rockchip,grf = <&grf>;
925 status = "disabled"; 877 status = "disabled";
926 }; 878 };
927 879
928 usb20_otg: usb@ff300000 { 880 usb20_otg: usb@ff300000 {
929 compatible = "rockchip,px30-us 881 compatible = "rockchip,px30-usb", "rockchip,rk3066-usb",
930 "snps,dwc2"; 882 "snps,dwc2";
931 reg = <0x0 0xff300000 0x0 0x40 883 reg = <0x0 0xff300000 0x0 0x40000>;
932 interrupts = <GIC_SPI 62 IRQ_T 884 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
933 clocks = <&cru HCLK_OTG>; 885 clocks = <&cru HCLK_OTG>;
934 clock-names = "otg"; 886 clock-names = "otg";
935 dr_mode = "otg"; 887 dr_mode = "otg";
936 g-np-tx-fifo-size = <16>; 888 g-np-tx-fifo-size = <16>;
937 g-rx-fifo-size = <280>; 889 g-rx-fifo-size = <280>;
938 g-tx-fifo-size = <256 128 128 890 g-tx-fifo-size = <256 128 128 64 32 16>;
939 phys = <&u2phy_otg>; 891 phys = <&u2phy_otg>;
940 phy-names = "usb2-phy"; 892 phy-names = "usb2-phy";
941 power-domains = <&power PX30_P 893 power-domains = <&power PX30_PD_USB>;
942 status = "disabled"; 894 status = "disabled";
943 }; 895 };
944 896
945 usb_host0_ehci: usb@ff340000 { 897 usb_host0_ehci: usb@ff340000 {
946 compatible = "generic-ehci"; 898 compatible = "generic-ehci";
947 reg = <0x0 0xff340000 0x0 0x10 899 reg = <0x0 0xff340000 0x0 0x10000>;
948 interrupts = <GIC_SPI 60 IRQ_T 900 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
949 clocks = <&cru HCLK_HOST>; 901 clocks = <&cru HCLK_HOST>;
950 phys = <&u2phy_host>; 902 phys = <&u2phy_host>;
951 phy-names = "usb"; 903 phy-names = "usb";
952 power-domains = <&power PX30_P 904 power-domains = <&power PX30_PD_USB>;
953 status = "disabled"; 905 status = "disabled";
954 }; 906 };
955 907
956 usb_host0_ohci: usb@ff350000 { 908 usb_host0_ohci: usb@ff350000 {
957 compatible = "generic-ohci"; 909 compatible = "generic-ohci";
958 reg = <0x0 0xff350000 0x0 0x10 910 reg = <0x0 0xff350000 0x0 0x10000>;
959 interrupts = <GIC_SPI 61 IRQ_T 911 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
960 clocks = <&cru HCLK_HOST>; 912 clocks = <&cru HCLK_HOST>;
961 phys = <&u2phy_host>; 913 phys = <&u2phy_host>;
962 phy-names = "usb"; 914 phy-names = "usb";
963 power-domains = <&power PX30_P 915 power-domains = <&power PX30_PD_USB>;
964 status = "disabled"; 916 status = "disabled";
965 }; 917 };
966 918
967 gmac: ethernet@ff360000 { 919 gmac: ethernet@ff360000 {
968 compatible = "rockchip,px30-gm 920 compatible = "rockchip,px30-gmac";
969 reg = <0x0 0xff360000 0x0 0x10 921 reg = <0x0 0xff360000 0x0 0x10000>;
970 interrupts = <GIC_SPI 43 IRQ_T 922 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
971 interrupt-names = "macirq"; 923 interrupt-names = "macirq";
972 clocks = <&cru SCLK_GMAC>, <&c 924 clocks = <&cru SCLK_GMAC>, <&cru SCLK_GMAC_RX_TX>,
973 <&cru SCLK_GMAC_RX_TX 925 <&cru SCLK_GMAC_RX_TX>, <&cru SCLK_MAC_REF>,
974 <&cru SCLK_MAC_REFOUT 926 <&cru SCLK_MAC_REFOUT>, <&cru ACLK_GMAC>,
975 <&cru PCLK_GMAC>, <&c 927 <&cru PCLK_GMAC>, <&cru SCLK_GMAC_RMII>;
976 clock-names = "stmmaceth", "ma 928 clock-names = "stmmaceth", "mac_clk_rx",
977 "mac_clk_tx", "c 929 "mac_clk_tx", "clk_mac_ref",
978 "clk_mac_refout" 930 "clk_mac_refout", "aclk_mac",
979 "pclk_mac", "clk 931 "pclk_mac", "clk_mac_speed";
980 rockchip,grf = <&grf>; 932 rockchip,grf = <&grf>;
981 phy-mode = "rmii"; 933 phy-mode = "rmii";
982 pinctrl-names = "default"; 934 pinctrl-names = "default";
983 pinctrl-0 = <&rmii_pins &mac_r 935 pinctrl-0 = <&rmii_pins &mac_refclk_12ma>;
984 power-domains = <&power PX30_P 936 power-domains = <&power PX30_PD_GMAC>;
985 resets = <&cru SRST_GMAC_A>; 937 resets = <&cru SRST_GMAC_A>;
986 reset-names = "stmmaceth"; 938 reset-names = "stmmaceth";
987 status = "disabled"; 939 status = "disabled";
988 }; 940 };
989 941
990 sdmmc: mmc@ff370000 { 942 sdmmc: mmc@ff370000 {
991 compatible = "rockchip,px30-dw 943 compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc";
992 reg = <0x0 0xff370000 0x0 0x40 944 reg = <0x0 0xff370000 0x0 0x4000>;
993 interrupts = <GIC_SPI 54 IRQ_T 945 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
994 clocks = <&cru HCLK_SDMMC>, <& 946 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
995 <&cru SCLK_SDMMC_DRV> 947 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
996 clock-names = "biu", "ciu", "c 948 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
997 bus-width = <4>; 949 bus-width = <4>;
998 fifo-depth = <0x100>; 950 fifo-depth = <0x100>;
999 max-frequency = <150000000>; 951 max-frequency = <150000000>;
1000 pinctrl-names = "default"; 952 pinctrl-names = "default";
1001 pinctrl-0 = <&sdmmc_clk &sdmm 953 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_det &sdmmc_bus4>;
1002 power-domains = <&power PX30_ 954 power-domains = <&power PX30_PD_SDCARD>;
1003 status = "disabled"; 955 status = "disabled";
1004 }; 956 };
1005 957
1006 sdio: mmc@ff380000 { 958 sdio: mmc@ff380000 {
1007 compatible = "rockchip,px30-d 959 compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc";
1008 reg = <0x0 0xff380000 0x0 0x4 960 reg = <0x0 0xff380000 0x0 0x4000>;
1009 interrupts = <GIC_SPI 55 IRQ_ 961 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
1010 clocks = <&cru HCLK_SDIO>, <& 962 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
1011 <&cru SCLK_SDIO_DRV> 963 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
1012 clock-names = "biu", "ciu", " 964 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
1013 bus-width = <4>; 965 bus-width = <4>;
1014 fifo-depth = <0x100>; 966 fifo-depth = <0x100>;
1015 max-frequency = <150000000>; 967 max-frequency = <150000000>;
1016 pinctrl-names = "default"; 968 pinctrl-names = "default";
1017 pinctrl-0 = <&sdio_bus4 &sdio 969 pinctrl-0 = <&sdio_bus4 &sdio_cmd &sdio_clk>;
1018 power-domains = <&power PX30_ 970 power-domains = <&power PX30_PD_MMC_NAND>;
1019 status = "disabled"; 971 status = "disabled";
1020 }; 972 };
1021 973
1022 emmc: mmc@ff390000 { 974 emmc: mmc@ff390000 {
1023 compatible = "rockchip,px30-d 975 compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc";
1024 reg = <0x0 0xff390000 0x0 0x4 976 reg = <0x0 0xff390000 0x0 0x4000>;
1025 interrupts = <GIC_SPI 53 IRQ_ 977 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
1026 clocks = <&cru HCLK_EMMC>, <& 978 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
1027 <&cru SCLK_EMMC_DRV> 979 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
1028 clock-names = "biu", "ciu", " 980 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
1029 bus-width = <8>; 981 bus-width = <8>;
1030 fifo-depth = <0x100>; 982 fifo-depth = <0x100>;
1031 max-frequency = <150000000>; 983 max-frequency = <150000000>;
1032 pinctrl-names = "default"; 984 pinctrl-names = "default";
1033 pinctrl-0 = <&emmc_clk &emmc_ 985 pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
1034 power-domains = <&power PX30_ 986 power-domains = <&power PX30_PD_MMC_NAND>;
1035 status = "disabled"; 987 status = "disabled";
1036 }; 988 };
1037 989
1038 sfc: spi@ff3a0000 { 990 sfc: spi@ff3a0000 {
1039 compatible = "rockchip,sfc"; 991 compatible = "rockchip,sfc";
1040 reg = <0x0 0xff3a0000 0x0 0x4 992 reg = <0x0 0xff3a0000 0x0 0x4000>;
1041 interrupts = <GIC_SPI 56 IRQ_ 993 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
1042 clocks = <&cru SCLK_SFC>, <&c 994 clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>;
1043 clock-names = "clk_sfc", "hcl 995 clock-names = "clk_sfc", "hclk_sfc";
1044 pinctrl-0 = <&sfc_clk &sfc_cs 996 pinctrl-0 = <&sfc_clk &sfc_cs0 &sfc_bus4>;
1045 pinctrl-names = "default"; 997 pinctrl-names = "default";
1046 power-domains = <&power PX30_ 998 power-domains = <&power PX30_PD_MMC_NAND>;
1047 status = "disabled"; 999 status = "disabled";
1048 }; 1000 };
1049 1001
1050 nfc: nand-controller@ff3b0000 { 1002 nfc: nand-controller@ff3b0000 {
1051 compatible = "rockchip,px30-n 1003 compatible = "rockchip,px30-nfc";
1052 reg = <0x0 0xff3b0000 0x0 0x4 1004 reg = <0x0 0xff3b0000 0x0 0x4000>;
1053 interrupts = <GIC_SPI 57 IRQ_ 1005 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
1054 clocks = <&cru HCLK_NANDC>, < 1006 clocks = <&cru HCLK_NANDC>, <&cru SCLK_NANDC>;
1055 clock-names = "ahb", "nfc"; 1007 clock-names = "ahb", "nfc";
1056 assigned-clocks = <&cru SCLK_ 1008 assigned-clocks = <&cru SCLK_NANDC>;
1057 assigned-clock-rates = <15000 1009 assigned-clock-rates = <150000000>;
1058 pinctrl-names = "default"; 1010 pinctrl-names = "default";
1059 pinctrl-0 = <&flash_ale &flas 1011 pinctrl-0 = <&flash_ale &flash_bus8 &flash_cle &flash_cs0
1060 &flash_rdn &flas 1012 &flash_rdn &flash_rdy &flash_wrn &flash_dqs>;
1061 power-domains = <&power PX30_ 1013 power-domains = <&power PX30_PD_MMC_NAND>;
1062 status = "disabled"; 1014 status = "disabled";
1063 }; 1015 };
1064 1016
1065 gpu_opp_table: opp-table-1 { 1017 gpu_opp_table: opp-table-1 {
1066 compatible = "operating-point 1018 compatible = "operating-points-v2";
1067 1019
1068 opp-200000000 { 1020 opp-200000000 {
1069 opp-hz = /bits/ 64 <2 1021 opp-hz = /bits/ 64 <200000000>;
1070 opp-microvolt = <9500 1022 opp-microvolt = <950000>;
1071 }; 1023 };
1072 opp-300000000 { 1024 opp-300000000 {
1073 opp-hz = /bits/ 64 <3 1025 opp-hz = /bits/ 64 <300000000>;
1074 opp-microvolt = <9750 1026 opp-microvolt = <975000>;
1075 }; 1027 };
1076 opp-400000000 { 1028 opp-400000000 {
1077 opp-hz = /bits/ 64 <4 1029 opp-hz = /bits/ 64 <400000000>;
1078 opp-microvolt = <1050 1030 opp-microvolt = <1050000>;
1079 }; 1031 };
1080 opp-480000000 { 1032 opp-480000000 {
1081 opp-hz = /bits/ 64 <4 1033 opp-hz = /bits/ 64 <480000000>;
1082 opp-microvolt = <1125 1034 opp-microvolt = <1125000>;
1083 }; 1035 };
1084 }; 1036 };
1085 1037
1086 gpu: gpu@ff400000 { 1038 gpu: gpu@ff400000 {
1087 compatible = "rockchip,px30-m 1039 compatible = "rockchip,px30-mali", "arm,mali-bifrost";
1088 reg = <0x0 0xff400000 0x0 0x4 1040 reg = <0x0 0xff400000 0x0 0x4000>;
1089 interrupts = <GIC_SPI 47 IRQ_ 1041 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
1090 <GIC_SPI 46 IRQ_ 1042 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
1091 <GIC_SPI 45 IRQ_ 1043 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
1092 interrupt-names = "job", "mmu 1044 interrupt-names = "job", "mmu", "gpu";
1093 clocks = <&cru SCLK_GPU>; 1045 clocks = <&cru SCLK_GPU>;
1094 #cooling-cells = <2>; 1046 #cooling-cells = <2>;
1095 power-domains = <&power PX30_ 1047 power-domains = <&power PX30_PD_GPU>;
1096 operating-points-v2 = <&gpu_o 1048 operating-points-v2 = <&gpu_opp_table>;
1097 status = "disabled"; 1049 status = "disabled";
1098 }; 1050 };
1099 1051
1100 vpu: video-codec@ff442000 { 1052 vpu: video-codec@ff442000 {
1101 compatible = "rockchip,px30-v 1053 compatible = "rockchip,px30-vpu";
1102 reg = <0x0 0xff442000 0x0 0x8 1054 reg = <0x0 0xff442000 0x0 0x800>;
1103 interrupts = <GIC_SPI 80 IRQ_ 1055 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
1104 <GIC_SPI 79 IRQ_ 1056 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
1105 interrupt-names = "vepu", "vd 1057 interrupt-names = "vepu", "vdpu";
1106 clocks = <&cru ACLK_VPU>, <&c 1058 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
1107 clock-names = "aclk", "hclk"; 1059 clock-names = "aclk", "hclk";
1108 iommus = <&vpu_mmu>; 1060 iommus = <&vpu_mmu>;
1109 power-domains = <&power PX30_ 1061 power-domains = <&power PX30_PD_VPU>;
1110 }; 1062 };
1111 1063
1112 vpu_mmu: iommu@ff442800 { 1064 vpu_mmu: iommu@ff442800 {
1113 compatible = "rockchip,iommu" 1065 compatible = "rockchip,iommu";
1114 reg = <0x0 0xff442800 0x0 0x1 1066 reg = <0x0 0xff442800 0x0 0x100>;
1115 interrupts = <GIC_SPI 81 IRQ_ 1067 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
1116 clocks = <&cru ACLK_VPU>, <&c 1068 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
1117 clock-names = "aclk", "iface" 1069 clock-names = "aclk", "iface";
1118 #iommu-cells = <0>; 1070 #iommu-cells = <0>;
1119 power-domains = <&power PX30_ 1071 power-domains = <&power PX30_PD_VPU>;
1120 }; 1072 };
1121 1073
1122 dsi: dsi@ff450000 { 1074 dsi: dsi@ff450000 {
1123 compatible = "rockchip,px30-m !! 1075 compatible = "rockchip,px30-mipi-dsi";
1124 reg = <0x0 0xff450000 0x0 0x1 1076 reg = <0x0 0xff450000 0x0 0x10000>;
1125 interrupts = <GIC_SPI 75 IRQ_ 1077 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
1126 clocks = <&cru PCLK_MIPI_DSI> 1078 clocks = <&cru PCLK_MIPI_DSI>;
1127 clock-names = "pclk"; 1079 clock-names = "pclk";
1128 phys = <&dsi_dphy>; 1080 phys = <&dsi_dphy>;
1129 phy-names = "dphy"; 1081 phy-names = "dphy";
1130 power-domains = <&power PX30_ 1082 power-domains = <&power PX30_PD_VO>;
1131 resets = <&cru SRST_MIPIDSI_H 1083 resets = <&cru SRST_MIPIDSI_HOST_P>;
1132 reset-names = "apb"; 1084 reset-names = "apb";
1133 rockchip,grf = <&grf>; 1085 rockchip,grf = <&grf>;
1134 #address-cells = <1>; 1086 #address-cells = <1>;
1135 #size-cells = <0>; 1087 #size-cells = <0>;
1136 status = "disabled"; 1088 status = "disabled";
1137 1089
1138 ports { 1090 ports {
1139 #address-cells = <1>; 1091 #address-cells = <1>;
1140 #size-cells = <0>; 1092 #size-cells = <0>;
1141 1093
1142 dsi_in: port@0 { !! 1094 port@0 {
1143 reg = <0>; 1095 reg = <0>;
1144 #address-cell 1096 #address-cells = <1>;
1145 #size-cells = 1097 #size-cells = <0>;
1146 1098
1147 dsi_in_vopb: 1099 dsi_in_vopb: endpoint@0 {
1148 reg = 1100 reg = <0>;
1149 remot 1101 remote-endpoint = <&vopb_out_dsi>;
1150 }; 1102 };
1151 1103
1152 dsi_in_vopl: 1104 dsi_in_vopl: endpoint@1 {
1153 reg = 1105 reg = <1>;
1154 remot 1106 remote-endpoint = <&vopl_out_dsi>;
1155 }; 1107 };
1156 }; <<
1157 <<
1158 dsi_out: port@1 { <<
1159 reg = <1>; <<
1160 }; 1108 };
1161 }; 1109 };
1162 }; 1110 };
1163 1111
1164 vopb: vop@ff460000 { 1112 vopb: vop@ff460000 {
1165 compatible = "rockchip,px30-v 1113 compatible = "rockchip,px30-vop-big";
1166 reg = <0x0 0xff460000 0x0 0xe 1114 reg = <0x0 0xff460000 0x0 0xefc>;
1167 interrupts = <GIC_SPI 77 IRQ_ 1115 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
1168 clocks = <&cru ACLK_VOPB>, <& 1116 clocks = <&cru ACLK_VOPB>, <&cru DCLK_VOPB>,
1169 <&cru HCLK_VOPB>; 1117 <&cru HCLK_VOPB>;
1170 clock-names = "aclk_vop", "dc 1118 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1171 resets = <&cru SRST_VOPB_A>, 1119 resets = <&cru SRST_VOPB_A>, <&cru SRST_VOPB_H>, <&cru SRST_VOPB>;
1172 reset-names = "axi", "ahb", " 1120 reset-names = "axi", "ahb", "dclk";
1173 iommus = <&vopb_mmu>; 1121 iommus = <&vopb_mmu>;
1174 power-domains = <&power PX30_ 1122 power-domains = <&power PX30_PD_VO>;
1175 status = "disabled"; 1123 status = "disabled";
1176 1124
1177 vopb_out: port { 1125 vopb_out: port {
1178 #address-cells = <1>; 1126 #address-cells = <1>;
1179 #size-cells = <0>; 1127 #size-cells = <0>;
1180 1128
1181 vopb_out_dsi: endpoin 1129 vopb_out_dsi: endpoint@0 {
1182 reg = <0>; 1130 reg = <0>;
1183 remote-endpoi 1131 remote-endpoint = <&dsi_in_vopb>;
1184 }; 1132 };
1185 1133
1186 vopb_out_lvds: endpoi 1134 vopb_out_lvds: endpoint@1 {
1187 reg = <1>; 1135 reg = <1>;
1188 remote-endpoi 1136 remote-endpoint = <&lvds_vopb_in>;
1189 }; 1137 };
1190 }; 1138 };
1191 }; 1139 };
1192 1140
1193 vopb_mmu: iommu@ff460f00 { 1141 vopb_mmu: iommu@ff460f00 {
1194 compatible = "rockchip,iommu" 1142 compatible = "rockchip,iommu";
1195 reg = <0x0 0xff460f00 0x0 0x1 1143 reg = <0x0 0xff460f00 0x0 0x100>;
1196 interrupts = <GIC_SPI 77 IRQ_ 1144 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
1197 clocks = <&cru ACLK_VOPB>, <& 1145 clocks = <&cru ACLK_VOPB>, <&cru HCLK_VOPB>;
1198 clock-names = "aclk", "iface" 1146 clock-names = "aclk", "iface";
1199 power-domains = <&power PX30_ 1147 power-domains = <&power PX30_PD_VO>;
1200 #iommu-cells = <0>; 1148 #iommu-cells = <0>;
1201 status = "disabled"; 1149 status = "disabled";
1202 }; 1150 };
1203 1151
1204 vopl: vop@ff470000 { 1152 vopl: vop@ff470000 {
1205 compatible = "rockchip,px30-v 1153 compatible = "rockchip,px30-vop-lit";
1206 reg = <0x0 0xff470000 0x0 0xe 1154 reg = <0x0 0xff470000 0x0 0xefc>;
1207 interrupts = <GIC_SPI 78 IRQ_ 1155 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
1208 clocks = <&cru ACLK_VOPL>, <& 1156 clocks = <&cru ACLK_VOPL>, <&cru DCLK_VOPL>,
1209 <&cru HCLK_VOPL>; 1157 <&cru HCLK_VOPL>;
1210 clock-names = "aclk_vop", "dc 1158 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1211 resets = <&cru SRST_VOPL_A>, 1159 resets = <&cru SRST_VOPL_A>, <&cru SRST_VOPL_H>, <&cru SRST_VOPL>;
1212 reset-names = "axi", "ahb", " 1160 reset-names = "axi", "ahb", "dclk";
1213 iommus = <&vopl_mmu>; 1161 iommus = <&vopl_mmu>;
1214 power-domains = <&power PX30_ 1162 power-domains = <&power PX30_PD_VO>;
1215 status = "disabled"; 1163 status = "disabled";
1216 1164
1217 vopl_out: port { 1165 vopl_out: port {
1218 #address-cells = <1>; 1166 #address-cells = <1>;
1219 #size-cells = <0>; 1167 #size-cells = <0>;
1220 1168
1221 vopl_out_dsi: endpoin 1169 vopl_out_dsi: endpoint@0 {
1222 reg = <0>; 1170 reg = <0>;
1223 remote-endpoi 1171 remote-endpoint = <&dsi_in_vopl>;
1224 }; 1172 };
1225 1173
1226 vopl_out_lvds: endpoi 1174 vopl_out_lvds: endpoint@1 {
1227 reg = <1>; 1175 reg = <1>;
1228 remote-endpoi 1176 remote-endpoint = <&lvds_vopl_in>;
1229 }; 1177 };
1230 }; 1178 };
1231 }; 1179 };
1232 1180
1233 vopl_mmu: iommu@ff470f00 { 1181 vopl_mmu: iommu@ff470f00 {
1234 compatible = "rockchip,iommu" 1182 compatible = "rockchip,iommu";
1235 reg = <0x0 0xff470f00 0x0 0x1 1183 reg = <0x0 0xff470f00 0x0 0x100>;
1236 interrupts = <GIC_SPI 78 IRQ_ 1184 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
1237 clocks = <&cru ACLK_VOPL>, <& 1185 clocks = <&cru ACLK_VOPL>, <&cru HCLK_VOPL>;
1238 clock-names = "aclk", "iface" 1186 clock-names = "aclk", "iface";
1239 power-domains = <&power PX30_ 1187 power-domains = <&power PX30_PD_VO>;
1240 #iommu-cells = <0>; 1188 #iommu-cells = <0>;
1241 status = "disabled"; 1189 status = "disabled";
1242 }; 1190 };
1243 1191
1244 isp: isp@ff4a0000 { 1192 isp: isp@ff4a0000 {
1245 compatible = "rockchip,px30-c 1193 compatible = "rockchip,px30-cif-isp"; /*rk3326-rkisp1*/
1246 reg = <0x0 0xff4a0000 0x0 0x8 1194 reg = <0x0 0xff4a0000 0x0 0x8000>;
1247 interrupts = <GIC_SPI 70 IRQ_ 1195 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
1248 <GIC_SPI 73 IRQ_ 1196 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
1249 <GIC_SPI 74 IRQ_ 1197 <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
1250 interrupt-names = "isp", "mi" 1198 interrupt-names = "isp", "mi", "mipi";
1251 clocks = <&cru SCLK_ISP>, 1199 clocks = <&cru SCLK_ISP>,
1252 <&cru ACLK_ISP>, 1200 <&cru ACLK_ISP>,
1253 <&cru HCLK_ISP>, 1201 <&cru HCLK_ISP>,
1254 <&cru PCLK_ISP>; 1202 <&cru PCLK_ISP>;
1255 clock-names = "isp", "aclk", 1203 clock-names = "isp", "aclk", "hclk", "pclk";
1256 iommus = <&isp_mmu>; 1204 iommus = <&isp_mmu>;
1257 phys = <&csi_dphy>; 1205 phys = <&csi_dphy>;
1258 phy-names = "dphy"; 1206 phy-names = "dphy";
1259 power-domains = <&power PX30_ 1207 power-domains = <&power PX30_PD_VI>;
1260 status = "disabled"; 1208 status = "disabled";
1261 1209
1262 ports { 1210 ports {
1263 #address-cells = <1>; 1211 #address-cells = <1>;
1264 #size-cells = <0>; 1212 #size-cells = <0>;
1265 1213
1266 port@0 { 1214 port@0 {
1267 reg = <0>; 1215 reg = <0>;
1268 #address-cell 1216 #address-cells = <1>;
1269 #size-cells = 1217 #size-cells = <0>;
1270 }; 1218 };
1271 }; 1219 };
1272 }; 1220 };
1273 1221
1274 isp_mmu: iommu@ff4a8000 { 1222 isp_mmu: iommu@ff4a8000 {
1275 compatible = "rockchip,iommu" 1223 compatible = "rockchip,iommu";
1276 reg = <0x0 0xff4a8000 0x0 0x1 1224 reg = <0x0 0xff4a8000 0x0 0x100>;
1277 interrupts = <GIC_SPI 70 IRQ_ 1225 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
1278 clocks = <&cru ACLK_ISP>, <&c 1226 clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>;
1279 clock-names = "aclk", "iface" 1227 clock-names = "aclk", "iface";
1280 power-domains = <&power PX30_ 1228 power-domains = <&power PX30_PD_VI>;
1281 rockchip,disable-mmu-reset; 1229 rockchip,disable-mmu-reset;
1282 #iommu-cells = <0>; 1230 #iommu-cells = <0>;
1283 }; 1231 };
1284 1232
1285 qos_gmac: qos@ff518000 { 1233 qos_gmac: qos@ff518000 {
1286 compatible = "rockchip,px30-q 1234 compatible = "rockchip,px30-qos", "syscon";
1287 reg = <0x0 0xff518000 0x0 0x2 1235 reg = <0x0 0xff518000 0x0 0x20>;
1288 }; 1236 };
1289 1237
1290 qos_gpu: qos@ff520000 { 1238 qos_gpu: qos@ff520000 {
1291 compatible = "rockchip,px30-q 1239 compatible = "rockchip,px30-qos", "syscon";
1292 reg = <0x0 0xff520000 0x0 0x2 1240 reg = <0x0 0xff520000 0x0 0x20>;
1293 }; 1241 };
1294 1242
1295 qos_sdmmc: qos@ff52c000 { 1243 qos_sdmmc: qos@ff52c000 {
1296 compatible = "rockchip,px30-q 1244 compatible = "rockchip,px30-qos", "syscon";
1297 reg = <0x0 0xff52c000 0x0 0x2 1245 reg = <0x0 0xff52c000 0x0 0x20>;
1298 }; 1246 };
1299 1247
1300 qos_emmc: qos@ff538000 { 1248 qos_emmc: qos@ff538000 {
1301 compatible = "rockchip,px30-q 1249 compatible = "rockchip,px30-qos", "syscon";
1302 reg = <0x0 0xff538000 0x0 0x2 1250 reg = <0x0 0xff538000 0x0 0x20>;
1303 }; 1251 };
1304 1252
1305 qos_nand: qos@ff538080 { 1253 qos_nand: qos@ff538080 {
1306 compatible = "rockchip,px30-q 1254 compatible = "rockchip,px30-qos", "syscon";
1307 reg = <0x0 0xff538080 0x0 0x2 1255 reg = <0x0 0xff538080 0x0 0x20>;
1308 }; 1256 };
1309 1257
1310 qos_sdio: qos@ff538100 { 1258 qos_sdio: qos@ff538100 {
1311 compatible = "rockchip,px30-q 1259 compatible = "rockchip,px30-qos", "syscon";
1312 reg = <0x0 0xff538100 0x0 0x2 1260 reg = <0x0 0xff538100 0x0 0x20>;
1313 }; 1261 };
1314 1262
1315 qos_sfc: qos@ff538180 { 1263 qos_sfc: qos@ff538180 {
1316 compatible = "rockchip,px30-q 1264 compatible = "rockchip,px30-qos", "syscon";
1317 reg = <0x0 0xff538180 0x0 0x2 1265 reg = <0x0 0xff538180 0x0 0x20>;
1318 }; 1266 };
1319 1267
1320 qos_usb_host: qos@ff540000 { 1268 qos_usb_host: qos@ff540000 {
1321 compatible = "rockchip,px30-q 1269 compatible = "rockchip,px30-qos", "syscon";
1322 reg = <0x0 0xff540000 0x0 0x2 1270 reg = <0x0 0xff540000 0x0 0x20>;
1323 }; 1271 };
1324 1272
1325 qos_usb_otg: qos@ff540080 { 1273 qos_usb_otg: qos@ff540080 {
1326 compatible = "rockchip,px30-q 1274 compatible = "rockchip,px30-qos", "syscon";
1327 reg = <0x0 0xff540080 0x0 0x2 1275 reg = <0x0 0xff540080 0x0 0x20>;
1328 }; 1276 };
1329 1277
1330 qos_isp_128: qos@ff548000 { 1278 qos_isp_128: qos@ff548000 {
1331 compatible = "rockchip,px30-q 1279 compatible = "rockchip,px30-qos", "syscon";
1332 reg = <0x0 0xff548000 0x0 0x2 1280 reg = <0x0 0xff548000 0x0 0x20>;
1333 }; 1281 };
1334 1282
1335 qos_isp_rd: qos@ff548080 { 1283 qos_isp_rd: qos@ff548080 {
1336 compatible = "rockchip,px30-q 1284 compatible = "rockchip,px30-qos", "syscon";
1337 reg = <0x0 0xff548080 0x0 0x2 1285 reg = <0x0 0xff548080 0x0 0x20>;
1338 }; 1286 };
1339 1287
1340 qos_isp_wr: qos@ff548100 { 1288 qos_isp_wr: qos@ff548100 {
1341 compatible = "rockchip,px30-q 1289 compatible = "rockchip,px30-qos", "syscon";
1342 reg = <0x0 0xff548100 0x0 0x2 1290 reg = <0x0 0xff548100 0x0 0x20>;
1343 }; 1291 };
1344 1292
1345 qos_isp_m1: qos@ff548180 { 1293 qos_isp_m1: qos@ff548180 {
1346 compatible = "rockchip,px30-q 1294 compatible = "rockchip,px30-qos", "syscon";
1347 reg = <0x0 0xff548180 0x0 0x2 1295 reg = <0x0 0xff548180 0x0 0x20>;
1348 }; 1296 };
1349 1297
1350 qos_vip: qos@ff548200 { 1298 qos_vip: qos@ff548200 {
1351 compatible = "rockchip,px30-q 1299 compatible = "rockchip,px30-qos", "syscon";
1352 reg = <0x0 0xff548200 0x0 0x2 1300 reg = <0x0 0xff548200 0x0 0x20>;
1353 }; 1301 };
1354 1302
1355 qos_rga_rd: qos@ff550000 { 1303 qos_rga_rd: qos@ff550000 {
1356 compatible = "rockchip,px30-q 1304 compatible = "rockchip,px30-qos", "syscon";
1357 reg = <0x0 0xff550000 0x0 0x2 1305 reg = <0x0 0xff550000 0x0 0x20>;
1358 }; 1306 };
1359 1307
1360 qos_rga_wr: qos@ff550080 { 1308 qos_rga_wr: qos@ff550080 {
1361 compatible = "rockchip,px30-q 1309 compatible = "rockchip,px30-qos", "syscon";
1362 reg = <0x0 0xff550080 0x0 0x2 1310 reg = <0x0 0xff550080 0x0 0x20>;
1363 }; 1311 };
1364 1312
1365 qos_vop_m0: qos@ff550100 { 1313 qos_vop_m0: qos@ff550100 {
1366 compatible = "rockchip,px30-q 1314 compatible = "rockchip,px30-qos", "syscon";
1367 reg = <0x0 0xff550100 0x0 0x2 1315 reg = <0x0 0xff550100 0x0 0x20>;
1368 }; 1316 };
1369 1317
1370 qos_vop_m1: qos@ff550180 { 1318 qos_vop_m1: qos@ff550180 {
1371 compatible = "rockchip,px30-q 1319 compatible = "rockchip,px30-qos", "syscon";
1372 reg = <0x0 0xff550180 0x0 0x2 1320 reg = <0x0 0xff550180 0x0 0x20>;
1373 }; 1321 };
1374 1322
1375 qos_vpu: qos@ff558000 { 1323 qos_vpu: qos@ff558000 {
1376 compatible = "rockchip,px30-q 1324 compatible = "rockchip,px30-qos", "syscon";
1377 reg = <0x0 0xff558000 0x0 0x2 1325 reg = <0x0 0xff558000 0x0 0x20>;
1378 }; 1326 };
1379 1327
1380 qos_vpu_r128: qos@ff558080 { 1328 qos_vpu_r128: qos@ff558080 {
1381 compatible = "rockchip,px30-q 1329 compatible = "rockchip,px30-qos", "syscon";
1382 reg = <0x0 0xff558080 0x0 0x2 1330 reg = <0x0 0xff558080 0x0 0x20>;
1383 }; 1331 };
1384 1332
1385 pinctrl: pinctrl { 1333 pinctrl: pinctrl {
1386 compatible = "rockchip,px30-p 1334 compatible = "rockchip,px30-pinctrl";
1387 rockchip,grf = <&grf>; 1335 rockchip,grf = <&grf>;
1388 rockchip,pmu = <&pmugrf>; 1336 rockchip,pmu = <&pmugrf>;
1389 #address-cells = <2>; 1337 #address-cells = <2>;
1390 #size-cells = <2>; 1338 #size-cells = <2>;
1391 ranges; 1339 ranges;
1392 1340
1393 gpio0: gpio@ff040000 { 1341 gpio0: gpio@ff040000 {
1394 compatible = "rockchi 1342 compatible = "rockchip,gpio-bank";
1395 reg = <0x0 0xff040000 1343 reg = <0x0 0xff040000 0x0 0x100>;
1396 interrupts = <GIC_SPI 1344 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
1397 clocks = <&pmucru PCL 1345 clocks = <&pmucru PCLK_GPIO0_PMU>;
1398 gpio-controller; 1346 gpio-controller;
1399 #gpio-cells = <2>; 1347 #gpio-cells = <2>;
1400 1348
1401 interrupt-controller; 1349 interrupt-controller;
1402 #interrupt-cells = <2 1350 #interrupt-cells = <2>;
1403 }; 1351 };
1404 1352
1405 gpio1: gpio@ff250000 { 1353 gpio1: gpio@ff250000 {
1406 compatible = "rockchi 1354 compatible = "rockchip,gpio-bank";
1407 reg = <0x0 0xff250000 1355 reg = <0x0 0xff250000 0x0 0x100>;
1408 interrupts = <GIC_SPI 1356 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
1409 clocks = <&cru PCLK_G 1357 clocks = <&cru PCLK_GPIO1>;
1410 gpio-controller; 1358 gpio-controller;
1411 #gpio-cells = <2>; 1359 #gpio-cells = <2>;
1412 1360
1413 interrupt-controller; 1361 interrupt-controller;
1414 #interrupt-cells = <2 1362 #interrupt-cells = <2>;
1415 }; 1363 };
1416 1364
1417 gpio2: gpio@ff260000 { 1365 gpio2: gpio@ff260000 {
1418 compatible = "rockchi 1366 compatible = "rockchip,gpio-bank";
1419 reg = <0x0 0xff260000 1367 reg = <0x0 0xff260000 0x0 0x100>;
1420 interrupts = <GIC_SPI 1368 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
1421 clocks = <&cru PCLK_G 1369 clocks = <&cru PCLK_GPIO2>;
1422 gpio-controller; 1370 gpio-controller;
1423 #gpio-cells = <2>; 1371 #gpio-cells = <2>;
1424 1372
1425 interrupt-controller; 1373 interrupt-controller;
1426 #interrupt-cells = <2 1374 #interrupt-cells = <2>;
1427 }; 1375 };
1428 1376
1429 gpio3: gpio@ff270000 { 1377 gpio3: gpio@ff270000 {
1430 compatible = "rockchi 1378 compatible = "rockchip,gpio-bank";
1431 reg = <0x0 0xff270000 1379 reg = <0x0 0xff270000 0x0 0x100>;
1432 interrupts = <GIC_SPI 1380 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
1433 clocks = <&cru PCLK_G 1381 clocks = <&cru PCLK_GPIO3>;
1434 gpio-controller; 1382 gpio-controller;
1435 #gpio-cells = <2>; 1383 #gpio-cells = <2>;
1436 1384
1437 interrupt-controller; 1385 interrupt-controller;
1438 #interrupt-cells = <2 1386 #interrupt-cells = <2>;
1439 }; 1387 };
1440 1388
1441 pcfg_pull_up: pcfg-pull-up { 1389 pcfg_pull_up: pcfg-pull-up {
1442 bias-pull-up; 1390 bias-pull-up;
1443 }; 1391 };
1444 1392
1445 pcfg_pull_down: pcfg-pull-dow 1393 pcfg_pull_down: pcfg-pull-down {
1446 bias-pull-down; 1394 bias-pull-down;
1447 }; 1395 };
1448 1396
1449 pcfg_pull_none: pcfg-pull-non 1397 pcfg_pull_none: pcfg-pull-none {
1450 bias-disable; 1398 bias-disable;
1451 }; 1399 };
1452 1400
1453 pcfg_pull_none_2ma: pcfg-pull 1401 pcfg_pull_none_2ma: pcfg-pull-none-2ma {
1454 bias-disable; 1402 bias-disable;
1455 drive-strength = <2>; 1403 drive-strength = <2>;
1456 }; 1404 };
1457 1405
1458 pcfg_pull_up_2ma: pcfg-pull-u 1406 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
1459 bias-pull-up; 1407 bias-pull-up;
1460 drive-strength = <2>; 1408 drive-strength = <2>;
1461 }; 1409 };
1462 1410
1463 pcfg_pull_up_4ma: pcfg-pull-u 1411 pcfg_pull_up_4ma: pcfg-pull-up-4ma {
1464 bias-pull-up; 1412 bias-pull-up;
1465 drive-strength = <4>; 1413 drive-strength = <4>;
1466 }; 1414 };
1467 1415
1468 pcfg_pull_none_4ma: pcfg-pull 1416 pcfg_pull_none_4ma: pcfg-pull-none-4ma {
1469 bias-disable; 1417 bias-disable;
1470 drive-strength = <4>; 1418 drive-strength = <4>;
1471 }; 1419 };
1472 1420
1473 pcfg_pull_down_4ma: pcfg-pull 1421 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
1474 bias-pull-down; 1422 bias-pull-down;
1475 drive-strength = <4>; 1423 drive-strength = <4>;
1476 }; 1424 };
1477 1425
1478 pcfg_pull_none_8ma: pcfg-pull 1426 pcfg_pull_none_8ma: pcfg-pull-none-8ma {
1479 bias-disable; 1427 bias-disable;
1480 drive-strength = <8>; 1428 drive-strength = <8>;
1481 }; 1429 };
1482 1430
1483 pcfg_pull_up_8ma: pcfg-pull-u 1431 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
1484 bias-pull-up; 1432 bias-pull-up;
1485 drive-strength = <8>; 1433 drive-strength = <8>;
1486 }; 1434 };
1487 1435
1488 pcfg_pull_none_12ma: pcfg-pul 1436 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1489 bias-disable; 1437 bias-disable;
1490 drive-strength = <12> 1438 drive-strength = <12>;
1491 }; 1439 };
1492 1440
1493 pcfg_pull_up_12ma: pcfg-pull- 1441 pcfg_pull_up_12ma: pcfg-pull-up-12ma {
1494 bias-pull-up; 1442 bias-pull-up;
1495 drive-strength = <12> 1443 drive-strength = <12>;
1496 }; 1444 };
1497 1445
1498 pcfg_pull_none_smt: pcfg-pull 1446 pcfg_pull_none_smt: pcfg-pull-none-smt {
1499 bias-disable; 1447 bias-disable;
1500 input-schmitt-enable; 1448 input-schmitt-enable;
1501 }; 1449 };
1502 1450
1503 pcfg_output_high: pcfg-output 1451 pcfg_output_high: pcfg-output-high {
1504 output-high; 1452 output-high;
1505 }; 1453 };
1506 1454
1507 pcfg_output_low: pcfg-output- 1455 pcfg_output_low: pcfg-output-low {
1508 output-low; 1456 output-low;
1509 }; 1457 };
1510 1458
1511 pcfg_input_high: pcfg-input-h 1459 pcfg_input_high: pcfg-input-high {
1512 bias-pull-up; 1460 bias-pull-up;
1513 input-enable; 1461 input-enable;
1514 }; 1462 };
1515 1463
1516 pcfg_input: pcfg-input { 1464 pcfg_input: pcfg-input {
1517 input-enable; 1465 input-enable;
1518 }; 1466 };
1519 1467
1520 i2c0 { 1468 i2c0 {
1521 i2c0_xfer: i2c0-xfer 1469 i2c0_xfer: i2c0-xfer {
1522 rockchip,pins 1470 rockchip,pins =
1523 <0 RK 1471 <0 RK_PB0 1 &pcfg_pull_none_smt>,
1524 <0 RK 1472 <0 RK_PB1 1 &pcfg_pull_none_smt>;
1525 }; 1473 };
1526 }; 1474 };
1527 1475
1528 i2c1 { 1476 i2c1 {
1529 i2c1_xfer: i2c1-xfer 1477 i2c1_xfer: i2c1-xfer {
1530 rockchip,pins 1478 rockchip,pins =
1531 <0 RK 1479 <0 RK_PC2 1 &pcfg_pull_none_smt>,
1532 <0 RK 1480 <0 RK_PC3 1 &pcfg_pull_none_smt>;
1533 }; 1481 };
1534 }; 1482 };
1535 1483
1536 i2c2 { 1484 i2c2 {
1537 i2c2_xfer: i2c2-xfer 1485 i2c2_xfer: i2c2-xfer {
1538 rockchip,pins 1486 rockchip,pins =
1539 <2 RK 1487 <2 RK_PB7 2 &pcfg_pull_none_smt>,
1540 <2 RK 1488 <2 RK_PC0 2 &pcfg_pull_none_smt>;
1541 }; 1489 };
1542 }; 1490 };
1543 1491
1544 i2c3 { 1492 i2c3 {
1545 i2c3_xfer: i2c3-xfer 1493 i2c3_xfer: i2c3-xfer {
1546 rockchip,pins 1494 rockchip,pins =
1547 <1 RK 1495 <1 RK_PB4 4 &pcfg_pull_none_smt>,
1548 <1 RK 1496 <1 RK_PB5 4 &pcfg_pull_none_smt>;
1549 }; 1497 };
1550 }; 1498 };
1551 1499
1552 tsadc { 1500 tsadc {
1553 tsadc_otp_pin: tsadc- 1501 tsadc_otp_pin: tsadc-otp-pin {
1554 rockchip,pins 1502 rockchip,pins =
1555 <0 RK 1503 <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
1556 }; 1504 };
1557 1505
1558 tsadc_otp_out: tsadc- 1506 tsadc_otp_out: tsadc-otp-out {
1559 rockchip,pins 1507 rockchip,pins =
1560 <0 RK 1508 <0 RK_PA6 1 &pcfg_pull_none>;
1561 }; 1509 };
1562 }; 1510 };
1563 1511
1564 uart0 { 1512 uart0 {
1565 uart0_xfer: uart0-xfe 1513 uart0_xfer: uart0-xfer {
1566 rockchip,pins 1514 rockchip,pins =
1567 <0 RK 1515 <0 RK_PB2 1 &pcfg_pull_up>,
1568 <0 RK 1516 <0 RK_PB3 1 &pcfg_pull_up>;
1569 }; 1517 };
1570 1518
1571 uart0_cts: uart0-cts 1519 uart0_cts: uart0-cts {
1572 rockchip,pins 1520 rockchip,pins =
1573 <0 RK 1521 <0 RK_PB4 1 &pcfg_pull_none>;
1574 }; 1522 };
1575 1523
1576 uart0_rts: uart0-rts 1524 uart0_rts: uart0-rts {
1577 rockchip,pins 1525 rockchip,pins =
1578 <0 RK 1526 <0 RK_PB5 1 &pcfg_pull_none>;
1579 }; 1527 };
1580 }; 1528 };
1581 1529
1582 uart1 { 1530 uart1 {
1583 uart1_xfer: uart1-xfe 1531 uart1_xfer: uart1-xfer {
1584 rockchip,pins 1532 rockchip,pins =
1585 <1 RK 1533 <1 RK_PC1 1 &pcfg_pull_up>,
1586 <1 RK 1534 <1 RK_PC0 1 &pcfg_pull_up>;
1587 }; 1535 };
1588 1536
1589 uart1_cts: uart1-cts 1537 uart1_cts: uart1-cts {
1590 rockchip,pins 1538 rockchip,pins =
1591 <1 RK 1539 <1 RK_PC2 1 &pcfg_pull_none>;
1592 }; 1540 };
1593 1541
1594 uart1_rts: uart1-rts 1542 uart1_rts: uart1-rts {
1595 rockchip,pins 1543 rockchip,pins =
1596 <1 RK 1544 <1 RK_PC3 1 &pcfg_pull_none>;
1597 }; 1545 };
1598 }; 1546 };
1599 1547
1600 uart2-m0 { 1548 uart2-m0 {
1601 uart2m0_xfer: uart2m0 1549 uart2m0_xfer: uart2m0-xfer {
1602 rockchip,pins 1550 rockchip,pins =
1603 <1 RK 1551 <1 RK_PD2 2 &pcfg_pull_up>,
1604 <1 RK 1552 <1 RK_PD3 2 &pcfg_pull_up>;
1605 }; 1553 };
1606 }; 1554 };
1607 1555
1608 uart2-m1 { 1556 uart2-m1 {
1609 uart2m1_xfer: uart2m1 1557 uart2m1_xfer: uart2m1-xfer {
1610 rockchip,pins 1558 rockchip,pins =
1611 <2 RK 1559 <2 RK_PB4 2 &pcfg_pull_up>,
1612 <2 RK 1560 <2 RK_PB6 2 &pcfg_pull_up>;
1613 }; 1561 };
1614 }; 1562 };
1615 1563
1616 uart3-m0 { 1564 uart3-m0 {
1617 uart3m0_xfer: uart3m0 1565 uart3m0_xfer: uart3m0-xfer {
1618 rockchip,pins 1566 rockchip,pins =
1619 <0 RK 1567 <0 RK_PC0 2 &pcfg_pull_up>,
1620 <0 RK 1568 <0 RK_PC1 2 &pcfg_pull_up>;
1621 }; 1569 };
1622 1570
1623 uart3m0_cts: uart3m0- 1571 uart3m0_cts: uart3m0-cts {
1624 rockchip,pins 1572 rockchip,pins =
1625 <0 RK 1573 <0 RK_PC2 2 &pcfg_pull_none>;
1626 }; 1574 };
1627 1575
1628 uart3m0_rts: uart3m0- 1576 uart3m0_rts: uart3m0-rts {
1629 rockchip,pins 1577 rockchip,pins =
1630 <0 RK 1578 <0 RK_PC3 2 &pcfg_pull_none>;
1631 }; 1579 };
1632 }; 1580 };
1633 1581
1634 uart3-m1 { 1582 uart3-m1 {
1635 uart3m1_xfer: uart3m1 1583 uart3m1_xfer: uart3m1-xfer {
1636 rockchip,pins 1584 rockchip,pins =
1637 <1 RK 1585 <1 RK_PB6 2 &pcfg_pull_up>,
1638 <1 RK 1586 <1 RK_PB7 2 &pcfg_pull_up>;
1639 }; 1587 };
1640 1588
1641 uart3m1_cts: uart3m1- 1589 uart3m1_cts: uart3m1-cts {
1642 rockchip,pins 1590 rockchip,pins =
1643 <1 RK 1591 <1 RK_PB4 2 &pcfg_pull_none>;
1644 }; 1592 };
1645 1593
1646 uart3m1_rts: uart3m1- 1594 uart3m1_rts: uart3m1-rts {
1647 rockchip,pins 1595 rockchip,pins =
1648 <1 RK 1596 <1 RK_PB5 2 &pcfg_pull_none>;
1649 }; 1597 };
1650 }; 1598 };
1651 1599
1652 uart4 { 1600 uart4 {
1653 uart4_xfer: uart4-xfe 1601 uart4_xfer: uart4-xfer {
1654 rockchip,pins 1602 rockchip,pins =
1655 <1 RK 1603 <1 RK_PD4 2 &pcfg_pull_up>,
1656 <1 RK 1604 <1 RK_PD5 2 &pcfg_pull_up>;
1657 }; 1605 };
1658 1606
1659 uart4_cts: uart4-cts 1607 uart4_cts: uart4-cts {
1660 rockchip,pins 1608 rockchip,pins =
1661 <1 RK 1609 <1 RK_PD6 2 &pcfg_pull_none>;
1662 }; 1610 };
1663 1611
1664 uart4_rts: uart4-rts 1612 uart4_rts: uart4-rts {
1665 rockchip,pins 1613 rockchip,pins =
1666 <1 RK 1614 <1 RK_PD7 2 &pcfg_pull_none>;
1667 }; 1615 };
1668 }; 1616 };
1669 1617
1670 uart5 { 1618 uart5 {
1671 uart5_xfer: uart5-xfe 1619 uart5_xfer: uart5-xfer {
1672 rockchip,pins 1620 rockchip,pins =
1673 <3 RK 1621 <3 RK_PA2 4 &pcfg_pull_up>,
1674 <3 RK 1622 <3 RK_PA1 4 &pcfg_pull_up>;
1675 }; 1623 };
1676 1624
1677 uart5_cts: uart5-cts 1625 uart5_cts: uart5-cts {
1678 rockchip,pins 1626 rockchip,pins =
1679 <3 RK 1627 <3 RK_PA3 4 &pcfg_pull_none>;
1680 }; 1628 };
1681 1629
1682 uart5_rts: uart5-rts 1630 uart5_rts: uart5-rts {
1683 rockchip,pins 1631 rockchip,pins =
1684 <3 RK 1632 <3 RK_PA5 4 &pcfg_pull_none>;
1685 }; 1633 };
1686 }; 1634 };
1687 1635
1688 spi0 { 1636 spi0 {
1689 spi0_clk: spi0-clk { 1637 spi0_clk: spi0-clk {
1690 rockchip,pins 1638 rockchip,pins =
1691 <1 RK 1639 <1 RK_PB7 3 &pcfg_pull_up_4ma>;
1692 }; 1640 };
1693 1641
1694 spi0_csn: spi0-csn { 1642 spi0_csn: spi0-csn {
1695 rockchip,pins 1643 rockchip,pins =
1696 <1 RK 1644 <1 RK_PB6 3 &pcfg_pull_up_4ma>;
1697 }; 1645 };
1698 1646
1699 spi0_miso: spi0-miso 1647 spi0_miso: spi0-miso {
1700 rockchip,pins 1648 rockchip,pins =
1701 <1 RK 1649 <1 RK_PB5 3 &pcfg_pull_up_4ma>;
1702 }; 1650 };
1703 1651
1704 spi0_mosi: spi0-mosi 1652 spi0_mosi: spi0-mosi {
1705 rockchip,pins 1653 rockchip,pins =
1706 <1 RK 1654 <1 RK_PB4 3 &pcfg_pull_up_4ma>;
1707 }; 1655 };
1708 1656
1709 spi0_clk_hs: spi0-clk 1657 spi0_clk_hs: spi0-clk-hs {
1710 rockchip,pins 1658 rockchip,pins =
1711 <1 RK 1659 <1 RK_PB7 3 &pcfg_pull_up_8ma>;
1712 }; 1660 };
1713 1661
1714 spi0_miso_hs: spi0-mi 1662 spi0_miso_hs: spi0-miso-hs {
1715 rockchip,pins 1663 rockchip,pins =
1716 <1 RK 1664 <1 RK_PB5 3 &pcfg_pull_up_8ma>;
1717 }; 1665 };
1718 1666
1719 spi0_mosi_hs: spi0-mo 1667 spi0_mosi_hs: spi0-mosi-hs {
1720 rockchip,pins 1668 rockchip,pins =
1721 <1 RK 1669 <1 RK_PB4 3 &pcfg_pull_up_8ma>;
1722 }; 1670 };
1723 }; 1671 };
1724 1672
1725 spi1 { 1673 spi1 {
1726 spi1_clk: spi1-clk { 1674 spi1_clk: spi1-clk {
1727 rockchip,pins 1675 rockchip,pins =
1728 <3 RK 1676 <3 RK_PB7 4 &pcfg_pull_up_4ma>;
1729 }; 1677 };
1730 1678
1731 spi1_csn0: spi1-csn0 1679 spi1_csn0: spi1-csn0 {
1732 rockchip,pins 1680 rockchip,pins =
1733 <3 RK 1681 <3 RK_PB1 4 &pcfg_pull_up_4ma>;
1734 }; 1682 };
1735 1683
1736 spi1_csn1: spi1-csn1 1684 spi1_csn1: spi1-csn1 {
1737 rockchip,pins 1685 rockchip,pins =
1738 <3 RK 1686 <3 RK_PB2 2 &pcfg_pull_up_4ma>;
1739 }; 1687 };
1740 1688
1741 spi1_miso: spi1-miso 1689 spi1_miso: spi1-miso {
1742 rockchip,pins 1690 rockchip,pins =
1743 <3 RK 1691 <3 RK_PB6 4 &pcfg_pull_up_4ma>;
1744 }; 1692 };
1745 1693
1746 spi1_mosi: spi1-mosi 1694 spi1_mosi: spi1-mosi {
1747 rockchip,pins 1695 rockchip,pins =
1748 <3 RK 1696 <3 RK_PB4 4 &pcfg_pull_up_4ma>;
1749 }; 1697 };
1750 1698
1751 spi1_clk_hs: spi1-clk 1699 spi1_clk_hs: spi1-clk-hs {
1752 rockchip,pins 1700 rockchip,pins =
1753 <3 RK 1701 <3 RK_PB7 4 &pcfg_pull_up_8ma>;
1754 }; 1702 };
1755 1703
1756 spi1_miso_hs: spi1-mi 1704 spi1_miso_hs: spi1-miso-hs {
1757 rockchip,pins 1705 rockchip,pins =
1758 <3 RK 1706 <3 RK_PB6 4 &pcfg_pull_up_8ma>;
1759 }; 1707 };
1760 1708
1761 spi1_mosi_hs: spi1-mo 1709 spi1_mosi_hs: spi1-mosi-hs {
1762 rockchip,pins 1710 rockchip,pins =
1763 <3 RK 1711 <3 RK_PB4 4 &pcfg_pull_up_8ma>;
1764 }; 1712 };
1765 }; 1713 };
1766 1714
1767 pdm { 1715 pdm {
1768 pdm_clk0m0: pdm-clk0m 1716 pdm_clk0m0: pdm-clk0m0 {
1769 rockchip,pins 1717 rockchip,pins =
1770 <3 RK 1718 <3 RK_PC6 2 &pcfg_pull_none>;
1771 }; 1719 };
1772 1720
1773 pdm_clk0m1: pdm-clk0m 1721 pdm_clk0m1: pdm-clk0m1 {
1774 rockchip,pins 1722 rockchip,pins =
1775 <2 RK 1723 <2 RK_PC6 1 &pcfg_pull_none>;
1776 }; 1724 };
1777 1725
1778 pdm_clk1: pdm-clk1 { 1726 pdm_clk1: pdm-clk1 {
1779 rockchip,pins 1727 rockchip,pins =
1780 <3 RK 1728 <3 RK_PC7 2 &pcfg_pull_none>;
1781 }; 1729 };
1782 1730
1783 pdm_sdi0m0: pdm-sdi0m 1731 pdm_sdi0m0: pdm-sdi0m0 {
1784 rockchip,pins 1732 rockchip,pins =
1785 <3 RK 1733 <3 RK_PD3 2 &pcfg_pull_none>;
1786 }; 1734 };
1787 1735
1788 pdm_sdi0m1: pdm-sdi0m 1736 pdm_sdi0m1: pdm-sdi0m1 {
1789 rockchip,pins 1737 rockchip,pins =
1790 <2 RK 1738 <2 RK_PC5 2 &pcfg_pull_none>;
1791 }; 1739 };
1792 1740
1793 pdm_sdi1: pdm-sdi1 { 1741 pdm_sdi1: pdm-sdi1 {
1794 rockchip,pins 1742 rockchip,pins =
1795 <3 RK 1743 <3 RK_PD0 2 &pcfg_pull_none>;
1796 }; 1744 };
1797 1745
1798 pdm_sdi2: pdm-sdi2 { 1746 pdm_sdi2: pdm-sdi2 {
1799 rockchip,pins 1747 rockchip,pins =
1800 <3 RK 1748 <3 RK_PD1 2 &pcfg_pull_none>;
1801 }; 1749 };
1802 1750
1803 pdm_sdi3: pdm-sdi3 { 1751 pdm_sdi3: pdm-sdi3 {
1804 rockchip,pins 1752 rockchip,pins =
1805 <3 RK 1753 <3 RK_PD2 2 &pcfg_pull_none>;
1806 }; 1754 };
1807 1755
1808 pdm_clk0m0_sleep: pdm 1756 pdm_clk0m0_sleep: pdm-clk0m0-sleep {
1809 rockchip,pins 1757 rockchip,pins =
1810 <3 RK 1758 <3 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>;
1811 }; 1759 };
1812 1760
1813 pdm_clk0m_sleep1: pdm 1761 pdm_clk0m_sleep1: pdm-clk0m1-sleep {
1814 rockchip,pins 1762 rockchip,pins =
1815 <2 RK 1763 <2 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>;
1816 }; 1764 };
1817 1765
1818 pdm_clk1_sleep: pdm-c 1766 pdm_clk1_sleep: pdm-clk1-sleep {
1819 rockchip,pins 1767 rockchip,pins =
1820 <3 RK 1768 <3 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>;
1821 }; 1769 };
1822 1770
1823 pdm_sdi0m0_sleep: pdm 1771 pdm_sdi0m0_sleep: pdm-sdi0m0-sleep {
1824 rockchip,pins 1772 rockchip,pins =
1825 <3 RK 1773 <3 RK_PD3 RK_FUNC_GPIO &pcfg_input_high>;
1826 }; 1774 };
1827 1775
1828 pdm_sdi0m1_sleep: pdm 1776 pdm_sdi0m1_sleep: pdm-sdi0m1-sleep {
1829 rockchip,pins 1777 rockchip,pins =
1830 <2 RK 1778 <2 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>;
1831 }; 1779 };
1832 1780
1833 pdm_sdi1_sleep: pdm-s 1781 pdm_sdi1_sleep: pdm-sdi1-sleep {
1834 rockchip,pins 1782 rockchip,pins =
1835 <3 RK 1783 <3 RK_PD0 RK_FUNC_GPIO &pcfg_input_high>;
1836 }; 1784 };
1837 1785
1838 pdm_sdi2_sleep: pdm-s 1786 pdm_sdi2_sleep: pdm-sdi2-sleep {
1839 rockchip,pins 1787 rockchip,pins =
1840 <3 RK 1788 <3 RK_PD1 RK_FUNC_GPIO &pcfg_input_high>;
1841 }; 1789 };
1842 1790
1843 pdm_sdi3_sleep: pdm-s 1791 pdm_sdi3_sleep: pdm-sdi3-sleep {
1844 rockchip,pins 1792 rockchip,pins =
1845 <3 RK 1793 <3 RK_PD2 RK_FUNC_GPIO &pcfg_input_high>;
1846 }; 1794 };
1847 }; 1795 };
1848 1796
1849 i2s0 { 1797 i2s0 {
1850 i2s0_8ch_mclk: i2s0-8 1798 i2s0_8ch_mclk: i2s0-8ch-mclk {
1851 rockchip,pins 1799 rockchip,pins =
1852 <3 RK 1800 <3 RK_PC1 2 &pcfg_pull_none>;
1853 }; 1801 };
1854 1802
1855 i2s0_8ch_sclktx: i2s0 1803 i2s0_8ch_sclktx: i2s0-8ch-sclktx {
1856 rockchip,pins 1804 rockchip,pins =
1857 <3 RK 1805 <3 RK_PC3 2 &pcfg_pull_none>;
1858 }; 1806 };
1859 1807
1860 i2s0_8ch_sclkrx: i2s0 1808 i2s0_8ch_sclkrx: i2s0-8ch-sclkrx {
1861 rockchip,pins 1809 rockchip,pins =
1862 <3 RK 1810 <3 RK_PB4 2 &pcfg_pull_none>;
1863 }; 1811 };
1864 1812
1865 i2s0_8ch_lrcktx: i2s0 1813 i2s0_8ch_lrcktx: i2s0-8ch-lrcktx {
1866 rockchip,pins 1814 rockchip,pins =
1867 <3 RK 1815 <3 RK_PC2 2 &pcfg_pull_none>;
1868 }; 1816 };
1869 1817
1870 i2s0_8ch_lrckrx: i2s0 1818 i2s0_8ch_lrckrx: i2s0-8ch-lrckrx {
1871 rockchip,pins 1819 rockchip,pins =
1872 <3 RK 1820 <3 RK_PB5 2 &pcfg_pull_none>;
1873 }; 1821 };
1874 1822
1875 i2s0_8ch_sdo0: i2s0-8 1823 i2s0_8ch_sdo0: i2s0-8ch-sdo0 {
1876 rockchip,pins 1824 rockchip,pins =
1877 <3 RK 1825 <3 RK_PC4 2 &pcfg_pull_none>;
1878 }; 1826 };
1879 1827
1880 i2s0_8ch_sdo1: i2s0-8 1828 i2s0_8ch_sdo1: i2s0-8ch-sdo1 {
1881 rockchip,pins 1829 rockchip,pins =
1882 <3 RK 1830 <3 RK_PC0 2 &pcfg_pull_none>;
1883 }; 1831 };
1884 1832
1885 i2s0_8ch_sdo2: i2s0-8 1833 i2s0_8ch_sdo2: i2s0-8ch-sdo2 {
1886 rockchip,pins 1834 rockchip,pins =
1887 <3 RK 1835 <3 RK_PB7 2 &pcfg_pull_none>;
1888 }; 1836 };
1889 1837
1890 i2s0_8ch_sdo3: i2s0-8 1838 i2s0_8ch_sdo3: i2s0-8ch-sdo3 {
1891 rockchip,pins 1839 rockchip,pins =
1892 <3 RK 1840 <3 RK_PB6 2 &pcfg_pull_none>;
1893 }; 1841 };
1894 1842
1895 i2s0_8ch_sdi0: i2s0-8 1843 i2s0_8ch_sdi0: i2s0-8ch-sdi0 {
1896 rockchip,pins 1844 rockchip,pins =
1897 <3 RK 1845 <3 RK_PC5 2 &pcfg_pull_none>;
1898 }; 1846 };
1899 1847
1900 i2s0_8ch_sdi1: i2s0-8 1848 i2s0_8ch_sdi1: i2s0-8ch-sdi1 {
1901 rockchip,pins 1849 rockchip,pins =
1902 <3 RK 1850 <3 RK_PB3 2 &pcfg_pull_none>;
1903 }; 1851 };
1904 1852
1905 i2s0_8ch_sdi2: i2s0-8 1853 i2s0_8ch_sdi2: i2s0-8ch-sdi2 {
1906 rockchip,pins 1854 rockchip,pins =
1907 <3 RK 1855 <3 RK_PB1 2 &pcfg_pull_none>;
1908 }; 1856 };
1909 1857
1910 i2s0_8ch_sdi3: i2s0-8 1858 i2s0_8ch_sdi3: i2s0-8ch-sdi3 {
1911 rockchip,pins 1859 rockchip,pins =
1912 <3 RK 1860 <3 RK_PB0 2 &pcfg_pull_none>;
1913 }; 1861 };
1914 }; 1862 };
1915 1863
1916 i2s1 { 1864 i2s1 {
1917 i2s1_2ch_mclk: i2s1-2 1865 i2s1_2ch_mclk: i2s1-2ch-mclk {
1918 rockchip,pins 1866 rockchip,pins =
1919 <2 RK 1867 <2 RK_PC3 1 &pcfg_pull_none>;
1920 }; 1868 };
1921 1869
1922 i2s1_2ch_sclk: i2s1-2 1870 i2s1_2ch_sclk: i2s1-2ch-sclk {
1923 rockchip,pins 1871 rockchip,pins =
1924 <2 RK 1872 <2 RK_PC2 1 &pcfg_pull_none>;
1925 }; 1873 };
1926 1874
1927 i2s1_2ch_lrck: i2s1-2 1875 i2s1_2ch_lrck: i2s1-2ch-lrck {
1928 rockchip,pins 1876 rockchip,pins =
1929 <2 RK 1877 <2 RK_PC1 1 &pcfg_pull_none>;
1930 }; 1878 };
1931 1879
1932 i2s1_2ch_sdi: i2s1-2c 1880 i2s1_2ch_sdi: i2s1-2ch-sdi {
1933 rockchip,pins 1881 rockchip,pins =
1934 <2 RK 1882 <2 RK_PC5 1 &pcfg_pull_none>;
1935 }; 1883 };
1936 1884
1937 i2s1_2ch_sdo: i2s1-2c 1885 i2s1_2ch_sdo: i2s1-2ch-sdo {
1938 rockchip,pins 1886 rockchip,pins =
1939 <2 RK 1887 <2 RK_PC4 1 &pcfg_pull_none>;
1940 }; 1888 };
1941 }; 1889 };
1942 1890
1943 i2s2 { 1891 i2s2 {
1944 i2s2_2ch_mclk: i2s2-2 1892 i2s2_2ch_mclk: i2s2-2ch-mclk {
1945 rockchip,pins 1893 rockchip,pins =
1946 <3 RK 1894 <3 RK_PA1 2 &pcfg_pull_none>;
1947 }; 1895 };
1948 1896
1949 i2s2_2ch_sclk: i2s2-2 1897 i2s2_2ch_sclk: i2s2-2ch-sclk {
1950 rockchip,pins 1898 rockchip,pins =
1951 <3 RK 1899 <3 RK_PA2 2 &pcfg_pull_none>;
1952 }; 1900 };
1953 1901
1954 i2s2_2ch_lrck: i2s2-2 1902 i2s2_2ch_lrck: i2s2-2ch-lrck {
1955 rockchip,pins 1903 rockchip,pins =
1956 <3 RK 1904 <3 RK_PA3 2 &pcfg_pull_none>;
1957 }; 1905 };
1958 1906
1959 i2s2_2ch_sdi: i2s2-2c 1907 i2s2_2ch_sdi: i2s2-2ch-sdi {
1960 rockchip,pins 1908 rockchip,pins =
1961 <3 RK 1909 <3 RK_PA5 2 &pcfg_pull_none>;
1962 }; 1910 };
1963 1911
1964 i2s2_2ch_sdo: i2s2-2c 1912 i2s2_2ch_sdo: i2s2-2ch-sdo {
1965 rockchip,pins 1913 rockchip,pins =
1966 <3 RK 1914 <3 RK_PA7 2 &pcfg_pull_none>;
1967 }; 1915 };
1968 }; 1916 };
1969 1917
1970 sdmmc { 1918 sdmmc {
1971 sdmmc_clk: sdmmc-clk 1919 sdmmc_clk: sdmmc-clk {
1972 rockchip,pins 1920 rockchip,pins =
1973 <1 RK 1921 <1 RK_PD6 1 &pcfg_pull_none_8ma>;
1974 }; 1922 };
1975 1923
1976 sdmmc_cmd: sdmmc-cmd 1924 sdmmc_cmd: sdmmc-cmd {
1977 rockchip,pins 1925 rockchip,pins =
1978 <1 RK 1926 <1 RK_PD7 1 &pcfg_pull_up_8ma>;
1979 }; 1927 };
1980 1928
1981 sdmmc_det: sdmmc-det 1929 sdmmc_det: sdmmc-det {
1982 rockchip,pins 1930 rockchip,pins =
1983 <0 RK 1931 <0 RK_PA3 1 &pcfg_pull_up_8ma>;
1984 }; 1932 };
1985 1933
1986 sdmmc_bus1: sdmmc-bus 1934 sdmmc_bus1: sdmmc-bus1 {
1987 rockchip,pins 1935 rockchip,pins =
1988 <1 RK 1936 <1 RK_PD2 1 &pcfg_pull_up_8ma>;
1989 }; 1937 };
1990 1938
1991 sdmmc_bus4: sdmmc-bus 1939 sdmmc_bus4: sdmmc-bus4 {
1992 rockchip,pins 1940 rockchip,pins =
1993 <1 RK 1941 <1 RK_PD2 1 &pcfg_pull_up_8ma>,
1994 <1 RK 1942 <1 RK_PD3 1 &pcfg_pull_up_8ma>,
1995 <1 RK 1943 <1 RK_PD4 1 &pcfg_pull_up_8ma>,
1996 <1 RK 1944 <1 RK_PD5 1 &pcfg_pull_up_8ma>;
1997 }; 1945 };
1998 }; 1946 };
1999 1947
2000 sdio { 1948 sdio {
2001 sdio_clk: sdio-clk { 1949 sdio_clk: sdio-clk {
2002 rockchip,pins 1950 rockchip,pins =
2003 <1 RK 1951 <1 RK_PC5 1 &pcfg_pull_none>;
2004 }; 1952 };
2005 1953
2006 sdio_cmd: sdio-cmd { 1954 sdio_cmd: sdio-cmd {
2007 rockchip,pins 1955 rockchip,pins =
2008 <1 RK 1956 <1 RK_PC4 1 &pcfg_pull_up>;
2009 }; 1957 };
2010 1958
2011 sdio_bus4: sdio-bus4 1959 sdio_bus4: sdio-bus4 {
2012 rockchip,pins 1960 rockchip,pins =
2013 <1 RK 1961 <1 RK_PC6 1 &pcfg_pull_up>,
2014 <1 RK 1962 <1 RK_PC7 1 &pcfg_pull_up>,
2015 <1 RK 1963 <1 RK_PD0 1 &pcfg_pull_up>,
2016 <1 RK 1964 <1 RK_PD1 1 &pcfg_pull_up>;
2017 }; 1965 };
2018 }; 1966 };
2019 1967
2020 emmc { 1968 emmc {
2021 emmc_clk: emmc-clk { 1969 emmc_clk: emmc-clk {
2022 rockchip,pins 1970 rockchip,pins =
2023 <1 RK 1971 <1 RK_PB1 2 &pcfg_pull_none_8ma>;
2024 }; 1972 };
2025 1973
2026 emmc_cmd: emmc-cmd { 1974 emmc_cmd: emmc-cmd {
2027 rockchip,pins 1975 rockchip,pins =
2028 <1 RK 1976 <1 RK_PB2 2 &pcfg_pull_up_8ma>;
2029 }; 1977 };
2030 1978
2031 emmc_rstnout: emmc-rs 1979 emmc_rstnout: emmc-rstnout {
2032 rockchip,pins 1980 rockchip,pins =
2033 <1 RK 1981 <1 RK_PB3 2 &pcfg_pull_none>;
2034 }; 1982 };
2035 1983
2036 emmc_bus1: emmc-bus1 1984 emmc_bus1: emmc-bus1 {
2037 rockchip,pins 1985 rockchip,pins =
2038 <1 RK 1986 <1 RK_PA0 2 &pcfg_pull_up_8ma>;
2039 }; 1987 };
2040 1988
2041 emmc_bus4: emmc-bus4 1989 emmc_bus4: emmc-bus4 {
2042 rockchip,pins 1990 rockchip,pins =
2043 <1 RK 1991 <1 RK_PA0 2 &pcfg_pull_up_8ma>,
2044 <1 RK 1992 <1 RK_PA1 2 &pcfg_pull_up_8ma>,
2045 <1 RK 1993 <1 RK_PA2 2 &pcfg_pull_up_8ma>,
2046 <1 RK 1994 <1 RK_PA3 2 &pcfg_pull_up_8ma>;
2047 }; 1995 };
2048 1996
2049 emmc_bus8: emmc-bus8 1997 emmc_bus8: emmc-bus8 {
2050 rockchip,pins 1998 rockchip,pins =
2051 <1 RK 1999 <1 RK_PA0 2 &pcfg_pull_up_8ma>,
2052 <1 RK 2000 <1 RK_PA1 2 &pcfg_pull_up_8ma>,
2053 <1 RK 2001 <1 RK_PA2 2 &pcfg_pull_up_8ma>,
2054 <1 RK 2002 <1 RK_PA3 2 &pcfg_pull_up_8ma>,
2055 <1 RK 2003 <1 RK_PA4 2 &pcfg_pull_up_8ma>,
2056 <1 RK 2004 <1 RK_PA5 2 &pcfg_pull_up_8ma>,
2057 <1 RK 2005 <1 RK_PA6 2 &pcfg_pull_up_8ma>,
2058 <1 RK 2006 <1 RK_PA7 2 &pcfg_pull_up_8ma>;
2059 }; 2007 };
2060 }; 2008 };
2061 2009
2062 flash { 2010 flash {
2063 flash_cs0: flash-cs0 2011 flash_cs0: flash-cs0 {
2064 rockchip,pins 2012 rockchip,pins =
2065 <1 RK 2013 <1 RK_PB0 1 &pcfg_pull_none>;
2066 }; 2014 };
2067 2015
2068 flash_rdy: flash-rdy 2016 flash_rdy: flash-rdy {
2069 rockchip,pins 2017 rockchip,pins =
2070 <1 RK 2018 <1 RK_PB1 1 &pcfg_pull_none>;
2071 }; 2019 };
2072 2020
2073 flash_dqs: flash-dqs 2021 flash_dqs: flash-dqs {
2074 rockchip,pins 2022 rockchip,pins =
2075 <1 RK 2023 <1 RK_PB2 1 &pcfg_pull_none>;
2076 }; 2024 };
2077 2025
2078 flash_ale: flash-ale 2026 flash_ale: flash-ale {
2079 rockchip,pins 2027 rockchip,pins =
2080 <1 RK 2028 <1 RK_PB3 1 &pcfg_pull_none>;
2081 }; 2029 };
2082 2030
2083 flash_cle: flash-cle 2031 flash_cle: flash-cle {
2084 rockchip,pins 2032 rockchip,pins =
2085 <1 RK 2033 <1 RK_PB4 1 &pcfg_pull_none>;
2086 }; 2034 };
2087 2035
2088 flash_wrn: flash-wrn 2036 flash_wrn: flash-wrn {
2089 rockchip,pins 2037 rockchip,pins =
2090 <1 RK 2038 <1 RK_PB5 1 &pcfg_pull_none>;
2091 }; 2039 };
2092 2040
2093 flash_csl: flash-csl 2041 flash_csl: flash-csl {
2094 rockchip,pins 2042 rockchip,pins =
2095 <1 RK 2043 <1 RK_PB6 1 &pcfg_pull_none>;
2096 }; 2044 };
2097 2045
2098 flash_rdn: flash-rdn 2046 flash_rdn: flash-rdn {
2099 rockchip,pins 2047 rockchip,pins =
2100 <1 RK 2048 <1 RK_PB7 1 &pcfg_pull_none>;
2101 }; 2049 };
2102 2050
2103 flash_bus8: flash-bus 2051 flash_bus8: flash-bus8 {
2104 rockchip,pins 2052 rockchip,pins =
2105 <1 RK 2053 <1 RK_PA0 1 &pcfg_pull_up_12ma>,
2106 <1 RK 2054 <1 RK_PA1 1 &pcfg_pull_up_12ma>,
2107 <1 RK 2055 <1 RK_PA2 1 &pcfg_pull_up_12ma>,
2108 <1 RK 2056 <1 RK_PA3 1 &pcfg_pull_up_12ma>,
2109 <1 RK 2057 <1 RK_PA4 1 &pcfg_pull_up_12ma>,
2110 <1 RK 2058 <1 RK_PA5 1 &pcfg_pull_up_12ma>,
2111 <1 RK 2059 <1 RK_PA6 1 &pcfg_pull_up_12ma>,
2112 <1 RK 2060 <1 RK_PA7 1 &pcfg_pull_up_12ma>;
2113 }; 2061 };
2114 }; 2062 };
2115 2063
2116 sfc { 2064 sfc {
2117 sfc_bus4: sfc-bus4 { 2065 sfc_bus4: sfc-bus4 {
2118 rockchip,pins 2066 rockchip,pins =
2119 <1 RK 2067 <1 RK_PA0 3 &pcfg_pull_none>,
2120 <1 RK 2068 <1 RK_PA1 3 &pcfg_pull_none>,
2121 <1 RK 2069 <1 RK_PA2 3 &pcfg_pull_none>,
2122 <1 RK 2070 <1 RK_PA3 3 &pcfg_pull_none>;
2123 }; 2071 };
2124 2072
2125 sfc_bus2: sfc-bus2 { 2073 sfc_bus2: sfc-bus2 {
2126 rockchip,pins 2074 rockchip,pins =
2127 <1 RK 2075 <1 RK_PA0 3 &pcfg_pull_none>,
2128 <1 RK 2076 <1 RK_PA1 3 &pcfg_pull_none>;
2129 }; 2077 };
2130 2078
2131 sfc_cs0: sfc-cs0 { 2079 sfc_cs0: sfc-cs0 {
2132 rockchip,pins 2080 rockchip,pins =
2133 <1 RK 2081 <1 RK_PA4 3 &pcfg_pull_none>;
2134 }; 2082 };
2135 2083
2136 sfc_clk: sfc-clk { 2084 sfc_clk: sfc-clk {
2137 rockchip,pins 2085 rockchip,pins =
2138 <1 RK 2086 <1 RK_PB1 3 &pcfg_pull_none>;
2139 }; 2087 };
2140 }; 2088 };
2141 2089
2142 lcdc { 2090 lcdc {
2143 lcdc_rgb_dclk_pin: lc 2091 lcdc_rgb_dclk_pin: lcdc-rgb-dclk-pin {
2144 rockchip,pins 2092 rockchip,pins =
2145 <3 RK 2093 <3 RK_PA0 1 &pcfg_pull_none_12ma>;
2146 }; 2094 };
2147 2095
2148 lcdc_rgb_m0_hsync_pin 2096 lcdc_rgb_m0_hsync_pin: lcdc-rgb-m0-hsync-pin {
2149 rockchip,pins 2097 rockchip,pins =
2150 <3 RK 2098 <3 RK_PA1 1 &pcfg_pull_none_12ma>;
2151 }; 2099 };
2152 2100
2153 lcdc_rgb_m0_vsync_pin 2101 lcdc_rgb_m0_vsync_pin: lcdc-rgb-m0-vsync-pin {
2154 rockchip,pins 2102 rockchip,pins =
2155 <3 RK 2103 <3 RK_PA2 1 &pcfg_pull_none_12ma>;
2156 }; 2104 };
2157 2105
2158 lcdc_rgb_m0_den_pin: 2106 lcdc_rgb_m0_den_pin: lcdc-rgb-m0-den-pin {
2159 rockchip,pins 2107 rockchip,pins =
2160 <3 RK 2108 <3 RK_PA3 1 &pcfg_pull_none_12ma>;
2161 }; 2109 };
2162 2110
2163 lcdc_rgb888_m0_data_p 2111 lcdc_rgb888_m0_data_pins: lcdc-rgb888-m0-data-pins {
2164 rockchip,pins 2112 rockchip,pins =
2165 <3 RK 2113 <3 RK_PA7 1 &pcfg_pull_none_8ma>, /* lcdc_d3 */
2166 <3 RK 2114 <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */
2167 <3 RK 2115 <3 RK_PA5 1 &pcfg_pull_none_8ma>, /* lcdc_d1 */
2168 <3 RK 2116 <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */
2169 <3 RK 2117 <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */
2170 <3 RK 2118 <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */
2171 <3 RK 2119 <3 RK_PB1 1 &pcfg_pull_none_8ma>, /* lcdc_d5 */
2172 <3 RK 2120 <3 RK_PB0 1 &pcfg_pull_none_8ma>, /* lcdc_d4 */
2173 <3 RK 2121 <3 RK_PB7 1 &pcfg_pull_none_8ma>, /* lcdc_d11 */
2174 <3 RK 2122 <3 RK_PB6 1 &pcfg_pull_none_8ma>, /* lcdc_d10 */
2175 <3 RK 2123 <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */
2176 <3 RK 2124 <3 RK_PB4 1 &pcfg_pull_none_8ma>, /* lcdc_d8 */
2177 <3 RK 2125 <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */
2178 <3 RK 2126 <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */
2179 <3 RK 2127 <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */
2180 <3 RK 2128 <3 RK_PC0 1 &pcfg_pull_none_8ma>, /* lcdc_d12 */
2181 <3 RK 2129 <3 RK_PC7 1 &pcfg_pull_none_8ma>, /* lcdc_d19 */
2182 <3 RK 2130 <3 RK_PC6 1 &pcfg_pull_none_8ma>, /* lcdc_d18 */
2183 <3 RK 2131 <3 RK_PC5 1 &pcfg_pull_none_8ma>, /* lcdc_d17 */
2184 <3 RK 2132 <3 RK_PC4 1 &pcfg_pull_none_8ma>, /* lcdc_d16 */
2185 <3 RK 2133 <3 RK_PD3 1 &pcfg_pull_none_8ma>, /* lcdc_d23 */
2186 <3 RK 2134 <3 RK_PD2 1 &pcfg_pull_none_8ma>, /* lcdc_d22 */
2187 <3 RK 2135 <3 RK_PD1 1 &pcfg_pull_none_8ma>, /* lcdc_d21 */
2188 <3 RK 2136 <3 RK_PD0 1 &pcfg_pull_none_8ma>; /* lcdc_d20 */
2189 }; 2137 };
2190 2138
2191 lcdc_rgb666_m0_data_p 2139 lcdc_rgb666_m0_data_pins: lcdc-rgb666-m0-data-pins {
2192 rockchip,pins 2140 rockchip,pins =
2193 <3 RK 2141 <3 RK_PA7 1 &pcfg_pull_none_8ma>, /* lcdc_d3 */
2194 <3 RK 2142 <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */
2195 <3 RK 2143 <3 RK_PA5 1 &pcfg_pull_none_8ma>, /* lcdc_d1 */
2196 <3 RK 2144 <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */
2197 <3 RK 2145 <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */
2198 <3 RK 2146 <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */
2199 <3 RK 2147 <3 RK_PB1 1 &pcfg_pull_none_8ma>, /* lcdc_d5 */
2200 <3 RK 2148 <3 RK_PB0 1 &pcfg_pull_none_8ma>, /* lcdc_d4 */
2201 <3 RK 2149 <3 RK_PB7 1 &pcfg_pull_none_8ma>, /* lcdc_d11 */
2202 <3 RK 2150 <3 RK_PB6 1 &pcfg_pull_none_8ma>, /* lcdc_d10 */
2203 <3 RK 2151 <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */
2204 <3 RK 2152 <3 RK_PB4 1 &pcfg_pull_none_8ma>, /* lcdc_d8 */
2205 <3 RK 2153 <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */
2206 <3 RK 2154 <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */
2207 <3 RK 2155 <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */
2208 <3 RK 2156 <3 RK_PC0 1 &pcfg_pull_none_8ma>, /* lcdc_d12 */
2209 <3 RK 2157 <3 RK_PC5 1 &pcfg_pull_none_8ma>, /* lcdc_d17 */
2210 <3 RK 2158 <3 RK_PC4 1 &pcfg_pull_none_8ma>; /* lcdc_d16 */
2211 }; 2159 };
2212 2160
2213 lcdc_rgb565_m0_data_p 2161 lcdc_rgb565_m0_data_pins: lcdc-rgb565-m0-data-pins {
2214 rockchip,pins 2162 rockchip,pins =
2215 <3 RK 2163 <3 RK_PA7 1 &pcfg_pull_none_8ma>, /* lcdc_d3 */
2216 <3 RK 2164 <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */
2217 <3 RK 2165 <3 RK_PA5 1 &pcfg_pull_none_8ma>, /* lcdc_d1 */
2218 <3 RK 2166 <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */
2219 <3 RK 2167 <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */
2220 <3 RK 2168 <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */
2221 <3 RK 2169 <3 RK_PB1 1 &pcfg_pull_none_8ma>, /* lcdc_d5 */
2222 <3 RK 2170 <3 RK_PB0 1 &pcfg_pull_none_8ma>, /* lcdc_d4 */
2223 <3 RK 2171 <3 RK_PB7 1 &pcfg_pull_none_8ma>, /* lcdc_d11 */
2224 <3 RK 2172 <3 RK_PB6 1 &pcfg_pull_none_8ma>, /* lcdc_d10 */
2225 <3 RK 2173 <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */
2226 <3 RK 2174 <3 RK_PB4 1 &pcfg_pull_none_8ma>, /* lcdc_d8 */
2227 <3 RK 2175 <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */
2228 <3 RK 2176 <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */
2229 <3 RK 2177 <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */
2230 <3 RK 2178 <3 RK_PC0 1 &pcfg_pull_none_8ma>; /* lcdc_d12 */
2231 }; 2179 };
2232 2180
2233 lcdc_rgb888_m1_data_p 2181 lcdc_rgb888_m1_data_pins: lcdc-rgb888-m1-data-pins {
2234 rockchip,pins 2182 rockchip,pins =
2235 <3 RK 2183 <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */
2236 <3 RK 2184 <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */
2237 <3 RK 2185 <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */
2238 <3 RK 2186 <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */
2239 <3 RK 2187 <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */
2240 <3 RK 2188 <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */
2241 <3 RK 2189 <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */
2242 <3 RK 2190 <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */
2243 <3 RK 2191 <3 RK_PC0 1 &pcfg_pull_none_8ma>, /* lcdc_d12 */
2244 <3 RK 2192 <3 RK_PC7 1 &pcfg_pull_none_8ma>, /* lcdc_d19 */
2245 <3 RK 2193 <3 RK_PC6 1 &pcfg_pull_none_8ma>, /* lcdc_d18 */
2246 <3 RK 2194 <3 RK_PC5 1 &pcfg_pull_none_8ma>, /* lcdc_d17 */
2247 <3 RK 2195 <3 RK_PC4 1 &pcfg_pull_none_8ma>, /* lcdc_d16 */
2248 <3 RK 2196 <3 RK_PD3 1 &pcfg_pull_none_8ma>, /* lcdc_d23 */
2249 <3 RK 2197 <3 RK_PD2 1 &pcfg_pull_none_8ma>, /* lcdc_d22 */
2250 <3 RK 2198 <3 RK_PD1 1 &pcfg_pull_none_8ma>, /* lcdc_d21 */
2251 <3 RK 2199 <3 RK_PD0 1 &pcfg_pull_none_8ma>; /* lcdc_d20 */
2252 }; 2200 };
2253 2201
2254 lcdc_rgb666_m1_data_p 2202 lcdc_rgb666_m1_data_pins: lcdc-rgb666-m1-data-pins {
2255 rockchip,pins 2203 rockchip,pins =
2256 <3 RK 2204 <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */
2257 <3 RK 2205 <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */
2258 <3 RK 2206 <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */
2259 <3 RK 2207 <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */
2260 <3 RK 2208 <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */
2261 <3 RK 2209 <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */
2262 <3 RK 2210 <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */
2263 <3 RK 2211 <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */
2264 <3 RK 2212 <3 RK_PC0 1 &pcfg_pull_none_8ma>, /* lcdc_d12 */
2265 <3 RK 2213 <3 RK_PC5 1 &pcfg_pull_none_8ma>, /* lcdc_d17 */
2266 <3 RK 2214 <3 RK_PC4 1 &pcfg_pull_none_8ma>; /* lcdc_d16 */
2267 }; 2215 };
2268 2216
2269 lcdc_rgb565_m1_data_p 2217 lcdc_rgb565_m1_data_pins: lcdc-rgb565-m1-data-pins {
2270 rockchip,pins 2218 rockchip,pins =
2271 <3 RK 2219 <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */
2272 <3 RK 2220 <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */
2273 <3 RK 2221 <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */
2274 <3 RK 2222 <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */
2275 <3 RK 2223 <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */
2276 <3 RK 2224 <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */
2277 <3 RK 2225 <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */
2278 <3 RK 2226 <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */
2279 <3 RK 2227 <3 RK_PC0 1 &pcfg_pull_none_8ma>; /* lcdc_d12 */
2280 }; 2228 };
2281 }; 2229 };
2282 2230
2283 pwm0 { 2231 pwm0 {
2284 pwm0_pin: pwm0-pin { 2232 pwm0_pin: pwm0-pin {
2285 rockchip,pins 2233 rockchip,pins =
2286 <0 RK 2234 <0 RK_PB7 1 &pcfg_pull_none>;
2287 }; 2235 };
2288 }; 2236 };
2289 2237
2290 pwm1 { 2238 pwm1 {
2291 pwm1_pin: pwm1-pin { 2239 pwm1_pin: pwm1-pin {
2292 rockchip,pins 2240 rockchip,pins =
2293 <0 RK 2241 <0 RK_PC0 1 &pcfg_pull_none>;
2294 }; 2242 };
2295 }; 2243 };
2296 2244
2297 pwm2 { 2245 pwm2 {
2298 pwm2_pin: pwm2-pin { 2246 pwm2_pin: pwm2-pin {
2299 rockchip,pins 2247 rockchip,pins =
2300 <2 RK 2248 <2 RK_PB5 1 &pcfg_pull_none>;
2301 }; 2249 };
2302 }; 2250 };
2303 2251
2304 pwm3 { 2252 pwm3 {
2305 pwm3_pin: pwm3-pin { 2253 pwm3_pin: pwm3-pin {
2306 rockchip,pins 2254 rockchip,pins =
2307 <0 RK 2255 <0 RK_PC1 1 &pcfg_pull_none>;
2308 }; 2256 };
2309 }; 2257 };
2310 2258
2311 pwm4 { 2259 pwm4 {
2312 pwm4_pin: pwm4-pin { 2260 pwm4_pin: pwm4-pin {
2313 rockchip,pins 2261 rockchip,pins =
2314 <3 RK 2262 <3 RK_PC2 3 &pcfg_pull_none>;
2315 }; 2263 };
2316 }; 2264 };
2317 2265
2318 pwm5 { 2266 pwm5 {
2319 pwm5_pin: pwm5-pin { 2267 pwm5_pin: pwm5-pin {
2320 rockchip,pins 2268 rockchip,pins =
2321 <3 RK 2269 <3 RK_PC3 3 &pcfg_pull_none>;
2322 }; 2270 };
2323 }; 2271 };
2324 2272
2325 pwm6 { 2273 pwm6 {
2326 pwm6_pin: pwm6-pin { 2274 pwm6_pin: pwm6-pin {
2327 rockchip,pins 2275 rockchip,pins =
2328 <3 RK 2276 <3 RK_PC4 3 &pcfg_pull_none>;
2329 }; 2277 };
2330 }; 2278 };
2331 2279
2332 pwm7 { 2280 pwm7 {
2333 pwm7_pin: pwm7-pin { 2281 pwm7_pin: pwm7-pin {
2334 rockchip,pins 2282 rockchip,pins =
2335 <3 RK 2283 <3 RK_PC5 3 &pcfg_pull_none>;
2336 }; 2284 };
2337 }; 2285 };
2338 2286
2339 gmac { 2287 gmac {
2340 rmii_pins: rmii-pins 2288 rmii_pins: rmii-pins {
2341 rockchip,pins 2289 rockchip,pins =
2342 <2 RK 2290 <2 RK_PA0 2 &pcfg_pull_none_12ma>, /* mac_txen */
2343 <2 RK 2291 <2 RK_PA1 2 &pcfg_pull_none_12ma>, /* mac_txd1 */
2344 <2 RK 2292 <2 RK_PA2 2 &pcfg_pull_none_12ma>, /* mac_txd0 */
2345 <2 RK 2293 <2 RK_PA3 2 &pcfg_pull_none>, /* mac_rxd0 */
2346 <2 RK 2294 <2 RK_PA4 2 &pcfg_pull_none>, /* mac_rxd1 */
2347 <2 RK 2295 <2 RK_PA5 2 &pcfg_pull_none>, /* mac_rxer */
2348 <2 RK 2296 <2 RK_PA6 2 &pcfg_pull_none>, /* mac_rxdv */
2349 <2 RK 2297 <2 RK_PA7 2 &pcfg_pull_none>, /* mac_mdio */
2350 <2 RK 2298 <2 RK_PB1 2 &pcfg_pull_none>; /* mac_mdc */
2351 }; 2299 };
2352 2300
2353 mac_refclk_12ma: mac- 2301 mac_refclk_12ma: mac-refclk-12ma {
2354 rockchip,pins 2302 rockchip,pins =
2355 <2 RK 2303 <2 RK_PB2 2 &pcfg_pull_none_12ma>;
2356 }; 2304 };
2357 2305
2358 mac_refclk: mac-refcl 2306 mac_refclk: mac-refclk {
2359 rockchip,pins 2307 rockchip,pins =
2360 <2 RK 2308 <2 RK_PB2 2 &pcfg_pull_none>;
2361 }; 2309 };
2362 }; 2310 };
2363 2311
2364 cif-m0 { 2312 cif-m0 {
2365 cif_clkout_m0: cif-cl 2313 cif_clkout_m0: cif-clkout-m0 {
2366 rockchip,pins 2314 rockchip,pins =
2367 <2 RK 2315 <2 RK_PB3 1 &pcfg_pull_none>;
2368 }; 2316 };
2369 2317
2370 dvp_d2d9_m0: dvp-d2d9 2318 dvp_d2d9_m0: dvp-d2d9-m0 {
2371 rockchip,pins 2319 rockchip,pins =
2372 <2 RK 2320 <2 RK_PA0 1 &pcfg_pull_none>, /* cif_data2 */
2373 <2 RK 2321 <2 RK_PA1 1 &pcfg_pull_none>, /* cif_data3 */
2374 <2 RK 2322 <2 RK_PA2 1 &pcfg_pull_none>, /* cif_data4 */
2375 <2 RK 2323 <2 RK_PA3 1 &pcfg_pull_none>, /* cif_data5 */
2376 <2 RK 2324 <2 RK_PA4 1 &pcfg_pull_none>, /* cif_data6 */
2377 <2 RK 2325 <2 RK_PA5 1 &pcfg_pull_none>, /* cif_data7 */
2378 <2 RK 2326 <2 RK_PA6 1 &pcfg_pull_none>, /* cif_data8 */
2379 <2 RK 2327 <2 RK_PA7 1 &pcfg_pull_none>, /* cif_data9 */
2380 <2 RK 2328 <2 RK_PB0 1 &pcfg_pull_none>, /* cif_sync */
2381 <2 RK 2329 <2 RK_PB1 1 &pcfg_pull_none>, /* cif_href */
2382 <2 RK 2330 <2 RK_PB2 1 &pcfg_pull_none>, /* cif_clkin */
2383 <2 RK 2331 <2 RK_PB3 1 &pcfg_pull_none>; /* cif_clkout */
2384 }; 2332 };
2385 2333
2386 dvp_d0d1_m0: dvp-d0d1 2334 dvp_d0d1_m0: dvp-d0d1-m0 {
2387 rockchip,pins 2335 rockchip,pins =
2388 <2 RK 2336 <2 RK_PB4 1 &pcfg_pull_none>, /* cif_data0 */
2389 <2 RK 2337 <2 RK_PB6 1 &pcfg_pull_none>; /* cif_data1 */
2390 }; 2338 };
2391 2339
2392 dvp_d10d11_m0:d10-d11 2340 dvp_d10d11_m0:d10-d11-m0 {
2393 rockchip,pins 2341 rockchip,pins =
2394 <2 RK 2342 <2 RK_PB7 1 &pcfg_pull_none>, /* cif_data10 */
2395 <2 RK 2343 <2 RK_PC0 1 &pcfg_pull_none>; /* cif_data11 */
2396 }; 2344 };
2397 }; 2345 };
2398 2346
2399 cif-m1 { 2347 cif-m1 {
2400 cif_clkout_m1: cif-cl 2348 cif_clkout_m1: cif-clkout-m1 {
2401 rockchip,pins 2349 rockchip,pins =
2402 <3 RK 2350 <3 RK_PD0 3 &pcfg_pull_none>;
2403 }; 2351 };
2404 2352
2405 dvp_d2d9_m1: dvp-d2d9 2353 dvp_d2d9_m1: dvp-d2d9-m1 {
2406 rockchip,pins 2354 rockchip,pins =
2407 <3 RK 2355 <3 RK_PA3 3 &pcfg_pull_none>, /* cif_data2 */
2408 <3 RK 2356 <3 RK_PA5 3 &pcfg_pull_none>, /* cif_data3 */
2409 <3 RK 2357 <3 RK_PA7 3 &pcfg_pull_none>, /* cif_data4 */
2410 <3 RK 2358 <3 RK_PB0 3 &pcfg_pull_none>, /* cif_data5 */
2411 <3 RK 2359 <3 RK_PB1 3 &pcfg_pull_none>, /* cif_data6 */
2412 <3 RK 2360 <3 RK_PB4 3 &pcfg_pull_none>, /* cif_data7 */
2413 <3 RK 2361 <3 RK_PB6 3 &pcfg_pull_none>, /* cif_data8 */
2414 <3 RK 2362 <3 RK_PB7 3 &pcfg_pull_none>, /* cif_data9 */
2415 <3 RK 2363 <3 RK_PD1 3 &pcfg_pull_none>, /* cif_sync */
2416 <3 RK 2364 <3 RK_PD2 3 &pcfg_pull_none>, /* cif_href */
2417 <3 RK 2365 <3 RK_PD3 3 &pcfg_pull_none>, /* cif_clkin */
2418 <3 RK 2366 <3 RK_PD0 3 &pcfg_pull_none>; /* cif_clkout */
2419 }; 2367 };
2420 2368
2421 dvp_d0d1_m1: dvp-d0d1 2369 dvp_d0d1_m1: dvp-d0d1-m1 {
2422 rockchip,pins 2370 rockchip,pins =
2423 <3 RK 2371 <3 RK_PA1 3 &pcfg_pull_none>, /* cif_data0 */
2424 <3 RK 2372 <3 RK_PA2 3 &pcfg_pull_none>; /* cif_data1 */
2425 }; 2373 };
2426 2374
2427 dvp_d10d11_m1:d10-d11 2375 dvp_d10d11_m1:d10-d11-m1 {
2428 rockchip,pins 2376 rockchip,pins =
2429 <3 RK 2377 <3 RK_PC6 3 &pcfg_pull_none>, /* cif_data10 */
2430 <3 RK 2378 <3 RK_PC7 3 &pcfg_pull_none>; /* cif_data11 */
2431 }; 2379 };
2432 }; 2380 };
2433 2381
2434 isp { 2382 isp {
2435 isp_prelight: isp-pre 2383 isp_prelight: isp-prelight {
2436 rockchip,pins 2384 rockchip,pins =
2437 <3 RK 2385 <3 RK_PD1 4 &pcfg_pull_none>;
2438 }; 2386 };
2439 }; 2387 };
2440 }; 2388 };
2441 }; 2389 };
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