1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /* 2 /*
3 * Copyright (c) 2018 Fuzhou Rockchip Electron 3 * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd
4 */ 4 */
5 5
6 #include <dt-bindings/clock/px30-cru.h> 6 #include <dt-bindings/clock/px30-cru.h>
7 #include <dt-bindings/gpio/gpio.h> 7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/interrupt-controller/arm 8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/interrupt-controller/irq 9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/pinctrl/rockchip.h> 10 #include <dt-bindings/pinctrl/rockchip.h>
11 #include <dt-bindings/power/px30-power.h> 11 #include <dt-bindings/power/px30-power.h>
12 #include <dt-bindings/soc/rockchip,boot-mode.h 12 #include <dt-bindings/soc/rockchip,boot-mode.h>
13 #include <dt-bindings/thermal/thermal.h> <<
14 13
15 / { 14 / {
16 compatible = "rockchip,px30"; 15 compatible = "rockchip,px30";
17 16
18 interrupt-parent = <&gic>; 17 interrupt-parent = <&gic>;
19 #address-cells = <2>; 18 #address-cells = <2>;
20 #size-cells = <2>; 19 #size-cells = <2>;
21 20
22 aliases { 21 aliases {
>> 22 ethernet0 = &gmac;
23 i2c0 = &i2c0; 23 i2c0 = &i2c0;
24 i2c1 = &i2c1; 24 i2c1 = &i2c1;
25 i2c2 = &i2c2; 25 i2c2 = &i2c2;
26 i2c3 = &i2c3; 26 i2c3 = &i2c3;
27 serial0 = &uart0; 27 serial0 = &uart0;
28 serial1 = &uart1; 28 serial1 = &uart1;
29 serial2 = &uart2; 29 serial2 = &uart2;
30 serial3 = &uart3; 30 serial3 = &uart3;
31 serial4 = &uart4; 31 serial4 = &uart4;
32 serial5 = &uart5; 32 serial5 = &uart5;
33 spi0 = &spi0; 33 spi0 = &spi0;
34 spi1 = &spi1; 34 spi1 = &spi1;
35 }; 35 };
36 36
37 cpus { 37 cpus {
38 #address-cells = <2>; 38 #address-cells = <2>;
39 #size-cells = <0>; 39 #size-cells = <0>;
40 40
41 cpu0: cpu@0 { 41 cpu0: cpu@0 {
42 device_type = "cpu"; 42 device_type = "cpu";
43 compatible = "arm,cort 43 compatible = "arm,cortex-a35";
44 reg = <0x0 0x0>; 44 reg = <0x0 0x0>;
45 enable-method = "psci" 45 enable-method = "psci";
46 clocks = <&cru ARMCLK> 46 clocks = <&cru ARMCLK>;
47 #cooling-cells = <2>; 47 #cooling-cells = <2>;
48 cpu-idle-states = <&CP 48 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
49 dynamic-power-coeffici 49 dynamic-power-coefficient = <90>;
50 operating-points-v2 = 50 operating-points-v2 = <&cpu0_opp_table>;
51 }; 51 };
52 52
53 cpu1: cpu@1 { 53 cpu1: cpu@1 {
54 device_type = "cpu"; 54 device_type = "cpu";
55 compatible = "arm,cort 55 compatible = "arm,cortex-a35";
56 reg = <0x0 0x1>; 56 reg = <0x0 0x1>;
57 enable-method = "psci" 57 enable-method = "psci";
58 clocks = <&cru ARMCLK> 58 clocks = <&cru ARMCLK>;
59 #cooling-cells = <2>; 59 #cooling-cells = <2>;
60 cpu-idle-states = <&CP 60 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
61 dynamic-power-coeffici 61 dynamic-power-coefficient = <90>;
62 operating-points-v2 = 62 operating-points-v2 = <&cpu0_opp_table>;
63 }; 63 };
64 64
65 cpu2: cpu@2 { 65 cpu2: cpu@2 {
66 device_type = "cpu"; 66 device_type = "cpu";
67 compatible = "arm,cort 67 compatible = "arm,cortex-a35";
68 reg = <0x0 0x2>; 68 reg = <0x0 0x2>;
69 enable-method = "psci" 69 enable-method = "psci";
70 clocks = <&cru ARMCLK> 70 clocks = <&cru ARMCLK>;
71 #cooling-cells = <2>; 71 #cooling-cells = <2>;
72 cpu-idle-states = <&CP 72 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
73 dynamic-power-coeffici 73 dynamic-power-coefficient = <90>;
74 operating-points-v2 = 74 operating-points-v2 = <&cpu0_opp_table>;
75 }; 75 };
76 76
77 cpu3: cpu@3 { 77 cpu3: cpu@3 {
78 device_type = "cpu"; 78 device_type = "cpu";
79 compatible = "arm,cort 79 compatible = "arm,cortex-a35";
80 reg = <0x0 0x3>; 80 reg = <0x0 0x3>;
81 enable-method = "psci" 81 enable-method = "psci";
82 clocks = <&cru ARMCLK> 82 clocks = <&cru ARMCLK>;
83 #cooling-cells = <2>; 83 #cooling-cells = <2>;
84 cpu-idle-states = <&CP 84 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
85 dynamic-power-coeffici 85 dynamic-power-coefficient = <90>;
86 operating-points-v2 = 86 operating-points-v2 = <&cpu0_opp_table>;
87 }; 87 };
88 88
89 idle-states { 89 idle-states {
90 entry-method = "psci"; 90 entry-method = "psci";
91 91
92 CPU_SLEEP: cpu-sleep { 92 CPU_SLEEP: cpu-sleep {
93 compatible = " 93 compatible = "arm,idle-state";
94 local-timer-st 94 local-timer-stop;
95 arm,psci-suspe 95 arm,psci-suspend-param = <0x0010000>;
96 entry-latency- 96 entry-latency-us = <120>;
97 exit-latency-u 97 exit-latency-us = <250>;
98 min-residency- 98 min-residency-us = <900>;
99 }; 99 };
100 100
101 CLUSTER_SLEEP: cluster 101 CLUSTER_SLEEP: cluster-sleep {
102 compatible = " 102 compatible = "arm,idle-state";
103 local-timer-st 103 local-timer-stop;
104 arm,psci-suspe 104 arm,psci-suspend-param = <0x1010000>;
105 entry-latency- 105 entry-latency-us = <400>;
106 exit-latency-u 106 exit-latency-us = <500>;
107 min-residency- 107 min-residency-us = <2000>;
108 }; 108 };
109 }; 109 };
110 }; 110 };
111 111
112 cpu0_opp_table: opp-table-0 { !! 112 cpu0_opp_table: cpu0-opp-table {
113 compatible = "operating-points 113 compatible = "operating-points-v2";
114 opp-shared; 114 opp-shared;
115 115
>> 116 opp-408000000 {
>> 117 opp-hz = /bits/ 64 <408000000>;
>> 118 opp-microvolt = <950000 950000 1350000>;
>> 119 clock-latency-ns = <40000>;
>> 120 opp-suspend;
>> 121 };
116 opp-600000000 { 122 opp-600000000 {
117 opp-hz = /bits/ 64 <60 123 opp-hz = /bits/ 64 <600000000>;
118 opp-microvolt = <95000 124 opp-microvolt = <950000 950000 1350000>;
119 clock-latency-ns = <40 125 clock-latency-ns = <40000>;
120 opp-suspend; <<
121 }; 126 };
122 opp-816000000 { 127 opp-816000000 {
123 opp-hz = /bits/ 64 <81 128 opp-hz = /bits/ 64 <816000000>;
124 opp-microvolt = <10500 129 opp-microvolt = <1050000 1050000 1350000>;
125 clock-latency-ns = <40 130 clock-latency-ns = <40000>;
126 }; 131 };
127 opp-1008000000 { 132 opp-1008000000 {
128 opp-hz = /bits/ 64 <10 133 opp-hz = /bits/ 64 <1008000000>;
129 opp-microvolt = <11750 134 opp-microvolt = <1175000 1175000 1350000>;
130 clock-latency-ns = <40 135 clock-latency-ns = <40000>;
131 }; 136 };
132 opp-1200000000 { 137 opp-1200000000 {
133 opp-hz = /bits/ 64 <12 138 opp-hz = /bits/ 64 <1200000000>;
134 opp-microvolt = <13000 139 opp-microvolt = <1300000 1300000 1350000>;
135 clock-latency-ns = <40 140 clock-latency-ns = <40000>;
136 }; 141 };
137 opp-1296000000 { 142 opp-1296000000 {
138 opp-hz = /bits/ 64 <12 143 opp-hz = /bits/ 64 <1296000000>;
139 opp-microvolt = <13500 144 opp-microvolt = <1350000 1350000 1350000>;
140 clock-latency-ns = <40 145 clock-latency-ns = <40000>;
141 }; 146 };
142 }; 147 };
143 148
144 arm-pmu { 149 arm-pmu {
145 compatible = "arm,cortex-a35-p !! 150 compatible = "arm,cortex-a53-pmu";
146 interrupts = <GIC_SPI 100 IRQ_ 151 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
147 <GIC_SPI 101 IRQ_ 152 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
148 <GIC_SPI 102 IRQ_ 153 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
149 <GIC_SPI 103 IRQ_ 154 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
150 interrupt-affinity = <&cpu0>, 155 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
151 }; 156 };
152 157
153 display_subsystem: display-subsystem { 158 display_subsystem: display-subsystem {
154 compatible = "rockchip,display 159 compatible = "rockchip,display-subsystem";
155 ports = <&vopb_out>, <&vopl_ou 160 ports = <&vopb_out>, <&vopl_out>;
156 status = "disabled"; 161 status = "disabled";
157 }; 162 };
158 163
>> 164 firmware {
>> 165 optee {
>> 166 compatible = "linaro,optee-tz";
>> 167 method = "smc";
>> 168 };
>> 169 };
>> 170
159 gmac_clkin: external-gmac-clock { 171 gmac_clkin: external-gmac-clock {
160 compatible = "fixed-clock"; 172 compatible = "fixed-clock";
161 clock-frequency = <50000000>; 173 clock-frequency = <50000000>;
162 clock-output-names = "gmac_clk 174 clock-output-names = "gmac_clkin";
163 #clock-cells = <0>; 175 #clock-cells = <0>;
164 }; 176 };
165 177
166 psci { 178 psci {
167 compatible = "arm,psci-1.0"; 179 compatible = "arm,psci-1.0";
168 method = "smc"; 180 method = "smc";
169 }; 181 };
170 182
171 timer { 183 timer {
172 compatible = "arm,armv8-timer" 184 compatible = "arm,armv8-timer";
173 interrupts = <GIC_PPI 13 (GIC_ 185 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
174 <GIC_PPI 14 (GIC_ 186 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
175 <GIC_PPI 11 (GIC_ 187 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
176 <GIC_PPI 10 (GIC_ 188 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
177 }; 189 };
178 190
179 thermal_zones: thermal-zones { <<
180 soc_thermal: soc-thermal { <<
181 polling-delay-passive <<
182 polling-delay = <1000> <<
183 sustainable-power = <7 <<
184 thermal-sensors = <&ts <<
185 <<
186 trips { <<
187 threshold: tri <<
188 temper <<
189 hyster <<
190 type = <<
191 }; <<
192 <<
193 target: trip-p <<
194 temper <<
195 hyster <<
196 type = <<
197 }; <<
198 <<
199 soc_crit: soc- <<
200 temper <<
201 hyster <<
202 type = <<
203 }; <<
204 }; <<
205 <<
206 cooling-maps { <<
207 map0 { <<
208 trip = <<
209 coolin <<
210 contri <<
211 }; <<
212 }; <<
213 }; <<
214 <<
215 gpu_thermal: gpu-thermal { <<
216 polling-delay-passive <<
217 polling-delay = <1000> <<
218 thermal-sensors = <&ts <<
219 <<
220 trips { <<
221 gpu_threshold: <<
222 temper <<
223 hyster <<
224 type = <<
225 }; <<
226 <<
227 gpu_target: gp <<
228 temper <<
229 hyster <<
230 type = <<
231 }; <<
232 <<
233 gpu_crit: gpu- <<
234 temper <<
235 hyster <<
236 type = <<
237 }; <<
238 }; <<
239 <<
240 cooling-maps { <<
241 map0 { <<
242 trip = <<
243 coolin <<
244 }; <<
245 }; <<
246 }; <<
247 }; <<
248 <<
249 xin24m: xin24m { 191 xin24m: xin24m {
250 compatible = "fixed-clock"; 192 compatible = "fixed-clock";
251 #clock-cells = <0>; 193 #clock-cells = <0>;
252 clock-frequency = <24000000>; 194 clock-frequency = <24000000>;
253 clock-output-names = "xin24m"; 195 clock-output-names = "xin24m";
254 }; 196 };
255 197
>> 198 xin32k: xin32k {
>> 199 compatible = "fixed-clock";
>> 200 #clock-cells = <0>;
>> 201 clock-frequency = <32768>;
>> 202 clock-output-names = "xin32k";
>> 203 };
>> 204
256 pmu: power-management@ff000000 { 205 pmu: power-management@ff000000 {
257 compatible = "rockchip,px30-pm 206 compatible = "rockchip,px30-pmu", "syscon", "simple-mfd";
258 reg = <0x0 0xff000000 0x0 0x10 207 reg = <0x0 0xff000000 0x0 0x1000>;
259 208
260 power: power-controller { 209 power: power-controller {
261 compatible = "rockchip 210 compatible = "rockchip,px30-power-controller";
262 #power-domain-cells = 211 #power-domain-cells = <1>;
263 #address-cells = <1>; 212 #address-cells = <1>;
264 #size-cells = <0>; 213 #size-cells = <0>;
265 214
266 /* These power domains 215 /* These power domains are grouped by VD_LOGIC */
267 power-domain@PX30_PD_U !! 216 pd_usb@PX30_PD_USB {
268 reg = <PX30_PD 217 reg = <PX30_PD_USB>;
269 clocks = <&cru 218 clocks = <&cru HCLK_HOST>,
270 <&cru 219 <&cru HCLK_OTG>,
271 <&cru 220 <&cru SCLK_OTG_ADP>;
272 pm_qos = <&qos 221 pm_qos = <&qos_usb_host>, <&qos_usb_otg>;
273 #power-domain- <<
274 }; 222 };
275 power-domain@PX30_PD_S !! 223 pd_sdcard@PX30_PD_SDCARD {
276 reg = <PX30_PD 224 reg = <PX30_PD_SDCARD>;
277 clocks = <&cru 225 clocks = <&cru HCLK_SDMMC>,
278 <&cru 226 <&cru SCLK_SDMMC>;
279 pm_qos = <&qos 227 pm_qos = <&qos_sdmmc>;
280 #power-domain- <<
281 }; 228 };
282 power-domain@PX30_PD_G !! 229 pd_gmac@PX30_PD_GMAC {
283 reg = <PX30_PD 230 reg = <PX30_PD_GMAC>;
284 clocks = <&cru 231 clocks = <&cru ACLK_GMAC>,
285 <&cru 232 <&cru PCLK_GMAC>,
286 <&cru 233 <&cru SCLK_MAC_REF>,
287 <&cru 234 <&cru SCLK_GMAC_RX_TX>;
288 pm_qos = <&qos 235 pm_qos = <&qos_gmac>;
289 #power-domain- <<
290 }; 236 };
291 power-domain@PX30_PD_M !! 237 pd_mmc_nand@PX30_PD_MMC_NAND {
292 reg = <PX30_PD 238 reg = <PX30_PD_MMC_NAND>;
293 clocks = <&cru !! 239 clocks = <&cru HCLK_NANDC>,
294 <&cru !! 240 <&cru HCLK_EMMC>,
295 <&cru !! 241 <&cru HCLK_SDIO>,
296 <&cru !! 242 <&cru HCLK_SFC>,
297 <&cru !! 243 <&cru SCLK_EMMC>,
298 <&cru !! 244 <&cru SCLK_NANDC>,
299 <&cru !! 245 <&cru SCLK_SDIO>,
300 <&cru !! 246 <&cru SCLK_SFC>;
301 pm_qos = <&qos 247 pm_qos = <&qos_emmc>, <&qos_nand>,
302 <&qos 248 <&qos_sdio>, <&qos_sfc>;
303 #power-domain- <<
304 }; 249 };
305 power-domain@PX30_PD_V !! 250 pd_vpu@PX30_PD_VPU {
306 reg = <PX30_PD 251 reg = <PX30_PD_VPU>;
307 clocks = <&cru 252 clocks = <&cru ACLK_VPU>,
308 <&cru 253 <&cru HCLK_VPU>,
309 <&cru 254 <&cru SCLK_CORE_VPU>;
310 pm_qos = <&qos 255 pm_qos = <&qos_vpu>, <&qos_vpu_r128>;
311 #power-domain- <<
312 }; 256 };
313 power-domain@PX30_PD_V !! 257 pd_vo@PX30_PD_VO {
314 reg = <PX30_PD 258 reg = <PX30_PD_VO>;
315 clocks = <&cru 259 clocks = <&cru ACLK_RGA>,
316 <&cru 260 <&cru ACLK_VOPB>,
317 <&cru 261 <&cru ACLK_VOPL>,
318 <&cru 262 <&cru DCLK_VOPB>,
319 <&cru 263 <&cru DCLK_VOPL>,
320 <&cru 264 <&cru HCLK_RGA>,
321 <&cru 265 <&cru HCLK_VOPB>,
322 <&cru 266 <&cru HCLK_VOPL>,
323 <&cru 267 <&cru PCLK_MIPI_DSI>,
324 <&cru 268 <&cru SCLK_RGA_CORE>,
325 <&cru 269 <&cru SCLK_VOPB_PWM>;
326 pm_qos = <&qos 270 pm_qos = <&qos_rga_rd>, <&qos_rga_wr>,
327 <&qos 271 <&qos_vop_m0>, <&qos_vop_m1>;
328 #power-domain- <<
329 }; 272 };
330 power-domain@PX30_PD_V !! 273 pd_vi@PX30_PD_VI {
331 reg = <PX30_PD 274 reg = <PX30_PD_VI>;
332 clocks = <&cru 275 clocks = <&cru ACLK_CIF>,
333 <&cru 276 <&cru ACLK_ISP>,
334 <&cru 277 <&cru HCLK_CIF>,
335 <&cru 278 <&cru HCLK_ISP>,
336 <&cru 279 <&cru SCLK_ISP>;
337 pm_qos = <&qos 280 pm_qos = <&qos_isp_128>, <&qos_isp_rd>,
338 <&qos 281 <&qos_isp_wr>, <&qos_isp_m1>,
339 <&qos 282 <&qos_vip>;
340 #power-domain- <<
341 }; 283 };
342 power-domain@PX30_PD_G !! 284 pd_gpu@PX30_PD_GPU {
343 reg = <PX30_PD 285 reg = <PX30_PD_GPU>;
344 clocks = <&cru 286 clocks = <&cru SCLK_GPU>;
345 pm_qos = <&qos 287 pm_qos = <&qos_gpu>;
346 #power-domain- <<
347 }; 288 };
348 }; 289 };
349 }; 290 };
350 291
351 pmugrf: syscon@ff010000 { 292 pmugrf: syscon@ff010000 {
352 compatible = "rockchip,px30-pm 293 compatible = "rockchip,px30-pmugrf", "syscon", "simple-mfd";
353 reg = <0x0 0xff010000 0x0 0x10 294 reg = <0x0 0xff010000 0x0 0x1000>;
354 #address-cells = <1>; 295 #address-cells = <1>;
355 #size-cells = <1>; 296 #size-cells = <1>;
356 297
357 pmu_io_domains: io-domains { 298 pmu_io_domains: io-domains {
358 compatible = "rockchip 299 compatible = "rockchip,px30-pmu-io-voltage-domain";
359 status = "disabled"; 300 status = "disabled";
360 }; 301 };
361 302
362 reboot-mode { 303 reboot-mode {
363 compatible = "syscon-r 304 compatible = "syscon-reboot-mode";
364 offset = <0x200>; 305 offset = <0x200>;
365 mode-bootloader = <BOO 306 mode-bootloader = <BOOT_BL_DOWNLOAD>;
366 mode-fastboot = <BOOT_ 307 mode-fastboot = <BOOT_FASTBOOT>;
367 mode-loader = <BOOT_BL 308 mode-loader = <BOOT_BL_DOWNLOAD>;
368 mode-normal = <BOOT_NO 309 mode-normal = <BOOT_NORMAL>;
369 mode-recovery = <BOOT_ 310 mode-recovery = <BOOT_RECOVERY>;
370 }; 311 };
371 }; 312 };
372 313
373 uart0: serial@ff030000 { 314 uart0: serial@ff030000 {
374 compatible = "rockchip,px30-ua 315 compatible = "rockchip,px30-uart", "snps,dw-apb-uart";
375 reg = <0x0 0xff030000 0x0 0x10 316 reg = <0x0 0xff030000 0x0 0x100>;
376 interrupts = <GIC_SPI 15 IRQ_T 317 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
377 clocks = <&pmucru SCLK_UART0_P 318 clocks = <&pmucru SCLK_UART0_PMU>, <&pmucru PCLK_UART0_PMU>;
378 clock-names = "baudclk", "apb_ 319 clock-names = "baudclk", "apb_pclk";
379 dmas = <&dmac 0>, <&dmac 1>; 320 dmas = <&dmac 0>, <&dmac 1>;
380 dma-names = "tx", "rx"; 321 dma-names = "tx", "rx";
381 reg-shift = <2>; 322 reg-shift = <2>;
382 reg-io-width = <4>; 323 reg-io-width = <4>;
383 pinctrl-names = "default"; 324 pinctrl-names = "default";
384 pinctrl-0 = <&uart0_xfer &uart 325 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
385 status = "disabled"; 326 status = "disabled";
386 }; 327 };
387 328
388 i2s0_8ch: i2s@ff060000 { <<
389 compatible = "rockchip,px30-i2 <<
390 reg = <0x0 0xff060000 0x0 0x10 <<
391 interrupts = <GIC_SPI 12 IRQ_T <<
392 clocks = <&cru SCLK_I2S0_TX>, <<
393 clock-names = "mclk_tx", "mclk <<
394 dmas = <&dmac 16>, <&dmac 17>; <<
395 dma-names = "tx", "rx"; <<
396 rockchip,grf = <&grf>; <<
397 resets = <&cru SRST_I2S0_TX>, <<
398 reset-names = "tx-m", "rx-m"; <<
399 pinctrl-names = "default"; <<
400 pinctrl-0 = <&i2s0_8ch_sclktx <<
401 &i2s0_8ch_lrcktx <<
402 &i2s0_8ch_sdo0 &i <<
403 &i2s0_8ch_sdo1 &i <<
404 &i2s0_8ch_sdo2 &i <<
405 &i2s0_8ch_sdo3 &i <<
406 #sound-dai-cells = <0>; <<
407 status = "disabled"; <<
408 }; <<
409 <<
410 i2s1_2ch: i2s@ff070000 { 329 i2s1_2ch: i2s@ff070000 {
411 compatible = "rockchip,px30-i2 330 compatible = "rockchip,px30-i2s", "rockchip,rk3066-i2s";
412 reg = <0x0 0xff070000 0x0 0x10 331 reg = <0x0 0xff070000 0x0 0x1000>;
413 interrupts = <GIC_SPI 13 IRQ_T 332 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
414 clocks = <&cru SCLK_I2S1>, <&c 333 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1>;
415 clock-names = "i2s_clk", "i2s_ 334 clock-names = "i2s_clk", "i2s_hclk";
416 dmas = <&dmac 18>, <&dmac 19>; 335 dmas = <&dmac 18>, <&dmac 19>;
417 dma-names = "tx", "rx"; 336 dma-names = "tx", "rx";
418 pinctrl-names = "default"; 337 pinctrl-names = "default";
419 pinctrl-0 = <&i2s1_2ch_sclk &i 338 pinctrl-0 = <&i2s1_2ch_sclk &i2s1_2ch_lrck
420 &i2s1_2ch_sdi &i2 339 &i2s1_2ch_sdi &i2s1_2ch_sdo>;
421 #sound-dai-cells = <0>; 340 #sound-dai-cells = <0>;
422 status = "disabled"; 341 status = "disabled";
423 }; 342 };
424 343
425 i2s2_2ch: i2s@ff080000 { 344 i2s2_2ch: i2s@ff080000 {
426 compatible = "rockchip,px30-i2 345 compatible = "rockchip,px30-i2s", "rockchip,rk3066-i2s";
427 reg = <0x0 0xff080000 0x0 0x10 346 reg = <0x0 0xff080000 0x0 0x1000>;
428 interrupts = <GIC_SPI 14 IRQ_T 347 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
429 clocks = <&cru SCLK_I2S2>, <&c 348 clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2>;
430 clock-names = "i2s_clk", "i2s_ 349 clock-names = "i2s_clk", "i2s_hclk";
431 dmas = <&dmac 20>, <&dmac 21>; 350 dmas = <&dmac 20>, <&dmac 21>;
432 dma-names = "tx", "rx"; 351 dma-names = "tx", "rx";
433 pinctrl-names = "default"; 352 pinctrl-names = "default";
434 pinctrl-0 = <&i2s2_2ch_sclk &i 353 pinctrl-0 = <&i2s2_2ch_sclk &i2s2_2ch_lrck
435 &i2s2_2ch_sdi &i2 354 &i2s2_2ch_sdi &i2s2_2ch_sdo>;
436 #sound-dai-cells = <0>; 355 #sound-dai-cells = <0>;
437 status = "disabled"; 356 status = "disabled";
438 }; 357 };
439 358
440 gic: interrupt-controller@ff131000 { 359 gic: interrupt-controller@ff131000 {
441 compatible = "arm,gic-400"; 360 compatible = "arm,gic-400";
442 #interrupt-cells = <3>; 361 #interrupt-cells = <3>;
443 #address-cells = <0>; 362 #address-cells = <0>;
444 interrupt-controller; 363 interrupt-controller;
445 reg = <0x0 0xff131000 0 0x1000 364 reg = <0x0 0xff131000 0 0x1000>,
446 <0x0 0xff132000 0 0x2000 365 <0x0 0xff132000 0 0x2000>,
447 <0x0 0xff134000 0 0x2000 366 <0x0 0xff134000 0 0x2000>,
448 <0x0 0xff136000 0 0x2000 367 <0x0 0xff136000 0 0x2000>;
449 interrupts = <GIC_PPI 9 368 interrupts = <GIC_PPI 9
450 (GIC_CPU_MASK_SIMPLE(4) 369 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
451 }; 370 };
452 371
453 grf: syscon@ff140000 { 372 grf: syscon@ff140000 {
454 compatible = "rockchip,px30-gr 373 compatible = "rockchip,px30-grf", "syscon", "simple-mfd";
455 reg = <0x0 0xff140000 0x0 0x10 374 reg = <0x0 0xff140000 0x0 0x1000>;
456 #address-cells = <1>; 375 #address-cells = <1>;
457 #size-cells = <1>; 376 #size-cells = <1>;
458 377
459 io_domains: io-domains { 378 io_domains: io-domains {
460 compatible = "rockchip 379 compatible = "rockchip,px30-io-voltage-domain";
461 status = "disabled"; 380 status = "disabled";
462 }; 381 };
463 <<
464 lvds: lvds { <<
465 compatible = "rockchip <<
466 phys = <&dsi_dphy>; <<
467 phy-names = "dphy"; <<
468 rockchip,grf = <&grf>; <<
469 rockchip,output = "lvd <<
470 status = "disabled"; <<
471 <<
472 ports { <<
473 #address-cells <<
474 #size-cells = <<
475 <<
476 lvds_in: port@ <<
477 reg = <<
478 #addre <<
479 #size- <<
480 <<
481 lvds_v <<
482 <<
483 <<
484 }; <<
485 <<
486 lvds_v <<
487 <<
488 <<
489 }; <<
490 }; <<
491 <<
492 lvds_out: port <<
493 reg = <<
494 }; <<
495 }; <<
496 }; <<
497 }; 382 };
498 383
499 uart1: serial@ff158000 { 384 uart1: serial@ff158000 {
500 compatible = "rockchip,px30-ua 385 compatible = "rockchip,px30-uart", "snps,dw-apb-uart";
501 reg = <0x0 0xff158000 0x0 0x10 386 reg = <0x0 0xff158000 0x0 0x100>;
502 interrupts = <GIC_SPI 16 IRQ_T 387 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
503 clocks = <&cru SCLK_UART1>, <& 388 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
504 clock-names = "baudclk", "apb_ 389 clock-names = "baudclk", "apb_pclk";
505 dmas = <&dmac 2>, <&dmac 3>; 390 dmas = <&dmac 2>, <&dmac 3>;
506 dma-names = "tx", "rx"; 391 dma-names = "tx", "rx";
507 reg-shift = <2>; 392 reg-shift = <2>;
508 reg-io-width = <4>; 393 reg-io-width = <4>;
509 pinctrl-names = "default"; 394 pinctrl-names = "default";
510 pinctrl-0 = <&uart1_xfer &uart 395 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
511 status = "disabled"; 396 status = "disabled";
512 }; 397 };
513 398
514 uart2: serial@ff160000 { 399 uart2: serial@ff160000 {
515 compatible = "rockchip,px30-ua 400 compatible = "rockchip,px30-uart", "snps,dw-apb-uart";
516 reg = <0x0 0xff160000 0x0 0x10 401 reg = <0x0 0xff160000 0x0 0x100>;
517 interrupts = <GIC_SPI 17 IRQ_T 402 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
518 clocks = <&cru SCLK_UART2>, <& 403 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
519 clock-names = "baudclk", "apb_ 404 clock-names = "baudclk", "apb_pclk";
520 dmas = <&dmac 4>, <&dmac 5>; 405 dmas = <&dmac 4>, <&dmac 5>;
521 dma-names = "tx", "rx"; 406 dma-names = "tx", "rx";
522 reg-shift = <2>; 407 reg-shift = <2>;
523 reg-io-width = <4>; 408 reg-io-width = <4>;
524 pinctrl-names = "default"; 409 pinctrl-names = "default";
525 pinctrl-0 = <&uart2m0_xfer>; 410 pinctrl-0 = <&uart2m0_xfer>;
526 status = "disabled"; 411 status = "disabled";
527 }; 412 };
528 413
529 uart3: serial@ff168000 { 414 uart3: serial@ff168000 {
530 compatible = "rockchip,px30-ua 415 compatible = "rockchip,px30-uart", "snps,dw-apb-uart";
531 reg = <0x0 0xff168000 0x0 0x10 416 reg = <0x0 0xff168000 0x0 0x100>;
532 interrupts = <GIC_SPI 18 IRQ_T 417 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
533 clocks = <&cru SCLK_UART3>, <& 418 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
534 clock-names = "baudclk", "apb_ 419 clock-names = "baudclk", "apb_pclk";
535 dmas = <&dmac 6>, <&dmac 7>; 420 dmas = <&dmac 6>, <&dmac 7>;
536 dma-names = "tx", "rx"; 421 dma-names = "tx", "rx";
537 reg-shift = <2>; 422 reg-shift = <2>;
538 reg-io-width = <4>; 423 reg-io-width = <4>;
539 pinctrl-names = "default"; 424 pinctrl-names = "default";
540 pinctrl-0 = <&uart3m1_xfer &ua 425 pinctrl-0 = <&uart3m1_xfer &uart3m1_cts &uart3m1_rts>;
541 status = "disabled"; 426 status = "disabled";
542 }; 427 };
543 428
544 uart4: serial@ff170000 { 429 uart4: serial@ff170000 {
545 compatible = "rockchip,px30-ua 430 compatible = "rockchip,px30-uart", "snps,dw-apb-uart";
546 reg = <0x0 0xff170000 0x0 0x10 431 reg = <0x0 0xff170000 0x0 0x100>;
547 interrupts = <GIC_SPI 19 IRQ_T 432 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
548 clocks = <&cru SCLK_UART4>, <& 433 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
549 clock-names = "baudclk", "apb_ 434 clock-names = "baudclk", "apb_pclk";
550 dmas = <&dmac 8>, <&dmac 9>; 435 dmas = <&dmac 8>, <&dmac 9>;
551 dma-names = "tx", "rx"; 436 dma-names = "tx", "rx";
552 reg-shift = <2>; 437 reg-shift = <2>;
553 reg-io-width = <4>; 438 reg-io-width = <4>;
554 pinctrl-names = "default"; 439 pinctrl-names = "default";
555 pinctrl-0 = <&uart4_xfer &uart 440 pinctrl-0 = <&uart4_xfer &uart4_cts &uart4_rts>;
556 status = "disabled"; 441 status = "disabled";
557 }; 442 };
558 443
559 uart5: serial@ff178000 { 444 uart5: serial@ff178000 {
560 compatible = "rockchip,px30-ua 445 compatible = "rockchip,px30-uart", "snps,dw-apb-uart";
561 reg = <0x0 0xff178000 0x0 0x10 446 reg = <0x0 0xff178000 0x0 0x100>;
562 interrupts = <GIC_SPI 20 IRQ_T 447 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
563 clocks = <&cru SCLK_UART5>, <& 448 clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>;
564 clock-names = "baudclk", "apb_ 449 clock-names = "baudclk", "apb_pclk";
565 dmas = <&dmac 10>, <&dmac 11>; 450 dmas = <&dmac 10>, <&dmac 11>;
566 dma-names = "tx", "rx"; 451 dma-names = "tx", "rx";
567 reg-shift = <2>; 452 reg-shift = <2>;
568 reg-io-width = <4>; 453 reg-io-width = <4>;
569 pinctrl-names = "default"; 454 pinctrl-names = "default";
570 pinctrl-0 = <&uart5_xfer &uart 455 pinctrl-0 = <&uart5_xfer &uart5_cts &uart5_rts>;
571 status = "disabled"; 456 status = "disabled";
572 }; 457 };
573 458
574 i2c0: i2c@ff180000 { 459 i2c0: i2c@ff180000 {
575 compatible = "rockchip,px30-i2 460 compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c";
576 reg = <0x0 0xff180000 0x0 0x10 461 reg = <0x0 0xff180000 0x0 0x1000>;
577 clocks = <&cru SCLK_I2C0>, <&c !! 462 clocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>;
578 clock-names = "i2c", "pclk"; 463 clock-names = "i2c", "pclk";
579 interrupts = <GIC_SPI 7 IRQ_TY 464 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
580 pinctrl-names = "default"; 465 pinctrl-names = "default";
581 pinctrl-0 = <&i2c0_xfer>; 466 pinctrl-0 = <&i2c0_xfer>;
582 #address-cells = <1>; 467 #address-cells = <1>;
583 #size-cells = <0>; 468 #size-cells = <0>;
584 status = "disabled"; 469 status = "disabled";
585 }; 470 };
586 471
587 i2c1: i2c@ff190000 { 472 i2c1: i2c@ff190000 {
588 compatible = "rockchip,px30-i2 473 compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c";
589 reg = <0x0 0xff190000 0x0 0x10 474 reg = <0x0 0xff190000 0x0 0x1000>;
590 clocks = <&cru SCLK_I2C1>, <&c 475 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
591 clock-names = "i2c", "pclk"; 476 clock-names = "i2c", "pclk";
592 interrupts = <GIC_SPI 8 IRQ_TY 477 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
593 pinctrl-names = "default"; 478 pinctrl-names = "default";
594 pinctrl-0 = <&i2c1_xfer>; 479 pinctrl-0 = <&i2c1_xfer>;
595 #address-cells = <1>; 480 #address-cells = <1>;
596 #size-cells = <0>; 481 #size-cells = <0>;
597 status = "disabled"; 482 status = "disabled";
598 }; 483 };
599 484
600 i2c2: i2c@ff1a0000 { 485 i2c2: i2c@ff1a0000 {
601 compatible = "rockchip,px30-i2 486 compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c";
602 reg = <0x0 0xff1a0000 0x0 0x10 487 reg = <0x0 0xff1a0000 0x0 0x1000>;
603 clocks = <&cru SCLK_I2C2>, <&c 488 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
604 clock-names = "i2c", "pclk"; 489 clock-names = "i2c", "pclk";
605 interrupts = <GIC_SPI 9 IRQ_TY 490 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
606 pinctrl-names = "default"; 491 pinctrl-names = "default";
607 pinctrl-0 = <&i2c2_xfer>; 492 pinctrl-0 = <&i2c2_xfer>;
608 #address-cells = <1>; 493 #address-cells = <1>;
609 #size-cells = <0>; 494 #size-cells = <0>;
610 status = "disabled"; 495 status = "disabled";
611 }; 496 };
612 497
613 i2c3: i2c@ff1b0000 { 498 i2c3: i2c@ff1b0000 {
614 compatible = "rockchip,px30-i2 499 compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c";
615 reg = <0x0 0xff1b0000 0x0 0x10 500 reg = <0x0 0xff1b0000 0x0 0x1000>;
616 clocks = <&cru SCLK_I2C3>, <&c 501 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
617 clock-names = "i2c", "pclk"; 502 clock-names = "i2c", "pclk";
618 interrupts = <GIC_SPI 10 IRQ_T 503 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
619 pinctrl-names = "default"; 504 pinctrl-names = "default";
620 pinctrl-0 = <&i2c3_xfer>; 505 pinctrl-0 = <&i2c3_xfer>;
621 #address-cells = <1>; 506 #address-cells = <1>;
622 #size-cells = <0>; 507 #size-cells = <0>;
623 status = "disabled"; 508 status = "disabled";
624 }; 509 };
625 510
626 spi0: spi@ff1d0000 { 511 spi0: spi@ff1d0000 {
627 compatible = "rockchip,px30-sp 512 compatible = "rockchip,px30-spi", "rockchip,rk3066-spi";
628 reg = <0x0 0xff1d0000 0x0 0x10 513 reg = <0x0 0xff1d0000 0x0 0x1000>;
629 interrupts = <GIC_SPI 26 IRQ_T 514 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
630 clocks = <&cru SCLK_SPI0>, <&c 515 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
631 clock-names = "spiclk", "apb_p 516 clock-names = "spiclk", "apb_pclk";
632 dmas = <&dmac 12>, <&dmac 13>; 517 dmas = <&dmac 12>, <&dmac 13>;
633 dma-names = "tx", "rx"; 518 dma-names = "tx", "rx";
634 num-cs = <2>; <<
635 pinctrl-names = "default"; 519 pinctrl-names = "default";
636 pinctrl-0 = <&spi0_clk &spi0_c 520 pinctrl-0 = <&spi0_clk &spi0_csn &spi0_miso &spi0_mosi>;
637 #address-cells = <1>; 521 #address-cells = <1>;
638 #size-cells = <0>; 522 #size-cells = <0>;
639 status = "disabled"; 523 status = "disabled";
640 }; 524 };
641 525
642 spi1: spi@ff1d8000 { 526 spi1: spi@ff1d8000 {
643 compatible = "rockchip,px30-sp 527 compatible = "rockchip,px30-spi", "rockchip,rk3066-spi";
644 reg = <0x0 0xff1d8000 0x0 0x10 528 reg = <0x0 0xff1d8000 0x0 0x1000>;
645 interrupts = <GIC_SPI 27 IRQ_T 529 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
646 clocks = <&cru SCLK_SPI1>, <&c 530 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
647 clock-names = "spiclk", "apb_p 531 clock-names = "spiclk", "apb_pclk";
648 dmas = <&dmac 14>, <&dmac 15>; 532 dmas = <&dmac 14>, <&dmac 15>;
649 dma-names = "tx", "rx"; 533 dma-names = "tx", "rx";
650 num-cs = <2>; <<
651 pinctrl-names = "default"; 534 pinctrl-names = "default";
652 pinctrl-0 = <&spi1_clk &spi1_c 535 pinctrl-0 = <&spi1_clk &spi1_csn0 &spi1_csn1 &spi1_miso &spi1_mosi>;
653 #address-cells = <1>; 536 #address-cells = <1>;
654 #size-cells = <0>; 537 #size-cells = <0>;
655 status = "disabled"; 538 status = "disabled";
656 }; 539 };
657 540
658 wdt: watchdog@ff1e0000 { 541 wdt: watchdog@ff1e0000 {
659 compatible = "rockchip,px30-wd !! 542 compatible = "snps,dw-wdt";
660 reg = <0x0 0xff1e0000 0x0 0x10 543 reg = <0x0 0xff1e0000 0x0 0x100>;
661 clocks = <&cru PCLK_WDT_NS>; 544 clocks = <&cru PCLK_WDT_NS>;
662 interrupts = <GIC_SPI 37 IRQ_T 545 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
663 status = "disabled"; 546 status = "disabled";
664 }; 547 };
665 548
666 pwm0: pwm@ff200000 { 549 pwm0: pwm@ff200000 {
667 compatible = "rockchip,px30-pw 550 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
668 reg = <0x0 0xff200000 0x0 0x10 551 reg = <0x0 0xff200000 0x0 0x10>;
669 clocks = <&cru SCLK_PWM0>, <&c 552 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
670 clock-names = "pwm", "pclk"; 553 clock-names = "pwm", "pclk";
671 pinctrl-names = "default"; 554 pinctrl-names = "default";
672 pinctrl-0 = <&pwm0_pin>; 555 pinctrl-0 = <&pwm0_pin>;
673 #pwm-cells = <3>; 556 #pwm-cells = <3>;
674 status = "disabled"; 557 status = "disabled";
675 }; 558 };
676 559
677 pwm1: pwm@ff200010 { 560 pwm1: pwm@ff200010 {
678 compatible = "rockchip,px30-pw 561 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
679 reg = <0x0 0xff200010 0x0 0x10 562 reg = <0x0 0xff200010 0x0 0x10>;
680 clocks = <&cru SCLK_PWM0>, <&c 563 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
681 clock-names = "pwm", "pclk"; 564 clock-names = "pwm", "pclk";
682 pinctrl-names = "default"; 565 pinctrl-names = "default";
683 pinctrl-0 = <&pwm1_pin>; 566 pinctrl-0 = <&pwm1_pin>;
684 #pwm-cells = <3>; 567 #pwm-cells = <3>;
685 status = "disabled"; 568 status = "disabled";
686 }; 569 };
687 570
688 pwm2: pwm@ff200020 { 571 pwm2: pwm@ff200020 {
689 compatible = "rockchip,px30-pw 572 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
690 reg = <0x0 0xff200020 0x0 0x10 573 reg = <0x0 0xff200020 0x0 0x10>;
691 clocks = <&cru SCLK_PWM0>, <&c 574 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
692 clock-names = "pwm", "pclk"; 575 clock-names = "pwm", "pclk";
693 pinctrl-names = "default"; 576 pinctrl-names = "default";
694 pinctrl-0 = <&pwm2_pin>; 577 pinctrl-0 = <&pwm2_pin>;
695 #pwm-cells = <3>; 578 #pwm-cells = <3>;
696 status = "disabled"; 579 status = "disabled";
697 }; 580 };
698 581
699 pwm3: pwm@ff200030 { 582 pwm3: pwm@ff200030 {
700 compatible = "rockchip,px30-pw 583 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
701 reg = <0x0 0xff200030 0x0 0x10 584 reg = <0x0 0xff200030 0x0 0x10>;
702 clocks = <&cru SCLK_PWM0>, <&c 585 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
703 clock-names = "pwm", "pclk"; 586 clock-names = "pwm", "pclk";
704 pinctrl-names = "default"; 587 pinctrl-names = "default";
705 pinctrl-0 = <&pwm3_pin>; 588 pinctrl-0 = <&pwm3_pin>;
706 #pwm-cells = <3>; 589 #pwm-cells = <3>;
707 status = "disabled"; 590 status = "disabled";
708 }; 591 };
709 592
710 pwm4: pwm@ff208000 { 593 pwm4: pwm@ff208000 {
711 compatible = "rockchip,px30-pw 594 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
712 reg = <0x0 0xff208000 0x0 0x10 595 reg = <0x0 0xff208000 0x0 0x10>;
713 clocks = <&cru SCLK_PWM1>, <&c 596 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>;
714 clock-names = "pwm", "pclk"; 597 clock-names = "pwm", "pclk";
715 pinctrl-names = "default"; 598 pinctrl-names = "default";
716 pinctrl-0 = <&pwm4_pin>; 599 pinctrl-0 = <&pwm4_pin>;
717 #pwm-cells = <3>; 600 #pwm-cells = <3>;
718 status = "disabled"; 601 status = "disabled";
719 }; 602 };
720 603
721 pwm5: pwm@ff208010 { 604 pwm5: pwm@ff208010 {
722 compatible = "rockchip,px30-pw 605 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
723 reg = <0x0 0xff208010 0x0 0x10 606 reg = <0x0 0xff208010 0x0 0x10>;
724 clocks = <&cru SCLK_PWM1>, <&c 607 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>;
725 clock-names = "pwm", "pclk"; 608 clock-names = "pwm", "pclk";
726 pinctrl-names = "default"; 609 pinctrl-names = "default";
727 pinctrl-0 = <&pwm5_pin>; 610 pinctrl-0 = <&pwm5_pin>;
728 #pwm-cells = <3>; 611 #pwm-cells = <3>;
729 status = "disabled"; 612 status = "disabled";
730 }; 613 };
731 614
732 pwm6: pwm@ff208020 { 615 pwm6: pwm@ff208020 {
733 compatible = "rockchip,px30-pw 616 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
734 reg = <0x0 0xff208020 0x0 0x10 617 reg = <0x0 0xff208020 0x0 0x10>;
735 clocks = <&cru SCLK_PWM1>, <&c 618 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>;
736 clock-names = "pwm", "pclk"; 619 clock-names = "pwm", "pclk";
737 pinctrl-names = "default"; 620 pinctrl-names = "default";
738 pinctrl-0 = <&pwm6_pin>; 621 pinctrl-0 = <&pwm6_pin>;
739 #pwm-cells = <3>; 622 #pwm-cells = <3>;
740 status = "disabled"; 623 status = "disabled";
741 }; 624 };
742 625
743 pwm7: pwm@ff208030 { 626 pwm7: pwm@ff208030 {
744 compatible = "rockchip,px30-pw 627 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
745 reg = <0x0 0xff208030 0x0 0x10 628 reg = <0x0 0xff208030 0x0 0x10>;
746 clocks = <&cru SCLK_PWM1>, <&c 629 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>;
747 clock-names = "pwm", "pclk"; 630 clock-names = "pwm", "pclk";
748 pinctrl-names = "default"; 631 pinctrl-names = "default";
749 pinctrl-0 = <&pwm7_pin>; 632 pinctrl-0 = <&pwm7_pin>;
750 #pwm-cells = <3>; 633 #pwm-cells = <3>;
751 status = "disabled"; 634 status = "disabled";
752 }; 635 };
753 636
754 rktimer: timer@ff210000 { 637 rktimer: timer@ff210000 {
755 compatible = "rockchip,px30-ti 638 compatible = "rockchip,px30-timer", "rockchip,rk3288-timer";
756 reg = <0x0 0xff210000 0x0 0x10 639 reg = <0x0 0xff210000 0x0 0x1000>;
757 interrupts = <GIC_SPI 30 IRQ_T 640 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
758 clocks = <&cru PCLK_TIMER>, <& 641 clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER0>;
759 clock-names = "pclk", "timer"; 642 clock-names = "pclk", "timer";
760 }; 643 };
761 644
762 dmac: dma-controller@ff240000 { !! 645 amba {
763 compatible = "arm,pl330", "arm !! 646 compatible = "simple-bus";
764 reg = <0x0 0xff240000 0x0 0x40 !! 647 #address-cells = <2>;
765 interrupts = <GIC_SPI 1 IRQ_TY !! 648 #size-cells = <2>;
766 <GIC_SPI 2 IRQ_TY !! 649 ranges;
767 arm,pl330-periph-burst; !! 650
768 clocks = <&cru ACLK_DMAC>; !! 651 dmac: dmac@ff240000 {
769 clock-names = "apb_pclk"; !! 652 compatible = "arm,pl330", "arm,primecell";
770 #dma-cells = <1>; !! 653 reg = <0x0 0xff240000 0x0 0x4000>;
771 }; !! 654 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
772 !! 655 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
773 tsadc: tsadc@ff280000 { !! 656 clocks = <&cru ACLK_DMAC>;
774 compatible = "rockchip,px30-ts !! 657 clock-names = "apb_pclk";
775 reg = <0x0 0xff280000 0x0 0x10 !! 658 #dma-cells = <1>;
776 interrupts = <GIC_SPI 36 IRQ_T !! 659 };
777 assigned-clocks = <&cru SCLK_T <<
778 assigned-clock-rates = <50000> <<
779 clocks = <&cru SCLK_TSADC>, <& <<
780 clock-names = "tsadc", "apb_pc <<
781 resets = <&cru SRST_TSADC>; <<
782 reset-names = "tsadc-apb"; <<
783 rockchip,grf = <&grf>; <<
784 rockchip,hw-tshut-temp = <1200 <<
785 pinctrl-names = "init", "defau <<
786 pinctrl-0 = <&tsadc_otp_pin>; <<
787 pinctrl-1 = <&tsadc_otp_out>; <<
788 pinctrl-2 = <&tsadc_otp_pin>; <<
789 #thermal-sensor-cells = <1>; <<
790 status = "disabled"; <<
791 }; 660 };
792 661
793 saradc: saradc@ff288000 { 662 saradc: saradc@ff288000 {
794 compatible = "rockchip,px30-sa 663 compatible = "rockchip,px30-saradc", "rockchip,rk3399-saradc";
795 reg = <0x0 0xff288000 0x0 0x10 664 reg = <0x0 0xff288000 0x0 0x100>;
796 interrupts = <GIC_SPI 84 IRQ_T 665 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
797 #io-channel-cells = <1>; 666 #io-channel-cells = <1>;
798 clocks = <&cru SCLK_SARADC>, < 667 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
799 clock-names = "saradc", "apb_p 668 clock-names = "saradc", "apb_pclk";
800 resets = <&cru SRST_SARADC_P>; 669 resets = <&cru SRST_SARADC_P>;
801 reset-names = "saradc-apb"; 670 reset-names = "saradc-apb";
802 status = "disabled"; 671 status = "disabled";
803 }; 672 };
804 673
805 otp: nvmem@ff290000 { <<
806 compatible = "rockchip,px30-ot <<
807 reg = <0x0 0xff290000 0x0 0x40 <<
808 clocks = <&cru SCLK_OTP_USR>, <<
809 <&cru PCLK_OTP_PHY>; <<
810 clock-names = "otp", "apb_pclk <<
811 resets = <&cru SRST_OTP_PHY>; <<
812 reset-names = "phy"; <<
813 #address-cells = <1>; <<
814 #size-cells = <1>; <<
815 <<
816 /* Data cells */ <<
817 cpu_id: id@7 { <<
818 reg = <0x07 0x10>; <<
819 }; <<
820 cpu_leakage: cpu-leakage@17 { <<
821 reg = <0x17 0x1>; <<
822 }; <<
823 performance: performance@1e { <<
824 reg = <0x1e 0x1>; <<
825 bits = <4 3>; <<
826 }; <<
827 }; <<
828 <<
829 cru: clock-controller@ff2b0000 { 674 cru: clock-controller@ff2b0000 {
830 compatible = "rockchip,px30-cr 675 compatible = "rockchip,px30-cru";
831 reg = <0x0 0xff2b0000 0x0 0x10 676 reg = <0x0 0xff2b0000 0x0 0x1000>;
832 clocks = <&xin24m>, <&pmucru P <<
833 clock-names = "xin24m", "gpll" <<
834 rockchip,grf = <&grf>; 677 rockchip,grf = <&grf>;
835 #clock-cells = <1>; 678 #clock-cells = <1>;
836 #reset-cells = <1>; 679 #reset-cells = <1>;
837 680
838 assigned-clocks = <&cru PLL_NP !! 681 assigned-clocks = <&cru PLL_NPLL>;
839 <&cru ACLK_BUS_PRE>, < !! 682 assigned-clock-rates = <1188000000>;
840 <&cru HCLK_BUS_PRE>, < <<
841 <&cru PCLK_BUS_PRE>, < <<
842 <<
843 assigned-clock-rates = <118800 <<
844 <200000000>, <20000000 <<
845 <150000000>, <15000000 <<
846 <100000000>, <20000000 <<
847 }; 683 };
848 684
849 pmucru: clock-controller@ff2bc000 { 685 pmucru: clock-controller@ff2bc000 {
850 compatible = "rockchip,px30-pm 686 compatible = "rockchip,px30-pmucru";
851 reg = <0x0 0xff2bc000 0x0 0x10 687 reg = <0x0 0xff2bc000 0x0 0x1000>;
852 clocks = <&xin24m>; <<
853 clock-names = "xin24m"; <<
854 rockchip,grf = <&grf>; 688 rockchip,grf = <&grf>;
855 #clock-cells = <1>; 689 #clock-cells = <1>;
856 #reset-cells = <1>; 690 #reset-cells = <1>;
857 691
858 assigned-clocks = 692 assigned-clocks =
859 <&pmucru PLL_GPLL>, <& 693 <&pmucru PLL_GPLL>, <&pmucru PCLK_PMU_PRE>,
860 <&pmucru SCLK_WIFI_PMU !! 694 <&pmucru SCLK_WIFI_PMU>, <&cru ARMCLK>,
>> 695 <&cru ACLK_BUS_PRE>, <&cru ACLK_PERI_PRE>,
>> 696 <&cru HCLK_BUS_PRE>, <&cru HCLK_PERI_PRE>,
>> 697 <&cru PCLK_BUS_PRE>, <&cru SCLK_GPU>;
861 assigned-clock-rates = 698 assigned-clock-rates =
862 <1200000000>, <1000000 699 <1200000000>, <100000000>,
863 <26000000>; !! 700 <26000000>, <600000000>,
864 }; !! 701 <200000000>, <200000000>,
865 !! 702 <150000000>, <150000000>,
866 usb2phy_grf: syscon@ff2c0000 { !! 703 <100000000>, <200000000>;
867 compatible = "rockchip,px30-us <<
868 "simple-mfd"; <<
869 reg = <0x0 0xff2c0000 0x0 0x10 <<
870 #address-cells = <1>; <<
871 #size-cells = <1>; <<
872 <<
873 u2phy: usb2phy@100 { <<
874 compatible = "rockchip <<
875 reg = <0x100 0x20>; <<
876 clocks = <&pmucru SCLK <<
877 clock-names = "phyclk" <<
878 #clock-cells = <0>; <<
879 assigned-clocks = <&cr <<
880 assigned-clock-parents <<
881 clock-output-names = " <<
882 status = "disabled"; <<
883 <<
884 u2phy_host: host-port <<
885 #phy-cells = < <<
886 interrupts = < <<
887 interrupt-name <<
888 status = "disa <<
889 }; <<
890 <<
891 u2phy_otg: otg-port { <<
892 #phy-cells = < <<
893 interrupts = < <<
894 < <<
895 < <<
896 interrupt-name <<
897 <<
898 status = "disa <<
899 }; <<
900 }; <<
901 }; <<
902 <<
903 dsi_dphy: phy@ff2e0000 { <<
904 compatible = "rockchip,px30-ds <<
905 reg = <0x0 0xff2e0000 0x0 0x10 <<
906 clocks = <&pmucru SCLK_MIPIDSI <<
907 clock-names = "ref", "pclk"; <<
908 resets = <&cru SRST_MIPIDSIPHY <<
909 reset-names = "apb"; <<
910 #phy-cells = <0>; <<
911 power-domains = <&power PX30_P <<
912 status = "disabled"; <<
913 }; <<
914 <<
915 csi_dphy: phy@ff2f0000 { <<
916 compatible = "rockchip,px30-cs <<
917 reg = <0x0 0xff2f0000 0x0 0x40 <<
918 clocks = <&cru PCLK_MIPICSIPHY <<
919 clock-names = "pclk"; <<
920 #phy-cells = <0>; <<
921 power-domains = <&power PX30_P <<
922 resets = <&cru SRST_MIPICSIPHY <<
923 reset-names = "apb"; <<
924 rockchip,grf = <&grf>; <<
925 status = "disabled"; <<
926 }; 704 };
927 705
928 usb20_otg: usb@ff300000 { 706 usb20_otg: usb@ff300000 {
929 compatible = "rockchip,px30-us 707 compatible = "rockchip,px30-usb", "rockchip,rk3066-usb",
930 "snps,dwc2"; 708 "snps,dwc2";
931 reg = <0x0 0xff300000 0x0 0x40 709 reg = <0x0 0xff300000 0x0 0x40000>;
932 interrupts = <GIC_SPI 62 IRQ_T 710 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
933 clocks = <&cru HCLK_OTG>; 711 clocks = <&cru HCLK_OTG>;
934 clock-names = "otg"; 712 clock-names = "otg";
935 dr_mode = "otg"; 713 dr_mode = "otg";
936 g-np-tx-fifo-size = <16>; 714 g-np-tx-fifo-size = <16>;
937 g-rx-fifo-size = <280>; 715 g-rx-fifo-size = <280>;
938 g-tx-fifo-size = <256 128 128 716 g-tx-fifo-size = <256 128 128 64 32 16>;
939 phys = <&u2phy_otg>; !! 717 g-use-dma;
940 phy-names = "usb2-phy"; <<
941 power-domains = <&power PX30_P 718 power-domains = <&power PX30_PD_USB>;
942 status = "disabled"; 719 status = "disabled";
943 }; 720 };
944 721
945 usb_host0_ehci: usb@ff340000 { 722 usb_host0_ehci: usb@ff340000 {
946 compatible = "generic-ehci"; 723 compatible = "generic-ehci";
947 reg = <0x0 0xff340000 0x0 0x10 724 reg = <0x0 0xff340000 0x0 0x10000>;
948 interrupts = <GIC_SPI 60 IRQ_T 725 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
949 clocks = <&cru HCLK_HOST>; 726 clocks = <&cru HCLK_HOST>;
950 phys = <&u2phy_host>; !! 727 clock-names = "usbhost";
951 phy-names = "usb"; <<
952 power-domains = <&power PX30_P 728 power-domains = <&power PX30_PD_USB>;
953 status = "disabled"; 729 status = "disabled";
954 }; 730 };
955 731
956 usb_host0_ohci: usb@ff350000 { 732 usb_host0_ohci: usb@ff350000 {
957 compatible = "generic-ohci"; 733 compatible = "generic-ohci";
958 reg = <0x0 0xff350000 0x0 0x10 734 reg = <0x0 0xff350000 0x0 0x10000>;
959 interrupts = <GIC_SPI 61 IRQ_T 735 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
960 clocks = <&cru HCLK_HOST>; 736 clocks = <&cru HCLK_HOST>;
961 phys = <&u2phy_host>; !! 737 clock-names = "usbhost";
962 phy-names = "usb"; <<
963 power-domains = <&power PX30_P 738 power-domains = <&power PX30_PD_USB>;
964 status = "disabled"; 739 status = "disabled";
965 }; 740 };
966 741
967 gmac: ethernet@ff360000 { 742 gmac: ethernet@ff360000 {
968 compatible = "rockchip,px30-gm 743 compatible = "rockchip,px30-gmac";
969 reg = <0x0 0xff360000 0x0 0x10 744 reg = <0x0 0xff360000 0x0 0x10000>;
970 interrupts = <GIC_SPI 43 IRQ_T 745 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
971 interrupt-names = "macirq"; 746 interrupt-names = "macirq";
972 clocks = <&cru SCLK_GMAC>, <&c 747 clocks = <&cru SCLK_GMAC>, <&cru SCLK_GMAC_RX_TX>,
973 <&cru SCLK_GMAC_RX_TX 748 <&cru SCLK_GMAC_RX_TX>, <&cru SCLK_MAC_REF>,
974 <&cru SCLK_MAC_REFOUT 749 <&cru SCLK_MAC_REFOUT>, <&cru ACLK_GMAC>,
975 <&cru PCLK_GMAC>, <&c 750 <&cru PCLK_GMAC>, <&cru SCLK_GMAC_RMII>;
976 clock-names = "stmmaceth", "ma 751 clock-names = "stmmaceth", "mac_clk_rx",
977 "mac_clk_tx", "c 752 "mac_clk_tx", "clk_mac_ref",
978 "clk_mac_refout" 753 "clk_mac_refout", "aclk_mac",
979 "pclk_mac", "clk 754 "pclk_mac", "clk_mac_speed";
980 rockchip,grf = <&grf>; 755 rockchip,grf = <&grf>;
981 phy-mode = "rmii"; 756 phy-mode = "rmii";
982 pinctrl-names = "default"; 757 pinctrl-names = "default";
983 pinctrl-0 = <&rmii_pins &mac_r 758 pinctrl-0 = <&rmii_pins &mac_refclk_12ma>;
984 power-domains = <&power PX30_P 759 power-domains = <&power PX30_PD_GMAC>;
985 resets = <&cru SRST_GMAC_A>; 760 resets = <&cru SRST_GMAC_A>;
986 reset-names = "stmmaceth"; 761 reset-names = "stmmaceth";
987 status = "disabled"; 762 status = "disabled";
988 }; 763 };
989 764
990 sdmmc: mmc@ff370000 { !! 765 sdmmc: dwmmc@ff370000 {
991 compatible = "rockchip,px30-dw 766 compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc";
992 reg = <0x0 0xff370000 0x0 0x40 767 reg = <0x0 0xff370000 0x0 0x4000>;
993 interrupts = <GIC_SPI 54 IRQ_T 768 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
994 clocks = <&cru HCLK_SDMMC>, <& 769 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
995 <&cru SCLK_SDMMC_DRV> 770 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
996 clock-names = "biu", "ciu", "c !! 771 clock-names = "biu", "ciu", "ciu-drv", "ciu-sample";
997 bus-width = <4>; <<
998 fifo-depth = <0x100>; 772 fifo-depth = <0x100>;
999 max-frequency = <150000000>; 773 max-frequency = <150000000>;
1000 pinctrl-names = "default"; 774 pinctrl-names = "default";
1001 pinctrl-0 = <&sdmmc_clk &sdmm 775 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_det &sdmmc_bus4>;
1002 power-domains = <&power PX30_ 776 power-domains = <&power PX30_PD_SDCARD>;
1003 status = "disabled"; 777 status = "disabled";
1004 }; 778 };
1005 779
1006 sdio: mmc@ff380000 { !! 780 sdio: dwmmc@ff380000 {
1007 compatible = "rockchip,px30-d 781 compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc";
1008 reg = <0x0 0xff380000 0x0 0x4 782 reg = <0x0 0xff380000 0x0 0x4000>;
1009 interrupts = <GIC_SPI 55 IRQ_ 783 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
1010 clocks = <&cru HCLK_SDIO>, <& 784 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
1011 <&cru SCLK_SDIO_DRV> 785 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
1012 clock-names = "biu", "ciu", " !! 786 clock-names = "biu", "ciu", "ciu-drv", "ciu-sample";
1013 bus-width = <4>; <<
1014 fifo-depth = <0x100>; 787 fifo-depth = <0x100>;
1015 max-frequency = <150000000>; 788 max-frequency = <150000000>;
1016 pinctrl-names = "default"; 789 pinctrl-names = "default";
1017 pinctrl-0 = <&sdio_bus4 &sdio 790 pinctrl-0 = <&sdio_bus4 &sdio_cmd &sdio_clk>;
1018 power-domains = <&power PX30_ 791 power-domains = <&power PX30_PD_MMC_NAND>;
1019 status = "disabled"; 792 status = "disabled";
1020 }; 793 };
1021 794
1022 emmc: mmc@ff390000 { !! 795 emmc: dwmmc@ff390000 {
1023 compatible = "rockchip,px30-d 796 compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc";
1024 reg = <0x0 0xff390000 0x0 0x4 797 reg = <0x0 0xff390000 0x0 0x4000>;
1025 interrupts = <GIC_SPI 53 IRQ_ 798 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
1026 clocks = <&cru HCLK_EMMC>, <& 799 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
1027 <&cru SCLK_EMMC_DRV> 800 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
1028 clock-names = "biu", "ciu", " !! 801 clock-names = "biu", "ciu", "ciu-drv", "ciu-sample";
1029 bus-width = <8>; <<
1030 fifo-depth = <0x100>; 802 fifo-depth = <0x100>;
1031 max-frequency = <150000000>; 803 max-frequency = <150000000>;
1032 pinctrl-names = "default"; <<
1033 pinctrl-0 = <&emmc_clk &emmc_ <<
1034 power-domains = <&power PX30_ 804 power-domains = <&power PX30_PD_MMC_NAND>;
1035 status = "disabled"; 805 status = "disabled";
1036 }; 806 };
1037 807
1038 sfc: spi@ff3a0000 { <<
1039 compatible = "rockchip,sfc"; <<
1040 reg = <0x0 0xff3a0000 0x0 0x4 <<
1041 interrupts = <GIC_SPI 56 IRQ_ <<
1042 clocks = <&cru SCLK_SFC>, <&c <<
1043 clock-names = "clk_sfc", "hcl <<
1044 pinctrl-0 = <&sfc_clk &sfc_cs <<
1045 pinctrl-names = "default"; <<
1046 power-domains = <&power PX30_ <<
1047 status = "disabled"; <<
1048 }; <<
1049 <<
1050 nfc: nand-controller@ff3b0000 { <<
1051 compatible = "rockchip,px30-n <<
1052 reg = <0x0 0xff3b0000 0x0 0x4 <<
1053 interrupts = <GIC_SPI 57 IRQ_ <<
1054 clocks = <&cru HCLK_NANDC>, < <<
1055 clock-names = "ahb", "nfc"; <<
1056 assigned-clocks = <&cru SCLK_ <<
1057 assigned-clock-rates = <15000 <<
1058 pinctrl-names = "default"; <<
1059 pinctrl-0 = <&flash_ale &flas <<
1060 &flash_rdn &flas <<
1061 power-domains = <&power PX30_ <<
1062 status = "disabled"; <<
1063 }; <<
1064 <<
1065 gpu_opp_table: opp-table-1 { <<
1066 compatible = "operating-point <<
1067 <<
1068 opp-200000000 { <<
1069 opp-hz = /bits/ 64 <2 <<
1070 opp-microvolt = <9500 <<
1071 }; <<
1072 opp-300000000 { <<
1073 opp-hz = /bits/ 64 <3 <<
1074 opp-microvolt = <9750 <<
1075 }; <<
1076 opp-400000000 { <<
1077 opp-hz = /bits/ 64 <4 <<
1078 opp-microvolt = <1050 <<
1079 }; <<
1080 opp-480000000 { <<
1081 opp-hz = /bits/ 64 <4 <<
1082 opp-microvolt = <1125 <<
1083 }; <<
1084 }; <<
1085 <<
1086 gpu: gpu@ff400000 { <<
1087 compatible = "rockchip,px30-m <<
1088 reg = <0x0 0xff400000 0x0 0x4 <<
1089 interrupts = <GIC_SPI 47 IRQ_ <<
1090 <GIC_SPI 46 IRQ_ <<
1091 <GIC_SPI 45 IRQ_ <<
1092 interrupt-names = "job", "mmu <<
1093 clocks = <&cru SCLK_GPU>; <<
1094 #cooling-cells = <2>; <<
1095 power-domains = <&power PX30_ <<
1096 operating-points-v2 = <&gpu_o <<
1097 status = "disabled"; <<
1098 }; <<
1099 <<
1100 vpu: video-codec@ff442000 { <<
1101 compatible = "rockchip,px30-v <<
1102 reg = <0x0 0xff442000 0x0 0x8 <<
1103 interrupts = <GIC_SPI 80 IRQ_ <<
1104 <GIC_SPI 79 IRQ_ <<
1105 interrupt-names = "vepu", "vd <<
1106 clocks = <&cru ACLK_VPU>, <&c <<
1107 clock-names = "aclk", "hclk"; <<
1108 iommus = <&vpu_mmu>; <<
1109 power-domains = <&power PX30_ <<
1110 }; <<
1111 <<
1112 vpu_mmu: iommu@ff442800 { <<
1113 compatible = "rockchip,iommu" <<
1114 reg = <0x0 0xff442800 0x0 0x1 <<
1115 interrupts = <GIC_SPI 81 IRQ_ <<
1116 clocks = <&cru ACLK_VPU>, <&c <<
1117 clock-names = "aclk", "iface" <<
1118 #iommu-cells = <0>; <<
1119 power-domains = <&power PX30_ <<
1120 }; <<
1121 <<
1122 dsi: dsi@ff450000 { <<
1123 compatible = "rockchip,px30-m <<
1124 reg = <0x0 0xff450000 0x0 0x1 <<
1125 interrupts = <GIC_SPI 75 IRQ_ <<
1126 clocks = <&cru PCLK_MIPI_DSI> <<
1127 clock-names = "pclk"; <<
1128 phys = <&dsi_dphy>; <<
1129 phy-names = "dphy"; <<
1130 power-domains = <&power PX30_ <<
1131 resets = <&cru SRST_MIPIDSI_H <<
1132 reset-names = "apb"; <<
1133 rockchip,grf = <&grf>; <<
1134 #address-cells = <1>; <<
1135 #size-cells = <0>; <<
1136 status = "disabled"; <<
1137 <<
1138 ports { <<
1139 #address-cells = <1>; <<
1140 #size-cells = <0>; <<
1141 <<
1142 dsi_in: port@0 { <<
1143 reg = <0>; <<
1144 #address-cell <<
1145 #size-cells = <<
1146 <<
1147 dsi_in_vopb: <<
1148 reg = <<
1149 remot <<
1150 }; <<
1151 <<
1152 dsi_in_vopl: <<
1153 reg = <<
1154 remot <<
1155 }; <<
1156 }; <<
1157 <<
1158 dsi_out: port@1 { <<
1159 reg = <1>; <<
1160 }; <<
1161 }; <<
1162 }; <<
1163 <<
1164 vopb: vop@ff460000 { 808 vopb: vop@ff460000 {
1165 compatible = "rockchip,px30-v 809 compatible = "rockchip,px30-vop-big";
1166 reg = <0x0 0xff460000 0x0 0xe 810 reg = <0x0 0xff460000 0x0 0xefc>;
1167 interrupts = <GIC_SPI 77 IRQ_ 811 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
1168 clocks = <&cru ACLK_VOPB>, <& 812 clocks = <&cru ACLK_VOPB>, <&cru DCLK_VOPB>,
1169 <&cru HCLK_VOPB>; 813 <&cru HCLK_VOPB>;
1170 clock-names = "aclk_vop", "dc 814 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1171 resets = <&cru SRST_VOPB_A>, 815 resets = <&cru SRST_VOPB_A>, <&cru SRST_VOPB_H>, <&cru SRST_VOPB>;
1172 reset-names = "axi", "ahb", " 816 reset-names = "axi", "ahb", "dclk";
1173 iommus = <&vopb_mmu>; 817 iommus = <&vopb_mmu>;
1174 power-domains = <&power PX30_ 818 power-domains = <&power PX30_PD_VO>;
>> 819 rockchip,grf = <&grf>;
1175 status = "disabled"; 820 status = "disabled";
1176 821
1177 vopb_out: port { 822 vopb_out: port {
1178 #address-cells = <1>; 823 #address-cells = <1>;
1179 #size-cells = <0>; 824 #size-cells = <0>;
1180 <<
1181 vopb_out_dsi: endpoin <<
1182 reg = <0>; <<
1183 remote-endpoi <<
1184 }; <<
1185 <<
1186 vopb_out_lvds: endpoi <<
1187 reg = <1>; <<
1188 remote-endpoi <<
1189 }; <<
1190 }; 825 };
1191 }; 826 };
1192 827
1193 vopb_mmu: iommu@ff460f00 { 828 vopb_mmu: iommu@ff460f00 {
1194 compatible = "rockchip,iommu" 829 compatible = "rockchip,iommu";
1195 reg = <0x0 0xff460f00 0x0 0x1 830 reg = <0x0 0xff460f00 0x0 0x100>;
1196 interrupts = <GIC_SPI 77 IRQ_ 831 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
>> 832 interrupt-names = "vopb_mmu";
1197 clocks = <&cru ACLK_VOPB>, <& 833 clocks = <&cru ACLK_VOPB>, <&cru HCLK_VOPB>;
1198 clock-names = "aclk", "iface" !! 834 clock-names = "aclk", "hclk";
1199 power-domains = <&power PX30_ 835 power-domains = <&power PX30_PD_VO>;
1200 #iommu-cells = <0>; 836 #iommu-cells = <0>;
1201 status = "disabled"; 837 status = "disabled";
1202 }; 838 };
1203 839
1204 vopl: vop@ff470000 { 840 vopl: vop@ff470000 {
1205 compatible = "rockchip,px30-v 841 compatible = "rockchip,px30-vop-lit";
1206 reg = <0x0 0xff470000 0x0 0xe 842 reg = <0x0 0xff470000 0x0 0xefc>;
1207 interrupts = <GIC_SPI 78 IRQ_ 843 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
1208 clocks = <&cru ACLK_VOPL>, <& 844 clocks = <&cru ACLK_VOPL>, <&cru DCLK_VOPL>,
1209 <&cru HCLK_VOPL>; 845 <&cru HCLK_VOPL>;
1210 clock-names = "aclk_vop", "dc 846 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1211 resets = <&cru SRST_VOPL_A>, 847 resets = <&cru SRST_VOPL_A>, <&cru SRST_VOPL_H>, <&cru SRST_VOPL>;
1212 reset-names = "axi", "ahb", " 848 reset-names = "axi", "ahb", "dclk";
1213 iommus = <&vopl_mmu>; 849 iommus = <&vopl_mmu>;
1214 power-domains = <&power PX30_ 850 power-domains = <&power PX30_PD_VO>;
>> 851 rockchip,grf = <&grf>;
1215 status = "disabled"; 852 status = "disabled";
1216 853
1217 vopl_out: port { 854 vopl_out: port {
1218 #address-cells = <1>; 855 #address-cells = <1>;
1219 #size-cells = <0>; 856 #size-cells = <0>;
1220 <<
1221 vopl_out_dsi: endpoin <<
1222 reg = <0>; <<
1223 remote-endpoi <<
1224 }; <<
1225 <<
1226 vopl_out_lvds: endpoi <<
1227 reg = <1>; <<
1228 remote-endpoi <<
1229 }; <<
1230 }; 857 };
1231 }; 858 };
1232 859
1233 vopl_mmu: iommu@ff470f00 { 860 vopl_mmu: iommu@ff470f00 {
1234 compatible = "rockchip,iommu" 861 compatible = "rockchip,iommu";
1235 reg = <0x0 0xff470f00 0x0 0x1 862 reg = <0x0 0xff470f00 0x0 0x100>;
1236 interrupts = <GIC_SPI 78 IRQ_ !! 863 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
>> 864 interrupt-names = "vopl_mmu";
1237 clocks = <&cru ACLK_VOPL>, <& 865 clocks = <&cru ACLK_VOPL>, <&cru HCLK_VOPL>;
1238 clock-names = "aclk", "iface" !! 866 clock-names = "aclk", "hclk";
1239 power-domains = <&power PX30_ 867 power-domains = <&power PX30_PD_VO>;
1240 #iommu-cells = <0>; 868 #iommu-cells = <0>;
1241 status = "disabled"; 869 status = "disabled";
1242 }; 870 };
1243 871
1244 isp: isp@ff4a0000 { <<
1245 compatible = "rockchip,px30-c <<
1246 reg = <0x0 0xff4a0000 0x0 0x8 <<
1247 interrupts = <GIC_SPI 70 IRQ_ <<
1248 <GIC_SPI 73 IRQ_ <<
1249 <GIC_SPI 74 IRQ_ <<
1250 interrupt-names = "isp", "mi" <<
1251 clocks = <&cru SCLK_ISP>, <<
1252 <&cru ACLK_ISP>, <<
1253 <&cru HCLK_ISP>, <<
1254 <&cru PCLK_ISP>; <<
1255 clock-names = "isp", "aclk", <<
1256 iommus = <&isp_mmu>; <<
1257 phys = <&csi_dphy>; <<
1258 phy-names = "dphy"; <<
1259 power-domains = <&power PX30_ <<
1260 status = "disabled"; <<
1261 <<
1262 ports { <<
1263 #address-cells = <1>; <<
1264 #size-cells = <0>; <<
1265 <<
1266 port@0 { <<
1267 reg = <0>; <<
1268 #address-cell <<
1269 #size-cells = <<
1270 }; <<
1271 }; <<
1272 }; <<
1273 <<
1274 isp_mmu: iommu@ff4a8000 { <<
1275 compatible = "rockchip,iommu" <<
1276 reg = <0x0 0xff4a8000 0x0 0x1 <<
1277 interrupts = <GIC_SPI 70 IRQ_ <<
1278 clocks = <&cru ACLK_ISP>, <&c <<
1279 clock-names = "aclk", "iface" <<
1280 power-domains = <&power PX30_ <<
1281 rockchip,disable-mmu-reset; <<
1282 #iommu-cells = <0>; <<
1283 }; <<
1284 <<
1285 qos_gmac: qos@ff518000 { 872 qos_gmac: qos@ff518000 {
1286 compatible = "rockchip,px30-q !! 873 compatible = "syscon";
1287 reg = <0x0 0xff518000 0x0 0x2 874 reg = <0x0 0xff518000 0x0 0x20>;
1288 }; 875 };
1289 876
1290 qos_gpu: qos@ff520000 { 877 qos_gpu: qos@ff520000 {
1291 compatible = "rockchip,px30-q !! 878 compatible = "syscon";
1292 reg = <0x0 0xff520000 0x0 0x2 879 reg = <0x0 0xff520000 0x0 0x20>;
1293 }; 880 };
1294 881
1295 qos_sdmmc: qos@ff52c000 { 882 qos_sdmmc: qos@ff52c000 {
1296 compatible = "rockchip,px30-q !! 883 compatible = "syscon";
1297 reg = <0x0 0xff52c000 0x0 0x2 884 reg = <0x0 0xff52c000 0x0 0x20>;
1298 }; 885 };
1299 886
1300 qos_emmc: qos@ff538000 { 887 qos_emmc: qos@ff538000 {
1301 compatible = "rockchip,px30-q !! 888 compatible = "syscon";
1302 reg = <0x0 0xff538000 0x0 0x2 889 reg = <0x0 0xff538000 0x0 0x20>;
1303 }; 890 };
1304 891
1305 qos_nand: qos@ff538080 { 892 qos_nand: qos@ff538080 {
1306 compatible = "rockchip,px30-q !! 893 compatible = "syscon";
1307 reg = <0x0 0xff538080 0x0 0x2 894 reg = <0x0 0xff538080 0x0 0x20>;
1308 }; 895 };
1309 896
1310 qos_sdio: qos@ff538100 { 897 qos_sdio: qos@ff538100 {
1311 compatible = "rockchip,px30-q !! 898 compatible = "syscon";
1312 reg = <0x0 0xff538100 0x0 0x2 899 reg = <0x0 0xff538100 0x0 0x20>;
1313 }; 900 };
1314 901
1315 qos_sfc: qos@ff538180 { 902 qos_sfc: qos@ff538180 {
1316 compatible = "rockchip,px30-q !! 903 compatible = "syscon";
1317 reg = <0x0 0xff538180 0x0 0x2 904 reg = <0x0 0xff538180 0x0 0x20>;
1318 }; 905 };
1319 906
1320 qos_usb_host: qos@ff540000 { 907 qos_usb_host: qos@ff540000 {
1321 compatible = "rockchip,px30-q !! 908 compatible = "syscon";
1322 reg = <0x0 0xff540000 0x0 0x2 909 reg = <0x0 0xff540000 0x0 0x20>;
1323 }; 910 };
1324 911
1325 qos_usb_otg: qos@ff540080 { 912 qos_usb_otg: qos@ff540080 {
1326 compatible = "rockchip,px30-q !! 913 compatible = "syscon";
1327 reg = <0x0 0xff540080 0x0 0x2 914 reg = <0x0 0xff540080 0x0 0x20>;
1328 }; 915 };
1329 916
1330 qos_isp_128: qos@ff548000 { 917 qos_isp_128: qos@ff548000 {
1331 compatible = "rockchip,px30-q !! 918 compatible = "syscon";
1332 reg = <0x0 0xff548000 0x0 0x2 919 reg = <0x0 0xff548000 0x0 0x20>;
1333 }; 920 };
1334 921
1335 qos_isp_rd: qos@ff548080 { 922 qos_isp_rd: qos@ff548080 {
1336 compatible = "rockchip,px30-q !! 923 compatible = "syscon";
1337 reg = <0x0 0xff548080 0x0 0x2 924 reg = <0x0 0xff548080 0x0 0x20>;
1338 }; 925 };
1339 926
1340 qos_isp_wr: qos@ff548100 { 927 qos_isp_wr: qos@ff548100 {
1341 compatible = "rockchip,px30-q !! 928 compatible = "syscon";
1342 reg = <0x0 0xff548100 0x0 0x2 929 reg = <0x0 0xff548100 0x0 0x20>;
1343 }; 930 };
1344 931
1345 qos_isp_m1: qos@ff548180 { 932 qos_isp_m1: qos@ff548180 {
1346 compatible = "rockchip,px30-q !! 933 compatible = "syscon";
1347 reg = <0x0 0xff548180 0x0 0x2 934 reg = <0x0 0xff548180 0x0 0x20>;
1348 }; 935 };
1349 936
1350 qos_vip: qos@ff548200 { 937 qos_vip: qos@ff548200 {
1351 compatible = "rockchip,px30-q !! 938 compatible = "syscon";
1352 reg = <0x0 0xff548200 0x0 0x2 939 reg = <0x0 0xff548200 0x0 0x20>;
1353 }; 940 };
1354 941
1355 qos_rga_rd: qos@ff550000 { 942 qos_rga_rd: qos@ff550000 {
1356 compatible = "rockchip,px30-q !! 943 compatible = "syscon";
1357 reg = <0x0 0xff550000 0x0 0x2 944 reg = <0x0 0xff550000 0x0 0x20>;
1358 }; 945 };
1359 946
1360 qos_rga_wr: qos@ff550080 { 947 qos_rga_wr: qos@ff550080 {
1361 compatible = "rockchip,px30-q !! 948 compatible = "syscon";
1362 reg = <0x0 0xff550080 0x0 0x2 949 reg = <0x0 0xff550080 0x0 0x20>;
1363 }; 950 };
1364 951
1365 qos_vop_m0: qos@ff550100 { 952 qos_vop_m0: qos@ff550100 {
1366 compatible = "rockchip,px30-q !! 953 compatible = "syscon";
1367 reg = <0x0 0xff550100 0x0 0x2 954 reg = <0x0 0xff550100 0x0 0x20>;
1368 }; 955 };
1369 956
1370 qos_vop_m1: qos@ff550180 { 957 qos_vop_m1: qos@ff550180 {
1371 compatible = "rockchip,px30-q !! 958 compatible = "syscon";
1372 reg = <0x0 0xff550180 0x0 0x2 959 reg = <0x0 0xff550180 0x0 0x20>;
1373 }; 960 };
1374 961
1375 qos_vpu: qos@ff558000 { 962 qos_vpu: qos@ff558000 {
1376 compatible = "rockchip,px30-q !! 963 compatible = "syscon";
1377 reg = <0x0 0xff558000 0x0 0x2 964 reg = <0x0 0xff558000 0x0 0x20>;
1378 }; 965 };
1379 966
1380 qos_vpu_r128: qos@ff558080 { 967 qos_vpu_r128: qos@ff558080 {
1381 compatible = "rockchip,px30-q !! 968 compatible = "syscon";
1382 reg = <0x0 0xff558080 0x0 0x2 969 reg = <0x0 0xff558080 0x0 0x20>;
1383 }; 970 };
1384 971
1385 pinctrl: pinctrl { 972 pinctrl: pinctrl {
1386 compatible = "rockchip,px30-p 973 compatible = "rockchip,px30-pinctrl";
1387 rockchip,grf = <&grf>; 974 rockchip,grf = <&grf>;
1388 rockchip,pmu = <&pmugrf>; 975 rockchip,pmu = <&pmugrf>;
1389 #address-cells = <2>; 976 #address-cells = <2>;
1390 #size-cells = <2>; 977 #size-cells = <2>;
1391 ranges; 978 ranges;
1392 979
1393 gpio0: gpio@ff040000 { !! 980 gpio0: gpio0@ff040000 {
1394 compatible = "rockchi 981 compatible = "rockchip,gpio-bank";
1395 reg = <0x0 0xff040000 982 reg = <0x0 0xff040000 0x0 0x100>;
1396 interrupts = <GIC_SPI 983 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
1397 clocks = <&pmucru PCL 984 clocks = <&pmucru PCLK_GPIO0_PMU>;
1398 gpio-controller; 985 gpio-controller;
1399 #gpio-cells = <2>; 986 #gpio-cells = <2>;
1400 987
1401 interrupt-controller; 988 interrupt-controller;
1402 #interrupt-cells = <2 989 #interrupt-cells = <2>;
1403 }; 990 };
1404 991
1405 gpio1: gpio@ff250000 { !! 992 gpio1: gpio1@ff250000 {
1406 compatible = "rockchi 993 compatible = "rockchip,gpio-bank";
1407 reg = <0x0 0xff250000 994 reg = <0x0 0xff250000 0x0 0x100>;
1408 interrupts = <GIC_SPI 995 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
1409 clocks = <&cru PCLK_G 996 clocks = <&cru PCLK_GPIO1>;
1410 gpio-controller; 997 gpio-controller;
1411 #gpio-cells = <2>; 998 #gpio-cells = <2>;
1412 999
1413 interrupt-controller; 1000 interrupt-controller;
1414 #interrupt-cells = <2 1001 #interrupt-cells = <2>;
1415 }; 1002 };
1416 1003
1417 gpio2: gpio@ff260000 { !! 1004 gpio2: gpio2@ff260000 {
1418 compatible = "rockchi 1005 compatible = "rockchip,gpio-bank";
1419 reg = <0x0 0xff260000 1006 reg = <0x0 0xff260000 0x0 0x100>;
1420 interrupts = <GIC_SPI 1007 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
1421 clocks = <&cru PCLK_G 1008 clocks = <&cru PCLK_GPIO2>;
1422 gpio-controller; 1009 gpio-controller;
1423 #gpio-cells = <2>; 1010 #gpio-cells = <2>;
1424 1011
1425 interrupt-controller; 1012 interrupt-controller;
1426 #interrupt-cells = <2 1013 #interrupt-cells = <2>;
1427 }; 1014 };
1428 1015
1429 gpio3: gpio@ff270000 { !! 1016 gpio3: gpio3@ff270000 {
1430 compatible = "rockchi 1017 compatible = "rockchip,gpio-bank";
1431 reg = <0x0 0xff270000 1018 reg = <0x0 0xff270000 0x0 0x100>;
1432 interrupts = <GIC_SPI 1019 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
1433 clocks = <&cru PCLK_G 1020 clocks = <&cru PCLK_GPIO3>;
1434 gpio-controller; 1021 gpio-controller;
1435 #gpio-cells = <2>; 1022 #gpio-cells = <2>;
1436 1023
1437 interrupt-controller; 1024 interrupt-controller;
1438 #interrupt-cells = <2 1025 #interrupt-cells = <2>;
1439 }; 1026 };
1440 1027
1441 pcfg_pull_up: pcfg-pull-up { 1028 pcfg_pull_up: pcfg-pull-up {
1442 bias-pull-up; 1029 bias-pull-up;
1443 }; 1030 };
1444 1031
1445 pcfg_pull_down: pcfg-pull-dow 1032 pcfg_pull_down: pcfg-pull-down {
1446 bias-pull-down; 1033 bias-pull-down;
1447 }; 1034 };
1448 1035
1449 pcfg_pull_none: pcfg-pull-non 1036 pcfg_pull_none: pcfg-pull-none {
1450 bias-disable; 1037 bias-disable;
1451 }; 1038 };
1452 1039
1453 pcfg_pull_none_2ma: pcfg-pull 1040 pcfg_pull_none_2ma: pcfg-pull-none-2ma {
1454 bias-disable; 1041 bias-disable;
1455 drive-strength = <2>; 1042 drive-strength = <2>;
1456 }; 1043 };
1457 1044
1458 pcfg_pull_up_2ma: pcfg-pull-u 1045 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
1459 bias-pull-up; 1046 bias-pull-up;
1460 drive-strength = <2>; 1047 drive-strength = <2>;
1461 }; 1048 };
1462 1049
1463 pcfg_pull_up_4ma: pcfg-pull-u 1050 pcfg_pull_up_4ma: pcfg-pull-up-4ma {
1464 bias-pull-up; 1051 bias-pull-up;
1465 drive-strength = <4>; 1052 drive-strength = <4>;
1466 }; 1053 };
1467 1054
1468 pcfg_pull_none_4ma: pcfg-pull 1055 pcfg_pull_none_4ma: pcfg-pull-none-4ma {
1469 bias-disable; 1056 bias-disable;
1470 drive-strength = <4>; 1057 drive-strength = <4>;
1471 }; 1058 };
1472 1059
1473 pcfg_pull_down_4ma: pcfg-pull 1060 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
1474 bias-pull-down; 1061 bias-pull-down;
1475 drive-strength = <4>; 1062 drive-strength = <4>;
1476 }; 1063 };
1477 1064
1478 pcfg_pull_none_8ma: pcfg-pull 1065 pcfg_pull_none_8ma: pcfg-pull-none-8ma {
1479 bias-disable; 1066 bias-disable;
1480 drive-strength = <8>; 1067 drive-strength = <8>;
1481 }; 1068 };
1482 1069
1483 pcfg_pull_up_8ma: pcfg-pull-u 1070 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
1484 bias-pull-up; 1071 bias-pull-up;
1485 drive-strength = <8>; 1072 drive-strength = <8>;
1486 }; 1073 };
1487 1074
1488 pcfg_pull_none_12ma: pcfg-pul 1075 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1489 bias-disable; 1076 bias-disable;
1490 drive-strength = <12> 1077 drive-strength = <12>;
1491 }; 1078 };
1492 1079
1493 pcfg_pull_up_12ma: pcfg-pull- 1080 pcfg_pull_up_12ma: pcfg-pull-up-12ma {
1494 bias-pull-up; 1081 bias-pull-up;
1495 drive-strength = <12> 1082 drive-strength = <12>;
1496 }; 1083 };
1497 1084
1498 pcfg_pull_none_smt: pcfg-pull 1085 pcfg_pull_none_smt: pcfg-pull-none-smt {
1499 bias-disable; 1086 bias-disable;
1500 input-schmitt-enable; 1087 input-schmitt-enable;
1501 }; 1088 };
1502 1089
1503 pcfg_output_high: pcfg-output 1090 pcfg_output_high: pcfg-output-high {
1504 output-high; 1091 output-high;
1505 }; 1092 };
1506 1093
1507 pcfg_output_low: pcfg-output- 1094 pcfg_output_low: pcfg-output-low {
1508 output-low; 1095 output-low;
1509 }; 1096 };
1510 1097
1511 pcfg_input_high: pcfg-input-h 1098 pcfg_input_high: pcfg-input-high {
1512 bias-pull-up; 1099 bias-pull-up;
1513 input-enable; 1100 input-enable;
1514 }; 1101 };
1515 1102
1516 pcfg_input: pcfg-input { 1103 pcfg_input: pcfg-input {
1517 input-enable; 1104 input-enable;
1518 }; 1105 };
1519 1106
1520 i2c0 { 1107 i2c0 {
1521 i2c0_xfer: i2c0-xfer 1108 i2c0_xfer: i2c0-xfer {
1522 rockchip,pins 1109 rockchip,pins =
1523 <0 RK 1110 <0 RK_PB0 1 &pcfg_pull_none_smt>,
1524 <0 RK 1111 <0 RK_PB1 1 &pcfg_pull_none_smt>;
1525 }; 1112 };
1526 }; 1113 };
1527 1114
1528 i2c1 { 1115 i2c1 {
1529 i2c1_xfer: i2c1-xfer 1116 i2c1_xfer: i2c1-xfer {
1530 rockchip,pins 1117 rockchip,pins =
1531 <0 RK 1118 <0 RK_PC2 1 &pcfg_pull_none_smt>,
1532 <0 RK 1119 <0 RK_PC3 1 &pcfg_pull_none_smt>;
1533 }; 1120 };
1534 }; 1121 };
1535 1122
1536 i2c2 { 1123 i2c2 {
1537 i2c2_xfer: i2c2-xfer 1124 i2c2_xfer: i2c2-xfer {
1538 rockchip,pins 1125 rockchip,pins =
1539 <2 RK 1126 <2 RK_PB7 2 &pcfg_pull_none_smt>,
1540 <2 RK 1127 <2 RK_PC0 2 &pcfg_pull_none_smt>;
1541 }; 1128 };
1542 }; 1129 };
1543 1130
1544 i2c3 { 1131 i2c3 {
1545 i2c3_xfer: i2c3-xfer 1132 i2c3_xfer: i2c3-xfer {
1546 rockchip,pins 1133 rockchip,pins =
1547 <1 RK 1134 <1 RK_PB4 4 &pcfg_pull_none_smt>,
1548 <1 RK 1135 <1 RK_PB5 4 &pcfg_pull_none_smt>;
1549 }; 1136 };
1550 }; 1137 };
1551 1138
1552 tsadc { 1139 tsadc {
1553 tsadc_otp_pin: tsadc- !! 1140 tsadc_otp_gpio: tsadc-otp-gpio {
1554 rockchip,pins 1141 rockchip,pins =
1555 <0 RK 1142 <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
1556 }; 1143 };
1557 1144
1558 tsadc_otp_out: tsadc- 1145 tsadc_otp_out: tsadc-otp-out {
1559 rockchip,pins 1146 rockchip,pins =
1560 <0 RK 1147 <0 RK_PA6 1 &pcfg_pull_none>;
1561 }; 1148 };
1562 }; 1149 };
1563 1150
1564 uart0 { 1151 uart0 {
1565 uart0_xfer: uart0-xfe 1152 uart0_xfer: uart0-xfer {
1566 rockchip,pins 1153 rockchip,pins =
1567 <0 RK 1154 <0 RK_PB2 1 &pcfg_pull_up>,
1568 <0 RK 1155 <0 RK_PB3 1 &pcfg_pull_up>;
1569 }; 1156 };
1570 1157
1571 uart0_cts: uart0-cts 1158 uart0_cts: uart0-cts {
1572 rockchip,pins 1159 rockchip,pins =
1573 <0 RK 1160 <0 RK_PB4 1 &pcfg_pull_none>;
1574 }; 1161 };
1575 1162
1576 uart0_rts: uart0-rts 1163 uart0_rts: uart0-rts {
1577 rockchip,pins 1164 rockchip,pins =
1578 <0 RK 1165 <0 RK_PB5 1 &pcfg_pull_none>;
1579 }; 1166 };
>> 1167
>> 1168 uart0_rts_gpio: uart0-rts-gpio {
>> 1169 rockchip,pins =
>> 1170 <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
>> 1171 };
1580 }; 1172 };
1581 1173
1582 uart1 { 1174 uart1 {
1583 uart1_xfer: uart1-xfe 1175 uart1_xfer: uart1-xfer {
1584 rockchip,pins 1176 rockchip,pins =
1585 <1 RK 1177 <1 RK_PC1 1 &pcfg_pull_up>,
1586 <1 RK 1178 <1 RK_PC0 1 &pcfg_pull_up>;
1587 }; 1179 };
1588 1180
1589 uart1_cts: uart1-cts 1181 uart1_cts: uart1-cts {
1590 rockchip,pins 1182 rockchip,pins =
1591 <1 RK 1183 <1 RK_PC2 1 &pcfg_pull_none>;
1592 }; 1184 };
1593 1185
1594 uart1_rts: uart1-rts 1186 uart1_rts: uart1-rts {
1595 rockchip,pins 1187 rockchip,pins =
1596 <1 RK 1188 <1 RK_PC3 1 &pcfg_pull_none>;
1597 }; 1189 };
>> 1190
>> 1191 uart1_rts_gpio: uart1-rts-gpio {
>> 1192 rockchip,pins =
>> 1193 <1 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>;
>> 1194 };
1598 }; 1195 };
1599 1196
1600 uart2-m0 { 1197 uart2-m0 {
1601 uart2m0_xfer: uart2m0 1198 uart2m0_xfer: uart2m0-xfer {
1602 rockchip,pins 1199 rockchip,pins =
1603 <1 RK 1200 <1 RK_PD2 2 &pcfg_pull_up>,
1604 <1 RK 1201 <1 RK_PD3 2 &pcfg_pull_up>;
1605 }; 1202 };
1606 }; 1203 };
1607 1204
1608 uart2-m1 { 1205 uart2-m1 {
1609 uart2m1_xfer: uart2m1 1206 uart2m1_xfer: uart2m1-xfer {
1610 rockchip,pins 1207 rockchip,pins =
1611 <2 RK 1208 <2 RK_PB4 2 &pcfg_pull_up>,
1612 <2 RK 1209 <2 RK_PB6 2 &pcfg_pull_up>;
1613 }; 1210 };
1614 }; 1211 };
1615 1212
1616 uart3-m0 { 1213 uart3-m0 {
1617 uart3m0_xfer: uart3m0 1214 uart3m0_xfer: uart3m0-xfer {
1618 rockchip,pins 1215 rockchip,pins =
1619 <0 RK 1216 <0 RK_PC0 2 &pcfg_pull_up>,
1620 <0 RK 1217 <0 RK_PC1 2 &pcfg_pull_up>;
1621 }; 1218 };
1622 1219
1623 uart3m0_cts: uart3m0- 1220 uart3m0_cts: uart3m0-cts {
1624 rockchip,pins 1221 rockchip,pins =
1625 <0 RK 1222 <0 RK_PC2 2 &pcfg_pull_none>;
1626 }; 1223 };
1627 1224
1628 uart3m0_rts: uart3m0- 1225 uart3m0_rts: uart3m0-rts {
1629 rockchip,pins 1226 rockchip,pins =
1630 <0 RK 1227 <0 RK_PC3 2 &pcfg_pull_none>;
1631 }; 1228 };
>> 1229
>> 1230 uart3m0_rts_gpio: uart3m0-rts-gpio {
>> 1231 rockchip,pins =
>> 1232 <0 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>;
>> 1233 };
1632 }; 1234 };
1633 1235
1634 uart3-m1 { 1236 uart3-m1 {
1635 uart3m1_xfer: uart3m1 1237 uart3m1_xfer: uart3m1-xfer {
1636 rockchip,pins 1238 rockchip,pins =
1637 <1 RK 1239 <1 RK_PB6 2 &pcfg_pull_up>,
1638 <1 RK 1240 <1 RK_PB7 2 &pcfg_pull_up>;
1639 }; 1241 };
1640 1242
1641 uart3m1_cts: uart3m1- 1243 uart3m1_cts: uart3m1-cts {
1642 rockchip,pins 1244 rockchip,pins =
1643 <1 RK 1245 <1 RK_PB4 2 &pcfg_pull_none>;
1644 }; 1246 };
1645 1247
1646 uart3m1_rts: uart3m1- 1248 uart3m1_rts: uart3m1-rts {
1647 rockchip,pins 1249 rockchip,pins =
1648 <1 RK 1250 <1 RK_PB5 2 &pcfg_pull_none>;
1649 }; 1251 };
>> 1252
>> 1253 uart3m1_rts_gpio: uart3m1-rts-gpio {
>> 1254 rockchip,pins =
>> 1255 <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
>> 1256 };
1650 }; 1257 };
1651 1258
1652 uart4 { 1259 uart4 {
1653 uart4_xfer: uart4-xfe 1260 uart4_xfer: uart4-xfer {
1654 rockchip,pins 1261 rockchip,pins =
1655 <1 RK 1262 <1 RK_PD4 2 &pcfg_pull_up>,
1656 <1 RK 1263 <1 RK_PD5 2 &pcfg_pull_up>;
1657 }; 1264 };
1658 1265
1659 uart4_cts: uart4-cts 1266 uart4_cts: uart4-cts {
1660 rockchip,pins 1267 rockchip,pins =
1661 <1 RK 1268 <1 RK_PD6 2 &pcfg_pull_none>;
1662 }; 1269 };
1663 1270
1664 uart4_rts: uart4-rts 1271 uart4_rts: uart4-rts {
1665 rockchip,pins 1272 rockchip,pins =
1666 <1 RK 1273 <1 RK_PD7 2 &pcfg_pull_none>;
1667 }; 1274 };
1668 }; 1275 };
1669 1276
1670 uart5 { 1277 uart5 {
1671 uart5_xfer: uart5-xfe 1278 uart5_xfer: uart5-xfer {
1672 rockchip,pins 1279 rockchip,pins =
1673 <3 RK 1280 <3 RK_PA2 4 &pcfg_pull_up>,
1674 <3 RK 1281 <3 RK_PA1 4 &pcfg_pull_up>;
1675 }; 1282 };
1676 1283
1677 uart5_cts: uart5-cts 1284 uart5_cts: uart5-cts {
1678 rockchip,pins 1285 rockchip,pins =
1679 <3 RK 1286 <3 RK_PA3 4 &pcfg_pull_none>;
1680 }; 1287 };
1681 1288
1682 uart5_rts: uart5-rts 1289 uart5_rts: uart5-rts {
1683 rockchip,pins 1290 rockchip,pins =
1684 <3 RK 1291 <3 RK_PA5 4 &pcfg_pull_none>;
1685 }; 1292 };
1686 }; 1293 };
1687 1294
1688 spi0 { 1295 spi0 {
1689 spi0_clk: spi0-clk { 1296 spi0_clk: spi0-clk {
1690 rockchip,pins 1297 rockchip,pins =
1691 <1 RK 1298 <1 RK_PB7 3 &pcfg_pull_up_4ma>;
1692 }; 1299 };
1693 1300
1694 spi0_csn: spi0-csn { 1301 spi0_csn: spi0-csn {
1695 rockchip,pins 1302 rockchip,pins =
1696 <1 RK 1303 <1 RK_PB6 3 &pcfg_pull_up_4ma>;
1697 }; 1304 };
1698 1305
1699 spi0_miso: spi0-miso 1306 spi0_miso: spi0-miso {
1700 rockchip,pins 1307 rockchip,pins =
1701 <1 RK 1308 <1 RK_PB5 3 &pcfg_pull_up_4ma>;
1702 }; 1309 };
1703 1310
1704 spi0_mosi: spi0-mosi 1311 spi0_mosi: spi0-mosi {
1705 rockchip,pins 1312 rockchip,pins =
1706 <1 RK 1313 <1 RK_PB4 3 &pcfg_pull_up_4ma>;
1707 }; 1314 };
1708 1315
1709 spi0_clk_hs: spi0-clk 1316 spi0_clk_hs: spi0-clk-hs {
1710 rockchip,pins 1317 rockchip,pins =
1711 <1 RK 1318 <1 RK_PB7 3 &pcfg_pull_up_8ma>;
1712 }; 1319 };
1713 1320
1714 spi0_miso_hs: spi0-mi 1321 spi0_miso_hs: spi0-miso-hs {
1715 rockchip,pins 1322 rockchip,pins =
1716 <1 RK 1323 <1 RK_PB5 3 &pcfg_pull_up_8ma>;
1717 }; 1324 };
1718 1325
1719 spi0_mosi_hs: spi0-mo 1326 spi0_mosi_hs: spi0-mosi-hs {
1720 rockchip,pins 1327 rockchip,pins =
1721 <1 RK 1328 <1 RK_PB4 3 &pcfg_pull_up_8ma>;
1722 }; 1329 };
1723 }; 1330 };
1724 1331
1725 spi1 { 1332 spi1 {
1726 spi1_clk: spi1-clk { 1333 spi1_clk: spi1-clk {
1727 rockchip,pins 1334 rockchip,pins =
1728 <3 RK 1335 <3 RK_PB7 4 &pcfg_pull_up_4ma>;
1729 }; 1336 };
1730 1337
1731 spi1_csn0: spi1-csn0 1338 spi1_csn0: spi1-csn0 {
1732 rockchip,pins 1339 rockchip,pins =
1733 <3 RK 1340 <3 RK_PB1 4 &pcfg_pull_up_4ma>;
1734 }; 1341 };
1735 1342
1736 spi1_csn1: spi1-csn1 1343 spi1_csn1: spi1-csn1 {
1737 rockchip,pins 1344 rockchip,pins =
1738 <3 RK 1345 <3 RK_PB2 2 &pcfg_pull_up_4ma>;
1739 }; 1346 };
1740 1347
1741 spi1_miso: spi1-miso 1348 spi1_miso: spi1-miso {
1742 rockchip,pins 1349 rockchip,pins =
1743 <3 RK 1350 <3 RK_PB6 4 &pcfg_pull_up_4ma>;
1744 }; 1351 };
1745 1352
1746 spi1_mosi: spi1-mosi 1353 spi1_mosi: spi1-mosi {
1747 rockchip,pins 1354 rockchip,pins =
1748 <3 RK 1355 <3 RK_PB4 4 &pcfg_pull_up_4ma>;
1749 }; 1356 };
1750 1357
1751 spi1_clk_hs: spi1-clk 1358 spi1_clk_hs: spi1-clk-hs {
1752 rockchip,pins 1359 rockchip,pins =
1753 <3 RK 1360 <3 RK_PB7 4 &pcfg_pull_up_8ma>;
1754 }; 1361 };
1755 1362
1756 spi1_miso_hs: spi1-mi 1363 spi1_miso_hs: spi1-miso-hs {
1757 rockchip,pins 1364 rockchip,pins =
1758 <3 RK 1365 <3 RK_PB6 4 &pcfg_pull_up_8ma>;
1759 }; 1366 };
1760 1367
1761 spi1_mosi_hs: spi1-mo 1368 spi1_mosi_hs: spi1-mosi-hs {
1762 rockchip,pins 1369 rockchip,pins =
1763 <3 RK 1370 <3 RK_PB4 4 &pcfg_pull_up_8ma>;
1764 }; 1371 };
1765 }; 1372 };
1766 1373
1767 pdm { 1374 pdm {
1768 pdm_clk0m0: pdm-clk0m 1375 pdm_clk0m0: pdm-clk0m0 {
1769 rockchip,pins 1376 rockchip,pins =
1770 <3 RK 1377 <3 RK_PC6 2 &pcfg_pull_none>;
1771 }; 1378 };
1772 1379
1773 pdm_clk0m1: pdm-clk0m 1380 pdm_clk0m1: pdm-clk0m1 {
1774 rockchip,pins 1381 rockchip,pins =
1775 <2 RK 1382 <2 RK_PC6 1 &pcfg_pull_none>;
1776 }; 1383 };
1777 1384
1778 pdm_clk1: pdm-clk1 { 1385 pdm_clk1: pdm-clk1 {
1779 rockchip,pins 1386 rockchip,pins =
1780 <3 RK 1387 <3 RK_PC7 2 &pcfg_pull_none>;
1781 }; 1388 };
1782 1389
1783 pdm_sdi0m0: pdm-sdi0m 1390 pdm_sdi0m0: pdm-sdi0m0 {
1784 rockchip,pins 1391 rockchip,pins =
1785 <3 RK 1392 <3 RK_PD3 2 &pcfg_pull_none>;
1786 }; 1393 };
1787 1394
1788 pdm_sdi0m1: pdm-sdi0m 1395 pdm_sdi0m1: pdm-sdi0m1 {
1789 rockchip,pins 1396 rockchip,pins =
1790 <2 RK 1397 <2 RK_PC5 2 &pcfg_pull_none>;
1791 }; 1398 };
1792 1399
1793 pdm_sdi1: pdm-sdi1 { 1400 pdm_sdi1: pdm-sdi1 {
1794 rockchip,pins 1401 rockchip,pins =
1795 <3 RK 1402 <3 RK_PD0 2 &pcfg_pull_none>;
1796 }; 1403 };
1797 1404
1798 pdm_sdi2: pdm-sdi2 { 1405 pdm_sdi2: pdm-sdi2 {
1799 rockchip,pins 1406 rockchip,pins =
1800 <3 RK 1407 <3 RK_PD1 2 &pcfg_pull_none>;
1801 }; 1408 };
1802 1409
1803 pdm_sdi3: pdm-sdi3 { 1410 pdm_sdi3: pdm-sdi3 {
1804 rockchip,pins 1411 rockchip,pins =
1805 <3 RK 1412 <3 RK_PD2 2 &pcfg_pull_none>;
1806 }; 1413 };
1807 1414
1808 pdm_clk0m0_sleep: pdm 1415 pdm_clk0m0_sleep: pdm-clk0m0-sleep {
1809 rockchip,pins 1416 rockchip,pins =
1810 <3 RK 1417 <3 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>;
1811 }; 1418 };
1812 1419
1813 pdm_clk0m_sleep1: pdm 1420 pdm_clk0m_sleep1: pdm-clk0m1-sleep {
1814 rockchip,pins 1421 rockchip,pins =
1815 <2 RK 1422 <2 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>;
1816 }; 1423 };
1817 1424
1818 pdm_clk1_sleep: pdm-c 1425 pdm_clk1_sleep: pdm-clk1-sleep {
1819 rockchip,pins 1426 rockchip,pins =
1820 <3 RK 1427 <3 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>;
1821 }; 1428 };
1822 1429
1823 pdm_sdi0m0_sleep: pdm 1430 pdm_sdi0m0_sleep: pdm-sdi0m0-sleep {
1824 rockchip,pins 1431 rockchip,pins =
1825 <3 RK 1432 <3 RK_PD3 RK_FUNC_GPIO &pcfg_input_high>;
1826 }; 1433 };
1827 1434
1828 pdm_sdi0m1_sleep: pdm 1435 pdm_sdi0m1_sleep: pdm-sdi0m1-sleep {
1829 rockchip,pins 1436 rockchip,pins =
1830 <2 RK 1437 <2 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>;
1831 }; 1438 };
1832 1439
1833 pdm_sdi1_sleep: pdm-s 1440 pdm_sdi1_sleep: pdm-sdi1-sleep {
1834 rockchip,pins 1441 rockchip,pins =
1835 <3 RK 1442 <3 RK_PD0 RK_FUNC_GPIO &pcfg_input_high>;
1836 }; 1443 };
1837 1444
1838 pdm_sdi2_sleep: pdm-s 1445 pdm_sdi2_sleep: pdm-sdi2-sleep {
1839 rockchip,pins 1446 rockchip,pins =
1840 <3 RK 1447 <3 RK_PD1 RK_FUNC_GPIO &pcfg_input_high>;
1841 }; 1448 };
1842 1449
1843 pdm_sdi3_sleep: pdm-s 1450 pdm_sdi3_sleep: pdm-sdi3-sleep {
1844 rockchip,pins 1451 rockchip,pins =
1845 <3 RK 1452 <3 RK_PD2 RK_FUNC_GPIO &pcfg_input_high>;
1846 }; 1453 };
1847 }; 1454 };
1848 1455
1849 i2s0 { 1456 i2s0 {
1850 i2s0_8ch_mclk: i2s0-8 1457 i2s0_8ch_mclk: i2s0-8ch-mclk {
1851 rockchip,pins 1458 rockchip,pins =
1852 <3 RK 1459 <3 RK_PC1 2 &pcfg_pull_none>;
1853 }; 1460 };
1854 1461
1855 i2s0_8ch_sclktx: i2s0 1462 i2s0_8ch_sclktx: i2s0-8ch-sclktx {
1856 rockchip,pins 1463 rockchip,pins =
1857 <3 RK 1464 <3 RK_PC3 2 &pcfg_pull_none>;
1858 }; 1465 };
1859 1466
1860 i2s0_8ch_sclkrx: i2s0 1467 i2s0_8ch_sclkrx: i2s0-8ch-sclkrx {
1861 rockchip,pins 1468 rockchip,pins =
1862 <3 RK 1469 <3 RK_PB4 2 &pcfg_pull_none>;
1863 }; 1470 };
1864 1471
1865 i2s0_8ch_lrcktx: i2s0 1472 i2s0_8ch_lrcktx: i2s0-8ch-lrcktx {
1866 rockchip,pins 1473 rockchip,pins =
1867 <3 RK 1474 <3 RK_PC2 2 &pcfg_pull_none>;
1868 }; 1475 };
1869 1476
1870 i2s0_8ch_lrckrx: i2s0 1477 i2s0_8ch_lrckrx: i2s0-8ch-lrckrx {
1871 rockchip,pins 1478 rockchip,pins =
1872 <3 RK 1479 <3 RK_PB5 2 &pcfg_pull_none>;
1873 }; 1480 };
1874 1481
1875 i2s0_8ch_sdo0: i2s0-8 1482 i2s0_8ch_sdo0: i2s0-8ch-sdo0 {
1876 rockchip,pins 1483 rockchip,pins =
1877 <3 RK 1484 <3 RK_PC4 2 &pcfg_pull_none>;
1878 }; 1485 };
1879 1486
1880 i2s0_8ch_sdo1: i2s0-8 1487 i2s0_8ch_sdo1: i2s0-8ch-sdo1 {
1881 rockchip,pins 1488 rockchip,pins =
1882 <3 RK 1489 <3 RK_PC0 2 &pcfg_pull_none>;
1883 }; 1490 };
1884 1491
1885 i2s0_8ch_sdo2: i2s0-8 1492 i2s0_8ch_sdo2: i2s0-8ch-sdo2 {
1886 rockchip,pins 1493 rockchip,pins =
1887 <3 RK 1494 <3 RK_PB7 2 &pcfg_pull_none>;
1888 }; 1495 };
1889 1496
1890 i2s0_8ch_sdo3: i2s0-8 1497 i2s0_8ch_sdo3: i2s0-8ch-sdo3 {
1891 rockchip,pins 1498 rockchip,pins =
1892 <3 RK 1499 <3 RK_PB6 2 &pcfg_pull_none>;
1893 }; 1500 };
1894 1501
1895 i2s0_8ch_sdi0: i2s0-8 1502 i2s0_8ch_sdi0: i2s0-8ch-sdi0 {
1896 rockchip,pins 1503 rockchip,pins =
1897 <3 RK 1504 <3 RK_PC5 2 &pcfg_pull_none>;
1898 }; 1505 };
1899 1506
1900 i2s0_8ch_sdi1: i2s0-8 1507 i2s0_8ch_sdi1: i2s0-8ch-sdi1 {
1901 rockchip,pins 1508 rockchip,pins =
1902 <3 RK 1509 <3 RK_PB3 2 &pcfg_pull_none>;
1903 }; 1510 };
1904 1511
1905 i2s0_8ch_sdi2: i2s0-8 1512 i2s0_8ch_sdi2: i2s0-8ch-sdi2 {
1906 rockchip,pins 1513 rockchip,pins =
1907 <3 RK 1514 <3 RK_PB1 2 &pcfg_pull_none>;
1908 }; 1515 };
1909 1516
1910 i2s0_8ch_sdi3: i2s0-8 1517 i2s0_8ch_sdi3: i2s0-8ch-sdi3 {
1911 rockchip,pins 1518 rockchip,pins =
1912 <3 RK 1519 <3 RK_PB0 2 &pcfg_pull_none>;
1913 }; 1520 };
1914 }; 1521 };
1915 1522
1916 i2s1 { 1523 i2s1 {
1917 i2s1_2ch_mclk: i2s1-2 1524 i2s1_2ch_mclk: i2s1-2ch-mclk {
1918 rockchip,pins 1525 rockchip,pins =
1919 <2 RK 1526 <2 RK_PC3 1 &pcfg_pull_none>;
1920 }; 1527 };
1921 1528
1922 i2s1_2ch_sclk: i2s1-2 1529 i2s1_2ch_sclk: i2s1-2ch-sclk {
1923 rockchip,pins 1530 rockchip,pins =
1924 <2 RK 1531 <2 RK_PC2 1 &pcfg_pull_none>;
1925 }; 1532 };
1926 1533
1927 i2s1_2ch_lrck: i2s1-2 1534 i2s1_2ch_lrck: i2s1-2ch-lrck {
1928 rockchip,pins 1535 rockchip,pins =
1929 <2 RK 1536 <2 RK_PC1 1 &pcfg_pull_none>;
1930 }; 1537 };
1931 1538
1932 i2s1_2ch_sdi: i2s1-2c 1539 i2s1_2ch_sdi: i2s1-2ch-sdi {
1933 rockchip,pins 1540 rockchip,pins =
1934 <2 RK 1541 <2 RK_PC5 1 &pcfg_pull_none>;
1935 }; 1542 };
1936 1543
1937 i2s1_2ch_sdo: i2s1-2c 1544 i2s1_2ch_sdo: i2s1-2ch-sdo {
1938 rockchip,pins 1545 rockchip,pins =
1939 <2 RK 1546 <2 RK_PC4 1 &pcfg_pull_none>;
1940 }; 1547 };
1941 }; 1548 };
1942 1549
1943 i2s2 { 1550 i2s2 {
1944 i2s2_2ch_mclk: i2s2-2 1551 i2s2_2ch_mclk: i2s2-2ch-mclk {
1945 rockchip,pins 1552 rockchip,pins =
1946 <3 RK 1553 <3 RK_PA1 2 &pcfg_pull_none>;
1947 }; 1554 };
1948 1555
1949 i2s2_2ch_sclk: i2s2-2 1556 i2s2_2ch_sclk: i2s2-2ch-sclk {
1950 rockchip,pins 1557 rockchip,pins =
1951 <3 RK 1558 <3 RK_PA2 2 &pcfg_pull_none>;
1952 }; 1559 };
1953 1560
1954 i2s2_2ch_lrck: i2s2-2 1561 i2s2_2ch_lrck: i2s2-2ch-lrck {
1955 rockchip,pins 1562 rockchip,pins =
1956 <3 RK 1563 <3 RK_PA3 2 &pcfg_pull_none>;
1957 }; 1564 };
1958 1565
1959 i2s2_2ch_sdi: i2s2-2c 1566 i2s2_2ch_sdi: i2s2-2ch-sdi {
1960 rockchip,pins 1567 rockchip,pins =
1961 <3 RK 1568 <3 RK_PA5 2 &pcfg_pull_none>;
1962 }; 1569 };
1963 1570
1964 i2s2_2ch_sdo: i2s2-2c 1571 i2s2_2ch_sdo: i2s2-2ch-sdo {
1965 rockchip,pins 1572 rockchip,pins =
1966 <3 RK 1573 <3 RK_PA7 2 &pcfg_pull_none>;
1967 }; 1574 };
1968 }; 1575 };
1969 1576
1970 sdmmc { 1577 sdmmc {
1971 sdmmc_clk: sdmmc-clk 1578 sdmmc_clk: sdmmc-clk {
1972 rockchip,pins 1579 rockchip,pins =
1973 <1 RK 1580 <1 RK_PD6 1 &pcfg_pull_none_8ma>;
1974 }; 1581 };
1975 1582
1976 sdmmc_cmd: sdmmc-cmd 1583 sdmmc_cmd: sdmmc-cmd {
1977 rockchip,pins 1584 rockchip,pins =
1978 <1 RK 1585 <1 RK_PD7 1 &pcfg_pull_up_8ma>;
1979 }; 1586 };
1980 1587
1981 sdmmc_det: sdmmc-det 1588 sdmmc_det: sdmmc-det {
1982 rockchip,pins 1589 rockchip,pins =
1983 <0 RK 1590 <0 RK_PA3 1 &pcfg_pull_up_8ma>;
1984 }; 1591 };
1985 1592
1986 sdmmc_bus1: sdmmc-bus 1593 sdmmc_bus1: sdmmc-bus1 {
1987 rockchip,pins 1594 rockchip,pins =
1988 <1 RK 1595 <1 RK_PD2 1 &pcfg_pull_up_8ma>;
1989 }; 1596 };
1990 1597
1991 sdmmc_bus4: sdmmc-bus 1598 sdmmc_bus4: sdmmc-bus4 {
1992 rockchip,pins 1599 rockchip,pins =
1993 <1 RK 1600 <1 RK_PD2 1 &pcfg_pull_up_8ma>,
1994 <1 RK 1601 <1 RK_PD3 1 &pcfg_pull_up_8ma>,
1995 <1 RK 1602 <1 RK_PD4 1 &pcfg_pull_up_8ma>,
1996 <1 RK 1603 <1 RK_PD5 1 &pcfg_pull_up_8ma>;
1997 }; 1604 };
>> 1605
>> 1606 sdmmc_gpio: sdmmc-gpio {
>> 1607 rockchip,pins =
>> 1608 <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
>> 1609 <1 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
>> 1610 <1 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
>> 1611 <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
>> 1612 <1 RK_PD6 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
>> 1613 <1 RK_PD7 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
>> 1614 };
1998 }; 1615 };
1999 1616
2000 sdio { 1617 sdio {
2001 sdio_clk: sdio-clk { 1618 sdio_clk: sdio-clk {
2002 rockchip,pins 1619 rockchip,pins =
2003 <1 RK 1620 <1 RK_PC5 1 &pcfg_pull_none>;
2004 }; 1621 };
2005 1622
2006 sdio_cmd: sdio-cmd { 1623 sdio_cmd: sdio-cmd {
2007 rockchip,pins 1624 rockchip,pins =
2008 <1 RK 1625 <1 RK_PC4 1 &pcfg_pull_up>;
2009 }; 1626 };
2010 1627
2011 sdio_bus4: sdio-bus4 1628 sdio_bus4: sdio-bus4 {
2012 rockchip,pins 1629 rockchip,pins =
2013 <1 RK 1630 <1 RK_PC6 1 &pcfg_pull_up>,
2014 <1 RK 1631 <1 RK_PC7 1 &pcfg_pull_up>,
2015 <1 RK 1632 <1 RK_PD0 1 &pcfg_pull_up>,
2016 <1 RK 1633 <1 RK_PD1 1 &pcfg_pull_up>;
2017 }; 1634 };
>> 1635
>> 1636 sdio_gpio: sdio-gpio {
>> 1637 rockchip,pins =
>> 1638 <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_up>,
>> 1639 <1 RK_PC7 RK_FUNC_GPIO &pcfg_pull_up>,
>> 1640 <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up>,
>> 1641 <1 RK_PD1 RK_FUNC_GPIO &pcfg_pull_up>,
>> 1642 <1 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up>,
>> 1643 <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>;
>> 1644 };
2018 }; 1645 };
2019 1646
2020 emmc { 1647 emmc {
2021 emmc_clk: emmc-clk { 1648 emmc_clk: emmc-clk {
2022 rockchip,pins 1649 rockchip,pins =
2023 <1 RK 1650 <1 RK_PB1 2 &pcfg_pull_none_8ma>;
2024 }; 1651 };
2025 1652
2026 emmc_cmd: emmc-cmd { 1653 emmc_cmd: emmc-cmd {
2027 rockchip,pins 1654 rockchip,pins =
2028 <1 RK 1655 <1 RK_PB2 2 &pcfg_pull_up_8ma>;
2029 }; 1656 };
2030 1657
>> 1658 emmc_pwren: emmc-pwren {
>> 1659 rockchip,pins =
>> 1660 <1 RK_PB0 2 &pcfg_pull_none>;
>> 1661 };
>> 1662
2031 emmc_rstnout: emmc-rs 1663 emmc_rstnout: emmc-rstnout {
2032 rockchip,pins 1664 rockchip,pins =
2033 <1 RK 1665 <1 RK_PB3 2 &pcfg_pull_none>;
2034 }; 1666 };
2035 1667
2036 emmc_bus1: emmc-bus1 1668 emmc_bus1: emmc-bus1 {
2037 rockchip,pins 1669 rockchip,pins =
2038 <1 RK 1670 <1 RK_PA0 2 &pcfg_pull_up_8ma>;
2039 }; 1671 };
2040 1672
2041 emmc_bus4: emmc-bus4 1673 emmc_bus4: emmc-bus4 {
2042 rockchip,pins 1674 rockchip,pins =
2043 <1 RK 1675 <1 RK_PA0 2 &pcfg_pull_up_8ma>,
2044 <1 RK 1676 <1 RK_PA1 2 &pcfg_pull_up_8ma>,
2045 <1 RK 1677 <1 RK_PA2 2 &pcfg_pull_up_8ma>,
2046 <1 RK 1678 <1 RK_PA3 2 &pcfg_pull_up_8ma>;
2047 }; 1679 };
2048 1680
2049 emmc_bus8: emmc-bus8 1681 emmc_bus8: emmc-bus8 {
2050 rockchip,pins 1682 rockchip,pins =
2051 <1 RK 1683 <1 RK_PA0 2 &pcfg_pull_up_8ma>,
2052 <1 RK 1684 <1 RK_PA1 2 &pcfg_pull_up_8ma>,
2053 <1 RK 1685 <1 RK_PA2 2 &pcfg_pull_up_8ma>,
2054 <1 RK 1686 <1 RK_PA3 2 &pcfg_pull_up_8ma>,
2055 <1 RK 1687 <1 RK_PA4 2 &pcfg_pull_up_8ma>,
2056 <1 RK 1688 <1 RK_PA5 2 &pcfg_pull_up_8ma>,
2057 <1 RK 1689 <1 RK_PA6 2 &pcfg_pull_up_8ma>,
2058 <1 RK 1690 <1 RK_PA7 2 &pcfg_pull_up_8ma>;
2059 }; 1691 };
2060 }; 1692 };
2061 1693
2062 flash { 1694 flash {
2063 flash_cs0: flash-cs0 1695 flash_cs0: flash-cs0 {
2064 rockchip,pins 1696 rockchip,pins =
2065 <1 RK 1697 <1 RK_PB0 1 &pcfg_pull_none>;
2066 }; 1698 };
2067 1699
2068 flash_rdy: flash-rdy 1700 flash_rdy: flash-rdy {
2069 rockchip,pins 1701 rockchip,pins =
2070 <1 RK 1702 <1 RK_PB1 1 &pcfg_pull_none>;
2071 }; 1703 };
2072 1704
2073 flash_dqs: flash-dqs 1705 flash_dqs: flash-dqs {
2074 rockchip,pins 1706 rockchip,pins =
2075 <1 RK 1707 <1 RK_PB2 1 &pcfg_pull_none>;
2076 }; 1708 };
2077 1709
2078 flash_ale: flash-ale 1710 flash_ale: flash-ale {
2079 rockchip,pins 1711 rockchip,pins =
2080 <1 RK 1712 <1 RK_PB3 1 &pcfg_pull_none>;
2081 }; 1713 };
2082 1714
2083 flash_cle: flash-cle 1715 flash_cle: flash-cle {
2084 rockchip,pins 1716 rockchip,pins =
2085 <1 RK 1717 <1 RK_PB4 1 &pcfg_pull_none>;
2086 }; 1718 };
2087 1719
2088 flash_wrn: flash-wrn 1720 flash_wrn: flash-wrn {
2089 rockchip,pins 1721 rockchip,pins =
2090 <1 RK 1722 <1 RK_PB5 1 &pcfg_pull_none>;
2091 }; 1723 };
2092 1724
2093 flash_csl: flash-csl 1725 flash_csl: flash-csl {
2094 rockchip,pins 1726 rockchip,pins =
2095 <1 RK 1727 <1 RK_PB6 1 &pcfg_pull_none>;
2096 }; 1728 };
2097 1729
2098 flash_rdn: flash-rdn 1730 flash_rdn: flash-rdn {
2099 rockchip,pins 1731 rockchip,pins =
2100 <1 RK 1732 <1 RK_PB7 1 &pcfg_pull_none>;
2101 }; 1733 };
2102 1734
2103 flash_bus8: flash-bus 1735 flash_bus8: flash-bus8 {
2104 rockchip,pins 1736 rockchip,pins =
2105 <1 RK 1737 <1 RK_PA0 1 &pcfg_pull_up_12ma>,
2106 <1 RK 1738 <1 RK_PA1 1 &pcfg_pull_up_12ma>,
2107 <1 RK 1739 <1 RK_PA2 1 &pcfg_pull_up_12ma>,
2108 <1 RK 1740 <1 RK_PA3 1 &pcfg_pull_up_12ma>,
2109 <1 RK 1741 <1 RK_PA4 1 &pcfg_pull_up_12ma>,
2110 <1 RK 1742 <1 RK_PA5 1 &pcfg_pull_up_12ma>,
2111 <1 RK 1743 <1 RK_PA6 1 &pcfg_pull_up_12ma>,
2112 <1 RK 1744 <1 RK_PA7 1 &pcfg_pull_up_12ma>;
2113 }; <<
2114 }; <<
2115 <<
2116 sfc { <<
2117 sfc_bus4: sfc-bus4 { <<
2118 rockchip,pins <<
2119 <1 RK <<
2120 <1 RK <<
2121 <1 RK <<
2122 <1 RK <<
2123 }; <<
2124 <<
2125 sfc_bus2: sfc-bus2 { <<
2126 rockchip,pins <<
2127 <1 RK <<
2128 <1 RK <<
2129 }; <<
2130 <<
2131 sfc_cs0: sfc-cs0 { <<
2132 rockchip,pins <<
2133 <1 RK <<
2134 }; <<
2135 <<
2136 sfc_clk: sfc-clk { <<
2137 rockchip,pins <<
2138 <1 RK <<
2139 }; 1745 };
2140 }; 1746 };
2141 1747
2142 lcdc { 1748 lcdc {
2143 lcdc_rgb_dclk_pin: lc 1749 lcdc_rgb_dclk_pin: lcdc-rgb-dclk-pin {
2144 rockchip,pins 1750 rockchip,pins =
2145 <3 RK 1751 <3 RK_PA0 1 &pcfg_pull_none_12ma>;
2146 }; 1752 };
2147 1753
2148 lcdc_rgb_m0_hsync_pin 1754 lcdc_rgb_m0_hsync_pin: lcdc-rgb-m0-hsync-pin {
2149 rockchip,pins 1755 rockchip,pins =
2150 <3 RK 1756 <3 RK_PA1 1 &pcfg_pull_none_12ma>;
2151 }; 1757 };
2152 1758
2153 lcdc_rgb_m0_vsync_pin 1759 lcdc_rgb_m0_vsync_pin: lcdc-rgb-m0-vsync-pin {
2154 rockchip,pins 1760 rockchip,pins =
2155 <3 RK 1761 <3 RK_PA2 1 &pcfg_pull_none_12ma>;
2156 }; 1762 };
2157 1763
2158 lcdc_rgb_m0_den_pin: 1764 lcdc_rgb_m0_den_pin: lcdc-rgb-m0-den-pin {
2159 rockchip,pins 1765 rockchip,pins =
2160 <3 RK 1766 <3 RK_PA3 1 &pcfg_pull_none_12ma>;
2161 }; 1767 };
2162 1768
2163 lcdc_rgb888_m0_data_p 1769 lcdc_rgb888_m0_data_pins: lcdc-rgb888-m0-data-pins {
2164 rockchip,pins 1770 rockchip,pins =
2165 <3 RK 1771 <3 RK_PA7 1 &pcfg_pull_none_8ma>, /* lcdc_d3 */
2166 <3 RK 1772 <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */
2167 <3 RK 1773 <3 RK_PA5 1 &pcfg_pull_none_8ma>, /* lcdc_d1 */
2168 <3 RK 1774 <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */
2169 <3 RK 1775 <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */
2170 <3 RK 1776 <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */
2171 <3 RK 1777 <3 RK_PB1 1 &pcfg_pull_none_8ma>, /* lcdc_d5 */
2172 <3 RK 1778 <3 RK_PB0 1 &pcfg_pull_none_8ma>, /* lcdc_d4 */
2173 <3 RK 1779 <3 RK_PB7 1 &pcfg_pull_none_8ma>, /* lcdc_d11 */
2174 <3 RK 1780 <3 RK_PB6 1 &pcfg_pull_none_8ma>, /* lcdc_d10 */
2175 <3 RK 1781 <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */
2176 <3 RK 1782 <3 RK_PB4 1 &pcfg_pull_none_8ma>, /* lcdc_d8 */
2177 <3 RK 1783 <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */
2178 <3 RK 1784 <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */
2179 <3 RK 1785 <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */
2180 <3 RK 1786 <3 RK_PC0 1 &pcfg_pull_none_8ma>, /* lcdc_d12 */
2181 <3 RK 1787 <3 RK_PC7 1 &pcfg_pull_none_8ma>, /* lcdc_d19 */
2182 <3 RK 1788 <3 RK_PC6 1 &pcfg_pull_none_8ma>, /* lcdc_d18 */
2183 <3 RK 1789 <3 RK_PC5 1 &pcfg_pull_none_8ma>, /* lcdc_d17 */
2184 <3 RK 1790 <3 RK_PC4 1 &pcfg_pull_none_8ma>, /* lcdc_d16 */
2185 <3 RK 1791 <3 RK_PD3 1 &pcfg_pull_none_8ma>, /* lcdc_d23 */
2186 <3 RK 1792 <3 RK_PD2 1 &pcfg_pull_none_8ma>, /* lcdc_d22 */
2187 <3 RK 1793 <3 RK_PD1 1 &pcfg_pull_none_8ma>, /* lcdc_d21 */
2188 <3 RK 1794 <3 RK_PD0 1 &pcfg_pull_none_8ma>; /* lcdc_d20 */
2189 }; 1795 };
2190 1796
2191 lcdc_rgb666_m0_data_p 1797 lcdc_rgb666_m0_data_pins: lcdc-rgb666-m0-data-pins {
2192 rockchip,pins 1798 rockchip,pins =
2193 <3 RK 1799 <3 RK_PA7 1 &pcfg_pull_none_8ma>, /* lcdc_d3 */
2194 <3 RK 1800 <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */
2195 <3 RK 1801 <3 RK_PA5 1 &pcfg_pull_none_8ma>, /* lcdc_d1 */
2196 <3 RK 1802 <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */
2197 <3 RK 1803 <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */
2198 <3 RK 1804 <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */
2199 <3 RK 1805 <3 RK_PB1 1 &pcfg_pull_none_8ma>, /* lcdc_d5 */
2200 <3 RK 1806 <3 RK_PB0 1 &pcfg_pull_none_8ma>, /* lcdc_d4 */
2201 <3 RK 1807 <3 RK_PB7 1 &pcfg_pull_none_8ma>, /* lcdc_d11 */
2202 <3 RK 1808 <3 RK_PB6 1 &pcfg_pull_none_8ma>, /* lcdc_d10 */
2203 <3 RK 1809 <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */
2204 <3 RK 1810 <3 RK_PB4 1 &pcfg_pull_none_8ma>, /* lcdc_d8 */
2205 <3 RK 1811 <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */
2206 <3 RK 1812 <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */
2207 <3 RK 1813 <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */
2208 <3 RK 1814 <3 RK_PC0 1 &pcfg_pull_none_8ma>, /* lcdc_d12 */
2209 <3 RK 1815 <3 RK_PC5 1 &pcfg_pull_none_8ma>, /* lcdc_d17 */
2210 <3 RK 1816 <3 RK_PC4 1 &pcfg_pull_none_8ma>; /* lcdc_d16 */
2211 }; 1817 };
2212 1818
2213 lcdc_rgb565_m0_data_p 1819 lcdc_rgb565_m0_data_pins: lcdc-rgb565-m0-data-pins {
2214 rockchip,pins 1820 rockchip,pins =
2215 <3 RK 1821 <3 RK_PA7 1 &pcfg_pull_none_8ma>, /* lcdc_d3 */
2216 <3 RK 1822 <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */
2217 <3 RK 1823 <3 RK_PA5 1 &pcfg_pull_none_8ma>, /* lcdc_d1 */
2218 <3 RK 1824 <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */
2219 <3 RK 1825 <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */
2220 <3 RK 1826 <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */
2221 <3 RK 1827 <3 RK_PB1 1 &pcfg_pull_none_8ma>, /* lcdc_d5 */
2222 <3 RK 1828 <3 RK_PB0 1 &pcfg_pull_none_8ma>, /* lcdc_d4 */
2223 <3 RK 1829 <3 RK_PB7 1 &pcfg_pull_none_8ma>, /* lcdc_d11 */
2224 <3 RK 1830 <3 RK_PB6 1 &pcfg_pull_none_8ma>, /* lcdc_d10 */
2225 <3 RK 1831 <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */
2226 <3 RK 1832 <3 RK_PB4 1 &pcfg_pull_none_8ma>, /* lcdc_d8 */
2227 <3 RK 1833 <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */
2228 <3 RK 1834 <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */
2229 <3 RK 1835 <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */
2230 <3 RK 1836 <3 RK_PC0 1 &pcfg_pull_none_8ma>; /* lcdc_d12 */
2231 }; 1837 };
2232 1838
2233 lcdc_rgb888_m1_data_p 1839 lcdc_rgb888_m1_data_pins: lcdc-rgb888-m1-data-pins {
2234 rockchip,pins 1840 rockchip,pins =
2235 <3 RK 1841 <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */
2236 <3 RK 1842 <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */
2237 <3 RK 1843 <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */
2238 <3 RK 1844 <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */
2239 <3 RK 1845 <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */
2240 <3 RK 1846 <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */
2241 <3 RK 1847 <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */
2242 <3 RK 1848 <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */
2243 <3 RK 1849 <3 RK_PC0 1 &pcfg_pull_none_8ma>, /* lcdc_d12 */
2244 <3 RK 1850 <3 RK_PC7 1 &pcfg_pull_none_8ma>, /* lcdc_d19 */
2245 <3 RK 1851 <3 RK_PC6 1 &pcfg_pull_none_8ma>, /* lcdc_d18 */
2246 <3 RK 1852 <3 RK_PC5 1 &pcfg_pull_none_8ma>, /* lcdc_d17 */
2247 <3 RK 1853 <3 RK_PC4 1 &pcfg_pull_none_8ma>, /* lcdc_d16 */
2248 <3 RK 1854 <3 RK_PD3 1 &pcfg_pull_none_8ma>, /* lcdc_d23 */
2249 <3 RK 1855 <3 RK_PD2 1 &pcfg_pull_none_8ma>, /* lcdc_d22 */
2250 <3 RK 1856 <3 RK_PD1 1 &pcfg_pull_none_8ma>, /* lcdc_d21 */
2251 <3 RK 1857 <3 RK_PD0 1 &pcfg_pull_none_8ma>; /* lcdc_d20 */
2252 }; 1858 };
2253 1859
2254 lcdc_rgb666_m1_data_p 1860 lcdc_rgb666_m1_data_pins: lcdc-rgb666-m1-data-pins {
2255 rockchip,pins 1861 rockchip,pins =
2256 <3 RK 1862 <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */
2257 <3 RK 1863 <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */
2258 <3 RK 1864 <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */
2259 <3 RK 1865 <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */
2260 <3 RK 1866 <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */
2261 <3 RK 1867 <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */
2262 <3 RK 1868 <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */
2263 <3 RK 1869 <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */
2264 <3 RK 1870 <3 RK_PC0 1 &pcfg_pull_none_8ma>, /* lcdc_d12 */
2265 <3 RK 1871 <3 RK_PC5 1 &pcfg_pull_none_8ma>, /* lcdc_d17 */
2266 <3 RK 1872 <3 RK_PC4 1 &pcfg_pull_none_8ma>; /* lcdc_d16 */
2267 }; 1873 };
2268 1874
2269 lcdc_rgb565_m1_data_p 1875 lcdc_rgb565_m1_data_pins: lcdc-rgb565-m1-data-pins {
2270 rockchip,pins 1876 rockchip,pins =
2271 <3 RK 1877 <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */
2272 <3 RK 1878 <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */
2273 <3 RK 1879 <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */
2274 <3 RK 1880 <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */
2275 <3 RK 1881 <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */
2276 <3 RK 1882 <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */
2277 <3 RK 1883 <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */
2278 <3 RK 1884 <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */
2279 <3 RK 1885 <3 RK_PC0 1 &pcfg_pull_none_8ma>; /* lcdc_d12 */
2280 }; 1886 };
2281 }; 1887 };
2282 1888
2283 pwm0 { 1889 pwm0 {
2284 pwm0_pin: pwm0-pin { 1890 pwm0_pin: pwm0-pin {
2285 rockchip,pins 1891 rockchip,pins =
2286 <0 RK 1892 <0 RK_PB7 1 &pcfg_pull_none>;
2287 }; 1893 };
2288 }; 1894 };
2289 1895
2290 pwm1 { 1896 pwm1 {
2291 pwm1_pin: pwm1-pin { 1897 pwm1_pin: pwm1-pin {
2292 rockchip,pins 1898 rockchip,pins =
2293 <0 RK 1899 <0 RK_PC0 1 &pcfg_pull_none>;
2294 }; 1900 };
2295 }; 1901 };
2296 1902
2297 pwm2 { 1903 pwm2 {
2298 pwm2_pin: pwm2-pin { 1904 pwm2_pin: pwm2-pin {
2299 rockchip,pins 1905 rockchip,pins =
2300 <2 RK 1906 <2 RK_PB5 1 &pcfg_pull_none>;
2301 }; 1907 };
2302 }; 1908 };
2303 1909
2304 pwm3 { 1910 pwm3 {
2305 pwm3_pin: pwm3-pin { 1911 pwm3_pin: pwm3-pin {
2306 rockchip,pins 1912 rockchip,pins =
2307 <0 RK 1913 <0 RK_PC1 1 &pcfg_pull_none>;
2308 }; 1914 };
2309 }; 1915 };
2310 1916
2311 pwm4 { 1917 pwm4 {
2312 pwm4_pin: pwm4-pin { 1918 pwm4_pin: pwm4-pin {
2313 rockchip,pins 1919 rockchip,pins =
2314 <3 RK 1920 <3 RK_PC2 3 &pcfg_pull_none>;
2315 }; 1921 };
2316 }; 1922 };
2317 1923
2318 pwm5 { 1924 pwm5 {
2319 pwm5_pin: pwm5-pin { 1925 pwm5_pin: pwm5-pin {
2320 rockchip,pins 1926 rockchip,pins =
2321 <3 RK 1927 <3 RK_PC3 3 &pcfg_pull_none>;
2322 }; 1928 };
2323 }; 1929 };
2324 1930
2325 pwm6 { 1931 pwm6 {
2326 pwm6_pin: pwm6-pin { 1932 pwm6_pin: pwm6-pin {
2327 rockchip,pins 1933 rockchip,pins =
2328 <3 RK 1934 <3 RK_PC4 3 &pcfg_pull_none>;
2329 }; 1935 };
2330 }; 1936 };
2331 1937
2332 pwm7 { 1938 pwm7 {
2333 pwm7_pin: pwm7-pin { 1939 pwm7_pin: pwm7-pin {
2334 rockchip,pins 1940 rockchip,pins =
2335 <3 RK 1941 <3 RK_PC5 3 &pcfg_pull_none>;
2336 }; 1942 };
2337 }; 1943 };
2338 1944
2339 gmac { 1945 gmac {
2340 rmii_pins: rmii-pins 1946 rmii_pins: rmii-pins {
2341 rockchip,pins 1947 rockchip,pins =
2342 <2 RK 1948 <2 RK_PA0 2 &pcfg_pull_none_12ma>, /* mac_txen */
2343 <2 RK 1949 <2 RK_PA1 2 &pcfg_pull_none_12ma>, /* mac_txd1 */
2344 <2 RK 1950 <2 RK_PA2 2 &pcfg_pull_none_12ma>, /* mac_txd0 */
2345 <2 RK 1951 <2 RK_PA3 2 &pcfg_pull_none>, /* mac_rxd0 */
2346 <2 RK 1952 <2 RK_PA4 2 &pcfg_pull_none>, /* mac_rxd1 */
2347 <2 RK 1953 <2 RK_PA5 2 &pcfg_pull_none>, /* mac_rxer */
2348 <2 RK 1954 <2 RK_PA6 2 &pcfg_pull_none>, /* mac_rxdv */
2349 <2 RK 1955 <2 RK_PA7 2 &pcfg_pull_none>, /* mac_mdio */
2350 <2 RK 1956 <2 RK_PB1 2 &pcfg_pull_none>; /* mac_mdc */
2351 }; 1957 };
2352 1958
2353 mac_refclk_12ma: mac- 1959 mac_refclk_12ma: mac-refclk-12ma {
2354 rockchip,pins 1960 rockchip,pins =
2355 <2 RK 1961 <2 RK_PB2 2 &pcfg_pull_none_12ma>;
2356 }; 1962 };
2357 1963
2358 mac_refclk: mac-refcl 1964 mac_refclk: mac-refclk {
2359 rockchip,pins 1965 rockchip,pins =
2360 <2 RK 1966 <2 RK_PB2 2 &pcfg_pull_none>;
2361 }; 1967 };
2362 }; 1968 };
2363 1969
2364 cif-m0 { 1970 cif-m0 {
2365 cif_clkout_m0: cif-cl 1971 cif_clkout_m0: cif-clkout-m0 {
2366 rockchip,pins 1972 rockchip,pins =
2367 <2 RK 1973 <2 RK_PB3 1 &pcfg_pull_none>;
2368 }; 1974 };
2369 1975
2370 dvp_d2d9_m0: dvp-d2d9 1976 dvp_d2d9_m0: dvp-d2d9-m0 {
2371 rockchip,pins 1977 rockchip,pins =
2372 <2 RK 1978 <2 RK_PA0 1 &pcfg_pull_none>, /* cif_data2 */
2373 <2 RK 1979 <2 RK_PA1 1 &pcfg_pull_none>, /* cif_data3 */
2374 <2 RK 1980 <2 RK_PA2 1 &pcfg_pull_none>, /* cif_data4 */
2375 <2 RK 1981 <2 RK_PA3 1 &pcfg_pull_none>, /* cif_data5 */
2376 <2 RK 1982 <2 RK_PA4 1 &pcfg_pull_none>, /* cif_data6 */
2377 <2 RK 1983 <2 RK_PA5 1 &pcfg_pull_none>, /* cif_data7 */
2378 <2 RK 1984 <2 RK_PA6 1 &pcfg_pull_none>, /* cif_data8 */
2379 <2 RK 1985 <2 RK_PA7 1 &pcfg_pull_none>, /* cif_data9 */
2380 <2 RK 1986 <2 RK_PB0 1 &pcfg_pull_none>, /* cif_sync */
2381 <2 RK 1987 <2 RK_PB1 1 &pcfg_pull_none>, /* cif_href */
2382 <2 RK 1988 <2 RK_PB2 1 &pcfg_pull_none>, /* cif_clkin */
2383 <2 RK 1989 <2 RK_PB3 1 &pcfg_pull_none>; /* cif_clkout */
2384 }; 1990 };
2385 1991
2386 dvp_d0d1_m0: dvp-d0d1 1992 dvp_d0d1_m0: dvp-d0d1-m0 {
2387 rockchip,pins 1993 rockchip,pins =
2388 <2 RK 1994 <2 RK_PB4 1 &pcfg_pull_none>, /* cif_data0 */
2389 <2 RK 1995 <2 RK_PB6 1 &pcfg_pull_none>; /* cif_data1 */
2390 }; 1996 };
2391 1997
2392 dvp_d10d11_m0:d10-d11 1998 dvp_d10d11_m0:d10-d11-m0 {
2393 rockchip,pins 1999 rockchip,pins =
2394 <2 RK 2000 <2 RK_PB7 1 &pcfg_pull_none>, /* cif_data10 */
2395 <2 RK 2001 <2 RK_PC0 1 &pcfg_pull_none>; /* cif_data11 */
2396 }; 2002 };
2397 }; 2003 };
2398 2004
2399 cif-m1 { 2005 cif-m1 {
2400 cif_clkout_m1: cif-cl 2006 cif_clkout_m1: cif-clkout-m1 {
2401 rockchip,pins 2007 rockchip,pins =
2402 <3 RK 2008 <3 RK_PD0 3 &pcfg_pull_none>;
2403 }; 2009 };
2404 2010
2405 dvp_d2d9_m1: dvp-d2d9 2011 dvp_d2d9_m1: dvp-d2d9-m1 {
2406 rockchip,pins 2012 rockchip,pins =
2407 <3 RK 2013 <3 RK_PA3 3 &pcfg_pull_none>, /* cif_data2 */
2408 <3 RK 2014 <3 RK_PA5 3 &pcfg_pull_none>, /* cif_data3 */
2409 <3 RK 2015 <3 RK_PA7 3 &pcfg_pull_none>, /* cif_data4 */
2410 <3 RK 2016 <3 RK_PB0 3 &pcfg_pull_none>, /* cif_data5 */
2411 <3 RK 2017 <3 RK_PB1 3 &pcfg_pull_none>, /* cif_data6 */
2412 <3 RK 2018 <3 RK_PB4 3 &pcfg_pull_none>, /* cif_data7 */
2413 <3 RK 2019 <3 RK_PB6 3 &pcfg_pull_none>, /* cif_data8 */
2414 <3 RK 2020 <3 RK_PB7 3 &pcfg_pull_none>, /* cif_data9 */
2415 <3 RK 2021 <3 RK_PD1 3 &pcfg_pull_none>, /* cif_sync */
2416 <3 RK 2022 <3 RK_PD2 3 &pcfg_pull_none>, /* cif_href */
2417 <3 RK 2023 <3 RK_PD3 3 &pcfg_pull_none>, /* cif_clkin */
2418 <3 RK 2024 <3 RK_PD0 3 &pcfg_pull_none>; /* cif_clkout */
2419 }; 2025 };
2420 2026
2421 dvp_d0d1_m1: dvp-d0d1 2027 dvp_d0d1_m1: dvp-d0d1-m1 {
2422 rockchip,pins 2028 rockchip,pins =
2423 <3 RK 2029 <3 RK_PA1 3 &pcfg_pull_none>, /* cif_data0 */
2424 <3 RK 2030 <3 RK_PA2 3 &pcfg_pull_none>; /* cif_data1 */
2425 }; 2031 };
2426 2032
2427 dvp_d10d11_m1:d10-d11 2033 dvp_d10d11_m1:d10-d11-m1 {
2428 rockchip,pins 2034 rockchip,pins =
2429 <3 RK 2035 <3 RK_PC6 3 &pcfg_pull_none>, /* cif_data10 */
2430 <3 RK 2036 <3 RK_PC7 3 &pcfg_pull_none>; /* cif_data11 */
2431 }; 2037 };
2432 }; 2038 };
2433 2039
2434 isp { 2040 isp {
2435 isp_prelight: isp-pre 2041 isp_prelight: isp-prelight {
2436 rockchip,pins 2042 rockchip,pins =
2437 <3 RK 2043 <3 RK_PD1 4 &pcfg_pull_none>;
2438 }; 2044 };
2439 }; 2045 };
2440 }; 2046 };
2441 }; 2047 };
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