1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /* 2 /*
3 * Copyright (c) 2018 Fuzhou Rockchip Electron 3 * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd
4 */ 4 */
5 5
6 #include <dt-bindings/clock/px30-cru.h> 6 #include <dt-bindings/clock/px30-cru.h>
7 #include <dt-bindings/gpio/gpio.h> 7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/interrupt-controller/arm 8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/interrupt-controller/irq 9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/pinctrl/rockchip.h> 10 #include <dt-bindings/pinctrl/rockchip.h>
11 #include <dt-bindings/power/px30-power.h> 11 #include <dt-bindings/power/px30-power.h>
12 #include <dt-bindings/soc/rockchip,boot-mode.h 12 #include <dt-bindings/soc/rockchip,boot-mode.h>
13 #include <dt-bindings/thermal/thermal.h> <<
14 13
15 / { 14 / {
16 compatible = "rockchip,px30"; 15 compatible = "rockchip,px30";
17 16
18 interrupt-parent = <&gic>; 17 interrupt-parent = <&gic>;
19 #address-cells = <2>; 18 #address-cells = <2>;
20 #size-cells = <2>; 19 #size-cells = <2>;
21 20
22 aliases { 21 aliases {
>> 22 ethernet0 = &gmac;
23 i2c0 = &i2c0; 23 i2c0 = &i2c0;
24 i2c1 = &i2c1; 24 i2c1 = &i2c1;
25 i2c2 = &i2c2; 25 i2c2 = &i2c2;
26 i2c3 = &i2c3; 26 i2c3 = &i2c3;
27 serial0 = &uart0; 27 serial0 = &uart0;
28 serial1 = &uart1; 28 serial1 = &uart1;
29 serial2 = &uart2; 29 serial2 = &uart2;
30 serial3 = &uart3; 30 serial3 = &uart3;
31 serial4 = &uart4; 31 serial4 = &uart4;
32 serial5 = &uart5; 32 serial5 = &uart5;
33 spi0 = &spi0; 33 spi0 = &spi0;
34 spi1 = &spi1; 34 spi1 = &spi1;
35 }; 35 };
36 36
37 cpus { 37 cpus {
38 #address-cells = <2>; 38 #address-cells = <2>;
39 #size-cells = <0>; 39 #size-cells = <0>;
40 40
41 cpu0: cpu@0 { 41 cpu0: cpu@0 {
42 device_type = "cpu"; 42 device_type = "cpu";
43 compatible = "arm,cort 43 compatible = "arm,cortex-a35";
44 reg = <0x0 0x0>; 44 reg = <0x0 0x0>;
45 enable-method = "psci" 45 enable-method = "psci";
46 clocks = <&cru ARMCLK> 46 clocks = <&cru ARMCLK>;
47 #cooling-cells = <2>; 47 #cooling-cells = <2>;
48 cpu-idle-states = <&CP 48 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
49 dynamic-power-coeffici 49 dynamic-power-coefficient = <90>;
50 operating-points-v2 = 50 operating-points-v2 = <&cpu0_opp_table>;
51 }; 51 };
52 52
53 cpu1: cpu@1 { 53 cpu1: cpu@1 {
54 device_type = "cpu"; 54 device_type = "cpu";
55 compatible = "arm,cort 55 compatible = "arm,cortex-a35";
56 reg = <0x0 0x1>; 56 reg = <0x0 0x1>;
57 enable-method = "psci" 57 enable-method = "psci";
58 clocks = <&cru ARMCLK> 58 clocks = <&cru ARMCLK>;
59 #cooling-cells = <2>; 59 #cooling-cells = <2>;
60 cpu-idle-states = <&CP 60 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
61 dynamic-power-coeffici 61 dynamic-power-coefficient = <90>;
62 operating-points-v2 = 62 operating-points-v2 = <&cpu0_opp_table>;
63 }; 63 };
64 64
65 cpu2: cpu@2 { 65 cpu2: cpu@2 {
66 device_type = "cpu"; 66 device_type = "cpu";
67 compatible = "arm,cort 67 compatible = "arm,cortex-a35";
68 reg = <0x0 0x2>; 68 reg = <0x0 0x2>;
69 enable-method = "psci" 69 enable-method = "psci";
70 clocks = <&cru ARMCLK> 70 clocks = <&cru ARMCLK>;
71 #cooling-cells = <2>; 71 #cooling-cells = <2>;
72 cpu-idle-states = <&CP 72 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
73 dynamic-power-coeffici 73 dynamic-power-coefficient = <90>;
74 operating-points-v2 = 74 operating-points-v2 = <&cpu0_opp_table>;
75 }; 75 };
76 76
77 cpu3: cpu@3 { 77 cpu3: cpu@3 {
78 device_type = "cpu"; 78 device_type = "cpu";
79 compatible = "arm,cort 79 compatible = "arm,cortex-a35";
80 reg = <0x0 0x3>; 80 reg = <0x0 0x3>;
81 enable-method = "psci" 81 enable-method = "psci";
82 clocks = <&cru ARMCLK> 82 clocks = <&cru ARMCLK>;
83 #cooling-cells = <2>; 83 #cooling-cells = <2>;
84 cpu-idle-states = <&CP 84 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
85 dynamic-power-coeffici 85 dynamic-power-coefficient = <90>;
86 operating-points-v2 = 86 operating-points-v2 = <&cpu0_opp_table>;
87 }; 87 };
88 88
89 idle-states { 89 idle-states {
90 entry-method = "psci"; 90 entry-method = "psci";
91 91
92 CPU_SLEEP: cpu-sleep { 92 CPU_SLEEP: cpu-sleep {
93 compatible = " 93 compatible = "arm,idle-state";
94 local-timer-st 94 local-timer-stop;
95 arm,psci-suspe 95 arm,psci-suspend-param = <0x0010000>;
96 entry-latency- 96 entry-latency-us = <120>;
97 exit-latency-u 97 exit-latency-us = <250>;
98 min-residency- 98 min-residency-us = <900>;
99 }; 99 };
100 100
101 CLUSTER_SLEEP: cluster 101 CLUSTER_SLEEP: cluster-sleep {
102 compatible = " 102 compatible = "arm,idle-state";
103 local-timer-st 103 local-timer-stop;
104 arm,psci-suspe 104 arm,psci-suspend-param = <0x1010000>;
105 entry-latency- 105 entry-latency-us = <400>;
106 exit-latency-u 106 exit-latency-us = <500>;
107 min-residency- 107 min-residency-us = <2000>;
108 }; 108 };
109 }; 109 };
110 }; 110 };
111 111
112 cpu0_opp_table: opp-table-0 { !! 112 cpu0_opp_table: cpu0-opp-table {
113 compatible = "operating-points 113 compatible = "operating-points-v2";
114 opp-shared; 114 opp-shared;
115 115
>> 116 opp-408000000 {
>> 117 opp-hz = /bits/ 64 <408000000>;
>> 118 opp-microvolt = <950000 950000 1350000>;
>> 119 clock-latency-ns = <40000>;
>> 120 opp-suspend;
>> 121 };
116 opp-600000000 { 122 opp-600000000 {
117 opp-hz = /bits/ 64 <60 123 opp-hz = /bits/ 64 <600000000>;
118 opp-microvolt = <95000 124 opp-microvolt = <950000 950000 1350000>;
119 clock-latency-ns = <40 125 clock-latency-ns = <40000>;
120 opp-suspend; <<
121 }; 126 };
122 opp-816000000 { 127 opp-816000000 {
123 opp-hz = /bits/ 64 <81 128 opp-hz = /bits/ 64 <816000000>;
124 opp-microvolt = <10500 129 opp-microvolt = <1050000 1050000 1350000>;
125 clock-latency-ns = <40 130 clock-latency-ns = <40000>;
126 }; 131 };
127 opp-1008000000 { 132 opp-1008000000 {
128 opp-hz = /bits/ 64 <10 133 opp-hz = /bits/ 64 <1008000000>;
129 opp-microvolt = <11750 134 opp-microvolt = <1175000 1175000 1350000>;
130 clock-latency-ns = <40 135 clock-latency-ns = <40000>;
131 }; 136 };
132 opp-1200000000 { 137 opp-1200000000 {
133 opp-hz = /bits/ 64 <12 138 opp-hz = /bits/ 64 <1200000000>;
134 opp-microvolt = <13000 139 opp-microvolt = <1300000 1300000 1350000>;
135 clock-latency-ns = <40 140 clock-latency-ns = <40000>;
136 }; 141 };
137 opp-1296000000 { 142 opp-1296000000 {
138 opp-hz = /bits/ 64 <12 143 opp-hz = /bits/ 64 <1296000000>;
139 opp-microvolt = <13500 144 opp-microvolt = <1350000 1350000 1350000>;
140 clock-latency-ns = <40 145 clock-latency-ns = <40000>;
141 }; 146 };
142 }; 147 };
143 148
144 arm-pmu { 149 arm-pmu {
145 compatible = "arm,cortex-a35-p !! 150 compatible = "arm,cortex-a53-pmu";
146 interrupts = <GIC_SPI 100 IRQ_ 151 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
147 <GIC_SPI 101 IRQ_ 152 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
148 <GIC_SPI 102 IRQ_ 153 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
149 <GIC_SPI 103 IRQ_ 154 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
150 interrupt-affinity = <&cpu0>, 155 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
151 }; 156 };
152 157
153 display_subsystem: display-subsystem { 158 display_subsystem: display-subsystem {
154 compatible = "rockchip,display 159 compatible = "rockchip,display-subsystem";
155 ports = <&vopb_out>, <&vopl_ou 160 ports = <&vopb_out>, <&vopl_out>;
156 status = "disabled"; 161 status = "disabled";
157 }; 162 };
158 163
159 gmac_clkin: external-gmac-clock { 164 gmac_clkin: external-gmac-clock {
160 compatible = "fixed-clock"; 165 compatible = "fixed-clock";
161 clock-frequency = <50000000>; 166 clock-frequency = <50000000>;
162 clock-output-names = "gmac_clk 167 clock-output-names = "gmac_clkin";
163 #clock-cells = <0>; 168 #clock-cells = <0>;
164 }; 169 };
165 170
166 psci { 171 psci {
167 compatible = "arm,psci-1.0"; 172 compatible = "arm,psci-1.0";
168 method = "smc"; 173 method = "smc";
169 }; 174 };
170 175
171 timer { 176 timer {
172 compatible = "arm,armv8-timer" 177 compatible = "arm,armv8-timer";
173 interrupts = <GIC_PPI 13 (GIC_ 178 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
174 <GIC_PPI 14 (GIC_ 179 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
175 <GIC_PPI 11 (GIC_ 180 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
176 <GIC_PPI 10 (GIC_ 181 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
177 }; 182 };
178 183
179 thermal_zones: thermal-zones { <<
180 soc_thermal: soc-thermal { <<
181 polling-delay-passive <<
182 polling-delay = <1000> <<
183 sustainable-power = <7 <<
184 thermal-sensors = <&ts <<
185 <<
186 trips { <<
187 threshold: tri <<
188 temper <<
189 hyster <<
190 type = <<
191 }; <<
192 <<
193 target: trip-p <<
194 temper <<
195 hyster <<
196 type = <<
197 }; <<
198 <<
199 soc_crit: soc- <<
200 temper <<
201 hyster <<
202 type = <<
203 }; <<
204 }; <<
205 <<
206 cooling-maps { <<
207 map0 { <<
208 trip = <<
209 coolin <<
210 contri <<
211 }; <<
212 }; <<
213 }; <<
214 <<
215 gpu_thermal: gpu-thermal { <<
216 polling-delay-passive <<
217 polling-delay = <1000> <<
218 thermal-sensors = <&ts <<
219 <<
220 trips { <<
221 gpu_threshold: <<
222 temper <<
223 hyster <<
224 type = <<
225 }; <<
226 <<
227 gpu_target: gp <<
228 temper <<
229 hyster <<
230 type = <<
231 }; <<
232 <<
233 gpu_crit: gpu- <<
234 temper <<
235 hyster <<
236 type = <<
237 }; <<
238 }; <<
239 <<
240 cooling-maps { <<
241 map0 { <<
242 trip = <<
243 coolin <<
244 }; <<
245 }; <<
246 }; <<
247 }; <<
248 <<
249 xin24m: xin24m { 184 xin24m: xin24m {
250 compatible = "fixed-clock"; 185 compatible = "fixed-clock";
251 #clock-cells = <0>; 186 #clock-cells = <0>;
252 clock-frequency = <24000000>; 187 clock-frequency = <24000000>;
253 clock-output-names = "xin24m"; 188 clock-output-names = "xin24m";
254 }; 189 };
255 190
256 pmu: power-management@ff000000 { 191 pmu: power-management@ff000000 {
257 compatible = "rockchip,px30-pm 192 compatible = "rockchip,px30-pmu", "syscon", "simple-mfd";
258 reg = <0x0 0xff000000 0x0 0x10 193 reg = <0x0 0xff000000 0x0 0x1000>;
259 194
260 power: power-controller { 195 power: power-controller {
261 compatible = "rockchip 196 compatible = "rockchip,px30-power-controller";
262 #power-domain-cells = 197 #power-domain-cells = <1>;
263 #address-cells = <1>; 198 #address-cells = <1>;
264 #size-cells = <0>; 199 #size-cells = <0>;
265 200
266 /* These power domains 201 /* These power domains are grouped by VD_LOGIC */
267 power-domain@PX30_PD_U !! 202 pd_usb@PX30_PD_USB {
268 reg = <PX30_PD 203 reg = <PX30_PD_USB>;
269 clocks = <&cru 204 clocks = <&cru HCLK_HOST>,
270 <&cru 205 <&cru HCLK_OTG>,
271 <&cru 206 <&cru SCLK_OTG_ADP>;
272 pm_qos = <&qos 207 pm_qos = <&qos_usb_host>, <&qos_usb_otg>;
273 #power-domain- <<
274 }; 208 };
275 power-domain@PX30_PD_S !! 209 pd_sdcard@PX30_PD_SDCARD {
276 reg = <PX30_PD 210 reg = <PX30_PD_SDCARD>;
277 clocks = <&cru 211 clocks = <&cru HCLK_SDMMC>,
278 <&cru 212 <&cru SCLK_SDMMC>;
279 pm_qos = <&qos 213 pm_qos = <&qos_sdmmc>;
280 #power-domain- <<
281 }; 214 };
282 power-domain@PX30_PD_G !! 215 pd_gmac@PX30_PD_GMAC {
283 reg = <PX30_PD 216 reg = <PX30_PD_GMAC>;
284 clocks = <&cru 217 clocks = <&cru ACLK_GMAC>,
285 <&cru 218 <&cru PCLK_GMAC>,
286 <&cru 219 <&cru SCLK_MAC_REF>,
287 <&cru 220 <&cru SCLK_GMAC_RX_TX>;
288 pm_qos = <&qos 221 pm_qos = <&qos_gmac>;
289 #power-domain- <<
290 }; 222 };
291 power-domain@PX30_PD_M !! 223 pd_mmc_nand@PX30_PD_MMC_NAND {
292 reg = <PX30_PD 224 reg = <PX30_PD_MMC_NAND>;
293 clocks = <&cru !! 225 clocks = <&cru HCLK_NANDC>,
294 <&cru !! 226 <&cru HCLK_EMMC>,
295 <&cru !! 227 <&cru HCLK_SDIO>,
296 <&cru !! 228 <&cru HCLK_SFC>,
297 <&cru !! 229 <&cru SCLK_EMMC>,
298 <&cru !! 230 <&cru SCLK_NANDC>,
299 <&cru !! 231 <&cru SCLK_SDIO>,
300 <&cru !! 232 <&cru SCLK_SFC>;
301 pm_qos = <&qos 233 pm_qos = <&qos_emmc>, <&qos_nand>,
302 <&qos 234 <&qos_sdio>, <&qos_sfc>;
303 #power-domain- <<
304 }; 235 };
305 power-domain@PX30_PD_V !! 236 pd_vpu@PX30_PD_VPU {
306 reg = <PX30_PD 237 reg = <PX30_PD_VPU>;
307 clocks = <&cru 238 clocks = <&cru ACLK_VPU>,
308 <&cru 239 <&cru HCLK_VPU>,
309 <&cru 240 <&cru SCLK_CORE_VPU>;
310 pm_qos = <&qos 241 pm_qos = <&qos_vpu>, <&qos_vpu_r128>;
311 #power-domain- <<
312 }; 242 };
313 power-domain@PX30_PD_V !! 243 pd_vo@PX30_PD_VO {
314 reg = <PX30_PD 244 reg = <PX30_PD_VO>;
315 clocks = <&cru 245 clocks = <&cru ACLK_RGA>,
316 <&cru 246 <&cru ACLK_VOPB>,
317 <&cru 247 <&cru ACLK_VOPL>,
318 <&cru 248 <&cru DCLK_VOPB>,
319 <&cru 249 <&cru DCLK_VOPL>,
320 <&cru 250 <&cru HCLK_RGA>,
321 <&cru 251 <&cru HCLK_VOPB>,
322 <&cru 252 <&cru HCLK_VOPL>,
323 <&cru 253 <&cru PCLK_MIPI_DSI>,
324 <&cru 254 <&cru SCLK_RGA_CORE>,
325 <&cru 255 <&cru SCLK_VOPB_PWM>;
326 pm_qos = <&qos 256 pm_qos = <&qos_rga_rd>, <&qos_rga_wr>,
327 <&qos 257 <&qos_vop_m0>, <&qos_vop_m1>;
328 #power-domain- <<
329 }; 258 };
330 power-domain@PX30_PD_V !! 259 pd_vi@PX30_PD_VI {
331 reg = <PX30_PD 260 reg = <PX30_PD_VI>;
332 clocks = <&cru 261 clocks = <&cru ACLK_CIF>,
333 <&cru 262 <&cru ACLK_ISP>,
334 <&cru 263 <&cru HCLK_CIF>,
335 <&cru 264 <&cru HCLK_ISP>,
336 <&cru 265 <&cru SCLK_ISP>;
337 pm_qos = <&qos 266 pm_qos = <&qos_isp_128>, <&qos_isp_rd>,
338 <&qos 267 <&qos_isp_wr>, <&qos_isp_m1>,
339 <&qos 268 <&qos_vip>;
340 #power-domain- <<
341 }; 269 };
342 power-domain@PX30_PD_G !! 270 pd_gpu@PX30_PD_GPU {
343 reg = <PX30_PD 271 reg = <PX30_PD_GPU>;
344 clocks = <&cru 272 clocks = <&cru SCLK_GPU>;
345 pm_qos = <&qos 273 pm_qos = <&qos_gpu>;
346 #power-domain- <<
347 }; 274 };
348 }; 275 };
349 }; 276 };
350 277
351 pmugrf: syscon@ff010000 { 278 pmugrf: syscon@ff010000 {
352 compatible = "rockchip,px30-pm 279 compatible = "rockchip,px30-pmugrf", "syscon", "simple-mfd";
353 reg = <0x0 0xff010000 0x0 0x10 280 reg = <0x0 0xff010000 0x0 0x1000>;
354 #address-cells = <1>; 281 #address-cells = <1>;
355 #size-cells = <1>; 282 #size-cells = <1>;
356 283
357 pmu_io_domains: io-domains { 284 pmu_io_domains: io-domains {
358 compatible = "rockchip 285 compatible = "rockchip,px30-pmu-io-voltage-domain";
359 status = "disabled"; 286 status = "disabled";
360 }; 287 };
361 288
362 reboot-mode { 289 reboot-mode {
363 compatible = "syscon-r 290 compatible = "syscon-reboot-mode";
364 offset = <0x200>; 291 offset = <0x200>;
365 mode-bootloader = <BOO 292 mode-bootloader = <BOOT_BL_DOWNLOAD>;
366 mode-fastboot = <BOOT_ 293 mode-fastboot = <BOOT_FASTBOOT>;
367 mode-loader = <BOOT_BL 294 mode-loader = <BOOT_BL_DOWNLOAD>;
368 mode-normal = <BOOT_NO 295 mode-normal = <BOOT_NORMAL>;
369 mode-recovery = <BOOT_ 296 mode-recovery = <BOOT_RECOVERY>;
370 }; 297 };
371 }; 298 };
372 299
373 uart0: serial@ff030000 { 300 uart0: serial@ff030000 {
374 compatible = "rockchip,px30-ua 301 compatible = "rockchip,px30-uart", "snps,dw-apb-uart";
375 reg = <0x0 0xff030000 0x0 0x10 302 reg = <0x0 0xff030000 0x0 0x100>;
376 interrupts = <GIC_SPI 15 IRQ_T 303 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
377 clocks = <&pmucru SCLK_UART0_P 304 clocks = <&pmucru SCLK_UART0_PMU>, <&pmucru PCLK_UART0_PMU>;
378 clock-names = "baudclk", "apb_ 305 clock-names = "baudclk", "apb_pclk";
379 dmas = <&dmac 0>, <&dmac 1>; 306 dmas = <&dmac 0>, <&dmac 1>;
380 dma-names = "tx", "rx"; 307 dma-names = "tx", "rx";
381 reg-shift = <2>; 308 reg-shift = <2>;
382 reg-io-width = <4>; 309 reg-io-width = <4>;
383 pinctrl-names = "default"; 310 pinctrl-names = "default";
384 pinctrl-0 = <&uart0_xfer &uart 311 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
385 status = "disabled"; 312 status = "disabled";
386 }; 313 };
387 314
388 i2s0_8ch: i2s@ff060000 { <<
389 compatible = "rockchip,px30-i2 <<
390 reg = <0x0 0xff060000 0x0 0x10 <<
391 interrupts = <GIC_SPI 12 IRQ_T <<
392 clocks = <&cru SCLK_I2S0_TX>, <<
393 clock-names = "mclk_tx", "mclk <<
394 dmas = <&dmac 16>, <&dmac 17>; <<
395 dma-names = "tx", "rx"; <<
396 rockchip,grf = <&grf>; <<
397 resets = <&cru SRST_I2S0_TX>, <<
398 reset-names = "tx-m", "rx-m"; <<
399 pinctrl-names = "default"; <<
400 pinctrl-0 = <&i2s0_8ch_sclktx <<
401 &i2s0_8ch_lrcktx <<
402 &i2s0_8ch_sdo0 &i <<
403 &i2s0_8ch_sdo1 &i <<
404 &i2s0_8ch_sdo2 &i <<
405 &i2s0_8ch_sdo3 &i <<
406 #sound-dai-cells = <0>; <<
407 status = "disabled"; <<
408 }; <<
409 <<
410 i2s1_2ch: i2s@ff070000 { 315 i2s1_2ch: i2s@ff070000 {
411 compatible = "rockchip,px30-i2 316 compatible = "rockchip,px30-i2s", "rockchip,rk3066-i2s";
412 reg = <0x0 0xff070000 0x0 0x10 317 reg = <0x0 0xff070000 0x0 0x1000>;
413 interrupts = <GIC_SPI 13 IRQ_T 318 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
414 clocks = <&cru SCLK_I2S1>, <&c 319 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1>;
415 clock-names = "i2s_clk", "i2s_ 320 clock-names = "i2s_clk", "i2s_hclk";
416 dmas = <&dmac 18>, <&dmac 19>; 321 dmas = <&dmac 18>, <&dmac 19>;
417 dma-names = "tx", "rx"; 322 dma-names = "tx", "rx";
418 pinctrl-names = "default"; 323 pinctrl-names = "default";
419 pinctrl-0 = <&i2s1_2ch_sclk &i 324 pinctrl-0 = <&i2s1_2ch_sclk &i2s1_2ch_lrck
420 &i2s1_2ch_sdi &i2 325 &i2s1_2ch_sdi &i2s1_2ch_sdo>;
421 #sound-dai-cells = <0>; 326 #sound-dai-cells = <0>;
422 status = "disabled"; 327 status = "disabled";
423 }; 328 };
424 329
425 i2s2_2ch: i2s@ff080000 { 330 i2s2_2ch: i2s@ff080000 {
426 compatible = "rockchip,px30-i2 331 compatible = "rockchip,px30-i2s", "rockchip,rk3066-i2s";
427 reg = <0x0 0xff080000 0x0 0x10 332 reg = <0x0 0xff080000 0x0 0x1000>;
428 interrupts = <GIC_SPI 14 IRQ_T 333 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
429 clocks = <&cru SCLK_I2S2>, <&c 334 clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2>;
430 clock-names = "i2s_clk", "i2s_ 335 clock-names = "i2s_clk", "i2s_hclk";
431 dmas = <&dmac 20>, <&dmac 21>; 336 dmas = <&dmac 20>, <&dmac 21>;
432 dma-names = "tx", "rx"; 337 dma-names = "tx", "rx";
433 pinctrl-names = "default"; 338 pinctrl-names = "default";
434 pinctrl-0 = <&i2s2_2ch_sclk &i 339 pinctrl-0 = <&i2s2_2ch_sclk &i2s2_2ch_lrck
435 &i2s2_2ch_sdi &i2 340 &i2s2_2ch_sdi &i2s2_2ch_sdo>;
436 #sound-dai-cells = <0>; 341 #sound-dai-cells = <0>;
437 status = "disabled"; 342 status = "disabled";
438 }; 343 };
439 344
440 gic: interrupt-controller@ff131000 { 345 gic: interrupt-controller@ff131000 {
441 compatible = "arm,gic-400"; 346 compatible = "arm,gic-400";
442 #interrupt-cells = <3>; 347 #interrupt-cells = <3>;
443 #address-cells = <0>; 348 #address-cells = <0>;
444 interrupt-controller; 349 interrupt-controller;
445 reg = <0x0 0xff131000 0 0x1000 350 reg = <0x0 0xff131000 0 0x1000>,
446 <0x0 0xff132000 0 0x2000 351 <0x0 0xff132000 0 0x2000>,
447 <0x0 0xff134000 0 0x2000 352 <0x0 0xff134000 0 0x2000>,
448 <0x0 0xff136000 0 0x2000 353 <0x0 0xff136000 0 0x2000>;
449 interrupts = <GIC_PPI 9 354 interrupts = <GIC_PPI 9
450 (GIC_CPU_MASK_SIMPLE(4) 355 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
451 }; 356 };
452 357
453 grf: syscon@ff140000 { 358 grf: syscon@ff140000 {
454 compatible = "rockchip,px30-gr 359 compatible = "rockchip,px30-grf", "syscon", "simple-mfd";
455 reg = <0x0 0xff140000 0x0 0x10 360 reg = <0x0 0xff140000 0x0 0x1000>;
456 #address-cells = <1>; 361 #address-cells = <1>;
457 #size-cells = <1>; 362 #size-cells = <1>;
458 363
459 io_domains: io-domains { 364 io_domains: io-domains {
460 compatible = "rockchip 365 compatible = "rockchip,px30-io-voltage-domain";
461 status = "disabled"; 366 status = "disabled";
462 }; 367 };
463 <<
464 lvds: lvds { <<
465 compatible = "rockchip <<
466 phys = <&dsi_dphy>; <<
467 phy-names = "dphy"; <<
468 rockchip,grf = <&grf>; <<
469 rockchip,output = "lvd <<
470 status = "disabled"; <<
471 <<
472 ports { <<
473 #address-cells <<
474 #size-cells = <<
475 <<
476 lvds_in: port@ <<
477 reg = <<
478 #addre <<
479 #size- <<
480 <<
481 lvds_v <<
482 <<
483 <<
484 }; <<
485 <<
486 lvds_v <<
487 <<
488 <<
489 }; <<
490 }; <<
491 <<
492 lvds_out: port <<
493 reg = <<
494 }; <<
495 }; <<
496 }; <<
497 }; 368 };
498 369
499 uart1: serial@ff158000 { 370 uart1: serial@ff158000 {
500 compatible = "rockchip,px30-ua 371 compatible = "rockchip,px30-uart", "snps,dw-apb-uart";
501 reg = <0x0 0xff158000 0x0 0x10 372 reg = <0x0 0xff158000 0x0 0x100>;
502 interrupts = <GIC_SPI 16 IRQ_T 373 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
503 clocks = <&cru SCLK_UART1>, <& 374 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
504 clock-names = "baudclk", "apb_ 375 clock-names = "baudclk", "apb_pclk";
505 dmas = <&dmac 2>, <&dmac 3>; 376 dmas = <&dmac 2>, <&dmac 3>;
506 dma-names = "tx", "rx"; 377 dma-names = "tx", "rx";
507 reg-shift = <2>; 378 reg-shift = <2>;
508 reg-io-width = <4>; 379 reg-io-width = <4>;
509 pinctrl-names = "default"; 380 pinctrl-names = "default";
510 pinctrl-0 = <&uart1_xfer &uart 381 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
511 status = "disabled"; 382 status = "disabled";
512 }; 383 };
513 384
514 uart2: serial@ff160000 { 385 uart2: serial@ff160000 {
515 compatible = "rockchip,px30-ua 386 compatible = "rockchip,px30-uart", "snps,dw-apb-uart";
516 reg = <0x0 0xff160000 0x0 0x10 387 reg = <0x0 0xff160000 0x0 0x100>;
517 interrupts = <GIC_SPI 17 IRQ_T 388 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
518 clocks = <&cru SCLK_UART2>, <& 389 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
519 clock-names = "baudclk", "apb_ 390 clock-names = "baudclk", "apb_pclk";
520 dmas = <&dmac 4>, <&dmac 5>; 391 dmas = <&dmac 4>, <&dmac 5>;
521 dma-names = "tx", "rx"; 392 dma-names = "tx", "rx";
522 reg-shift = <2>; 393 reg-shift = <2>;
523 reg-io-width = <4>; 394 reg-io-width = <4>;
524 pinctrl-names = "default"; 395 pinctrl-names = "default";
525 pinctrl-0 = <&uart2m0_xfer>; 396 pinctrl-0 = <&uart2m0_xfer>;
526 status = "disabled"; 397 status = "disabled";
527 }; 398 };
528 399
529 uart3: serial@ff168000 { 400 uart3: serial@ff168000 {
530 compatible = "rockchip,px30-ua 401 compatible = "rockchip,px30-uart", "snps,dw-apb-uart";
531 reg = <0x0 0xff168000 0x0 0x10 402 reg = <0x0 0xff168000 0x0 0x100>;
532 interrupts = <GIC_SPI 18 IRQ_T 403 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
533 clocks = <&cru SCLK_UART3>, <& 404 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
534 clock-names = "baudclk", "apb_ 405 clock-names = "baudclk", "apb_pclk";
535 dmas = <&dmac 6>, <&dmac 7>; 406 dmas = <&dmac 6>, <&dmac 7>;
536 dma-names = "tx", "rx"; 407 dma-names = "tx", "rx";
537 reg-shift = <2>; 408 reg-shift = <2>;
538 reg-io-width = <4>; 409 reg-io-width = <4>;
539 pinctrl-names = "default"; 410 pinctrl-names = "default";
540 pinctrl-0 = <&uart3m1_xfer &ua 411 pinctrl-0 = <&uart3m1_xfer &uart3m1_cts &uart3m1_rts>;
541 status = "disabled"; 412 status = "disabled";
542 }; 413 };
543 414
544 uart4: serial@ff170000 { 415 uart4: serial@ff170000 {
545 compatible = "rockchip,px30-ua 416 compatible = "rockchip,px30-uart", "snps,dw-apb-uart";
546 reg = <0x0 0xff170000 0x0 0x10 417 reg = <0x0 0xff170000 0x0 0x100>;
547 interrupts = <GIC_SPI 19 IRQ_T 418 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
548 clocks = <&cru SCLK_UART4>, <& 419 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
549 clock-names = "baudclk", "apb_ 420 clock-names = "baudclk", "apb_pclk";
550 dmas = <&dmac 8>, <&dmac 9>; 421 dmas = <&dmac 8>, <&dmac 9>;
551 dma-names = "tx", "rx"; 422 dma-names = "tx", "rx";
552 reg-shift = <2>; 423 reg-shift = <2>;
553 reg-io-width = <4>; 424 reg-io-width = <4>;
554 pinctrl-names = "default"; 425 pinctrl-names = "default";
555 pinctrl-0 = <&uart4_xfer &uart 426 pinctrl-0 = <&uart4_xfer &uart4_cts &uart4_rts>;
556 status = "disabled"; 427 status = "disabled";
557 }; 428 };
558 429
559 uart5: serial@ff178000 { 430 uart5: serial@ff178000 {
560 compatible = "rockchip,px30-ua 431 compatible = "rockchip,px30-uart", "snps,dw-apb-uart";
561 reg = <0x0 0xff178000 0x0 0x10 432 reg = <0x0 0xff178000 0x0 0x100>;
562 interrupts = <GIC_SPI 20 IRQ_T 433 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
563 clocks = <&cru SCLK_UART5>, <& 434 clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>;
564 clock-names = "baudclk", "apb_ 435 clock-names = "baudclk", "apb_pclk";
565 dmas = <&dmac 10>, <&dmac 11>; 436 dmas = <&dmac 10>, <&dmac 11>;
566 dma-names = "tx", "rx"; 437 dma-names = "tx", "rx";
567 reg-shift = <2>; 438 reg-shift = <2>;
568 reg-io-width = <4>; 439 reg-io-width = <4>;
569 pinctrl-names = "default"; 440 pinctrl-names = "default";
570 pinctrl-0 = <&uart5_xfer &uart 441 pinctrl-0 = <&uart5_xfer &uart5_cts &uart5_rts>;
571 status = "disabled"; 442 status = "disabled";
572 }; 443 };
573 444
574 i2c0: i2c@ff180000 { 445 i2c0: i2c@ff180000 {
575 compatible = "rockchip,px30-i2 446 compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c";
576 reg = <0x0 0xff180000 0x0 0x10 447 reg = <0x0 0xff180000 0x0 0x1000>;
577 clocks = <&cru SCLK_I2C0>, <&c !! 448 clocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>;
578 clock-names = "i2c", "pclk"; 449 clock-names = "i2c", "pclk";
579 interrupts = <GIC_SPI 7 IRQ_TY 450 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
580 pinctrl-names = "default"; 451 pinctrl-names = "default";
581 pinctrl-0 = <&i2c0_xfer>; 452 pinctrl-0 = <&i2c0_xfer>;
582 #address-cells = <1>; 453 #address-cells = <1>;
583 #size-cells = <0>; 454 #size-cells = <0>;
584 status = "disabled"; 455 status = "disabled";
585 }; 456 };
586 457
587 i2c1: i2c@ff190000 { 458 i2c1: i2c@ff190000 {
588 compatible = "rockchip,px30-i2 459 compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c";
589 reg = <0x0 0xff190000 0x0 0x10 460 reg = <0x0 0xff190000 0x0 0x1000>;
590 clocks = <&cru SCLK_I2C1>, <&c 461 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
591 clock-names = "i2c", "pclk"; 462 clock-names = "i2c", "pclk";
592 interrupts = <GIC_SPI 8 IRQ_TY 463 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
593 pinctrl-names = "default"; 464 pinctrl-names = "default";
594 pinctrl-0 = <&i2c1_xfer>; 465 pinctrl-0 = <&i2c1_xfer>;
595 #address-cells = <1>; 466 #address-cells = <1>;
596 #size-cells = <0>; 467 #size-cells = <0>;
597 status = "disabled"; 468 status = "disabled";
598 }; 469 };
599 470
600 i2c2: i2c@ff1a0000 { 471 i2c2: i2c@ff1a0000 {
601 compatible = "rockchip,px30-i2 472 compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c";
602 reg = <0x0 0xff1a0000 0x0 0x10 473 reg = <0x0 0xff1a0000 0x0 0x1000>;
603 clocks = <&cru SCLK_I2C2>, <&c 474 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
604 clock-names = "i2c", "pclk"; 475 clock-names = "i2c", "pclk";
605 interrupts = <GIC_SPI 9 IRQ_TY 476 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
606 pinctrl-names = "default"; 477 pinctrl-names = "default";
607 pinctrl-0 = <&i2c2_xfer>; 478 pinctrl-0 = <&i2c2_xfer>;
608 #address-cells = <1>; 479 #address-cells = <1>;
609 #size-cells = <0>; 480 #size-cells = <0>;
610 status = "disabled"; 481 status = "disabled";
611 }; 482 };
612 483
613 i2c3: i2c@ff1b0000 { 484 i2c3: i2c@ff1b0000 {
614 compatible = "rockchip,px30-i2 485 compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c";
615 reg = <0x0 0xff1b0000 0x0 0x10 486 reg = <0x0 0xff1b0000 0x0 0x1000>;
616 clocks = <&cru SCLK_I2C3>, <&c 487 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
617 clock-names = "i2c", "pclk"; 488 clock-names = "i2c", "pclk";
618 interrupts = <GIC_SPI 10 IRQ_T 489 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
619 pinctrl-names = "default"; 490 pinctrl-names = "default";
620 pinctrl-0 = <&i2c3_xfer>; 491 pinctrl-0 = <&i2c3_xfer>;
621 #address-cells = <1>; 492 #address-cells = <1>;
622 #size-cells = <0>; 493 #size-cells = <0>;
623 status = "disabled"; 494 status = "disabled";
624 }; 495 };
625 496
626 spi0: spi@ff1d0000 { 497 spi0: spi@ff1d0000 {
627 compatible = "rockchip,px30-sp 498 compatible = "rockchip,px30-spi", "rockchip,rk3066-spi";
628 reg = <0x0 0xff1d0000 0x0 0x10 499 reg = <0x0 0xff1d0000 0x0 0x1000>;
629 interrupts = <GIC_SPI 26 IRQ_T 500 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
630 clocks = <&cru SCLK_SPI0>, <&c 501 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
631 clock-names = "spiclk", "apb_p 502 clock-names = "spiclk", "apb_pclk";
632 dmas = <&dmac 12>, <&dmac 13>; 503 dmas = <&dmac 12>, <&dmac 13>;
633 dma-names = "tx", "rx"; 504 dma-names = "tx", "rx";
634 num-cs = <2>; <<
635 pinctrl-names = "default"; 505 pinctrl-names = "default";
636 pinctrl-0 = <&spi0_clk &spi0_c 506 pinctrl-0 = <&spi0_clk &spi0_csn &spi0_miso &spi0_mosi>;
637 #address-cells = <1>; 507 #address-cells = <1>;
638 #size-cells = <0>; 508 #size-cells = <0>;
639 status = "disabled"; 509 status = "disabled";
640 }; 510 };
641 511
642 spi1: spi@ff1d8000 { 512 spi1: spi@ff1d8000 {
643 compatible = "rockchip,px30-sp 513 compatible = "rockchip,px30-spi", "rockchip,rk3066-spi";
644 reg = <0x0 0xff1d8000 0x0 0x10 514 reg = <0x0 0xff1d8000 0x0 0x1000>;
645 interrupts = <GIC_SPI 27 IRQ_T 515 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
646 clocks = <&cru SCLK_SPI1>, <&c 516 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
647 clock-names = "spiclk", "apb_p 517 clock-names = "spiclk", "apb_pclk";
648 dmas = <&dmac 14>, <&dmac 15>; 518 dmas = <&dmac 14>, <&dmac 15>;
649 dma-names = "tx", "rx"; 519 dma-names = "tx", "rx";
650 num-cs = <2>; <<
651 pinctrl-names = "default"; 520 pinctrl-names = "default";
652 pinctrl-0 = <&spi1_clk &spi1_c 521 pinctrl-0 = <&spi1_clk &spi1_csn0 &spi1_csn1 &spi1_miso &spi1_mosi>;
653 #address-cells = <1>; 522 #address-cells = <1>;
654 #size-cells = <0>; 523 #size-cells = <0>;
655 status = "disabled"; 524 status = "disabled";
656 }; 525 };
657 526
658 wdt: watchdog@ff1e0000 { 527 wdt: watchdog@ff1e0000 {
659 compatible = "rockchip,px30-wd !! 528 compatible = "snps,dw-wdt";
660 reg = <0x0 0xff1e0000 0x0 0x10 529 reg = <0x0 0xff1e0000 0x0 0x100>;
661 clocks = <&cru PCLK_WDT_NS>; 530 clocks = <&cru PCLK_WDT_NS>;
662 interrupts = <GIC_SPI 37 IRQ_T 531 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
663 status = "disabled"; 532 status = "disabled";
664 }; 533 };
665 534
666 pwm0: pwm@ff200000 { 535 pwm0: pwm@ff200000 {
667 compatible = "rockchip,px30-pw 536 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
668 reg = <0x0 0xff200000 0x0 0x10 537 reg = <0x0 0xff200000 0x0 0x10>;
669 clocks = <&cru SCLK_PWM0>, <&c 538 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
670 clock-names = "pwm", "pclk"; 539 clock-names = "pwm", "pclk";
671 pinctrl-names = "default"; 540 pinctrl-names = "default";
672 pinctrl-0 = <&pwm0_pin>; 541 pinctrl-0 = <&pwm0_pin>;
673 #pwm-cells = <3>; 542 #pwm-cells = <3>;
674 status = "disabled"; 543 status = "disabled";
675 }; 544 };
676 545
677 pwm1: pwm@ff200010 { 546 pwm1: pwm@ff200010 {
678 compatible = "rockchip,px30-pw 547 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
679 reg = <0x0 0xff200010 0x0 0x10 548 reg = <0x0 0xff200010 0x0 0x10>;
680 clocks = <&cru SCLK_PWM0>, <&c 549 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
681 clock-names = "pwm", "pclk"; 550 clock-names = "pwm", "pclk";
682 pinctrl-names = "default"; 551 pinctrl-names = "default";
683 pinctrl-0 = <&pwm1_pin>; 552 pinctrl-0 = <&pwm1_pin>;
684 #pwm-cells = <3>; 553 #pwm-cells = <3>;
685 status = "disabled"; 554 status = "disabled";
686 }; 555 };
687 556
688 pwm2: pwm@ff200020 { 557 pwm2: pwm@ff200020 {
689 compatible = "rockchip,px30-pw 558 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
690 reg = <0x0 0xff200020 0x0 0x10 559 reg = <0x0 0xff200020 0x0 0x10>;
691 clocks = <&cru SCLK_PWM0>, <&c 560 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
692 clock-names = "pwm", "pclk"; 561 clock-names = "pwm", "pclk";
693 pinctrl-names = "default"; 562 pinctrl-names = "default";
694 pinctrl-0 = <&pwm2_pin>; 563 pinctrl-0 = <&pwm2_pin>;
695 #pwm-cells = <3>; 564 #pwm-cells = <3>;
696 status = "disabled"; 565 status = "disabled";
697 }; 566 };
698 567
699 pwm3: pwm@ff200030 { 568 pwm3: pwm@ff200030 {
700 compatible = "rockchip,px30-pw 569 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
701 reg = <0x0 0xff200030 0x0 0x10 570 reg = <0x0 0xff200030 0x0 0x10>;
702 clocks = <&cru SCLK_PWM0>, <&c 571 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
703 clock-names = "pwm", "pclk"; 572 clock-names = "pwm", "pclk";
704 pinctrl-names = "default"; 573 pinctrl-names = "default";
705 pinctrl-0 = <&pwm3_pin>; 574 pinctrl-0 = <&pwm3_pin>;
706 #pwm-cells = <3>; 575 #pwm-cells = <3>;
707 status = "disabled"; 576 status = "disabled";
708 }; 577 };
709 578
710 pwm4: pwm@ff208000 { 579 pwm4: pwm@ff208000 {
711 compatible = "rockchip,px30-pw 580 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
712 reg = <0x0 0xff208000 0x0 0x10 581 reg = <0x0 0xff208000 0x0 0x10>;
713 clocks = <&cru SCLK_PWM1>, <&c 582 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>;
714 clock-names = "pwm", "pclk"; 583 clock-names = "pwm", "pclk";
715 pinctrl-names = "default"; 584 pinctrl-names = "default";
716 pinctrl-0 = <&pwm4_pin>; 585 pinctrl-0 = <&pwm4_pin>;
717 #pwm-cells = <3>; 586 #pwm-cells = <3>;
718 status = "disabled"; 587 status = "disabled";
719 }; 588 };
720 589
721 pwm5: pwm@ff208010 { 590 pwm5: pwm@ff208010 {
722 compatible = "rockchip,px30-pw 591 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
723 reg = <0x0 0xff208010 0x0 0x10 592 reg = <0x0 0xff208010 0x0 0x10>;
724 clocks = <&cru SCLK_PWM1>, <&c 593 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>;
725 clock-names = "pwm", "pclk"; 594 clock-names = "pwm", "pclk";
726 pinctrl-names = "default"; 595 pinctrl-names = "default";
727 pinctrl-0 = <&pwm5_pin>; 596 pinctrl-0 = <&pwm5_pin>;
728 #pwm-cells = <3>; 597 #pwm-cells = <3>;
729 status = "disabled"; 598 status = "disabled";
730 }; 599 };
731 600
732 pwm6: pwm@ff208020 { 601 pwm6: pwm@ff208020 {
733 compatible = "rockchip,px30-pw 602 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
734 reg = <0x0 0xff208020 0x0 0x10 603 reg = <0x0 0xff208020 0x0 0x10>;
735 clocks = <&cru SCLK_PWM1>, <&c 604 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>;
736 clock-names = "pwm", "pclk"; 605 clock-names = "pwm", "pclk";
737 pinctrl-names = "default"; 606 pinctrl-names = "default";
738 pinctrl-0 = <&pwm6_pin>; 607 pinctrl-0 = <&pwm6_pin>;
739 #pwm-cells = <3>; 608 #pwm-cells = <3>;
740 status = "disabled"; 609 status = "disabled";
741 }; 610 };
742 611
743 pwm7: pwm@ff208030 { 612 pwm7: pwm@ff208030 {
744 compatible = "rockchip,px30-pw 613 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
745 reg = <0x0 0xff208030 0x0 0x10 614 reg = <0x0 0xff208030 0x0 0x10>;
746 clocks = <&cru SCLK_PWM1>, <&c 615 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>;
747 clock-names = "pwm", "pclk"; 616 clock-names = "pwm", "pclk";
748 pinctrl-names = "default"; 617 pinctrl-names = "default";
749 pinctrl-0 = <&pwm7_pin>; 618 pinctrl-0 = <&pwm7_pin>;
750 #pwm-cells = <3>; 619 #pwm-cells = <3>;
751 status = "disabled"; 620 status = "disabled";
752 }; 621 };
753 622
754 rktimer: timer@ff210000 { 623 rktimer: timer@ff210000 {
755 compatible = "rockchip,px30-ti 624 compatible = "rockchip,px30-timer", "rockchip,rk3288-timer";
756 reg = <0x0 0xff210000 0x0 0x10 625 reg = <0x0 0xff210000 0x0 0x1000>;
757 interrupts = <GIC_SPI 30 IRQ_T 626 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
758 clocks = <&cru PCLK_TIMER>, <& 627 clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER0>;
759 clock-names = "pclk", "timer"; 628 clock-names = "pclk", "timer";
760 }; 629 };
761 630
762 dmac: dma-controller@ff240000 { !! 631 amba {
763 compatible = "arm,pl330", "arm !! 632 compatible = "simple-bus";
764 reg = <0x0 0xff240000 0x0 0x40 !! 633 #address-cells = <2>;
765 interrupts = <GIC_SPI 1 IRQ_TY !! 634 #size-cells = <2>;
766 <GIC_SPI 2 IRQ_TY !! 635 ranges;
767 arm,pl330-periph-burst; !! 636
768 clocks = <&cru ACLK_DMAC>; !! 637 dmac: dmac@ff240000 {
769 clock-names = "apb_pclk"; !! 638 compatible = "arm,pl330", "arm,primecell";
770 #dma-cells = <1>; !! 639 reg = <0x0 0xff240000 0x0 0x4000>;
771 }; !! 640 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
772 !! 641 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
773 tsadc: tsadc@ff280000 { !! 642 clocks = <&cru ACLK_DMAC>;
774 compatible = "rockchip,px30-ts !! 643 clock-names = "apb_pclk";
775 reg = <0x0 0xff280000 0x0 0x10 !! 644 #dma-cells = <1>;
776 interrupts = <GIC_SPI 36 IRQ_T !! 645 };
777 assigned-clocks = <&cru SCLK_T <<
778 assigned-clock-rates = <50000> <<
779 clocks = <&cru SCLK_TSADC>, <& <<
780 clock-names = "tsadc", "apb_pc <<
781 resets = <&cru SRST_TSADC>; <<
782 reset-names = "tsadc-apb"; <<
783 rockchip,grf = <&grf>; <<
784 rockchip,hw-tshut-temp = <1200 <<
785 pinctrl-names = "init", "defau <<
786 pinctrl-0 = <&tsadc_otp_pin>; <<
787 pinctrl-1 = <&tsadc_otp_out>; <<
788 pinctrl-2 = <&tsadc_otp_pin>; <<
789 #thermal-sensor-cells = <1>; <<
790 status = "disabled"; <<
791 }; 646 };
792 647
793 saradc: saradc@ff288000 { 648 saradc: saradc@ff288000 {
794 compatible = "rockchip,px30-sa 649 compatible = "rockchip,px30-saradc", "rockchip,rk3399-saradc";
795 reg = <0x0 0xff288000 0x0 0x10 650 reg = <0x0 0xff288000 0x0 0x100>;
796 interrupts = <GIC_SPI 84 IRQ_T 651 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
797 #io-channel-cells = <1>; 652 #io-channel-cells = <1>;
798 clocks = <&cru SCLK_SARADC>, < 653 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
799 clock-names = "saradc", "apb_p 654 clock-names = "saradc", "apb_pclk";
800 resets = <&cru SRST_SARADC_P>; 655 resets = <&cru SRST_SARADC_P>;
801 reset-names = "saradc-apb"; 656 reset-names = "saradc-apb";
802 status = "disabled"; 657 status = "disabled";
803 }; 658 };
804 659
805 otp: nvmem@ff290000 { 660 otp: nvmem@ff290000 {
806 compatible = "rockchip,px30-ot 661 compatible = "rockchip,px30-otp";
807 reg = <0x0 0xff290000 0x0 0x40 662 reg = <0x0 0xff290000 0x0 0x4000>;
808 clocks = <&cru SCLK_OTP_USR>, 663 clocks = <&cru SCLK_OTP_USR>, <&cru PCLK_OTP_NS>,
809 <&cru PCLK_OTP_PHY>; 664 <&cru PCLK_OTP_PHY>;
810 clock-names = "otp", "apb_pclk 665 clock-names = "otp", "apb_pclk", "phy";
811 resets = <&cru SRST_OTP_PHY>; 666 resets = <&cru SRST_OTP_PHY>;
812 reset-names = "phy"; 667 reset-names = "phy";
813 #address-cells = <1>; 668 #address-cells = <1>;
814 #size-cells = <1>; 669 #size-cells = <1>;
815 670
816 /* Data cells */ 671 /* Data cells */
817 cpu_id: id@7 { 672 cpu_id: id@7 {
818 reg = <0x07 0x10>; 673 reg = <0x07 0x10>;
819 }; 674 };
820 cpu_leakage: cpu-leakage@17 { 675 cpu_leakage: cpu-leakage@17 {
821 reg = <0x17 0x1>; 676 reg = <0x17 0x1>;
822 }; 677 };
823 performance: performance@1e { 678 performance: performance@1e {
824 reg = <0x1e 0x1>; 679 reg = <0x1e 0x1>;
825 bits = <4 3>; 680 bits = <4 3>;
826 }; 681 };
827 }; 682 };
828 683
829 cru: clock-controller@ff2b0000 { 684 cru: clock-controller@ff2b0000 {
830 compatible = "rockchip,px30-cr 685 compatible = "rockchip,px30-cru";
831 reg = <0x0 0xff2b0000 0x0 0x10 686 reg = <0x0 0xff2b0000 0x0 0x1000>;
832 clocks = <&xin24m>, <&pmucru P 687 clocks = <&xin24m>, <&pmucru PLL_GPLL>;
833 clock-names = "xin24m", "gpll" 688 clock-names = "xin24m", "gpll";
834 rockchip,grf = <&grf>; 689 rockchip,grf = <&grf>;
835 #clock-cells = <1>; 690 #clock-cells = <1>;
836 #reset-cells = <1>; 691 #reset-cells = <1>;
837 692
838 assigned-clocks = <&cru PLL_NP 693 assigned-clocks = <&cru PLL_NPLL>,
839 <&cru ACLK_BUS_PRE>, < 694 <&cru ACLK_BUS_PRE>, <&cru ACLK_PERI_PRE>,
840 <&cru HCLK_BUS_PRE>, < 695 <&cru HCLK_BUS_PRE>, <&cru HCLK_PERI_PRE>,
841 <&cru PCLK_BUS_PRE>, < 696 <&cru PCLK_BUS_PRE>, <&cru SCLK_GPU>;
842 697
843 assigned-clock-rates = <118800 698 assigned-clock-rates = <1188000000>,
844 <200000000>, <20000000 699 <200000000>, <200000000>,
845 <150000000>, <15000000 700 <150000000>, <150000000>,
846 <100000000>, <20000000 701 <100000000>, <200000000>;
847 }; 702 };
848 703
849 pmucru: clock-controller@ff2bc000 { 704 pmucru: clock-controller@ff2bc000 {
850 compatible = "rockchip,px30-pm 705 compatible = "rockchip,px30-pmucru";
851 reg = <0x0 0xff2bc000 0x0 0x10 706 reg = <0x0 0xff2bc000 0x0 0x1000>;
852 clocks = <&xin24m>; 707 clocks = <&xin24m>;
853 clock-names = "xin24m"; 708 clock-names = "xin24m";
854 rockchip,grf = <&grf>; 709 rockchip,grf = <&grf>;
855 #clock-cells = <1>; 710 #clock-cells = <1>;
856 #reset-cells = <1>; 711 #reset-cells = <1>;
857 712
858 assigned-clocks = 713 assigned-clocks =
859 <&pmucru PLL_GPLL>, <& 714 <&pmucru PLL_GPLL>, <&pmucru PCLK_PMU_PRE>,
860 <&pmucru SCLK_WIFI_PMU 715 <&pmucru SCLK_WIFI_PMU>;
861 assigned-clock-rates = 716 assigned-clock-rates =
862 <1200000000>, <1000000 717 <1200000000>, <100000000>,
863 <26000000>; 718 <26000000>;
864 }; 719 };
865 720
866 usb2phy_grf: syscon@ff2c0000 { 721 usb2phy_grf: syscon@ff2c0000 {
867 compatible = "rockchip,px30-us 722 compatible = "rockchip,px30-usb2phy-grf", "syscon",
868 "simple-mfd"; 723 "simple-mfd";
869 reg = <0x0 0xff2c0000 0x0 0x10 724 reg = <0x0 0xff2c0000 0x0 0x10000>;
870 #address-cells = <1>; 725 #address-cells = <1>;
871 #size-cells = <1>; 726 #size-cells = <1>;
872 727
873 u2phy: usb2phy@100 { !! 728 u2phy: usb2-phy@100 {
874 compatible = "rockchip 729 compatible = "rockchip,px30-usb2phy";
875 reg = <0x100 0x20>; 730 reg = <0x100 0x20>;
876 clocks = <&pmucru SCLK 731 clocks = <&pmucru SCLK_USBPHY_REF>;
877 clock-names = "phyclk" 732 clock-names = "phyclk";
878 #clock-cells = <0>; 733 #clock-cells = <0>;
879 assigned-clocks = <&cr 734 assigned-clocks = <&cru USB480M>;
880 assigned-clock-parents 735 assigned-clock-parents = <&u2phy>;
881 clock-output-names = " 736 clock-output-names = "usb480m_phy";
882 status = "disabled"; 737 status = "disabled";
883 738
884 u2phy_host: host-port 739 u2phy_host: host-port {
885 #phy-cells = < 740 #phy-cells = <0>;
886 interrupts = < 741 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
887 interrupt-name 742 interrupt-names = "linestate";
888 status = "disa 743 status = "disabled";
889 }; 744 };
890 745
891 u2phy_otg: otg-port { 746 u2phy_otg: otg-port {
892 #phy-cells = < 747 #phy-cells = <0>;
893 interrupts = < 748 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
894 < 749 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
895 < 750 <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
896 interrupt-name 751 interrupt-names = "otg-bvalid", "otg-id",
897 752 "linestate";
898 status = "disa 753 status = "disabled";
899 }; 754 };
900 }; 755 };
901 }; 756 };
902 757
903 dsi_dphy: phy@ff2e0000 { <<
904 compatible = "rockchip,px30-ds <<
905 reg = <0x0 0xff2e0000 0x0 0x10 <<
906 clocks = <&pmucru SCLK_MIPIDSI <<
907 clock-names = "ref", "pclk"; <<
908 resets = <&cru SRST_MIPIDSIPHY <<
909 reset-names = "apb"; <<
910 #phy-cells = <0>; <<
911 power-domains = <&power PX30_P <<
912 status = "disabled"; <<
913 }; <<
914 <<
915 csi_dphy: phy@ff2f0000 { <<
916 compatible = "rockchip,px30-cs <<
917 reg = <0x0 0xff2f0000 0x0 0x40 <<
918 clocks = <&cru PCLK_MIPICSIPHY <<
919 clock-names = "pclk"; <<
920 #phy-cells = <0>; <<
921 power-domains = <&power PX30_P <<
922 resets = <&cru SRST_MIPICSIPHY <<
923 reset-names = "apb"; <<
924 rockchip,grf = <&grf>; <<
925 status = "disabled"; <<
926 }; <<
927 <<
928 usb20_otg: usb@ff300000 { 758 usb20_otg: usb@ff300000 {
929 compatible = "rockchip,px30-us 759 compatible = "rockchip,px30-usb", "rockchip,rk3066-usb",
930 "snps,dwc2"; 760 "snps,dwc2";
931 reg = <0x0 0xff300000 0x0 0x40 761 reg = <0x0 0xff300000 0x0 0x40000>;
932 interrupts = <GIC_SPI 62 IRQ_T 762 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
933 clocks = <&cru HCLK_OTG>; 763 clocks = <&cru HCLK_OTG>;
934 clock-names = "otg"; 764 clock-names = "otg";
935 dr_mode = "otg"; 765 dr_mode = "otg";
936 g-np-tx-fifo-size = <16>; 766 g-np-tx-fifo-size = <16>;
937 g-rx-fifo-size = <280>; 767 g-rx-fifo-size = <280>;
938 g-tx-fifo-size = <256 128 128 768 g-tx-fifo-size = <256 128 128 64 32 16>;
>> 769 g-use-dma;
939 phys = <&u2phy_otg>; 770 phys = <&u2phy_otg>;
940 phy-names = "usb2-phy"; 771 phy-names = "usb2-phy";
941 power-domains = <&power PX30_P 772 power-domains = <&power PX30_PD_USB>;
942 status = "disabled"; 773 status = "disabled";
943 }; 774 };
944 775
945 usb_host0_ehci: usb@ff340000 { 776 usb_host0_ehci: usb@ff340000 {
946 compatible = "generic-ehci"; 777 compatible = "generic-ehci";
947 reg = <0x0 0xff340000 0x0 0x10 778 reg = <0x0 0xff340000 0x0 0x10000>;
948 interrupts = <GIC_SPI 60 IRQ_T 779 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
949 clocks = <&cru HCLK_HOST>; 780 clocks = <&cru HCLK_HOST>;
>> 781 clock-names = "usbhost";
950 phys = <&u2phy_host>; 782 phys = <&u2phy_host>;
951 phy-names = "usb"; 783 phy-names = "usb";
952 power-domains = <&power PX30_P 784 power-domains = <&power PX30_PD_USB>;
953 status = "disabled"; 785 status = "disabled";
954 }; 786 };
955 787
956 usb_host0_ohci: usb@ff350000 { 788 usb_host0_ohci: usb@ff350000 {
957 compatible = "generic-ohci"; 789 compatible = "generic-ohci";
958 reg = <0x0 0xff350000 0x0 0x10 790 reg = <0x0 0xff350000 0x0 0x10000>;
959 interrupts = <GIC_SPI 61 IRQ_T 791 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
960 clocks = <&cru HCLK_HOST>; 792 clocks = <&cru HCLK_HOST>;
>> 793 clock-names = "usbhost";
961 phys = <&u2phy_host>; 794 phys = <&u2phy_host>;
962 phy-names = "usb"; 795 phy-names = "usb";
963 power-domains = <&power PX30_P 796 power-domains = <&power PX30_PD_USB>;
964 status = "disabled"; 797 status = "disabled";
965 }; 798 };
966 799
967 gmac: ethernet@ff360000 { 800 gmac: ethernet@ff360000 {
968 compatible = "rockchip,px30-gm 801 compatible = "rockchip,px30-gmac";
969 reg = <0x0 0xff360000 0x0 0x10 802 reg = <0x0 0xff360000 0x0 0x10000>;
970 interrupts = <GIC_SPI 43 IRQ_T 803 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
971 interrupt-names = "macirq"; 804 interrupt-names = "macirq";
972 clocks = <&cru SCLK_GMAC>, <&c 805 clocks = <&cru SCLK_GMAC>, <&cru SCLK_GMAC_RX_TX>,
973 <&cru SCLK_GMAC_RX_TX 806 <&cru SCLK_GMAC_RX_TX>, <&cru SCLK_MAC_REF>,
974 <&cru SCLK_MAC_REFOUT 807 <&cru SCLK_MAC_REFOUT>, <&cru ACLK_GMAC>,
975 <&cru PCLK_GMAC>, <&c 808 <&cru PCLK_GMAC>, <&cru SCLK_GMAC_RMII>;
976 clock-names = "stmmaceth", "ma 809 clock-names = "stmmaceth", "mac_clk_rx",
977 "mac_clk_tx", "c 810 "mac_clk_tx", "clk_mac_ref",
978 "clk_mac_refout" 811 "clk_mac_refout", "aclk_mac",
979 "pclk_mac", "clk 812 "pclk_mac", "clk_mac_speed";
980 rockchip,grf = <&grf>; 813 rockchip,grf = <&grf>;
981 phy-mode = "rmii"; 814 phy-mode = "rmii";
982 pinctrl-names = "default"; 815 pinctrl-names = "default";
983 pinctrl-0 = <&rmii_pins &mac_r 816 pinctrl-0 = <&rmii_pins &mac_refclk_12ma>;
984 power-domains = <&power PX30_P 817 power-domains = <&power PX30_PD_GMAC>;
985 resets = <&cru SRST_GMAC_A>; 818 resets = <&cru SRST_GMAC_A>;
986 reset-names = "stmmaceth"; 819 reset-names = "stmmaceth";
987 status = "disabled"; 820 status = "disabled";
988 }; 821 };
989 822
990 sdmmc: mmc@ff370000 { !! 823 sdmmc: dwmmc@ff370000 {
991 compatible = "rockchip,px30-dw 824 compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc";
992 reg = <0x0 0xff370000 0x0 0x40 825 reg = <0x0 0xff370000 0x0 0x4000>;
993 interrupts = <GIC_SPI 54 IRQ_T 826 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
994 clocks = <&cru HCLK_SDMMC>, <& 827 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
995 <&cru SCLK_SDMMC_DRV> 828 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
996 clock-names = "biu", "ciu", "c 829 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
997 bus-width = <4>; <<
998 fifo-depth = <0x100>; 830 fifo-depth = <0x100>;
999 max-frequency = <150000000>; 831 max-frequency = <150000000>;
1000 pinctrl-names = "default"; 832 pinctrl-names = "default";
1001 pinctrl-0 = <&sdmmc_clk &sdmm 833 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_det &sdmmc_bus4>;
1002 power-domains = <&power PX30_ 834 power-domains = <&power PX30_PD_SDCARD>;
1003 status = "disabled"; 835 status = "disabled";
1004 }; 836 };
1005 837
1006 sdio: mmc@ff380000 { !! 838 sdio: dwmmc@ff380000 {
1007 compatible = "rockchip,px30-d 839 compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc";
1008 reg = <0x0 0xff380000 0x0 0x4 840 reg = <0x0 0xff380000 0x0 0x4000>;
1009 interrupts = <GIC_SPI 55 IRQ_ 841 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
1010 clocks = <&cru HCLK_SDIO>, <& 842 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
1011 <&cru SCLK_SDIO_DRV> 843 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
1012 clock-names = "biu", "ciu", " 844 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
1013 bus-width = <4>; <<
1014 fifo-depth = <0x100>; 845 fifo-depth = <0x100>;
1015 max-frequency = <150000000>; 846 max-frequency = <150000000>;
1016 pinctrl-names = "default"; 847 pinctrl-names = "default";
1017 pinctrl-0 = <&sdio_bus4 &sdio 848 pinctrl-0 = <&sdio_bus4 &sdio_cmd &sdio_clk>;
1018 power-domains = <&power PX30_ 849 power-domains = <&power PX30_PD_MMC_NAND>;
1019 status = "disabled"; 850 status = "disabled";
1020 }; 851 };
1021 852
1022 emmc: mmc@ff390000 { !! 853 emmc: dwmmc@ff390000 {
1023 compatible = "rockchip,px30-d 854 compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc";
1024 reg = <0x0 0xff390000 0x0 0x4 855 reg = <0x0 0xff390000 0x0 0x4000>;
1025 interrupts = <GIC_SPI 53 IRQ_ 856 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
1026 clocks = <&cru HCLK_EMMC>, <& 857 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
1027 <&cru SCLK_EMMC_DRV> 858 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
1028 clock-names = "biu", "ciu", " 859 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
1029 bus-width = <8>; <<
1030 fifo-depth = <0x100>; 860 fifo-depth = <0x100>;
1031 max-frequency = <150000000>; 861 max-frequency = <150000000>;
1032 pinctrl-names = "default"; 862 pinctrl-names = "default";
1033 pinctrl-0 = <&emmc_clk &emmc_ 863 pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
1034 power-domains = <&power PX30_ 864 power-domains = <&power PX30_PD_MMC_NAND>;
1035 status = "disabled"; 865 status = "disabled";
1036 }; 866 };
1037 867
1038 sfc: spi@ff3a0000 { <<
1039 compatible = "rockchip,sfc"; <<
1040 reg = <0x0 0xff3a0000 0x0 0x4 <<
1041 interrupts = <GIC_SPI 56 IRQ_ <<
1042 clocks = <&cru SCLK_SFC>, <&c <<
1043 clock-names = "clk_sfc", "hcl <<
1044 pinctrl-0 = <&sfc_clk &sfc_cs <<
1045 pinctrl-names = "default"; <<
1046 power-domains = <&power PX30_ <<
1047 status = "disabled"; <<
1048 }; <<
1049 <<
1050 nfc: nand-controller@ff3b0000 { <<
1051 compatible = "rockchip,px30-n <<
1052 reg = <0x0 0xff3b0000 0x0 0x4 <<
1053 interrupts = <GIC_SPI 57 IRQ_ <<
1054 clocks = <&cru HCLK_NANDC>, < <<
1055 clock-names = "ahb", "nfc"; <<
1056 assigned-clocks = <&cru SCLK_ <<
1057 assigned-clock-rates = <15000 <<
1058 pinctrl-names = "default"; <<
1059 pinctrl-0 = <&flash_ale &flas <<
1060 &flash_rdn &flas <<
1061 power-domains = <&power PX30_ <<
1062 status = "disabled"; <<
1063 }; <<
1064 <<
1065 gpu_opp_table: opp-table-1 { <<
1066 compatible = "operating-point <<
1067 <<
1068 opp-200000000 { <<
1069 opp-hz = /bits/ 64 <2 <<
1070 opp-microvolt = <9500 <<
1071 }; <<
1072 opp-300000000 { <<
1073 opp-hz = /bits/ 64 <3 <<
1074 opp-microvolt = <9750 <<
1075 }; <<
1076 opp-400000000 { <<
1077 opp-hz = /bits/ 64 <4 <<
1078 opp-microvolt = <1050 <<
1079 }; <<
1080 opp-480000000 { <<
1081 opp-hz = /bits/ 64 <4 <<
1082 opp-microvolt = <1125 <<
1083 }; <<
1084 }; <<
1085 <<
1086 gpu: gpu@ff400000 { <<
1087 compatible = "rockchip,px30-m <<
1088 reg = <0x0 0xff400000 0x0 0x4 <<
1089 interrupts = <GIC_SPI 47 IRQ_ <<
1090 <GIC_SPI 46 IRQ_ <<
1091 <GIC_SPI 45 IRQ_ <<
1092 interrupt-names = "job", "mmu <<
1093 clocks = <&cru SCLK_GPU>; <<
1094 #cooling-cells = <2>; <<
1095 power-domains = <&power PX30_ <<
1096 operating-points-v2 = <&gpu_o <<
1097 status = "disabled"; <<
1098 }; <<
1099 <<
1100 vpu: video-codec@ff442000 { <<
1101 compatible = "rockchip,px30-v <<
1102 reg = <0x0 0xff442000 0x0 0x8 <<
1103 interrupts = <GIC_SPI 80 IRQ_ <<
1104 <GIC_SPI 79 IRQ_ <<
1105 interrupt-names = "vepu", "vd <<
1106 clocks = <&cru ACLK_VPU>, <&c <<
1107 clock-names = "aclk", "hclk"; <<
1108 iommus = <&vpu_mmu>; <<
1109 power-domains = <&power PX30_ <<
1110 }; <<
1111 <<
1112 vpu_mmu: iommu@ff442800 { <<
1113 compatible = "rockchip,iommu" <<
1114 reg = <0x0 0xff442800 0x0 0x1 <<
1115 interrupts = <GIC_SPI 81 IRQ_ <<
1116 clocks = <&cru ACLK_VPU>, <&c <<
1117 clock-names = "aclk", "iface" <<
1118 #iommu-cells = <0>; <<
1119 power-domains = <&power PX30_ <<
1120 }; <<
1121 <<
1122 dsi: dsi@ff450000 { <<
1123 compatible = "rockchip,px30-m <<
1124 reg = <0x0 0xff450000 0x0 0x1 <<
1125 interrupts = <GIC_SPI 75 IRQ_ <<
1126 clocks = <&cru PCLK_MIPI_DSI> <<
1127 clock-names = "pclk"; <<
1128 phys = <&dsi_dphy>; <<
1129 phy-names = "dphy"; <<
1130 power-domains = <&power PX30_ <<
1131 resets = <&cru SRST_MIPIDSI_H <<
1132 reset-names = "apb"; <<
1133 rockchip,grf = <&grf>; <<
1134 #address-cells = <1>; <<
1135 #size-cells = <0>; <<
1136 status = "disabled"; <<
1137 <<
1138 ports { <<
1139 #address-cells = <1>; <<
1140 #size-cells = <0>; <<
1141 <<
1142 dsi_in: port@0 { <<
1143 reg = <0>; <<
1144 #address-cell <<
1145 #size-cells = <<
1146 <<
1147 dsi_in_vopb: <<
1148 reg = <<
1149 remot <<
1150 }; <<
1151 <<
1152 dsi_in_vopl: <<
1153 reg = <<
1154 remot <<
1155 }; <<
1156 }; <<
1157 <<
1158 dsi_out: port@1 { <<
1159 reg = <1>; <<
1160 }; <<
1161 }; <<
1162 }; <<
1163 <<
1164 vopb: vop@ff460000 { 868 vopb: vop@ff460000 {
1165 compatible = "rockchip,px30-v 869 compatible = "rockchip,px30-vop-big";
1166 reg = <0x0 0xff460000 0x0 0xe 870 reg = <0x0 0xff460000 0x0 0xefc>;
1167 interrupts = <GIC_SPI 77 IRQ_ 871 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
1168 clocks = <&cru ACLK_VOPB>, <& 872 clocks = <&cru ACLK_VOPB>, <&cru DCLK_VOPB>,
1169 <&cru HCLK_VOPB>; 873 <&cru HCLK_VOPB>;
1170 clock-names = "aclk_vop", "dc 874 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1171 resets = <&cru SRST_VOPB_A>, 875 resets = <&cru SRST_VOPB_A>, <&cru SRST_VOPB_H>, <&cru SRST_VOPB>;
1172 reset-names = "axi", "ahb", " 876 reset-names = "axi", "ahb", "dclk";
1173 iommus = <&vopb_mmu>; 877 iommus = <&vopb_mmu>;
1174 power-domains = <&power PX30_ 878 power-domains = <&power PX30_PD_VO>;
>> 879 rockchip,grf = <&grf>;
1175 status = "disabled"; 880 status = "disabled";
1176 881
1177 vopb_out: port { 882 vopb_out: port {
1178 #address-cells = <1>; 883 #address-cells = <1>;
1179 #size-cells = <0>; 884 #size-cells = <0>;
1180 <<
1181 vopb_out_dsi: endpoin <<
1182 reg = <0>; <<
1183 remote-endpoi <<
1184 }; <<
1185 <<
1186 vopb_out_lvds: endpoi <<
1187 reg = <1>; <<
1188 remote-endpoi <<
1189 }; <<
1190 }; 885 };
1191 }; 886 };
1192 887
1193 vopb_mmu: iommu@ff460f00 { 888 vopb_mmu: iommu@ff460f00 {
1194 compatible = "rockchip,iommu" 889 compatible = "rockchip,iommu";
1195 reg = <0x0 0xff460f00 0x0 0x1 890 reg = <0x0 0xff460f00 0x0 0x100>;
1196 interrupts = <GIC_SPI 77 IRQ_ 891 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
>> 892 interrupt-names = "vopb_mmu";
1197 clocks = <&cru ACLK_VOPB>, <& 893 clocks = <&cru ACLK_VOPB>, <&cru HCLK_VOPB>;
1198 clock-names = "aclk", "iface" 894 clock-names = "aclk", "iface";
1199 power-domains = <&power PX30_ 895 power-domains = <&power PX30_PD_VO>;
1200 #iommu-cells = <0>; 896 #iommu-cells = <0>;
1201 status = "disabled"; 897 status = "disabled";
1202 }; 898 };
1203 899
1204 vopl: vop@ff470000 { 900 vopl: vop@ff470000 {
1205 compatible = "rockchip,px30-v 901 compatible = "rockchip,px30-vop-lit";
1206 reg = <0x0 0xff470000 0x0 0xe 902 reg = <0x0 0xff470000 0x0 0xefc>;
1207 interrupts = <GIC_SPI 78 IRQ_ 903 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
1208 clocks = <&cru ACLK_VOPL>, <& 904 clocks = <&cru ACLK_VOPL>, <&cru DCLK_VOPL>,
1209 <&cru HCLK_VOPL>; 905 <&cru HCLK_VOPL>;
1210 clock-names = "aclk_vop", "dc 906 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1211 resets = <&cru SRST_VOPL_A>, 907 resets = <&cru SRST_VOPL_A>, <&cru SRST_VOPL_H>, <&cru SRST_VOPL>;
1212 reset-names = "axi", "ahb", " 908 reset-names = "axi", "ahb", "dclk";
1213 iommus = <&vopl_mmu>; 909 iommus = <&vopl_mmu>;
1214 power-domains = <&power PX30_ 910 power-domains = <&power PX30_PD_VO>;
>> 911 rockchip,grf = <&grf>;
1215 status = "disabled"; 912 status = "disabled";
1216 913
1217 vopl_out: port { 914 vopl_out: port {
1218 #address-cells = <1>; 915 #address-cells = <1>;
1219 #size-cells = <0>; 916 #size-cells = <0>;
1220 <<
1221 vopl_out_dsi: endpoin <<
1222 reg = <0>; <<
1223 remote-endpoi <<
1224 }; <<
1225 <<
1226 vopl_out_lvds: endpoi <<
1227 reg = <1>; <<
1228 remote-endpoi <<
1229 }; <<
1230 }; 917 };
1231 }; 918 };
1232 919
1233 vopl_mmu: iommu@ff470f00 { 920 vopl_mmu: iommu@ff470f00 {
1234 compatible = "rockchip,iommu" 921 compatible = "rockchip,iommu";
1235 reg = <0x0 0xff470f00 0x0 0x1 922 reg = <0x0 0xff470f00 0x0 0x100>;
1236 interrupts = <GIC_SPI 78 IRQ_ !! 923 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
>> 924 interrupt-names = "vopl_mmu";
1237 clocks = <&cru ACLK_VOPL>, <& 925 clocks = <&cru ACLK_VOPL>, <&cru HCLK_VOPL>;
1238 clock-names = "aclk", "iface" 926 clock-names = "aclk", "iface";
1239 power-domains = <&power PX30_ 927 power-domains = <&power PX30_PD_VO>;
1240 #iommu-cells = <0>; 928 #iommu-cells = <0>;
1241 status = "disabled"; 929 status = "disabled";
1242 }; 930 };
1243 931
1244 isp: isp@ff4a0000 { <<
1245 compatible = "rockchip,px30-c <<
1246 reg = <0x0 0xff4a0000 0x0 0x8 <<
1247 interrupts = <GIC_SPI 70 IRQ_ <<
1248 <GIC_SPI 73 IRQ_ <<
1249 <GIC_SPI 74 IRQ_ <<
1250 interrupt-names = "isp", "mi" <<
1251 clocks = <&cru SCLK_ISP>, <<
1252 <&cru ACLK_ISP>, <<
1253 <&cru HCLK_ISP>, <<
1254 <&cru PCLK_ISP>; <<
1255 clock-names = "isp", "aclk", <<
1256 iommus = <&isp_mmu>; <<
1257 phys = <&csi_dphy>; <<
1258 phy-names = "dphy"; <<
1259 power-domains = <&power PX30_ <<
1260 status = "disabled"; <<
1261 <<
1262 ports { <<
1263 #address-cells = <1>; <<
1264 #size-cells = <0>; <<
1265 <<
1266 port@0 { <<
1267 reg = <0>; <<
1268 #address-cell <<
1269 #size-cells = <<
1270 }; <<
1271 }; <<
1272 }; <<
1273 <<
1274 isp_mmu: iommu@ff4a8000 { <<
1275 compatible = "rockchip,iommu" <<
1276 reg = <0x0 0xff4a8000 0x0 0x1 <<
1277 interrupts = <GIC_SPI 70 IRQ_ <<
1278 clocks = <&cru ACLK_ISP>, <&c <<
1279 clock-names = "aclk", "iface" <<
1280 power-domains = <&power PX30_ <<
1281 rockchip,disable-mmu-reset; <<
1282 #iommu-cells = <0>; <<
1283 }; <<
1284 <<
1285 qos_gmac: qos@ff518000 { 932 qos_gmac: qos@ff518000 {
1286 compatible = "rockchip,px30-q !! 933 compatible = "syscon";
1287 reg = <0x0 0xff518000 0x0 0x2 934 reg = <0x0 0xff518000 0x0 0x20>;
1288 }; 935 };
1289 936
1290 qos_gpu: qos@ff520000 { 937 qos_gpu: qos@ff520000 {
1291 compatible = "rockchip,px30-q !! 938 compatible = "syscon";
1292 reg = <0x0 0xff520000 0x0 0x2 939 reg = <0x0 0xff520000 0x0 0x20>;
1293 }; 940 };
1294 941
1295 qos_sdmmc: qos@ff52c000 { 942 qos_sdmmc: qos@ff52c000 {
1296 compatible = "rockchip,px30-q !! 943 compatible = "syscon";
1297 reg = <0x0 0xff52c000 0x0 0x2 944 reg = <0x0 0xff52c000 0x0 0x20>;
1298 }; 945 };
1299 946
1300 qos_emmc: qos@ff538000 { 947 qos_emmc: qos@ff538000 {
1301 compatible = "rockchip,px30-q !! 948 compatible = "syscon";
1302 reg = <0x0 0xff538000 0x0 0x2 949 reg = <0x0 0xff538000 0x0 0x20>;
1303 }; 950 };
1304 951
1305 qos_nand: qos@ff538080 { 952 qos_nand: qos@ff538080 {
1306 compatible = "rockchip,px30-q !! 953 compatible = "syscon";
1307 reg = <0x0 0xff538080 0x0 0x2 954 reg = <0x0 0xff538080 0x0 0x20>;
1308 }; 955 };
1309 956
1310 qos_sdio: qos@ff538100 { 957 qos_sdio: qos@ff538100 {
1311 compatible = "rockchip,px30-q !! 958 compatible = "syscon";
1312 reg = <0x0 0xff538100 0x0 0x2 959 reg = <0x0 0xff538100 0x0 0x20>;
1313 }; 960 };
1314 961
1315 qos_sfc: qos@ff538180 { 962 qos_sfc: qos@ff538180 {
1316 compatible = "rockchip,px30-q !! 963 compatible = "syscon";
1317 reg = <0x0 0xff538180 0x0 0x2 964 reg = <0x0 0xff538180 0x0 0x20>;
1318 }; 965 };
1319 966
1320 qos_usb_host: qos@ff540000 { 967 qos_usb_host: qos@ff540000 {
1321 compatible = "rockchip,px30-q !! 968 compatible = "syscon";
1322 reg = <0x0 0xff540000 0x0 0x2 969 reg = <0x0 0xff540000 0x0 0x20>;
1323 }; 970 };
1324 971
1325 qos_usb_otg: qos@ff540080 { 972 qos_usb_otg: qos@ff540080 {
1326 compatible = "rockchip,px30-q !! 973 compatible = "syscon";
1327 reg = <0x0 0xff540080 0x0 0x2 974 reg = <0x0 0xff540080 0x0 0x20>;
1328 }; 975 };
1329 976
1330 qos_isp_128: qos@ff548000 { 977 qos_isp_128: qos@ff548000 {
1331 compatible = "rockchip,px30-q !! 978 compatible = "syscon";
1332 reg = <0x0 0xff548000 0x0 0x2 979 reg = <0x0 0xff548000 0x0 0x20>;
1333 }; 980 };
1334 981
1335 qos_isp_rd: qos@ff548080 { 982 qos_isp_rd: qos@ff548080 {
1336 compatible = "rockchip,px30-q !! 983 compatible = "syscon";
1337 reg = <0x0 0xff548080 0x0 0x2 984 reg = <0x0 0xff548080 0x0 0x20>;
1338 }; 985 };
1339 986
1340 qos_isp_wr: qos@ff548100 { 987 qos_isp_wr: qos@ff548100 {
1341 compatible = "rockchip,px30-q !! 988 compatible = "syscon";
1342 reg = <0x0 0xff548100 0x0 0x2 989 reg = <0x0 0xff548100 0x0 0x20>;
1343 }; 990 };
1344 991
1345 qos_isp_m1: qos@ff548180 { 992 qos_isp_m1: qos@ff548180 {
1346 compatible = "rockchip,px30-q !! 993 compatible = "syscon";
1347 reg = <0x0 0xff548180 0x0 0x2 994 reg = <0x0 0xff548180 0x0 0x20>;
1348 }; 995 };
1349 996
1350 qos_vip: qos@ff548200 { 997 qos_vip: qos@ff548200 {
1351 compatible = "rockchip,px30-q !! 998 compatible = "syscon";
1352 reg = <0x0 0xff548200 0x0 0x2 999 reg = <0x0 0xff548200 0x0 0x20>;
1353 }; 1000 };
1354 1001
1355 qos_rga_rd: qos@ff550000 { 1002 qos_rga_rd: qos@ff550000 {
1356 compatible = "rockchip,px30-q !! 1003 compatible = "syscon";
1357 reg = <0x0 0xff550000 0x0 0x2 1004 reg = <0x0 0xff550000 0x0 0x20>;
1358 }; 1005 };
1359 1006
1360 qos_rga_wr: qos@ff550080 { 1007 qos_rga_wr: qos@ff550080 {
1361 compatible = "rockchip,px30-q !! 1008 compatible = "syscon";
1362 reg = <0x0 0xff550080 0x0 0x2 1009 reg = <0x0 0xff550080 0x0 0x20>;
1363 }; 1010 };
1364 1011
1365 qos_vop_m0: qos@ff550100 { 1012 qos_vop_m0: qos@ff550100 {
1366 compatible = "rockchip,px30-q !! 1013 compatible = "syscon";
1367 reg = <0x0 0xff550100 0x0 0x2 1014 reg = <0x0 0xff550100 0x0 0x20>;
1368 }; 1015 };
1369 1016
1370 qos_vop_m1: qos@ff550180 { 1017 qos_vop_m1: qos@ff550180 {
1371 compatible = "rockchip,px30-q !! 1018 compatible = "syscon";
1372 reg = <0x0 0xff550180 0x0 0x2 1019 reg = <0x0 0xff550180 0x0 0x20>;
1373 }; 1020 };
1374 1021
1375 qos_vpu: qos@ff558000 { 1022 qos_vpu: qos@ff558000 {
1376 compatible = "rockchip,px30-q !! 1023 compatible = "syscon";
1377 reg = <0x0 0xff558000 0x0 0x2 1024 reg = <0x0 0xff558000 0x0 0x20>;
1378 }; 1025 };
1379 1026
1380 qos_vpu_r128: qos@ff558080 { 1027 qos_vpu_r128: qos@ff558080 {
1381 compatible = "rockchip,px30-q !! 1028 compatible = "syscon";
1382 reg = <0x0 0xff558080 0x0 0x2 1029 reg = <0x0 0xff558080 0x0 0x20>;
1383 }; 1030 };
1384 1031
1385 pinctrl: pinctrl { 1032 pinctrl: pinctrl {
1386 compatible = "rockchip,px30-p 1033 compatible = "rockchip,px30-pinctrl";
1387 rockchip,grf = <&grf>; 1034 rockchip,grf = <&grf>;
1388 rockchip,pmu = <&pmugrf>; 1035 rockchip,pmu = <&pmugrf>;
1389 #address-cells = <2>; 1036 #address-cells = <2>;
1390 #size-cells = <2>; 1037 #size-cells = <2>;
1391 ranges; 1038 ranges;
1392 1039
1393 gpio0: gpio@ff040000 { !! 1040 gpio0: gpio0@ff040000 {
1394 compatible = "rockchi 1041 compatible = "rockchip,gpio-bank";
1395 reg = <0x0 0xff040000 1042 reg = <0x0 0xff040000 0x0 0x100>;
1396 interrupts = <GIC_SPI 1043 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
1397 clocks = <&pmucru PCL 1044 clocks = <&pmucru PCLK_GPIO0_PMU>;
1398 gpio-controller; 1045 gpio-controller;
1399 #gpio-cells = <2>; 1046 #gpio-cells = <2>;
1400 1047
1401 interrupt-controller; 1048 interrupt-controller;
1402 #interrupt-cells = <2 1049 #interrupt-cells = <2>;
1403 }; 1050 };
1404 1051
1405 gpio1: gpio@ff250000 { !! 1052 gpio1: gpio1@ff250000 {
1406 compatible = "rockchi 1053 compatible = "rockchip,gpio-bank";
1407 reg = <0x0 0xff250000 1054 reg = <0x0 0xff250000 0x0 0x100>;
1408 interrupts = <GIC_SPI 1055 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
1409 clocks = <&cru PCLK_G 1056 clocks = <&cru PCLK_GPIO1>;
1410 gpio-controller; 1057 gpio-controller;
1411 #gpio-cells = <2>; 1058 #gpio-cells = <2>;
1412 1059
1413 interrupt-controller; 1060 interrupt-controller;
1414 #interrupt-cells = <2 1061 #interrupt-cells = <2>;
1415 }; 1062 };
1416 1063
1417 gpio2: gpio@ff260000 { !! 1064 gpio2: gpio2@ff260000 {
1418 compatible = "rockchi 1065 compatible = "rockchip,gpio-bank";
1419 reg = <0x0 0xff260000 1066 reg = <0x0 0xff260000 0x0 0x100>;
1420 interrupts = <GIC_SPI 1067 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
1421 clocks = <&cru PCLK_G 1068 clocks = <&cru PCLK_GPIO2>;
1422 gpio-controller; 1069 gpio-controller;
1423 #gpio-cells = <2>; 1070 #gpio-cells = <2>;
1424 1071
1425 interrupt-controller; 1072 interrupt-controller;
1426 #interrupt-cells = <2 1073 #interrupt-cells = <2>;
1427 }; 1074 };
1428 1075
1429 gpio3: gpio@ff270000 { !! 1076 gpio3: gpio3@ff270000 {
1430 compatible = "rockchi 1077 compatible = "rockchip,gpio-bank";
1431 reg = <0x0 0xff270000 1078 reg = <0x0 0xff270000 0x0 0x100>;
1432 interrupts = <GIC_SPI 1079 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
1433 clocks = <&cru PCLK_G 1080 clocks = <&cru PCLK_GPIO3>;
1434 gpio-controller; 1081 gpio-controller;
1435 #gpio-cells = <2>; 1082 #gpio-cells = <2>;
1436 1083
1437 interrupt-controller; 1084 interrupt-controller;
1438 #interrupt-cells = <2 1085 #interrupt-cells = <2>;
1439 }; 1086 };
1440 1087
1441 pcfg_pull_up: pcfg-pull-up { 1088 pcfg_pull_up: pcfg-pull-up {
1442 bias-pull-up; 1089 bias-pull-up;
1443 }; 1090 };
1444 1091
1445 pcfg_pull_down: pcfg-pull-dow 1092 pcfg_pull_down: pcfg-pull-down {
1446 bias-pull-down; 1093 bias-pull-down;
1447 }; 1094 };
1448 1095
1449 pcfg_pull_none: pcfg-pull-non 1096 pcfg_pull_none: pcfg-pull-none {
1450 bias-disable; 1097 bias-disable;
1451 }; 1098 };
1452 1099
1453 pcfg_pull_none_2ma: pcfg-pull 1100 pcfg_pull_none_2ma: pcfg-pull-none-2ma {
1454 bias-disable; 1101 bias-disable;
1455 drive-strength = <2>; 1102 drive-strength = <2>;
1456 }; 1103 };
1457 1104
1458 pcfg_pull_up_2ma: pcfg-pull-u 1105 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
1459 bias-pull-up; 1106 bias-pull-up;
1460 drive-strength = <2>; 1107 drive-strength = <2>;
1461 }; 1108 };
1462 1109
1463 pcfg_pull_up_4ma: pcfg-pull-u 1110 pcfg_pull_up_4ma: pcfg-pull-up-4ma {
1464 bias-pull-up; 1111 bias-pull-up;
1465 drive-strength = <4>; 1112 drive-strength = <4>;
1466 }; 1113 };
1467 1114
1468 pcfg_pull_none_4ma: pcfg-pull 1115 pcfg_pull_none_4ma: pcfg-pull-none-4ma {
1469 bias-disable; 1116 bias-disable;
1470 drive-strength = <4>; 1117 drive-strength = <4>;
1471 }; 1118 };
1472 1119
1473 pcfg_pull_down_4ma: pcfg-pull 1120 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
1474 bias-pull-down; 1121 bias-pull-down;
1475 drive-strength = <4>; 1122 drive-strength = <4>;
1476 }; 1123 };
1477 1124
1478 pcfg_pull_none_8ma: pcfg-pull 1125 pcfg_pull_none_8ma: pcfg-pull-none-8ma {
1479 bias-disable; 1126 bias-disable;
1480 drive-strength = <8>; 1127 drive-strength = <8>;
1481 }; 1128 };
1482 1129
1483 pcfg_pull_up_8ma: pcfg-pull-u 1130 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
1484 bias-pull-up; 1131 bias-pull-up;
1485 drive-strength = <8>; 1132 drive-strength = <8>;
1486 }; 1133 };
1487 1134
1488 pcfg_pull_none_12ma: pcfg-pul 1135 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1489 bias-disable; 1136 bias-disable;
1490 drive-strength = <12> 1137 drive-strength = <12>;
1491 }; 1138 };
1492 1139
1493 pcfg_pull_up_12ma: pcfg-pull- 1140 pcfg_pull_up_12ma: pcfg-pull-up-12ma {
1494 bias-pull-up; 1141 bias-pull-up;
1495 drive-strength = <12> 1142 drive-strength = <12>;
1496 }; 1143 };
1497 1144
1498 pcfg_pull_none_smt: pcfg-pull 1145 pcfg_pull_none_smt: pcfg-pull-none-smt {
1499 bias-disable; 1146 bias-disable;
1500 input-schmitt-enable; 1147 input-schmitt-enable;
1501 }; 1148 };
1502 1149
1503 pcfg_output_high: pcfg-output 1150 pcfg_output_high: pcfg-output-high {
1504 output-high; 1151 output-high;
1505 }; 1152 };
1506 1153
1507 pcfg_output_low: pcfg-output- 1154 pcfg_output_low: pcfg-output-low {
1508 output-low; 1155 output-low;
1509 }; 1156 };
1510 1157
1511 pcfg_input_high: pcfg-input-h 1158 pcfg_input_high: pcfg-input-high {
1512 bias-pull-up; 1159 bias-pull-up;
1513 input-enable; 1160 input-enable;
1514 }; 1161 };
1515 1162
1516 pcfg_input: pcfg-input { 1163 pcfg_input: pcfg-input {
1517 input-enable; 1164 input-enable;
1518 }; 1165 };
1519 1166
1520 i2c0 { 1167 i2c0 {
1521 i2c0_xfer: i2c0-xfer 1168 i2c0_xfer: i2c0-xfer {
1522 rockchip,pins 1169 rockchip,pins =
1523 <0 RK 1170 <0 RK_PB0 1 &pcfg_pull_none_smt>,
1524 <0 RK 1171 <0 RK_PB1 1 &pcfg_pull_none_smt>;
1525 }; 1172 };
1526 }; 1173 };
1527 1174
1528 i2c1 { 1175 i2c1 {
1529 i2c1_xfer: i2c1-xfer 1176 i2c1_xfer: i2c1-xfer {
1530 rockchip,pins 1177 rockchip,pins =
1531 <0 RK 1178 <0 RK_PC2 1 &pcfg_pull_none_smt>,
1532 <0 RK 1179 <0 RK_PC3 1 &pcfg_pull_none_smt>;
1533 }; 1180 };
1534 }; 1181 };
1535 1182
1536 i2c2 { 1183 i2c2 {
1537 i2c2_xfer: i2c2-xfer 1184 i2c2_xfer: i2c2-xfer {
1538 rockchip,pins 1185 rockchip,pins =
1539 <2 RK 1186 <2 RK_PB7 2 &pcfg_pull_none_smt>,
1540 <2 RK 1187 <2 RK_PC0 2 &pcfg_pull_none_smt>;
1541 }; 1188 };
1542 }; 1189 };
1543 1190
1544 i2c3 { 1191 i2c3 {
1545 i2c3_xfer: i2c3-xfer 1192 i2c3_xfer: i2c3-xfer {
1546 rockchip,pins 1193 rockchip,pins =
1547 <1 RK 1194 <1 RK_PB4 4 &pcfg_pull_none_smt>,
1548 <1 RK 1195 <1 RK_PB5 4 &pcfg_pull_none_smt>;
1549 }; 1196 };
1550 }; 1197 };
1551 1198
1552 tsadc { 1199 tsadc {
1553 tsadc_otp_pin: tsadc- !! 1200 tsadc_otp_gpio: tsadc-otp-gpio {
1554 rockchip,pins 1201 rockchip,pins =
1555 <0 RK 1202 <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
1556 }; 1203 };
1557 1204
1558 tsadc_otp_out: tsadc- 1205 tsadc_otp_out: tsadc-otp-out {
1559 rockchip,pins 1206 rockchip,pins =
1560 <0 RK 1207 <0 RK_PA6 1 &pcfg_pull_none>;
1561 }; 1208 };
1562 }; 1209 };
1563 1210
1564 uart0 { 1211 uart0 {
1565 uart0_xfer: uart0-xfe 1212 uart0_xfer: uart0-xfer {
1566 rockchip,pins 1213 rockchip,pins =
1567 <0 RK 1214 <0 RK_PB2 1 &pcfg_pull_up>,
1568 <0 RK 1215 <0 RK_PB3 1 &pcfg_pull_up>;
1569 }; 1216 };
1570 1217
1571 uart0_cts: uart0-cts 1218 uart0_cts: uart0-cts {
1572 rockchip,pins 1219 rockchip,pins =
1573 <0 RK 1220 <0 RK_PB4 1 &pcfg_pull_none>;
1574 }; 1221 };
1575 1222
1576 uart0_rts: uart0-rts 1223 uart0_rts: uart0-rts {
1577 rockchip,pins 1224 rockchip,pins =
1578 <0 RK 1225 <0 RK_PB5 1 &pcfg_pull_none>;
1579 }; 1226 };
1580 }; 1227 };
1581 1228
1582 uart1 { 1229 uart1 {
1583 uart1_xfer: uart1-xfe 1230 uart1_xfer: uart1-xfer {
1584 rockchip,pins 1231 rockchip,pins =
1585 <1 RK 1232 <1 RK_PC1 1 &pcfg_pull_up>,
1586 <1 RK 1233 <1 RK_PC0 1 &pcfg_pull_up>;
1587 }; 1234 };
1588 1235
1589 uart1_cts: uart1-cts 1236 uart1_cts: uart1-cts {
1590 rockchip,pins 1237 rockchip,pins =
1591 <1 RK 1238 <1 RK_PC2 1 &pcfg_pull_none>;
1592 }; 1239 };
1593 1240
1594 uart1_rts: uart1-rts 1241 uart1_rts: uart1-rts {
1595 rockchip,pins 1242 rockchip,pins =
1596 <1 RK 1243 <1 RK_PC3 1 &pcfg_pull_none>;
1597 }; 1244 };
1598 }; 1245 };
1599 1246
1600 uart2-m0 { 1247 uart2-m0 {
1601 uart2m0_xfer: uart2m0 1248 uart2m0_xfer: uart2m0-xfer {
1602 rockchip,pins 1249 rockchip,pins =
1603 <1 RK 1250 <1 RK_PD2 2 &pcfg_pull_up>,
1604 <1 RK 1251 <1 RK_PD3 2 &pcfg_pull_up>;
1605 }; 1252 };
1606 }; 1253 };
1607 1254
1608 uart2-m1 { 1255 uart2-m1 {
1609 uart2m1_xfer: uart2m1 1256 uart2m1_xfer: uart2m1-xfer {
1610 rockchip,pins 1257 rockchip,pins =
1611 <2 RK 1258 <2 RK_PB4 2 &pcfg_pull_up>,
1612 <2 RK 1259 <2 RK_PB6 2 &pcfg_pull_up>;
1613 }; 1260 };
1614 }; 1261 };
1615 1262
1616 uart3-m0 { 1263 uart3-m0 {
1617 uart3m0_xfer: uart3m0 1264 uart3m0_xfer: uart3m0-xfer {
1618 rockchip,pins 1265 rockchip,pins =
1619 <0 RK 1266 <0 RK_PC0 2 &pcfg_pull_up>,
1620 <0 RK 1267 <0 RK_PC1 2 &pcfg_pull_up>;
1621 }; 1268 };
1622 1269
1623 uart3m0_cts: uart3m0- 1270 uart3m0_cts: uart3m0-cts {
1624 rockchip,pins 1271 rockchip,pins =
1625 <0 RK 1272 <0 RK_PC2 2 &pcfg_pull_none>;
1626 }; 1273 };
1627 1274
1628 uart3m0_rts: uart3m0- 1275 uart3m0_rts: uart3m0-rts {
1629 rockchip,pins 1276 rockchip,pins =
1630 <0 RK 1277 <0 RK_PC3 2 &pcfg_pull_none>;
1631 }; 1278 };
1632 }; 1279 };
1633 1280
1634 uart3-m1 { 1281 uart3-m1 {
1635 uart3m1_xfer: uart3m1 1282 uart3m1_xfer: uart3m1-xfer {
1636 rockchip,pins 1283 rockchip,pins =
1637 <1 RK 1284 <1 RK_PB6 2 &pcfg_pull_up>,
1638 <1 RK 1285 <1 RK_PB7 2 &pcfg_pull_up>;
1639 }; 1286 };
1640 1287
1641 uart3m1_cts: uart3m1- 1288 uart3m1_cts: uart3m1-cts {
1642 rockchip,pins 1289 rockchip,pins =
1643 <1 RK 1290 <1 RK_PB4 2 &pcfg_pull_none>;
1644 }; 1291 };
1645 1292
1646 uart3m1_rts: uart3m1- 1293 uart3m1_rts: uart3m1-rts {
1647 rockchip,pins 1294 rockchip,pins =
1648 <1 RK 1295 <1 RK_PB5 2 &pcfg_pull_none>;
1649 }; 1296 };
1650 }; 1297 };
1651 1298
1652 uart4 { 1299 uart4 {
1653 uart4_xfer: uart4-xfe 1300 uart4_xfer: uart4-xfer {
1654 rockchip,pins 1301 rockchip,pins =
1655 <1 RK 1302 <1 RK_PD4 2 &pcfg_pull_up>,
1656 <1 RK 1303 <1 RK_PD5 2 &pcfg_pull_up>;
1657 }; 1304 };
1658 1305
1659 uart4_cts: uart4-cts 1306 uart4_cts: uart4-cts {
1660 rockchip,pins 1307 rockchip,pins =
1661 <1 RK 1308 <1 RK_PD6 2 &pcfg_pull_none>;
1662 }; 1309 };
1663 1310
1664 uart4_rts: uart4-rts 1311 uart4_rts: uart4-rts {
1665 rockchip,pins 1312 rockchip,pins =
1666 <1 RK 1313 <1 RK_PD7 2 &pcfg_pull_none>;
1667 }; 1314 };
1668 }; 1315 };
1669 1316
1670 uart5 { 1317 uart5 {
1671 uart5_xfer: uart5-xfe 1318 uart5_xfer: uart5-xfer {
1672 rockchip,pins 1319 rockchip,pins =
1673 <3 RK 1320 <3 RK_PA2 4 &pcfg_pull_up>,
1674 <3 RK 1321 <3 RK_PA1 4 &pcfg_pull_up>;
1675 }; 1322 };
1676 1323
1677 uart5_cts: uart5-cts 1324 uart5_cts: uart5-cts {
1678 rockchip,pins 1325 rockchip,pins =
1679 <3 RK 1326 <3 RK_PA3 4 &pcfg_pull_none>;
1680 }; 1327 };
1681 1328
1682 uart5_rts: uart5-rts 1329 uart5_rts: uart5-rts {
1683 rockchip,pins 1330 rockchip,pins =
1684 <3 RK 1331 <3 RK_PA5 4 &pcfg_pull_none>;
1685 }; 1332 };
1686 }; 1333 };
1687 1334
1688 spi0 { 1335 spi0 {
1689 spi0_clk: spi0-clk { 1336 spi0_clk: spi0-clk {
1690 rockchip,pins 1337 rockchip,pins =
1691 <1 RK 1338 <1 RK_PB7 3 &pcfg_pull_up_4ma>;
1692 }; 1339 };
1693 1340
1694 spi0_csn: spi0-csn { 1341 spi0_csn: spi0-csn {
1695 rockchip,pins 1342 rockchip,pins =
1696 <1 RK 1343 <1 RK_PB6 3 &pcfg_pull_up_4ma>;
1697 }; 1344 };
1698 1345
1699 spi0_miso: spi0-miso 1346 spi0_miso: spi0-miso {
1700 rockchip,pins 1347 rockchip,pins =
1701 <1 RK 1348 <1 RK_PB5 3 &pcfg_pull_up_4ma>;
1702 }; 1349 };
1703 1350
1704 spi0_mosi: spi0-mosi 1351 spi0_mosi: spi0-mosi {
1705 rockchip,pins 1352 rockchip,pins =
1706 <1 RK 1353 <1 RK_PB4 3 &pcfg_pull_up_4ma>;
1707 }; 1354 };
1708 1355
1709 spi0_clk_hs: spi0-clk 1356 spi0_clk_hs: spi0-clk-hs {
1710 rockchip,pins 1357 rockchip,pins =
1711 <1 RK 1358 <1 RK_PB7 3 &pcfg_pull_up_8ma>;
1712 }; 1359 };
1713 1360
1714 spi0_miso_hs: spi0-mi 1361 spi0_miso_hs: spi0-miso-hs {
1715 rockchip,pins 1362 rockchip,pins =
1716 <1 RK 1363 <1 RK_PB5 3 &pcfg_pull_up_8ma>;
1717 }; 1364 };
1718 1365
1719 spi0_mosi_hs: spi0-mo 1366 spi0_mosi_hs: spi0-mosi-hs {
1720 rockchip,pins 1367 rockchip,pins =
1721 <1 RK 1368 <1 RK_PB4 3 &pcfg_pull_up_8ma>;
1722 }; 1369 };
1723 }; 1370 };
1724 1371
1725 spi1 { 1372 spi1 {
1726 spi1_clk: spi1-clk { 1373 spi1_clk: spi1-clk {
1727 rockchip,pins 1374 rockchip,pins =
1728 <3 RK 1375 <3 RK_PB7 4 &pcfg_pull_up_4ma>;
1729 }; 1376 };
1730 1377
1731 spi1_csn0: spi1-csn0 1378 spi1_csn0: spi1-csn0 {
1732 rockchip,pins 1379 rockchip,pins =
1733 <3 RK 1380 <3 RK_PB1 4 &pcfg_pull_up_4ma>;
1734 }; 1381 };
1735 1382
1736 spi1_csn1: spi1-csn1 1383 spi1_csn1: spi1-csn1 {
1737 rockchip,pins 1384 rockchip,pins =
1738 <3 RK 1385 <3 RK_PB2 2 &pcfg_pull_up_4ma>;
1739 }; 1386 };
1740 1387
1741 spi1_miso: spi1-miso 1388 spi1_miso: spi1-miso {
1742 rockchip,pins 1389 rockchip,pins =
1743 <3 RK 1390 <3 RK_PB6 4 &pcfg_pull_up_4ma>;
1744 }; 1391 };
1745 1392
1746 spi1_mosi: spi1-mosi 1393 spi1_mosi: spi1-mosi {
1747 rockchip,pins 1394 rockchip,pins =
1748 <3 RK 1395 <3 RK_PB4 4 &pcfg_pull_up_4ma>;
1749 }; 1396 };
1750 1397
1751 spi1_clk_hs: spi1-clk 1398 spi1_clk_hs: spi1-clk-hs {
1752 rockchip,pins 1399 rockchip,pins =
1753 <3 RK 1400 <3 RK_PB7 4 &pcfg_pull_up_8ma>;
1754 }; 1401 };
1755 1402
1756 spi1_miso_hs: spi1-mi 1403 spi1_miso_hs: spi1-miso-hs {
1757 rockchip,pins 1404 rockchip,pins =
1758 <3 RK 1405 <3 RK_PB6 4 &pcfg_pull_up_8ma>;
1759 }; 1406 };
1760 1407
1761 spi1_mosi_hs: spi1-mo 1408 spi1_mosi_hs: spi1-mosi-hs {
1762 rockchip,pins 1409 rockchip,pins =
1763 <3 RK 1410 <3 RK_PB4 4 &pcfg_pull_up_8ma>;
1764 }; 1411 };
1765 }; 1412 };
1766 1413
1767 pdm { 1414 pdm {
1768 pdm_clk0m0: pdm-clk0m 1415 pdm_clk0m0: pdm-clk0m0 {
1769 rockchip,pins 1416 rockchip,pins =
1770 <3 RK 1417 <3 RK_PC6 2 &pcfg_pull_none>;
1771 }; 1418 };
1772 1419
1773 pdm_clk0m1: pdm-clk0m 1420 pdm_clk0m1: pdm-clk0m1 {
1774 rockchip,pins 1421 rockchip,pins =
1775 <2 RK 1422 <2 RK_PC6 1 &pcfg_pull_none>;
1776 }; 1423 };
1777 1424
1778 pdm_clk1: pdm-clk1 { 1425 pdm_clk1: pdm-clk1 {
1779 rockchip,pins 1426 rockchip,pins =
1780 <3 RK 1427 <3 RK_PC7 2 &pcfg_pull_none>;
1781 }; 1428 };
1782 1429
1783 pdm_sdi0m0: pdm-sdi0m 1430 pdm_sdi0m0: pdm-sdi0m0 {
1784 rockchip,pins 1431 rockchip,pins =
1785 <3 RK 1432 <3 RK_PD3 2 &pcfg_pull_none>;
1786 }; 1433 };
1787 1434
1788 pdm_sdi0m1: pdm-sdi0m 1435 pdm_sdi0m1: pdm-sdi0m1 {
1789 rockchip,pins 1436 rockchip,pins =
1790 <2 RK 1437 <2 RK_PC5 2 &pcfg_pull_none>;
1791 }; 1438 };
1792 1439
1793 pdm_sdi1: pdm-sdi1 { 1440 pdm_sdi1: pdm-sdi1 {
1794 rockchip,pins 1441 rockchip,pins =
1795 <3 RK 1442 <3 RK_PD0 2 &pcfg_pull_none>;
1796 }; 1443 };
1797 1444
1798 pdm_sdi2: pdm-sdi2 { 1445 pdm_sdi2: pdm-sdi2 {
1799 rockchip,pins 1446 rockchip,pins =
1800 <3 RK 1447 <3 RK_PD1 2 &pcfg_pull_none>;
1801 }; 1448 };
1802 1449
1803 pdm_sdi3: pdm-sdi3 { 1450 pdm_sdi3: pdm-sdi3 {
1804 rockchip,pins 1451 rockchip,pins =
1805 <3 RK 1452 <3 RK_PD2 2 &pcfg_pull_none>;
1806 }; 1453 };
1807 1454
1808 pdm_clk0m0_sleep: pdm 1455 pdm_clk0m0_sleep: pdm-clk0m0-sleep {
1809 rockchip,pins 1456 rockchip,pins =
1810 <3 RK 1457 <3 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>;
1811 }; 1458 };
1812 1459
1813 pdm_clk0m_sleep1: pdm 1460 pdm_clk0m_sleep1: pdm-clk0m1-sleep {
1814 rockchip,pins 1461 rockchip,pins =
1815 <2 RK 1462 <2 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>;
1816 }; 1463 };
1817 1464
1818 pdm_clk1_sleep: pdm-c 1465 pdm_clk1_sleep: pdm-clk1-sleep {
1819 rockchip,pins 1466 rockchip,pins =
1820 <3 RK 1467 <3 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>;
1821 }; 1468 };
1822 1469
1823 pdm_sdi0m0_sleep: pdm 1470 pdm_sdi0m0_sleep: pdm-sdi0m0-sleep {
1824 rockchip,pins 1471 rockchip,pins =
1825 <3 RK 1472 <3 RK_PD3 RK_FUNC_GPIO &pcfg_input_high>;
1826 }; 1473 };
1827 1474
1828 pdm_sdi0m1_sleep: pdm 1475 pdm_sdi0m1_sleep: pdm-sdi0m1-sleep {
1829 rockchip,pins 1476 rockchip,pins =
1830 <2 RK 1477 <2 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>;
1831 }; 1478 };
1832 1479
1833 pdm_sdi1_sleep: pdm-s 1480 pdm_sdi1_sleep: pdm-sdi1-sleep {
1834 rockchip,pins 1481 rockchip,pins =
1835 <3 RK 1482 <3 RK_PD0 RK_FUNC_GPIO &pcfg_input_high>;
1836 }; 1483 };
1837 1484
1838 pdm_sdi2_sleep: pdm-s 1485 pdm_sdi2_sleep: pdm-sdi2-sleep {
1839 rockchip,pins 1486 rockchip,pins =
1840 <3 RK 1487 <3 RK_PD1 RK_FUNC_GPIO &pcfg_input_high>;
1841 }; 1488 };
1842 1489
1843 pdm_sdi3_sleep: pdm-s 1490 pdm_sdi3_sleep: pdm-sdi3-sleep {
1844 rockchip,pins 1491 rockchip,pins =
1845 <3 RK 1492 <3 RK_PD2 RK_FUNC_GPIO &pcfg_input_high>;
1846 }; 1493 };
1847 }; 1494 };
1848 1495
1849 i2s0 { 1496 i2s0 {
1850 i2s0_8ch_mclk: i2s0-8 1497 i2s0_8ch_mclk: i2s0-8ch-mclk {
1851 rockchip,pins 1498 rockchip,pins =
1852 <3 RK 1499 <3 RK_PC1 2 &pcfg_pull_none>;
1853 }; 1500 };
1854 1501
1855 i2s0_8ch_sclktx: i2s0 1502 i2s0_8ch_sclktx: i2s0-8ch-sclktx {
1856 rockchip,pins 1503 rockchip,pins =
1857 <3 RK 1504 <3 RK_PC3 2 &pcfg_pull_none>;
1858 }; 1505 };
1859 1506
1860 i2s0_8ch_sclkrx: i2s0 1507 i2s0_8ch_sclkrx: i2s0-8ch-sclkrx {
1861 rockchip,pins 1508 rockchip,pins =
1862 <3 RK 1509 <3 RK_PB4 2 &pcfg_pull_none>;
1863 }; 1510 };
1864 1511
1865 i2s0_8ch_lrcktx: i2s0 1512 i2s0_8ch_lrcktx: i2s0-8ch-lrcktx {
1866 rockchip,pins 1513 rockchip,pins =
1867 <3 RK 1514 <3 RK_PC2 2 &pcfg_pull_none>;
1868 }; 1515 };
1869 1516
1870 i2s0_8ch_lrckrx: i2s0 1517 i2s0_8ch_lrckrx: i2s0-8ch-lrckrx {
1871 rockchip,pins 1518 rockchip,pins =
1872 <3 RK 1519 <3 RK_PB5 2 &pcfg_pull_none>;
1873 }; 1520 };
1874 1521
1875 i2s0_8ch_sdo0: i2s0-8 1522 i2s0_8ch_sdo0: i2s0-8ch-sdo0 {
1876 rockchip,pins 1523 rockchip,pins =
1877 <3 RK 1524 <3 RK_PC4 2 &pcfg_pull_none>;
1878 }; 1525 };
1879 1526
1880 i2s0_8ch_sdo1: i2s0-8 1527 i2s0_8ch_sdo1: i2s0-8ch-sdo1 {
1881 rockchip,pins 1528 rockchip,pins =
1882 <3 RK 1529 <3 RK_PC0 2 &pcfg_pull_none>;
1883 }; 1530 };
1884 1531
1885 i2s0_8ch_sdo2: i2s0-8 1532 i2s0_8ch_sdo2: i2s0-8ch-sdo2 {
1886 rockchip,pins 1533 rockchip,pins =
1887 <3 RK 1534 <3 RK_PB7 2 &pcfg_pull_none>;
1888 }; 1535 };
1889 1536
1890 i2s0_8ch_sdo3: i2s0-8 1537 i2s0_8ch_sdo3: i2s0-8ch-sdo3 {
1891 rockchip,pins 1538 rockchip,pins =
1892 <3 RK 1539 <3 RK_PB6 2 &pcfg_pull_none>;
1893 }; 1540 };
1894 1541
1895 i2s0_8ch_sdi0: i2s0-8 1542 i2s0_8ch_sdi0: i2s0-8ch-sdi0 {
1896 rockchip,pins 1543 rockchip,pins =
1897 <3 RK 1544 <3 RK_PC5 2 &pcfg_pull_none>;
1898 }; 1545 };
1899 1546
1900 i2s0_8ch_sdi1: i2s0-8 1547 i2s0_8ch_sdi1: i2s0-8ch-sdi1 {
1901 rockchip,pins 1548 rockchip,pins =
1902 <3 RK 1549 <3 RK_PB3 2 &pcfg_pull_none>;
1903 }; 1550 };
1904 1551
1905 i2s0_8ch_sdi2: i2s0-8 1552 i2s0_8ch_sdi2: i2s0-8ch-sdi2 {
1906 rockchip,pins 1553 rockchip,pins =
1907 <3 RK 1554 <3 RK_PB1 2 &pcfg_pull_none>;
1908 }; 1555 };
1909 1556
1910 i2s0_8ch_sdi3: i2s0-8 1557 i2s0_8ch_sdi3: i2s0-8ch-sdi3 {
1911 rockchip,pins 1558 rockchip,pins =
1912 <3 RK 1559 <3 RK_PB0 2 &pcfg_pull_none>;
1913 }; 1560 };
1914 }; 1561 };
1915 1562
1916 i2s1 { 1563 i2s1 {
1917 i2s1_2ch_mclk: i2s1-2 1564 i2s1_2ch_mclk: i2s1-2ch-mclk {
1918 rockchip,pins 1565 rockchip,pins =
1919 <2 RK 1566 <2 RK_PC3 1 &pcfg_pull_none>;
1920 }; 1567 };
1921 1568
1922 i2s1_2ch_sclk: i2s1-2 1569 i2s1_2ch_sclk: i2s1-2ch-sclk {
1923 rockchip,pins 1570 rockchip,pins =
1924 <2 RK 1571 <2 RK_PC2 1 &pcfg_pull_none>;
1925 }; 1572 };
1926 1573
1927 i2s1_2ch_lrck: i2s1-2 1574 i2s1_2ch_lrck: i2s1-2ch-lrck {
1928 rockchip,pins 1575 rockchip,pins =
1929 <2 RK 1576 <2 RK_PC1 1 &pcfg_pull_none>;
1930 }; 1577 };
1931 1578
1932 i2s1_2ch_sdi: i2s1-2c 1579 i2s1_2ch_sdi: i2s1-2ch-sdi {
1933 rockchip,pins 1580 rockchip,pins =
1934 <2 RK 1581 <2 RK_PC5 1 &pcfg_pull_none>;
1935 }; 1582 };
1936 1583
1937 i2s1_2ch_sdo: i2s1-2c 1584 i2s1_2ch_sdo: i2s1-2ch-sdo {
1938 rockchip,pins 1585 rockchip,pins =
1939 <2 RK 1586 <2 RK_PC4 1 &pcfg_pull_none>;
1940 }; 1587 };
1941 }; 1588 };
1942 1589
1943 i2s2 { 1590 i2s2 {
1944 i2s2_2ch_mclk: i2s2-2 1591 i2s2_2ch_mclk: i2s2-2ch-mclk {
1945 rockchip,pins 1592 rockchip,pins =
1946 <3 RK 1593 <3 RK_PA1 2 &pcfg_pull_none>;
1947 }; 1594 };
1948 1595
1949 i2s2_2ch_sclk: i2s2-2 1596 i2s2_2ch_sclk: i2s2-2ch-sclk {
1950 rockchip,pins 1597 rockchip,pins =
1951 <3 RK 1598 <3 RK_PA2 2 &pcfg_pull_none>;
1952 }; 1599 };
1953 1600
1954 i2s2_2ch_lrck: i2s2-2 1601 i2s2_2ch_lrck: i2s2-2ch-lrck {
1955 rockchip,pins 1602 rockchip,pins =
1956 <3 RK 1603 <3 RK_PA3 2 &pcfg_pull_none>;
1957 }; 1604 };
1958 1605
1959 i2s2_2ch_sdi: i2s2-2c 1606 i2s2_2ch_sdi: i2s2-2ch-sdi {
1960 rockchip,pins 1607 rockchip,pins =
1961 <3 RK 1608 <3 RK_PA5 2 &pcfg_pull_none>;
1962 }; 1609 };
1963 1610
1964 i2s2_2ch_sdo: i2s2-2c 1611 i2s2_2ch_sdo: i2s2-2ch-sdo {
1965 rockchip,pins 1612 rockchip,pins =
1966 <3 RK 1613 <3 RK_PA7 2 &pcfg_pull_none>;
1967 }; 1614 };
1968 }; 1615 };
1969 1616
1970 sdmmc { 1617 sdmmc {
1971 sdmmc_clk: sdmmc-clk 1618 sdmmc_clk: sdmmc-clk {
1972 rockchip,pins 1619 rockchip,pins =
1973 <1 RK 1620 <1 RK_PD6 1 &pcfg_pull_none_8ma>;
1974 }; 1621 };
1975 1622
1976 sdmmc_cmd: sdmmc-cmd 1623 sdmmc_cmd: sdmmc-cmd {
1977 rockchip,pins 1624 rockchip,pins =
1978 <1 RK 1625 <1 RK_PD7 1 &pcfg_pull_up_8ma>;
1979 }; 1626 };
1980 1627
1981 sdmmc_det: sdmmc-det 1628 sdmmc_det: sdmmc-det {
1982 rockchip,pins 1629 rockchip,pins =
1983 <0 RK 1630 <0 RK_PA3 1 &pcfg_pull_up_8ma>;
1984 }; 1631 };
1985 1632
1986 sdmmc_bus1: sdmmc-bus 1633 sdmmc_bus1: sdmmc-bus1 {
1987 rockchip,pins 1634 rockchip,pins =
1988 <1 RK 1635 <1 RK_PD2 1 &pcfg_pull_up_8ma>;
1989 }; 1636 };
1990 1637
1991 sdmmc_bus4: sdmmc-bus 1638 sdmmc_bus4: sdmmc-bus4 {
1992 rockchip,pins 1639 rockchip,pins =
1993 <1 RK 1640 <1 RK_PD2 1 &pcfg_pull_up_8ma>,
1994 <1 RK 1641 <1 RK_PD3 1 &pcfg_pull_up_8ma>,
1995 <1 RK 1642 <1 RK_PD4 1 &pcfg_pull_up_8ma>,
1996 <1 RK 1643 <1 RK_PD5 1 &pcfg_pull_up_8ma>;
1997 }; 1644 };
1998 }; 1645 };
1999 1646
2000 sdio { 1647 sdio {
2001 sdio_clk: sdio-clk { 1648 sdio_clk: sdio-clk {
2002 rockchip,pins 1649 rockchip,pins =
2003 <1 RK 1650 <1 RK_PC5 1 &pcfg_pull_none>;
2004 }; 1651 };
2005 1652
2006 sdio_cmd: sdio-cmd { 1653 sdio_cmd: sdio-cmd {
2007 rockchip,pins 1654 rockchip,pins =
2008 <1 RK 1655 <1 RK_PC4 1 &pcfg_pull_up>;
2009 }; 1656 };
2010 1657
2011 sdio_bus4: sdio-bus4 1658 sdio_bus4: sdio-bus4 {
2012 rockchip,pins 1659 rockchip,pins =
2013 <1 RK 1660 <1 RK_PC6 1 &pcfg_pull_up>,
2014 <1 RK 1661 <1 RK_PC7 1 &pcfg_pull_up>,
2015 <1 RK 1662 <1 RK_PD0 1 &pcfg_pull_up>,
2016 <1 RK 1663 <1 RK_PD1 1 &pcfg_pull_up>;
2017 }; 1664 };
2018 }; 1665 };
2019 1666
2020 emmc { 1667 emmc {
2021 emmc_clk: emmc-clk { 1668 emmc_clk: emmc-clk {
2022 rockchip,pins 1669 rockchip,pins =
2023 <1 RK 1670 <1 RK_PB1 2 &pcfg_pull_none_8ma>;
2024 }; 1671 };
2025 1672
2026 emmc_cmd: emmc-cmd { 1673 emmc_cmd: emmc-cmd {
2027 rockchip,pins 1674 rockchip,pins =
2028 <1 RK 1675 <1 RK_PB2 2 &pcfg_pull_up_8ma>;
2029 }; 1676 };
2030 1677
2031 emmc_rstnout: emmc-rs 1678 emmc_rstnout: emmc-rstnout {
2032 rockchip,pins 1679 rockchip,pins =
2033 <1 RK 1680 <1 RK_PB3 2 &pcfg_pull_none>;
2034 }; 1681 };
2035 1682
2036 emmc_bus1: emmc-bus1 1683 emmc_bus1: emmc-bus1 {
2037 rockchip,pins 1684 rockchip,pins =
2038 <1 RK 1685 <1 RK_PA0 2 &pcfg_pull_up_8ma>;
2039 }; 1686 };
2040 1687
2041 emmc_bus4: emmc-bus4 1688 emmc_bus4: emmc-bus4 {
2042 rockchip,pins 1689 rockchip,pins =
2043 <1 RK 1690 <1 RK_PA0 2 &pcfg_pull_up_8ma>,
2044 <1 RK 1691 <1 RK_PA1 2 &pcfg_pull_up_8ma>,
2045 <1 RK 1692 <1 RK_PA2 2 &pcfg_pull_up_8ma>,
2046 <1 RK 1693 <1 RK_PA3 2 &pcfg_pull_up_8ma>;
2047 }; 1694 };
2048 1695
2049 emmc_bus8: emmc-bus8 1696 emmc_bus8: emmc-bus8 {
2050 rockchip,pins 1697 rockchip,pins =
2051 <1 RK 1698 <1 RK_PA0 2 &pcfg_pull_up_8ma>,
2052 <1 RK 1699 <1 RK_PA1 2 &pcfg_pull_up_8ma>,
2053 <1 RK 1700 <1 RK_PA2 2 &pcfg_pull_up_8ma>,
2054 <1 RK 1701 <1 RK_PA3 2 &pcfg_pull_up_8ma>,
2055 <1 RK 1702 <1 RK_PA4 2 &pcfg_pull_up_8ma>,
2056 <1 RK 1703 <1 RK_PA5 2 &pcfg_pull_up_8ma>,
2057 <1 RK 1704 <1 RK_PA6 2 &pcfg_pull_up_8ma>,
2058 <1 RK 1705 <1 RK_PA7 2 &pcfg_pull_up_8ma>;
2059 }; 1706 };
2060 }; 1707 };
2061 1708
2062 flash { 1709 flash {
2063 flash_cs0: flash-cs0 1710 flash_cs0: flash-cs0 {
2064 rockchip,pins 1711 rockchip,pins =
2065 <1 RK 1712 <1 RK_PB0 1 &pcfg_pull_none>;
2066 }; 1713 };
2067 1714
2068 flash_rdy: flash-rdy 1715 flash_rdy: flash-rdy {
2069 rockchip,pins 1716 rockchip,pins =
2070 <1 RK 1717 <1 RK_PB1 1 &pcfg_pull_none>;
2071 }; 1718 };
2072 1719
2073 flash_dqs: flash-dqs 1720 flash_dqs: flash-dqs {
2074 rockchip,pins 1721 rockchip,pins =
2075 <1 RK 1722 <1 RK_PB2 1 &pcfg_pull_none>;
2076 }; 1723 };
2077 1724
2078 flash_ale: flash-ale 1725 flash_ale: flash-ale {
2079 rockchip,pins 1726 rockchip,pins =
2080 <1 RK 1727 <1 RK_PB3 1 &pcfg_pull_none>;
2081 }; 1728 };
2082 1729
2083 flash_cle: flash-cle 1730 flash_cle: flash-cle {
2084 rockchip,pins 1731 rockchip,pins =
2085 <1 RK 1732 <1 RK_PB4 1 &pcfg_pull_none>;
2086 }; 1733 };
2087 1734
2088 flash_wrn: flash-wrn 1735 flash_wrn: flash-wrn {
2089 rockchip,pins 1736 rockchip,pins =
2090 <1 RK 1737 <1 RK_PB5 1 &pcfg_pull_none>;
2091 }; 1738 };
2092 1739
2093 flash_csl: flash-csl 1740 flash_csl: flash-csl {
2094 rockchip,pins 1741 rockchip,pins =
2095 <1 RK 1742 <1 RK_PB6 1 &pcfg_pull_none>;
2096 }; 1743 };
2097 1744
2098 flash_rdn: flash-rdn 1745 flash_rdn: flash-rdn {
2099 rockchip,pins 1746 rockchip,pins =
2100 <1 RK 1747 <1 RK_PB7 1 &pcfg_pull_none>;
2101 }; 1748 };
2102 1749
2103 flash_bus8: flash-bus 1750 flash_bus8: flash-bus8 {
2104 rockchip,pins 1751 rockchip,pins =
2105 <1 RK 1752 <1 RK_PA0 1 &pcfg_pull_up_12ma>,
2106 <1 RK 1753 <1 RK_PA1 1 &pcfg_pull_up_12ma>,
2107 <1 RK 1754 <1 RK_PA2 1 &pcfg_pull_up_12ma>,
2108 <1 RK 1755 <1 RK_PA3 1 &pcfg_pull_up_12ma>,
2109 <1 RK 1756 <1 RK_PA4 1 &pcfg_pull_up_12ma>,
2110 <1 RK 1757 <1 RK_PA5 1 &pcfg_pull_up_12ma>,
2111 <1 RK 1758 <1 RK_PA6 1 &pcfg_pull_up_12ma>,
2112 <1 RK 1759 <1 RK_PA7 1 &pcfg_pull_up_12ma>;
2113 }; <<
2114 }; <<
2115 <<
2116 sfc { <<
2117 sfc_bus4: sfc-bus4 { <<
2118 rockchip,pins <<
2119 <1 RK <<
2120 <1 RK <<
2121 <1 RK <<
2122 <1 RK <<
2123 }; <<
2124 <<
2125 sfc_bus2: sfc-bus2 { <<
2126 rockchip,pins <<
2127 <1 RK <<
2128 <1 RK <<
2129 }; <<
2130 <<
2131 sfc_cs0: sfc-cs0 { <<
2132 rockchip,pins <<
2133 <1 RK <<
2134 }; <<
2135 <<
2136 sfc_clk: sfc-clk { <<
2137 rockchip,pins <<
2138 <1 RK <<
2139 }; 1760 };
2140 }; 1761 };
2141 1762
2142 lcdc { 1763 lcdc {
2143 lcdc_rgb_dclk_pin: lc 1764 lcdc_rgb_dclk_pin: lcdc-rgb-dclk-pin {
2144 rockchip,pins 1765 rockchip,pins =
2145 <3 RK 1766 <3 RK_PA0 1 &pcfg_pull_none_12ma>;
2146 }; 1767 };
2147 1768
2148 lcdc_rgb_m0_hsync_pin 1769 lcdc_rgb_m0_hsync_pin: lcdc-rgb-m0-hsync-pin {
2149 rockchip,pins 1770 rockchip,pins =
2150 <3 RK 1771 <3 RK_PA1 1 &pcfg_pull_none_12ma>;
2151 }; 1772 };
2152 1773
2153 lcdc_rgb_m0_vsync_pin 1774 lcdc_rgb_m0_vsync_pin: lcdc-rgb-m0-vsync-pin {
2154 rockchip,pins 1775 rockchip,pins =
2155 <3 RK 1776 <3 RK_PA2 1 &pcfg_pull_none_12ma>;
2156 }; 1777 };
2157 1778
2158 lcdc_rgb_m0_den_pin: 1779 lcdc_rgb_m0_den_pin: lcdc-rgb-m0-den-pin {
2159 rockchip,pins 1780 rockchip,pins =
2160 <3 RK 1781 <3 RK_PA3 1 &pcfg_pull_none_12ma>;
2161 }; 1782 };
2162 1783
2163 lcdc_rgb888_m0_data_p 1784 lcdc_rgb888_m0_data_pins: lcdc-rgb888-m0-data-pins {
2164 rockchip,pins 1785 rockchip,pins =
2165 <3 RK 1786 <3 RK_PA7 1 &pcfg_pull_none_8ma>, /* lcdc_d3 */
2166 <3 RK 1787 <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */
2167 <3 RK 1788 <3 RK_PA5 1 &pcfg_pull_none_8ma>, /* lcdc_d1 */
2168 <3 RK 1789 <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */
2169 <3 RK 1790 <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */
2170 <3 RK 1791 <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */
2171 <3 RK 1792 <3 RK_PB1 1 &pcfg_pull_none_8ma>, /* lcdc_d5 */
2172 <3 RK 1793 <3 RK_PB0 1 &pcfg_pull_none_8ma>, /* lcdc_d4 */
2173 <3 RK 1794 <3 RK_PB7 1 &pcfg_pull_none_8ma>, /* lcdc_d11 */
2174 <3 RK 1795 <3 RK_PB6 1 &pcfg_pull_none_8ma>, /* lcdc_d10 */
2175 <3 RK 1796 <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */
2176 <3 RK 1797 <3 RK_PB4 1 &pcfg_pull_none_8ma>, /* lcdc_d8 */
2177 <3 RK 1798 <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */
2178 <3 RK 1799 <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */
2179 <3 RK 1800 <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */
2180 <3 RK 1801 <3 RK_PC0 1 &pcfg_pull_none_8ma>, /* lcdc_d12 */
2181 <3 RK 1802 <3 RK_PC7 1 &pcfg_pull_none_8ma>, /* lcdc_d19 */
2182 <3 RK 1803 <3 RK_PC6 1 &pcfg_pull_none_8ma>, /* lcdc_d18 */
2183 <3 RK 1804 <3 RK_PC5 1 &pcfg_pull_none_8ma>, /* lcdc_d17 */
2184 <3 RK 1805 <3 RK_PC4 1 &pcfg_pull_none_8ma>, /* lcdc_d16 */
2185 <3 RK 1806 <3 RK_PD3 1 &pcfg_pull_none_8ma>, /* lcdc_d23 */
2186 <3 RK 1807 <3 RK_PD2 1 &pcfg_pull_none_8ma>, /* lcdc_d22 */
2187 <3 RK 1808 <3 RK_PD1 1 &pcfg_pull_none_8ma>, /* lcdc_d21 */
2188 <3 RK 1809 <3 RK_PD0 1 &pcfg_pull_none_8ma>; /* lcdc_d20 */
2189 }; 1810 };
2190 1811
2191 lcdc_rgb666_m0_data_p 1812 lcdc_rgb666_m0_data_pins: lcdc-rgb666-m0-data-pins {
2192 rockchip,pins 1813 rockchip,pins =
2193 <3 RK 1814 <3 RK_PA7 1 &pcfg_pull_none_8ma>, /* lcdc_d3 */
2194 <3 RK 1815 <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */
2195 <3 RK 1816 <3 RK_PA5 1 &pcfg_pull_none_8ma>, /* lcdc_d1 */
2196 <3 RK 1817 <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */
2197 <3 RK 1818 <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */
2198 <3 RK 1819 <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */
2199 <3 RK 1820 <3 RK_PB1 1 &pcfg_pull_none_8ma>, /* lcdc_d5 */
2200 <3 RK 1821 <3 RK_PB0 1 &pcfg_pull_none_8ma>, /* lcdc_d4 */
2201 <3 RK 1822 <3 RK_PB7 1 &pcfg_pull_none_8ma>, /* lcdc_d11 */
2202 <3 RK 1823 <3 RK_PB6 1 &pcfg_pull_none_8ma>, /* lcdc_d10 */
2203 <3 RK 1824 <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */
2204 <3 RK 1825 <3 RK_PB4 1 &pcfg_pull_none_8ma>, /* lcdc_d8 */
2205 <3 RK 1826 <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */
2206 <3 RK 1827 <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */
2207 <3 RK 1828 <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */
2208 <3 RK 1829 <3 RK_PC0 1 &pcfg_pull_none_8ma>, /* lcdc_d12 */
2209 <3 RK 1830 <3 RK_PC5 1 &pcfg_pull_none_8ma>, /* lcdc_d17 */
2210 <3 RK 1831 <3 RK_PC4 1 &pcfg_pull_none_8ma>; /* lcdc_d16 */
2211 }; 1832 };
2212 1833
2213 lcdc_rgb565_m0_data_p 1834 lcdc_rgb565_m0_data_pins: lcdc-rgb565-m0-data-pins {
2214 rockchip,pins 1835 rockchip,pins =
2215 <3 RK 1836 <3 RK_PA7 1 &pcfg_pull_none_8ma>, /* lcdc_d3 */
2216 <3 RK 1837 <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */
2217 <3 RK 1838 <3 RK_PA5 1 &pcfg_pull_none_8ma>, /* lcdc_d1 */
2218 <3 RK 1839 <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */
2219 <3 RK 1840 <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */
2220 <3 RK 1841 <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */
2221 <3 RK 1842 <3 RK_PB1 1 &pcfg_pull_none_8ma>, /* lcdc_d5 */
2222 <3 RK 1843 <3 RK_PB0 1 &pcfg_pull_none_8ma>, /* lcdc_d4 */
2223 <3 RK 1844 <3 RK_PB7 1 &pcfg_pull_none_8ma>, /* lcdc_d11 */
2224 <3 RK 1845 <3 RK_PB6 1 &pcfg_pull_none_8ma>, /* lcdc_d10 */
2225 <3 RK 1846 <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */
2226 <3 RK 1847 <3 RK_PB4 1 &pcfg_pull_none_8ma>, /* lcdc_d8 */
2227 <3 RK 1848 <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */
2228 <3 RK 1849 <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */
2229 <3 RK 1850 <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */
2230 <3 RK 1851 <3 RK_PC0 1 &pcfg_pull_none_8ma>; /* lcdc_d12 */
2231 }; 1852 };
2232 1853
2233 lcdc_rgb888_m1_data_p 1854 lcdc_rgb888_m1_data_pins: lcdc-rgb888-m1-data-pins {
2234 rockchip,pins 1855 rockchip,pins =
2235 <3 RK 1856 <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */
2236 <3 RK 1857 <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */
2237 <3 RK 1858 <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */
2238 <3 RK 1859 <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */
2239 <3 RK 1860 <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */
2240 <3 RK 1861 <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */
2241 <3 RK 1862 <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */
2242 <3 RK 1863 <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */
2243 <3 RK 1864 <3 RK_PC0 1 &pcfg_pull_none_8ma>, /* lcdc_d12 */
2244 <3 RK 1865 <3 RK_PC7 1 &pcfg_pull_none_8ma>, /* lcdc_d19 */
2245 <3 RK 1866 <3 RK_PC6 1 &pcfg_pull_none_8ma>, /* lcdc_d18 */
2246 <3 RK 1867 <3 RK_PC5 1 &pcfg_pull_none_8ma>, /* lcdc_d17 */
2247 <3 RK 1868 <3 RK_PC4 1 &pcfg_pull_none_8ma>, /* lcdc_d16 */
2248 <3 RK 1869 <3 RK_PD3 1 &pcfg_pull_none_8ma>, /* lcdc_d23 */
2249 <3 RK 1870 <3 RK_PD2 1 &pcfg_pull_none_8ma>, /* lcdc_d22 */
2250 <3 RK 1871 <3 RK_PD1 1 &pcfg_pull_none_8ma>, /* lcdc_d21 */
2251 <3 RK 1872 <3 RK_PD0 1 &pcfg_pull_none_8ma>; /* lcdc_d20 */
2252 }; 1873 };
2253 1874
2254 lcdc_rgb666_m1_data_p 1875 lcdc_rgb666_m1_data_pins: lcdc-rgb666-m1-data-pins {
2255 rockchip,pins 1876 rockchip,pins =
2256 <3 RK 1877 <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */
2257 <3 RK 1878 <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */
2258 <3 RK 1879 <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */
2259 <3 RK 1880 <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */
2260 <3 RK 1881 <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */
2261 <3 RK 1882 <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */
2262 <3 RK 1883 <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */
2263 <3 RK 1884 <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */
2264 <3 RK 1885 <3 RK_PC0 1 &pcfg_pull_none_8ma>, /* lcdc_d12 */
2265 <3 RK 1886 <3 RK_PC5 1 &pcfg_pull_none_8ma>, /* lcdc_d17 */
2266 <3 RK 1887 <3 RK_PC4 1 &pcfg_pull_none_8ma>; /* lcdc_d16 */
2267 }; 1888 };
2268 1889
2269 lcdc_rgb565_m1_data_p 1890 lcdc_rgb565_m1_data_pins: lcdc-rgb565-m1-data-pins {
2270 rockchip,pins 1891 rockchip,pins =
2271 <3 RK 1892 <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */
2272 <3 RK 1893 <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */
2273 <3 RK 1894 <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */
2274 <3 RK 1895 <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */
2275 <3 RK 1896 <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */
2276 <3 RK 1897 <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */
2277 <3 RK 1898 <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */
2278 <3 RK 1899 <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */
2279 <3 RK 1900 <3 RK_PC0 1 &pcfg_pull_none_8ma>; /* lcdc_d12 */
2280 }; 1901 };
2281 }; 1902 };
2282 1903
2283 pwm0 { 1904 pwm0 {
2284 pwm0_pin: pwm0-pin { 1905 pwm0_pin: pwm0-pin {
2285 rockchip,pins 1906 rockchip,pins =
2286 <0 RK 1907 <0 RK_PB7 1 &pcfg_pull_none>;
2287 }; 1908 };
2288 }; 1909 };
2289 1910
2290 pwm1 { 1911 pwm1 {
2291 pwm1_pin: pwm1-pin { 1912 pwm1_pin: pwm1-pin {
2292 rockchip,pins 1913 rockchip,pins =
2293 <0 RK 1914 <0 RK_PC0 1 &pcfg_pull_none>;
2294 }; 1915 };
2295 }; 1916 };
2296 1917
2297 pwm2 { 1918 pwm2 {
2298 pwm2_pin: pwm2-pin { 1919 pwm2_pin: pwm2-pin {
2299 rockchip,pins 1920 rockchip,pins =
2300 <2 RK 1921 <2 RK_PB5 1 &pcfg_pull_none>;
2301 }; 1922 };
2302 }; 1923 };
2303 1924
2304 pwm3 { 1925 pwm3 {
2305 pwm3_pin: pwm3-pin { 1926 pwm3_pin: pwm3-pin {
2306 rockchip,pins 1927 rockchip,pins =
2307 <0 RK 1928 <0 RK_PC1 1 &pcfg_pull_none>;
2308 }; 1929 };
2309 }; 1930 };
2310 1931
2311 pwm4 { 1932 pwm4 {
2312 pwm4_pin: pwm4-pin { 1933 pwm4_pin: pwm4-pin {
2313 rockchip,pins 1934 rockchip,pins =
2314 <3 RK 1935 <3 RK_PC2 3 &pcfg_pull_none>;
2315 }; 1936 };
2316 }; 1937 };
2317 1938
2318 pwm5 { 1939 pwm5 {
2319 pwm5_pin: pwm5-pin { 1940 pwm5_pin: pwm5-pin {
2320 rockchip,pins 1941 rockchip,pins =
2321 <3 RK 1942 <3 RK_PC3 3 &pcfg_pull_none>;
2322 }; 1943 };
2323 }; 1944 };
2324 1945
2325 pwm6 { 1946 pwm6 {
2326 pwm6_pin: pwm6-pin { 1947 pwm6_pin: pwm6-pin {
2327 rockchip,pins 1948 rockchip,pins =
2328 <3 RK 1949 <3 RK_PC4 3 &pcfg_pull_none>;
2329 }; 1950 };
2330 }; 1951 };
2331 1952
2332 pwm7 { 1953 pwm7 {
2333 pwm7_pin: pwm7-pin { 1954 pwm7_pin: pwm7-pin {
2334 rockchip,pins 1955 rockchip,pins =
2335 <3 RK 1956 <3 RK_PC5 3 &pcfg_pull_none>;
2336 }; 1957 };
2337 }; 1958 };
2338 1959
2339 gmac { 1960 gmac {
2340 rmii_pins: rmii-pins 1961 rmii_pins: rmii-pins {
2341 rockchip,pins 1962 rockchip,pins =
2342 <2 RK 1963 <2 RK_PA0 2 &pcfg_pull_none_12ma>, /* mac_txen */
2343 <2 RK 1964 <2 RK_PA1 2 &pcfg_pull_none_12ma>, /* mac_txd1 */
2344 <2 RK 1965 <2 RK_PA2 2 &pcfg_pull_none_12ma>, /* mac_txd0 */
2345 <2 RK 1966 <2 RK_PA3 2 &pcfg_pull_none>, /* mac_rxd0 */
2346 <2 RK 1967 <2 RK_PA4 2 &pcfg_pull_none>, /* mac_rxd1 */
2347 <2 RK 1968 <2 RK_PA5 2 &pcfg_pull_none>, /* mac_rxer */
2348 <2 RK 1969 <2 RK_PA6 2 &pcfg_pull_none>, /* mac_rxdv */
2349 <2 RK 1970 <2 RK_PA7 2 &pcfg_pull_none>, /* mac_mdio */
2350 <2 RK 1971 <2 RK_PB1 2 &pcfg_pull_none>; /* mac_mdc */
2351 }; 1972 };
2352 1973
2353 mac_refclk_12ma: mac- 1974 mac_refclk_12ma: mac-refclk-12ma {
2354 rockchip,pins 1975 rockchip,pins =
2355 <2 RK 1976 <2 RK_PB2 2 &pcfg_pull_none_12ma>;
2356 }; 1977 };
2357 1978
2358 mac_refclk: mac-refcl 1979 mac_refclk: mac-refclk {
2359 rockchip,pins 1980 rockchip,pins =
2360 <2 RK 1981 <2 RK_PB2 2 &pcfg_pull_none>;
2361 }; 1982 };
2362 }; 1983 };
2363 1984
2364 cif-m0 { 1985 cif-m0 {
2365 cif_clkout_m0: cif-cl 1986 cif_clkout_m0: cif-clkout-m0 {
2366 rockchip,pins 1987 rockchip,pins =
2367 <2 RK 1988 <2 RK_PB3 1 &pcfg_pull_none>;
2368 }; 1989 };
2369 1990
2370 dvp_d2d9_m0: dvp-d2d9 1991 dvp_d2d9_m0: dvp-d2d9-m0 {
2371 rockchip,pins 1992 rockchip,pins =
2372 <2 RK 1993 <2 RK_PA0 1 &pcfg_pull_none>, /* cif_data2 */
2373 <2 RK 1994 <2 RK_PA1 1 &pcfg_pull_none>, /* cif_data3 */
2374 <2 RK 1995 <2 RK_PA2 1 &pcfg_pull_none>, /* cif_data4 */
2375 <2 RK 1996 <2 RK_PA3 1 &pcfg_pull_none>, /* cif_data5 */
2376 <2 RK 1997 <2 RK_PA4 1 &pcfg_pull_none>, /* cif_data6 */
2377 <2 RK 1998 <2 RK_PA5 1 &pcfg_pull_none>, /* cif_data7 */
2378 <2 RK 1999 <2 RK_PA6 1 &pcfg_pull_none>, /* cif_data8 */
2379 <2 RK 2000 <2 RK_PA7 1 &pcfg_pull_none>, /* cif_data9 */
2380 <2 RK 2001 <2 RK_PB0 1 &pcfg_pull_none>, /* cif_sync */
2381 <2 RK 2002 <2 RK_PB1 1 &pcfg_pull_none>, /* cif_href */
2382 <2 RK 2003 <2 RK_PB2 1 &pcfg_pull_none>, /* cif_clkin */
2383 <2 RK 2004 <2 RK_PB3 1 &pcfg_pull_none>; /* cif_clkout */
2384 }; 2005 };
2385 2006
2386 dvp_d0d1_m0: dvp-d0d1 2007 dvp_d0d1_m0: dvp-d0d1-m0 {
2387 rockchip,pins 2008 rockchip,pins =
2388 <2 RK 2009 <2 RK_PB4 1 &pcfg_pull_none>, /* cif_data0 */
2389 <2 RK 2010 <2 RK_PB6 1 &pcfg_pull_none>; /* cif_data1 */
2390 }; 2011 };
2391 2012
2392 dvp_d10d11_m0:d10-d11 2013 dvp_d10d11_m0:d10-d11-m0 {
2393 rockchip,pins 2014 rockchip,pins =
2394 <2 RK 2015 <2 RK_PB7 1 &pcfg_pull_none>, /* cif_data10 */
2395 <2 RK 2016 <2 RK_PC0 1 &pcfg_pull_none>; /* cif_data11 */
2396 }; 2017 };
2397 }; 2018 };
2398 2019
2399 cif-m1 { 2020 cif-m1 {
2400 cif_clkout_m1: cif-cl 2021 cif_clkout_m1: cif-clkout-m1 {
2401 rockchip,pins 2022 rockchip,pins =
2402 <3 RK 2023 <3 RK_PD0 3 &pcfg_pull_none>;
2403 }; 2024 };
2404 2025
2405 dvp_d2d9_m1: dvp-d2d9 2026 dvp_d2d9_m1: dvp-d2d9-m1 {
2406 rockchip,pins 2027 rockchip,pins =
2407 <3 RK 2028 <3 RK_PA3 3 &pcfg_pull_none>, /* cif_data2 */
2408 <3 RK 2029 <3 RK_PA5 3 &pcfg_pull_none>, /* cif_data3 */
2409 <3 RK 2030 <3 RK_PA7 3 &pcfg_pull_none>, /* cif_data4 */
2410 <3 RK 2031 <3 RK_PB0 3 &pcfg_pull_none>, /* cif_data5 */
2411 <3 RK 2032 <3 RK_PB1 3 &pcfg_pull_none>, /* cif_data6 */
2412 <3 RK 2033 <3 RK_PB4 3 &pcfg_pull_none>, /* cif_data7 */
2413 <3 RK 2034 <3 RK_PB6 3 &pcfg_pull_none>, /* cif_data8 */
2414 <3 RK 2035 <3 RK_PB7 3 &pcfg_pull_none>, /* cif_data9 */
2415 <3 RK 2036 <3 RK_PD1 3 &pcfg_pull_none>, /* cif_sync */
2416 <3 RK 2037 <3 RK_PD2 3 &pcfg_pull_none>, /* cif_href */
2417 <3 RK 2038 <3 RK_PD3 3 &pcfg_pull_none>, /* cif_clkin */
2418 <3 RK 2039 <3 RK_PD0 3 &pcfg_pull_none>; /* cif_clkout */
2419 }; 2040 };
2420 2041
2421 dvp_d0d1_m1: dvp-d0d1 2042 dvp_d0d1_m1: dvp-d0d1-m1 {
2422 rockchip,pins 2043 rockchip,pins =
2423 <3 RK 2044 <3 RK_PA1 3 &pcfg_pull_none>, /* cif_data0 */
2424 <3 RK 2045 <3 RK_PA2 3 &pcfg_pull_none>; /* cif_data1 */
2425 }; 2046 };
2426 2047
2427 dvp_d10d11_m1:d10-d11 2048 dvp_d10d11_m1:d10-d11-m1 {
2428 rockchip,pins 2049 rockchip,pins =
2429 <3 RK 2050 <3 RK_PC6 3 &pcfg_pull_none>, /* cif_data10 */
2430 <3 RK 2051 <3 RK_PC7 3 &pcfg_pull_none>; /* cif_data11 */
2431 }; 2052 };
2432 }; 2053 };
2433 2054
2434 isp { 2055 isp {
2435 isp_prelight: isp-pre 2056 isp_prelight: isp-prelight {
2436 rockchip,pins 2057 rockchip,pins =
2437 <3 RK 2058 <3 RK_PD1 4 &pcfg_pull_none>;
2438 }; 2059 };
2439 }; 2060 };
2440 }; 2061 };
2441 }; 2062 };
Linux® is a registered trademark of Linus Torvalds in the United States and other countries.
TOMOYO® is a registered trademark of NTT DATA CORPORATION.