1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /* 2 /*
3 * Copyright (c) 2018 Fuzhou Rockchip Electron 3 * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd
4 */ 4 */
5 5
6 #include <dt-bindings/clock/px30-cru.h> 6 #include <dt-bindings/clock/px30-cru.h>
7 #include <dt-bindings/gpio/gpio.h> 7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/interrupt-controller/arm 8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/interrupt-controller/irq 9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/pinctrl/rockchip.h> 10 #include <dt-bindings/pinctrl/rockchip.h>
11 #include <dt-bindings/power/px30-power.h> 11 #include <dt-bindings/power/px30-power.h>
12 #include <dt-bindings/soc/rockchip,boot-mode.h 12 #include <dt-bindings/soc/rockchip,boot-mode.h>
13 #include <dt-bindings/thermal/thermal.h> 13 #include <dt-bindings/thermal/thermal.h>
14 14
15 / { 15 / {
16 compatible = "rockchip,px30"; 16 compatible = "rockchip,px30";
17 17
18 interrupt-parent = <&gic>; 18 interrupt-parent = <&gic>;
19 #address-cells = <2>; 19 #address-cells = <2>;
20 #size-cells = <2>; 20 #size-cells = <2>;
21 21
22 aliases { 22 aliases {
>> 23 ethernet0 = &gmac;
23 i2c0 = &i2c0; 24 i2c0 = &i2c0;
24 i2c1 = &i2c1; 25 i2c1 = &i2c1;
25 i2c2 = &i2c2; 26 i2c2 = &i2c2;
26 i2c3 = &i2c3; 27 i2c3 = &i2c3;
27 serial0 = &uart0; 28 serial0 = &uart0;
28 serial1 = &uart1; 29 serial1 = &uart1;
29 serial2 = &uart2; 30 serial2 = &uart2;
30 serial3 = &uart3; 31 serial3 = &uart3;
31 serial4 = &uart4; 32 serial4 = &uart4;
32 serial5 = &uart5; 33 serial5 = &uart5;
33 spi0 = &spi0; 34 spi0 = &spi0;
34 spi1 = &spi1; 35 spi1 = &spi1;
35 }; 36 };
36 37
37 cpus { 38 cpus {
38 #address-cells = <2>; 39 #address-cells = <2>;
39 #size-cells = <0>; 40 #size-cells = <0>;
40 41
41 cpu0: cpu@0 { 42 cpu0: cpu@0 {
42 device_type = "cpu"; 43 device_type = "cpu";
43 compatible = "arm,cort 44 compatible = "arm,cortex-a35";
44 reg = <0x0 0x0>; 45 reg = <0x0 0x0>;
45 enable-method = "psci" 46 enable-method = "psci";
46 clocks = <&cru ARMCLK> 47 clocks = <&cru ARMCLK>;
47 #cooling-cells = <2>; 48 #cooling-cells = <2>;
48 cpu-idle-states = <&CP 49 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
49 dynamic-power-coeffici 50 dynamic-power-coefficient = <90>;
50 operating-points-v2 = 51 operating-points-v2 = <&cpu0_opp_table>;
51 }; 52 };
52 53
53 cpu1: cpu@1 { 54 cpu1: cpu@1 {
54 device_type = "cpu"; 55 device_type = "cpu";
55 compatible = "arm,cort 56 compatible = "arm,cortex-a35";
56 reg = <0x0 0x1>; 57 reg = <0x0 0x1>;
57 enable-method = "psci" 58 enable-method = "psci";
58 clocks = <&cru ARMCLK> 59 clocks = <&cru ARMCLK>;
59 #cooling-cells = <2>; 60 #cooling-cells = <2>;
60 cpu-idle-states = <&CP 61 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
61 dynamic-power-coeffici 62 dynamic-power-coefficient = <90>;
62 operating-points-v2 = 63 operating-points-v2 = <&cpu0_opp_table>;
63 }; 64 };
64 65
65 cpu2: cpu@2 { 66 cpu2: cpu@2 {
66 device_type = "cpu"; 67 device_type = "cpu";
67 compatible = "arm,cort 68 compatible = "arm,cortex-a35";
68 reg = <0x0 0x2>; 69 reg = <0x0 0x2>;
69 enable-method = "psci" 70 enable-method = "psci";
70 clocks = <&cru ARMCLK> 71 clocks = <&cru ARMCLK>;
71 #cooling-cells = <2>; 72 #cooling-cells = <2>;
72 cpu-idle-states = <&CP 73 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
73 dynamic-power-coeffici 74 dynamic-power-coefficient = <90>;
74 operating-points-v2 = 75 operating-points-v2 = <&cpu0_opp_table>;
75 }; 76 };
76 77
77 cpu3: cpu@3 { 78 cpu3: cpu@3 {
78 device_type = "cpu"; 79 device_type = "cpu";
79 compatible = "arm,cort 80 compatible = "arm,cortex-a35";
80 reg = <0x0 0x3>; 81 reg = <0x0 0x3>;
81 enable-method = "psci" 82 enable-method = "psci";
82 clocks = <&cru ARMCLK> 83 clocks = <&cru ARMCLK>;
83 #cooling-cells = <2>; 84 #cooling-cells = <2>;
84 cpu-idle-states = <&CP 85 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
85 dynamic-power-coeffici 86 dynamic-power-coefficient = <90>;
86 operating-points-v2 = 87 operating-points-v2 = <&cpu0_opp_table>;
87 }; 88 };
88 89
89 idle-states { 90 idle-states {
90 entry-method = "psci"; 91 entry-method = "psci";
91 92
92 CPU_SLEEP: cpu-sleep { 93 CPU_SLEEP: cpu-sleep {
93 compatible = " 94 compatible = "arm,idle-state";
94 local-timer-st 95 local-timer-stop;
95 arm,psci-suspe 96 arm,psci-suspend-param = <0x0010000>;
96 entry-latency- 97 entry-latency-us = <120>;
97 exit-latency-u 98 exit-latency-us = <250>;
98 min-residency- 99 min-residency-us = <900>;
99 }; 100 };
100 101
101 CLUSTER_SLEEP: cluster 102 CLUSTER_SLEEP: cluster-sleep {
102 compatible = " 103 compatible = "arm,idle-state";
103 local-timer-st 104 local-timer-stop;
104 arm,psci-suspe 105 arm,psci-suspend-param = <0x1010000>;
105 entry-latency- 106 entry-latency-us = <400>;
106 exit-latency-u 107 exit-latency-us = <500>;
107 min-residency- 108 min-residency-us = <2000>;
108 }; 109 };
109 }; 110 };
110 }; 111 };
111 112
112 cpu0_opp_table: opp-table-0 { 113 cpu0_opp_table: opp-table-0 {
113 compatible = "operating-points 114 compatible = "operating-points-v2";
114 opp-shared; 115 opp-shared;
115 116
116 opp-600000000 { 117 opp-600000000 {
117 opp-hz = /bits/ 64 <60 118 opp-hz = /bits/ 64 <600000000>;
118 opp-microvolt = <95000 119 opp-microvolt = <950000 950000 1350000>;
119 clock-latency-ns = <40 120 clock-latency-ns = <40000>;
120 opp-suspend; 121 opp-suspend;
121 }; 122 };
122 opp-816000000 { 123 opp-816000000 {
123 opp-hz = /bits/ 64 <81 124 opp-hz = /bits/ 64 <816000000>;
124 opp-microvolt = <10500 125 opp-microvolt = <1050000 1050000 1350000>;
125 clock-latency-ns = <40 126 clock-latency-ns = <40000>;
126 }; 127 };
127 opp-1008000000 { 128 opp-1008000000 {
128 opp-hz = /bits/ 64 <10 129 opp-hz = /bits/ 64 <1008000000>;
129 opp-microvolt = <11750 130 opp-microvolt = <1175000 1175000 1350000>;
130 clock-latency-ns = <40 131 clock-latency-ns = <40000>;
131 }; 132 };
132 opp-1200000000 { 133 opp-1200000000 {
133 opp-hz = /bits/ 64 <12 134 opp-hz = /bits/ 64 <1200000000>;
134 opp-microvolt = <13000 135 opp-microvolt = <1300000 1300000 1350000>;
135 clock-latency-ns = <40 136 clock-latency-ns = <40000>;
136 }; 137 };
137 opp-1296000000 { 138 opp-1296000000 {
138 opp-hz = /bits/ 64 <12 139 opp-hz = /bits/ 64 <1296000000>;
139 opp-microvolt = <13500 140 opp-microvolt = <1350000 1350000 1350000>;
140 clock-latency-ns = <40 141 clock-latency-ns = <40000>;
141 }; 142 };
142 }; 143 };
143 144
144 arm-pmu { 145 arm-pmu {
145 compatible = "arm,cortex-a35-p 146 compatible = "arm,cortex-a35-pmu";
146 interrupts = <GIC_SPI 100 IRQ_ 147 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
147 <GIC_SPI 101 IRQ_ 148 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
148 <GIC_SPI 102 IRQ_ 149 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
149 <GIC_SPI 103 IRQ_ 150 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
150 interrupt-affinity = <&cpu0>, 151 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
151 }; 152 };
152 153
153 display_subsystem: display-subsystem { 154 display_subsystem: display-subsystem {
154 compatible = "rockchip,display 155 compatible = "rockchip,display-subsystem";
155 ports = <&vopb_out>, <&vopl_ou 156 ports = <&vopb_out>, <&vopl_out>;
156 status = "disabled"; 157 status = "disabled";
157 }; 158 };
158 159
159 gmac_clkin: external-gmac-clock { 160 gmac_clkin: external-gmac-clock {
160 compatible = "fixed-clock"; 161 compatible = "fixed-clock";
161 clock-frequency = <50000000>; 162 clock-frequency = <50000000>;
162 clock-output-names = "gmac_clk 163 clock-output-names = "gmac_clkin";
163 #clock-cells = <0>; 164 #clock-cells = <0>;
164 }; 165 };
165 166
166 psci { 167 psci {
167 compatible = "arm,psci-1.0"; 168 compatible = "arm,psci-1.0";
168 method = "smc"; 169 method = "smc";
169 }; 170 };
170 171
171 timer { 172 timer {
172 compatible = "arm,armv8-timer" 173 compatible = "arm,armv8-timer";
173 interrupts = <GIC_PPI 13 (GIC_ 174 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
174 <GIC_PPI 14 (GIC_ 175 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
175 <GIC_PPI 11 (GIC_ 176 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
176 <GIC_PPI 10 (GIC_ 177 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
177 }; 178 };
178 179
179 thermal_zones: thermal-zones { 180 thermal_zones: thermal-zones {
180 soc_thermal: soc-thermal { 181 soc_thermal: soc-thermal {
181 polling-delay-passive 182 polling-delay-passive = <20>;
182 polling-delay = <1000> 183 polling-delay = <1000>;
183 sustainable-power = <7 184 sustainable-power = <750>;
184 thermal-sensors = <&ts 185 thermal-sensors = <&tsadc 0>;
185 186
186 trips { 187 trips {
187 threshold: tri 188 threshold: trip-point-0 {
188 temper 189 temperature = <70000>;
189 hyster 190 hysteresis = <2000>;
190 type = 191 type = "passive";
191 }; 192 };
192 193
193 target: trip-p 194 target: trip-point-1 {
194 temper 195 temperature = <85000>;
195 hyster 196 hysteresis = <2000>;
196 type = 197 type = "passive";
197 }; 198 };
198 199
199 soc_crit: soc- 200 soc_crit: soc-crit {
200 temper 201 temperature = <115000>;
201 hyster 202 hysteresis = <2000>;
202 type = 203 type = "critical";
203 }; 204 };
204 }; 205 };
205 206
206 cooling-maps { 207 cooling-maps {
207 map0 { 208 map0 {
208 trip = 209 trip = <&target>;
209 coolin 210 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
210 contri 211 contribution = <4096>;
211 }; 212 };
>> 213
>> 214 map1 {
>> 215 trip = <&target>;
>> 216 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
>> 217 contribution = <4096>;
>> 218 };
212 }; 219 };
213 }; 220 };
214 221
215 gpu_thermal: gpu-thermal { 222 gpu_thermal: gpu-thermal {
216 polling-delay-passive 223 polling-delay-passive = <100>; /* milliseconds */
217 polling-delay = <1000> 224 polling-delay = <1000>; /* milliseconds */
218 thermal-sensors = <&ts 225 thermal-sensors = <&tsadc 1>;
219 <<
220 trips { <<
221 gpu_threshold: <<
222 temper <<
223 hyster <<
224 type = <<
225 }; <<
226 <<
227 gpu_target: gp <<
228 temper <<
229 hyster <<
230 type = <<
231 }; <<
232 <<
233 gpu_crit: gpu- <<
234 temper <<
235 hyster <<
236 type = <<
237 }; <<
238 }; <<
239 <<
240 cooling-maps { <<
241 map0 { <<
242 trip = <<
243 coolin <<
244 }; <<
245 }; <<
246 }; 226 };
247 }; 227 };
248 228
249 xin24m: xin24m { 229 xin24m: xin24m {
250 compatible = "fixed-clock"; 230 compatible = "fixed-clock";
251 #clock-cells = <0>; 231 #clock-cells = <0>;
252 clock-frequency = <24000000>; 232 clock-frequency = <24000000>;
253 clock-output-names = "xin24m"; 233 clock-output-names = "xin24m";
254 }; 234 };
255 235
256 pmu: power-management@ff000000 { 236 pmu: power-management@ff000000 {
257 compatible = "rockchip,px30-pm 237 compatible = "rockchip,px30-pmu", "syscon", "simple-mfd";
258 reg = <0x0 0xff000000 0x0 0x10 238 reg = <0x0 0xff000000 0x0 0x1000>;
259 239
260 power: power-controller { 240 power: power-controller {
261 compatible = "rockchip 241 compatible = "rockchip,px30-power-controller";
262 #power-domain-cells = 242 #power-domain-cells = <1>;
263 #address-cells = <1>; 243 #address-cells = <1>;
264 #size-cells = <0>; 244 #size-cells = <0>;
265 245
266 /* These power domains 246 /* These power domains are grouped by VD_LOGIC */
267 power-domain@PX30_PD_U 247 power-domain@PX30_PD_USB {
268 reg = <PX30_PD 248 reg = <PX30_PD_USB>;
269 clocks = <&cru 249 clocks = <&cru HCLK_HOST>,
270 <&cru 250 <&cru HCLK_OTG>,
271 <&cru 251 <&cru SCLK_OTG_ADP>;
272 pm_qos = <&qos 252 pm_qos = <&qos_usb_host>, <&qos_usb_otg>;
273 #power-domain- 253 #power-domain-cells = <0>;
274 }; 254 };
275 power-domain@PX30_PD_S 255 power-domain@PX30_PD_SDCARD {
276 reg = <PX30_PD 256 reg = <PX30_PD_SDCARD>;
277 clocks = <&cru 257 clocks = <&cru HCLK_SDMMC>,
278 <&cru 258 <&cru SCLK_SDMMC>;
279 pm_qos = <&qos 259 pm_qos = <&qos_sdmmc>;
280 #power-domain- 260 #power-domain-cells = <0>;
281 }; 261 };
282 power-domain@PX30_PD_G 262 power-domain@PX30_PD_GMAC {
283 reg = <PX30_PD 263 reg = <PX30_PD_GMAC>;
284 clocks = <&cru 264 clocks = <&cru ACLK_GMAC>,
285 <&cru 265 <&cru PCLK_GMAC>,
286 <&cru 266 <&cru SCLK_MAC_REF>,
287 <&cru 267 <&cru SCLK_GMAC_RX_TX>;
288 pm_qos = <&qos 268 pm_qos = <&qos_gmac>;
289 #power-domain- 269 #power-domain-cells = <0>;
290 }; 270 };
291 power-domain@PX30_PD_M 271 power-domain@PX30_PD_MMC_NAND {
292 reg = <PX30_PD 272 reg = <PX30_PD_MMC_NAND>;
293 clocks = <&cru !! 273 clocks = <&cru HCLK_NANDC>,
294 <&cru !! 274 <&cru HCLK_EMMC>,
295 <&cru !! 275 <&cru HCLK_SDIO>,
296 <&cru !! 276 <&cru HCLK_SFC>,
297 <&cru !! 277 <&cru SCLK_EMMC>,
298 <&cru !! 278 <&cru SCLK_NANDC>,
299 <&cru !! 279 <&cru SCLK_SDIO>,
300 <&cru !! 280 <&cru SCLK_SFC>;
301 pm_qos = <&qos 281 pm_qos = <&qos_emmc>, <&qos_nand>,
302 <&qos 282 <&qos_sdio>, <&qos_sfc>;
303 #power-domain- 283 #power-domain-cells = <0>;
304 }; 284 };
305 power-domain@PX30_PD_V 285 power-domain@PX30_PD_VPU {
306 reg = <PX30_PD 286 reg = <PX30_PD_VPU>;
307 clocks = <&cru 287 clocks = <&cru ACLK_VPU>,
308 <&cru 288 <&cru HCLK_VPU>,
309 <&cru 289 <&cru SCLK_CORE_VPU>;
310 pm_qos = <&qos 290 pm_qos = <&qos_vpu>, <&qos_vpu_r128>;
311 #power-domain- 291 #power-domain-cells = <0>;
312 }; 292 };
313 power-domain@PX30_PD_V 293 power-domain@PX30_PD_VO {
314 reg = <PX30_PD 294 reg = <PX30_PD_VO>;
315 clocks = <&cru 295 clocks = <&cru ACLK_RGA>,
316 <&cru 296 <&cru ACLK_VOPB>,
317 <&cru 297 <&cru ACLK_VOPL>,
318 <&cru 298 <&cru DCLK_VOPB>,
319 <&cru 299 <&cru DCLK_VOPL>,
320 <&cru 300 <&cru HCLK_RGA>,
321 <&cru 301 <&cru HCLK_VOPB>,
322 <&cru 302 <&cru HCLK_VOPL>,
323 <&cru 303 <&cru PCLK_MIPI_DSI>,
324 <&cru 304 <&cru SCLK_RGA_CORE>,
325 <&cru 305 <&cru SCLK_VOPB_PWM>;
326 pm_qos = <&qos 306 pm_qos = <&qos_rga_rd>, <&qos_rga_wr>,
327 <&qos 307 <&qos_vop_m0>, <&qos_vop_m1>;
328 #power-domain- 308 #power-domain-cells = <0>;
329 }; 309 };
330 power-domain@PX30_PD_V 310 power-domain@PX30_PD_VI {
331 reg = <PX30_PD 311 reg = <PX30_PD_VI>;
332 clocks = <&cru 312 clocks = <&cru ACLK_CIF>,
333 <&cru 313 <&cru ACLK_ISP>,
334 <&cru 314 <&cru HCLK_CIF>,
335 <&cru 315 <&cru HCLK_ISP>,
336 <&cru 316 <&cru SCLK_ISP>;
337 pm_qos = <&qos 317 pm_qos = <&qos_isp_128>, <&qos_isp_rd>,
338 <&qos 318 <&qos_isp_wr>, <&qos_isp_m1>,
339 <&qos 319 <&qos_vip>;
340 #power-domain- 320 #power-domain-cells = <0>;
341 }; 321 };
342 power-domain@PX30_PD_G 322 power-domain@PX30_PD_GPU {
343 reg = <PX30_PD 323 reg = <PX30_PD_GPU>;
344 clocks = <&cru 324 clocks = <&cru SCLK_GPU>;
345 pm_qos = <&qos 325 pm_qos = <&qos_gpu>;
346 #power-domain- 326 #power-domain-cells = <0>;
347 }; 327 };
348 }; 328 };
349 }; 329 };
350 330
351 pmugrf: syscon@ff010000 { 331 pmugrf: syscon@ff010000 {
352 compatible = "rockchip,px30-pm 332 compatible = "rockchip,px30-pmugrf", "syscon", "simple-mfd";
353 reg = <0x0 0xff010000 0x0 0x10 333 reg = <0x0 0xff010000 0x0 0x1000>;
354 #address-cells = <1>; 334 #address-cells = <1>;
355 #size-cells = <1>; 335 #size-cells = <1>;
356 336
357 pmu_io_domains: io-domains { 337 pmu_io_domains: io-domains {
358 compatible = "rockchip 338 compatible = "rockchip,px30-pmu-io-voltage-domain";
359 status = "disabled"; 339 status = "disabled";
360 }; 340 };
361 341
362 reboot-mode { 342 reboot-mode {
363 compatible = "syscon-r 343 compatible = "syscon-reboot-mode";
364 offset = <0x200>; 344 offset = <0x200>;
365 mode-bootloader = <BOO 345 mode-bootloader = <BOOT_BL_DOWNLOAD>;
366 mode-fastboot = <BOOT_ 346 mode-fastboot = <BOOT_FASTBOOT>;
367 mode-loader = <BOOT_BL 347 mode-loader = <BOOT_BL_DOWNLOAD>;
368 mode-normal = <BOOT_NO 348 mode-normal = <BOOT_NORMAL>;
369 mode-recovery = <BOOT_ 349 mode-recovery = <BOOT_RECOVERY>;
370 }; 350 };
371 }; 351 };
372 352
373 uart0: serial@ff030000 { 353 uart0: serial@ff030000 {
374 compatible = "rockchip,px30-ua 354 compatible = "rockchip,px30-uart", "snps,dw-apb-uart";
375 reg = <0x0 0xff030000 0x0 0x10 355 reg = <0x0 0xff030000 0x0 0x100>;
376 interrupts = <GIC_SPI 15 IRQ_T 356 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
377 clocks = <&pmucru SCLK_UART0_P 357 clocks = <&pmucru SCLK_UART0_PMU>, <&pmucru PCLK_UART0_PMU>;
378 clock-names = "baudclk", "apb_ 358 clock-names = "baudclk", "apb_pclk";
379 dmas = <&dmac 0>, <&dmac 1>; 359 dmas = <&dmac 0>, <&dmac 1>;
380 dma-names = "tx", "rx"; 360 dma-names = "tx", "rx";
381 reg-shift = <2>; 361 reg-shift = <2>;
382 reg-io-width = <4>; 362 reg-io-width = <4>;
383 pinctrl-names = "default"; 363 pinctrl-names = "default";
384 pinctrl-0 = <&uart0_xfer &uart 364 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
385 status = "disabled"; 365 status = "disabled";
386 }; 366 };
387 367
388 i2s0_8ch: i2s@ff060000 { 368 i2s0_8ch: i2s@ff060000 {
389 compatible = "rockchip,px30-i2 369 compatible = "rockchip,px30-i2s-tdm";
390 reg = <0x0 0xff060000 0x0 0x10 370 reg = <0x0 0xff060000 0x0 0x1000>;
391 interrupts = <GIC_SPI 12 IRQ_T 371 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
392 clocks = <&cru SCLK_I2S0_TX>, 372 clocks = <&cru SCLK_I2S0_TX>, <&cru SCLK_I2S0_RX>, <&cru HCLK_I2S0>;
393 clock-names = "mclk_tx", "mclk 373 clock-names = "mclk_tx", "mclk_rx", "hclk";
394 dmas = <&dmac 16>, <&dmac 17>; 374 dmas = <&dmac 16>, <&dmac 17>;
395 dma-names = "tx", "rx"; 375 dma-names = "tx", "rx";
396 rockchip,grf = <&grf>; 376 rockchip,grf = <&grf>;
397 resets = <&cru SRST_I2S0_TX>, 377 resets = <&cru SRST_I2S0_TX>, <&cru SRST_I2S0_RX>;
398 reset-names = "tx-m", "rx-m"; 378 reset-names = "tx-m", "rx-m";
399 pinctrl-names = "default"; 379 pinctrl-names = "default";
400 pinctrl-0 = <&i2s0_8ch_sclktx 380 pinctrl-0 = <&i2s0_8ch_sclktx &i2s0_8ch_sclkrx
401 &i2s0_8ch_lrcktx 381 &i2s0_8ch_lrcktx &i2s0_8ch_lrckrx
402 &i2s0_8ch_sdo0 &i 382 &i2s0_8ch_sdo0 &i2s0_8ch_sdi0
403 &i2s0_8ch_sdo1 &i 383 &i2s0_8ch_sdo1 &i2s0_8ch_sdi1
404 &i2s0_8ch_sdo2 &i 384 &i2s0_8ch_sdo2 &i2s0_8ch_sdi2
405 &i2s0_8ch_sdo3 &i 385 &i2s0_8ch_sdo3 &i2s0_8ch_sdi3>;
406 #sound-dai-cells = <0>; 386 #sound-dai-cells = <0>;
407 status = "disabled"; 387 status = "disabled";
408 }; 388 };
409 389
410 i2s1_2ch: i2s@ff070000 { 390 i2s1_2ch: i2s@ff070000 {
411 compatible = "rockchip,px30-i2 391 compatible = "rockchip,px30-i2s", "rockchip,rk3066-i2s";
412 reg = <0x0 0xff070000 0x0 0x10 392 reg = <0x0 0xff070000 0x0 0x1000>;
413 interrupts = <GIC_SPI 13 IRQ_T 393 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
414 clocks = <&cru SCLK_I2S1>, <&c 394 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1>;
415 clock-names = "i2s_clk", "i2s_ 395 clock-names = "i2s_clk", "i2s_hclk";
416 dmas = <&dmac 18>, <&dmac 19>; 396 dmas = <&dmac 18>, <&dmac 19>;
417 dma-names = "tx", "rx"; 397 dma-names = "tx", "rx";
418 pinctrl-names = "default"; 398 pinctrl-names = "default";
419 pinctrl-0 = <&i2s1_2ch_sclk &i 399 pinctrl-0 = <&i2s1_2ch_sclk &i2s1_2ch_lrck
420 &i2s1_2ch_sdi &i2 400 &i2s1_2ch_sdi &i2s1_2ch_sdo>;
421 #sound-dai-cells = <0>; 401 #sound-dai-cells = <0>;
422 status = "disabled"; 402 status = "disabled";
423 }; 403 };
424 404
425 i2s2_2ch: i2s@ff080000 { 405 i2s2_2ch: i2s@ff080000 {
426 compatible = "rockchip,px30-i2 406 compatible = "rockchip,px30-i2s", "rockchip,rk3066-i2s";
427 reg = <0x0 0xff080000 0x0 0x10 407 reg = <0x0 0xff080000 0x0 0x1000>;
428 interrupts = <GIC_SPI 14 IRQ_T 408 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
429 clocks = <&cru SCLK_I2S2>, <&c 409 clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2>;
430 clock-names = "i2s_clk", "i2s_ 410 clock-names = "i2s_clk", "i2s_hclk";
431 dmas = <&dmac 20>, <&dmac 21>; 411 dmas = <&dmac 20>, <&dmac 21>;
432 dma-names = "tx", "rx"; 412 dma-names = "tx", "rx";
433 pinctrl-names = "default"; 413 pinctrl-names = "default";
434 pinctrl-0 = <&i2s2_2ch_sclk &i 414 pinctrl-0 = <&i2s2_2ch_sclk &i2s2_2ch_lrck
435 &i2s2_2ch_sdi &i2 415 &i2s2_2ch_sdi &i2s2_2ch_sdo>;
436 #sound-dai-cells = <0>; 416 #sound-dai-cells = <0>;
437 status = "disabled"; 417 status = "disabled";
438 }; 418 };
439 419
440 gic: interrupt-controller@ff131000 { 420 gic: interrupt-controller@ff131000 {
441 compatible = "arm,gic-400"; 421 compatible = "arm,gic-400";
442 #interrupt-cells = <3>; 422 #interrupt-cells = <3>;
443 #address-cells = <0>; 423 #address-cells = <0>;
444 interrupt-controller; 424 interrupt-controller;
445 reg = <0x0 0xff131000 0 0x1000 425 reg = <0x0 0xff131000 0 0x1000>,
446 <0x0 0xff132000 0 0x2000 426 <0x0 0xff132000 0 0x2000>,
447 <0x0 0xff134000 0 0x2000 427 <0x0 0xff134000 0 0x2000>,
448 <0x0 0xff136000 0 0x2000 428 <0x0 0xff136000 0 0x2000>;
449 interrupts = <GIC_PPI 9 429 interrupts = <GIC_PPI 9
450 (GIC_CPU_MASK_SIMPLE(4) 430 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
451 }; 431 };
452 432
453 grf: syscon@ff140000 { 433 grf: syscon@ff140000 {
454 compatible = "rockchip,px30-gr 434 compatible = "rockchip,px30-grf", "syscon", "simple-mfd";
455 reg = <0x0 0xff140000 0x0 0x10 435 reg = <0x0 0xff140000 0x0 0x1000>;
456 #address-cells = <1>; 436 #address-cells = <1>;
457 #size-cells = <1>; 437 #size-cells = <1>;
458 438
459 io_domains: io-domains { 439 io_domains: io-domains {
460 compatible = "rockchip 440 compatible = "rockchip,px30-io-voltage-domain";
461 status = "disabled"; 441 status = "disabled";
462 }; 442 };
463 443
464 lvds: lvds { 444 lvds: lvds {
465 compatible = "rockchip 445 compatible = "rockchip,px30-lvds";
466 phys = <&dsi_dphy>; 446 phys = <&dsi_dphy>;
467 phy-names = "dphy"; 447 phy-names = "dphy";
468 rockchip,grf = <&grf>; 448 rockchip,grf = <&grf>;
469 rockchip,output = "lvd 449 rockchip,output = "lvds";
470 status = "disabled"; 450 status = "disabled";
471 451
472 ports { 452 ports {
473 #address-cells 453 #address-cells = <1>;
474 #size-cells = 454 #size-cells = <0>;
475 455
476 lvds_in: port@ !! 456 port@0 {
477 reg = 457 reg = <0>;
478 #addre 458 #address-cells = <1>;
479 #size- 459 #size-cells = <0>;
480 460
481 lvds_v 461 lvds_vopb_in: endpoint@0 {
482 462 reg = <0>;
483 463 remote-endpoint = <&vopb_out_lvds>;
484 }; 464 };
485 465
486 lvds_v 466 lvds_vopl_in: endpoint@1 {
487 467 reg = <1>;
488 468 remote-endpoint = <&vopl_out_lvds>;
489 }; 469 };
490 }; 470 };
491 <<
492 lvds_out: port <<
493 reg = <<
494 }; <<
495 }; 471 };
496 }; 472 };
497 }; 473 };
498 474
499 uart1: serial@ff158000 { 475 uart1: serial@ff158000 {
500 compatible = "rockchip,px30-ua 476 compatible = "rockchip,px30-uart", "snps,dw-apb-uart";
501 reg = <0x0 0xff158000 0x0 0x10 477 reg = <0x0 0xff158000 0x0 0x100>;
502 interrupts = <GIC_SPI 16 IRQ_T 478 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
503 clocks = <&cru SCLK_UART1>, <& 479 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
504 clock-names = "baudclk", "apb_ 480 clock-names = "baudclk", "apb_pclk";
505 dmas = <&dmac 2>, <&dmac 3>; 481 dmas = <&dmac 2>, <&dmac 3>;
506 dma-names = "tx", "rx"; 482 dma-names = "tx", "rx";
507 reg-shift = <2>; 483 reg-shift = <2>;
508 reg-io-width = <4>; 484 reg-io-width = <4>;
509 pinctrl-names = "default"; 485 pinctrl-names = "default";
510 pinctrl-0 = <&uart1_xfer &uart 486 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
511 status = "disabled"; 487 status = "disabled";
512 }; 488 };
513 489
514 uart2: serial@ff160000 { 490 uart2: serial@ff160000 {
515 compatible = "rockchip,px30-ua 491 compatible = "rockchip,px30-uart", "snps,dw-apb-uart";
516 reg = <0x0 0xff160000 0x0 0x10 492 reg = <0x0 0xff160000 0x0 0x100>;
517 interrupts = <GIC_SPI 17 IRQ_T 493 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
518 clocks = <&cru SCLK_UART2>, <& 494 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
519 clock-names = "baudclk", "apb_ 495 clock-names = "baudclk", "apb_pclk";
520 dmas = <&dmac 4>, <&dmac 5>; 496 dmas = <&dmac 4>, <&dmac 5>;
521 dma-names = "tx", "rx"; 497 dma-names = "tx", "rx";
522 reg-shift = <2>; 498 reg-shift = <2>;
523 reg-io-width = <4>; 499 reg-io-width = <4>;
524 pinctrl-names = "default"; 500 pinctrl-names = "default";
525 pinctrl-0 = <&uart2m0_xfer>; 501 pinctrl-0 = <&uart2m0_xfer>;
526 status = "disabled"; 502 status = "disabled";
527 }; 503 };
528 504
529 uart3: serial@ff168000 { 505 uart3: serial@ff168000 {
530 compatible = "rockchip,px30-ua 506 compatible = "rockchip,px30-uart", "snps,dw-apb-uart";
531 reg = <0x0 0xff168000 0x0 0x10 507 reg = <0x0 0xff168000 0x0 0x100>;
532 interrupts = <GIC_SPI 18 IRQ_T 508 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
533 clocks = <&cru SCLK_UART3>, <& 509 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
534 clock-names = "baudclk", "apb_ 510 clock-names = "baudclk", "apb_pclk";
535 dmas = <&dmac 6>, <&dmac 7>; 511 dmas = <&dmac 6>, <&dmac 7>;
536 dma-names = "tx", "rx"; 512 dma-names = "tx", "rx";
537 reg-shift = <2>; 513 reg-shift = <2>;
538 reg-io-width = <4>; 514 reg-io-width = <4>;
539 pinctrl-names = "default"; 515 pinctrl-names = "default";
540 pinctrl-0 = <&uart3m1_xfer &ua 516 pinctrl-0 = <&uart3m1_xfer &uart3m1_cts &uart3m1_rts>;
541 status = "disabled"; 517 status = "disabled";
542 }; 518 };
543 519
544 uart4: serial@ff170000 { 520 uart4: serial@ff170000 {
545 compatible = "rockchip,px30-ua 521 compatible = "rockchip,px30-uart", "snps,dw-apb-uart";
546 reg = <0x0 0xff170000 0x0 0x10 522 reg = <0x0 0xff170000 0x0 0x100>;
547 interrupts = <GIC_SPI 19 IRQ_T 523 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
548 clocks = <&cru SCLK_UART4>, <& 524 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
549 clock-names = "baudclk", "apb_ 525 clock-names = "baudclk", "apb_pclk";
550 dmas = <&dmac 8>, <&dmac 9>; 526 dmas = <&dmac 8>, <&dmac 9>;
551 dma-names = "tx", "rx"; 527 dma-names = "tx", "rx";
552 reg-shift = <2>; 528 reg-shift = <2>;
553 reg-io-width = <4>; 529 reg-io-width = <4>;
554 pinctrl-names = "default"; 530 pinctrl-names = "default";
555 pinctrl-0 = <&uart4_xfer &uart 531 pinctrl-0 = <&uart4_xfer &uart4_cts &uart4_rts>;
556 status = "disabled"; 532 status = "disabled";
557 }; 533 };
558 534
559 uart5: serial@ff178000 { 535 uart5: serial@ff178000 {
560 compatible = "rockchip,px30-ua 536 compatible = "rockchip,px30-uart", "snps,dw-apb-uart";
561 reg = <0x0 0xff178000 0x0 0x10 537 reg = <0x0 0xff178000 0x0 0x100>;
562 interrupts = <GIC_SPI 20 IRQ_T 538 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
563 clocks = <&cru SCLK_UART5>, <& 539 clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>;
564 clock-names = "baudclk", "apb_ 540 clock-names = "baudclk", "apb_pclk";
565 dmas = <&dmac 10>, <&dmac 11>; 541 dmas = <&dmac 10>, <&dmac 11>;
566 dma-names = "tx", "rx"; 542 dma-names = "tx", "rx";
567 reg-shift = <2>; 543 reg-shift = <2>;
568 reg-io-width = <4>; 544 reg-io-width = <4>;
569 pinctrl-names = "default"; 545 pinctrl-names = "default";
570 pinctrl-0 = <&uart5_xfer &uart 546 pinctrl-0 = <&uart5_xfer &uart5_cts &uart5_rts>;
571 status = "disabled"; 547 status = "disabled";
572 }; 548 };
573 549
574 i2c0: i2c@ff180000 { 550 i2c0: i2c@ff180000 {
575 compatible = "rockchip,px30-i2 551 compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c";
576 reg = <0x0 0xff180000 0x0 0x10 552 reg = <0x0 0xff180000 0x0 0x1000>;
577 clocks = <&cru SCLK_I2C0>, <&c 553 clocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>;
578 clock-names = "i2c", "pclk"; 554 clock-names = "i2c", "pclk";
579 interrupts = <GIC_SPI 7 IRQ_TY 555 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
580 pinctrl-names = "default"; 556 pinctrl-names = "default";
581 pinctrl-0 = <&i2c0_xfer>; 557 pinctrl-0 = <&i2c0_xfer>;
582 #address-cells = <1>; 558 #address-cells = <1>;
583 #size-cells = <0>; 559 #size-cells = <0>;
584 status = "disabled"; 560 status = "disabled";
585 }; 561 };
586 562
587 i2c1: i2c@ff190000 { 563 i2c1: i2c@ff190000 {
588 compatible = "rockchip,px30-i2 564 compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c";
589 reg = <0x0 0xff190000 0x0 0x10 565 reg = <0x0 0xff190000 0x0 0x1000>;
590 clocks = <&cru SCLK_I2C1>, <&c 566 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
591 clock-names = "i2c", "pclk"; 567 clock-names = "i2c", "pclk";
592 interrupts = <GIC_SPI 8 IRQ_TY 568 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
593 pinctrl-names = "default"; 569 pinctrl-names = "default";
594 pinctrl-0 = <&i2c1_xfer>; 570 pinctrl-0 = <&i2c1_xfer>;
595 #address-cells = <1>; 571 #address-cells = <1>;
596 #size-cells = <0>; 572 #size-cells = <0>;
597 status = "disabled"; 573 status = "disabled";
598 }; 574 };
599 575
600 i2c2: i2c@ff1a0000 { 576 i2c2: i2c@ff1a0000 {
601 compatible = "rockchip,px30-i2 577 compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c";
602 reg = <0x0 0xff1a0000 0x0 0x10 578 reg = <0x0 0xff1a0000 0x0 0x1000>;
603 clocks = <&cru SCLK_I2C2>, <&c 579 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
604 clock-names = "i2c", "pclk"; 580 clock-names = "i2c", "pclk";
605 interrupts = <GIC_SPI 9 IRQ_TY 581 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
606 pinctrl-names = "default"; 582 pinctrl-names = "default";
607 pinctrl-0 = <&i2c2_xfer>; 583 pinctrl-0 = <&i2c2_xfer>;
608 #address-cells = <1>; 584 #address-cells = <1>;
609 #size-cells = <0>; 585 #size-cells = <0>;
610 status = "disabled"; 586 status = "disabled";
611 }; 587 };
612 588
613 i2c3: i2c@ff1b0000 { 589 i2c3: i2c@ff1b0000 {
614 compatible = "rockchip,px30-i2 590 compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c";
615 reg = <0x0 0xff1b0000 0x0 0x10 591 reg = <0x0 0xff1b0000 0x0 0x1000>;
616 clocks = <&cru SCLK_I2C3>, <&c 592 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
617 clock-names = "i2c", "pclk"; 593 clock-names = "i2c", "pclk";
618 interrupts = <GIC_SPI 10 IRQ_T 594 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
619 pinctrl-names = "default"; 595 pinctrl-names = "default";
620 pinctrl-0 = <&i2c3_xfer>; 596 pinctrl-0 = <&i2c3_xfer>;
621 #address-cells = <1>; 597 #address-cells = <1>;
622 #size-cells = <0>; 598 #size-cells = <0>;
623 status = "disabled"; 599 status = "disabled";
624 }; 600 };
625 601
626 spi0: spi@ff1d0000 { 602 spi0: spi@ff1d0000 {
627 compatible = "rockchip,px30-sp 603 compatible = "rockchip,px30-spi", "rockchip,rk3066-spi";
628 reg = <0x0 0xff1d0000 0x0 0x10 604 reg = <0x0 0xff1d0000 0x0 0x1000>;
629 interrupts = <GIC_SPI 26 IRQ_T 605 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
630 clocks = <&cru SCLK_SPI0>, <&c 606 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
631 clock-names = "spiclk", "apb_p 607 clock-names = "spiclk", "apb_pclk";
632 dmas = <&dmac 12>, <&dmac 13>; 608 dmas = <&dmac 12>, <&dmac 13>;
633 dma-names = "tx", "rx"; 609 dma-names = "tx", "rx";
634 num-cs = <2>; 610 num-cs = <2>;
635 pinctrl-names = "default"; 611 pinctrl-names = "default";
636 pinctrl-0 = <&spi0_clk &spi0_c 612 pinctrl-0 = <&spi0_clk &spi0_csn &spi0_miso &spi0_mosi>;
637 #address-cells = <1>; 613 #address-cells = <1>;
638 #size-cells = <0>; 614 #size-cells = <0>;
639 status = "disabled"; 615 status = "disabled";
640 }; 616 };
641 617
642 spi1: spi@ff1d8000 { 618 spi1: spi@ff1d8000 {
643 compatible = "rockchip,px30-sp 619 compatible = "rockchip,px30-spi", "rockchip,rk3066-spi";
644 reg = <0x0 0xff1d8000 0x0 0x10 620 reg = <0x0 0xff1d8000 0x0 0x1000>;
645 interrupts = <GIC_SPI 27 IRQ_T 621 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
646 clocks = <&cru SCLK_SPI1>, <&c 622 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
647 clock-names = "spiclk", "apb_p 623 clock-names = "spiclk", "apb_pclk";
648 dmas = <&dmac 14>, <&dmac 15>; 624 dmas = <&dmac 14>, <&dmac 15>;
649 dma-names = "tx", "rx"; 625 dma-names = "tx", "rx";
650 num-cs = <2>; 626 num-cs = <2>;
651 pinctrl-names = "default"; 627 pinctrl-names = "default";
652 pinctrl-0 = <&spi1_clk &spi1_c 628 pinctrl-0 = <&spi1_clk &spi1_csn0 &spi1_csn1 &spi1_miso &spi1_mosi>;
653 #address-cells = <1>; 629 #address-cells = <1>;
654 #size-cells = <0>; 630 #size-cells = <0>;
655 status = "disabled"; 631 status = "disabled";
656 }; 632 };
657 633
658 wdt: watchdog@ff1e0000 { 634 wdt: watchdog@ff1e0000 {
659 compatible = "rockchip,px30-wd 635 compatible = "rockchip,px30-wdt", "snps,dw-wdt";
660 reg = <0x0 0xff1e0000 0x0 0x10 636 reg = <0x0 0xff1e0000 0x0 0x100>;
661 clocks = <&cru PCLK_WDT_NS>; 637 clocks = <&cru PCLK_WDT_NS>;
662 interrupts = <GIC_SPI 37 IRQ_T 638 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
663 status = "disabled"; 639 status = "disabled";
664 }; 640 };
665 641
666 pwm0: pwm@ff200000 { 642 pwm0: pwm@ff200000 {
667 compatible = "rockchip,px30-pw 643 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
668 reg = <0x0 0xff200000 0x0 0x10 644 reg = <0x0 0xff200000 0x0 0x10>;
669 clocks = <&cru SCLK_PWM0>, <&c 645 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
670 clock-names = "pwm", "pclk"; 646 clock-names = "pwm", "pclk";
671 pinctrl-names = "default"; 647 pinctrl-names = "default";
672 pinctrl-0 = <&pwm0_pin>; 648 pinctrl-0 = <&pwm0_pin>;
673 #pwm-cells = <3>; 649 #pwm-cells = <3>;
674 status = "disabled"; 650 status = "disabled";
675 }; 651 };
676 652
677 pwm1: pwm@ff200010 { 653 pwm1: pwm@ff200010 {
678 compatible = "rockchip,px30-pw 654 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
679 reg = <0x0 0xff200010 0x0 0x10 655 reg = <0x0 0xff200010 0x0 0x10>;
680 clocks = <&cru SCLK_PWM0>, <&c 656 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
681 clock-names = "pwm", "pclk"; 657 clock-names = "pwm", "pclk";
682 pinctrl-names = "default"; 658 pinctrl-names = "default";
683 pinctrl-0 = <&pwm1_pin>; 659 pinctrl-0 = <&pwm1_pin>;
684 #pwm-cells = <3>; 660 #pwm-cells = <3>;
685 status = "disabled"; 661 status = "disabled";
686 }; 662 };
687 663
688 pwm2: pwm@ff200020 { 664 pwm2: pwm@ff200020 {
689 compatible = "rockchip,px30-pw 665 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
690 reg = <0x0 0xff200020 0x0 0x10 666 reg = <0x0 0xff200020 0x0 0x10>;
691 clocks = <&cru SCLK_PWM0>, <&c 667 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
692 clock-names = "pwm", "pclk"; 668 clock-names = "pwm", "pclk";
693 pinctrl-names = "default"; 669 pinctrl-names = "default";
694 pinctrl-0 = <&pwm2_pin>; 670 pinctrl-0 = <&pwm2_pin>;
695 #pwm-cells = <3>; 671 #pwm-cells = <3>;
696 status = "disabled"; 672 status = "disabled";
697 }; 673 };
698 674
699 pwm3: pwm@ff200030 { 675 pwm3: pwm@ff200030 {
700 compatible = "rockchip,px30-pw 676 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
701 reg = <0x0 0xff200030 0x0 0x10 677 reg = <0x0 0xff200030 0x0 0x10>;
702 clocks = <&cru SCLK_PWM0>, <&c 678 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
703 clock-names = "pwm", "pclk"; 679 clock-names = "pwm", "pclk";
704 pinctrl-names = "default"; 680 pinctrl-names = "default";
705 pinctrl-0 = <&pwm3_pin>; 681 pinctrl-0 = <&pwm3_pin>;
706 #pwm-cells = <3>; 682 #pwm-cells = <3>;
707 status = "disabled"; 683 status = "disabled";
708 }; 684 };
709 685
710 pwm4: pwm@ff208000 { 686 pwm4: pwm@ff208000 {
711 compatible = "rockchip,px30-pw 687 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
712 reg = <0x0 0xff208000 0x0 0x10 688 reg = <0x0 0xff208000 0x0 0x10>;
713 clocks = <&cru SCLK_PWM1>, <&c 689 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>;
714 clock-names = "pwm", "pclk"; 690 clock-names = "pwm", "pclk";
715 pinctrl-names = "default"; 691 pinctrl-names = "default";
716 pinctrl-0 = <&pwm4_pin>; 692 pinctrl-0 = <&pwm4_pin>;
717 #pwm-cells = <3>; 693 #pwm-cells = <3>;
718 status = "disabled"; 694 status = "disabled";
719 }; 695 };
720 696
721 pwm5: pwm@ff208010 { 697 pwm5: pwm@ff208010 {
722 compatible = "rockchip,px30-pw 698 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
723 reg = <0x0 0xff208010 0x0 0x10 699 reg = <0x0 0xff208010 0x0 0x10>;
724 clocks = <&cru SCLK_PWM1>, <&c 700 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>;
725 clock-names = "pwm", "pclk"; 701 clock-names = "pwm", "pclk";
726 pinctrl-names = "default"; 702 pinctrl-names = "default";
727 pinctrl-0 = <&pwm5_pin>; 703 pinctrl-0 = <&pwm5_pin>;
728 #pwm-cells = <3>; 704 #pwm-cells = <3>;
729 status = "disabled"; 705 status = "disabled";
730 }; 706 };
731 707
732 pwm6: pwm@ff208020 { 708 pwm6: pwm@ff208020 {
733 compatible = "rockchip,px30-pw 709 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
734 reg = <0x0 0xff208020 0x0 0x10 710 reg = <0x0 0xff208020 0x0 0x10>;
735 clocks = <&cru SCLK_PWM1>, <&c 711 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>;
736 clock-names = "pwm", "pclk"; 712 clock-names = "pwm", "pclk";
737 pinctrl-names = "default"; 713 pinctrl-names = "default";
738 pinctrl-0 = <&pwm6_pin>; 714 pinctrl-0 = <&pwm6_pin>;
739 #pwm-cells = <3>; 715 #pwm-cells = <3>;
740 status = "disabled"; 716 status = "disabled";
741 }; 717 };
742 718
743 pwm7: pwm@ff208030 { 719 pwm7: pwm@ff208030 {
744 compatible = "rockchip,px30-pw 720 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
745 reg = <0x0 0xff208030 0x0 0x10 721 reg = <0x0 0xff208030 0x0 0x10>;
746 clocks = <&cru SCLK_PWM1>, <&c 722 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>;
747 clock-names = "pwm", "pclk"; 723 clock-names = "pwm", "pclk";
748 pinctrl-names = "default"; 724 pinctrl-names = "default";
749 pinctrl-0 = <&pwm7_pin>; 725 pinctrl-0 = <&pwm7_pin>;
750 #pwm-cells = <3>; 726 #pwm-cells = <3>;
751 status = "disabled"; 727 status = "disabled";
752 }; 728 };
753 729
754 rktimer: timer@ff210000 { 730 rktimer: timer@ff210000 {
755 compatible = "rockchip,px30-ti 731 compatible = "rockchip,px30-timer", "rockchip,rk3288-timer";
756 reg = <0x0 0xff210000 0x0 0x10 732 reg = <0x0 0xff210000 0x0 0x1000>;
757 interrupts = <GIC_SPI 30 IRQ_T 733 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
758 clocks = <&cru PCLK_TIMER>, <& 734 clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER0>;
759 clock-names = "pclk", "timer"; 735 clock-names = "pclk", "timer";
760 }; 736 };
761 737
762 dmac: dma-controller@ff240000 { 738 dmac: dma-controller@ff240000 {
763 compatible = "arm,pl330", "arm 739 compatible = "arm,pl330", "arm,primecell";
764 reg = <0x0 0xff240000 0x0 0x40 740 reg = <0x0 0xff240000 0x0 0x4000>;
765 interrupts = <GIC_SPI 1 IRQ_TY 741 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
766 <GIC_SPI 2 IRQ_TY 742 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
767 arm,pl330-periph-burst; 743 arm,pl330-periph-burst;
768 clocks = <&cru ACLK_DMAC>; 744 clocks = <&cru ACLK_DMAC>;
769 clock-names = "apb_pclk"; 745 clock-names = "apb_pclk";
770 #dma-cells = <1>; 746 #dma-cells = <1>;
771 }; 747 };
772 748
773 tsadc: tsadc@ff280000 { 749 tsadc: tsadc@ff280000 {
774 compatible = "rockchip,px30-ts 750 compatible = "rockchip,px30-tsadc";
775 reg = <0x0 0xff280000 0x0 0x10 751 reg = <0x0 0xff280000 0x0 0x100>;
776 interrupts = <GIC_SPI 36 IRQ_T 752 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
777 assigned-clocks = <&cru SCLK_T 753 assigned-clocks = <&cru SCLK_TSADC>;
778 assigned-clock-rates = <50000> 754 assigned-clock-rates = <50000>;
779 clocks = <&cru SCLK_TSADC>, <& 755 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
780 clock-names = "tsadc", "apb_pc 756 clock-names = "tsadc", "apb_pclk";
781 resets = <&cru SRST_TSADC>; 757 resets = <&cru SRST_TSADC>;
782 reset-names = "tsadc-apb"; 758 reset-names = "tsadc-apb";
783 rockchip,grf = <&grf>; 759 rockchip,grf = <&grf>;
784 rockchip,hw-tshut-temp = <1200 760 rockchip,hw-tshut-temp = <120000>;
785 pinctrl-names = "init", "defau 761 pinctrl-names = "init", "default", "sleep";
786 pinctrl-0 = <&tsadc_otp_pin>; 762 pinctrl-0 = <&tsadc_otp_pin>;
787 pinctrl-1 = <&tsadc_otp_out>; 763 pinctrl-1 = <&tsadc_otp_out>;
788 pinctrl-2 = <&tsadc_otp_pin>; 764 pinctrl-2 = <&tsadc_otp_pin>;
789 #thermal-sensor-cells = <1>; 765 #thermal-sensor-cells = <1>;
790 status = "disabled"; 766 status = "disabled";
791 }; 767 };
792 768
793 saradc: saradc@ff288000 { 769 saradc: saradc@ff288000 {
794 compatible = "rockchip,px30-sa 770 compatible = "rockchip,px30-saradc", "rockchip,rk3399-saradc";
795 reg = <0x0 0xff288000 0x0 0x10 771 reg = <0x0 0xff288000 0x0 0x100>;
796 interrupts = <GIC_SPI 84 IRQ_T 772 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
797 #io-channel-cells = <1>; 773 #io-channel-cells = <1>;
798 clocks = <&cru SCLK_SARADC>, < 774 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
799 clock-names = "saradc", "apb_p 775 clock-names = "saradc", "apb_pclk";
800 resets = <&cru SRST_SARADC_P>; 776 resets = <&cru SRST_SARADC_P>;
801 reset-names = "saradc-apb"; 777 reset-names = "saradc-apb";
802 status = "disabled"; 778 status = "disabled";
803 }; 779 };
804 780
805 otp: nvmem@ff290000 { 781 otp: nvmem@ff290000 {
806 compatible = "rockchip,px30-ot 782 compatible = "rockchip,px30-otp";
807 reg = <0x0 0xff290000 0x0 0x40 783 reg = <0x0 0xff290000 0x0 0x4000>;
808 clocks = <&cru SCLK_OTP_USR>, 784 clocks = <&cru SCLK_OTP_USR>, <&cru PCLK_OTP_NS>,
809 <&cru PCLK_OTP_PHY>; 785 <&cru PCLK_OTP_PHY>;
810 clock-names = "otp", "apb_pclk 786 clock-names = "otp", "apb_pclk", "phy";
811 resets = <&cru SRST_OTP_PHY>; 787 resets = <&cru SRST_OTP_PHY>;
812 reset-names = "phy"; 788 reset-names = "phy";
813 #address-cells = <1>; 789 #address-cells = <1>;
814 #size-cells = <1>; 790 #size-cells = <1>;
815 791
816 /* Data cells */ 792 /* Data cells */
817 cpu_id: id@7 { 793 cpu_id: id@7 {
818 reg = <0x07 0x10>; 794 reg = <0x07 0x10>;
819 }; 795 };
820 cpu_leakage: cpu-leakage@17 { 796 cpu_leakage: cpu-leakage@17 {
821 reg = <0x17 0x1>; 797 reg = <0x17 0x1>;
822 }; 798 };
823 performance: performance@1e { 799 performance: performance@1e {
824 reg = <0x1e 0x1>; 800 reg = <0x1e 0x1>;
825 bits = <4 3>; 801 bits = <4 3>;
826 }; 802 };
827 }; 803 };
828 804
829 cru: clock-controller@ff2b0000 { 805 cru: clock-controller@ff2b0000 {
830 compatible = "rockchip,px30-cr 806 compatible = "rockchip,px30-cru";
831 reg = <0x0 0xff2b0000 0x0 0x10 807 reg = <0x0 0xff2b0000 0x0 0x1000>;
832 clocks = <&xin24m>, <&pmucru P 808 clocks = <&xin24m>, <&pmucru PLL_GPLL>;
833 clock-names = "xin24m", "gpll" 809 clock-names = "xin24m", "gpll";
834 rockchip,grf = <&grf>; 810 rockchip,grf = <&grf>;
835 #clock-cells = <1>; 811 #clock-cells = <1>;
836 #reset-cells = <1>; 812 #reset-cells = <1>;
837 813
838 assigned-clocks = <&cru PLL_NP 814 assigned-clocks = <&cru PLL_NPLL>,
839 <&cru ACLK_BUS_PRE>, < 815 <&cru ACLK_BUS_PRE>, <&cru ACLK_PERI_PRE>,
840 <&cru HCLK_BUS_PRE>, < 816 <&cru HCLK_BUS_PRE>, <&cru HCLK_PERI_PRE>,
841 <&cru PCLK_BUS_PRE>, < 817 <&cru PCLK_BUS_PRE>, <&cru SCLK_GPU>;
842 818
843 assigned-clock-rates = <118800 819 assigned-clock-rates = <1188000000>,
844 <200000000>, <20000000 820 <200000000>, <200000000>,
845 <150000000>, <15000000 821 <150000000>, <150000000>,
846 <100000000>, <20000000 822 <100000000>, <200000000>;
847 }; 823 };
848 824
849 pmucru: clock-controller@ff2bc000 { 825 pmucru: clock-controller@ff2bc000 {
850 compatible = "rockchip,px30-pm 826 compatible = "rockchip,px30-pmucru";
851 reg = <0x0 0xff2bc000 0x0 0x10 827 reg = <0x0 0xff2bc000 0x0 0x1000>;
852 clocks = <&xin24m>; 828 clocks = <&xin24m>;
853 clock-names = "xin24m"; 829 clock-names = "xin24m";
854 rockchip,grf = <&grf>; 830 rockchip,grf = <&grf>;
855 #clock-cells = <1>; 831 #clock-cells = <1>;
856 #reset-cells = <1>; 832 #reset-cells = <1>;
857 833
858 assigned-clocks = 834 assigned-clocks =
859 <&pmucru PLL_GPLL>, <& 835 <&pmucru PLL_GPLL>, <&pmucru PCLK_PMU_PRE>,
860 <&pmucru SCLK_WIFI_PMU 836 <&pmucru SCLK_WIFI_PMU>;
861 assigned-clock-rates = 837 assigned-clock-rates =
862 <1200000000>, <1000000 838 <1200000000>, <100000000>,
863 <26000000>; 839 <26000000>;
864 }; 840 };
865 841
866 usb2phy_grf: syscon@ff2c0000 { 842 usb2phy_grf: syscon@ff2c0000 {
867 compatible = "rockchip,px30-us 843 compatible = "rockchip,px30-usb2phy-grf", "syscon",
868 "simple-mfd"; 844 "simple-mfd";
869 reg = <0x0 0xff2c0000 0x0 0x10 845 reg = <0x0 0xff2c0000 0x0 0x10000>;
870 #address-cells = <1>; 846 #address-cells = <1>;
871 #size-cells = <1>; 847 #size-cells = <1>;
872 848
873 u2phy: usb2phy@100 { 849 u2phy: usb2phy@100 {
874 compatible = "rockchip 850 compatible = "rockchip,px30-usb2phy";
875 reg = <0x100 0x20>; 851 reg = <0x100 0x20>;
876 clocks = <&pmucru SCLK 852 clocks = <&pmucru SCLK_USBPHY_REF>;
877 clock-names = "phyclk" 853 clock-names = "phyclk";
878 #clock-cells = <0>; 854 #clock-cells = <0>;
879 assigned-clocks = <&cr 855 assigned-clocks = <&cru USB480M>;
880 assigned-clock-parents 856 assigned-clock-parents = <&u2phy>;
881 clock-output-names = " 857 clock-output-names = "usb480m_phy";
882 status = "disabled"; 858 status = "disabled";
883 859
884 u2phy_host: host-port 860 u2phy_host: host-port {
885 #phy-cells = < 861 #phy-cells = <0>;
886 interrupts = < 862 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
887 interrupt-name 863 interrupt-names = "linestate";
888 status = "disa 864 status = "disabled";
889 }; 865 };
890 866
891 u2phy_otg: otg-port { 867 u2phy_otg: otg-port {
892 #phy-cells = < 868 #phy-cells = <0>;
893 interrupts = < 869 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
894 < 870 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
895 < 871 <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
896 interrupt-name 872 interrupt-names = "otg-bvalid", "otg-id",
897 873 "linestate";
898 status = "disa 874 status = "disabled";
899 }; 875 };
900 }; 876 };
901 }; 877 };
902 878
903 dsi_dphy: phy@ff2e0000 { 879 dsi_dphy: phy@ff2e0000 {
904 compatible = "rockchip,px30-ds 880 compatible = "rockchip,px30-dsi-dphy";
905 reg = <0x0 0xff2e0000 0x0 0x10 881 reg = <0x0 0xff2e0000 0x0 0x10000>;
906 clocks = <&pmucru SCLK_MIPIDSI 882 clocks = <&pmucru SCLK_MIPIDSIPHY_REF>, <&cru PCLK_MIPIDSIPHY>;
907 clock-names = "ref", "pclk"; 883 clock-names = "ref", "pclk";
908 resets = <&cru SRST_MIPIDSIPHY 884 resets = <&cru SRST_MIPIDSIPHY_P>;
909 reset-names = "apb"; 885 reset-names = "apb";
910 #phy-cells = <0>; 886 #phy-cells = <0>;
911 power-domains = <&power PX30_P 887 power-domains = <&power PX30_PD_VO>;
912 status = "disabled"; 888 status = "disabled";
913 }; 889 };
914 890
915 csi_dphy: phy@ff2f0000 { 891 csi_dphy: phy@ff2f0000 {
916 compatible = "rockchip,px30-cs 892 compatible = "rockchip,px30-csi-dphy";
917 reg = <0x0 0xff2f0000 0x0 0x40 893 reg = <0x0 0xff2f0000 0x0 0x4000>;
918 clocks = <&cru PCLK_MIPICSIPHY 894 clocks = <&cru PCLK_MIPICSIPHY>;
919 clock-names = "pclk"; 895 clock-names = "pclk";
920 #phy-cells = <0>; 896 #phy-cells = <0>;
921 power-domains = <&power PX30_P 897 power-domains = <&power PX30_PD_VI>;
922 resets = <&cru SRST_MIPICSIPHY 898 resets = <&cru SRST_MIPICSIPHY_P>;
923 reset-names = "apb"; 899 reset-names = "apb";
924 rockchip,grf = <&grf>; 900 rockchip,grf = <&grf>;
925 status = "disabled"; 901 status = "disabled";
926 }; 902 };
927 903
928 usb20_otg: usb@ff300000 { 904 usb20_otg: usb@ff300000 {
929 compatible = "rockchip,px30-us 905 compatible = "rockchip,px30-usb", "rockchip,rk3066-usb",
930 "snps,dwc2"; 906 "snps,dwc2";
931 reg = <0x0 0xff300000 0x0 0x40 907 reg = <0x0 0xff300000 0x0 0x40000>;
932 interrupts = <GIC_SPI 62 IRQ_T 908 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
933 clocks = <&cru HCLK_OTG>; 909 clocks = <&cru HCLK_OTG>;
934 clock-names = "otg"; 910 clock-names = "otg";
935 dr_mode = "otg"; 911 dr_mode = "otg";
936 g-np-tx-fifo-size = <16>; 912 g-np-tx-fifo-size = <16>;
937 g-rx-fifo-size = <280>; 913 g-rx-fifo-size = <280>;
938 g-tx-fifo-size = <256 128 128 914 g-tx-fifo-size = <256 128 128 64 32 16>;
939 phys = <&u2phy_otg>; 915 phys = <&u2phy_otg>;
940 phy-names = "usb2-phy"; 916 phy-names = "usb2-phy";
941 power-domains = <&power PX30_P 917 power-domains = <&power PX30_PD_USB>;
942 status = "disabled"; 918 status = "disabled";
943 }; 919 };
944 920
945 usb_host0_ehci: usb@ff340000 { 921 usb_host0_ehci: usb@ff340000 {
946 compatible = "generic-ehci"; 922 compatible = "generic-ehci";
947 reg = <0x0 0xff340000 0x0 0x10 923 reg = <0x0 0xff340000 0x0 0x10000>;
948 interrupts = <GIC_SPI 60 IRQ_T 924 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
949 clocks = <&cru HCLK_HOST>; 925 clocks = <&cru HCLK_HOST>;
950 phys = <&u2phy_host>; 926 phys = <&u2phy_host>;
951 phy-names = "usb"; 927 phy-names = "usb";
952 power-domains = <&power PX30_P 928 power-domains = <&power PX30_PD_USB>;
953 status = "disabled"; 929 status = "disabled";
954 }; 930 };
955 931
956 usb_host0_ohci: usb@ff350000 { 932 usb_host0_ohci: usb@ff350000 {
957 compatible = "generic-ohci"; 933 compatible = "generic-ohci";
958 reg = <0x0 0xff350000 0x0 0x10 934 reg = <0x0 0xff350000 0x0 0x10000>;
959 interrupts = <GIC_SPI 61 IRQ_T 935 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
960 clocks = <&cru HCLK_HOST>; 936 clocks = <&cru HCLK_HOST>;
961 phys = <&u2phy_host>; 937 phys = <&u2phy_host>;
962 phy-names = "usb"; 938 phy-names = "usb";
963 power-domains = <&power PX30_P 939 power-domains = <&power PX30_PD_USB>;
964 status = "disabled"; 940 status = "disabled";
965 }; 941 };
966 942
967 gmac: ethernet@ff360000 { 943 gmac: ethernet@ff360000 {
968 compatible = "rockchip,px30-gm 944 compatible = "rockchip,px30-gmac";
969 reg = <0x0 0xff360000 0x0 0x10 945 reg = <0x0 0xff360000 0x0 0x10000>;
970 interrupts = <GIC_SPI 43 IRQ_T 946 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
971 interrupt-names = "macirq"; 947 interrupt-names = "macirq";
972 clocks = <&cru SCLK_GMAC>, <&c 948 clocks = <&cru SCLK_GMAC>, <&cru SCLK_GMAC_RX_TX>,
973 <&cru SCLK_GMAC_RX_TX 949 <&cru SCLK_GMAC_RX_TX>, <&cru SCLK_MAC_REF>,
974 <&cru SCLK_MAC_REFOUT 950 <&cru SCLK_MAC_REFOUT>, <&cru ACLK_GMAC>,
975 <&cru PCLK_GMAC>, <&c 951 <&cru PCLK_GMAC>, <&cru SCLK_GMAC_RMII>;
976 clock-names = "stmmaceth", "ma 952 clock-names = "stmmaceth", "mac_clk_rx",
977 "mac_clk_tx", "c 953 "mac_clk_tx", "clk_mac_ref",
978 "clk_mac_refout" 954 "clk_mac_refout", "aclk_mac",
979 "pclk_mac", "clk 955 "pclk_mac", "clk_mac_speed";
980 rockchip,grf = <&grf>; 956 rockchip,grf = <&grf>;
981 phy-mode = "rmii"; 957 phy-mode = "rmii";
982 pinctrl-names = "default"; 958 pinctrl-names = "default";
983 pinctrl-0 = <&rmii_pins &mac_r 959 pinctrl-0 = <&rmii_pins &mac_refclk_12ma>;
984 power-domains = <&power PX30_P 960 power-domains = <&power PX30_PD_GMAC>;
985 resets = <&cru SRST_GMAC_A>; 961 resets = <&cru SRST_GMAC_A>;
986 reset-names = "stmmaceth"; 962 reset-names = "stmmaceth";
987 status = "disabled"; 963 status = "disabled";
988 }; 964 };
989 965
990 sdmmc: mmc@ff370000 { 966 sdmmc: mmc@ff370000 {
991 compatible = "rockchip,px30-dw 967 compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc";
992 reg = <0x0 0xff370000 0x0 0x40 968 reg = <0x0 0xff370000 0x0 0x4000>;
993 interrupts = <GIC_SPI 54 IRQ_T 969 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
994 clocks = <&cru HCLK_SDMMC>, <& 970 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
995 <&cru SCLK_SDMMC_DRV> 971 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
996 clock-names = "biu", "ciu", "c 972 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
997 bus-width = <4>; 973 bus-width = <4>;
998 fifo-depth = <0x100>; 974 fifo-depth = <0x100>;
999 max-frequency = <150000000>; 975 max-frequency = <150000000>;
1000 pinctrl-names = "default"; 976 pinctrl-names = "default";
1001 pinctrl-0 = <&sdmmc_clk &sdmm 977 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_det &sdmmc_bus4>;
1002 power-domains = <&power PX30_ 978 power-domains = <&power PX30_PD_SDCARD>;
1003 status = "disabled"; 979 status = "disabled";
1004 }; 980 };
1005 981
1006 sdio: mmc@ff380000 { 982 sdio: mmc@ff380000 {
1007 compatible = "rockchip,px30-d 983 compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc";
1008 reg = <0x0 0xff380000 0x0 0x4 984 reg = <0x0 0xff380000 0x0 0x4000>;
1009 interrupts = <GIC_SPI 55 IRQ_ 985 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
1010 clocks = <&cru HCLK_SDIO>, <& 986 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
1011 <&cru SCLK_SDIO_DRV> 987 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
1012 clock-names = "biu", "ciu", " 988 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
1013 bus-width = <4>; 989 bus-width = <4>;
1014 fifo-depth = <0x100>; 990 fifo-depth = <0x100>;
1015 max-frequency = <150000000>; 991 max-frequency = <150000000>;
1016 pinctrl-names = "default"; 992 pinctrl-names = "default";
1017 pinctrl-0 = <&sdio_bus4 &sdio 993 pinctrl-0 = <&sdio_bus4 &sdio_cmd &sdio_clk>;
1018 power-domains = <&power PX30_ 994 power-domains = <&power PX30_PD_MMC_NAND>;
1019 status = "disabled"; 995 status = "disabled";
1020 }; 996 };
1021 997
1022 emmc: mmc@ff390000 { 998 emmc: mmc@ff390000 {
1023 compatible = "rockchip,px30-d 999 compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc";
1024 reg = <0x0 0xff390000 0x0 0x4 1000 reg = <0x0 0xff390000 0x0 0x4000>;
1025 interrupts = <GIC_SPI 53 IRQ_ 1001 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
1026 clocks = <&cru HCLK_EMMC>, <& 1002 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
1027 <&cru SCLK_EMMC_DRV> 1003 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
1028 clock-names = "biu", "ciu", " 1004 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
1029 bus-width = <8>; 1005 bus-width = <8>;
1030 fifo-depth = <0x100>; 1006 fifo-depth = <0x100>;
1031 max-frequency = <150000000>; 1007 max-frequency = <150000000>;
1032 pinctrl-names = "default"; 1008 pinctrl-names = "default";
1033 pinctrl-0 = <&emmc_clk &emmc_ 1009 pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
1034 power-domains = <&power PX30_ 1010 power-domains = <&power PX30_PD_MMC_NAND>;
1035 status = "disabled"; 1011 status = "disabled";
1036 }; 1012 };
1037 1013
1038 sfc: spi@ff3a0000 { 1014 sfc: spi@ff3a0000 {
1039 compatible = "rockchip,sfc"; 1015 compatible = "rockchip,sfc";
1040 reg = <0x0 0xff3a0000 0x0 0x4 1016 reg = <0x0 0xff3a0000 0x0 0x4000>;
1041 interrupts = <GIC_SPI 56 IRQ_ 1017 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
1042 clocks = <&cru SCLK_SFC>, <&c 1018 clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>;
1043 clock-names = "clk_sfc", "hcl 1019 clock-names = "clk_sfc", "hclk_sfc";
1044 pinctrl-0 = <&sfc_clk &sfc_cs 1020 pinctrl-0 = <&sfc_clk &sfc_cs0 &sfc_bus4>;
1045 pinctrl-names = "default"; 1021 pinctrl-names = "default";
1046 power-domains = <&power PX30_ 1022 power-domains = <&power PX30_PD_MMC_NAND>;
1047 status = "disabled"; 1023 status = "disabled";
1048 }; 1024 };
1049 1025
1050 nfc: nand-controller@ff3b0000 { 1026 nfc: nand-controller@ff3b0000 {
1051 compatible = "rockchip,px30-n 1027 compatible = "rockchip,px30-nfc";
1052 reg = <0x0 0xff3b0000 0x0 0x4 1028 reg = <0x0 0xff3b0000 0x0 0x4000>;
1053 interrupts = <GIC_SPI 57 IRQ_ 1029 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
1054 clocks = <&cru HCLK_NANDC>, < 1030 clocks = <&cru HCLK_NANDC>, <&cru SCLK_NANDC>;
1055 clock-names = "ahb", "nfc"; 1031 clock-names = "ahb", "nfc";
1056 assigned-clocks = <&cru SCLK_ 1032 assigned-clocks = <&cru SCLK_NANDC>;
1057 assigned-clock-rates = <15000 1033 assigned-clock-rates = <150000000>;
1058 pinctrl-names = "default"; 1034 pinctrl-names = "default";
1059 pinctrl-0 = <&flash_ale &flas 1035 pinctrl-0 = <&flash_ale &flash_bus8 &flash_cle &flash_cs0
1060 &flash_rdn &flas 1036 &flash_rdn &flash_rdy &flash_wrn &flash_dqs>;
1061 power-domains = <&power PX30_ 1037 power-domains = <&power PX30_PD_MMC_NAND>;
1062 status = "disabled"; 1038 status = "disabled";
1063 }; 1039 };
1064 1040
1065 gpu_opp_table: opp-table-1 { 1041 gpu_opp_table: opp-table-1 {
1066 compatible = "operating-point 1042 compatible = "operating-points-v2";
1067 1043
1068 opp-200000000 { 1044 opp-200000000 {
1069 opp-hz = /bits/ 64 <2 1045 opp-hz = /bits/ 64 <200000000>;
1070 opp-microvolt = <9500 1046 opp-microvolt = <950000>;
1071 }; 1047 };
1072 opp-300000000 { 1048 opp-300000000 {
1073 opp-hz = /bits/ 64 <3 1049 opp-hz = /bits/ 64 <300000000>;
1074 opp-microvolt = <9750 1050 opp-microvolt = <975000>;
1075 }; 1051 };
1076 opp-400000000 { 1052 opp-400000000 {
1077 opp-hz = /bits/ 64 <4 1053 opp-hz = /bits/ 64 <400000000>;
1078 opp-microvolt = <1050 1054 opp-microvolt = <1050000>;
1079 }; 1055 };
1080 opp-480000000 { 1056 opp-480000000 {
1081 opp-hz = /bits/ 64 <4 1057 opp-hz = /bits/ 64 <480000000>;
1082 opp-microvolt = <1125 1058 opp-microvolt = <1125000>;
1083 }; 1059 };
1084 }; 1060 };
1085 1061
1086 gpu: gpu@ff400000 { 1062 gpu: gpu@ff400000 {
1087 compatible = "rockchip,px30-m 1063 compatible = "rockchip,px30-mali", "arm,mali-bifrost";
1088 reg = <0x0 0xff400000 0x0 0x4 1064 reg = <0x0 0xff400000 0x0 0x4000>;
1089 interrupts = <GIC_SPI 47 IRQ_ 1065 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
1090 <GIC_SPI 46 IRQ_ 1066 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
1091 <GIC_SPI 45 IRQ_ 1067 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
1092 interrupt-names = "job", "mmu 1068 interrupt-names = "job", "mmu", "gpu";
1093 clocks = <&cru SCLK_GPU>; 1069 clocks = <&cru SCLK_GPU>;
1094 #cooling-cells = <2>; 1070 #cooling-cells = <2>;
1095 power-domains = <&power PX30_ 1071 power-domains = <&power PX30_PD_GPU>;
1096 operating-points-v2 = <&gpu_o 1072 operating-points-v2 = <&gpu_opp_table>;
1097 status = "disabled"; 1073 status = "disabled";
1098 }; 1074 };
1099 1075
1100 vpu: video-codec@ff442000 { 1076 vpu: video-codec@ff442000 {
1101 compatible = "rockchip,px30-v 1077 compatible = "rockchip,px30-vpu";
1102 reg = <0x0 0xff442000 0x0 0x8 1078 reg = <0x0 0xff442000 0x0 0x800>;
1103 interrupts = <GIC_SPI 80 IRQ_ 1079 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
1104 <GIC_SPI 79 IRQ_ 1080 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
1105 interrupt-names = "vepu", "vd 1081 interrupt-names = "vepu", "vdpu";
1106 clocks = <&cru ACLK_VPU>, <&c 1082 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
1107 clock-names = "aclk", "hclk"; 1083 clock-names = "aclk", "hclk";
1108 iommus = <&vpu_mmu>; 1084 iommus = <&vpu_mmu>;
1109 power-domains = <&power PX30_ 1085 power-domains = <&power PX30_PD_VPU>;
1110 }; 1086 };
1111 1087
1112 vpu_mmu: iommu@ff442800 { 1088 vpu_mmu: iommu@ff442800 {
1113 compatible = "rockchip,iommu" 1089 compatible = "rockchip,iommu";
1114 reg = <0x0 0xff442800 0x0 0x1 1090 reg = <0x0 0xff442800 0x0 0x100>;
1115 interrupts = <GIC_SPI 81 IRQ_ 1091 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
1116 clocks = <&cru ACLK_VPU>, <&c 1092 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
1117 clock-names = "aclk", "iface" 1093 clock-names = "aclk", "iface";
1118 #iommu-cells = <0>; 1094 #iommu-cells = <0>;
1119 power-domains = <&power PX30_ 1095 power-domains = <&power PX30_PD_VPU>;
1120 }; 1096 };
1121 1097
1122 dsi: dsi@ff450000 { 1098 dsi: dsi@ff450000 {
1123 compatible = "rockchip,px30-m 1099 compatible = "rockchip,px30-mipi-dsi", "snps,dw-mipi-dsi";
1124 reg = <0x0 0xff450000 0x0 0x1 1100 reg = <0x0 0xff450000 0x0 0x10000>;
1125 interrupts = <GIC_SPI 75 IRQ_ 1101 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
1126 clocks = <&cru PCLK_MIPI_DSI> 1102 clocks = <&cru PCLK_MIPI_DSI>;
1127 clock-names = "pclk"; 1103 clock-names = "pclk";
1128 phys = <&dsi_dphy>; 1104 phys = <&dsi_dphy>;
1129 phy-names = "dphy"; 1105 phy-names = "dphy";
1130 power-domains = <&power PX30_ 1106 power-domains = <&power PX30_PD_VO>;
1131 resets = <&cru SRST_MIPIDSI_H 1107 resets = <&cru SRST_MIPIDSI_HOST_P>;
1132 reset-names = "apb"; 1108 reset-names = "apb";
1133 rockchip,grf = <&grf>; 1109 rockchip,grf = <&grf>;
1134 #address-cells = <1>; 1110 #address-cells = <1>;
1135 #size-cells = <0>; 1111 #size-cells = <0>;
1136 status = "disabled"; 1112 status = "disabled";
1137 1113
1138 ports { 1114 ports {
1139 #address-cells = <1>; 1115 #address-cells = <1>;
1140 #size-cells = <0>; 1116 #size-cells = <0>;
1141 1117
1142 dsi_in: port@0 { !! 1118 port@0 {
1143 reg = <0>; 1119 reg = <0>;
1144 #address-cell 1120 #address-cells = <1>;
1145 #size-cells = 1121 #size-cells = <0>;
1146 1122
1147 dsi_in_vopb: 1123 dsi_in_vopb: endpoint@0 {
1148 reg = 1124 reg = <0>;
1149 remot 1125 remote-endpoint = <&vopb_out_dsi>;
1150 }; 1126 };
1151 1127
1152 dsi_in_vopl: 1128 dsi_in_vopl: endpoint@1 {
1153 reg = 1129 reg = <1>;
1154 remot 1130 remote-endpoint = <&vopl_out_dsi>;
1155 }; 1131 };
1156 }; <<
1157 <<
1158 dsi_out: port@1 { <<
1159 reg = <1>; <<
1160 }; 1132 };
1161 }; 1133 };
1162 }; 1134 };
1163 1135
1164 vopb: vop@ff460000 { 1136 vopb: vop@ff460000 {
1165 compatible = "rockchip,px30-v 1137 compatible = "rockchip,px30-vop-big";
1166 reg = <0x0 0xff460000 0x0 0xe 1138 reg = <0x0 0xff460000 0x0 0xefc>;
1167 interrupts = <GIC_SPI 77 IRQ_ 1139 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
1168 clocks = <&cru ACLK_VOPB>, <& 1140 clocks = <&cru ACLK_VOPB>, <&cru DCLK_VOPB>,
1169 <&cru HCLK_VOPB>; 1141 <&cru HCLK_VOPB>;
1170 clock-names = "aclk_vop", "dc 1142 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1171 resets = <&cru SRST_VOPB_A>, 1143 resets = <&cru SRST_VOPB_A>, <&cru SRST_VOPB_H>, <&cru SRST_VOPB>;
1172 reset-names = "axi", "ahb", " 1144 reset-names = "axi", "ahb", "dclk";
1173 iommus = <&vopb_mmu>; 1145 iommus = <&vopb_mmu>;
1174 power-domains = <&power PX30_ 1146 power-domains = <&power PX30_PD_VO>;
1175 status = "disabled"; 1147 status = "disabled";
1176 1148
1177 vopb_out: port { 1149 vopb_out: port {
1178 #address-cells = <1>; 1150 #address-cells = <1>;
1179 #size-cells = <0>; 1151 #size-cells = <0>;
1180 1152
1181 vopb_out_dsi: endpoin 1153 vopb_out_dsi: endpoint@0 {
1182 reg = <0>; 1154 reg = <0>;
1183 remote-endpoi 1155 remote-endpoint = <&dsi_in_vopb>;
1184 }; 1156 };
1185 1157
1186 vopb_out_lvds: endpoi 1158 vopb_out_lvds: endpoint@1 {
1187 reg = <1>; 1159 reg = <1>;
1188 remote-endpoi 1160 remote-endpoint = <&lvds_vopb_in>;
1189 }; 1161 };
1190 }; 1162 };
1191 }; 1163 };
1192 1164
1193 vopb_mmu: iommu@ff460f00 { 1165 vopb_mmu: iommu@ff460f00 {
1194 compatible = "rockchip,iommu" 1166 compatible = "rockchip,iommu";
1195 reg = <0x0 0xff460f00 0x0 0x1 1167 reg = <0x0 0xff460f00 0x0 0x100>;
1196 interrupts = <GIC_SPI 77 IRQ_ 1168 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
1197 clocks = <&cru ACLK_VOPB>, <& 1169 clocks = <&cru ACLK_VOPB>, <&cru HCLK_VOPB>;
1198 clock-names = "aclk", "iface" 1170 clock-names = "aclk", "iface";
1199 power-domains = <&power PX30_ 1171 power-domains = <&power PX30_PD_VO>;
1200 #iommu-cells = <0>; 1172 #iommu-cells = <0>;
1201 status = "disabled"; 1173 status = "disabled";
1202 }; 1174 };
1203 1175
1204 vopl: vop@ff470000 { 1176 vopl: vop@ff470000 {
1205 compatible = "rockchip,px30-v 1177 compatible = "rockchip,px30-vop-lit";
1206 reg = <0x0 0xff470000 0x0 0xe 1178 reg = <0x0 0xff470000 0x0 0xefc>;
1207 interrupts = <GIC_SPI 78 IRQ_ 1179 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
1208 clocks = <&cru ACLK_VOPL>, <& 1180 clocks = <&cru ACLK_VOPL>, <&cru DCLK_VOPL>,
1209 <&cru HCLK_VOPL>; 1181 <&cru HCLK_VOPL>;
1210 clock-names = "aclk_vop", "dc 1182 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1211 resets = <&cru SRST_VOPL_A>, 1183 resets = <&cru SRST_VOPL_A>, <&cru SRST_VOPL_H>, <&cru SRST_VOPL>;
1212 reset-names = "axi", "ahb", " 1184 reset-names = "axi", "ahb", "dclk";
1213 iommus = <&vopl_mmu>; 1185 iommus = <&vopl_mmu>;
1214 power-domains = <&power PX30_ 1186 power-domains = <&power PX30_PD_VO>;
1215 status = "disabled"; 1187 status = "disabled";
1216 1188
1217 vopl_out: port { 1189 vopl_out: port {
1218 #address-cells = <1>; 1190 #address-cells = <1>;
1219 #size-cells = <0>; 1191 #size-cells = <0>;
1220 1192
1221 vopl_out_dsi: endpoin 1193 vopl_out_dsi: endpoint@0 {
1222 reg = <0>; 1194 reg = <0>;
1223 remote-endpoi 1195 remote-endpoint = <&dsi_in_vopl>;
1224 }; 1196 };
1225 1197
1226 vopl_out_lvds: endpoi 1198 vopl_out_lvds: endpoint@1 {
1227 reg = <1>; 1199 reg = <1>;
1228 remote-endpoi 1200 remote-endpoint = <&lvds_vopl_in>;
1229 }; 1201 };
1230 }; 1202 };
1231 }; 1203 };
1232 1204
1233 vopl_mmu: iommu@ff470f00 { 1205 vopl_mmu: iommu@ff470f00 {
1234 compatible = "rockchip,iommu" 1206 compatible = "rockchip,iommu";
1235 reg = <0x0 0xff470f00 0x0 0x1 1207 reg = <0x0 0xff470f00 0x0 0x100>;
1236 interrupts = <GIC_SPI 78 IRQ_ 1208 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
1237 clocks = <&cru ACLK_VOPL>, <& 1209 clocks = <&cru ACLK_VOPL>, <&cru HCLK_VOPL>;
1238 clock-names = "aclk", "iface" 1210 clock-names = "aclk", "iface";
1239 power-domains = <&power PX30_ 1211 power-domains = <&power PX30_PD_VO>;
1240 #iommu-cells = <0>; 1212 #iommu-cells = <0>;
1241 status = "disabled"; 1213 status = "disabled";
1242 }; 1214 };
1243 1215
1244 isp: isp@ff4a0000 { 1216 isp: isp@ff4a0000 {
1245 compatible = "rockchip,px30-c 1217 compatible = "rockchip,px30-cif-isp"; /*rk3326-rkisp1*/
1246 reg = <0x0 0xff4a0000 0x0 0x8 1218 reg = <0x0 0xff4a0000 0x0 0x8000>;
1247 interrupts = <GIC_SPI 70 IRQ_ 1219 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
1248 <GIC_SPI 73 IRQ_ 1220 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
1249 <GIC_SPI 74 IRQ_ 1221 <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
1250 interrupt-names = "isp", "mi" 1222 interrupt-names = "isp", "mi", "mipi";
1251 clocks = <&cru SCLK_ISP>, 1223 clocks = <&cru SCLK_ISP>,
1252 <&cru ACLK_ISP>, 1224 <&cru ACLK_ISP>,
1253 <&cru HCLK_ISP>, 1225 <&cru HCLK_ISP>,
1254 <&cru PCLK_ISP>; 1226 <&cru PCLK_ISP>;
1255 clock-names = "isp", "aclk", 1227 clock-names = "isp", "aclk", "hclk", "pclk";
1256 iommus = <&isp_mmu>; 1228 iommus = <&isp_mmu>;
1257 phys = <&csi_dphy>; 1229 phys = <&csi_dphy>;
1258 phy-names = "dphy"; 1230 phy-names = "dphy";
1259 power-domains = <&power PX30_ 1231 power-domains = <&power PX30_PD_VI>;
1260 status = "disabled"; 1232 status = "disabled";
1261 1233
1262 ports { 1234 ports {
1263 #address-cells = <1>; 1235 #address-cells = <1>;
1264 #size-cells = <0>; 1236 #size-cells = <0>;
1265 1237
1266 port@0 { 1238 port@0 {
1267 reg = <0>; 1239 reg = <0>;
1268 #address-cell 1240 #address-cells = <1>;
1269 #size-cells = 1241 #size-cells = <0>;
1270 }; 1242 };
1271 }; 1243 };
1272 }; 1244 };
1273 1245
1274 isp_mmu: iommu@ff4a8000 { 1246 isp_mmu: iommu@ff4a8000 {
1275 compatible = "rockchip,iommu" 1247 compatible = "rockchip,iommu";
1276 reg = <0x0 0xff4a8000 0x0 0x1 1248 reg = <0x0 0xff4a8000 0x0 0x100>;
1277 interrupts = <GIC_SPI 70 IRQ_ 1249 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
1278 clocks = <&cru ACLK_ISP>, <&c 1250 clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>;
1279 clock-names = "aclk", "iface" 1251 clock-names = "aclk", "iface";
1280 power-domains = <&power PX30_ 1252 power-domains = <&power PX30_PD_VI>;
1281 rockchip,disable-mmu-reset; 1253 rockchip,disable-mmu-reset;
1282 #iommu-cells = <0>; 1254 #iommu-cells = <0>;
1283 }; 1255 };
1284 1256
1285 qos_gmac: qos@ff518000 { 1257 qos_gmac: qos@ff518000 {
1286 compatible = "rockchip,px30-q 1258 compatible = "rockchip,px30-qos", "syscon";
1287 reg = <0x0 0xff518000 0x0 0x2 1259 reg = <0x0 0xff518000 0x0 0x20>;
1288 }; 1260 };
1289 1261
1290 qos_gpu: qos@ff520000 { 1262 qos_gpu: qos@ff520000 {
1291 compatible = "rockchip,px30-q 1263 compatible = "rockchip,px30-qos", "syscon";
1292 reg = <0x0 0xff520000 0x0 0x2 1264 reg = <0x0 0xff520000 0x0 0x20>;
1293 }; 1265 };
1294 1266
1295 qos_sdmmc: qos@ff52c000 { 1267 qos_sdmmc: qos@ff52c000 {
1296 compatible = "rockchip,px30-q 1268 compatible = "rockchip,px30-qos", "syscon";
1297 reg = <0x0 0xff52c000 0x0 0x2 1269 reg = <0x0 0xff52c000 0x0 0x20>;
1298 }; 1270 };
1299 1271
1300 qos_emmc: qos@ff538000 { 1272 qos_emmc: qos@ff538000 {
1301 compatible = "rockchip,px30-q 1273 compatible = "rockchip,px30-qos", "syscon";
1302 reg = <0x0 0xff538000 0x0 0x2 1274 reg = <0x0 0xff538000 0x0 0x20>;
1303 }; 1275 };
1304 1276
1305 qos_nand: qos@ff538080 { 1277 qos_nand: qos@ff538080 {
1306 compatible = "rockchip,px30-q 1278 compatible = "rockchip,px30-qos", "syscon";
1307 reg = <0x0 0xff538080 0x0 0x2 1279 reg = <0x0 0xff538080 0x0 0x20>;
1308 }; 1280 };
1309 1281
1310 qos_sdio: qos@ff538100 { 1282 qos_sdio: qos@ff538100 {
1311 compatible = "rockchip,px30-q 1283 compatible = "rockchip,px30-qos", "syscon";
1312 reg = <0x0 0xff538100 0x0 0x2 1284 reg = <0x0 0xff538100 0x0 0x20>;
1313 }; 1285 };
1314 1286
1315 qos_sfc: qos@ff538180 { 1287 qos_sfc: qos@ff538180 {
1316 compatible = "rockchip,px30-q 1288 compatible = "rockchip,px30-qos", "syscon";
1317 reg = <0x0 0xff538180 0x0 0x2 1289 reg = <0x0 0xff538180 0x0 0x20>;
1318 }; 1290 };
1319 1291
1320 qos_usb_host: qos@ff540000 { 1292 qos_usb_host: qos@ff540000 {
1321 compatible = "rockchip,px30-q 1293 compatible = "rockchip,px30-qos", "syscon";
1322 reg = <0x0 0xff540000 0x0 0x2 1294 reg = <0x0 0xff540000 0x0 0x20>;
1323 }; 1295 };
1324 1296
1325 qos_usb_otg: qos@ff540080 { 1297 qos_usb_otg: qos@ff540080 {
1326 compatible = "rockchip,px30-q 1298 compatible = "rockchip,px30-qos", "syscon";
1327 reg = <0x0 0xff540080 0x0 0x2 1299 reg = <0x0 0xff540080 0x0 0x20>;
1328 }; 1300 };
1329 1301
1330 qos_isp_128: qos@ff548000 { 1302 qos_isp_128: qos@ff548000 {
1331 compatible = "rockchip,px30-q 1303 compatible = "rockchip,px30-qos", "syscon";
1332 reg = <0x0 0xff548000 0x0 0x2 1304 reg = <0x0 0xff548000 0x0 0x20>;
1333 }; 1305 };
1334 1306
1335 qos_isp_rd: qos@ff548080 { 1307 qos_isp_rd: qos@ff548080 {
1336 compatible = "rockchip,px30-q 1308 compatible = "rockchip,px30-qos", "syscon";
1337 reg = <0x0 0xff548080 0x0 0x2 1309 reg = <0x0 0xff548080 0x0 0x20>;
1338 }; 1310 };
1339 1311
1340 qos_isp_wr: qos@ff548100 { 1312 qos_isp_wr: qos@ff548100 {
1341 compatible = "rockchip,px30-q 1313 compatible = "rockchip,px30-qos", "syscon";
1342 reg = <0x0 0xff548100 0x0 0x2 1314 reg = <0x0 0xff548100 0x0 0x20>;
1343 }; 1315 };
1344 1316
1345 qos_isp_m1: qos@ff548180 { 1317 qos_isp_m1: qos@ff548180 {
1346 compatible = "rockchip,px30-q 1318 compatible = "rockchip,px30-qos", "syscon";
1347 reg = <0x0 0xff548180 0x0 0x2 1319 reg = <0x0 0xff548180 0x0 0x20>;
1348 }; 1320 };
1349 1321
1350 qos_vip: qos@ff548200 { 1322 qos_vip: qos@ff548200 {
1351 compatible = "rockchip,px30-q 1323 compatible = "rockchip,px30-qos", "syscon";
1352 reg = <0x0 0xff548200 0x0 0x2 1324 reg = <0x0 0xff548200 0x0 0x20>;
1353 }; 1325 };
1354 1326
1355 qos_rga_rd: qos@ff550000 { 1327 qos_rga_rd: qos@ff550000 {
1356 compatible = "rockchip,px30-q 1328 compatible = "rockchip,px30-qos", "syscon";
1357 reg = <0x0 0xff550000 0x0 0x2 1329 reg = <0x0 0xff550000 0x0 0x20>;
1358 }; 1330 };
1359 1331
1360 qos_rga_wr: qos@ff550080 { 1332 qos_rga_wr: qos@ff550080 {
1361 compatible = "rockchip,px30-q 1333 compatible = "rockchip,px30-qos", "syscon";
1362 reg = <0x0 0xff550080 0x0 0x2 1334 reg = <0x0 0xff550080 0x0 0x20>;
1363 }; 1335 };
1364 1336
1365 qos_vop_m0: qos@ff550100 { 1337 qos_vop_m0: qos@ff550100 {
1366 compatible = "rockchip,px30-q 1338 compatible = "rockchip,px30-qos", "syscon";
1367 reg = <0x0 0xff550100 0x0 0x2 1339 reg = <0x0 0xff550100 0x0 0x20>;
1368 }; 1340 };
1369 1341
1370 qos_vop_m1: qos@ff550180 { 1342 qos_vop_m1: qos@ff550180 {
1371 compatible = "rockchip,px30-q 1343 compatible = "rockchip,px30-qos", "syscon";
1372 reg = <0x0 0xff550180 0x0 0x2 1344 reg = <0x0 0xff550180 0x0 0x20>;
1373 }; 1345 };
1374 1346
1375 qos_vpu: qos@ff558000 { 1347 qos_vpu: qos@ff558000 {
1376 compatible = "rockchip,px30-q 1348 compatible = "rockchip,px30-qos", "syscon";
1377 reg = <0x0 0xff558000 0x0 0x2 1349 reg = <0x0 0xff558000 0x0 0x20>;
1378 }; 1350 };
1379 1351
1380 qos_vpu_r128: qos@ff558080 { 1352 qos_vpu_r128: qos@ff558080 {
1381 compatible = "rockchip,px30-q 1353 compatible = "rockchip,px30-qos", "syscon";
1382 reg = <0x0 0xff558080 0x0 0x2 1354 reg = <0x0 0xff558080 0x0 0x20>;
1383 }; 1355 };
1384 1356
1385 pinctrl: pinctrl { 1357 pinctrl: pinctrl {
1386 compatible = "rockchip,px30-p 1358 compatible = "rockchip,px30-pinctrl";
1387 rockchip,grf = <&grf>; 1359 rockchip,grf = <&grf>;
1388 rockchip,pmu = <&pmugrf>; 1360 rockchip,pmu = <&pmugrf>;
1389 #address-cells = <2>; 1361 #address-cells = <2>;
1390 #size-cells = <2>; 1362 #size-cells = <2>;
1391 ranges; 1363 ranges;
1392 1364
1393 gpio0: gpio@ff040000 { 1365 gpio0: gpio@ff040000 {
1394 compatible = "rockchi 1366 compatible = "rockchip,gpio-bank";
1395 reg = <0x0 0xff040000 1367 reg = <0x0 0xff040000 0x0 0x100>;
1396 interrupts = <GIC_SPI 1368 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
1397 clocks = <&pmucru PCL 1369 clocks = <&pmucru PCLK_GPIO0_PMU>;
1398 gpio-controller; 1370 gpio-controller;
1399 #gpio-cells = <2>; 1371 #gpio-cells = <2>;
1400 1372
1401 interrupt-controller; 1373 interrupt-controller;
1402 #interrupt-cells = <2 1374 #interrupt-cells = <2>;
1403 }; 1375 };
1404 1376
1405 gpio1: gpio@ff250000 { 1377 gpio1: gpio@ff250000 {
1406 compatible = "rockchi 1378 compatible = "rockchip,gpio-bank";
1407 reg = <0x0 0xff250000 1379 reg = <0x0 0xff250000 0x0 0x100>;
1408 interrupts = <GIC_SPI 1380 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
1409 clocks = <&cru PCLK_G 1381 clocks = <&cru PCLK_GPIO1>;
1410 gpio-controller; 1382 gpio-controller;
1411 #gpio-cells = <2>; 1383 #gpio-cells = <2>;
1412 1384
1413 interrupt-controller; 1385 interrupt-controller;
1414 #interrupt-cells = <2 1386 #interrupt-cells = <2>;
1415 }; 1387 };
1416 1388
1417 gpio2: gpio@ff260000 { 1389 gpio2: gpio@ff260000 {
1418 compatible = "rockchi 1390 compatible = "rockchip,gpio-bank";
1419 reg = <0x0 0xff260000 1391 reg = <0x0 0xff260000 0x0 0x100>;
1420 interrupts = <GIC_SPI 1392 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
1421 clocks = <&cru PCLK_G 1393 clocks = <&cru PCLK_GPIO2>;
1422 gpio-controller; 1394 gpio-controller;
1423 #gpio-cells = <2>; 1395 #gpio-cells = <2>;
1424 1396
1425 interrupt-controller; 1397 interrupt-controller;
1426 #interrupt-cells = <2 1398 #interrupt-cells = <2>;
1427 }; 1399 };
1428 1400
1429 gpio3: gpio@ff270000 { 1401 gpio3: gpio@ff270000 {
1430 compatible = "rockchi 1402 compatible = "rockchip,gpio-bank";
1431 reg = <0x0 0xff270000 1403 reg = <0x0 0xff270000 0x0 0x100>;
1432 interrupts = <GIC_SPI 1404 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
1433 clocks = <&cru PCLK_G 1405 clocks = <&cru PCLK_GPIO3>;
1434 gpio-controller; 1406 gpio-controller;
1435 #gpio-cells = <2>; 1407 #gpio-cells = <2>;
1436 1408
1437 interrupt-controller; 1409 interrupt-controller;
1438 #interrupt-cells = <2 1410 #interrupt-cells = <2>;
1439 }; 1411 };
1440 1412
1441 pcfg_pull_up: pcfg-pull-up { 1413 pcfg_pull_up: pcfg-pull-up {
1442 bias-pull-up; 1414 bias-pull-up;
1443 }; 1415 };
1444 1416
1445 pcfg_pull_down: pcfg-pull-dow 1417 pcfg_pull_down: pcfg-pull-down {
1446 bias-pull-down; 1418 bias-pull-down;
1447 }; 1419 };
1448 1420
1449 pcfg_pull_none: pcfg-pull-non 1421 pcfg_pull_none: pcfg-pull-none {
1450 bias-disable; 1422 bias-disable;
1451 }; 1423 };
1452 1424
1453 pcfg_pull_none_2ma: pcfg-pull 1425 pcfg_pull_none_2ma: pcfg-pull-none-2ma {
1454 bias-disable; 1426 bias-disable;
1455 drive-strength = <2>; 1427 drive-strength = <2>;
1456 }; 1428 };
1457 1429
1458 pcfg_pull_up_2ma: pcfg-pull-u 1430 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
1459 bias-pull-up; 1431 bias-pull-up;
1460 drive-strength = <2>; 1432 drive-strength = <2>;
1461 }; 1433 };
1462 1434
1463 pcfg_pull_up_4ma: pcfg-pull-u 1435 pcfg_pull_up_4ma: pcfg-pull-up-4ma {
1464 bias-pull-up; 1436 bias-pull-up;
1465 drive-strength = <4>; 1437 drive-strength = <4>;
1466 }; 1438 };
1467 1439
1468 pcfg_pull_none_4ma: pcfg-pull 1440 pcfg_pull_none_4ma: pcfg-pull-none-4ma {
1469 bias-disable; 1441 bias-disable;
1470 drive-strength = <4>; 1442 drive-strength = <4>;
1471 }; 1443 };
1472 1444
1473 pcfg_pull_down_4ma: pcfg-pull 1445 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
1474 bias-pull-down; 1446 bias-pull-down;
1475 drive-strength = <4>; 1447 drive-strength = <4>;
1476 }; 1448 };
1477 1449
1478 pcfg_pull_none_8ma: pcfg-pull 1450 pcfg_pull_none_8ma: pcfg-pull-none-8ma {
1479 bias-disable; 1451 bias-disable;
1480 drive-strength = <8>; 1452 drive-strength = <8>;
1481 }; 1453 };
1482 1454
1483 pcfg_pull_up_8ma: pcfg-pull-u 1455 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
1484 bias-pull-up; 1456 bias-pull-up;
1485 drive-strength = <8>; 1457 drive-strength = <8>;
1486 }; 1458 };
1487 1459
1488 pcfg_pull_none_12ma: pcfg-pul 1460 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1489 bias-disable; 1461 bias-disable;
1490 drive-strength = <12> 1462 drive-strength = <12>;
1491 }; 1463 };
1492 1464
1493 pcfg_pull_up_12ma: pcfg-pull- 1465 pcfg_pull_up_12ma: pcfg-pull-up-12ma {
1494 bias-pull-up; 1466 bias-pull-up;
1495 drive-strength = <12> 1467 drive-strength = <12>;
1496 }; 1468 };
1497 1469
1498 pcfg_pull_none_smt: pcfg-pull 1470 pcfg_pull_none_smt: pcfg-pull-none-smt {
1499 bias-disable; 1471 bias-disable;
1500 input-schmitt-enable; 1472 input-schmitt-enable;
1501 }; 1473 };
1502 1474
1503 pcfg_output_high: pcfg-output 1475 pcfg_output_high: pcfg-output-high {
1504 output-high; 1476 output-high;
1505 }; 1477 };
1506 1478
1507 pcfg_output_low: pcfg-output- 1479 pcfg_output_low: pcfg-output-low {
1508 output-low; 1480 output-low;
1509 }; 1481 };
1510 1482
1511 pcfg_input_high: pcfg-input-h 1483 pcfg_input_high: pcfg-input-high {
1512 bias-pull-up; 1484 bias-pull-up;
1513 input-enable; 1485 input-enable;
1514 }; 1486 };
1515 1487
1516 pcfg_input: pcfg-input { 1488 pcfg_input: pcfg-input {
1517 input-enable; 1489 input-enable;
1518 }; 1490 };
1519 1491
1520 i2c0 { 1492 i2c0 {
1521 i2c0_xfer: i2c0-xfer 1493 i2c0_xfer: i2c0-xfer {
1522 rockchip,pins 1494 rockchip,pins =
1523 <0 RK 1495 <0 RK_PB0 1 &pcfg_pull_none_smt>,
1524 <0 RK 1496 <0 RK_PB1 1 &pcfg_pull_none_smt>;
1525 }; 1497 };
1526 }; 1498 };
1527 1499
1528 i2c1 { 1500 i2c1 {
1529 i2c1_xfer: i2c1-xfer 1501 i2c1_xfer: i2c1-xfer {
1530 rockchip,pins 1502 rockchip,pins =
1531 <0 RK 1503 <0 RK_PC2 1 &pcfg_pull_none_smt>,
1532 <0 RK 1504 <0 RK_PC3 1 &pcfg_pull_none_smt>;
1533 }; 1505 };
1534 }; 1506 };
1535 1507
1536 i2c2 { 1508 i2c2 {
1537 i2c2_xfer: i2c2-xfer 1509 i2c2_xfer: i2c2-xfer {
1538 rockchip,pins 1510 rockchip,pins =
1539 <2 RK 1511 <2 RK_PB7 2 &pcfg_pull_none_smt>,
1540 <2 RK 1512 <2 RK_PC0 2 &pcfg_pull_none_smt>;
1541 }; 1513 };
1542 }; 1514 };
1543 1515
1544 i2c3 { 1516 i2c3 {
1545 i2c3_xfer: i2c3-xfer 1517 i2c3_xfer: i2c3-xfer {
1546 rockchip,pins 1518 rockchip,pins =
1547 <1 RK 1519 <1 RK_PB4 4 &pcfg_pull_none_smt>,
1548 <1 RK 1520 <1 RK_PB5 4 &pcfg_pull_none_smt>;
1549 }; 1521 };
1550 }; 1522 };
1551 1523
1552 tsadc { 1524 tsadc {
1553 tsadc_otp_pin: tsadc- 1525 tsadc_otp_pin: tsadc-otp-pin {
1554 rockchip,pins 1526 rockchip,pins =
1555 <0 RK 1527 <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
1556 }; 1528 };
1557 1529
1558 tsadc_otp_out: tsadc- 1530 tsadc_otp_out: tsadc-otp-out {
1559 rockchip,pins 1531 rockchip,pins =
1560 <0 RK 1532 <0 RK_PA6 1 &pcfg_pull_none>;
1561 }; 1533 };
1562 }; 1534 };
1563 1535
1564 uart0 { 1536 uart0 {
1565 uart0_xfer: uart0-xfe 1537 uart0_xfer: uart0-xfer {
1566 rockchip,pins 1538 rockchip,pins =
1567 <0 RK 1539 <0 RK_PB2 1 &pcfg_pull_up>,
1568 <0 RK 1540 <0 RK_PB3 1 &pcfg_pull_up>;
1569 }; 1541 };
1570 1542
1571 uart0_cts: uart0-cts 1543 uart0_cts: uart0-cts {
1572 rockchip,pins 1544 rockchip,pins =
1573 <0 RK 1545 <0 RK_PB4 1 &pcfg_pull_none>;
1574 }; 1546 };
1575 1547
1576 uart0_rts: uart0-rts 1548 uart0_rts: uart0-rts {
1577 rockchip,pins 1549 rockchip,pins =
1578 <0 RK 1550 <0 RK_PB5 1 &pcfg_pull_none>;
1579 }; 1551 };
1580 }; 1552 };
1581 1553
1582 uart1 { 1554 uart1 {
1583 uart1_xfer: uart1-xfe 1555 uart1_xfer: uart1-xfer {
1584 rockchip,pins 1556 rockchip,pins =
1585 <1 RK 1557 <1 RK_PC1 1 &pcfg_pull_up>,
1586 <1 RK 1558 <1 RK_PC0 1 &pcfg_pull_up>;
1587 }; 1559 };
1588 1560
1589 uart1_cts: uart1-cts 1561 uart1_cts: uart1-cts {
1590 rockchip,pins 1562 rockchip,pins =
1591 <1 RK 1563 <1 RK_PC2 1 &pcfg_pull_none>;
1592 }; 1564 };
1593 1565
1594 uart1_rts: uart1-rts 1566 uart1_rts: uart1-rts {
1595 rockchip,pins 1567 rockchip,pins =
1596 <1 RK 1568 <1 RK_PC3 1 &pcfg_pull_none>;
1597 }; 1569 };
1598 }; 1570 };
1599 1571
1600 uart2-m0 { 1572 uart2-m0 {
1601 uart2m0_xfer: uart2m0 1573 uart2m0_xfer: uart2m0-xfer {
1602 rockchip,pins 1574 rockchip,pins =
1603 <1 RK 1575 <1 RK_PD2 2 &pcfg_pull_up>,
1604 <1 RK 1576 <1 RK_PD3 2 &pcfg_pull_up>;
1605 }; 1577 };
1606 }; 1578 };
1607 1579
1608 uart2-m1 { 1580 uart2-m1 {
1609 uart2m1_xfer: uart2m1 1581 uart2m1_xfer: uart2m1-xfer {
1610 rockchip,pins 1582 rockchip,pins =
1611 <2 RK 1583 <2 RK_PB4 2 &pcfg_pull_up>,
1612 <2 RK 1584 <2 RK_PB6 2 &pcfg_pull_up>;
1613 }; 1585 };
1614 }; 1586 };
1615 1587
1616 uart3-m0 { 1588 uart3-m0 {
1617 uart3m0_xfer: uart3m0 1589 uart3m0_xfer: uart3m0-xfer {
1618 rockchip,pins 1590 rockchip,pins =
1619 <0 RK 1591 <0 RK_PC0 2 &pcfg_pull_up>,
1620 <0 RK 1592 <0 RK_PC1 2 &pcfg_pull_up>;
1621 }; 1593 };
1622 1594
1623 uart3m0_cts: uart3m0- 1595 uart3m0_cts: uart3m0-cts {
1624 rockchip,pins 1596 rockchip,pins =
1625 <0 RK 1597 <0 RK_PC2 2 &pcfg_pull_none>;
1626 }; 1598 };
1627 1599
1628 uart3m0_rts: uart3m0- 1600 uart3m0_rts: uart3m0-rts {
1629 rockchip,pins 1601 rockchip,pins =
1630 <0 RK 1602 <0 RK_PC3 2 &pcfg_pull_none>;
1631 }; 1603 };
1632 }; 1604 };
1633 1605
1634 uart3-m1 { 1606 uart3-m1 {
1635 uart3m1_xfer: uart3m1 1607 uart3m1_xfer: uart3m1-xfer {
1636 rockchip,pins 1608 rockchip,pins =
1637 <1 RK 1609 <1 RK_PB6 2 &pcfg_pull_up>,
1638 <1 RK 1610 <1 RK_PB7 2 &pcfg_pull_up>;
1639 }; 1611 };
1640 1612
1641 uart3m1_cts: uart3m1- 1613 uart3m1_cts: uart3m1-cts {
1642 rockchip,pins 1614 rockchip,pins =
1643 <1 RK 1615 <1 RK_PB4 2 &pcfg_pull_none>;
1644 }; 1616 };
1645 1617
1646 uart3m1_rts: uart3m1- 1618 uart3m1_rts: uart3m1-rts {
1647 rockchip,pins 1619 rockchip,pins =
1648 <1 RK 1620 <1 RK_PB5 2 &pcfg_pull_none>;
1649 }; 1621 };
1650 }; 1622 };
1651 1623
1652 uart4 { 1624 uart4 {
1653 uart4_xfer: uart4-xfe 1625 uart4_xfer: uart4-xfer {
1654 rockchip,pins 1626 rockchip,pins =
1655 <1 RK 1627 <1 RK_PD4 2 &pcfg_pull_up>,
1656 <1 RK 1628 <1 RK_PD5 2 &pcfg_pull_up>;
1657 }; 1629 };
1658 1630
1659 uart4_cts: uart4-cts 1631 uart4_cts: uart4-cts {
1660 rockchip,pins 1632 rockchip,pins =
1661 <1 RK 1633 <1 RK_PD6 2 &pcfg_pull_none>;
1662 }; 1634 };
1663 1635
1664 uart4_rts: uart4-rts 1636 uart4_rts: uart4-rts {
1665 rockchip,pins 1637 rockchip,pins =
1666 <1 RK 1638 <1 RK_PD7 2 &pcfg_pull_none>;
1667 }; 1639 };
1668 }; 1640 };
1669 1641
1670 uart5 { 1642 uart5 {
1671 uart5_xfer: uart5-xfe 1643 uart5_xfer: uart5-xfer {
1672 rockchip,pins 1644 rockchip,pins =
1673 <3 RK 1645 <3 RK_PA2 4 &pcfg_pull_up>,
1674 <3 RK 1646 <3 RK_PA1 4 &pcfg_pull_up>;
1675 }; 1647 };
1676 1648
1677 uart5_cts: uart5-cts 1649 uart5_cts: uart5-cts {
1678 rockchip,pins 1650 rockchip,pins =
1679 <3 RK 1651 <3 RK_PA3 4 &pcfg_pull_none>;
1680 }; 1652 };
1681 1653
1682 uart5_rts: uart5-rts 1654 uart5_rts: uart5-rts {
1683 rockchip,pins 1655 rockchip,pins =
1684 <3 RK 1656 <3 RK_PA5 4 &pcfg_pull_none>;
1685 }; 1657 };
1686 }; 1658 };
1687 1659
1688 spi0 { 1660 spi0 {
1689 spi0_clk: spi0-clk { 1661 spi0_clk: spi0-clk {
1690 rockchip,pins 1662 rockchip,pins =
1691 <1 RK 1663 <1 RK_PB7 3 &pcfg_pull_up_4ma>;
1692 }; 1664 };
1693 1665
1694 spi0_csn: spi0-csn { 1666 spi0_csn: spi0-csn {
1695 rockchip,pins 1667 rockchip,pins =
1696 <1 RK 1668 <1 RK_PB6 3 &pcfg_pull_up_4ma>;
1697 }; 1669 };
1698 1670
1699 spi0_miso: spi0-miso 1671 spi0_miso: spi0-miso {
1700 rockchip,pins 1672 rockchip,pins =
1701 <1 RK 1673 <1 RK_PB5 3 &pcfg_pull_up_4ma>;
1702 }; 1674 };
1703 1675
1704 spi0_mosi: spi0-mosi 1676 spi0_mosi: spi0-mosi {
1705 rockchip,pins 1677 rockchip,pins =
1706 <1 RK 1678 <1 RK_PB4 3 &pcfg_pull_up_4ma>;
1707 }; 1679 };
1708 1680
1709 spi0_clk_hs: spi0-clk 1681 spi0_clk_hs: spi0-clk-hs {
1710 rockchip,pins 1682 rockchip,pins =
1711 <1 RK 1683 <1 RK_PB7 3 &pcfg_pull_up_8ma>;
1712 }; 1684 };
1713 1685
1714 spi0_miso_hs: spi0-mi 1686 spi0_miso_hs: spi0-miso-hs {
1715 rockchip,pins 1687 rockchip,pins =
1716 <1 RK 1688 <1 RK_PB5 3 &pcfg_pull_up_8ma>;
1717 }; 1689 };
1718 1690
1719 spi0_mosi_hs: spi0-mo 1691 spi0_mosi_hs: spi0-mosi-hs {
1720 rockchip,pins 1692 rockchip,pins =
1721 <1 RK 1693 <1 RK_PB4 3 &pcfg_pull_up_8ma>;
1722 }; 1694 };
1723 }; 1695 };
1724 1696
1725 spi1 { 1697 spi1 {
1726 spi1_clk: spi1-clk { 1698 spi1_clk: spi1-clk {
1727 rockchip,pins 1699 rockchip,pins =
1728 <3 RK 1700 <3 RK_PB7 4 &pcfg_pull_up_4ma>;
1729 }; 1701 };
1730 1702
1731 spi1_csn0: spi1-csn0 1703 spi1_csn0: spi1-csn0 {
1732 rockchip,pins 1704 rockchip,pins =
1733 <3 RK 1705 <3 RK_PB1 4 &pcfg_pull_up_4ma>;
1734 }; 1706 };
1735 1707
1736 spi1_csn1: spi1-csn1 1708 spi1_csn1: spi1-csn1 {
1737 rockchip,pins 1709 rockchip,pins =
1738 <3 RK 1710 <3 RK_PB2 2 &pcfg_pull_up_4ma>;
1739 }; 1711 };
1740 1712
1741 spi1_miso: spi1-miso 1713 spi1_miso: spi1-miso {
1742 rockchip,pins 1714 rockchip,pins =
1743 <3 RK 1715 <3 RK_PB6 4 &pcfg_pull_up_4ma>;
1744 }; 1716 };
1745 1717
1746 spi1_mosi: spi1-mosi 1718 spi1_mosi: spi1-mosi {
1747 rockchip,pins 1719 rockchip,pins =
1748 <3 RK 1720 <3 RK_PB4 4 &pcfg_pull_up_4ma>;
1749 }; 1721 };
1750 1722
1751 spi1_clk_hs: spi1-clk 1723 spi1_clk_hs: spi1-clk-hs {
1752 rockchip,pins 1724 rockchip,pins =
1753 <3 RK 1725 <3 RK_PB7 4 &pcfg_pull_up_8ma>;
1754 }; 1726 };
1755 1727
1756 spi1_miso_hs: spi1-mi 1728 spi1_miso_hs: spi1-miso-hs {
1757 rockchip,pins 1729 rockchip,pins =
1758 <3 RK 1730 <3 RK_PB6 4 &pcfg_pull_up_8ma>;
1759 }; 1731 };
1760 1732
1761 spi1_mosi_hs: spi1-mo 1733 spi1_mosi_hs: spi1-mosi-hs {
1762 rockchip,pins 1734 rockchip,pins =
1763 <3 RK 1735 <3 RK_PB4 4 &pcfg_pull_up_8ma>;
1764 }; 1736 };
1765 }; 1737 };
1766 1738
1767 pdm { 1739 pdm {
1768 pdm_clk0m0: pdm-clk0m 1740 pdm_clk0m0: pdm-clk0m0 {
1769 rockchip,pins 1741 rockchip,pins =
1770 <3 RK 1742 <3 RK_PC6 2 &pcfg_pull_none>;
1771 }; 1743 };
1772 1744
1773 pdm_clk0m1: pdm-clk0m 1745 pdm_clk0m1: pdm-clk0m1 {
1774 rockchip,pins 1746 rockchip,pins =
1775 <2 RK 1747 <2 RK_PC6 1 &pcfg_pull_none>;
1776 }; 1748 };
1777 1749
1778 pdm_clk1: pdm-clk1 { 1750 pdm_clk1: pdm-clk1 {
1779 rockchip,pins 1751 rockchip,pins =
1780 <3 RK 1752 <3 RK_PC7 2 &pcfg_pull_none>;
1781 }; 1753 };
1782 1754
1783 pdm_sdi0m0: pdm-sdi0m 1755 pdm_sdi0m0: pdm-sdi0m0 {
1784 rockchip,pins 1756 rockchip,pins =
1785 <3 RK 1757 <3 RK_PD3 2 &pcfg_pull_none>;
1786 }; 1758 };
1787 1759
1788 pdm_sdi0m1: pdm-sdi0m 1760 pdm_sdi0m1: pdm-sdi0m1 {
1789 rockchip,pins 1761 rockchip,pins =
1790 <2 RK 1762 <2 RK_PC5 2 &pcfg_pull_none>;
1791 }; 1763 };
1792 1764
1793 pdm_sdi1: pdm-sdi1 { 1765 pdm_sdi1: pdm-sdi1 {
1794 rockchip,pins 1766 rockchip,pins =
1795 <3 RK 1767 <3 RK_PD0 2 &pcfg_pull_none>;
1796 }; 1768 };
1797 1769
1798 pdm_sdi2: pdm-sdi2 { 1770 pdm_sdi2: pdm-sdi2 {
1799 rockchip,pins 1771 rockchip,pins =
1800 <3 RK 1772 <3 RK_PD1 2 &pcfg_pull_none>;
1801 }; 1773 };
1802 1774
1803 pdm_sdi3: pdm-sdi3 { 1775 pdm_sdi3: pdm-sdi3 {
1804 rockchip,pins 1776 rockchip,pins =
1805 <3 RK 1777 <3 RK_PD2 2 &pcfg_pull_none>;
1806 }; 1778 };
1807 1779
1808 pdm_clk0m0_sleep: pdm 1780 pdm_clk0m0_sleep: pdm-clk0m0-sleep {
1809 rockchip,pins 1781 rockchip,pins =
1810 <3 RK 1782 <3 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>;
1811 }; 1783 };
1812 1784
1813 pdm_clk0m_sleep1: pdm 1785 pdm_clk0m_sleep1: pdm-clk0m1-sleep {
1814 rockchip,pins 1786 rockchip,pins =
1815 <2 RK 1787 <2 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>;
1816 }; 1788 };
1817 1789
1818 pdm_clk1_sleep: pdm-c 1790 pdm_clk1_sleep: pdm-clk1-sleep {
1819 rockchip,pins 1791 rockchip,pins =
1820 <3 RK 1792 <3 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>;
1821 }; 1793 };
1822 1794
1823 pdm_sdi0m0_sleep: pdm 1795 pdm_sdi0m0_sleep: pdm-sdi0m0-sleep {
1824 rockchip,pins 1796 rockchip,pins =
1825 <3 RK 1797 <3 RK_PD3 RK_FUNC_GPIO &pcfg_input_high>;
1826 }; 1798 };
1827 1799
1828 pdm_sdi0m1_sleep: pdm 1800 pdm_sdi0m1_sleep: pdm-sdi0m1-sleep {
1829 rockchip,pins 1801 rockchip,pins =
1830 <2 RK 1802 <2 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>;
1831 }; 1803 };
1832 1804
1833 pdm_sdi1_sleep: pdm-s 1805 pdm_sdi1_sleep: pdm-sdi1-sleep {
1834 rockchip,pins 1806 rockchip,pins =
1835 <3 RK 1807 <3 RK_PD0 RK_FUNC_GPIO &pcfg_input_high>;
1836 }; 1808 };
1837 1809
1838 pdm_sdi2_sleep: pdm-s 1810 pdm_sdi2_sleep: pdm-sdi2-sleep {
1839 rockchip,pins 1811 rockchip,pins =
1840 <3 RK 1812 <3 RK_PD1 RK_FUNC_GPIO &pcfg_input_high>;
1841 }; 1813 };
1842 1814
1843 pdm_sdi3_sleep: pdm-s 1815 pdm_sdi3_sleep: pdm-sdi3-sleep {
1844 rockchip,pins 1816 rockchip,pins =
1845 <3 RK 1817 <3 RK_PD2 RK_FUNC_GPIO &pcfg_input_high>;
1846 }; 1818 };
1847 }; 1819 };
1848 1820
1849 i2s0 { 1821 i2s0 {
1850 i2s0_8ch_mclk: i2s0-8 1822 i2s0_8ch_mclk: i2s0-8ch-mclk {
1851 rockchip,pins 1823 rockchip,pins =
1852 <3 RK 1824 <3 RK_PC1 2 &pcfg_pull_none>;
1853 }; 1825 };
1854 1826
1855 i2s0_8ch_sclktx: i2s0 1827 i2s0_8ch_sclktx: i2s0-8ch-sclktx {
1856 rockchip,pins 1828 rockchip,pins =
1857 <3 RK 1829 <3 RK_PC3 2 &pcfg_pull_none>;
1858 }; 1830 };
1859 1831
1860 i2s0_8ch_sclkrx: i2s0 1832 i2s0_8ch_sclkrx: i2s0-8ch-sclkrx {
1861 rockchip,pins 1833 rockchip,pins =
1862 <3 RK 1834 <3 RK_PB4 2 &pcfg_pull_none>;
1863 }; 1835 };
1864 1836
1865 i2s0_8ch_lrcktx: i2s0 1837 i2s0_8ch_lrcktx: i2s0-8ch-lrcktx {
1866 rockchip,pins 1838 rockchip,pins =
1867 <3 RK 1839 <3 RK_PC2 2 &pcfg_pull_none>;
1868 }; 1840 };
1869 1841
1870 i2s0_8ch_lrckrx: i2s0 1842 i2s0_8ch_lrckrx: i2s0-8ch-lrckrx {
1871 rockchip,pins 1843 rockchip,pins =
1872 <3 RK 1844 <3 RK_PB5 2 &pcfg_pull_none>;
1873 }; 1845 };
1874 1846
1875 i2s0_8ch_sdo0: i2s0-8 1847 i2s0_8ch_sdo0: i2s0-8ch-sdo0 {
1876 rockchip,pins 1848 rockchip,pins =
1877 <3 RK 1849 <3 RK_PC4 2 &pcfg_pull_none>;
1878 }; 1850 };
1879 1851
1880 i2s0_8ch_sdo1: i2s0-8 1852 i2s0_8ch_sdo1: i2s0-8ch-sdo1 {
1881 rockchip,pins 1853 rockchip,pins =
1882 <3 RK 1854 <3 RK_PC0 2 &pcfg_pull_none>;
1883 }; 1855 };
1884 1856
1885 i2s0_8ch_sdo2: i2s0-8 1857 i2s0_8ch_sdo2: i2s0-8ch-sdo2 {
1886 rockchip,pins 1858 rockchip,pins =
1887 <3 RK 1859 <3 RK_PB7 2 &pcfg_pull_none>;
1888 }; 1860 };
1889 1861
1890 i2s0_8ch_sdo3: i2s0-8 1862 i2s0_8ch_sdo3: i2s0-8ch-sdo3 {
1891 rockchip,pins 1863 rockchip,pins =
1892 <3 RK 1864 <3 RK_PB6 2 &pcfg_pull_none>;
1893 }; 1865 };
1894 1866
1895 i2s0_8ch_sdi0: i2s0-8 1867 i2s0_8ch_sdi0: i2s0-8ch-sdi0 {
1896 rockchip,pins 1868 rockchip,pins =
1897 <3 RK 1869 <3 RK_PC5 2 &pcfg_pull_none>;
1898 }; 1870 };
1899 1871
1900 i2s0_8ch_sdi1: i2s0-8 1872 i2s0_8ch_sdi1: i2s0-8ch-sdi1 {
1901 rockchip,pins 1873 rockchip,pins =
1902 <3 RK 1874 <3 RK_PB3 2 &pcfg_pull_none>;
1903 }; 1875 };
1904 1876
1905 i2s0_8ch_sdi2: i2s0-8 1877 i2s0_8ch_sdi2: i2s0-8ch-sdi2 {
1906 rockchip,pins 1878 rockchip,pins =
1907 <3 RK 1879 <3 RK_PB1 2 &pcfg_pull_none>;
1908 }; 1880 };
1909 1881
1910 i2s0_8ch_sdi3: i2s0-8 1882 i2s0_8ch_sdi3: i2s0-8ch-sdi3 {
1911 rockchip,pins 1883 rockchip,pins =
1912 <3 RK 1884 <3 RK_PB0 2 &pcfg_pull_none>;
1913 }; 1885 };
1914 }; 1886 };
1915 1887
1916 i2s1 { 1888 i2s1 {
1917 i2s1_2ch_mclk: i2s1-2 1889 i2s1_2ch_mclk: i2s1-2ch-mclk {
1918 rockchip,pins 1890 rockchip,pins =
1919 <2 RK 1891 <2 RK_PC3 1 &pcfg_pull_none>;
1920 }; 1892 };
1921 1893
1922 i2s1_2ch_sclk: i2s1-2 1894 i2s1_2ch_sclk: i2s1-2ch-sclk {
1923 rockchip,pins 1895 rockchip,pins =
1924 <2 RK 1896 <2 RK_PC2 1 &pcfg_pull_none>;
1925 }; 1897 };
1926 1898
1927 i2s1_2ch_lrck: i2s1-2 1899 i2s1_2ch_lrck: i2s1-2ch-lrck {
1928 rockchip,pins 1900 rockchip,pins =
1929 <2 RK 1901 <2 RK_PC1 1 &pcfg_pull_none>;
1930 }; 1902 };
1931 1903
1932 i2s1_2ch_sdi: i2s1-2c 1904 i2s1_2ch_sdi: i2s1-2ch-sdi {
1933 rockchip,pins 1905 rockchip,pins =
1934 <2 RK 1906 <2 RK_PC5 1 &pcfg_pull_none>;
1935 }; 1907 };
1936 1908
1937 i2s1_2ch_sdo: i2s1-2c 1909 i2s1_2ch_sdo: i2s1-2ch-sdo {
1938 rockchip,pins 1910 rockchip,pins =
1939 <2 RK 1911 <2 RK_PC4 1 &pcfg_pull_none>;
1940 }; 1912 };
1941 }; 1913 };
1942 1914
1943 i2s2 { 1915 i2s2 {
1944 i2s2_2ch_mclk: i2s2-2 1916 i2s2_2ch_mclk: i2s2-2ch-mclk {
1945 rockchip,pins 1917 rockchip,pins =
1946 <3 RK 1918 <3 RK_PA1 2 &pcfg_pull_none>;
1947 }; 1919 };
1948 1920
1949 i2s2_2ch_sclk: i2s2-2 1921 i2s2_2ch_sclk: i2s2-2ch-sclk {
1950 rockchip,pins 1922 rockchip,pins =
1951 <3 RK 1923 <3 RK_PA2 2 &pcfg_pull_none>;
1952 }; 1924 };
1953 1925
1954 i2s2_2ch_lrck: i2s2-2 1926 i2s2_2ch_lrck: i2s2-2ch-lrck {
1955 rockchip,pins 1927 rockchip,pins =
1956 <3 RK 1928 <3 RK_PA3 2 &pcfg_pull_none>;
1957 }; 1929 };
1958 1930
1959 i2s2_2ch_sdi: i2s2-2c 1931 i2s2_2ch_sdi: i2s2-2ch-sdi {
1960 rockchip,pins 1932 rockchip,pins =
1961 <3 RK 1933 <3 RK_PA5 2 &pcfg_pull_none>;
1962 }; 1934 };
1963 1935
1964 i2s2_2ch_sdo: i2s2-2c 1936 i2s2_2ch_sdo: i2s2-2ch-sdo {
1965 rockchip,pins 1937 rockchip,pins =
1966 <3 RK 1938 <3 RK_PA7 2 &pcfg_pull_none>;
1967 }; 1939 };
1968 }; 1940 };
1969 1941
1970 sdmmc { 1942 sdmmc {
1971 sdmmc_clk: sdmmc-clk 1943 sdmmc_clk: sdmmc-clk {
1972 rockchip,pins 1944 rockchip,pins =
1973 <1 RK 1945 <1 RK_PD6 1 &pcfg_pull_none_8ma>;
1974 }; 1946 };
1975 1947
1976 sdmmc_cmd: sdmmc-cmd 1948 sdmmc_cmd: sdmmc-cmd {
1977 rockchip,pins 1949 rockchip,pins =
1978 <1 RK 1950 <1 RK_PD7 1 &pcfg_pull_up_8ma>;
1979 }; 1951 };
1980 1952
1981 sdmmc_det: sdmmc-det 1953 sdmmc_det: sdmmc-det {
1982 rockchip,pins 1954 rockchip,pins =
1983 <0 RK 1955 <0 RK_PA3 1 &pcfg_pull_up_8ma>;
1984 }; 1956 };
1985 1957
1986 sdmmc_bus1: sdmmc-bus 1958 sdmmc_bus1: sdmmc-bus1 {
1987 rockchip,pins 1959 rockchip,pins =
1988 <1 RK 1960 <1 RK_PD2 1 &pcfg_pull_up_8ma>;
1989 }; 1961 };
1990 1962
1991 sdmmc_bus4: sdmmc-bus 1963 sdmmc_bus4: sdmmc-bus4 {
1992 rockchip,pins 1964 rockchip,pins =
1993 <1 RK 1965 <1 RK_PD2 1 &pcfg_pull_up_8ma>,
1994 <1 RK 1966 <1 RK_PD3 1 &pcfg_pull_up_8ma>,
1995 <1 RK 1967 <1 RK_PD4 1 &pcfg_pull_up_8ma>,
1996 <1 RK 1968 <1 RK_PD5 1 &pcfg_pull_up_8ma>;
1997 }; 1969 };
1998 }; 1970 };
1999 1971
2000 sdio { 1972 sdio {
2001 sdio_clk: sdio-clk { 1973 sdio_clk: sdio-clk {
2002 rockchip,pins 1974 rockchip,pins =
2003 <1 RK 1975 <1 RK_PC5 1 &pcfg_pull_none>;
2004 }; 1976 };
2005 1977
2006 sdio_cmd: sdio-cmd { 1978 sdio_cmd: sdio-cmd {
2007 rockchip,pins 1979 rockchip,pins =
2008 <1 RK 1980 <1 RK_PC4 1 &pcfg_pull_up>;
2009 }; 1981 };
2010 1982
2011 sdio_bus4: sdio-bus4 1983 sdio_bus4: sdio-bus4 {
2012 rockchip,pins 1984 rockchip,pins =
2013 <1 RK 1985 <1 RK_PC6 1 &pcfg_pull_up>,
2014 <1 RK 1986 <1 RK_PC7 1 &pcfg_pull_up>,
2015 <1 RK 1987 <1 RK_PD0 1 &pcfg_pull_up>,
2016 <1 RK 1988 <1 RK_PD1 1 &pcfg_pull_up>;
2017 }; 1989 };
2018 }; 1990 };
2019 1991
2020 emmc { 1992 emmc {
2021 emmc_clk: emmc-clk { 1993 emmc_clk: emmc-clk {
2022 rockchip,pins 1994 rockchip,pins =
2023 <1 RK 1995 <1 RK_PB1 2 &pcfg_pull_none_8ma>;
2024 }; 1996 };
2025 1997
2026 emmc_cmd: emmc-cmd { 1998 emmc_cmd: emmc-cmd {
2027 rockchip,pins 1999 rockchip,pins =
2028 <1 RK 2000 <1 RK_PB2 2 &pcfg_pull_up_8ma>;
2029 }; 2001 };
2030 2002
2031 emmc_rstnout: emmc-rs 2003 emmc_rstnout: emmc-rstnout {
2032 rockchip,pins 2004 rockchip,pins =
2033 <1 RK 2005 <1 RK_PB3 2 &pcfg_pull_none>;
2034 }; 2006 };
2035 2007
2036 emmc_bus1: emmc-bus1 2008 emmc_bus1: emmc-bus1 {
2037 rockchip,pins 2009 rockchip,pins =
2038 <1 RK 2010 <1 RK_PA0 2 &pcfg_pull_up_8ma>;
2039 }; 2011 };
2040 2012
2041 emmc_bus4: emmc-bus4 2013 emmc_bus4: emmc-bus4 {
2042 rockchip,pins 2014 rockchip,pins =
2043 <1 RK 2015 <1 RK_PA0 2 &pcfg_pull_up_8ma>,
2044 <1 RK 2016 <1 RK_PA1 2 &pcfg_pull_up_8ma>,
2045 <1 RK 2017 <1 RK_PA2 2 &pcfg_pull_up_8ma>,
2046 <1 RK 2018 <1 RK_PA3 2 &pcfg_pull_up_8ma>;
2047 }; 2019 };
2048 2020
2049 emmc_bus8: emmc-bus8 2021 emmc_bus8: emmc-bus8 {
2050 rockchip,pins 2022 rockchip,pins =
2051 <1 RK 2023 <1 RK_PA0 2 &pcfg_pull_up_8ma>,
2052 <1 RK 2024 <1 RK_PA1 2 &pcfg_pull_up_8ma>,
2053 <1 RK 2025 <1 RK_PA2 2 &pcfg_pull_up_8ma>,
2054 <1 RK 2026 <1 RK_PA3 2 &pcfg_pull_up_8ma>,
2055 <1 RK 2027 <1 RK_PA4 2 &pcfg_pull_up_8ma>,
2056 <1 RK 2028 <1 RK_PA5 2 &pcfg_pull_up_8ma>,
2057 <1 RK 2029 <1 RK_PA6 2 &pcfg_pull_up_8ma>,
2058 <1 RK 2030 <1 RK_PA7 2 &pcfg_pull_up_8ma>;
2059 }; 2031 };
2060 }; 2032 };
2061 2033
2062 flash { 2034 flash {
2063 flash_cs0: flash-cs0 2035 flash_cs0: flash-cs0 {
2064 rockchip,pins 2036 rockchip,pins =
2065 <1 RK 2037 <1 RK_PB0 1 &pcfg_pull_none>;
2066 }; 2038 };
2067 2039
2068 flash_rdy: flash-rdy 2040 flash_rdy: flash-rdy {
2069 rockchip,pins 2041 rockchip,pins =
2070 <1 RK 2042 <1 RK_PB1 1 &pcfg_pull_none>;
2071 }; 2043 };
2072 2044
2073 flash_dqs: flash-dqs 2045 flash_dqs: flash-dqs {
2074 rockchip,pins 2046 rockchip,pins =
2075 <1 RK 2047 <1 RK_PB2 1 &pcfg_pull_none>;
2076 }; 2048 };
2077 2049
2078 flash_ale: flash-ale 2050 flash_ale: flash-ale {
2079 rockchip,pins 2051 rockchip,pins =
2080 <1 RK 2052 <1 RK_PB3 1 &pcfg_pull_none>;
2081 }; 2053 };
2082 2054
2083 flash_cle: flash-cle 2055 flash_cle: flash-cle {
2084 rockchip,pins 2056 rockchip,pins =
2085 <1 RK 2057 <1 RK_PB4 1 &pcfg_pull_none>;
2086 }; 2058 };
2087 2059
2088 flash_wrn: flash-wrn 2060 flash_wrn: flash-wrn {
2089 rockchip,pins 2061 rockchip,pins =
2090 <1 RK 2062 <1 RK_PB5 1 &pcfg_pull_none>;
2091 }; 2063 };
2092 2064
2093 flash_csl: flash-csl 2065 flash_csl: flash-csl {
2094 rockchip,pins 2066 rockchip,pins =
2095 <1 RK 2067 <1 RK_PB6 1 &pcfg_pull_none>;
2096 }; 2068 };
2097 2069
2098 flash_rdn: flash-rdn 2070 flash_rdn: flash-rdn {
2099 rockchip,pins 2071 rockchip,pins =
2100 <1 RK 2072 <1 RK_PB7 1 &pcfg_pull_none>;
2101 }; 2073 };
2102 2074
2103 flash_bus8: flash-bus 2075 flash_bus8: flash-bus8 {
2104 rockchip,pins 2076 rockchip,pins =
2105 <1 RK 2077 <1 RK_PA0 1 &pcfg_pull_up_12ma>,
2106 <1 RK 2078 <1 RK_PA1 1 &pcfg_pull_up_12ma>,
2107 <1 RK 2079 <1 RK_PA2 1 &pcfg_pull_up_12ma>,
2108 <1 RK 2080 <1 RK_PA3 1 &pcfg_pull_up_12ma>,
2109 <1 RK 2081 <1 RK_PA4 1 &pcfg_pull_up_12ma>,
2110 <1 RK 2082 <1 RK_PA5 1 &pcfg_pull_up_12ma>,
2111 <1 RK 2083 <1 RK_PA6 1 &pcfg_pull_up_12ma>,
2112 <1 RK 2084 <1 RK_PA7 1 &pcfg_pull_up_12ma>;
2113 }; 2085 };
2114 }; 2086 };
2115 2087
2116 sfc { 2088 sfc {
2117 sfc_bus4: sfc-bus4 { 2089 sfc_bus4: sfc-bus4 {
2118 rockchip,pins 2090 rockchip,pins =
2119 <1 RK 2091 <1 RK_PA0 3 &pcfg_pull_none>,
2120 <1 RK 2092 <1 RK_PA1 3 &pcfg_pull_none>,
2121 <1 RK 2093 <1 RK_PA2 3 &pcfg_pull_none>,
2122 <1 RK 2094 <1 RK_PA3 3 &pcfg_pull_none>;
2123 }; 2095 };
2124 2096
2125 sfc_bus2: sfc-bus2 { 2097 sfc_bus2: sfc-bus2 {
2126 rockchip,pins 2098 rockchip,pins =
2127 <1 RK 2099 <1 RK_PA0 3 &pcfg_pull_none>,
2128 <1 RK 2100 <1 RK_PA1 3 &pcfg_pull_none>;
2129 }; 2101 };
2130 2102
2131 sfc_cs0: sfc-cs0 { 2103 sfc_cs0: sfc-cs0 {
2132 rockchip,pins 2104 rockchip,pins =
2133 <1 RK 2105 <1 RK_PA4 3 &pcfg_pull_none>;
2134 }; 2106 };
2135 2107
2136 sfc_clk: sfc-clk { 2108 sfc_clk: sfc-clk {
2137 rockchip,pins 2109 rockchip,pins =
2138 <1 RK 2110 <1 RK_PB1 3 &pcfg_pull_none>;
2139 }; 2111 };
2140 }; 2112 };
2141 2113
2142 lcdc { 2114 lcdc {
2143 lcdc_rgb_dclk_pin: lc 2115 lcdc_rgb_dclk_pin: lcdc-rgb-dclk-pin {
2144 rockchip,pins 2116 rockchip,pins =
2145 <3 RK 2117 <3 RK_PA0 1 &pcfg_pull_none_12ma>;
2146 }; 2118 };
2147 2119
2148 lcdc_rgb_m0_hsync_pin 2120 lcdc_rgb_m0_hsync_pin: lcdc-rgb-m0-hsync-pin {
2149 rockchip,pins 2121 rockchip,pins =
2150 <3 RK 2122 <3 RK_PA1 1 &pcfg_pull_none_12ma>;
2151 }; 2123 };
2152 2124
2153 lcdc_rgb_m0_vsync_pin 2125 lcdc_rgb_m0_vsync_pin: lcdc-rgb-m0-vsync-pin {
2154 rockchip,pins 2126 rockchip,pins =
2155 <3 RK 2127 <3 RK_PA2 1 &pcfg_pull_none_12ma>;
2156 }; 2128 };
2157 2129
2158 lcdc_rgb_m0_den_pin: 2130 lcdc_rgb_m0_den_pin: lcdc-rgb-m0-den-pin {
2159 rockchip,pins 2131 rockchip,pins =
2160 <3 RK 2132 <3 RK_PA3 1 &pcfg_pull_none_12ma>;
2161 }; 2133 };
2162 2134
2163 lcdc_rgb888_m0_data_p 2135 lcdc_rgb888_m0_data_pins: lcdc-rgb888-m0-data-pins {
2164 rockchip,pins 2136 rockchip,pins =
2165 <3 RK 2137 <3 RK_PA7 1 &pcfg_pull_none_8ma>, /* lcdc_d3 */
2166 <3 RK 2138 <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */
2167 <3 RK 2139 <3 RK_PA5 1 &pcfg_pull_none_8ma>, /* lcdc_d1 */
2168 <3 RK 2140 <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */
2169 <3 RK 2141 <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */
2170 <3 RK 2142 <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */
2171 <3 RK 2143 <3 RK_PB1 1 &pcfg_pull_none_8ma>, /* lcdc_d5 */
2172 <3 RK 2144 <3 RK_PB0 1 &pcfg_pull_none_8ma>, /* lcdc_d4 */
2173 <3 RK 2145 <3 RK_PB7 1 &pcfg_pull_none_8ma>, /* lcdc_d11 */
2174 <3 RK 2146 <3 RK_PB6 1 &pcfg_pull_none_8ma>, /* lcdc_d10 */
2175 <3 RK 2147 <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */
2176 <3 RK 2148 <3 RK_PB4 1 &pcfg_pull_none_8ma>, /* lcdc_d8 */
2177 <3 RK 2149 <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */
2178 <3 RK 2150 <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */
2179 <3 RK 2151 <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */
2180 <3 RK 2152 <3 RK_PC0 1 &pcfg_pull_none_8ma>, /* lcdc_d12 */
2181 <3 RK 2153 <3 RK_PC7 1 &pcfg_pull_none_8ma>, /* lcdc_d19 */
2182 <3 RK 2154 <3 RK_PC6 1 &pcfg_pull_none_8ma>, /* lcdc_d18 */
2183 <3 RK 2155 <3 RK_PC5 1 &pcfg_pull_none_8ma>, /* lcdc_d17 */
2184 <3 RK 2156 <3 RK_PC4 1 &pcfg_pull_none_8ma>, /* lcdc_d16 */
2185 <3 RK 2157 <3 RK_PD3 1 &pcfg_pull_none_8ma>, /* lcdc_d23 */
2186 <3 RK 2158 <3 RK_PD2 1 &pcfg_pull_none_8ma>, /* lcdc_d22 */
2187 <3 RK 2159 <3 RK_PD1 1 &pcfg_pull_none_8ma>, /* lcdc_d21 */
2188 <3 RK 2160 <3 RK_PD0 1 &pcfg_pull_none_8ma>; /* lcdc_d20 */
2189 }; 2161 };
2190 2162
2191 lcdc_rgb666_m0_data_p 2163 lcdc_rgb666_m0_data_pins: lcdc-rgb666-m0-data-pins {
2192 rockchip,pins 2164 rockchip,pins =
2193 <3 RK 2165 <3 RK_PA7 1 &pcfg_pull_none_8ma>, /* lcdc_d3 */
2194 <3 RK 2166 <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */
2195 <3 RK 2167 <3 RK_PA5 1 &pcfg_pull_none_8ma>, /* lcdc_d1 */
2196 <3 RK 2168 <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */
2197 <3 RK 2169 <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */
2198 <3 RK 2170 <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */
2199 <3 RK 2171 <3 RK_PB1 1 &pcfg_pull_none_8ma>, /* lcdc_d5 */
2200 <3 RK 2172 <3 RK_PB0 1 &pcfg_pull_none_8ma>, /* lcdc_d4 */
2201 <3 RK 2173 <3 RK_PB7 1 &pcfg_pull_none_8ma>, /* lcdc_d11 */
2202 <3 RK 2174 <3 RK_PB6 1 &pcfg_pull_none_8ma>, /* lcdc_d10 */
2203 <3 RK 2175 <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */
2204 <3 RK 2176 <3 RK_PB4 1 &pcfg_pull_none_8ma>, /* lcdc_d8 */
2205 <3 RK 2177 <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */
2206 <3 RK 2178 <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */
2207 <3 RK 2179 <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */
2208 <3 RK 2180 <3 RK_PC0 1 &pcfg_pull_none_8ma>, /* lcdc_d12 */
2209 <3 RK 2181 <3 RK_PC5 1 &pcfg_pull_none_8ma>, /* lcdc_d17 */
2210 <3 RK 2182 <3 RK_PC4 1 &pcfg_pull_none_8ma>; /* lcdc_d16 */
2211 }; 2183 };
2212 2184
2213 lcdc_rgb565_m0_data_p 2185 lcdc_rgb565_m0_data_pins: lcdc-rgb565-m0-data-pins {
2214 rockchip,pins 2186 rockchip,pins =
2215 <3 RK 2187 <3 RK_PA7 1 &pcfg_pull_none_8ma>, /* lcdc_d3 */
2216 <3 RK 2188 <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */
2217 <3 RK 2189 <3 RK_PA5 1 &pcfg_pull_none_8ma>, /* lcdc_d1 */
2218 <3 RK 2190 <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */
2219 <3 RK 2191 <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */
2220 <3 RK 2192 <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */
2221 <3 RK 2193 <3 RK_PB1 1 &pcfg_pull_none_8ma>, /* lcdc_d5 */
2222 <3 RK 2194 <3 RK_PB0 1 &pcfg_pull_none_8ma>, /* lcdc_d4 */
2223 <3 RK 2195 <3 RK_PB7 1 &pcfg_pull_none_8ma>, /* lcdc_d11 */
2224 <3 RK 2196 <3 RK_PB6 1 &pcfg_pull_none_8ma>, /* lcdc_d10 */
2225 <3 RK 2197 <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */
2226 <3 RK 2198 <3 RK_PB4 1 &pcfg_pull_none_8ma>, /* lcdc_d8 */
2227 <3 RK 2199 <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */
2228 <3 RK 2200 <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */
2229 <3 RK 2201 <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */
2230 <3 RK 2202 <3 RK_PC0 1 &pcfg_pull_none_8ma>; /* lcdc_d12 */
2231 }; 2203 };
2232 2204
2233 lcdc_rgb888_m1_data_p 2205 lcdc_rgb888_m1_data_pins: lcdc-rgb888-m1-data-pins {
2234 rockchip,pins 2206 rockchip,pins =
2235 <3 RK 2207 <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */
2236 <3 RK 2208 <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */
2237 <3 RK 2209 <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */
2238 <3 RK 2210 <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */
2239 <3 RK 2211 <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */
2240 <3 RK 2212 <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */
2241 <3 RK 2213 <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */
2242 <3 RK 2214 <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */
2243 <3 RK 2215 <3 RK_PC0 1 &pcfg_pull_none_8ma>, /* lcdc_d12 */
2244 <3 RK 2216 <3 RK_PC7 1 &pcfg_pull_none_8ma>, /* lcdc_d19 */
2245 <3 RK 2217 <3 RK_PC6 1 &pcfg_pull_none_8ma>, /* lcdc_d18 */
2246 <3 RK 2218 <3 RK_PC5 1 &pcfg_pull_none_8ma>, /* lcdc_d17 */
2247 <3 RK 2219 <3 RK_PC4 1 &pcfg_pull_none_8ma>, /* lcdc_d16 */
2248 <3 RK 2220 <3 RK_PD3 1 &pcfg_pull_none_8ma>, /* lcdc_d23 */
2249 <3 RK 2221 <3 RK_PD2 1 &pcfg_pull_none_8ma>, /* lcdc_d22 */
2250 <3 RK 2222 <3 RK_PD1 1 &pcfg_pull_none_8ma>, /* lcdc_d21 */
2251 <3 RK 2223 <3 RK_PD0 1 &pcfg_pull_none_8ma>; /* lcdc_d20 */
2252 }; 2224 };
2253 2225
2254 lcdc_rgb666_m1_data_p 2226 lcdc_rgb666_m1_data_pins: lcdc-rgb666-m1-data-pins {
2255 rockchip,pins 2227 rockchip,pins =
2256 <3 RK 2228 <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */
2257 <3 RK 2229 <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */
2258 <3 RK 2230 <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */
2259 <3 RK 2231 <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */
2260 <3 RK 2232 <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */
2261 <3 RK 2233 <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */
2262 <3 RK 2234 <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */
2263 <3 RK 2235 <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */
2264 <3 RK 2236 <3 RK_PC0 1 &pcfg_pull_none_8ma>, /* lcdc_d12 */
2265 <3 RK 2237 <3 RK_PC5 1 &pcfg_pull_none_8ma>, /* lcdc_d17 */
2266 <3 RK 2238 <3 RK_PC4 1 &pcfg_pull_none_8ma>; /* lcdc_d16 */
2267 }; 2239 };
2268 2240
2269 lcdc_rgb565_m1_data_p 2241 lcdc_rgb565_m1_data_pins: lcdc-rgb565-m1-data-pins {
2270 rockchip,pins 2242 rockchip,pins =
2271 <3 RK 2243 <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */
2272 <3 RK 2244 <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */
2273 <3 RK 2245 <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */
2274 <3 RK 2246 <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */
2275 <3 RK 2247 <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */
2276 <3 RK 2248 <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */
2277 <3 RK 2249 <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */
2278 <3 RK 2250 <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */
2279 <3 RK 2251 <3 RK_PC0 1 &pcfg_pull_none_8ma>; /* lcdc_d12 */
2280 }; 2252 };
2281 }; 2253 };
2282 2254
2283 pwm0 { 2255 pwm0 {
2284 pwm0_pin: pwm0-pin { 2256 pwm0_pin: pwm0-pin {
2285 rockchip,pins 2257 rockchip,pins =
2286 <0 RK 2258 <0 RK_PB7 1 &pcfg_pull_none>;
2287 }; 2259 };
2288 }; 2260 };
2289 2261
2290 pwm1 { 2262 pwm1 {
2291 pwm1_pin: pwm1-pin { 2263 pwm1_pin: pwm1-pin {
2292 rockchip,pins 2264 rockchip,pins =
2293 <0 RK 2265 <0 RK_PC0 1 &pcfg_pull_none>;
2294 }; 2266 };
2295 }; 2267 };
2296 2268
2297 pwm2 { 2269 pwm2 {
2298 pwm2_pin: pwm2-pin { 2270 pwm2_pin: pwm2-pin {
2299 rockchip,pins 2271 rockchip,pins =
2300 <2 RK 2272 <2 RK_PB5 1 &pcfg_pull_none>;
2301 }; 2273 };
2302 }; 2274 };
2303 2275
2304 pwm3 { 2276 pwm3 {
2305 pwm3_pin: pwm3-pin { 2277 pwm3_pin: pwm3-pin {
2306 rockchip,pins 2278 rockchip,pins =
2307 <0 RK 2279 <0 RK_PC1 1 &pcfg_pull_none>;
2308 }; 2280 };
2309 }; 2281 };
2310 2282
2311 pwm4 { 2283 pwm4 {
2312 pwm4_pin: pwm4-pin { 2284 pwm4_pin: pwm4-pin {
2313 rockchip,pins 2285 rockchip,pins =
2314 <3 RK 2286 <3 RK_PC2 3 &pcfg_pull_none>;
2315 }; 2287 };
2316 }; 2288 };
2317 2289
2318 pwm5 { 2290 pwm5 {
2319 pwm5_pin: pwm5-pin { 2291 pwm5_pin: pwm5-pin {
2320 rockchip,pins 2292 rockchip,pins =
2321 <3 RK 2293 <3 RK_PC3 3 &pcfg_pull_none>;
2322 }; 2294 };
2323 }; 2295 };
2324 2296
2325 pwm6 { 2297 pwm6 {
2326 pwm6_pin: pwm6-pin { 2298 pwm6_pin: pwm6-pin {
2327 rockchip,pins 2299 rockchip,pins =
2328 <3 RK 2300 <3 RK_PC4 3 &pcfg_pull_none>;
2329 }; 2301 };
2330 }; 2302 };
2331 2303
2332 pwm7 { 2304 pwm7 {
2333 pwm7_pin: pwm7-pin { 2305 pwm7_pin: pwm7-pin {
2334 rockchip,pins 2306 rockchip,pins =
2335 <3 RK 2307 <3 RK_PC5 3 &pcfg_pull_none>;
2336 }; 2308 };
2337 }; 2309 };
2338 2310
2339 gmac { 2311 gmac {
2340 rmii_pins: rmii-pins 2312 rmii_pins: rmii-pins {
2341 rockchip,pins 2313 rockchip,pins =
2342 <2 RK 2314 <2 RK_PA0 2 &pcfg_pull_none_12ma>, /* mac_txen */
2343 <2 RK 2315 <2 RK_PA1 2 &pcfg_pull_none_12ma>, /* mac_txd1 */
2344 <2 RK 2316 <2 RK_PA2 2 &pcfg_pull_none_12ma>, /* mac_txd0 */
2345 <2 RK 2317 <2 RK_PA3 2 &pcfg_pull_none>, /* mac_rxd0 */
2346 <2 RK 2318 <2 RK_PA4 2 &pcfg_pull_none>, /* mac_rxd1 */
2347 <2 RK 2319 <2 RK_PA5 2 &pcfg_pull_none>, /* mac_rxer */
2348 <2 RK 2320 <2 RK_PA6 2 &pcfg_pull_none>, /* mac_rxdv */
2349 <2 RK 2321 <2 RK_PA7 2 &pcfg_pull_none>, /* mac_mdio */
2350 <2 RK 2322 <2 RK_PB1 2 &pcfg_pull_none>; /* mac_mdc */
2351 }; 2323 };
2352 2324
2353 mac_refclk_12ma: mac- 2325 mac_refclk_12ma: mac-refclk-12ma {
2354 rockchip,pins 2326 rockchip,pins =
2355 <2 RK 2327 <2 RK_PB2 2 &pcfg_pull_none_12ma>;
2356 }; 2328 };
2357 2329
2358 mac_refclk: mac-refcl 2330 mac_refclk: mac-refclk {
2359 rockchip,pins 2331 rockchip,pins =
2360 <2 RK 2332 <2 RK_PB2 2 &pcfg_pull_none>;
2361 }; 2333 };
2362 }; 2334 };
2363 2335
2364 cif-m0 { 2336 cif-m0 {
2365 cif_clkout_m0: cif-cl 2337 cif_clkout_m0: cif-clkout-m0 {
2366 rockchip,pins 2338 rockchip,pins =
2367 <2 RK 2339 <2 RK_PB3 1 &pcfg_pull_none>;
2368 }; 2340 };
2369 2341
2370 dvp_d2d9_m0: dvp-d2d9 2342 dvp_d2d9_m0: dvp-d2d9-m0 {
2371 rockchip,pins 2343 rockchip,pins =
2372 <2 RK 2344 <2 RK_PA0 1 &pcfg_pull_none>, /* cif_data2 */
2373 <2 RK 2345 <2 RK_PA1 1 &pcfg_pull_none>, /* cif_data3 */
2374 <2 RK 2346 <2 RK_PA2 1 &pcfg_pull_none>, /* cif_data4 */
2375 <2 RK 2347 <2 RK_PA3 1 &pcfg_pull_none>, /* cif_data5 */
2376 <2 RK 2348 <2 RK_PA4 1 &pcfg_pull_none>, /* cif_data6 */
2377 <2 RK 2349 <2 RK_PA5 1 &pcfg_pull_none>, /* cif_data7 */
2378 <2 RK 2350 <2 RK_PA6 1 &pcfg_pull_none>, /* cif_data8 */
2379 <2 RK 2351 <2 RK_PA7 1 &pcfg_pull_none>, /* cif_data9 */
2380 <2 RK 2352 <2 RK_PB0 1 &pcfg_pull_none>, /* cif_sync */
2381 <2 RK 2353 <2 RK_PB1 1 &pcfg_pull_none>, /* cif_href */
2382 <2 RK 2354 <2 RK_PB2 1 &pcfg_pull_none>, /* cif_clkin */
2383 <2 RK 2355 <2 RK_PB3 1 &pcfg_pull_none>; /* cif_clkout */
2384 }; 2356 };
2385 2357
2386 dvp_d0d1_m0: dvp-d0d1 2358 dvp_d0d1_m0: dvp-d0d1-m0 {
2387 rockchip,pins 2359 rockchip,pins =
2388 <2 RK 2360 <2 RK_PB4 1 &pcfg_pull_none>, /* cif_data0 */
2389 <2 RK 2361 <2 RK_PB6 1 &pcfg_pull_none>; /* cif_data1 */
2390 }; 2362 };
2391 2363
2392 dvp_d10d11_m0:d10-d11 2364 dvp_d10d11_m0:d10-d11-m0 {
2393 rockchip,pins 2365 rockchip,pins =
2394 <2 RK 2366 <2 RK_PB7 1 &pcfg_pull_none>, /* cif_data10 */
2395 <2 RK 2367 <2 RK_PC0 1 &pcfg_pull_none>; /* cif_data11 */
2396 }; 2368 };
2397 }; 2369 };
2398 2370
2399 cif-m1 { 2371 cif-m1 {
2400 cif_clkout_m1: cif-cl 2372 cif_clkout_m1: cif-clkout-m1 {
2401 rockchip,pins 2373 rockchip,pins =
2402 <3 RK 2374 <3 RK_PD0 3 &pcfg_pull_none>;
2403 }; 2375 };
2404 2376
2405 dvp_d2d9_m1: dvp-d2d9 2377 dvp_d2d9_m1: dvp-d2d9-m1 {
2406 rockchip,pins 2378 rockchip,pins =
2407 <3 RK 2379 <3 RK_PA3 3 &pcfg_pull_none>, /* cif_data2 */
2408 <3 RK 2380 <3 RK_PA5 3 &pcfg_pull_none>, /* cif_data3 */
2409 <3 RK 2381 <3 RK_PA7 3 &pcfg_pull_none>, /* cif_data4 */
2410 <3 RK 2382 <3 RK_PB0 3 &pcfg_pull_none>, /* cif_data5 */
2411 <3 RK 2383 <3 RK_PB1 3 &pcfg_pull_none>, /* cif_data6 */
2412 <3 RK 2384 <3 RK_PB4 3 &pcfg_pull_none>, /* cif_data7 */
2413 <3 RK 2385 <3 RK_PB6 3 &pcfg_pull_none>, /* cif_data8 */
2414 <3 RK 2386 <3 RK_PB7 3 &pcfg_pull_none>, /* cif_data9 */
2415 <3 RK 2387 <3 RK_PD1 3 &pcfg_pull_none>, /* cif_sync */
2416 <3 RK 2388 <3 RK_PD2 3 &pcfg_pull_none>, /* cif_href */
2417 <3 RK 2389 <3 RK_PD3 3 &pcfg_pull_none>, /* cif_clkin */
2418 <3 RK 2390 <3 RK_PD0 3 &pcfg_pull_none>; /* cif_clkout */
2419 }; 2391 };
2420 2392
2421 dvp_d0d1_m1: dvp-d0d1 2393 dvp_d0d1_m1: dvp-d0d1-m1 {
2422 rockchip,pins 2394 rockchip,pins =
2423 <3 RK 2395 <3 RK_PA1 3 &pcfg_pull_none>, /* cif_data0 */
2424 <3 RK 2396 <3 RK_PA2 3 &pcfg_pull_none>; /* cif_data1 */
2425 }; 2397 };
2426 2398
2427 dvp_d10d11_m1:d10-d11 2399 dvp_d10d11_m1:d10-d11-m1 {
2428 rockchip,pins 2400 rockchip,pins =
2429 <3 RK 2401 <3 RK_PC6 3 &pcfg_pull_none>, /* cif_data10 */
2430 <3 RK 2402 <3 RK_PC7 3 &pcfg_pull_none>; /* cif_data11 */
2431 }; 2403 };
2432 }; 2404 };
2433 2405
2434 isp { 2406 isp {
2435 isp_prelight: isp-pre 2407 isp_prelight: isp-prelight {
2436 rockchip,pins 2408 rockchip,pins =
2437 <3 RK 2409 <3 RK_PD1 4 &pcfg_pull_none>;
2438 }; 2410 };
2439 }; 2411 };
2440 }; 2412 };
2441 }; 2413 };
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