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TOMOYO Linux Cross Reference
Linux/scripts/dtc/include-prefixes/arm64/rockchip/px30.dtsi

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Diff markup

Differences between /scripts/dtc/include-prefixes/arm64/rockchip/px30.dtsi (Version linux-6.12-rc7) and /scripts/dtc/include-prefixes/arm64/rockchip/px30.dtsi (Version linux-6.4.16)


  1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)       1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
  2 /*                                                  2 /*
  3  * Copyright (c) 2018 Fuzhou Rockchip Electron      3  * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd
  4  */                                                 4  */
  5                                                     5 
  6 #include <dt-bindings/clock/px30-cru.h>             6 #include <dt-bindings/clock/px30-cru.h>
  7 #include <dt-bindings/gpio/gpio.h>                  7 #include <dt-bindings/gpio/gpio.h>
  8 #include <dt-bindings/interrupt-controller/arm      8 #include <dt-bindings/interrupt-controller/arm-gic.h>
  9 #include <dt-bindings/interrupt-controller/irq      9 #include <dt-bindings/interrupt-controller/irq.h>
 10 #include <dt-bindings/pinctrl/rockchip.h>          10 #include <dt-bindings/pinctrl/rockchip.h>
 11 #include <dt-bindings/power/px30-power.h>          11 #include <dt-bindings/power/px30-power.h>
 12 #include <dt-bindings/soc/rockchip,boot-mode.h     12 #include <dt-bindings/soc/rockchip,boot-mode.h>
 13 #include <dt-bindings/thermal/thermal.h>           13 #include <dt-bindings/thermal/thermal.h>
 14                                                    14 
 15 / {                                                15 / {
 16         compatible = "rockchip,px30";              16         compatible = "rockchip,px30";
 17                                                    17 
 18         interrupt-parent = <&gic>;                 18         interrupt-parent = <&gic>;
 19         #address-cells = <2>;                      19         #address-cells = <2>;
 20         #size-cells = <2>;                         20         #size-cells = <2>;
 21                                                    21 
 22         aliases {                                  22         aliases {
                                                   >>  23                 ethernet0 = &gmac;
 23                 i2c0 = &i2c0;                      24                 i2c0 = &i2c0;
 24                 i2c1 = &i2c1;                      25                 i2c1 = &i2c1;
 25                 i2c2 = &i2c2;                      26                 i2c2 = &i2c2;
 26                 i2c3 = &i2c3;                      27                 i2c3 = &i2c3;
 27                 serial0 = &uart0;                  28                 serial0 = &uart0;
 28                 serial1 = &uart1;                  29                 serial1 = &uart1;
 29                 serial2 = &uart2;                  30                 serial2 = &uart2;
 30                 serial3 = &uart3;                  31                 serial3 = &uart3;
 31                 serial4 = &uart4;                  32                 serial4 = &uart4;
 32                 serial5 = &uart5;                  33                 serial5 = &uart5;
 33                 spi0 = &spi0;                      34                 spi0 = &spi0;
 34                 spi1 = &spi1;                      35                 spi1 = &spi1;
 35         };                                         36         };
 36                                                    37 
 37         cpus {                                     38         cpus {
 38                 #address-cells = <2>;              39                 #address-cells = <2>;
 39                 #size-cells = <0>;                 40                 #size-cells = <0>;
 40                                                    41 
 41                 cpu0: cpu@0 {                      42                 cpu0: cpu@0 {
 42                         device_type = "cpu";       43                         device_type = "cpu";
 43                         compatible = "arm,cort     44                         compatible = "arm,cortex-a35";
 44                         reg = <0x0 0x0>;           45                         reg = <0x0 0x0>;
 45                         enable-method = "psci"     46                         enable-method = "psci";
 46                         clocks = <&cru ARMCLK>     47                         clocks = <&cru ARMCLK>;
 47                         #cooling-cells = <2>;      48                         #cooling-cells = <2>;
 48                         cpu-idle-states = <&CP     49                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
 49                         dynamic-power-coeffici     50                         dynamic-power-coefficient = <90>;
 50                         operating-points-v2 =      51                         operating-points-v2 = <&cpu0_opp_table>;
 51                 };                                 52                 };
 52                                                    53 
 53                 cpu1: cpu@1 {                      54                 cpu1: cpu@1 {
 54                         device_type = "cpu";       55                         device_type = "cpu";
 55                         compatible = "arm,cort     56                         compatible = "arm,cortex-a35";
 56                         reg = <0x0 0x1>;           57                         reg = <0x0 0x1>;
 57                         enable-method = "psci"     58                         enable-method = "psci";
 58                         clocks = <&cru ARMCLK>     59                         clocks = <&cru ARMCLK>;
 59                         #cooling-cells = <2>;      60                         #cooling-cells = <2>;
 60                         cpu-idle-states = <&CP     61                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
 61                         dynamic-power-coeffici     62                         dynamic-power-coefficient = <90>;
 62                         operating-points-v2 =      63                         operating-points-v2 = <&cpu0_opp_table>;
 63                 };                                 64                 };
 64                                                    65 
 65                 cpu2: cpu@2 {                      66                 cpu2: cpu@2 {
 66                         device_type = "cpu";       67                         device_type = "cpu";
 67                         compatible = "arm,cort     68                         compatible = "arm,cortex-a35";
 68                         reg = <0x0 0x2>;           69                         reg = <0x0 0x2>;
 69                         enable-method = "psci"     70                         enable-method = "psci";
 70                         clocks = <&cru ARMCLK>     71                         clocks = <&cru ARMCLK>;
 71                         #cooling-cells = <2>;      72                         #cooling-cells = <2>;
 72                         cpu-idle-states = <&CP     73                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
 73                         dynamic-power-coeffici     74                         dynamic-power-coefficient = <90>;
 74                         operating-points-v2 =      75                         operating-points-v2 = <&cpu0_opp_table>;
 75                 };                                 76                 };
 76                                                    77 
 77                 cpu3: cpu@3 {                      78                 cpu3: cpu@3 {
 78                         device_type = "cpu";       79                         device_type = "cpu";
 79                         compatible = "arm,cort     80                         compatible = "arm,cortex-a35";
 80                         reg = <0x0 0x3>;           81                         reg = <0x0 0x3>;
 81                         enable-method = "psci"     82                         enable-method = "psci";
 82                         clocks = <&cru ARMCLK>     83                         clocks = <&cru ARMCLK>;
 83                         #cooling-cells = <2>;      84                         #cooling-cells = <2>;
 84                         cpu-idle-states = <&CP     85                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
 85                         dynamic-power-coeffici     86                         dynamic-power-coefficient = <90>;
 86                         operating-points-v2 =      87                         operating-points-v2 = <&cpu0_opp_table>;
 87                 };                                 88                 };
 88                                                    89 
 89                 idle-states {                      90                 idle-states {
 90                         entry-method = "psci";     91                         entry-method = "psci";
 91                                                    92 
 92                         CPU_SLEEP: cpu-sleep {     93                         CPU_SLEEP: cpu-sleep {
 93                                 compatible = "     94                                 compatible = "arm,idle-state";
 94                                 local-timer-st     95                                 local-timer-stop;
 95                                 arm,psci-suspe     96                                 arm,psci-suspend-param = <0x0010000>;
 96                                 entry-latency-     97                                 entry-latency-us = <120>;
 97                                 exit-latency-u     98                                 exit-latency-us = <250>;
 98                                 min-residency-     99                                 min-residency-us = <900>;
 99                         };                        100                         };
100                                                   101 
101                         CLUSTER_SLEEP: cluster    102                         CLUSTER_SLEEP: cluster-sleep {
102                                 compatible = "    103                                 compatible = "arm,idle-state";
103                                 local-timer-st    104                                 local-timer-stop;
104                                 arm,psci-suspe    105                                 arm,psci-suspend-param = <0x1010000>;
105                                 entry-latency-    106                                 entry-latency-us = <400>;
106                                 exit-latency-u    107                                 exit-latency-us = <500>;
107                                 min-residency-    108                                 min-residency-us = <2000>;
108                         };                        109                         };
109                 };                                110                 };
110         };                                        111         };
111                                                   112 
112         cpu0_opp_table: opp-table-0 {             113         cpu0_opp_table: opp-table-0 {
113                 compatible = "operating-points    114                 compatible = "operating-points-v2";
114                 opp-shared;                       115                 opp-shared;
115                                                   116 
116                 opp-600000000 {                   117                 opp-600000000 {
117                         opp-hz = /bits/ 64 <60    118                         opp-hz = /bits/ 64 <600000000>;
118                         opp-microvolt = <95000    119                         opp-microvolt = <950000 950000 1350000>;
119                         clock-latency-ns = <40    120                         clock-latency-ns = <40000>;
120                         opp-suspend;              121                         opp-suspend;
121                 };                                122                 };
122                 opp-816000000 {                   123                 opp-816000000 {
123                         opp-hz = /bits/ 64 <81    124                         opp-hz = /bits/ 64 <816000000>;
124                         opp-microvolt = <10500    125                         opp-microvolt = <1050000 1050000 1350000>;
125                         clock-latency-ns = <40    126                         clock-latency-ns = <40000>;
126                 };                                127                 };
127                 opp-1008000000 {                  128                 opp-1008000000 {
128                         opp-hz = /bits/ 64 <10    129                         opp-hz = /bits/ 64 <1008000000>;
129                         opp-microvolt = <11750    130                         opp-microvolt = <1175000 1175000 1350000>;
130                         clock-latency-ns = <40    131                         clock-latency-ns = <40000>;
131                 };                                132                 };
132                 opp-1200000000 {                  133                 opp-1200000000 {
133                         opp-hz = /bits/ 64 <12    134                         opp-hz = /bits/ 64 <1200000000>;
134                         opp-microvolt = <13000    135                         opp-microvolt = <1300000 1300000 1350000>;
135                         clock-latency-ns = <40    136                         clock-latency-ns = <40000>;
136                 };                                137                 };
137                 opp-1296000000 {                  138                 opp-1296000000 {
138                         opp-hz = /bits/ 64 <12    139                         opp-hz = /bits/ 64 <1296000000>;
139                         opp-microvolt = <13500    140                         opp-microvolt = <1350000 1350000 1350000>;
140                         clock-latency-ns = <40    141                         clock-latency-ns = <40000>;
141                 };                                142                 };
142         };                                        143         };
143                                                   144 
144         arm-pmu {                                 145         arm-pmu {
145                 compatible = "arm,cortex-a35-p    146                 compatible = "arm,cortex-a35-pmu";
146                 interrupts = <GIC_SPI 100 IRQ_    147                 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
147                              <GIC_SPI 101 IRQ_    148                              <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
148                              <GIC_SPI 102 IRQ_    149                              <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
149                              <GIC_SPI 103 IRQ_    150                              <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
150                 interrupt-affinity = <&cpu0>,     151                 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
151         };                                        152         };
152                                                   153 
153         display_subsystem: display-subsystem {    154         display_subsystem: display-subsystem {
154                 compatible = "rockchip,display    155                 compatible = "rockchip,display-subsystem";
155                 ports = <&vopb_out>, <&vopl_ou    156                 ports = <&vopb_out>, <&vopl_out>;
156                 status = "disabled";              157                 status = "disabled";
157         };                                        158         };
158                                                   159 
159         gmac_clkin: external-gmac-clock {         160         gmac_clkin: external-gmac-clock {
160                 compatible = "fixed-clock";       161                 compatible = "fixed-clock";
161                 clock-frequency = <50000000>;     162                 clock-frequency = <50000000>;
162                 clock-output-names = "gmac_clk    163                 clock-output-names = "gmac_clkin";
163                 #clock-cells = <0>;               164                 #clock-cells = <0>;
164         };                                        165         };
165                                                   166 
166         psci {                                    167         psci {
167                 compatible = "arm,psci-1.0";      168                 compatible = "arm,psci-1.0";
168                 method = "smc";                   169                 method = "smc";
169         };                                        170         };
170                                                   171 
171         timer {                                   172         timer {
172                 compatible = "arm,armv8-timer"    173                 compatible = "arm,armv8-timer";
173                 interrupts = <GIC_PPI 13 (GIC_    174                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
174                              <GIC_PPI 14 (GIC_    175                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
175                              <GIC_PPI 11 (GIC_    176                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
176                              <GIC_PPI 10 (GIC_    177                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
177         };                                        178         };
178                                                   179 
179         thermal_zones: thermal-zones {            180         thermal_zones: thermal-zones {
180                 soc_thermal: soc-thermal {        181                 soc_thermal: soc-thermal {
181                         polling-delay-passive     182                         polling-delay-passive = <20>;
182                         polling-delay = <1000>    183                         polling-delay = <1000>;
183                         sustainable-power = <7    184                         sustainable-power = <750>;
184                         thermal-sensors = <&ts    185                         thermal-sensors = <&tsadc 0>;
185                                                   186 
186                         trips {                   187                         trips {
187                                 threshold: tri    188                                 threshold: trip-point-0 {
188                                         temper    189                                         temperature = <70000>;
189                                         hyster    190                                         hysteresis = <2000>;
190                                         type =    191                                         type = "passive";
191                                 };                192                                 };
192                                                   193 
193                                 target: trip-p    194                                 target: trip-point-1 {
194                                         temper    195                                         temperature = <85000>;
195                                         hyster    196                                         hysteresis = <2000>;
196                                         type =    197                                         type = "passive";
197                                 };                198                                 };
198                                                   199 
199                                 soc_crit: soc-    200                                 soc_crit: soc-crit {
200                                         temper    201                                         temperature = <115000>;
201                                         hyster    202                                         hysteresis = <2000>;
202                                         type =    203                                         type = "critical";
203                                 };                204                                 };
204                         };                        205                         };
205                                                   206 
206                         cooling-maps {            207                         cooling-maps {
207                                 map0 {            208                                 map0 {
208                                         trip =    209                                         trip = <&target>;
209                                         coolin    210                                         cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
210                                         contri    211                                         contribution = <4096>;
211                                 };                212                                 };
212                         };                        213                         };
213                 };                                214                 };
214                                                   215 
215                 gpu_thermal: gpu-thermal {        216                 gpu_thermal: gpu-thermal {
216                         polling-delay-passive     217                         polling-delay-passive = <100>; /* milliseconds */
217                         polling-delay = <1000>    218                         polling-delay = <1000>; /* milliseconds */
218                         thermal-sensors = <&ts    219                         thermal-sensors = <&tsadc 1>;
219                                                   220 
220                         trips {                   221                         trips {
221                                 gpu_threshold:    222                                 gpu_threshold: gpu-threshold {
222                                         temper    223                                         temperature = <70000>;
223                                         hyster    224                                         hysteresis = <2000>;
224                                         type =    225                                         type = "passive";
225                                 };                226                                 };
226                                                   227 
227                                 gpu_target: gp    228                                 gpu_target: gpu-target {
228                                         temper    229                                         temperature = <85000>;
229                                         hyster    230                                         hysteresis = <2000>;
230                                         type =    231                                         type = "passive";
231                                 };                232                                 };
232                                                   233 
233                                 gpu_crit: gpu-    234                                 gpu_crit: gpu-crit {
234                                         temper    235                                         temperature = <115000>;
235                                         hyster    236                                         hysteresis = <2000>;
236                                         type =    237                                         type = "critical";
237                                 };                238                                 };
238                         };                        239                         };
239                                                   240 
240                         cooling-maps {            241                         cooling-maps {
241                                 map0 {            242                                 map0 {
242                                         trip =    243                                         trip = <&gpu_target>;
243                                         coolin    244                                         cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
244                                 };                245                                 };
245                         };                        246                         };
246                 };                                247                 };
247         };                                        248         };
248                                                   249 
249         xin24m: xin24m {                          250         xin24m: xin24m {
250                 compatible = "fixed-clock";       251                 compatible = "fixed-clock";
251                 #clock-cells = <0>;               252                 #clock-cells = <0>;
252                 clock-frequency = <24000000>;     253                 clock-frequency = <24000000>;
253                 clock-output-names = "xin24m";    254                 clock-output-names = "xin24m";
254         };                                        255         };
255                                                   256 
256         pmu: power-management@ff000000 {          257         pmu: power-management@ff000000 {
257                 compatible = "rockchip,px30-pm    258                 compatible = "rockchip,px30-pmu", "syscon", "simple-mfd";
258                 reg = <0x0 0xff000000 0x0 0x10    259                 reg = <0x0 0xff000000 0x0 0x1000>;
259                                                   260 
260                 power: power-controller {         261                 power: power-controller {
261                         compatible = "rockchip    262                         compatible = "rockchip,px30-power-controller";
262                         #power-domain-cells =     263                         #power-domain-cells = <1>;
263                         #address-cells = <1>;     264                         #address-cells = <1>;
264                         #size-cells = <0>;        265                         #size-cells = <0>;
265                                                   266 
266                         /* These power domains    267                         /* These power domains are grouped by VD_LOGIC */
267                         power-domain@PX30_PD_U    268                         power-domain@PX30_PD_USB {
268                                 reg = <PX30_PD    269                                 reg = <PX30_PD_USB>;
269                                 clocks = <&cru    270                                 clocks = <&cru HCLK_HOST>,
270                                          <&cru    271                                          <&cru HCLK_OTG>,
271                                          <&cru    272                                          <&cru SCLK_OTG_ADP>;
272                                 pm_qos = <&qos    273                                 pm_qos = <&qos_usb_host>, <&qos_usb_otg>;
273                                 #power-domain-    274                                 #power-domain-cells = <0>;
274                         };                        275                         };
275                         power-domain@PX30_PD_S    276                         power-domain@PX30_PD_SDCARD {
276                                 reg = <PX30_PD    277                                 reg = <PX30_PD_SDCARD>;
277                                 clocks = <&cru    278                                 clocks = <&cru HCLK_SDMMC>,
278                                          <&cru    279                                          <&cru SCLK_SDMMC>;
279                                 pm_qos = <&qos    280                                 pm_qos = <&qos_sdmmc>;
280                                 #power-domain-    281                                 #power-domain-cells = <0>;
281                         };                        282                         };
282                         power-domain@PX30_PD_G    283                         power-domain@PX30_PD_GMAC {
283                                 reg = <PX30_PD    284                                 reg = <PX30_PD_GMAC>;
284                                 clocks = <&cru    285                                 clocks = <&cru ACLK_GMAC>,
285                                          <&cru    286                                          <&cru PCLK_GMAC>,
286                                          <&cru    287                                          <&cru SCLK_MAC_REF>,
287                                          <&cru    288                                          <&cru SCLK_GMAC_RX_TX>;
288                                 pm_qos = <&qos    289                                 pm_qos = <&qos_gmac>;
289                                 #power-domain-    290                                 #power-domain-cells = <0>;
290                         };                        291                         };
291                         power-domain@PX30_PD_M    292                         power-domain@PX30_PD_MMC_NAND {
292                                 reg = <PX30_PD    293                                 reg = <PX30_PD_MMC_NAND>;
293                                 clocks = <&cru !! 294                                 clocks =  <&cru HCLK_NANDC>,
294                                          <&cru !! 295                                           <&cru HCLK_EMMC>,
295                                          <&cru !! 296                                           <&cru HCLK_SDIO>,
296                                          <&cru !! 297                                           <&cru HCLK_SFC>,
297                                          <&cru !! 298                                           <&cru SCLK_EMMC>,
298                                          <&cru !! 299                                           <&cru SCLK_NANDC>,
299                                          <&cru !! 300                                           <&cru SCLK_SDIO>,
300                                          <&cru !! 301                                           <&cru SCLK_SFC>;
301                                 pm_qos = <&qos    302                                 pm_qos = <&qos_emmc>, <&qos_nand>,
302                                          <&qos    303                                          <&qos_sdio>, <&qos_sfc>;
303                                 #power-domain-    304                                 #power-domain-cells = <0>;
304                         };                        305                         };
305                         power-domain@PX30_PD_V    306                         power-domain@PX30_PD_VPU {
306                                 reg = <PX30_PD    307                                 reg = <PX30_PD_VPU>;
307                                 clocks = <&cru    308                                 clocks = <&cru ACLK_VPU>,
308                                          <&cru    309                                          <&cru HCLK_VPU>,
309                                          <&cru    310                                          <&cru SCLK_CORE_VPU>;
310                                 pm_qos = <&qos    311                                 pm_qos = <&qos_vpu>, <&qos_vpu_r128>;
311                                 #power-domain-    312                                 #power-domain-cells = <0>;
312                         };                        313                         };
313                         power-domain@PX30_PD_V    314                         power-domain@PX30_PD_VO {
314                                 reg = <PX30_PD    315                                 reg = <PX30_PD_VO>;
315                                 clocks = <&cru    316                                 clocks = <&cru ACLK_RGA>,
316                                          <&cru    317                                          <&cru ACLK_VOPB>,
317                                          <&cru    318                                          <&cru ACLK_VOPL>,
318                                          <&cru    319                                          <&cru DCLK_VOPB>,
319                                          <&cru    320                                          <&cru DCLK_VOPL>,
320                                          <&cru    321                                          <&cru HCLK_RGA>,
321                                          <&cru    322                                          <&cru HCLK_VOPB>,
322                                          <&cru    323                                          <&cru HCLK_VOPL>,
323                                          <&cru    324                                          <&cru PCLK_MIPI_DSI>,
324                                          <&cru    325                                          <&cru SCLK_RGA_CORE>,
325                                          <&cru    326                                          <&cru SCLK_VOPB_PWM>;
326                                 pm_qos = <&qos    327                                 pm_qos = <&qos_rga_rd>, <&qos_rga_wr>,
327                                          <&qos    328                                          <&qos_vop_m0>, <&qos_vop_m1>;
328                                 #power-domain-    329                                 #power-domain-cells = <0>;
329                         };                        330                         };
330                         power-domain@PX30_PD_V    331                         power-domain@PX30_PD_VI {
331                                 reg = <PX30_PD    332                                 reg = <PX30_PD_VI>;
332                                 clocks = <&cru    333                                 clocks = <&cru ACLK_CIF>,
333                                          <&cru    334                                          <&cru ACLK_ISP>,
334                                          <&cru    335                                          <&cru HCLK_CIF>,
335                                          <&cru    336                                          <&cru HCLK_ISP>,
336                                          <&cru    337                                          <&cru SCLK_ISP>;
337                                 pm_qos = <&qos    338                                 pm_qos = <&qos_isp_128>, <&qos_isp_rd>,
338                                          <&qos    339                                          <&qos_isp_wr>, <&qos_isp_m1>,
339                                          <&qos    340                                          <&qos_vip>;
340                                 #power-domain-    341                                 #power-domain-cells = <0>;
341                         };                        342                         };
342                         power-domain@PX30_PD_G    343                         power-domain@PX30_PD_GPU {
343                                 reg = <PX30_PD    344                                 reg = <PX30_PD_GPU>;
344                                 clocks = <&cru    345                                 clocks = <&cru SCLK_GPU>;
345                                 pm_qos = <&qos    346                                 pm_qos = <&qos_gpu>;
346                                 #power-domain-    347                                 #power-domain-cells = <0>;
347                         };                        348                         };
348                 };                                349                 };
349         };                                        350         };
350                                                   351 
351         pmugrf: syscon@ff010000 {                 352         pmugrf: syscon@ff010000 {
352                 compatible = "rockchip,px30-pm    353                 compatible = "rockchip,px30-pmugrf", "syscon", "simple-mfd";
353                 reg = <0x0 0xff010000 0x0 0x10    354                 reg = <0x0 0xff010000 0x0 0x1000>;
354                 #address-cells = <1>;             355                 #address-cells = <1>;
355                 #size-cells = <1>;                356                 #size-cells = <1>;
356                                                   357 
357                 pmu_io_domains: io-domains {      358                 pmu_io_domains: io-domains {
358                         compatible = "rockchip    359                         compatible = "rockchip,px30-pmu-io-voltage-domain";
359                         status = "disabled";      360                         status = "disabled";
360                 };                                361                 };
361                                                   362 
362                 reboot-mode {                     363                 reboot-mode {
363                         compatible = "syscon-r    364                         compatible = "syscon-reboot-mode";
364                         offset = <0x200>;         365                         offset = <0x200>;
365                         mode-bootloader = <BOO    366                         mode-bootloader = <BOOT_BL_DOWNLOAD>;
366                         mode-fastboot = <BOOT_    367                         mode-fastboot = <BOOT_FASTBOOT>;
367                         mode-loader = <BOOT_BL    368                         mode-loader = <BOOT_BL_DOWNLOAD>;
368                         mode-normal = <BOOT_NO    369                         mode-normal = <BOOT_NORMAL>;
369                         mode-recovery = <BOOT_    370                         mode-recovery = <BOOT_RECOVERY>;
370                 };                                371                 };
371         };                                        372         };
372                                                   373 
373         uart0: serial@ff030000 {                  374         uart0: serial@ff030000 {
374                 compatible = "rockchip,px30-ua    375                 compatible = "rockchip,px30-uart", "snps,dw-apb-uart";
375                 reg = <0x0 0xff030000 0x0 0x10    376                 reg = <0x0 0xff030000 0x0 0x100>;
376                 interrupts = <GIC_SPI 15 IRQ_T    377                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
377                 clocks = <&pmucru SCLK_UART0_P    378                 clocks = <&pmucru SCLK_UART0_PMU>, <&pmucru PCLK_UART0_PMU>;
378                 clock-names = "baudclk", "apb_    379                 clock-names = "baudclk", "apb_pclk";
379                 dmas = <&dmac 0>, <&dmac 1>;      380                 dmas = <&dmac 0>, <&dmac 1>;
380                 dma-names = "tx", "rx";           381                 dma-names = "tx", "rx";
381                 reg-shift = <2>;                  382                 reg-shift = <2>;
382                 reg-io-width = <4>;               383                 reg-io-width = <4>;
383                 pinctrl-names = "default";        384                 pinctrl-names = "default";
384                 pinctrl-0 = <&uart0_xfer &uart    385                 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
385                 status = "disabled";              386                 status = "disabled";
386         };                                        387         };
387                                                   388 
388         i2s0_8ch: i2s@ff060000 {                  389         i2s0_8ch: i2s@ff060000 {
389                 compatible = "rockchip,px30-i2    390                 compatible = "rockchip,px30-i2s-tdm";
390                 reg = <0x0 0xff060000 0x0 0x10    391                 reg = <0x0 0xff060000 0x0 0x1000>;
391                 interrupts = <GIC_SPI 12 IRQ_T    392                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
392                 clocks = <&cru SCLK_I2S0_TX>,     393                 clocks = <&cru SCLK_I2S0_TX>, <&cru SCLK_I2S0_RX>, <&cru HCLK_I2S0>;
393                 clock-names = "mclk_tx", "mclk    394                 clock-names = "mclk_tx", "mclk_rx", "hclk";
394                 dmas = <&dmac 16>, <&dmac 17>;    395                 dmas = <&dmac 16>, <&dmac 17>;
395                 dma-names = "tx", "rx";           396                 dma-names = "tx", "rx";
396                 rockchip,grf = <&grf>;            397                 rockchip,grf = <&grf>;
397                 resets = <&cru SRST_I2S0_TX>,     398                 resets = <&cru SRST_I2S0_TX>, <&cru SRST_I2S0_RX>;
398                 reset-names = "tx-m", "rx-m";     399                 reset-names = "tx-m", "rx-m";
399                 pinctrl-names = "default";        400                 pinctrl-names = "default";
400                 pinctrl-0 = <&i2s0_8ch_sclktx     401                 pinctrl-0 = <&i2s0_8ch_sclktx &i2s0_8ch_sclkrx
401                              &i2s0_8ch_lrcktx     402                              &i2s0_8ch_lrcktx &i2s0_8ch_lrckrx
402                              &i2s0_8ch_sdo0 &i    403                              &i2s0_8ch_sdo0 &i2s0_8ch_sdi0
403                              &i2s0_8ch_sdo1 &i    404                              &i2s0_8ch_sdo1 &i2s0_8ch_sdi1
404                              &i2s0_8ch_sdo2 &i    405                              &i2s0_8ch_sdo2 &i2s0_8ch_sdi2
405                              &i2s0_8ch_sdo3 &i    406                              &i2s0_8ch_sdo3 &i2s0_8ch_sdi3>;
406                 #sound-dai-cells = <0>;           407                 #sound-dai-cells = <0>;
407                 status = "disabled";              408                 status = "disabled";
408         };                                        409         };
409                                                   410 
410         i2s1_2ch: i2s@ff070000 {                  411         i2s1_2ch: i2s@ff070000 {
411                 compatible = "rockchip,px30-i2    412                 compatible = "rockchip,px30-i2s", "rockchip,rk3066-i2s";
412                 reg = <0x0 0xff070000 0x0 0x10    413                 reg = <0x0 0xff070000 0x0 0x1000>;
413                 interrupts = <GIC_SPI 13 IRQ_T    414                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
414                 clocks = <&cru SCLK_I2S1>, <&c    415                 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1>;
415                 clock-names = "i2s_clk", "i2s_    416                 clock-names = "i2s_clk", "i2s_hclk";
416                 dmas = <&dmac 18>, <&dmac 19>;    417                 dmas = <&dmac 18>, <&dmac 19>;
417                 dma-names = "tx", "rx";           418                 dma-names = "tx", "rx";
418                 pinctrl-names = "default";        419                 pinctrl-names = "default";
419                 pinctrl-0 = <&i2s1_2ch_sclk &i    420                 pinctrl-0 = <&i2s1_2ch_sclk &i2s1_2ch_lrck
420                              &i2s1_2ch_sdi &i2    421                              &i2s1_2ch_sdi &i2s1_2ch_sdo>;
421                 #sound-dai-cells = <0>;           422                 #sound-dai-cells = <0>;
422                 status = "disabled";              423                 status = "disabled";
423         };                                        424         };
424                                                   425 
425         i2s2_2ch: i2s@ff080000 {                  426         i2s2_2ch: i2s@ff080000 {
426                 compatible = "rockchip,px30-i2    427                 compatible = "rockchip,px30-i2s", "rockchip,rk3066-i2s";
427                 reg = <0x0 0xff080000 0x0 0x10    428                 reg = <0x0 0xff080000 0x0 0x1000>;
428                 interrupts = <GIC_SPI 14 IRQ_T    429                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
429                 clocks = <&cru SCLK_I2S2>, <&c    430                 clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2>;
430                 clock-names = "i2s_clk", "i2s_    431                 clock-names = "i2s_clk", "i2s_hclk";
431                 dmas = <&dmac 20>, <&dmac 21>;    432                 dmas = <&dmac 20>, <&dmac 21>;
432                 dma-names = "tx", "rx";           433                 dma-names = "tx", "rx";
433                 pinctrl-names = "default";        434                 pinctrl-names = "default";
434                 pinctrl-0 = <&i2s2_2ch_sclk &i    435                 pinctrl-0 = <&i2s2_2ch_sclk &i2s2_2ch_lrck
435                              &i2s2_2ch_sdi &i2    436                              &i2s2_2ch_sdi &i2s2_2ch_sdo>;
436                 #sound-dai-cells = <0>;           437                 #sound-dai-cells = <0>;
437                 status = "disabled";              438                 status = "disabled";
438         };                                        439         };
439                                                   440 
440         gic: interrupt-controller@ff131000 {      441         gic: interrupt-controller@ff131000 {
441                 compatible = "arm,gic-400";       442                 compatible = "arm,gic-400";
442                 #interrupt-cells = <3>;           443                 #interrupt-cells = <3>;
443                 #address-cells = <0>;             444                 #address-cells = <0>;
444                 interrupt-controller;             445                 interrupt-controller;
445                 reg = <0x0 0xff131000 0 0x1000    446                 reg = <0x0 0xff131000 0 0x1000>,
446                       <0x0 0xff132000 0 0x2000    447                       <0x0 0xff132000 0 0x2000>,
447                       <0x0 0xff134000 0 0x2000    448                       <0x0 0xff134000 0 0x2000>,
448                       <0x0 0xff136000 0 0x2000    449                       <0x0 0xff136000 0 0x2000>;
449                 interrupts = <GIC_PPI 9           450                 interrupts = <GIC_PPI 9
450                       (GIC_CPU_MASK_SIMPLE(4)     451                       (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
451         };                                        452         };
452                                                   453 
453         grf: syscon@ff140000 {                    454         grf: syscon@ff140000 {
454                 compatible = "rockchip,px30-gr    455                 compatible = "rockchip,px30-grf", "syscon", "simple-mfd";
455                 reg = <0x0 0xff140000 0x0 0x10    456                 reg = <0x0 0xff140000 0x0 0x1000>;
456                 #address-cells = <1>;             457                 #address-cells = <1>;
457                 #size-cells = <1>;                458                 #size-cells = <1>;
458                                                   459 
459                 io_domains: io-domains {          460                 io_domains: io-domains {
460                         compatible = "rockchip    461                         compatible = "rockchip,px30-io-voltage-domain";
461                         status = "disabled";      462                         status = "disabled";
462                 };                                463                 };
463                                                   464 
464                 lvds: lvds {                      465                 lvds: lvds {
465                         compatible = "rockchip    466                         compatible = "rockchip,px30-lvds";
466                         phys = <&dsi_dphy>;       467                         phys = <&dsi_dphy>;
467                         phy-names = "dphy";       468                         phy-names = "dphy";
468                         rockchip,grf = <&grf>;    469                         rockchip,grf = <&grf>;
469                         rockchip,output = "lvd    470                         rockchip,output = "lvds";
470                         status = "disabled";      471                         status = "disabled";
471                                                   472 
472                         ports {                   473                         ports {
473                                 #address-cells    474                                 #address-cells = <1>;
474                                 #size-cells =     475                                 #size-cells = <0>;
475                                                   476 
476                                 lvds_in: port@    477                                 lvds_in: port@0 {
477                                         reg =     478                                         reg = <0>;
478                                         #addre    479                                         #address-cells = <1>;
479                                         #size-    480                                         #size-cells = <0>;
480                                                   481 
481                                         lvds_v    482                                         lvds_vopb_in: endpoint@0 {
482                                                   483                                                 reg = <0>;
483                                                   484                                                 remote-endpoint = <&vopb_out_lvds>;
484                                         };        485                                         };
485                                                   486 
486                                         lvds_v    487                                         lvds_vopl_in: endpoint@1 {
487                                                   488                                                 reg = <1>;
488                                                   489                                                 remote-endpoint = <&vopl_out_lvds>;
489                                         };        490                                         };
490                                 };                491                                 };
491                                                   492 
492                                 lvds_out: port    493                                 lvds_out: port@1 {
493                                         reg =     494                                         reg = <1>;
494                                 };                495                                 };
495                         };                        496                         };
496                 };                                497                 };
497         };                                        498         };
498                                                   499 
499         uart1: serial@ff158000 {                  500         uart1: serial@ff158000 {
500                 compatible = "rockchip,px30-ua    501                 compatible = "rockchip,px30-uart", "snps,dw-apb-uart";
501                 reg = <0x0 0xff158000 0x0 0x10    502                 reg = <0x0 0xff158000 0x0 0x100>;
502                 interrupts = <GIC_SPI 16 IRQ_T    503                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
503                 clocks = <&cru SCLK_UART1>, <&    504                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
504                 clock-names = "baudclk", "apb_    505                 clock-names = "baudclk", "apb_pclk";
505                 dmas = <&dmac 2>, <&dmac 3>;      506                 dmas = <&dmac 2>, <&dmac 3>;
506                 dma-names = "tx", "rx";           507                 dma-names = "tx", "rx";
507                 reg-shift = <2>;                  508                 reg-shift = <2>;
508                 reg-io-width = <4>;               509                 reg-io-width = <4>;
509                 pinctrl-names = "default";        510                 pinctrl-names = "default";
510                 pinctrl-0 = <&uart1_xfer &uart    511                 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
511                 status = "disabled";              512                 status = "disabled";
512         };                                        513         };
513                                                   514 
514         uart2: serial@ff160000 {                  515         uart2: serial@ff160000 {
515                 compatible = "rockchip,px30-ua    516                 compatible = "rockchip,px30-uart", "snps,dw-apb-uart";
516                 reg = <0x0 0xff160000 0x0 0x10    517                 reg = <0x0 0xff160000 0x0 0x100>;
517                 interrupts = <GIC_SPI 17 IRQ_T    518                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
518                 clocks = <&cru SCLK_UART2>, <&    519                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
519                 clock-names = "baudclk", "apb_    520                 clock-names = "baudclk", "apb_pclk";
520                 dmas = <&dmac 4>, <&dmac 5>;      521                 dmas = <&dmac 4>, <&dmac 5>;
521                 dma-names = "tx", "rx";           522                 dma-names = "tx", "rx";
522                 reg-shift = <2>;                  523                 reg-shift = <2>;
523                 reg-io-width = <4>;               524                 reg-io-width = <4>;
524                 pinctrl-names = "default";        525                 pinctrl-names = "default";
525                 pinctrl-0 = <&uart2m0_xfer>;      526                 pinctrl-0 = <&uart2m0_xfer>;
526                 status = "disabled";              527                 status = "disabled";
527         };                                        528         };
528                                                   529 
529         uart3: serial@ff168000 {                  530         uart3: serial@ff168000 {
530                 compatible = "rockchip,px30-ua    531                 compatible = "rockchip,px30-uart", "snps,dw-apb-uart";
531                 reg = <0x0 0xff168000 0x0 0x10    532                 reg = <0x0 0xff168000 0x0 0x100>;
532                 interrupts = <GIC_SPI 18 IRQ_T    533                 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
533                 clocks = <&cru SCLK_UART3>, <&    534                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
534                 clock-names = "baudclk", "apb_    535                 clock-names = "baudclk", "apb_pclk";
535                 dmas = <&dmac 6>, <&dmac 7>;      536                 dmas = <&dmac 6>, <&dmac 7>;
536                 dma-names = "tx", "rx";           537                 dma-names = "tx", "rx";
537                 reg-shift = <2>;                  538                 reg-shift = <2>;
538                 reg-io-width = <4>;               539                 reg-io-width = <4>;
539                 pinctrl-names = "default";        540                 pinctrl-names = "default";
540                 pinctrl-0 = <&uart3m1_xfer &ua    541                 pinctrl-0 = <&uart3m1_xfer &uart3m1_cts &uart3m1_rts>;
541                 status = "disabled";              542                 status = "disabled";
542         };                                        543         };
543                                                   544 
544         uart4: serial@ff170000 {                  545         uart4: serial@ff170000 {
545                 compatible = "rockchip,px30-ua    546                 compatible = "rockchip,px30-uart", "snps,dw-apb-uart";
546                 reg = <0x0 0xff170000 0x0 0x10    547                 reg = <0x0 0xff170000 0x0 0x100>;
547                 interrupts = <GIC_SPI 19 IRQ_T    548                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
548                 clocks = <&cru SCLK_UART4>, <&    549                 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
549                 clock-names = "baudclk", "apb_    550                 clock-names = "baudclk", "apb_pclk";
550                 dmas = <&dmac 8>, <&dmac 9>;      551                 dmas = <&dmac 8>, <&dmac 9>;
551                 dma-names = "tx", "rx";           552                 dma-names = "tx", "rx";
552                 reg-shift = <2>;                  553                 reg-shift = <2>;
553                 reg-io-width = <4>;               554                 reg-io-width = <4>;
554                 pinctrl-names = "default";        555                 pinctrl-names = "default";
555                 pinctrl-0 = <&uart4_xfer &uart    556                 pinctrl-0 = <&uart4_xfer &uart4_cts &uart4_rts>;
556                 status = "disabled";              557                 status = "disabled";
557         };                                        558         };
558                                                   559 
559         uart5: serial@ff178000 {                  560         uart5: serial@ff178000 {
560                 compatible = "rockchip,px30-ua    561                 compatible = "rockchip,px30-uart", "snps,dw-apb-uart";
561                 reg = <0x0 0xff178000 0x0 0x10    562                 reg = <0x0 0xff178000 0x0 0x100>;
562                 interrupts = <GIC_SPI 20 IRQ_T    563                 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
563                 clocks = <&cru SCLK_UART5>, <&    564                 clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>;
564                 clock-names = "baudclk", "apb_    565                 clock-names = "baudclk", "apb_pclk";
565                 dmas = <&dmac 10>, <&dmac 11>;    566                 dmas = <&dmac 10>, <&dmac 11>;
566                 dma-names = "tx", "rx";           567                 dma-names = "tx", "rx";
567                 reg-shift = <2>;                  568                 reg-shift = <2>;
568                 reg-io-width = <4>;               569                 reg-io-width = <4>;
569                 pinctrl-names = "default";        570                 pinctrl-names = "default";
570                 pinctrl-0 = <&uart5_xfer &uart    571                 pinctrl-0 = <&uart5_xfer &uart5_cts &uart5_rts>;
571                 status = "disabled";              572                 status = "disabled";
572         };                                        573         };
573                                                   574 
574         i2c0: i2c@ff180000 {                      575         i2c0: i2c@ff180000 {
575                 compatible = "rockchip,px30-i2    576                 compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c";
576                 reg = <0x0 0xff180000 0x0 0x10    577                 reg = <0x0 0xff180000 0x0 0x1000>;
577                 clocks = <&cru SCLK_I2C0>, <&c    578                 clocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>;
578                 clock-names = "i2c", "pclk";      579                 clock-names = "i2c", "pclk";
579                 interrupts = <GIC_SPI 7 IRQ_TY    580                 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
580                 pinctrl-names = "default";        581                 pinctrl-names = "default";
581                 pinctrl-0 = <&i2c0_xfer>;         582                 pinctrl-0 = <&i2c0_xfer>;
582                 #address-cells = <1>;             583                 #address-cells = <1>;
583                 #size-cells = <0>;                584                 #size-cells = <0>;
584                 status = "disabled";              585                 status = "disabled";
585         };                                        586         };
586                                                   587 
587         i2c1: i2c@ff190000 {                      588         i2c1: i2c@ff190000 {
588                 compatible = "rockchip,px30-i2    589                 compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c";
589                 reg = <0x0 0xff190000 0x0 0x10    590                 reg = <0x0 0xff190000 0x0 0x1000>;
590                 clocks = <&cru SCLK_I2C1>, <&c    591                 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
591                 clock-names = "i2c", "pclk";      592                 clock-names = "i2c", "pclk";
592                 interrupts = <GIC_SPI 8 IRQ_TY    593                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
593                 pinctrl-names = "default";        594                 pinctrl-names = "default";
594                 pinctrl-0 = <&i2c1_xfer>;         595                 pinctrl-0 = <&i2c1_xfer>;
595                 #address-cells = <1>;             596                 #address-cells = <1>;
596                 #size-cells = <0>;                597                 #size-cells = <0>;
597                 status = "disabled";              598                 status = "disabled";
598         };                                        599         };
599                                                   600 
600         i2c2: i2c@ff1a0000 {                      601         i2c2: i2c@ff1a0000 {
601                 compatible = "rockchip,px30-i2    602                 compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c";
602                 reg = <0x0 0xff1a0000 0x0 0x10    603                 reg = <0x0 0xff1a0000 0x0 0x1000>;
603                 clocks = <&cru SCLK_I2C2>, <&c    604                 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
604                 clock-names = "i2c", "pclk";      605                 clock-names = "i2c", "pclk";
605                 interrupts = <GIC_SPI 9 IRQ_TY    606                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
606                 pinctrl-names = "default";        607                 pinctrl-names = "default";
607                 pinctrl-0 = <&i2c2_xfer>;         608                 pinctrl-0 = <&i2c2_xfer>;
608                 #address-cells = <1>;             609                 #address-cells = <1>;
609                 #size-cells = <0>;                610                 #size-cells = <0>;
610                 status = "disabled";              611                 status = "disabled";
611         };                                        612         };
612                                                   613 
613         i2c3: i2c@ff1b0000 {                      614         i2c3: i2c@ff1b0000 {
614                 compatible = "rockchip,px30-i2    615                 compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c";
615                 reg = <0x0 0xff1b0000 0x0 0x10    616                 reg = <0x0 0xff1b0000 0x0 0x1000>;
616                 clocks = <&cru SCLK_I2C3>, <&c    617                 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
617                 clock-names = "i2c", "pclk";      618                 clock-names = "i2c", "pclk";
618                 interrupts = <GIC_SPI 10 IRQ_T    619                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
619                 pinctrl-names = "default";        620                 pinctrl-names = "default";
620                 pinctrl-0 = <&i2c3_xfer>;         621                 pinctrl-0 = <&i2c3_xfer>;
621                 #address-cells = <1>;             622                 #address-cells = <1>;
622                 #size-cells = <0>;                623                 #size-cells = <0>;
623                 status = "disabled";              624                 status = "disabled";
624         };                                        625         };
625                                                   626 
626         spi0: spi@ff1d0000 {                      627         spi0: spi@ff1d0000 {
627                 compatible = "rockchip,px30-sp    628                 compatible = "rockchip,px30-spi", "rockchip,rk3066-spi";
628                 reg = <0x0 0xff1d0000 0x0 0x10    629                 reg = <0x0 0xff1d0000 0x0 0x1000>;
629                 interrupts = <GIC_SPI 26 IRQ_T    630                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
630                 clocks = <&cru SCLK_SPI0>, <&c    631                 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
631                 clock-names = "spiclk", "apb_p    632                 clock-names = "spiclk", "apb_pclk";
632                 dmas = <&dmac 12>, <&dmac 13>;    633                 dmas = <&dmac 12>, <&dmac 13>;
633                 dma-names = "tx", "rx";           634                 dma-names = "tx", "rx";
634                 num-cs = <2>;                  << 
635                 pinctrl-names = "default";        635                 pinctrl-names = "default";
636                 pinctrl-0 = <&spi0_clk &spi0_c    636                 pinctrl-0 = <&spi0_clk &spi0_csn &spi0_miso &spi0_mosi>;
637                 #address-cells = <1>;             637                 #address-cells = <1>;
638                 #size-cells = <0>;                638                 #size-cells = <0>;
639                 status = "disabled";              639                 status = "disabled";
640         };                                        640         };
641                                                   641 
642         spi1: spi@ff1d8000 {                      642         spi1: spi@ff1d8000 {
643                 compatible = "rockchip,px30-sp    643                 compatible = "rockchip,px30-spi", "rockchip,rk3066-spi";
644                 reg = <0x0 0xff1d8000 0x0 0x10    644                 reg = <0x0 0xff1d8000 0x0 0x1000>;
645                 interrupts = <GIC_SPI 27 IRQ_T    645                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
646                 clocks = <&cru SCLK_SPI1>, <&c    646                 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
647                 clock-names = "spiclk", "apb_p    647                 clock-names = "spiclk", "apb_pclk";
648                 dmas = <&dmac 14>, <&dmac 15>;    648                 dmas = <&dmac 14>, <&dmac 15>;
649                 dma-names = "tx", "rx";           649                 dma-names = "tx", "rx";
650                 num-cs = <2>;                  << 
651                 pinctrl-names = "default";        650                 pinctrl-names = "default";
652                 pinctrl-0 = <&spi1_clk &spi1_c    651                 pinctrl-0 = <&spi1_clk &spi1_csn0 &spi1_csn1 &spi1_miso &spi1_mosi>;
653                 #address-cells = <1>;             652                 #address-cells = <1>;
654                 #size-cells = <0>;                653                 #size-cells = <0>;
655                 status = "disabled";              654                 status = "disabled";
656         };                                        655         };
657                                                   656 
658         wdt: watchdog@ff1e0000 {                  657         wdt: watchdog@ff1e0000 {
659                 compatible = "rockchip,px30-wd    658                 compatible = "rockchip,px30-wdt", "snps,dw-wdt";
660                 reg = <0x0 0xff1e0000 0x0 0x10    659                 reg = <0x0 0xff1e0000 0x0 0x100>;
661                 clocks = <&cru PCLK_WDT_NS>;      660                 clocks = <&cru PCLK_WDT_NS>;
662                 interrupts = <GIC_SPI 37 IRQ_T    661                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
663                 status = "disabled";              662                 status = "disabled";
664         };                                        663         };
665                                                   664 
666         pwm0: pwm@ff200000 {                      665         pwm0: pwm@ff200000 {
667                 compatible = "rockchip,px30-pw    666                 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
668                 reg = <0x0 0xff200000 0x0 0x10    667                 reg = <0x0 0xff200000 0x0 0x10>;
669                 clocks = <&cru SCLK_PWM0>, <&c    668                 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
670                 clock-names = "pwm", "pclk";      669                 clock-names = "pwm", "pclk";
671                 pinctrl-names = "default";        670                 pinctrl-names = "default";
672                 pinctrl-0 = <&pwm0_pin>;          671                 pinctrl-0 = <&pwm0_pin>;
673                 #pwm-cells = <3>;                 672                 #pwm-cells = <3>;
674                 status = "disabled";              673                 status = "disabled";
675         };                                        674         };
676                                                   675 
677         pwm1: pwm@ff200010 {                      676         pwm1: pwm@ff200010 {
678                 compatible = "rockchip,px30-pw    677                 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
679                 reg = <0x0 0xff200010 0x0 0x10    678                 reg = <0x0 0xff200010 0x0 0x10>;
680                 clocks = <&cru SCLK_PWM0>, <&c    679                 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
681                 clock-names = "pwm", "pclk";      680                 clock-names = "pwm", "pclk";
682                 pinctrl-names = "default";        681                 pinctrl-names = "default";
683                 pinctrl-0 = <&pwm1_pin>;          682                 pinctrl-0 = <&pwm1_pin>;
684                 #pwm-cells = <3>;                 683                 #pwm-cells = <3>;
685                 status = "disabled";              684                 status = "disabled";
686         };                                        685         };
687                                                   686 
688         pwm2: pwm@ff200020 {                      687         pwm2: pwm@ff200020 {
689                 compatible = "rockchip,px30-pw    688                 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
690                 reg = <0x0 0xff200020 0x0 0x10    689                 reg = <0x0 0xff200020 0x0 0x10>;
691                 clocks = <&cru SCLK_PWM0>, <&c    690                 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
692                 clock-names = "pwm", "pclk";      691                 clock-names = "pwm", "pclk";
693                 pinctrl-names = "default";        692                 pinctrl-names = "default";
694                 pinctrl-0 = <&pwm2_pin>;          693                 pinctrl-0 = <&pwm2_pin>;
695                 #pwm-cells = <3>;                 694                 #pwm-cells = <3>;
696                 status = "disabled";              695                 status = "disabled";
697         };                                        696         };
698                                                   697 
699         pwm3: pwm@ff200030 {                      698         pwm3: pwm@ff200030 {
700                 compatible = "rockchip,px30-pw    699                 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
701                 reg = <0x0 0xff200030 0x0 0x10    700                 reg = <0x0 0xff200030 0x0 0x10>;
702                 clocks = <&cru SCLK_PWM0>, <&c    701                 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
703                 clock-names = "pwm", "pclk";      702                 clock-names = "pwm", "pclk";
704                 pinctrl-names = "default";        703                 pinctrl-names = "default";
705                 pinctrl-0 = <&pwm3_pin>;          704                 pinctrl-0 = <&pwm3_pin>;
706                 #pwm-cells = <3>;                 705                 #pwm-cells = <3>;
707                 status = "disabled";              706                 status = "disabled";
708         };                                        707         };
709                                                   708 
710         pwm4: pwm@ff208000 {                      709         pwm4: pwm@ff208000 {
711                 compatible = "rockchip,px30-pw    710                 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
712                 reg = <0x0 0xff208000 0x0 0x10    711                 reg = <0x0 0xff208000 0x0 0x10>;
713                 clocks = <&cru SCLK_PWM1>, <&c    712                 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>;
714                 clock-names = "pwm", "pclk";      713                 clock-names = "pwm", "pclk";
715                 pinctrl-names = "default";        714                 pinctrl-names = "default";
716                 pinctrl-0 = <&pwm4_pin>;          715                 pinctrl-0 = <&pwm4_pin>;
717                 #pwm-cells = <3>;                 716                 #pwm-cells = <3>;
718                 status = "disabled";              717                 status = "disabled";
719         };                                        718         };
720                                                   719 
721         pwm5: pwm@ff208010 {                      720         pwm5: pwm@ff208010 {
722                 compatible = "rockchip,px30-pw    721                 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
723                 reg = <0x0 0xff208010 0x0 0x10    722                 reg = <0x0 0xff208010 0x0 0x10>;
724                 clocks = <&cru SCLK_PWM1>, <&c    723                 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>;
725                 clock-names = "pwm", "pclk";      724                 clock-names = "pwm", "pclk";
726                 pinctrl-names = "default";        725                 pinctrl-names = "default";
727                 pinctrl-0 = <&pwm5_pin>;          726                 pinctrl-0 = <&pwm5_pin>;
728                 #pwm-cells = <3>;                 727                 #pwm-cells = <3>;
729                 status = "disabled";              728                 status = "disabled";
730         };                                        729         };
731                                                   730 
732         pwm6: pwm@ff208020 {                      731         pwm6: pwm@ff208020 {
733                 compatible = "rockchip,px30-pw    732                 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
734                 reg = <0x0 0xff208020 0x0 0x10    733                 reg = <0x0 0xff208020 0x0 0x10>;
735                 clocks = <&cru SCLK_PWM1>, <&c    734                 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>;
736                 clock-names = "pwm", "pclk";      735                 clock-names = "pwm", "pclk";
737                 pinctrl-names = "default";        736                 pinctrl-names = "default";
738                 pinctrl-0 = <&pwm6_pin>;          737                 pinctrl-0 = <&pwm6_pin>;
739                 #pwm-cells = <3>;                 738                 #pwm-cells = <3>;
740                 status = "disabled";              739                 status = "disabled";
741         };                                        740         };
742                                                   741 
743         pwm7: pwm@ff208030 {                      742         pwm7: pwm@ff208030 {
744                 compatible = "rockchip,px30-pw    743                 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm";
745                 reg = <0x0 0xff208030 0x0 0x10    744                 reg = <0x0 0xff208030 0x0 0x10>;
746                 clocks = <&cru SCLK_PWM1>, <&c    745                 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>;
747                 clock-names = "pwm", "pclk";      746                 clock-names = "pwm", "pclk";
748                 pinctrl-names = "default";        747                 pinctrl-names = "default";
749                 pinctrl-0 = <&pwm7_pin>;          748                 pinctrl-0 = <&pwm7_pin>;
750                 #pwm-cells = <3>;                 749                 #pwm-cells = <3>;
751                 status = "disabled";              750                 status = "disabled";
752         };                                        751         };
753                                                   752 
754         rktimer: timer@ff210000 {                 753         rktimer: timer@ff210000 {
755                 compatible = "rockchip,px30-ti    754                 compatible = "rockchip,px30-timer", "rockchip,rk3288-timer";
756                 reg = <0x0 0xff210000 0x0 0x10    755                 reg = <0x0 0xff210000 0x0 0x1000>;
757                 interrupts = <GIC_SPI 30 IRQ_T    756                 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
758                 clocks = <&cru PCLK_TIMER>, <&    757                 clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER0>;
759                 clock-names = "pclk", "timer";    758                 clock-names = "pclk", "timer";
760         };                                        759         };
761                                                   760 
762         dmac: dma-controller@ff240000 {           761         dmac: dma-controller@ff240000 {
763                 compatible = "arm,pl330", "arm    762                 compatible = "arm,pl330", "arm,primecell";
764                 reg = <0x0 0xff240000 0x0 0x40    763                 reg = <0x0 0xff240000 0x0 0x4000>;
765                 interrupts = <GIC_SPI 1 IRQ_TY    764                 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
766                              <GIC_SPI 2 IRQ_TY    765                              <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
767                 arm,pl330-periph-burst;           766                 arm,pl330-periph-burst;
768                 clocks = <&cru ACLK_DMAC>;        767                 clocks = <&cru ACLK_DMAC>;
769                 clock-names = "apb_pclk";         768                 clock-names = "apb_pclk";
770                 #dma-cells = <1>;                 769                 #dma-cells = <1>;
771         };                                        770         };
772                                                   771 
773         tsadc: tsadc@ff280000 {                   772         tsadc: tsadc@ff280000 {
774                 compatible = "rockchip,px30-ts    773                 compatible = "rockchip,px30-tsadc";
775                 reg = <0x0 0xff280000 0x0 0x10    774                 reg = <0x0 0xff280000 0x0 0x100>;
776                 interrupts = <GIC_SPI 36 IRQ_T    775                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
777                 assigned-clocks = <&cru SCLK_T    776                 assigned-clocks = <&cru SCLK_TSADC>;
778                 assigned-clock-rates = <50000>    777                 assigned-clock-rates = <50000>;
779                 clocks = <&cru SCLK_TSADC>, <&    778                 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
780                 clock-names = "tsadc", "apb_pc    779                 clock-names = "tsadc", "apb_pclk";
781                 resets = <&cru SRST_TSADC>;       780                 resets = <&cru SRST_TSADC>;
782                 reset-names = "tsadc-apb";        781                 reset-names = "tsadc-apb";
783                 rockchip,grf = <&grf>;            782                 rockchip,grf = <&grf>;
784                 rockchip,hw-tshut-temp = <1200    783                 rockchip,hw-tshut-temp = <120000>;
785                 pinctrl-names = "init", "defau    784                 pinctrl-names = "init", "default", "sleep";
786                 pinctrl-0 = <&tsadc_otp_pin>;     785                 pinctrl-0 = <&tsadc_otp_pin>;
787                 pinctrl-1 = <&tsadc_otp_out>;     786                 pinctrl-1 = <&tsadc_otp_out>;
788                 pinctrl-2 = <&tsadc_otp_pin>;     787                 pinctrl-2 = <&tsadc_otp_pin>;
789                 #thermal-sensor-cells = <1>;      788                 #thermal-sensor-cells = <1>;
790                 status = "disabled";              789                 status = "disabled";
791         };                                        790         };
792                                                   791 
793         saradc: saradc@ff288000 {                 792         saradc: saradc@ff288000 {
794                 compatible = "rockchip,px30-sa    793                 compatible = "rockchip,px30-saradc", "rockchip,rk3399-saradc";
795                 reg = <0x0 0xff288000 0x0 0x10    794                 reg = <0x0 0xff288000 0x0 0x100>;
796                 interrupts = <GIC_SPI 84 IRQ_T    795                 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
797                 #io-channel-cells = <1>;          796                 #io-channel-cells = <1>;
798                 clocks = <&cru SCLK_SARADC>, <    797                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
799                 clock-names = "saradc", "apb_p    798                 clock-names = "saradc", "apb_pclk";
800                 resets = <&cru SRST_SARADC_P>;    799                 resets = <&cru SRST_SARADC_P>;
801                 reset-names = "saradc-apb";       800                 reset-names = "saradc-apb";
802                 status = "disabled";              801                 status = "disabled";
803         };                                        802         };
804                                                   803 
805         otp: nvmem@ff290000 {                     804         otp: nvmem@ff290000 {
806                 compatible = "rockchip,px30-ot    805                 compatible = "rockchip,px30-otp";
807                 reg = <0x0 0xff290000 0x0 0x40    806                 reg = <0x0 0xff290000 0x0 0x4000>;
808                 clocks = <&cru SCLK_OTP_USR>,     807                 clocks = <&cru SCLK_OTP_USR>, <&cru PCLK_OTP_NS>,
809                          <&cru PCLK_OTP_PHY>;     808                          <&cru PCLK_OTP_PHY>;
810                 clock-names = "otp", "apb_pclk    809                 clock-names = "otp", "apb_pclk", "phy";
811                 resets = <&cru SRST_OTP_PHY>;     810                 resets = <&cru SRST_OTP_PHY>;
812                 reset-names = "phy";              811                 reset-names = "phy";
813                 #address-cells = <1>;             812                 #address-cells = <1>;
814                 #size-cells = <1>;                813                 #size-cells = <1>;
815                                                   814 
816                 /* Data cells */                  815                 /* Data cells */
817                 cpu_id: id@7 {                    816                 cpu_id: id@7 {
818                         reg = <0x07 0x10>;        817                         reg = <0x07 0x10>;
819                 };                                818                 };
820                 cpu_leakage: cpu-leakage@17 {     819                 cpu_leakage: cpu-leakage@17 {
821                         reg = <0x17 0x1>;         820                         reg = <0x17 0x1>;
822                 };                                821                 };
823                 performance: performance@1e {     822                 performance: performance@1e {
824                         reg = <0x1e 0x1>;         823                         reg = <0x1e 0x1>;
825                         bits = <4 3>;             824                         bits = <4 3>;
826                 };                                825                 };
827         };                                        826         };
828                                                   827 
829         cru: clock-controller@ff2b0000 {          828         cru: clock-controller@ff2b0000 {
830                 compatible = "rockchip,px30-cr    829                 compatible = "rockchip,px30-cru";
831                 reg = <0x0 0xff2b0000 0x0 0x10    830                 reg = <0x0 0xff2b0000 0x0 0x1000>;
832                 clocks = <&xin24m>, <&pmucru P    831                 clocks = <&xin24m>, <&pmucru PLL_GPLL>;
833                 clock-names = "xin24m", "gpll"    832                 clock-names = "xin24m", "gpll";
834                 rockchip,grf = <&grf>;            833                 rockchip,grf = <&grf>;
835                 #clock-cells = <1>;               834                 #clock-cells = <1>;
836                 #reset-cells = <1>;               835                 #reset-cells = <1>;
837                                                   836 
838                 assigned-clocks = <&cru PLL_NP    837                 assigned-clocks = <&cru PLL_NPLL>,
839                         <&cru ACLK_BUS_PRE>, <    838                         <&cru ACLK_BUS_PRE>, <&cru ACLK_PERI_PRE>,
840                         <&cru HCLK_BUS_PRE>, <    839                         <&cru HCLK_BUS_PRE>, <&cru HCLK_PERI_PRE>,
841                         <&cru PCLK_BUS_PRE>, <    840                         <&cru PCLK_BUS_PRE>, <&cru SCLK_GPU>;
842                                                   841 
843                 assigned-clock-rates = <118800    842                 assigned-clock-rates = <1188000000>,
844                         <200000000>, <20000000    843                         <200000000>, <200000000>,
845                         <150000000>, <15000000    844                         <150000000>, <150000000>,
846                         <100000000>, <20000000    845                         <100000000>, <200000000>;
847         };                                        846         };
848                                                   847 
849         pmucru: clock-controller@ff2bc000 {       848         pmucru: clock-controller@ff2bc000 {
850                 compatible = "rockchip,px30-pm    849                 compatible = "rockchip,px30-pmucru";
851                 reg = <0x0 0xff2bc000 0x0 0x10    850                 reg = <0x0 0xff2bc000 0x0 0x1000>;
852                 clocks = <&xin24m>;               851                 clocks = <&xin24m>;
853                 clock-names = "xin24m";           852                 clock-names = "xin24m";
854                 rockchip,grf = <&grf>;            853                 rockchip,grf = <&grf>;
855                 #clock-cells = <1>;               854                 #clock-cells = <1>;
856                 #reset-cells = <1>;               855                 #reset-cells = <1>;
857                                                   856 
858                 assigned-clocks =                 857                 assigned-clocks =
859                         <&pmucru PLL_GPLL>, <&    858                         <&pmucru PLL_GPLL>, <&pmucru PCLK_PMU_PRE>,
860                         <&pmucru SCLK_WIFI_PMU    859                         <&pmucru SCLK_WIFI_PMU>;
861                 assigned-clock-rates =            860                 assigned-clock-rates =
862                         <1200000000>, <1000000    861                         <1200000000>, <100000000>,
863                         <26000000>;               862                         <26000000>;
864         };                                        863         };
865                                                   864 
866         usb2phy_grf: syscon@ff2c0000 {            865         usb2phy_grf: syscon@ff2c0000 {
867                 compatible = "rockchip,px30-us    866                 compatible = "rockchip,px30-usb2phy-grf", "syscon",
868                              "simple-mfd";        867                              "simple-mfd";
869                 reg = <0x0 0xff2c0000 0x0 0x10    868                 reg = <0x0 0xff2c0000 0x0 0x10000>;
870                 #address-cells = <1>;             869                 #address-cells = <1>;
871                 #size-cells = <1>;                870                 #size-cells = <1>;
872                                                   871 
873                 u2phy: usb2phy@100 {              872                 u2phy: usb2phy@100 {
874                         compatible = "rockchip    873                         compatible = "rockchip,px30-usb2phy";
875                         reg = <0x100 0x20>;       874                         reg = <0x100 0x20>;
876                         clocks = <&pmucru SCLK    875                         clocks = <&pmucru SCLK_USBPHY_REF>;
877                         clock-names = "phyclk"    876                         clock-names = "phyclk";
878                         #clock-cells = <0>;       877                         #clock-cells = <0>;
879                         assigned-clocks = <&cr    878                         assigned-clocks = <&cru USB480M>;
880                         assigned-clock-parents    879                         assigned-clock-parents = <&u2phy>;
881                         clock-output-names = "    880                         clock-output-names = "usb480m_phy";
882                         status = "disabled";      881                         status = "disabled";
883                                                   882 
884                         u2phy_host: host-port     883                         u2phy_host: host-port {
885                                 #phy-cells = <    884                                 #phy-cells = <0>;
886                                 interrupts = <    885                                 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
887                                 interrupt-name    886                                 interrupt-names = "linestate";
888                                 status = "disa    887                                 status = "disabled";
889                         };                        888                         };
890                                                   889 
891                         u2phy_otg: otg-port {     890                         u2phy_otg: otg-port {
892                                 #phy-cells = <    891                                 #phy-cells = <0>;
893                                 interrupts = <    892                                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
894                                              <    893                                              <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
895                                              <    894                                              <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
896                                 interrupt-name    895                                 interrupt-names = "otg-bvalid", "otg-id",
897                                                   896                                                   "linestate";
898                                 status = "disa    897                                 status = "disabled";
899                         };                        898                         };
900                 };                                899                 };
901         };                                        900         };
902                                                   901 
903         dsi_dphy: phy@ff2e0000 {                  902         dsi_dphy: phy@ff2e0000 {
904                 compatible = "rockchip,px30-ds    903                 compatible = "rockchip,px30-dsi-dphy";
905                 reg = <0x0 0xff2e0000 0x0 0x10    904                 reg = <0x0 0xff2e0000 0x0 0x10000>;
906                 clocks = <&pmucru SCLK_MIPIDSI    905                 clocks = <&pmucru SCLK_MIPIDSIPHY_REF>, <&cru PCLK_MIPIDSIPHY>;
907                 clock-names = "ref", "pclk";      906                 clock-names = "ref", "pclk";
908                 resets = <&cru SRST_MIPIDSIPHY    907                 resets = <&cru SRST_MIPIDSIPHY_P>;
909                 reset-names = "apb";              908                 reset-names = "apb";
910                 #phy-cells = <0>;                 909                 #phy-cells = <0>;
911                 power-domains = <&power PX30_P    910                 power-domains = <&power PX30_PD_VO>;
912                 status = "disabled";              911                 status = "disabled";
913         };                                        912         };
914                                                   913 
915         csi_dphy: phy@ff2f0000 {                  914         csi_dphy: phy@ff2f0000 {
916                 compatible = "rockchip,px30-cs    915                 compatible = "rockchip,px30-csi-dphy";
917                 reg = <0x0 0xff2f0000 0x0 0x40    916                 reg = <0x0 0xff2f0000 0x0 0x4000>;
918                 clocks = <&cru PCLK_MIPICSIPHY    917                 clocks = <&cru PCLK_MIPICSIPHY>;
919                 clock-names = "pclk";             918                 clock-names = "pclk";
920                 #phy-cells = <0>;                 919                 #phy-cells = <0>;
921                 power-domains = <&power PX30_P    920                 power-domains = <&power PX30_PD_VI>;
922                 resets = <&cru SRST_MIPICSIPHY    921                 resets = <&cru SRST_MIPICSIPHY_P>;
923                 reset-names = "apb";              922                 reset-names = "apb";
924                 rockchip,grf = <&grf>;            923                 rockchip,grf = <&grf>;
925                 status = "disabled";              924                 status = "disabled";
926         };                                        925         };
927                                                   926 
928         usb20_otg: usb@ff300000 {                 927         usb20_otg: usb@ff300000 {
929                 compatible = "rockchip,px30-us    928                 compatible = "rockchip,px30-usb", "rockchip,rk3066-usb",
930                              "snps,dwc2";         929                              "snps,dwc2";
931                 reg = <0x0 0xff300000 0x0 0x40    930                 reg = <0x0 0xff300000 0x0 0x40000>;
932                 interrupts = <GIC_SPI 62 IRQ_T    931                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
933                 clocks = <&cru HCLK_OTG>;         932                 clocks = <&cru HCLK_OTG>;
934                 clock-names = "otg";              933                 clock-names = "otg";
935                 dr_mode = "otg";                  934                 dr_mode = "otg";
936                 g-np-tx-fifo-size = <16>;         935                 g-np-tx-fifo-size = <16>;
937                 g-rx-fifo-size = <280>;           936                 g-rx-fifo-size = <280>;
938                 g-tx-fifo-size = <256 128 128     937                 g-tx-fifo-size = <256 128 128 64 32 16>;
939                 phys = <&u2phy_otg>;              938                 phys = <&u2phy_otg>;
940                 phy-names = "usb2-phy";           939                 phy-names = "usb2-phy";
941                 power-domains = <&power PX30_P    940                 power-domains = <&power PX30_PD_USB>;
942                 status = "disabled";              941                 status = "disabled";
943         };                                        942         };
944                                                   943 
945         usb_host0_ehci: usb@ff340000 {            944         usb_host0_ehci: usb@ff340000 {
946                 compatible = "generic-ehci";      945                 compatible = "generic-ehci";
947                 reg = <0x0 0xff340000 0x0 0x10    946                 reg = <0x0 0xff340000 0x0 0x10000>;
948                 interrupts = <GIC_SPI 60 IRQ_T    947                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
949                 clocks = <&cru HCLK_HOST>;        948                 clocks = <&cru HCLK_HOST>;
950                 phys = <&u2phy_host>;             949                 phys = <&u2phy_host>;
951                 phy-names = "usb";                950                 phy-names = "usb";
952                 power-domains = <&power PX30_P    951                 power-domains = <&power PX30_PD_USB>;
953                 status = "disabled";              952                 status = "disabled";
954         };                                        953         };
955                                                   954 
956         usb_host0_ohci: usb@ff350000 {            955         usb_host0_ohci: usb@ff350000 {
957                 compatible = "generic-ohci";      956                 compatible = "generic-ohci";
958                 reg = <0x0 0xff350000 0x0 0x10    957                 reg = <0x0 0xff350000 0x0 0x10000>;
959                 interrupts = <GIC_SPI 61 IRQ_T    958                 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
960                 clocks = <&cru HCLK_HOST>;        959                 clocks = <&cru HCLK_HOST>;
961                 phys = <&u2phy_host>;             960                 phys = <&u2phy_host>;
962                 phy-names = "usb";                961                 phy-names = "usb";
963                 power-domains = <&power PX30_P    962                 power-domains = <&power PX30_PD_USB>;
964                 status = "disabled";              963                 status = "disabled";
965         };                                        964         };
966                                                   965 
967         gmac: ethernet@ff360000 {                 966         gmac: ethernet@ff360000 {
968                 compatible = "rockchip,px30-gm    967                 compatible = "rockchip,px30-gmac";
969                 reg = <0x0 0xff360000 0x0 0x10    968                 reg = <0x0 0xff360000 0x0 0x10000>;
970                 interrupts = <GIC_SPI 43 IRQ_T    969                 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
971                 interrupt-names = "macirq";       970                 interrupt-names = "macirq";
972                 clocks = <&cru SCLK_GMAC>, <&c    971                 clocks = <&cru SCLK_GMAC>, <&cru SCLK_GMAC_RX_TX>,
973                          <&cru SCLK_GMAC_RX_TX    972                          <&cru SCLK_GMAC_RX_TX>, <&cru SCLK_MAC_REF>,
974                          <&cru SCLK_MAC_REFOUT    973                          <&cru SCLK_MAC_REFOUT>, <&cru ACLK_GMAC>,
975                          <&cru PCLK_GMAC>, <&c    974                          <&cru PCLK_GMAC>, <&cru SCLK_GMAC_RMII>;
976                 clock-names = "stmmaceth", "ma    975                 clock-names = "stmmaceth", "mac_clk_rx",
977                               "mac_clk_tx", "c    976                               "mac_clk_tx", "clk_mac_ref",
978                               "clk_mac_refout"    977                               "clk_mac_refout", "aclk_mac",
979                               "pclk_mac", "clk    978                               "pclk_mac", "clk_mac_speed";
980                 rockchip,grf = <&grf>;            979                 rockchip,grf = <&grf>;
981                 phy-mode = "rmii";                980                 phy-mode = "rmii";
982                 pinctrl-names = "default";        981                 pinctrl-names = "default";
983                 pinctrl-0 = <&rmii_pins &mac_r    982                 pinctrl-0 = <&rmii_pins &mac_refclk_12ma>;
984                 power-domains = <&power PX30_P    983                 power-domains = <&power PX30_PD_GMAC>;
985                 resets = <&cru SRST_GMAC_A>;      984                 resets = <&cru SRST_GMAC_A>;
986                 reset-names = "stmmaceth";        985                 reset-names = "stmmaceth";
987                 status = "disabled";              986                 status = "disabled";
988         };                                        987         };
989                                                   988 
990         sdmmc: mmc@ff370000 {                     989         sdmmc: mmc@ff370000 {
991                 compatible = "rockchip,px30-dw    990                 compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc";
992                 reg = <0x0 0xff370000 0x0 0x40    991                 reg = <0x0 0xff370000 0x0 0x4000>;
993                 interrupts = <GIC_SPI 54 IRQ_T    992                 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
994                 clocks = <&cru HCLK_SDMMC>, <&    993                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
995                          <&cru SCLK_SDMMC_DRV>    994                          <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
996                 clock-names = "biu", "ciu", "c    995                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
997                 bus-width = <4>;                  996                 bus-width = <4>;
998                 fifo-depth = <0x100>;             997                 fifo-depth = <0x100>;
999                 max-frequency = <150000000>;      998                 max-frequency = <150000000>;
1000                 pinctrl-names = "default";       999                 pinctrl-names = "default";
1001                 pinctrl-0 = <&sdmmc_clk &sdmm    1000                 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_det &sdmmc_bus4>;
1002                 power-domains = <&power PX30_    1001                 power-domains = <&power PX30_PD_SDCARD>;
1003                 status = "disabled";             1002                 status = "disabled";
1004         };                                       1003         };
1005                                                  1004 
1006         sdio: mmc@ff380000 {                     1005         sdio: mmc@ff380000 {
1007                 compatible = "rockchip,px30-d    1006                 compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc";
1008                 reg = <0x0 0xff380000 0x0 0x4    1007                 reg = <0x0 0xff380000 0x0 0x4000>;
1009                 interrupts = <GIC_SPI 55 IRQ_    1008                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
1010                 clocks = <&cru HCLK_SDIO>, <&    1009                 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
1011                          <&cru SCLK_SDIO_DRV>    1010                          <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
1012                 clock-names = "biu", "ciu", "    1011                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
1013                 bus-width = <4>;                 1012                 bus-width = <4>;
1014                 fifo-depth = <0x100>;            1013                 fifo-depth = <0x100>;
1015                 max-frequency = <150000000>;     1014                 max-frequency = <150000000>;
1016                 pinctrl-names = "default";       1015                 pinctrl-names = "default";
1017                 pinctrl-0 = <&sdio_bus4 &sdio    1016                 pinctrl-0 = <&sdio_bus4 &sdio_cmd &sdio_clk>;
1018                 power-domains = <&power PX30_    1017                 power-domains = <&power PX30_PD_MMC_NAND>;
1019                 status = "disabled";             1018                 status = "disabled";
1020         };                                       1019         };
1021                                                  1020 
1022         emmc: mmc@ff390000 {                     1021         emmc: mmc@ff390000 {
1023                 compatible = "rockchip,px30-d    1022                 compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc";
1024                 reg = <0x0 0xff390000 0x0 0x4    1023                 reg = <0x0 0xff390000 0x0 0x4000>;
1025                 interrupts = <GIC_SPI 53 IRQ_    1024                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
1026                 clocks = <&cru HCLK_EMMC>, <&    1025                 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
1027                          <&cru SCLK_EMMC_DRV>    1026                          <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
1028                 clock-names = "biu", "ciu", "    1027                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
1029                 bus-width = <8>;                 1028                 bus-width = <8>;
1030                 fifo-depth = <0x100>;            1029                 fifo-depth = <0x100>;
1031                 max-frequency = <150000000>;     1030                 max-frequency = <150000000>;
1032                 pinctrl-names = "default";       1031                 pinctrl-names = "default";
1033                 pinctrl-0 = <&emmc_clk &emmc_    1032                 pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
1034                 power-domains = <&power PX30_    1033                 power-domains = <&power PX30_PD_MMC_NAND>;
1035                 status = "disabled";             1034                 status = "disabled";
1036         };                                       1035         };
1037                                                  1036 
1038         sfc: spi@ff3a0000 {                      1037         sfc: spi@ff3a0000 {
1039                 compatible = "rockchip,sfc";     1038                 compatible = "rockchip,sfc";
1040                 reg = <0x0 0xff3a0000 0x0 0x4    1039                 reg = <0x0 0xff3a0000 0x0 0x4000>;
1041                 interrupts = <GIC_SPI 56 IRQ_    1040                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
1042                 clocks = <&cru SCLK_SFC>, <&c    1041                 clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>;
1043                 clock-names = "clk_sfc", "hcl    1042                 clock-names = "clk_sfc", "hclk_sfc";
1044                 pinctrl-0 = <&sfc_clk &sfc_cs    1043                 pinctrl-0 = <&sfc_clk &sfc_cs0 &sfc_bus4>;
1045                 pinctrl-names = "default";       1044                 pinctrl-names = "default";
1046                 power-domains = <&power PX30_    1045                 power-domains = <&power PX30_PD_MMC_NAND>;
1047                 status = "disabled";             1046                 status = "disabled";
1048         };                                       1047         };
1049                                                  1048 
1050         nfc: nand-controller@ff3b0000 {          1049         nfc: nand-controller@ff3b0000 {
1051                 compatible = "rockchip,px30-n    1050                 compatible = "rockchip,px30-nfc";
1052                 reg = <0x0 0xff3b0000 0x0 0x4    1051                 reg = <0x0 0xff3b0000 0x0 0x4000>;
1053                 interrupts = <GIC_SPI 57 IRQ_    1052                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
1054                 clocks = <&cru HCLK_NANDC>, <    1053                 clocks = <&cru HCLK_NANDC>, <&cru SCLK_NANDC>;
1055                 clock-names = "ahb", "nfc";      1054                 clock-names = "ahb", "nfc";
1056                 assigned-clocks = <&cru SCLK_    1055                 assigned-clocks = <&cru SCLK_NANDC>;
1057                 assigned-clock-rates = <15000    1056                 assigned-clock-rates = <150000000>;
1058                 pinctrl-names = "default";       1057                 pinctrl-names = "default";
1059                 pinctrl-0 = <&flash_ale &flas    1058                 pinctrl-0 = <&flash_ale &flash_bus8 &flash_cle &flash_cs0
1060                              &flash_rdn &flas    1059                              &flash_rdn &flash_rdy &flash_wrn &flash_dqs>;
1061                 power-domains = <&power PX30_    1060                 power-domains = <&power PX30_PD_MMC_NAND>;
1062                 status = "disabled";             1061                 status = "disabled";
1063         };                                       1062         };
1064                                                  1063 
1065         gpu_opp_table: opp-table-1 {             1064         gpu_opp_table: opp-table-1 {
1066                 compatible = "operating-point    1065                 compatible = "operating-points-v2";
1067                                                  1066 
1068                 opp-200000000 {                  1067                 opp-200000000 {
1069                         opp-hz = /bits/ 64 <2    1068                         opp-hz = /bits/ 64 <200000000>;
1070                         opp-microvolt = <9500    1069                         opp-microvolt = <950000>;
1071                 };                               1070                 };
1072                 opp-300000000 {                  1071                 opp-300000000 {
1073                         opp-hz = /bits/ 64 <3    1072                         opp-hz = /bits/ 64 <300000000>;
1074                         opp-microvolt = <9750    1073                         opp-microvolt = <975000>;
1075                 };                               1074                 };
1076                 opp-400000000 {                  1075                 opp-400000000 {
1077                         opp-hz = /bits/ 64 <4    1076                         opp-hz = /bits/ 64 <400000000>;
1078                         opp-microvolt = <1050    1077                         opp-microvolt = <1050000>;
1079                 };                               1078                 };
1080                 opp-480000000 {                  1079                 opp-480000000 {
1081                         opp-hz = /bits/ 64 <4    1080                         opp-hz = /bits/ 64 <480000000>;
1082                         opp-microvolt = <1125    1081                         opp-microvolt = <1125000>;
1083                 };                               1082                 };
1084         };                                       1083         };
1085                                                  1084 
1086         gpu: gpu@ff400000 {                      1085         gpu: gpu@ff400000 {
1087                 compatible = "rockchip,px30-m    1086                 compatible = "rockchip,px30-mali", "arm,mali-bifrost";
1088                 reg = <0x0 0xff400000 0x0 0x4    1087                 reg = <0x0 0xff400000 0x0 0x4000>;
1089                 interrupts = <GIC_SPI 47 IRQ_    1088                 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
1090                              <GIC_SPI 46 IRQ_    1089                              <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
1091                              <GIC_SPI 45 IRQ_    1090                              <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
1092                 interrupt-names = "job", "mmu    1091                 interrupt-names = "job", "mmu", "gpu";
1093                 clocks = <&cru SCLK_GPU>;        1092                 clocks = <&cru SCLK_GPU>;
1094                 #cooling-cells = <2>;            1093                 #cooling-cells = <2>;
1095                 power-domains = <&power PX30_    1094                 power-domains = <&power PX30_PD_GPU>;
1096                 operating-points-v2 = <&gpu_o    1095                 operating-points-v2 = <&gpu_opp_table>;
1097                 status = "disabled";             1096                 status = "disabled";
1098         };                                       1097         };
1099                                                  1098 
1100         vpu: video-codec@ff442000 {              1099         vpu: video-codec@ff442000 {
1101                 compatible = "rockchip,px30-v    1100                 compatible = "rockchip,px30-vpu";
1102                 reg = <0x0 0xff442000 0x0 0x8    1101                 reg = <0x0 0xff442000 0x0 0x800>;
1103                 interrupts = <GIC_SPI 80 IRQ_    1102                 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
1104                              <GIC_SPI 79 IRQ_    1103                              <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
1105                 interrupt-names = "vepu", "vd    1104                 interrupt-names = "vepu", "vdpu";
1106                 clocks = <&cru ACLK_VPU>, <&c    1105                 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
1107                 clock-names = "aclk", "hclk";    1106                 clock-names = "aclk", "hclk";
1108                 iommus = <&vpu_mmu>;             1107                 iommus = <&vpu_mmu>;
1109                 power-domains = <&power PX30_    1108                 power-domains = <&power PX30_PD_VPU>;
1110         };                                       1109         };
1111                                                  1110 
1112         vpu_mmu: iommu@ff442800 {                1111         vpu_mmu: iommu@ff442800 {
1113                 compatible = "rockchip,iommu"    1112                 compatible = "rockchip,iommu";
1114                 reg = <0x0 0xff442800 0x0 0x1    1113                 reg = <0x0 0xff442800 0x0 0x100>;
1115                 interrupts = <GIC_SPI 81 IRQ_    1114                 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
1116                 clocks = <&cru ACLK_VPU>, <&c    1115                 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
1117                 clock-names = "aclk", "iface"    1116                 clock-names = "aclk", "iface";
1118                 #iommu-cells = <0>;              1117                 #iommu-cells = <0>;
1119                 power-domains = <&power PX30_    1118                 power-domains = <&power PX30_PD_VPU>;
1120         };                                       1119         };
1121                                                  1120 
1122         dsi: dsi@ff450000 {                      1121         dsi: dsi@ff450000 {
1123                 compatible = "rockchip,px30-m    1122                 compatible = "rockchip,px30-mipi-dsi", "snps,dw-mipi-dsi";
1124                 reg = <0x0 0xff450000 0x0 0x1    1123                 reg = <0x0 0xff450000 0x0 0x10000>;
1125                 interrupts = <GIC_SPI 75 IRQ_    1124                 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
1126                 clocks = <&cru PCLK_MIPI_DSI>    1125                 clocks = <&cru PCLK_MIPI_DSI>;
1127                 clock-names = "pclk";            1126                 clock-names = "pclk";
1128                 phys = <&dsi_dphy>;              1127                 phys = <&dsi_dphy>;
1129                 phy-names = "dphy";              1128                 phy-names = "dphy";
1130                 power-domains = <&power PX30_    1129                 power-domains = <&power PX30_PD_VO>;
1131                 resets = <&cru SRST_MIPIDSI_H    1130                 resets = <&cru SRST_MIPIDSI_HOST_P>;
1132                 reset-names = "apb";             1131                 reset-names = "apb";
1133                 rockchip,grf = <&grf>;           1132                 rockchip,grf = <&grf>;
1134                 #address-cells = <1>;            1133                 #address-cells = <1>;
1135                 #size-cells = <0>;               1134                 #size-cells = <0>;
1136                 status = "disabled";             1135                 status = "disabled";
1137                                                  1136 
1138                 ports {                          1137                 ports {
1139                         #address-cells = <1>;    1138                         #address-cells = <1>;
1140                         #size-cells = <0>;       1139                         #size-cells = <0>;
1141                                                  1140 
1142                         dsi_in: port@0 {         1141                         dsi_in: port@0 {
1143                                 reg = <0>;       1142                                 reg = <0>;
1144                                 #address-cell    1143                                 #address-cells = <1>;
1145                                 #size-cells =    1144                                 #size-cells = <0>;
1146                                                  1145 
1147                                 dsi_in_vopb:     1146                                 dsi_in_vopb: endpoint@0 {
1148                                         reg =    1147                                         reg = <0>;
1149                                         remot    1148                                         remote-endpoint = <&vopb_out_dsi>;
1150                                 };               1149                                 };
1151                                                  1150 
1152                                 dsi_in_vopl:     1151                                 dsi_in_vopl: endpoint@1 {
1153                                         reg =    1152                                         reg = <1>;
1154                                         remot    1153                                         remote-endpoint = <&vopl_out_dsi>;
1155                                 };               1154                                 };
1156                         };                       1155                         };
1157                                                  1156 
1158                         dsi_out: port@1 {        1157                         dsi_out: port@1 {
1159                                 reg = <1>;       1158                                 reg = <1>;
1160                         };                       1159                         };
1161                 };                               1160                 };
1162         };                                       1161         };
1163                                                  1162 
1164         vopb: vop@ff460000 {                     1163         vopb: vop@ff460000 {
1165                 compatible = "rockchip,px30-v    1164                 compatible = "rockchip,px30-vop-big";
1166                 reg = <0x0 0xff460000 0x0 0xe    1165                 reg = <0x0 0xff460000 0x0 0xefc>;
1167                 interrupts = <GIC_SPI 77 IRQ_    1166                 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
1168                 clocks = <&cru ACLK_VOPB>, <&    1167                 clocks = <&cru ACLK_VOPB>, <&cru DCLK_VOPB>,
1169                          <&cru HCLK_VOPB>;       1168                          <&cru HCLK_VOPB>;
1170                 clock-names = "aclk_vop", "dc    1169                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1171                 resets = <&cru SRST_VOPB_A>,     1170                 resets = <&cru SRST_VOPB_A>, <&cru SRST_VOPB_H>, <&cru SRST_VOPB>;
1172                 reset-names = "axi", "ahb", "    1171                 reset-names = "axi", "ahb", "dclk";
1173                 iommus = <&vopb_mmu>;            1172                 iommus = <&vopb_mmu>;
1174                 power-domains = <&power PX30_    1173                 power-domains = <&power PX30_PD_VO>;
1175                 status = "disabled";             1174                 status = "disabled";
1176                                                  1175 
1177                 vopb_out: port {                 1176                 vopb_out: port {
1178                         #address-cells = <1>;    1177                         #address-cells = <1>;
1179                         #size-cells = <0>;       1178                         #size-cells = <0>;
1180                                                  1179 
1181                         vopb_out_dsi: endpoin    1180                         vopb_out_dsi: endpoint@0 {
1182                                 reg = <0>;       1181                                 reg = <0>;
1183                                 remote-endpoi    1182                                 remote-endpoint = <&dsi_in_vopb>;
1184                         };                       1183                         };
1185                                                  1184 
1186                         vopb_out_lvds: endpoi    1185                         vopb_out_lvds: endpoint@1 {
1187                                 reg = <1>;       1186                                 reg = <1>;
1188                                 remote-endpoi    1187                                 remote-endpoint = <&lvds_vopb_in>;
1189                         };                       1188                         };
1190                 };                               1189                 };
1191         };                                       1190         };
1192                                                  1191 
1193         vopb_mmu: iommu@ff460f00 {               1192         vopb_mmu: iommu@ff460f00 {
1194                 compatible = "rockchip,iommu"    1193                 compatible = "rockchip,iommu";
1195                 reg = <0x0 0xff460f00 0x0 0x1    1194                 reg = <0x0 0xff460f00 0x0 0x100>;
1196                 interrupts = <GIC_SPI 77 IRQ_    1195                 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
1197                 clocks = <&cru ACLK_VOPB>, <&    1196                 clocks = <&cru ACLK_VOPB>, <&cru HCLK_VOPB>;
1198                 clock-names = "aclk", "iface"    1197                 clock-names = "aclk", "iface";
1199                 power-domains = <&power PX30_    1198                 power-domains = <&power PX30_PD_VO>;
1200                 #iommu-cells = <0>;              1199                 #iommu-cells = <0>;
1201                 status = "disabled";             1200                 status = "disabled";
1202         };                                       1201         };
1203                                                  1202 
1204         vopl: vop@ff470000 {                     1203         vopl: vop@ff470000 {
1205                 compatible = "rockchip,px30-v    1204                 compatible = "rockchip,px30-vop-lit";
1206                 reg = <0x0 0xff470000 0x0 0xe    1205                 reg = <0x0 0xff470000 0x0 0xefc>;
1207                 interrupts = <GIC_SPI 78 IRQ_    1206                 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
1208                 clocks = <&cru ACLK_VOPL>, <&    1207                 clocks = <&cru ACLK_VOPL>, <&cru DCLK_VOPL>,
1209                          <&cru HCLK_VOPL>;       1208                          <&cru HCLK_VOPL>;
1210                 clock-names = "aclk_vop", "dc    1209                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1211                 resets = <&cru SRST_VOPL_A>,     1210                 resets = <&cru SRST_VOPL_A>, <&cru SRST_VOPL_H>, <&cru SRST_VOPL>;
1212                 reset-names = "axi", "ahb", "    1211                 reset-names = "axi", "ahb", "dclk";
1213                 iommus = <&vopl_mmu>;            1212                 iommus = <&vopl_mmu>;
1214                 power-domains = <&power PX30_    1213                 power-domains = <&power PX30_PD_VO>;
1215                 status = "disabled";             1214                 status = "disabled";
1216                                                  1215 
1217                 vopl_out: port {                 1216                 vopl_out: port {
1218                         #address-cells = <1>;    1217                         #address-cells = <1>;
1219                         #size-cells = <0>;       1218                         #size-cells = <0>;
1220                                                  1219 
1221                         vopl_out_dsi: endpoin    1220                         vopl_out_dsi: endpoint@0 {
1222                                 reg = <0>;       1221                                 reg = <0>;
1223                                 remote-endpoi    1222                                 remote-endpoint = <&dsi_in_vopl>;
1224                         };                       1223                         };
1225                                                  1224 
1226                         vopl_out_lvds: endpoi    1225                         vopl_out_lvds: endpoint@1 {
1227                                 reg = <1>;       1226                                 reg = <1>;
1228                                 remote-endpoi    1227                                 remote-endpoint = <&lvds_vopl_in>;
1229                         };                       1228                         };
1230                 };                               1229                 };
1231         };                                       1230         };
1232                                                  1231 
1233         vopl_mmu: iommu@ff470f00 {               1232         vopl_mmu: iommu@ff470f00 {
1234                 compatible = "rockchip,iommu"    1233                 compatible = "rockchip,iommu";
1235                 reg = <0x0 0xff470f00 0x0 0x1    1234                 reg = <0x0 0xff470f00 0x0 0x100>;
1236                 interrupts = <GIC_SPI 78 IRQ_    1235                 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
1237                 clocks = <&cru ACLK_VOPL>, <&    1236                 clocks = <&cru ACLK_VOPL>, <&cru HCLK_VOPL>;
1238                 clock-names = "aclk", "iface"    1237                 clock-names = "aclk", "iface";
1239                 power-domains = <&power PX30_    1238                 power-domains = <&power PX30_PD_VO>;
1240                 #iommu-cells = <0>;              1239                 #iommu-cells = <0>;
1241                 status = "disabled";             1240                 status = "disabled";
1242         };                                       1241         };
1243                                                  1242 
1244         isp: isp@ff4a0000 {                      1243         isp: isp@ff4a0000 {
1245                 compatible = "rockchip,px30-c    1244                 compatible = "rockchip,px30-cif-isp"; /*rk3326-rkisp1*/
1246                 reg = <0x0 0xff4a0000 0x0 0x8    1245                 reg = <0x0 0xff4a0000 0x0 0x8000>;
1247                 interrupts = <GIC_SPI 70 IRQ_    1246                 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
1248                              <GIC_SPI 73 IRQ_    1247                              <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
1249                              <GIC_SPI 74 IRQ_    1248                              <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
1250                 interrupt-names = "isp", "mi"    1249                 interrupt-names = "isp", "mi", "mipi";
1251                 clocks = <&cru SCLK_ISP>,        1250                 clocks = <&cru SCLK_ISP>,
1252                          <&cru ACLK_ISP>,        1251                          <&cru ACLK_ISP>,
1253                          <&cru HCLK_ISP>,        1252                          <&cru HCLK_ISP>,
1254                          <&cru PCLK_ISP>;        1253                          <&cru PCLK_ISP>;
1255                 clock-names = "isp", "aclk",     1254                 clock-names = "isp", "aclk", "hclk", "pclk";
1256                 iommus = <&isp_mmu>;             1255                 iommus = <&isp_mmu>;
1257                 phys = <&csi_dphy>;              1256                 phys = <&csi_dphy>;
1258                 phy-names = "dphy";              1257                 phy-names = "dphy";
1259                 power-domains = <&power PX30_    1258                 power-domains = <&power PX30_PD_VI>;
1260                 status = "disabled";             1259                 status = "disabled";
1261                                                  1260 
1262                 ports {                          1261                 ports {
1263                         #address-cells = <1>;    1262                         #address-cells = <1>;
1264                         #size-cells = <0>;       1263                         #size-cells = <0>;
1265                                                  1264 
1266                         port@0 {                 1265                         port@0 {
1267                                 reg = <0>;       1266                                 reg = <0>;
1268                                 #address-cell    1267                                 #address-cells = <1>;
1269                                 #size-cells =    1268                                 #size-cells = <0>;
1270                         };                       1269                         };
1271                 };                               1270                 };
1272         };                                       1271         };
1273                                                  1272 
1274         isp_mmu: iommu@ff4a8000 {                1273         isp_mmu: iommu@ff4a8000 {
1275                 compatible = "rockchip,iommu"    1274                 compatible = "rockchip,iommu";
1276                 reg = <0x0 0xff4a8000 0x0 0x1    1275                 reg = <0x0 0xff4a8000 0x0 0x100>;
1277                 interrupts = <GIC_SPI 70 IRQ_    1276                 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
1278                 clocks = <&cru ACLK_ISP>, <&c    1277                 clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>;
1279                 clock-names = "aclk", "iface"    1278                 clock-names = "aclk", "iface";
1280                 power-domains = <&power PX30_    1279                 power-domains = <&power PX30_PD_VI>;
1281                 rockchip,disable-mmu-reset;      1280                 rockchip,disable-mmu-reset;
1282                 #iommu-cells = <0>;              1281                 #iommu-cells = <0>;
1283         };                                       1282         };
1284                                                  1283 
1285         qos_gmac: qos@ff518000 {                 1284         qos_gmac: qos@ff518000 {
1286                 compatible = "rockchip,px30-q    1285                 compatible = "rockchip,px30-qos", "syscon";
1287                 reg = <0x0 0xff518000 0x0 0x2    1286                 reg = <0x0 0xff518000 0x0 0x20>;
1288         };                                       1287         };
1289                                                  1288 
1290         qos_gpu: qos@ff520000 {                  1289         qos_gpu: qos@ff520000 {
1291                 compatible = "rockchip,px30-q    1290                 compatible = "rockchip,px30-qos", "syscon";
1292                 reg = <0x0 0xff520000 0x0 0x2    1291                 reg = <0x0 0xff520000 0x0 0x20>;
1293         };                                       1292         };
1294                                                  1293 
1295         qos_sdmmc: qos@ff52c000 {                1294         qos_sdmmc: qos@ff52c000 {
1296                 compatible = "rockchip,px30-q    1295                 compatible = "rockchip,px30-qos", "syscon";
1297                 reg = <0x0 0xff52c000 0x0 0x2    1296                 reg = <0x0 0xff52c000 0x0 0x20>;
1298         };                                       1297         };
1299                                                  1298 
1300         qos_emmc: qos@ff538000 {                 1299         qos_emmc: qos@ff538000 {
1301                 compatible = "rockchip,px30-q    1300                 compatible = "rockchip,px30-qos", "syscon";
1302                 reg = <0x0 0xff538000 0x0 0x2    1301                 reg = <0x0 0xff538000 0x0 0x20>;
1303         };                                       1302         };
1304                                                  1303 
1305         qos_nand: qos@ff538080 {                 1304         qos_nand: qos@ff538080 {
1306                 compatible = "rockchip,px30-q    1305                 compatible = "rockchip,px30-qos", "syscon";
1307                 reg = <0x0 0xff538080 0x0 0x2    1306                 reg = <0x0 0xff538080 0x0 0x20>;
1308         };                                       1307         };
1309                                                  1308 
1310         qos_sdio: qos@ff538100 {                 1309         qos_sdio: qos@ff538100 {
1311                 compatible = "rockchip,px30-q    1310                 compatible = "rockchip,px30-qos", "syscon";
1312                 reg = <0x0 0xff538100 0x0 0x2    1311                 reg = <0x0 0xff538100 0x0 0x20>;
1313         };                                       1312         };
1314                                                  1313 
1315         qos_sfc: qos@ff538180 {                  1314         qos_sfc: qos@ff538180 {
1316                 compatible = "rockchip,px30-q    1315                 compatible = "rockchip,px30-qos", "syscon";
1317                 reg = <0x0 0xff538180 0x0 0x2    1316                 reg = <0x0 0xff538180 0x0 0x20>;
1318         };                                       1317         };
1319                                                  1318 
1320         qos_usb_host: qos@ff540000 {             1319         qos_usb_host: qos@ff540000 {
1321                 compatible = "rockchip,px30-q    1320                 compatible = "rockchip,px30-qos", "syscon";
1322                 reg = <0x0 0xff540000 0x0 0x2    1321                 reg = <0x0 0xff540000 0x0 0x20>;
1323         };                                       1322         };
1324                                                  1323 
1325         qos_usb_otg: qos@ff540080 {              1324         qos_usb_otg: qos@ff540080 {
1326                 compatible = "rockchip,px30-q    1325                 compatible = "rockchip,px30-qos", "syscon";
1327                 reg = <0x0 0xff540080 0x0 0x2    1326                 reg = <0x0 0xff540080 0x0 0x20>;
1328         };                                       1327         };
1329                                                  1328 
1330         qos_isp_128: qos@ff548000 {              1329         qos_isp_128: qos@ff548000 {
1331                 compatible = "rockchip,px30-q    1330                 compatible = "rockchip,px30-qos", "syscon";
1332                 reg = <0x0 0xff548000 0x0 0x2    1331                 reg = <0x0 0xff548000 0x0 0x20>;
1333         };                                       1332         };
1334                                                  1333 
1335         qos_isp_rd: qos@ff548080 {               1334         qos_isp_rd: qos@ff548080 {
1336                 compatible = "rockchip,px30-q    1335                 compatible = "rockchip,px30-qos", "syscon";
1337                 reg = <0x0 0xff548080 0x0 0x2    1336                 reg = <0x0 0xff548080 0x0 0x20>;
1338         };                                       1337         };
1339                                                  1338 
1340         qos_isp_wr: qos@ff548100 {               1339         qos_isp_wr: qos@ff548100 {
1341                 compatible = "rockchip,px30-q    1340                 compatible = "rockchip,px30-qos", "syscon";
1342                 reg = <0x0 0xff548100 0x0 0x2    1341                 reg = <0x0 0xff548100 0x0 0x20>;
1343         };                                       1342         };
1344                                                  1343 
1345         qos_isp_m1: qos@ff548180 {               1344         qos_isp_m1: qos@ff548180 {
1346                 compatible = "rockchip,px30-q    1345                 compatible = "rockchip,px30-qos", "syscon";
1347                 reg = <0x0 0xff548180 0x0 0x2    1346                 reg = <0x0 0xff548180 0x0 0x20>;
1348         };                                       1347         };
1349                                                  1348 
1350         qos_vip: qos@ff548200 {                  1349         qos_vip: qos@ff548200 {
1351                 compatible = "rockchip,px30-q    1350                 compatible = "rockchip,px30-qos", "syscon";
1352                 reg = <0x0 0xff548200 0x0 0x2    1351                 reg = <0x0 0xff548200 0x0 0x20>;
1353         };                                       1352         };
1354                                                  1353 
1355         qos_rga_rd: qos@ff550000 {               1354         qos_rga_rd: qos@ff550000 {
1356                 compatible = "rockchip,px30-q    1355                 compatible = "rockchip,px30-qos", "syscon";
1357                 reg = <0x0 0xff550000 0x0 0x2    1356                 reg = <0x0 0xff550000 0x0 0x20>;
1358         };                                       1357         };
1359                                                  1358 
1360         qos_rga_wr: qos@ff550080 {               1359         qos_rga_wr: qos@ff550080 {
1361                 compatible = "rockchip,px30-q    1360                 compatible = "rockchip,px30-qos", "syscon";
1362                 reg = <0x0 0xff550080 0x0 0x2    1361                 reg = <0x0 0xff550080 0x0 0x20>;
1363         };                                       1362         };
1364                                                  1363 
1365         qos_vop_m0: qos@ff550100 {               1364         qos_vop_m0: qos@ff550100 {
1366                 compatible = "rockchip,px30-q    1365                 compatible = "rockchip,px30-qos", "syscon";
1367                 reg = <0x0 0xff550100 0x0 0x2    1366                 reg = <0x0 0xff550100 0x0 0x20>;
1368         };                                       1367         };
1369                                                  1368 
1370         qos_vop_m1: qos@ff550180 {               1369         qos_vop_m1: qos@ff550180 {
1371                 compatible = "rockchip,px30-q    1370                 compatible = "rockchip,px30-qos", "syscon";
1372                 reg = <0x0 0xff550180 0x0 0x2    1371                 reg = <0x0 0xff550180 0x0 0x20>;
1373         };                                       1372         };
1374                                                  1373 
1375         qos_vpu: qos@ff558000 {                  1374         qos_vpu: qos@ff558000 {
1376                 compatible = "rockchip,px30-q    1375                 compatible = "rockchip,px30-qos", "syscon";
1377                 reg = <0x0 0xff558000 0x0 0x2    1376                 reg = <0x0 0xff558000 0x0 0x20>;
1378         };                                       1377         };
1379                                                  1378 
1380         qos_vpu_r128: qos@ff558080 {             1379         qos_vpu_r128: qos@ff558080 {
1381                 compatible = "rockchip,px30-q    1380                 compatible = "rockchip,px30-qos", "syscon";
1382                 reg = <0x0 0xff558080 0x0 0x2    1381                 reg = <0x0 0xff558080 0x0 0x20>;
1383         };                                       1382         };
1384                                                  1383 
1385         pinctrl: pinctrl {                       1384         pinctrl: pinctrl {
1386                 compatible = "rockchip,px30-p    1385                 compatible = "rockchip,px30-pinctrl";
1387                 rockchip,grf = <&grf>;           1386                 rockchip,grf = <&grf>;
1388                 rockchip,pmu = <&pmugrf>;        1387                 rockchip,pmu = <&pmugrf>;
1389                 #address-cells = <2>;            1388                 #address-cells = <2>;
1390                 #size-cells = <2>;               1389                 #size-cells = <2>;
1391                 ranges;                          1390                 ranges;
1392                                                  1391 
1393                 gpio0: gpio@ff040000 {           1392                 gpio0: gpio@ff040000 {
1394                         compatible = "rockchi    1393                         compatible = "rockchip,gpio-bank";
1395                         reg = <0x0 0xff040000    1394                         reg = <0x0 0xff040000 0x0 0x100>;
1396                         interrupts = <GIC_SPI    1395                         interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
1397                         clocks = <&pmucru PCL    1396                         clocks = <&pmucru PCLK_GPIO0_PMU>;
1398                         gpio-controller;         1397                         gpio-controller;
1399                         #gpio-cells = <2>;       1398                         #gpio-cells = <2>;
1400                                                  1399 
1401                         interrupt-controller;    1400                         interrupt-controller;
1402                         #interrupt-cells = <2    1401                         #interrupt-cells = <2>;
1403                 };                               1402                 };
1404                                                  1403 
1405                 gpio1: gpio@ff250000 {           1404                 gpio1: gpio@ff250000 {
1406                         compatible = "rockchi    1405                         compatible = "rockchip,gpio-bank";
1407                         reg = <0x0 0xff250000    1406                         reg = <0x0 0xff250000 0x0 0x100>;
1408                         interrupts = <GIC_SPI    1407                         interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
1409                         clocks = <&cru PCLK_G    1408                         clocks = <&cru PCLK_GPIO1>;
1410                         gpio-controller;         1409                         gpio-controller;
1411                         #gpio-cells = <2>;       1410                         #gpio-cells = <2>;
1412                                                  1411 
1413                         interrupt-controller;    1412                         interrupt-controller;
1414                         #interrupt-cells = <2    1413                         #interrupt-cells = <2>;
1415                 };                               1414                 };
1416                                                  1415 
1417                 gpio2: gpio@ff260000 {           1416                 gpio2: gpio@ff260000 {
1418                         compatible = "rockchi    1417                         compatible = "rockchip,gpio-bank";
1419                         reg = <0x0 0xff260000    1418                         reg = <0x0 0xff260000 0x0 0x100>;
1420                         interrupts = <GIC_SPI    1419                         interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
1421                         clocks = <&cru PCLK_G    1420                         clocks = <&cru PCLK_GPIO2>;
1422                         gpio-controller;         1421                         gpio-controller;
1423                         #gpio-cells = <2>;       1422                         #gpio-cells = <2>;
1424                                                  1423 
1425                         interrupt-controller;    1424                         interrupt-controller;
1426                         #interrupt-cells = <2    1425                         #interrupt-cells = <2>;
1427                 };                               1426                 };
1428                                                  1427 
1429                 gpio3: gpio@ff270000 {           1428                 gpio3: gpio@ff270000 {
1430                         compatible = "rockchi    1429                         compatible = "rockchip,gpio-bank";
1431                         reg = <0x0 0xff270000    1430                         reg = <0x0 0xff270000 0x0 0x100>;
1432                         interrupts = <GIC_SPI    1431                         interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
1433                         clocks = <&cru PCLK_G    1432                         clocks = <&cru PCLK_GPIO3>;
1434                         gpio-controller;         1433                         gpio-controller;
1435                         #gpio-cells = <2>;       1434                         #gpio-cells = <2>;
1436                                                  1435 
1437                         interrupt-controller;    1436                         interrupt-controller;
1438                         #interrupt-cells = <2    1437                         #interrupt-cells = <2>;
1439                 };                               1438                 };
1440                                                  1439 
1441                 pcfg_pull_up: pcfg-pull-up {     1440                 pcfg_pull_up: pcfg-pull-up {
1442                         bias-pull-up;            1441                         bias-pull-up;
1443                 };                               1442                 };
1444                                                  1443 
1445                 pcfg_pull_down: pcfg-pull-dow    1444                 pcfg_pull_down: pcfg-pull-down {
1446                         bias-pull-down;          1445                         bias-pull-down;
1447                 };                               1446                 };
1448                                                  1447 
1449                 pcfg_pull_none: pcfg-pull-non    1448                 pcfg_pull_none: pcfg-pull-none {
1450                         bias-disable;            1449                         bias-disable;
1451                 };                               1450                 };
1452                                                  1451 
1453                 pcfg_pull_none_2ma: pcfg-pull    1452                 pcfg_pull_none_2ma: pcfg-pull-none-2ma {
1454                         bias-disable;            1453                         bias-disable;
1455                         drive-strength = <2>;    1454                         drive-strength = <2>;
1456                 };                               1455                 };
1457                                                  1456 
1458                 pcfg_pull_up_2ma: pcfg-pull-u    1457                 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
1459                         bias-pull-up;            1458                         bias-pull-up;
1460                         drive-strength = <2>;    1459                         drive-strength = <2>;
1461                 };                               1460                 };
1462                                                  1461 
1463                 pcfg_pull_up_4ma: pcfg-pull-u    1462                 pcfg_pull_up_4ma: pcfg-pull-up-4ma {
1464                         bias-pull-up;            1463                         bias-pull-up;
1465                         drive-strength = <4>;    1464                         drive-strength = <4>;
1466                 };                               1465                 };
1467                                                  1466 
1468                 pcfg_pull_none_4ma: pcfg-pull    1467                 pcfg_pull_none_4ma: pcfg-pull-none-4ma {
1469                         bias-disable;            1468                         bias-disable;
1470                         drive-strength = <4>;    1469                         drive-strength = <4>;
1471                 };                               1470                 };
1472                                                  1471 
1473                 pcfg_pull_down_4ma: pcfg-pull    1472                 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
1474                         bias-pull-down;          1473                         bias-pull-down;
1475                         drive-strength = <4>;    1474                         drive-strength = <4>;
1476                 };                               1475                 };
1477                                                  1476 
1478                 pcfg_pull_none_8ma: pcfg-pull    1477                 pcfg_pull_none_8ma: pcfg-pull-none-8ma {
1479                         bias-disable;            1478                         bias-disable;
1480                         drive-strength = <8>;    1479                         drive-strength = <8>;
1481                 };                               1480                 };
1482                                                  1481 
1483                 pcfg_pull_up_8ma: pcfg-pull-u    1482                 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
1484                         bias-pull-up;            1483                         bias-pull-up;
1485                         drive-strength = <8>;    1484                         drive-strength = <8>;
1486                 };                               1485                 };
1487                                                  1486 
1488                 pcfg_pull_none_12ma: pcfg-pul    1487                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1489                         bias-disable;            1488                         bias-disable;
1490                         drive-strength = <12>    1489                         drive-strength = <12>;
1491                 };                               1490                 };
1492                                                  1491 
1493                 pcfg_pull_up_12ma: pcfg-pull-    1492                 pcfg_pull_up_12ma: pcfg-pull-up-12ma {
1494                         bias-pull-up;            1493                         bias-pull-up;
1495                         drive-strength = <12>    1494                         drive-strength = <12>;
1496                 };                               1495                 };
1497                                                  1496 
1498                 pcfg_pull_none_smt: pcfg-pull    1497                 pcfg_pull_none_smt: pcfg-pull-none-smt {
1499                         bias-disable;            1498                         bias-disable;
1500                         input-schmitt-enable;    1499                         input-schmitt-enable;
1501                 };                               1500                 };
1502                                                  1501 
1503                 pcfg_output_high: pcfg-output    1502                 pcfg_output_high: pcfg-output-high {
1504                         output-high;             1503                         output-high;
1505                 };                               1504                 };
1506                                                  1505 
1507                 pcfg_output_low: pcfg-output-    1506                 pcfg_output_low: pcfg-output-low {
1508                         output-low;              1507                         output-low;
1509                 };                               1508                 };
1510                                                  1509 
1511                 pcfg_input_high: pcfg-input-h    1510                 pcfg_input_high: pcfg-input-high {
1512                         bias-pull-up;            1511                         bias-pull-up;
1513                         input-enable;            1512                         input-enable;
1514                 };                               1513                 };
1515                                                  1514 
1516                 pcfg_input: pcfg-input {         1515                 pcfg_input: pcfg-input {
1517                         input-enable;            1516                         input-enable;
1518                 };                               1517                 };
1519                                                  1518 
1520                 i2c0 {                           1519                 i2c0 {
1521                         i2c0_xfer: i2c0-xfer     1520                         i2c0_xfer: i2c0-xfer {
1522                                 rockchip,pins    1521                                 rockchip,pins =
1523                                         <0 RK    1522                                         <0 RK_PB0 1 &pcfg_pull_none_smt>,
1524                                         <0 RK    1523                                         <0 RK_PB1 1 &pcfg_pull_none_smt>;
1525                         };                       1524                         };
1526                 };                               1525                 };
1527                                                  1526 
1528                 i2c1 {                           1527                 i2c1 {
1529                         i2c1_xfer: i2c1-xfer     1528                         i2c1_xfer: i2c1-xfer {
1530                                 rockchip,pins    1529                                 rockchip,pins =
1531                                         <0 RK    1530                                         <0 RK_PC2 1 &pcfg_pull_none_smt>,
1532                                         <0 RK    1531                                         <0 RK_PC3 1 &pcfg_pull_none_smt>;
1533                         };                       1532                         };
1534                 };                               1533                 };
1535                                                  1534 
1536                 i2c2 {                           1535                 i2c2 {
1537                         i2c2_xfer: i2c2-xfer     1536                         i2c2_xfer: i2c2-xfer {
1538                                 rockchip,pins    1537                                 rockchip,pins =
1539                                         <2 RK    1538                                         <2 RK_PB7 2 &pcfg_pull_none_smt>,
1540                                         <2 RK    1539                                         <2 RK_PC0 2 &pcfg_pull_none_smt>;
1541                         };                       1540                         };
1542                 };                               1541                 };
1543                                                  1542 
1544                 i2c3 {                           1543                 i2c3 {
1545                         i2c3_xfer: i2c3-xfer     1544                         i2c3_xfer: i2c3-xfer {
1546                                 rockchip,pins    1545                                 rockchip,pins =
1547                                         <1 RK    1546                                         <1 RK_PB4 4 &pcfg_pull_none_smt>,
1548                                         <1 RK    1547                                         <1 RK_PB5 4 &pcfg_pull_none_smt>;
1549                         };                       1548                         };
1550                 };                               1549                 };
1551                                                  1550 
1552                 tsadc {                          1551                 tsadc {
1553                         tsadc_otp_pin: tsadc-    1552                         tsadc_otp_pin: tsadc-otp-pin {
1554                                 rockchip,pins    1553                                 rockchip,pins =
1555                                         <0 RK    1554                                         <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
1556                         };                       1555                         };
1557                                                  1556 
1558                         tsadc_otp_out: tsadc-    1557                         tsadc_otp_out: tsadc-otp-out {
1559                                 rockchip,pins    1558                                 rockchip,pins =
1560                                         <0 RK    1559                                         <0 RK_PA6 1 &pcfg_pull_none>;
1561                         };                       1560                         };
1562                 };                               1561                 };
1563                                                  1562 
1564                 uart0 {                          1563                 uart0 {
1565                         uart0_xfer: uart0-xfe    1564                         uart0_xfer: uart0-xfer {
1566                                 rockchip,pins    1565                                 rockchip,pins =
1567                                         <0 RK    1566                                         <0 RK_PB2 1 &pcfg_pull_up>,
1568                                         <0 RK    1567                                         <0 RK_PB3 1 &pcfg_pull_up>;
1569                         };                       1568                         };
1570                                                  1569 
1571                         uart0_cts: uart0-cts     1570                         uart0_cts: uart0-cts {
1572                                 rockchip,pins    1571                                 rockchip,pins =
1573                                         <0 RK    1572                                         <0 RK_PB4 1 &pcfg_pull_none>;
1574                         };                       1573                         };
1575                                                  1574 
1576                         uart0_rts: uart0-rts     1575                         uart0_rts: uart0-rts {
1577                                 rockchip,pins    1576                                 rockchip,pins =
1578                                         <0 RK    1577                                         <0 RK_PB5 1 &pcfg_pull_none>;
1579                         };                       1578                         };
1580                 };                               1579                 };
1581                                                  1580 
1582                 uart1 {                          1581                 uart1 {
1583                         uart1_xfer: uart1-xfe    1582                         uart1_xfer: uart1-xfer {
1584                                 rockchip,pins    1583                                 rockchip,pins =
1585                                         <1 RK    1584                                         <1 RK_PC1 1 &pcfg_pull_up>,
1586                                         <1 RK    1585                                         <1 RK_PC0 1 &pcfg_pull_up>;
1587                         };                       1586                         };
1588                                                  1587 
1589                         uart1_cts: uart1-cts     1588                         uart1_cts: uart1-cts {
1590                                 rockchip,pins    1589                                 rockchip,pins =
1591                                         <1 RK    1590                                         <1 RK_PC2 1 &pcfg_pull_none>;
1592                         };                       1591                         };
1593                                                  1592 
1594                         uart1_rts: uart1-rts     1593                         uart1_rts: uart1-rts {
1595                                 rockchip,pins    1594                                 rockchip,pins =
1596                                         <1 RK    1595                                         <1 RK_PC3 1 &pcfg_pull_none>;
1597                         };                       1596                         };
1598                 };                               1597                 };
1599                                                  1598 
1600                 uart2-m0 {                       1599                 uart2-m0 {
1601                         uart2m0_xfer: uart2m0    1600                         uart2m0_xfer: uart2m0-xfer {
1602                                 rockchip,pins    1601                                 rockchip,pins =
1603                                         <1 RK    1602                                         <1 RK_PD2 2 &pcfg_pull_up>,
1604                                         <1 RK    1603                                         <1 RK_PD3 2 &pcfg_pull_up>;
1605                         };                       1604                         };
1606                 };                               1605                 };
1607                                                  1606 
1608                 uart2-m1 {                       1607                 uart2-m1 {
1609                         uart2m1_xfer: uart2m1    1608                         uart2m1_xfer: uart2m1-xfer {
1610                                 rockchip,pins    1609                                 rockchip,pins =
1611                                         <2 RK    1610                                         <2 RK_PB4 2 &pcfg_pull_up>,
1612                                         <2 RK    1611                                         <2 RK_PB6 2 &pcfg_pull_up>;
1613                         };                       1612                         };
1614                 };                               1613                 };
1615                                                  1614 
1616                 uart3-m0 {                       1615                 uart3-m0 {
1617                         uart3m0_xfer: uart3m0    1616                         uart3m0_xfer: uart3m0-xfer {
1618                                 rockchip,pins    1617                                 rockchip,pins =
1619                                         <0 RK    1618                                         <0 RK_PC0 2 &pcfg_pull_up>,
1620                                         <0 RK    1619                                         <0 RK_PC1 2 &pcfg_pull_up>;
1621                         };                       1620                         };
1622                                                  1621 
1623                         uart3m0_cts: uart3m0-    1622                         uart3m0_cts: uart3m0-cts {
1624                                 rockchip,pins    1623                                 rockchip,pins =
1625                                         <0 RK    1624                                         <0 RK_PC2 2 &pcfg_pull_none>;
1626                         };                       1625                         };
1627                                                  1626 
1628                         uart3m0_rts: uart3m0-    1627                         uart3m0_rts: uart3m0-rts {
1629                                 rockchip,pins    1628                                 rockchip,pins =
1630                                         <0 RK    1629                                         <0 RK_PC3 2 &pcfg_pull_none>;
1631                         };                       1630                         };
1632                 };                               1631                 };
1633                                                  1632 
1634                 uart3-m1 {                       1633                 uart3-m1 {
1635                         uart3m1_xfer: uart3m1    1634                         uart3m1_xfer: uart3m1-xfer {
1636                                 rockchip,pins    1635                                 rockchip,pins =
1637                                         <1 RK    1636                                         <1 RK_PB6 2 &pcfg_pull_up>,
1638                                         <1 RK    1637                                         <1 RK_PB7 2 &pcfg_pull_up>;
1639                         };                       1638                         };
1640                                                  1639 
1641                         uart3m1_cts: uart3m1-    1640                         uart3m1_cts: uart3m1-cts {
1642                                 rockchip,pins    1641                                 rockchip,pins =
1643                                         <1 RK    1642                                         <1 RK_PB4 2 &pcfg_pull_none>;
1644                         };                       1643                         };
1645                                                  1644 
1646                         uart3m1_rts: uart3m1-    1645                         uart3m1_rts: uart3m1-rts {
1647                                 rockchip,pins    1646                                 rockchip,pins =
1648                                         <1 RK    1647                                         <1 RK_PB5 2 &pcfg_pull_none>;
1649                         };                       1648                         };
1650                 };                               1649                 };
1651                                                  1650 
1652                 uart4 {                          1651                 uart4 {
1653                         uart4_xfer: uart4-xfe    1652                         uart4_xfer: uart4-xfer {
1654                                 rockchip,pins    1653                                 rockchip,pins =
1655                                         <1 RK    1654                                         <1 RK_PD4 2 &pcfg_pull_up>,
1656                                         <1 RK    1655                                         <1 RK_PD5 2 &pcfg_pull_up>;
1657                         };                       1656                         };
1658                                                  1657 
1659                         uart4_cts: uart4-cts     1658                         uart4_cts: uart4-cts {
1660                                 rockchip,pins    1659                                 rockchip,pins =
1661                                         <1 RK    1660                                         <1 RK_PD6 2 &pcfg_pull_none>;
1662                         };                       1661                         };
1663                                                  1662 
1664                         uart4_rts: uart4-rts     1663                         uart4_rts: uart4-rts {
1665                                 rockchip,pins    1664                                 rockchip,pins =
1666                                         <1 RK    1665                                         <1 RK_PD7 2 &pcfg_pull_none>;
1667                         };                       1666                         };
1668                 };                               1667                 };
1669                                                  1668 
1670                 uart5 {                          1669                 uart5 {
1671                         uart5_xfer: uart5-xfe    1670                         uart5_xfer: uart5-xfer {
1672                                 rockchip,pins    1671                                 rockchip,pins =
1673                                         <3 RK    1672                                         <3 RK_PA2 4 &pcfg_pull_up>,
1674                                         <3 RK    1673                                         <3 RK_PA1 4 &pcfg_pull_up>;
1675                         };                       1674                         };
1676                                                  1675 
1677                         uart5_cts: uart5-cts     1676                         uart5_cts: uart5-cts {
1678                                 rockchip,pins    1677                                 rockchip,pins =
1679                                         <3 RK    1678                                         <3 RK_PA3 4 &pcfg_pull_none>;
1680                         };                       1679                         };
1681                                                  1680 
1682                         uart5_rts: uart5-rts     1681                         uart5_rts: uart5-rts {
1683                                 rockchip,pins    1682                                 rockchip,pins =
1684                                         <3 RK    1683                                         <3 RK_PA5 4 &pcfg_pull_none>;
1685                         };                       1684                         };
1686                 };                               1685                 };
1687                                                  1686 
1688                 spi0 {                           1687                 spi0 {
1689                         spi0_clk: spi0-clk {     1688                         spi0_clk: spi0-clk {
1690                                 rockchip,pins    1689                                 rockchip,pins =
1691                                         <1 RK    1690                                         <1 RK_PB7 3 &pcfg_pull_up_4ma>;
1692                         };                       1691                         };
1693                                                  1692 
1694                         spi0_csn: spi0-csn {     1693                         spi0_csn: spi0-csn {
1695                                 rockchip,pins    1694                                 rockchip,pins =
1696                                         <1 RK    1695                                         <1 RK_PB6 3 &pcfg_pull_up_4ma>;
1697                         };                       1696                         };
1698                                                  1697 
1699                         spi0_miso: spi0-miso     1698                         spi0_miso: spi0-miso {
1700                                 rockchip,pins    1699                                 rockchip,pins =
1701                                         <1 RK    1700                                         <1 RK_PB5 3 &pcfg_pull_up_4ma>;
1702                         };                       1701                         };
1703                                                  1702 
1704                         spi0_mosi: spi0-mosi     1703                         spi0_mosi: spi0-mosi {
1705                                 rockchip,pins    1704                                 rockchip,pins =
1706                                         <1 RK    1705                                         <1 RK_PB4 3 &pcfg_pull_up_4ma>;
1707                         };                       1706                         };
1708                                                  1707 
1709                         spi0_clk_hs: spi0-clk    1708                         spi0_clk_hs: spi0-clk-hs {
1710                                 rockchip,pins    1709                                 rockchip,pins =
1711                                         <1 RK    1710                                         <1 RK_PB7 3 &pcfg_pull_up_8ma>;
1712                         };                       1711                         };
1713                                                  1712 
1714                         spi0_miso_hs: spi0-mi    1713                         spi0_miso_hs: spi0-miso-hs {
1715                                 rockchip,pins    1714                                 rockchip,pins =
1716                                         <1 RK    1715                                         <1 RK_PB5 3 &pcfg_pull_up_8ma>;
1717                         };                       1716                         };
1718                                                  1717 
1719                         spi0_mosi_hs: spi0-mo    1718                         spi0_mosi_hs: spi0-mosi-hs {
1720                                 rockchip,pins    1719                                 rockchip,pins =
1721                                         <1 RK    1720                                         <1 RK_PB4 3 &pcfg_pull_up_8ma>;
1722                         };                       1721                         };
1723                 };                               1722                 };
1724                                                  1723 
1725                 spi1 {                           1724                 spi1 {
1726                         spi1_clk: spi1-clk {     1725                         spi1_clk: spi1-clk {
1727                                 rockchip,pins    1726                                 rockchip,pins =
1728                                         <3 RK    1727                                         <3 RK_PB7 4 &pcfg_pull_up_4ma>;
1729                         };                       1728                         };
1730                                                  1729 
1731                         spi1_csn0: spi1-csn0     1730                         spi1_csn0: spi1-csn0 {
1732                                 rockchip,pins    1731                                 rockchip,pins =
1733                                         <3 RK    1732                                         <3 RK_PB1 4 &pcfg_pull_up_4ma>;
1734                         };                       1733                         };
1735                                                  1734 
1736                         spi1_csn1: spi1-csn1     1735                         spi1_csn1: spi1-csn1 {
1737                                 rockchip,pins    1736                                 rockchip,pins =
1738                                         <3 RK    1737                                         <3 RK_PB2 2 &pcfg_pull_up_4ma>;
1739                         };                       1738                         };
1740                                                  1739 
1741                         spi1_miso: spi1-miso     1740                         spi1_miso: spi1-miso {
1742                                 rockchip,pins    1741                                 rockchip,pins =
1743                                         <3 RK    1742                                         <3 RK_PB6 4 &pcfg_pull_up_4ma>;
1744                         };                       1743                         };
1745                                                  1744 
1746                         spi1_mosi: spi1-mosi     1745                         spi1_mosi: spi1-mosi {
1747                                 rockchip,pins    1746                                 rockchip,pins =
1748                                         <3 RK    1747                                         <3 RK_PB4 4 &pcfg_pull_up_4ma>;
1749                         };                       1748                         };
1750                                                  1749 
1751                         spi1_clk_hs: spi1-clk    1750                         spi1_clk_hs: spi1-clk-hs {
1752                                 rockchip,pins    1751                                 rockchip,pins =
1753                                         <3 RK    1752                                         <3 RK_PB7 4 &pcfg_pull_up_8ma>;
1754                         };                       1753                         };
1755                                                  1754 
1756                         spi1_miso_hs: spi1-mi    1755                         spi1_miso_hs: spi1-miso-hs {
1757                                 rockchip,pins    1756                                 rockchip,pins =
1758                                         <3 RK    1757                                         <3 RK_PB6 4 &pcfg_pull_up_8ma>;
1759                         };                       1758                         };
1760                                                  1759 
1761                         spi1_mosi_hs: spi1-mo    1760                         spi1_mosi_hs: spi1-mosi-hs {
1762                                 rockchip,pins    1761                                 rockchip,pins =
1763                                         <3 RK    1762                                         <3 RK_PB4 4 &pcfg_pull_up_8ma>;
1764                         };                       1763                         };
1765                 };                               1764                 };
1766                                                  1765 
1767                 pdm {                            1766                 pdm {
1768                         pdm_clk0m0: pdm-clk0m    1767                         pdm_clk0m0: pdm-clk0m0 {
1769                                 rockchip,pins    1768                                 rockchip,pins =
1770                                         <3 RK    1769                                         <3 RK_PC6 2 &pcfg_pull_none>;
1771                         };                       1770                         };
1772                                                  1771 
1773                         pdm_clk0m1: pdm-clk0m    1772                         pdm_clk0m1: pdm-clk0m1 {
1774                                 rockchip,pins    1773                                 rockchip,pins =
1775                                         <2 RK    1774                                         <2 RK_PC6 1 &pcfg_pull_none>;
1776                         };                       1775                         };
1777                                                  1776 
1778                         pdm_clk1: pdm-clk1 {     1777                         pdm_clk1: pdm-clk1 {
1779                                 rockchip,pins    1778                                 rockchip,pins =
1780                                         <3 RK    1779                                         <3 RK_PC7 2 &pcfg_pull_none>;
1781                         };                       1780                         };
1782                                                  1781 
1783                         pdm_sdi0m0: pdm-sdi0m    1782                         pdm_sdi0m0: pdm-sdi0m0 {
1784                                 rockchip,pins    1783                                 rockchip,pins =
1785                                         <3 RK    1784                                         <3 RK_PD3 2 &pcfg_pull_none>;
1786                         };                       1785                         };
1787                                                  1786 
1788                         pdm_sdi0m1: pdm-sdi0m    1787                         pdm_sdi0m1: pdm-sdi0m1 {
1789                                 rockchip,pins    1788                                 rockchip,pins =
1790                                         <2 RK    1789                                         <2 RK_PC5 2 &pcfg_pull_none>;
1791                         };                       1790                         };
1792                                                  1791 
1793                         pdm_sdi1: pdm-sdi1 {     1792                         pdm_sdi1: pdm-sdi1 {
1794                                 rockchip,pins    1793                                 rockchip,pins =
1795                                         <3 RK    1794                                         <3 RK_PD0 2 &pcfg_pull_none>;
1796                         };                       1795                         };
1797                                                  1796 
1798                         pdm_sdi2: pdm-sdi2 {     1797                         pdm_sdi2: pdm-sdi2 {
1799                                 rockchip,pins    1798                                 rockchip,pins =
1800                                         <3 RK    1799                                         <3 RK_PD1 2 &pcfg_pull_none>;
1801                         };                       1800                         };
1802                                                  1801 
1803                         pdm_sdi3: pdm-sdi3 {     1802                         pdm_sdi3: pdm-sdi3 {
1804                                 rockchip,pins    1803                                 rockchip,pins =
1805                                         <3 RK    1804                                         <3 RK_PD2 2 &pcfg_pull_none>;
1806                         };                       1805                         };
1807                                                  1806 
1808                         pdm_clk0m0_sleep: pdm    1807                         pdm_clk0m0_sleep: pdm-clk0m0-sleep {
1809                                 rockchip,pins    1808                                 rockchip,pins =
1810                                         <3 RK    1809                                         <3 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>;
1811                         };                       1810                         };
1812                                                  1811 
1813                         pdm_clk0m_sleep1: pdm    1812                         pdm_clk0m_sleep1: pdm-clk0m1-sleep {
1814                                 rockchip,pins    1813                                 rockchip,pins =
1815                                         <2 RK    1814                                         <2 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>;
1816                         };                       1815                         };
1817                                                  1816 
1818                         pdm_clk1_sleep: pdm-c    1817                         pdm_clk1_sleep: pdm-clk1-sleep {
1819                                 rockchip,pins    1818                                 rockchip,pins =
1820                                         <3 RK    1819                                         <3 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>;
1821                         };                       1820                         };
1822                                                  1821 
1823                         pdm_sdi0m0_sleep: pdm    1822                         pdm_sdi0m0_sleep: pdm-sdi0m0-sleep {
1824                                 rockchip,pins    1823                                 rockchip,pins =
1825                                         <3 RK    1824                                         <3 RK_PD3 RK_FUNC_GPIO &pcfg_input_high>;
1826                         };                       1825                         };
1827                                                  1826 
1828                         pdm_sdi0m1_sleep: pdm    1827                         pdm_sdi0m1_sleep: pdm-sdi0m1-sleep {
1829                                 rockchip,pins    1828                                 rockchip,pins =
1830                                         <2 RK    1829                                         <2 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>;
1831                         };                       1830                         };
1832                                                  1831 
1833                         pdm_sdi1_sleep: pdm-s    1832                         pdm_sdi1_sleep: pdm-sdi1-sleep {
1834                                 rockchip,pins    1833                                 rockchip,pins =
1835                                         <3 RK    1834                                         <3 RK_PD0 RK_FUNC_GPIO &pcfg_input_high>;
1836                         };                       1835                         };
1837                                                  1836 
1838                         pdm_sdi2_sleep: pdm-s    1837                         pdm_sdi2_sleep: pdm-sdi2-sleep {
1839                                 rockchip,pins    1838                                 rockchip,pins =
1840                                         <3 RK    1839                                         <3 RK_PD1 RK_FUNC_GPIO &pcfg_input_high>;
1841                         };                       1840                         };
1842                                                  1841 
1843                         pdm_sdi3_sleep: pdm-s    1842                         pdm_sdi3_sleep: pdm-sdi3-sleep {
1844                                 rockchip,pins    1843                                 rockchip,pins =
1845                                         <3 RK    1844                                         <3 RK_PD2 RK_FUNC_GPIO &pcfg_input_high>;
1846                         };                       1845                         };
1847                 };                               1846                 };
1848                                                  1847 
1849                 i2s0 {                           1848                 i2s0 {
1850                         i2s0_8ch_mclk: i2s0-8    1849                         i2s0_8ch_mclk: i2s0-8ch-mclk {
1851                                 rockchip,pins    1850                                 rockchip,pins =
1852                                         <3 RK    1851                                         <3 RK_PC1 2 &pcfg_pull_none>;
1853                         };                       1852                         };
1854                                                  1853 
1855                         i2s0_8ch_sclktx: i2s0    1854                         i2s0_8ch_sclktx: i2s0-8ch-sclktx {
1856                                 rockchip,pins    1855                                 rockchip,pins =
1857                                         <3 RK    1856                                         <3 RK_PC3 2 &pcfg_pull_none>;
1858                         };                       1857                         };
1859                                                  1858 
1860                         i2s0_8ch_sclkrx: i2s0    1859                         i2s0_8ch_sclkrx: i2s0-8ch-sclkrx {
1861                                 rockchip,pins    1860                                 rockchip,pins =
1862                                         <3 RK    1861                                         <3 RK_PB4 2 &pcfg_pull_none>;
1863                         };                       1862                         };
1864                                                  1863 
1865                         i2s0_8ch_lrcktx: i2s0    1864                         i2s0_8ch_lrcktx: i2s0-8ch-lrcktx {
1866                                 rockchip,pins    1865                                 rockchip,pins =
1867                                         <3 RK    1866                                         <3 RK_PC2 2 &pcfg_pull_none>;
1868                         };                       1867                         };
1869                                                  1868 
1870                         i2s0_8ch_lrckrx: i2s0    1869                         i2s0_8ch_lrckrx: i2s0-8ch-lrckrx {
1871                                 rockchip,pins    1870                                 rockchip,pins =
1872                                         <3 RK    1871                                         <3 RK_PB5 2 &pcfg_pull_none>;
1873                         };                       1872                         };
1874                                                  1873 
1875                         i2s0_8ch_sdo0: i2s0-8    1874                         i2s0_8ch_sdo0: i2s0-8ch-sdo0 {
1876                                 rockchip,pins    1875                                 rockchip,pins =
1877                                         <3 RK    1876                                         <3 RK_PC4 2 &pcfg_pull_none>;
1878                         };                       1877                         };
1879                                                  1878 
1880                         i2s0_8ch_sdo1: i2s0-8    1879                         i2s0_8ch_sdo1: i2s0-8ch-sdo1 {
1881                                 rockchip,pins    1880                                 rockchip,pins =
1882                                         <3 RK    1881                                         <3 RK_PC0 2 &pcfg_pull_none>;
1883                         };                       1882                         };
1884                                                  1883 
1885                         i2s0_8ch_sdo2: i2s0-8    1884                         i2s0_8ch_sdo2: i2s0-8ch-sdo2 {
1886                                 rockchip,pins    1885                                 rockchip,pins =
1887                                         <3 RK    1886                                         <3 RK_PB7 2 &pcfg_pull_none>;
1888                         };                       1887                         };
1889                                                  1888 
1890                         i2s0_8ch_sdo3: i2s0-8    1889                         i2s0_8ch_sdo3: i2s0-8ch-sdo3 {
1891                                 rockchip,pins    1890                                 rockchip,pins =
1892                                         <3 RK    1891                                         <3 RK_PB6 2 &pcfg_pull_none>;
1893                         };                       1892                         };
1894                                                  1893 
1895                         i2s0_8ch_sdi0: i2s0-8    1894                         i2s0_8ch_sdi0: i2s0-8ch-sdi0 {
1896                                 rockchip,pins    1895                                 rockchip,pins =
1897                                         <3 RK    1896                                         <3 RK_PC5 2 &pcfg_pull_none>;
1898                         };                       1897                         };
1899                                                  1898 
1900                         i2s0_8ch_sdi1: i2s0-8    1899                         i2s0_8ch_sdi1: i2s0-8ch-sdi1 {
1901                                 rockchip,pins    1900                                 rockchip,pins =
1902                                         <3 RK    1901                                         <3 RK_PB3 2 &pcfg_pull_none>;
1903                         };                       1902                         };
1904                                                  1903 
1905                         i2s0_8ch_sdi2: i2s0-8    1904                         i2s0_8ch_sdi2: i2s0-8ch-sdi2 {
1906                                 rockchip,pins    1905                                 rockchip,pins =
1907                                         <3 RK    1906                                         <3 RK_PB1 2 &pcfg_pull_none>;
1908                         };                       1907                         };
1909                                                  1908 
1910                         i2s0_8ch_sdi3: i2s0-8    1909                         i2s0_8ch_sdi3: i2s0-8ch-sdi3 {
1911                                 rockchip,pins    1910                                 rockchip,pins =
1912                                         <3 RK    1911                                         <3 RK_PB0 2 &pcfg_pull_none>;
1913                         };                       1912                         };
1914                 };                               1913                 };
1915                                                  1914 
1916                 i2s1 {                           1915                 i2s1 {
1917                         i2s1_2ch_mclk: i2s1-2    1916                         i2s1_2ch_mclk: i2s1-2ch-mclk {
1918                                 rockchip,pins    1917                                 rockchip,pins =
1919                                         <2 RK    1918                                         <2 RK_PC3 1 &pcfg_pull_none>;
1920                         };                       1919                         };
1921                                                  1920 
1922                         i2s1_2ch_sclk: i2s1-2    1921                         i2s1_2ch_sclk: i2s1-2ch-sclk {
1923                                 rockchip,pins    1922                                 rockchip,pins =
1924                                         <2 RK    1923                                         <2 RK_PC2 1 &pcfg_pull_none>;
1925                         };                       1924                         };
1926                                                  1925 
1927                         i2s1_2ch_lrck: i2s1-2    1926                         i2s1_2ch_lrck: i2s1-2ch-lrck {
1928                                 rockchip,pins    1927                                 rockchip,pins =
1929                                         <2 RK    1928                                         <2 RK_PC1 1 &pcfg_pull_none>;
1930                         };                       1929                         };
1931                                                  1930 
1932                         i2s1_2ch_sdi: i2s1-2c    1931                         i2s1_2ch_sdi: i2s1-2ch-sdi {
1933                                 rockchip,pins    1932                                 rockchip,pins =
1934                                         <2 RK    1933                                         <2 RK_PC5 1 &pcfg_pull_none>;
1935                         };                       1934                         };
1936                                                  1935 
1937                         i2s1_2ch_sdo: i2s1-2c    1936                         i2s1_2ch_sdo: i2s1-2ch-sdo {
1938                                 rockchip,pins    1937                                 rockchip,pins =
1939                                         <2 RK    1938                                         <2 RK_PC4 1 &pcfg_pull_none>;
1940                         };                       1939                         };
1941                 };                               1940                 };
1942                                                  1941 
1943                 i2s2 {                           1942                 i2s2 {
1944                         i2s2_2ch_mclk: i2s2-2    1943                         i2s2_2ch_mclk: i2s2-2ch-mclk {
1945                                 rockchip,pins    1944                                 rockchip,pins =
1946                                         <3 RK    1945                                         <3 RK_PA1 2 &pcfg_pull_none>;
1947                         };                       1946                         };
1948                                                  1947 
1949                         i2s2_2ch_sclk: i2s2-2    1948                         i2s2_2ch_sclk: i2s2-2ch-sclk {
1950                                 rockchip,pins    1949                                 rockchip,pins =
1951                                         <3 RK    1950                                         <3 RK_PA2 2 &pcfg_pull_none>;
1952                         };                       1951                         };
1953                                                  1952 
1954                         i2s2_2ch_lrck: i2s2-2    1953                         i2s2_2ch_lrck: i2s2-2ch-lrck {
1955                                 rockchip,pins    1954                                 rockchip,pins =
1956                                         <3 RK    1955                                         <3 RK_PA3 2 &pcfg_pull_none>;
1957                         };                       1956                         };
1958                                                  1957 
1959                         i2s2_2ch_sdi: i2s2-2c    1958                         i2s2_2ch_sdi: i2s2-2ch-sdi {
1960                                 rockchip,pins    1959                                 rockchip,pins =
1961                                         <3 RK    1960                                         <3 RK_PA5 2 &pcfg_pull_none>;
1962                         };                       1961                         };
1963                                                  1962 
1964                         i2s2_2ch_sdo: i2s2-2c    1963                         i2s2_2ch_sdo: i2s2-2ch-sdo {
1965                                 rockchip,pins    1964                                 rockchip,pins =
1966                                         <3 RK    1965                                         <3 RK_PA7 2 &pcfg_pull_none>;
1967                         };                       1966                         };
1968                 };                               1967                 };
1969                                                  1968 
1970                 sdmmc {                          1969                 sdmmc {
1971                         sdmmc_clk: sdmmc-clk     1970                         sdmmc_clk: sdmmc-clk {
1972                                 rockchip,pins    1971                                 rockchip,pins =
1973                                         <1 RK    1972                                         <1 RK_PD6 1 &pcfg_pull_none_8ma>;
1974                         };                       1973                         };
1975                                                  1974 
1976                         sdmmc_cmd: sdmmc-cmd     1975                         sdmmc_cmd: sdmmc-cmd {
1977                                 rockchip,pins    1976                                 rockchip,pins =
1978                                         <1 RK    1977                                         <1 RK_PD7 1 &pcfg_pull_up_8ma>;
1979                         };                       1978                         };
1980                                                  1979 
1981                         sdmmc_det: sdmmc-det     1980                         sdmmc_det: sdmmc-det {
1982                                 rockchip,pins    1981                                 rockchip,pins =
1983                                         <0 RK    1982                                         <0 RK_PA3 1 &pcfg_pull_up_8ma>;
1984                         };                       1983                         };
1985                                                  1984 
1986                         sdmmc_bus1: sdmmc-bus    1985                         sdmmc_bus1: sdmmc-bus1 {
1987                                 rockchip,pins    1986                                 rockchip,pins =
1988                                         <1 RK    1987                                         <1 RK_PD2 1 &pcfg_pull_up_8ma>;
1989                         };                       1988                         };
1990                                                  1989 
1991                         sdmmc_bus4: sdmmc-bus    1990                         sdmmc_bus4: sdmmc-bus4 {
1992                                 rockchip,pins    1991                                 rockchip,pins =
1993                                         <1 RK    1992                                         <1 RK_PD2 1 &pcfg_pull_up_8ma>,
1994                                         <1 RK    1993                                         <1 RK_PD3 1 &pcfg_pull_up_8ma>,
1995                                         <1 RK    1994                                         <1 RK_PD4 1 &pcfg_pull_up_8ma>,
1996                                         <1 RK    1995                                         <1 RK_PD5 1 &pcfg_pull_up_8ma>;
1997                         };                       1996                         };
1998                 };                               1997                 };
1999                                                  1998 
2000                 sdio {                           1999                 sdio {
2001                         sdio_clk: sdio-clk {     2000                         sdio_clk: sdio-clk {
2002                                 rockchip,pins    2001                                 rockchip,pins =
2003                                         <1 RK    2002                                         <1 RK_PC5 1 &pcfg_pull_none>;
2004                         };                       2003                         };
2005                                                  2004 
2006                         sdio_cmd: sdio-cmd {     2005                         sdio_cmd: sdio-cmd {
2007                                 rockchip,pins    2006                                 rockchip,pins =
2008                                         <1 RK    2007                                         <1 RK_PC4 1 &pcfg_pull_up>;
2009                         };                       2008                         };
2010                                                  2009 
2011                         sdio_bus4: sdio-bus4     2010                         sdio_bus4: sdio-bus4 {
2012                                 rockchip,pins    2011                                 rockchip,pins =
2013                                         <1 RK    2012                                         <1 RK_PC6 1 &pcfg_pull_up>,
2014                                         <1 RK    2013                                         <1 RK_PC7 1 &pcfg_pull_up>,
2015                                         <1 RK    2014                                         <1 RK_PD0 1 &pcfg_pull_up>,
2016                                         <1 RK    2015                                         <1 RK_PD1 1 &pcfg_pull_up>;
2017                         };                       2016                         };
2018                 };                               2017                 };
2019                                                  2018 
2020                 emmc {                           2019                 emmc {
2021                         emmc_clk: emmc-clk {     2020                         emmc_clk: emmc-clk {
2022                                 rockchip,pins    2021                                 rockchip,pins =
2023                                         <1 RK    2022                                         <1 RK_PB1 2 &pcfg_pull_none_8ma>;
2024                         };                       2023                         };
2025                                                  2024 
2026                         emmc_cmd: emmc-cmd {     2025                         emmc_cmd: emmc-cmd {
2027                                 rockchip,pins    2026                                 rockchip,pins =
2028                                         <1 RK    2027                                         <1 RK_PB2 2 &pcfg_pull_up_8ma>;
2029                         };                       2028                         };
2030                                                  2029 
2031                         emmc_rstnout: emmc-rs    2030                         emmc_rstnout: emmc-rstnout {
2032                                 rockchip,pins    2031                                 rockchip,pins =
2033                                         <1 RK    2032                                         <1 RK_PB3 2 &pcfg_pull_none>;
2034                         };                       2033                         };
2035                                                  2034 
2036                         emmc_bus1: emmc-bus1     2035                         emmc_bus1: emmc-bus1 {
2037                                 rockchip,pins    2036                                 rockchip,pins =
2038                                         <1 RK    2037                                         <1 RK_PA0 2 &pcfg_pull_up_8ma>;
2039                         };                       2038                         };
2040                                                  2039 
2041                         emmc_bus4: emmc-bus4     2040                         emmc_bus4: emmc-bus4 {
2042                                 rockchip,pins    2041                                 rockchip,pins =
2043                                         <1 RK    2042                                         <1 RK_PA0 2 &pcfg_pull_up_8ma>,
2044                                         <1 RK    2043                                         <1 RK_PA1 2 &pcfg_pull_up_8ma>,
2045                                         <1 RK    2044                                         <1 RK_PA2 2 &pcfg_pull_up_8ma>,
2046                                         <1 RK    2045                                         <1 RK_PA3 2 &pcfg_pull_up_8ma>;
2047                         };                       2046                         };
2048                                                  2047 
2049                         emmc_bus8: emmc-bus8     2048                         emmc_bus8: emmc-bus8 {
2050                                 rockchip,pins    2049                                 rockchip,pins =
2051                                         <1 RK    2050                                         <1 RK_PA0 2 &pcfg_pull_up_8ma>,
2052                                         <1 RK    2051                                         <1 RK_PA1 2 &pcfg_pull_up_8ma>,
2053                                         <1 RK    2052                                         <1 RK_PA2 2 &pcfg_pull_up_8ma>,
2054                                         <1 RK    2053                                         <1 RK_PA3 2 &pcfg_pull_up_8ma>,
2055                                         <1 RK    2054                                         <1 RK_PA4 2 &pcfg_pull_up_8ma>,
2056                                         <1 RK    2055                                         <1 RK_PA5 2 &pcfg_pull_up_8ma>,
2057                                         <1 RK    2056                                         <1 RK_PA6 2 &pcfg_pull_up_8ma>,
2058                                         <1 RK    2057                                         <1 RK_PA7 2 &pcfg_pull_up_8ma>;
2059                         };                       2058                         };
2060                 };                               2059                 };
2061                                                  2060 
2062                 flash {                          2061                 flash {
2063                         flash_cs0: flash-cs0     2062                         flash_cs0: flash-cs0 {
2064                                 rockchip,pins    2063                                 rockchip,pins =
2065                                         <1 RK    2064                                         <1 RK_PB0 1 &pcfg_pull_none>;
2066                         };                       2065                         };
2067                                                  2066 
2068                         flash_rdy: flash-rdy     2067                         flash_rdy: flash-rdy {
2069                                 rockchip,pins    2068                                 rockchip,pins =
2070                                         <1 RK    2069                                         <1 RK_PB1 1 &pcfg_pull_none>;
2071                         };                       2070                         };
2072                                                  2071 
2073                         flash_dqs: flash-dqs     2072                         flash_dqs: flash-dqs {
2074                                 rockchip,pins    2073                                 rockchip,pins =
2075                                         <1 RK    2074                                         <1 RK_PB2 1 &pcfg_pull_none>;
2076                         };                       2075                         };
2077                                                  2076 
2078                         flash_ale: flash-ale     2077                         flash_ale: flash-ale {
2079                                 rockchip,pins    2078                                 rockchip,pins =
2080                                         <1 RK    2079                                         <1 RK_PB3 1 &pcfg_pull_none>;
2081                         };                       2080                         };
2082                                                  2081 
2083                         flash_cle: flash-cle     2082                         flash_cle: flash-cle {
2084                                 rockchip,pins    2083                                 rockchip,pins =
2085                                         <1 RK    2084                                         <1 RK_PB4 1 &pcfg_pull_none>;
2086                         };                       2085                         };
2087                                                  2086 
2088                         flash_wrn: flash-wrn     2087                         flash_wrn: flash-wrn {
2089                                 rockchip,pins    2088                                 rockchip,pins =
2090                                         <1 RK    2089                                         <1 RK_PB5 1 &pcfg_pull_none>;
2091                         };                       2090                         };
2092                                                  2091 
2093                         flash_csl: flash-csl     2092                         flash_csl: flash-csl {
2094                                 rockchip,pins    2093                                 rockchip,pins =
2095                                         <1 RK    2094                                         <1 RK_PB6 1 &pcfg_pull_none>;
2096                         };                       2095                         };
2097                                                  2096 
2098                         flash_rdn: flash-rdn     2097                         flash_rdn: flash-rdn {
2099                                 rockchip,pins    2098                                 rockchip,pins =
2100                                         <1 RK    2099                                         <1 RK_PB7 1 &pcfg_pull_none>;
2101                         };                       2100                         };
2102                                                  2101 
2103                         flash_bus8: flash-bus    2102                         flash_bus8: flash-bus8 {
2104                                 rockchip,pins    2103                                 rockchip,pins =
2105                                         <1 RK    2104                                         <1 RK_PA0 1 &pcfg_pull_up_12ma>,
2106                                         <1 RK    2105                                         <1 RK_PA1 1 &pcfg_pull_up_12ma>,
2107                                         <1 RK    2106                                         <1 RK_PA2 1 &pcfg_pull_up_12ma>,
2108                                         <1 RK    2107                                         <1 RK_PA3 1 &pcfg_pull_up_12ma>,
2109                                         <1 RK    2108                                         <1 RK_PA4 1 &pcfg_pull_up_12ma>,
2110                                         <1 RK    2109                                         <1 RK_PA5 1 &pcfg_pull_up_12ma>,
2111                                         <1 RK    2110                                         <1 RK_PA6 1 &pcfg_pull_up_12ma>,
2112                                         <1 RK    2111                                         <1 RK_PA7 1 &pcfg_pull_up_12ma>;
2113                         };                       2112                         };
2114                 };                               2113                 };
2115                                                  2114 
2116                 sfc {                            2115                 sfc {
2117                         sfc_bus4: sfc-bus4 {     2116                         sfc_bus4: sfc-bus4 {
2118                                 rockchip,pins    2117                                 rockchip,pins =
2119                                         <1 RK    2118                                         <1 RK_PA0 3 &pcfg_pull_none>,
2120                                         <1 RK    2119                                         <1 RK_PA1 3 &pcfg_pull_none>,
2121                                         <1 RK    2120                                         <1 RK_PA2 3 &pcfg_pull_none>,
2122                                         <1 RK    2121                                         <1 RK_PA3 3 &pcfg_pull_none>;
2123                         };                       2122                         };
2124                                                  2123 
2125                         sfc_bus2: sfc-bus2 {     2124                         sfc_bus2: sfc-bus2 {
2126                                 rockchip,pins    2125                                 rockchip,pins =
2127                                         <1 RK    2126                                         <1 RK_PA0 3 &pcfg_pull_none>,
2128                                         <1 RK    2127                                         <1 RK_PA1 3 &pcfg_pull_none>;
2129                         };                       2128                         };
2130                                                  2129 
2131                         sfc_cs0: sfc-cs0 {       2130                         sfc_cs0: sfc-cs0 {
2132                                 rockchip,pins    2131                                 rockchip,pins =
2133                                         <1 RK    2132                                         <1 RK_PA4 3 &pcfg_pull_none>;
2134                         };                       2133                         };
2135                                                  2134 
2136                         sfc_clk: sfc-clk {       2135                         sfc_clk: sfc-clk {
2137                                 rockchip,pins    2136                                 rockchip,pins =
2138                                         <1 RK    2137                                         <1 RK_PB1 3 &pcfg_pull_none>;
2139                         };                       2138                         };
2140                 };                               2139                 };
2141                                                  2140 
2142                 lcdc {                           2141                 lcdc {
2143                         lcdc_rgb_dclk_pin: lc    2142                         lcdc_rgb_dclk_pin: lcdc-rgb-dclk-pin {
2144                                 rockchip,pins    2143                                 rockchip,pins =
2145                                         <3 RK    2144                                         <3 RK_PA0 1 &pcfg_pull_none_12ma>;
2146                         };                       2145                         };
2147                                                  2146 
2148                         lcdc_rgb_m0_hsync_pin    2147                         lcdc_rgb_m0_hsync_pin: lcdc-rgb-m0-hsync-pin {
2149                                 rockchip,pins    2148                                 rockchip,pins =
2150                                         <3 RK    2149                                         <3 RK_PA1 1 &pcfg_pull_none_12ma>;
2151                         };                       2150                         };
2152                                                  2151 
2153                         lcdc_rgb_m0_vsync_pin    2152                         lcdc_rgb_m0_vsync_pin: lcdc-rgb-m0-vsync-pin {
2154                                 rockchip,pins    2153                                 rockchip,pins =
2155                                         <3 RK    2154                                         <3 RK_PA2 1 &pcfg_pull_none_12ma>;
2156                         };                       2155                         };
2157                                                  2156 
2158                         lcdc_rgb_m0_den_pin:     2157                         lcdc_rgb_m0_den_pin: lcdc-rgb-m0-den-pin {
2159                                 rockchip,pins    2158                                 rockchip,pins =
2160                                         <3 RK    2159                                         <3 RK_PA3 1 &pcfg_pull_none_12ma>;
2161                         };                       2160                         };
2162                                                  2161 
2163                         lcdc_rgb888_m0_data_p    2162                         lcdc_rgb888_m0_data_pins: lcdc-rgb888-m0-data-pins {
2164                                 rockchip,pins    2163                                 rockchip,pins =
2165                                         <3 RK    2164                                         <3 RK_PA7 1 &pcfg_pull_none_8ma>, /* lcdc_d3 */
2166                                         <3 RK    2165                                         <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */
2167                                         <3 RK    2166                                         <3 RK_PA5 1 &pcfg_pull_none_8ma>, /* lcdc_d1 */
2168                                         <3 RK    2167                                         <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */
2169                                         <3 RK    2168                                         <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */
2170                                         <3 RK    2169                                         <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */
2171                                         <3 RK    2170                                         <3 RK_PB1 1 &pcfg_pull_none_8ma>, /* lcdc_d5 */
2172                                         <3 RK    2171                                         <3 RK_PB0 1 &pcfg_pull_none_8ma>, /* lcdc_d4 */
2173                                         <3 RK    2172                                         <3 RK_PB7 1 &pcfg_pull_none_8ma>, /* lcdc_d11 */
2174                                         <3 RK    2173                                         <3 RK_PB6 1 &pcfg_pull_none_8ma>, /* lcdc_d10 */
2175                                         <3 RK    2174                                         <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */
2176                                         <3 RK    2175                                         <3 RK_PB4 1 &pcfg_pull_none_8ma>, /* lcdc_d8 */
2177                                         <3 RK    2176                                         <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */
2178                                         <3 RK    2177                                         <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */
2179                                         <3 RK    2178                                         <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */
2180                                         <3 RK    2179                                         <3 RK_PC0 1 &pcfg_pull_none_8ma>, /* lcdc_d12 */
2181                                         <3 RK    2180                                         <3 RK_PC7 1 &pcfg_pull_none_8ma>, /* lcdc_d19 */
2182                                         <3 RK    2181                                         <3 RK_PC6 1 &pcfg_pull_none_8ma>, /* lcdc_d18 */
2183                                         <3 RK    2182                                         <3 RK_PC5 1 &pcfg_pull_none_8ma>, /* lcdc_d17 */
2184                                         <3 RK    2183                                         <3 RK_PC4 1 &pcfg_pull_none_8ma>, /* lcdc_d16 */
2185                                         <3 RK    2184                                         <3 RK_PD3 1 &pcfg_pull_none_8ma>, /* lcdc_d23 */
2186                                         <3 RK    2185                                         <3 RK_PD2 1 &pcfg_pull_none_8ma>, /* lcdc_d22 */
2187                                         <3 RK    2186                                         <3 RK_PD1 1 &pcfg_pull_none_8ma>, /* lcdc_d21 */
2188                                         <3 RK    2187                                         <3 RK_PD0 1 &pcfg_pull_none_8ma>; /* lcdc_d20 */
2189                         };                       2188                         };
2190                                                  2189 
2191                         lcdc_rgb666_m0_data_p    2190                         lcdc_rgb666_m0_data_pins: lcdc-rgb666-m0-data-pins {
2192                                 rockchip,pins    2191                                 rockchip,pins =
2193                                         <3 RK    2192                                         <3 RK_PA7 1 &pcfg_pull_none_8ma>, /* lcdc_d3 */
2194                                         <3 RK    2193                                         <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */
2195                                         <3 RK    2194                                         <3 RK_PA5 1 &pcfg_pull_none_8ma>, /* lcdc_d1 */
2196                                         <3 RK    2195                                         <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */
2197                                         <3 RK    2196                                         <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */
2198                                         <3 RK    2197                                         <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */
2199                                         <3 RK    2198                                         <3 RK_PB1 1 &pcfg_pull_none_8ma>, /* lcdc_d5 */
2200                                         <3 RK    2199                                         <3 RK_PB0 1 &pcfg_pull_none_8ma>, /* lcdc_d4 */
2201                                         <3 RK    2200                                         <3 RK_PB7 1 &pcfg_pull_none_8ma>, /* lcdc_d11 */
2202                                         <3 RK    2201                                         <3 RK_PB6 1 &pcfg_pull_none_8ma>, /* lcdc_d10 */
2203                                         <3 RK    2202                                         <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */
2204                                         <3 RK    2203                                         <3 RK_PB4 1 &pcfg_pull_none_8ma>, /* lcdc_d8 */
2205                                         <3 RK    2204                                         <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */
2206                                         <3 RK    2205                                         <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */
2207                                         <3 RK    2206                                         <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */
2208                                         <3 RK    2207                                         <3 RK_PC0 1 &pcfg_pull_none_8ma>, /* lcdc_d12 */
2209                                         <3 RK    2208                                         <3 RK_PC5 1 &pcfg_pull_none_8ma>, /* lcdc_d17 */
2210                                         <3 RK    2209                                         <3 RK_PC4 1 &pcfg_pull_none_8ma>; /* lcdc_d16 */
2211                         };                       2210                         };
2212                                                  2211 
2213                         lcdc_rgb565_m0_data_p    2212                         lcdc_rgb565_m0_data_pins: lcdc-rgb565-m0-data-pins {
2214                                 rockchip,pins    2213                                 rockchip,pins =
2215                                         <3 RK    2214                                         <3 RK_PA7 1 &pcfg_pull_none_8ma>, /* lcdc_d3 */
2216                                         <3 RK    2215                                         <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */
2217                                         <3 RK    2216                                         <3 RK_PA5 1 &pcfg_pull_none_8ma>, /* lcdc_d1 */
2218                                         <3 RK    2217                                         <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */
2219                                         <3 RK    2218                                         <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */
2220                                         <3 RK    2219                                         <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */
2221                                         <3 RK    2220                                         <3 RK_PB1 1 &pcfg_pull_none_8ma>, /* lcdc_d5 */
2222                                         <3 RK    2221                                         <3 RK_PB0 1 &pcfg_pull_none_8ma>, /* lcdc_d4 */
2223                                         <3 RK    2222                                         <3 RK_PB7 1 &pcfg_pull_none_8ma>, /* lcdc_d11 */
2224                                         <3 RK    2223                                         <3 RK_PB6 1 &pcfg_pull_none_8ma>, /* lcdc_d10 */
2225                                         <3 RK    2224                                         <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */
2226                                         <3 RK    2225                                         <3 RK_PB4 1 &pcfg_pull_none_8ma>, /* lcdc_d8 */
2227                                         <3 RK    2226                                         <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */
2228                                         <3 RK    2227                                         <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */
2229                                         <3 RK    2228                                         <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */
2230                                         <3 RK    2229                                         <3 RK_PC0 1 &pcfg_pull_none_8ma>; /* lcdc_d12 */
2231                         };                       2230                         };
2232                                                  2231 
2233                         lcdc_rgb888_m1_data_p    2232                         lcdc_rgb888_m1_data_pins: lcdc-rgb888-m1-data-pins {
2234                                 rockchip,pins    2233                                 rockchip,pins =
2235                                         <3 RK    2234                                         <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */
2236                                         <3 RK    2235                                         <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */
2237                                         <3 RK    2236                                         <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */
2238                                         <3 RK    2237                                         <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */
2239                                         <3 RK    2238                                         <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */
2240                                         <3 RK    2239                                         <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */
2241                                         <3 RK    2240                                         <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */
2242                                         <3 RK    2241                                         <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */
2243                                         <3 RK    2242                                         <3 RK_PC0 1 &pcfg_pull_none_8ma>, /* lcdc_d12 */
2244                                         <3 RK    2243                                         <3 RK_PC7 1 &pcfg_pull_none_8ma>, /* lcdc_d19 */
2245                                         <3 RK    2244                                         <3 RK_PC6 1 &pcfg_pull_none_8ma>, /* lcdc_d18 */
2246                                         <3 RK    2245                                         <3 RK_PC5 1 &pcfg_pull_none_8ma>, /* lcdc_d17 */
2247                                         <3 RK    2246                                         <3 RK_PC4 1 &pcfg_pull_none_8ma>, /* lcdc_d16 */
2248                                         <3 RK    2247                                         <3 RK_PD3 1 &pcfg_pull_none_8ma>, /* lcdc_d23 */
2249                                         <3 RK    2248                                         <3 RK_PD2 1 &pcfg_pull_none_8ma>, /* lcdc_d22 */
2250                                         <3 RK    2249                                         <3 RK_PD1 1 &pcfg_pull_none_8ma>, /* lcdc_d21 */
2251                                         <3 RK    2250                                         <3 RK_PD0 1 &pcfg_pull_none_8ma>; /* lcdc_d20 */
2252                         };                       2251                         };
2253                                                  2252 
2254                         lcdc_rgb666_m1_data_p    2253                         lcdc_rgb666_m1_data_pins: lcdc-rgb666-m1-data-pins {
2255                                 rockchip,pins    2254                                 rockchip,pins =
2256                                         <3 RK    2255                                         <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */
2257                                         <3 RK    2256                                         <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */
2258                                         <3 RK    2257                                         <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */
2259                                         <3 RK    2258                                         <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */
2260                                         <3 RK    2259                                         <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */
2261                                         <3 RK    2260                                         <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */
2262                                         <3 RK    2261                                         <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */
2263                                         <3 RK    2262                                         <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */
2264                                         <3 RK    2263                                         <3 RK_PC0 1 &pcfg_pull_none_8ma>, /* lcdc_d12 */
2265                                         <3 RK    2264                                         <3 RK_PC5 1 &pcfg_pull_none_8ma>, /* lcdc_d17 */
2266                                         <3 RK    2265                                         <3 RK_PC4 1 &pcfg_pull_none_8ma>; /* lcdc_d16 */
2267                         };                       2266                         };
2268                                                  2267 
2269                         lcdc_rgb565_m1_data_p    2268                         lcdc_rgb565_m1_data_pins: lcdc-rgb565-m1-data-pins {
2270                                 rockchip,pins    2269                                 rockchip,pins =
2271                                         <3 RK    2270                                         <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */
2272                                         <3 RK    2271                                         <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */
2273                                         <3 RK    2272                                         <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */
2274                                         <3 RK    2273                                         <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */
2275                                         <3 RK    2274                                         <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */
2276                                         <3 RK    2275                                         <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */
2277                                         <3 RK    2276                                         <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */
2278                                         <3 RK    2277                                         <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */
2279                                         <3 RK    2278                                         <3 RK_PC0 1 &pcfg_pull_none_8ma>; /* lcdc_d12 */
2280                         };                       2279                         };
2281                 };                               2280                 };
2282                                                  2281 
2283                 pwm0 {                           2282                 pwm0 {
2284                         pwm0_pin: pwm0-pin {     2283                         pwm0_pin: pwm0-pin {
2285                                 rockchip,pins    2284                                 rockchip,pins =
2286                                         <0 RK    2285                                         <0 RK_PB7 1 &pcfg_pull_none>;
2287                         };                       2286                         };
2288                 };                               2287                 };
2289                                                  2288 
2290                 pwm1 {                           2289                 pwm1 {
2291                         pwm1_pin: pwm1-pin {     2290                         pwm1_pin: pwm1-pin {
2292                                 rockchip,pins    2291                                 rockchip,pins =
2293                                         <0 RK    2292                                         <0 RK_PC0 1 &pcfg_pull_none>;
2294                         };                       2293                         };
2295                 };                               2294                 };
2296                                                  2295 
2297                 pwm2 {                           2296                 pwm2 {
2298                         pwm2_pin: pwm2-pin {     2297                         pwm2_pin: pwm2-pin {
2299                                 rockchip,pins    2298                                 rockchip,pins =
2300                                         <2 RK    2299                                         <2 RK_PB5 1 &pcfg_pull_none>;
2301                         };                       2300                         };
2302                 };                               2301                 };
2303                                                  2302 
2304                 pwm3 {                           2303                 pwm3 {
2305                         pwm3_pin: pwm3-pin {     2304                         pwm3_pin: pwm3-pin {
2306                                 rockchip,pins    2305                                 rockchip,pins =
2307                                         <0 RK    2306                                         <0 RK_PC1 1 &pcfg_pull_none>;
2308                         };                       2307                         };
2309                 };                               2308                 };
2310                                                  2309 
2311                 pwm4 {                           2310                 pwm4 {
2312                         pwm4_pin: pwm4-pin {     2311                         pwm4_pin: pwm4-pin {
2313                                 rockchip,pins    2312                                 rockchip,pins =
2314                                         <3 RK    2313                                         <3 RK_PC2 3 &pcfg_pull_none>;
2315                         };                       2314                         };
2316                 };                               2315                 };
2317                                                  2316 
2318                 pwm5 {                           2317                 pwm5 {
2319                         pwm5_pin: pwm5-pin {     2318                         pwm5_pin: pwm5-pin {
2320                                 rockchip,pins    2319                                 rockchip,pins =
2321                                         <3 RK    2320                                         <3 RK_PC3 3 &pcfg_pull_none>;
2322                         };                       2321                         };
2323                 };                               2322                 };
2324                                                  2323 
2325                 pwm6 {                           2324                 pwm6 {
2326                         pwm6_pin: pwm6-pin {     2325                         pwm6_pin: pwm6-pin {
2327                                 rockchip,pins    2326                                 rockchip,pins =
2328                                         <3 RK    2327                                         <3 RK_PC4 3 &pcfg_pull_none>;
2329                         };                       2328                         };
2330                 };                               2329                 };
2331                                                  2330 
2332                 pwm7 {                           2331                 pwm7 {
2333                         pwm7_pin: pwm7-pin {     2332                         pwm7_pin: pwm7-pin {
2334                                 rockchip,pins    2333                                 rockchip,pins =
2335                                         <3 RK    2334                                         <3 RK_PC5 3 &pcfg_pull_none>;
2336                         };                       2335                         };
2337                 };                               2336                 };
2338                                                  2337 
2339                 gmac {                           2338                 gmac {
2340                         rmii_pins: rmii-pins     2339                         rmii_pins: rmii-pins {
2341                                 rockchip,pins    2340                                 rockchip,pins =
2342                                         <2 RK    2341                                         <2 RK_PA0 2 &pcfg_pull_none_12ma>, /* mac_txen */
2343                                         <2 RK    2342                                         <2 RK_PA1 2 &pcfg_pull_none_12ma>, /* mac_txd1 */
2344                                         <2 RK    2343                                         <2 RK_PA2 2 &pcfg_pull_none_12ma>, /* mac_txd0 */
2345                                         <2 RK    2344                                         <2 RK_PA3 2 &pcfg_pull_none>, /* mac_rxd0 */
2346                                         <2 RK    2345                                         <2 RK_PA4 2 &pcfg_pull_none>, /* mac_rxd1 */
2347                                         <2 RK    2346                                         <2 RK_PA5 2 &pcfg_pull_none>, /* mac_rxer */
2348                                         <2 RK    2347                                         <2 RK_PA6 2 &pcfg_pull_none>, /* mac_rxdv */
2349                                         <2 RK    2348                                         <2 RK_PA7 2 &pcfg_pull_none>, /* mac_mdio */
2350                                         <2 RK    2349                                         <2 RK_PB1 2 &pcfg_pull_none>; /* mac_mdc */
2351                         };                       2350                         };
2352                                                  2351 
2353                         mac_refclk_12ma: mac-    2352                         mac_refclk_12ma: mac-refclk-12ma {
2354                                 rockchip,pins    2353                                 rockchip,pins =
2355                                         <2 RK    2354                                         <2 RK_PB2 2 &pcfg_pull_none_12ma>;
2356                         };                       2355                         };
2357                                                  2356 
2358                         mac_refclk: mac-refcl    2357                         mac_refclk: mac-refclk {
2359                                 rockchip,pins    2358                                 rockchip,pins =
2360                                         <2 RK    2359                                         <2 RK_PB2 2 &pcfg_pull_none>;
2361                         };                       2360                         };
2362                 };                               2361                 };
2363                                                  2362 
2364                 cif-m0 {                         2363                 cif-m0 {
2365                         cif_clkout_m0: cif-cl    2364                         cif_clkout_m0: cif-clkout-m0 {
2366                                 rockchip,pins    2365                                 rockchip,pins =
2367                                         <2 RK    2366                                         <2 RK_PB3 1 &pcfg_pull_none>;
2368                         };                       2367                         };
2369                                                  2368 
2370                         dvp_d2d9_m0: dvp-d2d9    2369                         dvp_d2d9_m0: dvp-d2d9-m0 {
2371                                 rockchip,pins    2370                                 rockchip,pins =
2372                                         <2 RK    2371                                         <2 RK_PA0 1 &pcfg_pull_none>, /* cif_data2 */
2373                                         <2 RK    2372                                         <2 RK_PA1 1 &pcfg_pull_none>, /* cif_data3 */
2374                                         <2 RK    2373                                         <2 RK_PA2 1 &pcfg_pull_none>, /* cif_data4 */
2375                                         <2 RK    2374                                         <2 RK_PA3 1 &pcfg_pull_none>, /* cif_data5 */
2376                                         <2 RK    2375                                         <2 RK_PA4 1 &pcfg_pull_none>, /* cif_data6 */
2377                                         <2 RK    2376                                         <2 RK_PA5 1 &pcfg_pull_none>, /* cif_data7 */
2378                                         <2 RK    2377                                         <2 RK_PA6 1 &pcfg_pull_none>, /* cif_data8 */
2379                                         <2 RK    2378                                         <2 RK_PA7 1 &pcfg_pull_none>, /* cif_data9 */
2380                                         <2 RK    2379                                         <2 RK_PB0 1 &pcfg_pull_none>, /* cif_sync */
2381                                         <2 RK    2380                                         <2 RK_PB1 1 &pcfg_pull_none>, /* cif_href */
2382                                         <2 RK    2381                                         <2 RK_PB2 1 &pcfg_pull_none>, /* cif_clkin */
2383                                         <2 RK    2382                                         <2 RK_PB3 1 &pcfg_pull_none>; /* cif_clkout */
2384                         };                       2383                         };
2385                                                  2384 
2386                         dvp_d0d1_m0: dvp-d0d1    2385                         dvp_d0d1_m0: dvp-d0d1-m0 {
2387                                 rockchip,pins    2386                                 rockchip,pins =
2388                                         <2 RK    2387                                         <2 RK_PB4 1 &pcfg_pull_none>, /* cif_data0 */
2389                                         <2 RK    2388                                         <2 RK_PB6 1 &pcfg_pull_none>; /* cif_data1 */
2390                         };                       2389                         };
2391                                                  2390 
2392                         dvp_d10d11_m0:d10-d11    2391                         dvp_d10d11_m0:d10-d11-m0 {
2393                                 rockchip,pins    2392                                 rockchip,pins =
2394                                         <2 RK    2393                                         <2 RK_PB7 1 &pcfg_pull_none>, /* cif_data10 */
2395                                         <2 RK    2394                                         <2 RK_PC0 1 &pcfg_pull_none>; /* cif_data11 */
2396                         };                       2395                         };
2397                 };                               2396                 };
2398                                                  2397 
2399                 cif-m1 {                         2398                 cif-m1 {
2400                         cif_clkout_m1: cif-cl    2399                         cif_clkout_m1: cif-clkout-m1 {
2401                                 rockchip,pins    2400                                 rockchip,pins =
2402                                         <3 RK    2401                                         <3 RK_PD0 3 &pcfg_pull_none>;
2403                         };                       2402                         };
2404                                                  2403 
2405                         dvp_d2d9_m1: dvp-d2d9    2404                         dvp_d2d9_m1: dvp-d2d9-m1 {
2406                                 rockchip,pins    2405                                 rockchip,pins =
2407                                         <3 RK    2406                                         <3 RK_PA3 3 &pcfg_pull_none>, /* cif_data2 */
2408                                         <3 RK    2407                                         <3 RK_PA5 3 &pcfg_pull_none>, /* cif_data3 */
2409                                         <3 RK    2408                                         <3 RK_PA7 3 &pcfg_pull_none>, /* cif_data4 */
2410                                         <3 RK    2409                                         <3 RK_PB0 3 &pcfg_pull_none>, /* cif_data5 */
2411                                         <3 RK    2410                                         <3 RK_PB1 3 &pcfg_pull_none>, /* cif_data6 */
2412                                         <3 RK    2411                                         <3 RK_PB4 3 &pcfg_pull_none>, /* cif_data7 */
2413                                         <3 RK    2412                                         <3 RK_PB6 3 &pcfg_pull_none>, /* cif_data8 */
2414                                         <3 RK    2413                                         <3 RK_PB7 3 &pcfg_pull_none>, /* cif_data9 */
2415                                         <3 RK    2414                                         <3 RK_PD1 3 &pcfg_pull_none>, /* cif_sync */
2416                                         <3 RK    2415                                         <3 RK_PD2 3 &pcfg_pull_none>, /* cif_href */
2417                                         <3 RK    2416                                         <3 RK_PD3 3 &pcfg_pull_none>, /* cif_clkin */
2418                                         <3 RK    2417                                         <3 RK_PD0 3 &pcfg_pull_none>; /* cif_clkout */
2419                         };                       2418                         };
2420                                                  2419 
2421                         dvp_d0d1_m1: dvp-d0d1    2420                         dvp_d0d1_m1: dvp-d0d1-m1 {
2422                                 rockchip,pins    2421                                 rockchip,pins =
2423                                         <3 RK    2422                                         <3 RK_PA1 3 &pcfg_pull_none>, /* cif_data0 */
2424                                         <3 RK    2423                                         <3 RK_PA2 3 &pcfg_pull_none>; /* cif_data1 */
2425                         };                       2424                         };
2426                                                  2425 
2427                         dvp_d10d11_m1:d10-d11    2426                         dvp_d10d11_m1:d10-d11-m1 {
2428                                 rockchip,pins    2427                                 rockchip,pins =
2429                                         <3 RK    2428                                         <3 RK_PC6 3 &pcfg_pull_none>, /* cif_data10 */
2430                                         <3 RK    2429                                         <3 RK_PC7 3 &pcfg_pull_none>; /* cif_data11 */
2431                         };                       2430                         };
2432                 };                               2431                 };
2433                                                  2432 
2434                 isp {                            2433                 isp {
2435                         isp_prelight: isp-pre    2434                         isp_prelight: isp-prelight {
2436                                 rockchip,pins    2435                                 rockchip,pins =
2437                                         <3 RK    2436                                         <3 RK_PD1 4 &pcfg_pull_none>;
2438                         };                       2437                         };
2439                 };                               2438                 };
2440         };                                       2439         };
2441 };                                               2440 };
                                                      

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