1 // SPDX-License-Identifier: GPL-2.0-or-later O 1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
2 /* 2 /*
3 * Copyright (c) 2016 Xunlong Software. Co., L 3 * Copyright (c) 2016 Xunlong Software. Co., Ltd.
4 * (http://www.orangepi.org) 4 * (http://www.orangepi.org)
5 * 5 *
6 * Copyright (c) 2021-2023 Tianling Shen <cnszt 6 * Copyright (c) 2021-2023 Tianling Shen <cnsztl@gmail.com>
7 */ 7 */
8 8
9 /dts-v1/; 9 /dts-v1/;
10 #include "rk3328-orangepi-r1-plus.dts" 10 #include "rk3328-orangepi-r1-plus.dts"
11 11
12 / { 12 / {
13 model = "Xunlong Orange Pi R1 Plus LTS 13 model = "Xunlong Orange Pi R1 Plus LTS";
14 compatible = "xunlong,orangepi-r1-plus 14 compatible = "xunlong,orangepi-r1-plus-lts", "rockchip,rk3328";
15 }; 15 };
16 16
17 &gmac2io { 17 &gmac2io {
18 phy-handle = <&yt8531c>; 18 phy-handle = <&yt8531c>;
19 tx_delay = <0x19>; 19 tx_delay = <0x19>;
20 rx_delay = <0x05>; 20 rx_delay = <0x05>;
21 21
22 mdio { 22 mdio {
23 /delete-node/ ethernet-phy@1; 23 /delete-node/ ethernet-phy@1;
24 24
25 yt8531c: ethernet-phy@0 { 25 yt8531c: ethernet-phy@0 {
26 compatible = "ethernet 26 compatible = "ethernet-phy-ieee802.3-c22";
27 reg = <0>; 27 reg = <0>;
28 28
29 motorcomm,auto-sleep-d 29 motorcomm,auto-sleep-disabled;
30 motorcomm,clk-out-freq 30 motorcomm,clk-out-frequency-hz = <125000000>;
31 motorcomm,keep-pll-ena 31 motorcomm,keep-pll-enabled;
32 motorcomm,rx-clk-drv-m 32 motorcomm,rx-clk-drv-microamp = <5020>;
33 motorcomm,rx-data-drv- 33 motorcomm,rx-data-drv-microamp = <5020>;
34 34
35 pinctrl-0 = <ð_phy_ 35 pinctrl-0 = <ð_phy_reset_pin>;
36 pinctrl-names = "defau 36 pinctrl-names = "default";
37 reset-assert-us = <150 37 reset-assert-us = <15000>;
38 reset-deassert-us = <5 38 reset-deassert-us = <50000>;
39 reset-gpios = <&gpio1 39 reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
40 }; 40 };
41 }; 41 };
42 }; 42 };
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