1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /*
3 * Copyright (c) 2017 PINE64
4 */
5
6 /dts-v1/;
7 #include "rk3328.dtsi"
8
9 / {
10 model = "Pine64 Rock64";
11 compatible = "pine64,rock64", "rockchi
12
13 aliases {
14 ethernet0 = &gmac2io;
15 mmc0 = &sdmmc;
16 mmc1 = &emmc;
17 };
18
19 chosen {
20 stdout-path = "serial2:1500000
21 };
22
23 gmac_clkin: external-gmac-clock {
24 compatible = "fixed-clock";
25 clock-frequency = <125000000>;
26 clock-output-names = "gmac_clk
27 #clock-cells = <0>;
28 };
29
30 vcc_sd: sdmmc-regulator {
31 compatible = "regulator-fixed"
32 gpio = <&gpio0 RK_PD6 GPIO_ACT
33 pinctrl-names = "default";
34 pinctrl-0 = <&sdmmc0m1_pin>;
35 regulator-name = "vcc_sd";
36 regulator-min-microvolt = <330
37 regulator-max-microvolt = <330
38 vin-supply = <&vcc_io>;
39 };
40
41 /* Common enable line for all of the r
42 vcc_host_5v: vcc_host1_5v: vcc_otg_5v:
43 compatible = "regulator-fixed"
44 gpio = <&gpio0 RK_PA2 GPIO_ACT
45 pinctrl-names = "default";
46 pinctrl-0 = <&usb20_host_drv>;
47 regulator-name = "vcc_host_5v"
48 regulator-always-on;
49 regulator-boot-on;
50 vin-supply = <&vcc_sys>;
51 };
52
53 vcc_sys: vcc-sys {
54 compatible = "regulator-fixed"
55 regulator-name = "vcc_sys";
56 regulator-always-on;
57 regulator-boot-on;
58 regulator-min-microvolt = <500
59 regulator-max-microvolt = <500
60 };
61
62 ir-receiver {
63 compatible = "gpio-ir-receiver
64 gpios = <&gpio2 RK_PA2 GPIO_AC
65 pinctrl-0 = <&ir_int>;
66 pinctrl-names = "default";
67 };
68
69 leds {
70 compatible = "gpio-leds";
71
72 power_led: led-0 {
73 gpios = <&rk805 1 GPIO
74 linux,default-trigger
75 };
76
77 standby_led: led-1 {
78 gpios = <&rk805 0 GPIO
79 linux,default-trigger
80 };
81 };
82
83 spdif_sound: spdif-sound {
84 compatible = "simple-audio-car
85 simple-audio-card,name = "SPDI
86
87 simple-audio-card,cpu {
88 sound-dai = <&spdif>;
89 };
90
91 simple-audio-card,codec {
92 sound-dai = <&spdif_di
93 };
94 };
95
96 spdif_dit: spdif-dit {
97 compatible = "linux,spdif-dit"
98 #sound-dai-cells = <0>;
99 };
100 };
101
102 &analog_sound {
103 status = "okay";
104 };
105
106 &codec {
107 mute-gpios = <&grf_gpio 0 GPIO_ACTIVE_
108 status = "okay";
109 };
110
111 &cpu0 {
112 cpu-supply = <&vdd_arm>;
113 };
114
115 &cpu1 {
116 cpu-supply = <&vdd_arm>;
117 };
118
119 &cpu2 {
120 cpu-supply = <&vdd_arm>;
121 };
122
123 &cpu3 {
124 cpu-supply = <&vdd_arm>;
125 };
126
127 &emmc {
128 bus-width = <8>;
129 cap-mmc-highspeed;
130 mmc-hs200-1_8v;
131 non-removable;
132 pinctrl-names = "default";
133 pinctrl-0 = <&emmc_clk &emmc_cmd &emmc
134 vmmc-supply = <&vcc_io>;
135 vqmmc-supply = <&vcc18_emmc>;
136 status = "okay";
137 };
138
139 &gmac2io {
140 assigned-clocks = <&cru SCLK_MAC2IO>,
141 assigned-clock-parents = <&gmac_clkin>
142 clock_in_out = "input";
143 phy-supply = <&vcc_io>;
144 phy-mode = "rgmii";
145 pinctrl-names = "default";
146 pinctrl-0 = <&rgmiim1_pins>;
147 snps,force_thresh_dma_mode;
148 snps,reset-gpio = <&gpio1 RK_PC2 GPIO_
149 snps,reset-active-low;
150 snps,reset-delays-us = <0 10000 50000>
151 tx_delay = <0x24>;
152 rx_delay = <0x18>;
153 status = "okay";
154 };
155
156 &hdmi {
157 avdd-0v9-supply = <&vdd_10>;
158 avdd-1v8-supply = <&vcc_18>;
159 status = "okay";
160 };
161
162 &hdmi_sound {
163 status = "okay";
164 };
165
166 &hdmiphy {
167 status = "okay";
168 };
169
170 &i2c1 {
171 status = "okay";
172
173 rk805: pmic@18 {
174 compatible = "rockchip,rk805";
175 reg = <0x18>;
176 interrupt-parent = <&gpio2>;
177 interrupts = <6 IRQ_TYPE_LEVEL
178 #clock-cells = <1>;
179 clock-output-names = "xin32k",
180 gpio-controller;
181 #gpio-cells = <2>;
182 pinctrl-names = "default";
183 pinctrl-0 = <&pmic_int_l>;
184 rockchip,system-power-controll
185 wakeup-source;
186
187 vcc1-supply = <&vcc_sys>;
188 vcc2-supply = <&vcc_sys>;
189 vcc3-supply = <&vcc_sys>;
190 vcc4-supply = <&vcc_sys>;
191 vcc5-supply = <&vcc_io>;
192 vcc6-supply = <&vcc_sys>;
193
194 regulators {
195 vdd_logic: DCDC_REG1 {
196 regulator-name
197 regulator-min-
198 regulator-max-
199 regulator-ramp
200 regulator-alwa
201 regulator-boot
202 regulator-stat
203 regula
204 regula
205 };
206 };
207
208 vdd_arm: DCDC_REG2 {
209 regulator-name
210 regulator-min-
211 regulator-max-
212 regulator-ramp
213 regulator-alwa
214 regulator-boot
215 regulator-stat
216 regula
217 regula
218 };
219 };
220
221 vcc_ddr: DCDC_REG3 {
222 regulator-name
223 regulator-alwa
224 regulator-boot
225 regulator-stat
226 regula
227 };
228 };
229
230 vcc_io: DCDC_REG4 {
231 regulator-name
232 regulator-min-
233 regulator-max-
234 regulator-alwa
235 regulator-boot
236 regulator-stat
237 regula
238 regula
239 };
240 };
241
242 vcc_18: LDO_REG1 {
243 regulator-name
244 regulator-min-
245 regulator-max-
246 regulator-alwa
247 regulator-boot
248 regulator-stat
249 regula
250 regula
251 };
252 };
253
254 vcc18_emmc: LDO_REG2 {
255 regulator-name
256 regulator-min-
257 regulator-max-
258 regulator-alwa
259 regulator-boot
260 regulator-stat
261 regula
262 regula
263 };
264 };
265
266 vdd_10: LDO_REG3 {
267 regulator-name
268 regulator-min-
269 regulator-max-
270 regulator-alwa
271 regulator-boot
272 regulator-stat
273 regula
274 regula
275 };
276 };
277 };
278 };
279 };
280
281 &i2s0 {
282 status = "okay";
283 };
284
285 &i2s1 {
286 status = "okay";
287 };
288
289 &io_domains {
290 status = "okay";
291
292 vccio1-supply = <&vcc_io>;
293 vccio2-supply = <&vcc18_emmc>;
294 vccio3-supply = <&vcc_io>;
295 vccio4-supply = <&vcc_18>;
296 vccio5-supply = <&vcc_io>;
297 vccio6-supply = <&vcc_io>;
298 pmuio-supply = <&vcc_io>;
299 };
300
301 &pinctrl {
302 ir {
303 ir_int: ir-int {
304 rockchip,pins = <2 RK_
305 };
306 };
307
308 pmic {
309 pmic_int_l: pmic-int-l {
310 rockchip,pins = <2 RK_
311 };
312 };
313
314 usb2 {
315 usb20_host_drv: usb20-host-drv
316 rockchip,pins = <0 RK_
317 };
318 };
319 };
320
321 &sdmmc {
322 bus-width = <4>;
323 cap-mmc-highspeed;
324 cap-sd-highspeed;
325 disable-wp;
326 max-frequency = <150000000>;
327 pinctrl-names = "default";
328 pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &
329 vmmc-supply = <&vcc_sd>;
330 status = "okay";
331 };
332
333 &spdif {
334 pinctrl-0 = <&spdifm0_tx>;
335 status = "okay";
336 };
337
338 &spi0 {
339 status = "okay";
340
341 flash@0 {
342 compatible = "jedec,spi-nor";
343 reg = <0>;
344
345 /* maximum speed for Rockchip
346 spi-max-frequency = <50000000>
347 };
348 };
349
350 &tsadc {
351 rockchip,hw-tshut-mode = <0>;
352 rockchip,hw-tshut-polarity = <0>;
353 status = "okay";
354 };
355
356 &uart2 {
357 status = "okay";
358 };
359
360 &u2phy {
361 status = "okay";
362
363 u2phy_host: host-port {
364 status = "okay";
365 };
366
367 u2phy_otg: otg-port {
368 status = "okay";
369 };
370 };
371
372 &usb20_otg {
373 dr_mode = "host";
374 status = "okay";
375 };
376
377 &usbdrd3 {
378 dr_mode = "host";
379 status = "okay";
380 };
381
382 &usb_host0_ehci {
383 status = "okay";
384 };
385
386 &usb_host0_ohci {
387 status = "okay";
388 };
389
390 &vop {
391 status = "okay";
392 };
393
394 &vop_mmu {
395 status = "okay";
396 };
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