1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /*
3 * Copyright (c) 2015 Heiko Stuebner <heiko@snt
4 */
5
6 #include <dt-bindings/clock/rk3368-cru.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/interrupt-controller/irq
9 #include <dt-bindings/interrupt-controller/arm
10 #include <dt-bindings/pinctrl/rockchip.h>
11 #include <dt-bindings/power/rk3368-power.h>
12 #include <dt-bindings/soc/rockchip,boot-mode.h
13 #include <dt-bindings/thermal/thermal.h>
14
15 / {
16 compatible = "rockchip,rk3368";
17 interrupt-parent = <&gic>;
18 #address-cells = <2>;
19 #size-cells = <2>;
20
21 aliases {
22 gpio0 = &gpio0;
23 gpio1 = &gpio1;
24 gpio2 = &gpio2;
25 gpio3 = &gpio3;
26 i2c0 = &i2c0;
27 i2c1 = &i2c1;
28 i2c2 = &i2c2;
29 i2c3 = &i2c3;
30 i2c4 = &i2c4;
31 i2c5 = &i2c5;
32 serial0 = &uart0;
33 serial1 = &uart1;
34 serial2 = &uart2;
35 serial3 = &uart3;
36 serial4 = &uart4;
37 spi0 = &spi0;
38 spi1 = &spi1;
39 spi2 = &spi2;
40 };
41
42 cpus {
43 #address-cells = <0x2>;
44 #size-cells = <0x0>;
45
46 cpu-map {
47 cluster0 {
48 core0 {
49 cpu =
50 };
51 core1 {
52 cpu =
53 };
54 core2 {
55 cpu =
56 };
57 core3 {
58 cpu =
59 };
60 };
61
62 cluster1 {
63 core0 {
64 cpu =
65 };
66 core1 {
67 cpu =
68 };
69 core2 {
70 cpu =
71 };
72 core3 {
73 cpu =
74 };
75 };
76 };
77
78 cpu_l0: cpu@0 {
79 device_type = "cpu";
80 compatible = "arm,cort
81 reg = <0x0 0x0>;
82 enable-method = "psci"
83 #cooling-cells = <2>;
84 };
85
86 cpu_l1: cpu@1 {
87 device_type = "cpu";
88 compatible = "arm,cort
89 reg = <0x0 0x1>;
90 enable-method = "psci"
91 #cooling-cells = <2>;
92 };
93
94 cpu_l2: cpu@2 {
95 device_type = "cpu";
96 compatible = "arm,cort
97 reg = <0x0 0x2>;
98 enable-method = "psci"
99 #cooling-cells = <2>;
100 };
101
102 cpu_l3: cpu@3 {
103 device_type = "cpu";
104 compatible = "arm,cort
105 reg = <0x0 0x3>;
106 enable-method = "psci"
107 #cooling-cells = <2>;
108 };
109
110 cpu_b0: cpu@100 {
111 device_type = "cpu";
112 compatible = "arm,cort
113 reg = <0x0 0x100>;
114 enable-method = "psci"
115 #cooling-cells = <2>;
116 };
117
118 cpu_b1: cpu@101 {
119 device_type = "cpu";
120 compatible = "arm,cort
121 reg = <0x0 0x101>;
122 enable-method = "psci"
123 #cooling-cells = <2>;
124 };
125
126 cpu_b2: cpu@102 {
127 device_type = "cpu";
128 compatible = "arm,cort
129 reg = <0x0 0x102>;
130 enable-method = "psci"
131 #cooling-cells = <2>;
132 };
133
134 cpu_b3: cpu@103 {
135 device_type = "cpu";
136 compatible = "arm,cort
137 reg = <0x0 0x103>;
138 enable-method = "psci"
139 #cooling-cells = <2>;
140 };
141 };
142
143 arm-pmu {
144 compatible = "arm,cortex-a53-p
145 interrupts = <GIC_SPI 112 IRQ_
146 <GIC_SPI 113 IRQ_
147 <GIC_SPI 114 IRQ_
148 <GIC_SPI 115 IRQ_
149 <GIC_SPI 116 IRQ_
150 <GIC_SPI 117 IRQ_
151 <GIC_SPI 118 IRQ_
152 <GIC_SPI 119 IRQ_
153 interrupt-affinity = <&cpu_l0>
154 <&cpu_l3>
155 <&cpu_b2>
156 };
157
158 psci {
159 compatible = "arm,psci-0.2";
160 method = "smc";
161 };
162
163 timer {
164 compatible = "arm,armv8-timer"
165 interrupts = <GIC_PPI 13
166 (GIC_CPU_MASK_SIMPLE(8
167 <GIC_PPI 14
168 (GIC_CPU_MASK_SIMPLE(8
169 <GIC_PPI 11
170 (GIC_CPU_MASK_SIMPLE(8
171 <GIC_PPI 10
172 (GIC_CPU_MASK_SIMPLE(8
173 };
174
175 xin24m: oscillator {
176 compatible = "fixed-clock";
177 clock-frequency = <24000000>;
178 clock-output-names = "xin24m";
179 #clock-cells = <0>;
180 };
181
182 sdmmc: mmc@ff0c0000 {
183 compatible = "rockchip,rk3368-
184 reg = <0x0 0xff0c0000 0x0 0x40
185 max-frequency = <150000000>;
186 clocks = <&cru HCLK_SDMMC>, <&
187 <&cru SCLK_SDMMC_DRV>
188 clock-names = "biu", "ciu", "c
189 fifo-depth = <0x100>;
190 interrupts = <GIC_SPI 32 IRQ_T
191 resets = <&cru SRST_MMC0>;
192 reset-names = "reset";
193 status = "disabled";
194 };
195
196 sdio0: mmc@ff0d0000 {
197 compatible = "rockchip,rk3368-
198 reg = <0x0 0xff0d0000 0x0 0x40
199 max-frequency = <150000000>;
200 clocks = <&cru HCLK_SDIO0>, <&
201 <&cru SCLK_SDIO0_DRV>
202 clock-names = "biu", "ciu", "c
203 fifo-depth = <0x100>;
204 interrupts = <GIC_SPI 33 IRQ_T
205 resets = <&cru SRST_SDIO0>;
206 reset-names = "reset";
207 status = "disabled";
208 };
209
210 emmc: mmc@ff0f0000 {
211 compatible = "rockchip,rk3368-
212 reg = <0x0 0xff0f0000 0x0 0x40
213 max-frequency = <150000000>;
214 clocks = <&cru HCLK_EMMC>, <&c
215 <&cru SCLK_EMMC_DRV>,
216 clock-names = "biu", "ciu", "c
217 fifo-depth = <0x100>;
218 interrupts = <GIC_SPI 35 IRQ_T
219 resets = <&cru SRST_EMMC>;
220 reset-names = "reset";
221 status = "disabled";
222 };
223
224 saradc: saradc@ff100000 {
225 compatible = "rockchip,saradc"
226 reg = <0x0 0xff100000 0x0 0x10
227 interrupts = <GIC_SPI 36 IRQ_T
228 #io-channel-cells = <1>;
229 clocks = <&cru SCLK_SARADC>, <
230 clock-names = "saradc", "apb_p
231 resets = <&cru SRST_SARADC>;
232 reset-names = "saradc-apb";
233 status = "disabled";
234 };
235
236 spi0: spi@ff110000 {
237 compatible = "rockchip,rk3368-
238 reg = <0x0 0xff110000 0x0 0x10
239 clocks = <&cru SCLK_SPI0>, <&c
240 clock-names = "spiclk", "apb_p
241 interrupts = <GIC_SPI 44 IRQ_T
242 pinctrl-names = "default";
243 pinctrl-0 = <&spi0_clk &spi0_t
244 #address-cells = <1>;
245 #size-cells = <0>;
246 status = "disabled";
247 };
248
249 spi1: spi@ff120000 {
250 compatible = "rockchip,rk3368-
251 reg = <0x0 0xff120000 0x0 0x10
252 clocks = <&cru SCLK_SPI1>, <&c
253 clock-names = "spiclk", "apb_p
254 interrupts = <GIC_SPI 45 IRQ_T
255 pinctrl-names = "default";
256 pinctrl-0 = <&spi1_clk &spi1_t
257 #address-cells = <1>;
258 #size-cells = <0>;
259 status = "disabled";
260 };
261
262 spi2: spi@ff130000 {
263 compatible = "rockchip,rk3368-
264 reg = <0x0 0xff130000 0x0 0x10
265 clocks = <&cru SCLK_SPI2>, <&c
266 clock-names = "spiclk", "apb_p
267 interrupts = <GIC_SPI 41 IRQ_T
268 pinctrl-names = "default";
269 pinctrl-0 = <&spi2_clk &spi2_t
270 #address-cells = <1>;
271 #size-cells = <0>;
272 status = "disabled";
273 };
274
275 i2c2: i2c@ff140000 {
276 compatible = "rockchip,rk3368-
277 reg = <0x0 0xff140000 0x0 0x10
278 interrupts = <GIC_SPI 62 IRQ_T
279 #address-cells = <1>;
280 #size-cells = <0>;
281 clock-names = "i2c";
282 clocks = <&cru PCLK_I2C2>;
283 pinctrl-names = "default";
284 pinctrl-0 = <&i2c2_xfer>;
285 status = "disabled";
286 };
287
288 i2c3: i2c@ff150000 {
289 compatible = "rockchip,rk3368-
290 reg = <0x0 0xff150000 0x0 0x10
291 interrupts = <GIC_SPI 63 IRQ_T
292 #address-cells = <1>;
293 #size-cells = <0>;
294 clock-names = "i2c";
295 clocks = <&cru PCLK_I2C3>;
296 pinctrl-names = "default";
297 pinctrl-0 = <&i2c3_xfer>;
298 status = "disabled";
299 };
300
301 i2c4: i2c@ff160000 {
302 compatible = "rockchip,rk3368-
303 reg = <0x0 0xff160000 0x0 0x10
304 interrupts = <GIC_SPI 64 IRQ_T
305 #address-cells = <1>;
306 #size-cells = <0>;
307 clock-names = "i2c";
308 clocks = <&cru PCLK_I2C4>;
309 pinctrl-names = "default";
310 pinctrl-0 = <&i2c4_xfer>;
311 status = "disabled";
312 };
313
314 i2c5: i2c@ff170000 {
315 compatible = "rockchip,rk3368-
316 reg = <0x0 0xff170000 0x0 0x10
317 interrupts = <GIC_SPI 65 IRQ_T
318 #address-cells = <1>;
319 #size-cells = <0>;
320 clock-names = "i2c";
321 clocks = <&cru PCLK_I2C5>;
322 pinctrl-names = "default";
323 pinctrl-0 = <&i2c5_xfer>;
324 status = "disabled";
325 };
326
327 uart0: serial@ff180000 {
328 compatible = "rockchip,rk3368-
329 reg = <0x0 0xff180000 0x0 0x10
330 clock-frequency = <24000000>;
331 clocks = <&cru SCLK_UART0>, <&
332 clock-names = "baudclk", "apb_
333 interrupts = <GIC_SPI 55 IRQ_T
334 reg-shift = <2>;
335 reg-io-width = <4>;
336 status = "disabled";
337 };
338
339 uart1: serial@ff190000 {
340 compatible = "rockchip,rk3368-
341 reg = <0x0 0xff190000 0x0 0x10
342 clock-frequency = <24000000>;
343 clocks = <&cru SCLK_UART1>, <&
344 clock-names = "baudclk", "apb_
345 interrupts = <GIC_SPI 56 IRQ_T
346 reg-shift = <2>;
347 reg-io-width = <4>;
348 status = "disabled";
349 };
350
351 uart3: serial@ff1b0000 {
352 compatible = "rockchip,rk3368-
353 reg = <0x0 0xff1b0000 0x0 0x10
354 clock-frequency = <24000000>;
355 clocks = <&cru SCLK_UART3>, <&
356 clock-names = "baudclk", "apb_
357 interrupts = <GIC_SPI 58 IRQ_T
358 reg-shift = <2>;
359 reg-io-width = <4>;
360 status = "disabled";
361 };
362
363 uart4: serial@ff1c0000 {
364 compatible = "rockchip,rk3368-
365 reg = <0x0 0xff1c0000 0x0 0x10
366 clock-frequency = <24000000>;
367 clocks = <&cru SCLK_UART4>, <&
368 clock-names = "baudclk", "apb_
369 interrupts = <GIC_SPI 59 IRQ_T
370 reg-shift = <2>;
371 reg-io-width = <4>;
372 status = "disabled";
373 };
374
375 dmac_peri: dma-controller@ff250000 {
376 compatible = "arm,pl330", "arm
377 reg = <0x0 0xff250000 0x0 0x40
378 interrupts = <GIC_SPI 2 IRQ_TY
379 <GIC_SPI 3 IRQ_TY
380 #dma-cells = <1>;
381 arm,pl330-broken-no-flushp;
382 arm,pl330-periph-burst;
383 clocks = <&cru ACLK_DMAC_PERI>
384 clock-names = "apb_pclk";
385 };
386
387 thermal-zones {
388 cpu_thermal: cpu-thermal {
389 polling-delay-passive
390 polling-delay = <5000>
391
392 thermal-sensors = <&ts
393
394 trips {
395 cpu_alert0: cp
396 temper
397 hyster
398 type =
399 };
400 cpu_alert1: cp
401 temper
402 hyster
403 type =
404 };
405 cpu_crit: cpu_
406 temper
407 hyster
408 type =
409 };
410 };
411
412 cooling-maps {
413 map0 {
414 trip =
415 coolin
416 <&cpu_
417 <&cpu_
418 <&cpu_
419 <&cpu_
420 };
421 map1 {
422 trip =
423 coolin
424 <&cpu_
425 <&cpu_
426 <&cpu_
427 <&cpu_
428 };
429 };
430 };
431
432 gpu_thermal: gpu-thermal {
433 polling-delay-passive
434 polling-delay = <5000>
435
436 thermal-sensors = <&ts
437
438 trips {
439 gpu_alert0: gp
440 temper
441 hyster
442 type =
443 };
444 gpu_crit: gpu_
445 temper
446 hyster
447 type =
448 };
449 };
450
451 cooling-maps {
452 map0 {
453 trip =
454 coolin
455 <&cpu_
456 <&cpu_
457 <&cpu_
458 <&cpu_
459 };
460 };
461 };
462 };
463
464 tsadc: tsadc@ff280000 {
465 compatible = "rockchip,rk3368-
466 reg = <0x0 0xff280000 0x0 0x10
467 interrupts = <GIC_SPI 37 IRQ_T
468 clocks = <&cru SCLK_TSADC>, <&
469 clock-names = "tsadc", "apb_pc
470 resets = <&cru SRST_TSADC>;
471 reset-names = "tsadc-apb";
472 pinctrl-names = "init", "defau
473 pinctrl-0 = <&otp_pin>;
474 pinctrl-1 = <&otp_out>;
475 pinctrl-2 = <&otp_pin>;
476 #thermal-sensor-cells = <1>;
477 rockchip,hw-tshut-temp = <9500
478 status = "disabled";
479 };
480
481 gmac: ethernet@ff290000 {
482 compatible = "rockchip,rk3368-
483 reg = <0x0 0xff290000 0x0 0x10
484 interrupts = <GIC_SPI 27 IRQ_T
485 interrupt-names = "macirq";
486 rockchip,grf = <&grf>;
487 clocks = <&cru SCLK_MAC>,
488 <&cru SCLK_MAC_RX>, <&
489 <&cru SCLK_MACREF>, <&
490 <&cru ACLK_GMAC>, <&cr
491 clock-names = "stmmaceth",
492 "mac_clk_rx", "mac_clk
493 "clk_mac_ref", "clk_ma
494 "aclk_mac", "pclk_mac"
495 status = "disabled";
496 };
497
498 usb_host0_ehci: usb@ff500000 {
499 compatible = "generic-ehci";
500 reg = <0x0 0xff500000 0x0 0x10
501 interrupts = <GIC_SPI 24 IRQ_T
502 clocks = <&cru HCLK_HOST0>;
503 status = "disabled";
504 };
505
506 usb_otg: usb@ff580000 {
507 compatible = "rockchip,rk3368-
508 "snps,dwc2";
509 reg = <0x0 0xff580000 0x0 0x40
510 interrupts = <GIC_SPI 23 IRQ_T
511 clocks = <&cru HCLK_OTG0>;
512 clock-names = "otg";
513 dr_mode = "otg";
514 g-np-tx-fifo-size = <16>;
515 g-rx-fifo-size = <275>;
516 g-tx-fifo-size = <256 128 128
517 status = "disabled";
518 };
519
520 dmac_bus: dma-controller@ff600000 {
521 compatible = "arm,pl330", "arm
522 reg = <0x0 0xff600000 0x0 0x40
523 interrupts = <GIC_SPI 0 IRQ_TY
524 <GIC_SPI 1 IRQ_TY
525 #dma-cells = <1>;
526 arm,pl330-broken-no-flushp;
527 arm,pl330-periph-burst;
528 clocks = <&cru ACLK_DMAC_BUS>;
529 clock-names = "apb_pclk";
530 };
531
532 i2c0: i2c@ff650000 {
533 compatible = "rockchip,rk3368-
534 reg = <0x0 0xff650000 0x0 0x10
535 clocks = <&cru PCLK_I2C0>;
536 clock-names = "i2c";
537 interrupts = <GIC_SPI 60 IRQ_T
538 pinctrl-names = "default";
539 pinctrl-0 = <&i2c0_xfer>;
540 #address-cells = <1>;
541 #size-cells = <0>;
542 status = "disabled";
543 };
544
545 i2c1: i2c@ff660000 {
546 compatible = "rockchip,rk3368-
547 reg = <0x0 0xff660000 0x0 0x10
548 interrupts = <GIC_SPI 61 IRQ_T
549 #address-cells = <1>;
550 #size-cells = <0>;
551 clock-names = "i2c";
552 clocks = <&cru PCLK_I2C1>;
553 pinctrl-names = "default";
554 pinctrl-0 = <&i2c1_xfer>;
555 status = "disabled";
556 };
557
558 pwm0: pwm@ff680000 {
559 compatible = "rockchip,rk3368-
560 reg = <0x0 0xff680000 0x0 0x10
561 #pwm-cells = <3>;
562 pinctrl-names = "default";
563 pinctrl-0 = <&pwm0_pin>;
564 clocks = <&cru PCLK_PWM1>;
565 status = "disabled";
566 };
567
568 pwm1: pwm@ff680010 {
569 compatible = "rockchip,rk3368-
570 reg = <0x0 0xff680010 0x0 0x10
571 #pwm-cells = <3>;
572 pinctrl-names = "default";
573 pinctrl-0 = <&pwm1_pin>;
574 clocks = <&cru PCLK_PWM1>;
575 status = "disabled";
576 };
577
578 pwm2: pwm@ff680020 {
579 compatible = "rockchip,rk3368-
580 reg = <0x0 0xff680020 0x0 0x10
581 #pwm-cells = <3>;
582 clocks = <&cru PCLK_PWM1>;
583 status = "disabled";
584 };
585
586 pwm3: pwm@ff680030 {
587 compatible = "rockchip,rk3368-
588 reg = <0x0 0xff680030 0x0 0x10
589 #pwm-cells = <3>;
590 pinctrl-names = "default";
591 pinctrl-0 = <&pwm3_pin>;
592 clocks = <&cru PCLK_PWM1>;
593 status = "disabled";
594 };
595
596 uart2: serial@ff690000 {
597 compatible = "rockchip,rk3368-
598 reg = <0x0 0xff690000 0x0 0x10
599 clocks = <&cru SCLK_UART2>, <&
600 clock-names = "baudclk", "apb_
601 interrupts = <GIC_SPI 57 IRQ_T
602 pinctrl-names = "default";
603 pinctrl-0 = <&uart2_xfer>;
604 reg-shift = <2>;
605 reg-io-width = <4>;
606 status = "disabled";
607 };
608
609 mbox: mbox@ff6b0000 {
610 compatible = "rockchip,rk3368-
611 reg = <0x0 0xff6b0000 0x0 0x10
612 interrupts = <GIC_SPI 146 IRQ_
613 <GIC_SPI 147 IRQ_
614 <GIC_SPI 148 IRQ_
615 <GIC_SPI 149 IRQ_
616 clocks = <&cru PCLK_MAILBOX>;
617 clock-names = "pclk_mailbox";
618 #mbox-cells = <1>;
619 status = "disabled";
620 };
621
622 pmu: power-management@ff730000 {
623 compatible = "rockchip,rk3368-
624 reg = <0x0 0xff730000 0x0 0x10
625
626 power: power-controller {
627 compatible = "rockchip
628 #power-domain-cells =
629 #address-cells = <1>;
630 #size-cells = <0>;
631
632 /*
633 * Note: Although SCLK
634 * of device without i
635 * synchronous reset.
636 *
637 * The clocks on the w
638 * ACLK_IEP/ACLK_VIP/A
639 * ACLK_ISP/ACLK_VOP1
640 * ACLK_RGA is on ACLK
641 * The others (HCLK_*,
642 *
643 * Which clock are dev
644 * clocks
645 * *_IEP
646 * *_ISP
647 * *_VIP
648 * *_VOP*
649 * *_RGA
650 * *_EDP*
651 * *_DPHY*
652 * *_HDMI
653 * *_MIPI_*
654 */
655 power-domain@RK3368_PD
656 reg = <RK3368_
657 clocks = <&cru
658 <&cru
659 <&cru
660 <&cru
661 <&cru
662 <&cru
663 <&cru
664 <&cru
665 <&cru
666 <&cru
667 <&cru
668 <&cru
669 <&cru
670 <&cru
671 <&cru
672 <&cru
673 <&cru
674 <&cru
675 <&cru
676 <&cru
677 <&cru
678 <&cru
679 <&cru
680 <&cru
681 <&cru
682 <&cru
683 <&cru
684 <&cru
685 <&cru
686 <&cru
687 pm_qos = <&qos
688 <&qos
689 <&qos
690 <&qos
691 <&qos
692 <&qos
693 <&qos
694 <&qos
695 <&qos
696 #power-domain-
697 };
698
699 /*
700 * Note: ACLK_VCODEC/H
701 * (video endecoder &
702 * ACLK_VCODEC_NIU and
703 */
704 power-domain@RK3368_PD
705 reg = <RK3368_
706 clocks = <&cru
707 <&cru
708 <&cru
709 <&cru
710 pm_qos = <&qos
711 <&qos
712 <&qos
713 #power-domain-
714 };
715
716 /*
717 * Note: ACLK_GPU is t
718 * and on the ACLK_GPU
719 */
720 power-domain@RK3368_PD
721 reg = <RK3368_
722 clocks = <&cru
723 <&cru
724 <&cru
725 pm_qos = <&qos
726 #power-domain-
727 };
728 };
729 };
730
731 pmugrf: syscon@ff738000 {
732 compatible = "rockchip,rk3368-
733 reg = <0x0 0xff738000 0x0 0x10
734
735 pmu_io_domains: io-domains {
736 compatible = "rockchip
737 status = "disabled";
738 };
739
740 reboot-mode {
741 compatible = "syscon-r
742 offset = <0x200>;
743 mode-normal = <BOOT_NO
744 mode-recovery = <BOOT_
745 mode-bootloader = <BOO
746 mode-loader = <BOOT_BL
747 };
748 };
749
750 cru: clock-controller@ff760000 {
751 compatible = "rockchip,rk3368-
752 reg = <0x0 0xff760000 0x0 0x10
753 clocks = <&xin24m>;
754 clock-names = "xin24m";
755 rockchip,grf = <&grf>;
756 #clock-cells = <1>;
757 #reset-cells = <1>;
758 };
759
760 grf: syscon@ff770000 {
761 compatible = "rockchip,rk3368-
762 reg = <0x0 0xff770000 0x0 0x10
763
764 io_domains: io-domains {
765 compatible = "rockchip
766 status = "disabled";
767 };
768 };
769
770 wdt: watchdog@ff800000 {
771 compatible = "rockchip,rk3368-
772 reg = <0x0 0xff800000 0x0 0x10
773 clocks = <&cru PCLK_WDT>;
774 interrupts = <GIC_SPI 79 IRQ_T
775 status = "disabled";
776 };
777
778 timer0: timer@ff810000 {
779 compatible = "rockchip,rk3368-
780 reg = <0x0 0xff810000 0x0 0x20
781 interrupts = <GIC_SPI 66 IRQ_T
782 clocks = <&cru PCLK_TIMER0>, <
783 clock-names = "pclk", "timer";
784 };
785
786 spdif: spdif@ff880000 {
787 compatible = "rockchip,rk3368-
788 reg = <0x0 0xff880000 0x0 0x10
789 interrupts = <GIC_SPI 54 IRQ_T
790 clocks = <&cru SCLK_SPDIF_8CH>
791 clock-names = "mclk", "hclk";
792 dmas = <&dmac_bus 3>;
793 dma-names = "tx";
794 pinctrl-names = "default";
795 pinctrl-0 = <&spdif_tx>;
796 #sound-dai-cells = <0>;
797 status = "disabled";
798 };
799
800 i2s_2ch: i2s-2ch@ff890000 {
801 compatible = "rockchip,rk3368-
802 reg = <0x0 0xff890000 0x0 0x10
803 interrupts = <GIC_SPI 40 IRQ_T
804 clock-names = "i2s_clk", "i2s_
805 clocks = <&cru SCLK_I2S_2CH>,
806 dmas = <&dmac_bus 6>, <&dmac_b
807 dma-names = "tx", "rx";
808 #sound-dai-cells = <0>;
809 status = "disabled";
810 };
811
812 i2s_8ch: i2s-8ch@ff898000 {
813 compatible = "rockchip,rk3368-
814 reg = <0x0 0xff898000 0x0 0x10
815 interrupts = <GIC_SPI 53 IRQ_T
816 clock-names = "i2s_clk", "i2s_
817 clocks = <&cru SCLK_I2S_8CH>,
818 dmas = <&dmac_bus 0>, <&dmac_b
819 dma-names = "tx", "rx";
820 pinctrl-names = "default";
821 pinctrl-0 = <&i2s_8ch_bus>;
822 #sound-dai-cells = <0>;
823 status = "disabled";
824 };
825
826 iep_mmu: iommu@ff900800 {
827 compatible = "rockchip,iommu";
828 reg = <0x0 0xff900800 0x0 0x10
829 interrupts = <GIC_SPI 17 IRQ_T
830 clocks = <&cru ACLK_IEP>, <&cr
831 clock-names = "aclk", "iface";
832 power-domains = <&power RK3368
833 #iommu-cells = <0>;
834 status = "disabled";
835 };
836
837 isp_mmu: iommu@ff914000 {
838 compatible = "rockchip,iommu";
839 reg = <0x0 0xff914000 0x0 0x10
840 <0x0 0xff915000 0x0 0x10
841 interrupts = <GIC_SPI 14 IRQ_T
842 clocks = <&cru ACLK_ISP>, <&cr
843 clock-names = "aclk", "iface";
844 #iommu-cells = <0>;
845 power-domains = <&power RK3368
846 rockchip,disable-mmu-reset;
847 status = "disabled";
848 };
849
850 vop_mmu: iommu@ff930300 {
851 compatible = "rockchip,iommu";
852 reg = <0x0 0xff930300 0x0 0x10
853 interrupts = <GIC_SPI 15 IRQ_T
854 clocks = <&cru ACLK_VOP>, <&cr
855 clock-names = "aclk", "iface";
856 power-domains = <&power RK3368
857 #iommu-cells = <0>;
858 status = "disabled";
859 };
860
861 hevc_mmu: iommu@ff9a0440 {
862 compatible = "rockchip,iommu";
863 reg = <0x0 0xff9a0440 0x0 0x40
864 <0x0 0xff9a0480 0x0 0x40
865 interrupts = <GIC_SPI 12 IRQ_T
866 clocks = <&cru ACLK_VIDEO>, <&
867 clock-names = "aclk", "iface";
868 #iommu-cells = <0>;
869 status = "disabled";
870 };
871
872 vpu_mmu: iommu@ff9a0800 {
873 compatible = "rockchip,iommu";
874 reg = <0x0 0xff9a0800 0x0 0x10
875 interrupts = <GIC_SPI 9 IRQ_TY
876 <GIC_SPI 10 IRQ_T
877 clocks = <&cru ACLK_VIDEO>, <&
878 clock-names = "aclk", "iface";
879 #iommu-cells = <0>;
880 status = "disabled";
881 };
882
883 qos_iep: qos@ffad0000 {
884 compatible = "rockchip,rk3368-
885 reg = <0x0 0xffad0000 0x0 0x20
886 };
887
888 qos_isp_r0: qos@ffad0080 {
889 compatible = "rockchip,rk3368-
890 reg = <0x0 0xffad0080 0x0 0x20
891 };
892
893 qos_isp_r1: qos@ffad0100 {
894 compatible = "rockchip,rk3368-
895 reg = <0x0 0xffad0100 0x0 0x20
896 };
897
898 qos_isp_w0: qos@ffad0180 {
899 compatible = "rockchip,rk3368-
900 reg = <0x0 0xffad0180 0x0 0x20
901 };
902
903 qos_isp_w1: qos@ffad0200 {
904 compatible = "rockchip,rk3368-
905 reg = <0x0 0xffad0200 0x0 0x20
906 };
907
908 qos_vip: qos@ffad0280 {
909 compatible = "rockchip,rk3368-
910 reg = <0x0 0xffad0280 0x0 0x20
911 };
912
913 qos_vop: qos@ffad0300 {
914 compatible = "rockchip,rk3368-
915 reg = <0x0 0xffad0300 0x0 0x20
916 };
917
918 qos_rga_r: qos@ffad0380 {
919 compatible = "rockchip,rk3368-
920 reg = <0x0 0xffad0380 0x0 0x20
921 };
922
923 qos_rga_w: qos@ffad0400 {
924 compatible = "rockchip,rk3368-
925 reg = <0x0 0xffad0400 0x0 0x20
926 };
927
928 qos_hevc_r: qos@ffae0000 {
929 compatible = "rockchip,rk3368-
930 reg = <0x0 0xffae0000 0x0 0x20
931 };
932
933 qos_vpu_r: qos@ffae0100 {
934 compatible = "rockchip,rk3368-
935 reg = <0x0 0xffae0100 0x0 0x20
936 };
937
938 qos_vpu_w: qos@ffae0180 {
939 compatible = "rockchip,rk3368-
940 reg = <0x0 0xffae0180 0x0 0x20
941 };
942
943 qos_gpu: qos@ffaf0000 {
944 compatible = "rockchip,rk3368-
945 reg = <0x0 0xffaf0000 0x0 0x20
946 };
947
948 efuse256: efuse@ffb00000 {
949 compatible = "rockchip,rk3368-
950 reg = <0x0 0xffb00000 0x0 0x20
951 #address-cells = <1>;
952 #size-cells = <1>;
953 clocks = <&cru PCLK_EFUSE256>;
954 clock-names = "pclk_efuse";
955
956 cpu_leakage: cpu-leakage@17 {
957 reg = <0x17 0x1>;
958 };
959 temp_adjust: temp-adjust@1f {
960 reg = <0x1f 0x1>;
961 };
962 };
963
964 gic: interrupt-controller@ffb71000 {
965 compatible = "arm,gic-400";
966 interrupt-controller;
967 #interrupt-cells = <3>;
968 #address-cells = <0>;
969
970 reg = <0x0 0xffb71000 0x0 0x10
971 <0x0 0xffb72000 0x0 0x20
972 <0x0 0xffb74000 0x0 0x20
973 <0x0 0xffb76000 0x0 0x20
974 interrupts = <GIC_PPI 9
975 (GIC_CPU_MASK_SIMPLE(8)
976 };
977
978 pinctrl: pinctrl {
979 compatible = "rockchip,rk3368-
980 rockchip,grf = <&grf>;
981 rockchip,pmu = <&pmugrf>;
982 #address-cells = <0x2>;
983 #size-cells = <0x2>;
984 ranges;
985
986 gpio0: gpio@ff750000 {
987 compatible = "rockchip
988 reg = <0x0 0xff750000
989 clocks = <&cru PCLK_GP
990 interrupts = <GIC_SPI
991
992 gpio-controller;
993 #gpio-cells = <0x2>;
994
995 interrupt-controller;
996 #interrupt-cells = <0x
997 };
998
999 gpio1: gpio@ff780000 {
1000 compatible = "rockchi
1001 reg = <0x0 0xff780000
1002 clocks = <&cru PCLK_G
1003 interrupts = <GIC_SPI
1004
1005 gpio-controller;
1006 #gpio-cells = <0x2>;
1007
1008 interrupt-controller;
1009 #interrupt-cells = <0
1010 };
1011
1012 gpio2: gpio@ff790000 {
1013 compatible = "rockchi
1014 reg = <0x0 0xff790000
1015 clocks = <&cru PCLK_G
1016 interrupts = <GIC_SPI
1017
1018 gpio-controller;
1019 #gpio-cells = <0x2>;
1020
1021 interrupt-controller;
1022 #interrupt-cells = <0
1023 };
1024
1025 gpio3: gpio@ff7a0000 {
1026 compatible = "rockchi
1027 reg = <0x0 0xff7a0000
1028 clocks = <&cru PCLK_G
1029 interrupts = <GIC_SPI
1030
1031 gpio-controller;
1032 #gpio-cells = <0x2>;
1033
1034 interrupt-controller;
1035 #interrupt-cells = <0
1036 };
1037
1038 pcfg_pull_up: pcfg-pull-up {
1039 bias-pull-up;
1040 };
1041
1042 pcfg_pull_down: pcfg-pull-dow
1043 bias-pull-down;
1044 };
1045
1046 pcfg_pull_none: pcfg-pull-non
1047 bias-disable;
1048 };
1049
1050 pcfg_pull_none_12ma: pcfg-pul
1051 bias-disable;
1052 drive-strength = <12>
1053 };
1054
1055 emmc {
1056 emmc_clk: emmc-clk {
1057 rockchip,pins
1058 };
1059
1060 emmc_cmd: emmc-cmd {
1061 rockchip,pins
1062 };
1063
1064 emmc_pwr: emmc-pwr {
1065 rockchip,pins
1066 };
1067
1068 emmc_bus1: emmc-bus1
1069 rockchip,pins
1070 };
1071
1072 emmc_bus4: emmc-bus4
1073 rockchip,pins
1074
1075
1076
1077 };
1078
1079 emmc_bus8: emmc-bus8
1080 rockchip,pins
1081
1082
1083
1084
1085
1086
1087
1088 };
1089 };
1090
1091 gmac {
1092 rgmii_pins: rgmii-pin
1093 rockchip,pins
1094
1095
1096
1097
1098
1099
1100
1101
1102
1103
1104
1105
1106
1107
1108 };
1109
1110 rmii_pins: rmii-pins
1111 rockchip,pins
1112
1113
1114
1115
1116
1117
1118
1119
1120
1121 };
1122 };
1123
1124 i2c0 {
1125 i2c0_xfer: i2c0-xfer
1126 rockchip,pins
1127
1128 };
1129 };
1130
1131 i2c1 {
1132 i2c1_xfer: i2c1-xfer
1133 rockchip,pins
1134
1135 };
1136 };
1137
1138 i2c2 {
1139 i2c2_xfer: i2c2-xfer
1140 rockchip,pins
1141
1142 };
1143 };
1144
1145 i2c3 {
1146 i2c3_xfer: i2c3-xfer
1147 rockchip,pins
1148
1149 };
1150 };
1151
1152 i2c4 {
1153 i2c4_xfer: i2c4-xfer
1154 rockchip,pins
1155
1156 };
1157 };
1158
1159 i2c5 {
1160 i2c5_xfer: i2c5-xfer
1161 rockchip,pins
1162
1163 };
1164 };
1165
1166 i2s {
1167 i2s_8ch_bus: i2s-8ch-
1168 rockchip,pins
1169
1170
1171
1172
1173
1174
1175
1176
1177 };
1178 };
1179
1180 pwm0 {
1181 pwm0_pin: pwm0-pin {
1182 rockchip,pins
1183 };
1184 };
1185
1186 pwm1 {
1187 pwm1_pin: pwm1-pin {
1188 rockchip,pins
1189 };
1190 };
1191
1192 pwm3 {
1193 pwm3_pin: pwm3-pin {
1194 rockchip,pins
1195 };
1196 };
1197
1198 sdio0 {
1199 sdio0_bus1: sdio0-bus
1200 rockchip,pins
1201 };
1202
1203 sdio0_bus4: sdio0-bus
1204 rockchip,pins
1205
1206
1207
1208 };
1209
1210 sdio0_cmd: sdio0-cmd
1211 rockchip,pins
1212 };
1213
1214 sdio0_clk: sdio0-clk
1215 rockchip,pins
1216 };
1217
1218 sdio0_cd: sdio0-cd {
1219 rockchip,pins
1220 };
1221
1222 sdio0_wp: sdio0-wp {
1223 rockchip,pins
1224 };
1225
1226 sdio0_pwr: sdio0-pwr
1227 rockchip,pins
1228 };
1229
1230 sdio0_bkpwr: sdio0-bk
1231 rockchip,pins
1232 };
1233
1234 sdio0_int: sdio0-int
1235 rockchip,pins
1236 };
1237 };
1238
1239 sdmmc {
1240 sdmmc_clk: sdmmc-clk
1241 rockchip,pins
1242 };
1243
1244 sdmmc_cmd: sdmmc-cmd
1245 rockchip,pins
1246 };
1247
1248 sdmmc_cd: sdmmc-cd {
1249 rockchip,pins
1250 };
1251
1252 sdmmc_bus1: sdmmc-bus
1253 rockchip,pins
1254 };
1255
1256 sdmmc_bus4: sdmmc-bus
1257 rockchip,pins
1258
1259
1260
1261 };
1262 };
1263
1264 spdif {
1265 spdif_tx: spdif-tx {
1266 rockchip,pins
1267 };
1268 };
1269
1270 spi0 {
1271 spi0_clk: spi0-clk {
1272 rockchip,pins
1273 };
1274 spi0_cs0: spi0-cs0 {
1275 rockchip,pins
1276 };
1277 spi0_cs1: spi0-cs1 {
1278 rockchip,pins
1279 };
1280 spi0_tx: spi0-tx {
1281 rockchip,pins
1282 };
1283 spi0_rx: spi0-rx {
1284 rockchip,pins
1285 };
1286 };
1287
1288 spi1 {
1289 spi1_clk: spi1-clk {
1290 rockchip,pins
1291 };
1292 spi1_cs0: spi1-cs0 {
1293 rockchip,pins
1294 };
1295 spi1_cs1: spi1-cs1 {
1296 rockchip,pins
1297 };
1298 spi1_rx: spi1-rx {
1299 rockchip,pins
1300 };
1301 spi1_tx: spi1-tx {
1302 rockchip,pins
1303 };
1304 };
1305
1306 spi2 {
1307 spi2_clk: spi2-clk {
1308 rockchip,pins
1309 };
1310 spi2_cs0: spi2-cs0 {
1311 rockchip,pins
1312 };
1313 spi2_rx: spi2-rx {
1314 rockchip,pins
1315 };
1316 spi2_tx: spi2-tx {
1317 rockchip,pins
1318 };
1319 };
1320
1321 tsadc {
1322 otp_pin: otp-pin {
1323 rockchip,pins
1324 };
1325
1326 otp_out: otp-out {
1327 rockchip,pins
1328 };
1329 };
1330
1331 uart0 {
1332 uart0_xfer: uart0-xfe
1333 rockchip,pins
1334
1335 };
1336
1337 uart0_cts: uart0-cts
1338 rockchip,pins
1339 };
1340
1341 uart0_rts: uart0-rts
1342 rockchip,pins
1343 };
1344 };
1345
1346 uart1 {
1347 uart1_xfer: uart1-xfe
1348 rockchip,pins
1349
1350 };
1351
1352 uart1_cts: uart1-cts
1353 rockchip,pins
1354 };
1355
1356 uart1_rts: uart1-rts
1357 rockchip,pins
1358 };
1359 };
1360
1361 uart2 {
1362 uart2_xfer: uart2-xfe
1363 rockchip,pins
1364
1365 };
1366 /* no rts / cts for u
1367 };
1368
1369 uart3 {
1370 uart3_xfer: uart3-xfe
1371 rockchip,pins
1372
1373 };
1374
1375 uart3_cts: uart3-cts
1376 rockchip,pins
1377 };
1378
1379 uart3_rts: uart3-rts
1380 rockchip,pins
1381 };
1382 };
1383
1384 uart4 {
1385 uart4_xfer: uart4-xfe
1386 rockchip,pins
1387
1388 };
1389
1390 uart4_cts: uart4-cts
1391 rockchip,pins
1392 };
1393
1394 uart4_rts: uart4-rts
1395 rockchip,pins
1396 };
1397 };
1398 };
1399 };
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