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Linux/scripts/dtc/include-prefixes/arm64/rockchip/rk3368.dtsi

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Diff markup

Differences between /scripts/dtc/include-prefixes/arm64/rockchip/rk3368.dtsi (Version linux-6.12-rc7) and /scripts/dtc/include-prefixes/arm64/rockchip/rk3368.dtsi (Version linux-4.13.16)


  1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)  << 
  2 /*                                                  1 /*
  3  * Copyright (c) 2015 Heiko Stuebner <heiko@snt      2  * Copyright (c) 2015 Heiko Stuebner <heiko@sntech.de>
                                                   >>   3  *
                                                   >>   4  * This file is dual-licensed: you can use it either under the terms
                                                   >>   5  * of the GPL or the X11 license, at your option. Note that this dual
                                                   >>   6  * licensing only applies to this file, and not this project as a
                                                   >>   7  * whole.
                                                   >>   8  *
                                                   >>   9  *  a) This library is free software; you can redistribute it and/or
                                                   >>  10  *     modify it under the terms of the GNU General Public License as
                                                   >>  11  *     published by the Free Software Foundation; either version 2 of the
                                                   >>  12  *     License, or (at your option) any later version.
                                                   >>  13  *
                                                   >>  14  *     This library is distributed in the hope that it will be useful,
                                                   >>  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
                                                   >>  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
                                                   >>  17  *     GNU General Public License for more details.
                                                   >>  18  *
                                                   >>  19  * Or, alternatively,
                                                   >>  20  *
                                                   >>  21  *  b) Permission is hereby granted, free of charge, to any person
                                                   >>  22  *     obtaining a copy of this software and associated documentation
                                                   >>  23  *     files (the "Software"), to deal in the Software without
                                                   >>  24  *     restriction, including without limitation the rights to use,
                                                   >>  25  *     copy, modify, merge, publish, distribute, sublicense, and/or
                                                   >>  26  *     sell copies of the Software, and to permit persons to whom the
                                                   >>  27  *     Software is furnished to do so, subject to the following
                                                   >>  28  *     conditions:
                                                   >>  29  *
                                                   >>  30  *     The above copyright notice and this permission notice shall be
                                                   >>  31  *     included in all copies or substantial portions of the Software.
                                                   >>  32  *
                                                   >>  33  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
                                                   >>  34  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
                                                   >>  35  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
                                                   >>  36  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
                                                   >>  37  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
                                                   >>  38  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
                                                   >>  39  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
                                                   >>  40  *     OTHER DEALINGS IN THE SOFTWARE.
  4  */                                                41  */
  5                                                    42 
  6 #include <dt-bindings/clock/rk3368-cru.h>          43 #include <dt-bindings/clock/rk3368-cru.h>
  7 #include <dt-bindings/gpio/gpio.h>                 44 #include <dt-bindings/gpio/gpio.h>
  8 #include <dt-bindings/interrupt-controller/irq     45 #include <dt-bindings/interrupt-controller/irq.h>
  9 #include <dt-bindings/interrupt-controller/arm     46 #include <dt-bindings/interrupt-controller/arm-gic.h>
 10 #include <dt-bindings/pinctrl/rockchip.h>          47 #include <dt-bindings/pinctrl/rockchip.h>
 11 #include <dt-bindings/power/rk3368-power.h>    << 
 12 #include <dt-bindings/soc/rockchip,boot-mode.h     48 #include <dt-bindings/soc/rockchip,boot-mode.h>
 13 #include <dt-bindings/thermal/thermal.h>           49 #include <dt-bindings/thermal/thermal.h>
 14                                                    50 
 15 / {                                                51 / {
 16         compatible = "rockchip,rk3368";            52         compatible = "rockchip,rk3368";
 17         interrupt-parent = <&gic>;                 53         interrupt-parent = <&gic>;
 18         #address-cells = <2>;                      54         #address-cells = <2>;
 19         #size-cells = <2>;                         55         #size-cells = <2>;
 20                                                    56 
 21         aliases {                                  57         aliases {
 22                 gpio0 = &gpio0;                !!  58                 ethernet0 = &gmac;
 23                 gpio1 = &gpio1;                << 
 24                 gpio2 = &gpio2;                << 
 25                 gpio3 = &gpio3;                << 
 26                 i2c0 = &i2c0;                      59                 i2c0 = &i2c0;
 27                 i2c1 = &i2c1;                      60                 i2c1 = &i2c1;
 28                 i2c2 = &i2c2;                      61                 i2c2 = &i2c2;
 29                 i2c3 = &i2c3;                      62                 i2c3 = &i2c3;
 30                 i2c4 = &i2c4;                      63                 i2c4 = &i2c4;
 31                 i2c5 = &i2c5;                      64                 i2c5 = &i2c5;
 32                 serial0 = &uart0;                  65                 serial0 = &uart0;
 33                 serial1 = &uart1;                  66                 serial1 = &uart1;
 34                 serial2 = &uart2;                  67                 serial2 = &uart2;
 35                 serial3 = &uart3;                  68                 serial3 = &uart3;
 36                 serial4 = &uart4;                  69                 serial4 = &uart4;
 37                 spi0 = &spi0;                      70                 spi0 = &spi0;
 38                 spi1 = &spi1;                      71                 spi1 = &spi1;
 39                 spi2 = &spi2;                      72                 spi2 = &spi2;
 40         };                                         73         };
 41                                                    74 
 42         cpus {                                     75         cpus {
 43                 #address-cells = <0x2>;            76                 #address-cells = <0x2>;
 44                 #size-cells = <0x0>;               77                 #size-cells = <0x0>;
 45                                                    78 
 46                 cpu-map {                          79                 cpu-map {
 47                         cluster0 {                 80                         cluster0 {
 48                                 core0 {            81                                 core0 {
 49                                         cpu =      82                                         cpu = <&cpu_b0>;
 50                                 };                 83                                 };
 51                                 core1 {            84                                 core1 {
 52                                         cpu =      85                                         cpu = <&cpu_b1>;
 53                                 };                 86                                 };
 54                                 core2 {            87                                 core2 {
 55                                         cpu =      88                                         cpu = <&cpu_b2>;
 56                                 };                 89                                 };
 57                                 core3 {            90                                 core3 {
 58                                         cpu =      91                                         cpu = <&cpu_b3>;
 59                                 };                 92                                 };
 60                         };                         93                         };
 61                                                    94 
 62                         cluster1 {                 95                         cluster1 {
 63                                 core0 {            96                                 core0 {
 64                                         cpu =      97                                         cpu = <&cpu_l0>;
 65                                 };                 98                                 };
 66                                 core1 {            99                                 core1 {
 67                                         cpu =     100                                         cpu = <&cpu_l1>;
 68                                 };                101                                 };
 69                                 core2 {           102                                 core2 {
 70                                         cpu =     103                                         cpu = <&cpu_l2>;
 71                                 };                104                                 };
 72                                 core3 {           105                                 core3 {
 73                                         cpu =     106                                         cpu = <&cpu_l3>;
 74                                 };                107                                 };
 75                         };                        108                         };
 76                 };                                109                 };
 77                                                   110 
 78                 cpu_l0: cpu@0 {                   111                 cpu_l0: cpu@0 {
 79                         device_type = "cpu";      112                         device_type = "cpu";
 80                         compatible = "arm,cort !! 113                         compatible = "arm,cortex-a53", "arm,armv8";
 81                         reg = <0x0 0x0>;          114                         reg = <0x0 0x0>;
 82                         enable-method = "psci"    115                         enable-method = "psci";
                                                   >> 116 
 83                         #cooling-cells = <2>;     117                         #cooling-cells = <2>; /* min followed by max */
 84                 };                                118                 };
 85                                                   119 
 86                 cpu_l1: cpu@1 {                   120                 cpu_l1: cpu@1 {
 87                         device_type = "cpu";      121                         device_type = "cpu";
 88                         compatible = "arm,cort !! 122                         compatible = "arm,cortex-a53", "arm,armv8";
 89                         reg = <0x0 0x1>;          123                         reg = <0x0 0x1>;
 90                         enable-method = "psci"    124                         enable-method = "psci";
 91                         #cooling-cells = <2>;  << 
 92                 };                                125                 };
 93                                                   126 
 94                 cpu_l2: cpu@2 {                   127                 cpu_l2: cpu@2 {
 95                         device_type = "cpu";      128                         device_type = "cpu";
 96                         compatible = "arm,cort !! 129                         compatible = "arm,cortex-a53", "arm,armv8";
 97                         reg = <0x0 0x2>;          130                         reg = <0x0 0x2>;
 98                         enable-method = "psci"    131                         enable-method = "psci";
 99                         #cooling-cells = <2>;  << 
100                 };                                132                 };
101                                                   133 
102                 cpu_l3: cpu@3 {                   134                 cpu_l3: cpu@3 {
103                         device_type = "cpu";      135                         device_type = "cpu";
104                         compatible = "arm,cort !! 136                         compatible = "arm,cortex-a53", "arm,armv8";
105                         reg = <0x0 0x3>;          137                         reg = <0x0 0x3>;
106                         enable-method = "psci"    138                         enable-method = "psci";
107                         #cooling-cells = <2>;  << 
108                 };                                139                 };
109                                                   140 
110                 cpu_b0: cpu@100 {                 141                 cpu_b0: cpu@100 {
111                         device_type = "cpu";      142                         device_type = "cpu";
112                         compatible = "arm,cort !! 143                         compatible = "arm,cortex-a53", "arm,armv8";
113                         reg = <0x0 0x100>;        144                         reg = <0x0 0x100>;
114                         enable-method = "psci"    145                         enable-method = "psci";
                                                   >> 146 
115                         #cooling-cells = <2>;     147                         #cooling-cells = <2>; /* min followed by max */
116                 };                                148                 };
117                                                   149 
118                 cpu_b1: cpu@101 {                 150                 cpu_b1: cpu@101 {
119                         device_type = "cpu";      151                         device_type = "cpu";
120                         compatible = "arm,cort !! 152                         compatible = "arm,cortex-a53", "arm,armv8";
121                         reg = <0x0 0x101>;        153                         reg = <0x0 0x101>;
122                         enable-method = "psci"    154                         enable-method = "psci";
123                         #cooling-cells = <2>;  << 
124                 };                                155                 };
125                                                   156 
126                 cpu_b2: cpu@102 {                 157                 cpu_b2: cpu@102 {
127                         device_type = "cpu";      158                         device_type = "cpu";
128                         compatible = "arm,cort !! 159                         compatible = "arm,cortex-a53", "arm,armv8";
129                         reg = <0x0 0x102>;        160                         reg = <0x0 0x102>;
130                         enable-method = "psci"    161                         enable-method = "psci";
131                         #cooling-cells = <2>;  << 
132                 };                                162                 };
133                                                   163 
134                 cpu_b3: cpu@103 {                 164                 cpu_b3: cpu@103 {
135                         device_type = "cpu";      165                         device_type = "cpu";
136                         compatible = "arm,cort !! 166                         compatible = "arm,cortex-a53", "arm,armv8";
137                         reg = <0x0 0x103>;        167                         reg = <0x0 0x103>;
138                         enable-method = "psci"    168                         enable-method = "psci";
139                         #cooling-cells = <2>;  !! 169                 };
                                                   >> 170         };
                                                   >> 171 
                                                   >> 172         amba {
                                                   >> 173                 compatible = "simple-bus";
                                                   >> 174                 #address-cells = <2>;
                                                   >> 175                 #size-cells = <2>;
                                                   >> 176                 ranges;
                                                   >> 177 
                                                   >> 178                 dmac_peri: dma-controller@ff250000 {
                                                   >> 179                         compatible = "arm,pl330", "arm,primecell";
                                                   >> 180                         reg = <0x0 0xff250000 0x0 0x4000>;
                                                   >> 181                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
                                                   >> 182                                      <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
                                                   >> 183                         #dma-cells = <1>;
                                                   >> 184                         arm,pl330-broken-no-flushp;
                                                   >> 185                         clocks = <&cru ACLK_DMAC_PERI>;
                                                   >> 186                         clock-names = "apb_pclk";
                                                   >> 187                 };
                                                   >> 188 
                                                   >> 189                 dmac_bus: dma-controller@ff600000 {
                                                   >> 190                         compatible = "arm,pl330", "arm,primecell";
                                                   >> 191                         reg = <0x0 0xff600000 0x0 0x4000>;
                                                   >> 192                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
                                                   >> 193                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
                                                   >> 194                         #dma-cells = <1>;
                                                   >> 195                         arm,pl330-broken-no-flushp;
                                                   >> 196                         clocks = <&cru ACLK_DMAC_BUS>;
                                                   >> 197                         clock-names = "apb_pclk";
140                 };                                198                 };
141         };                                        199         };
142                                                   200 
143         arm-pmu {                                 201         arm-pmu {
144                 compatible = "arm,cortex-a53-p !! 202                 compatible = "arm,armv8-pmuv3";
145                 interrupts = <GIC_SPI 112 IRQ_    203                 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
146                              <GIC_SPI 113 IRQ_    204                              <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
147                              <GIC_SPI 114 IRQ_    205                              <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
148                              <GIC_SPI 115 IRQ_    206                              <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
149                              <GIC_SPI 116 IRQ_    207                              <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
150                              <GIC_SPI 117 IRQ_    208                              <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
151                              <GIC_SPI 118 IRQ_    209                              <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
152                              <GIC_SPI 119 IRQ_    210                              <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
153                 interrupt-affinity = <&cpu_l0>    211                 interrupt-affinity = <&cpu_l0>, <&cpu_l1>, <&cpu_l2>,
154                                      <&cpu_l3>    212                                      <&cpu_l3>, <&cpu_b0>, <&cpu_b1>,
155                                      <&cpu_b2>    213                                      <&cpu_b2>, <&cpu_b3>;
156         };                                        214         };
157                                                   215 
158         psci {                                    216         psci {
159                 compatible = "arm,psci-0.2";      217                 compatible = "arm,psci-0.2";
160                 method = "smc";                   218                 method = "smc";
161         };                                        219         };
162                                                   220 
163         timer {                                   221         timer {
164                 compatible = "arm,armv8-timer"    222                 compatible = "arm,armv8-timer";
165                 interrupts = <GIC_PPI 13          223                 interrupts = <GIC_PPI 13
166                         (GIC_CPU_MASK_SIMPLE(8    224                         (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
167                              <GIC_PPI 14          225                              <GIC_PPI 14
168                         (GIC_CPU_MASK_SIMPLE(8    226                         (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
169                              <GIC_PPI 11          227                              <GIC_PPI 11
170                         (GIC_CPU_MASK_SIMPLE(8    228                         (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
171                              <GIC_PPI 10          229                              <GIC_PPI 10
172                         (GIC_CPU_MASK_SIMPLE(8    230                         (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
173         };                                        231         };
174                                                   232 
175         xin24m: oscillator {                      233         xin24m: oscillator {
176                 compatible = "fixed-clock";       234                 compatible = "fixed-clock";
177                 clock-frequency = <24000000>;     235                 clock-frequency = <24000000>;
178                 clock-output-names = "xin24m";    236                 clock-output-names = "xin24m";
179                 #clock-cells = <0>;               237                 #clock-cells = <0>;
180         };                                        238         };
181                                                   239 
182         sdmmc: mmc@ff0c0000 {                  !! 240         sdmmc: dwmmc@ff0c0000 {
183                 compatible = "rockchip,rk3368-    241                 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
184                 reg = <0x0 0xff0c0000 0x0 0x40    242                 reg = <0x0 0xff0c0000 0x0 0x4000>;
185                 max-frequency = <150000000>;      243                 max-frequency = <150000000>;
186                 clocks = <&cru HCLK_SDMMC>, <&    244                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
187                          <&cru SCLK_SDMMC_DRV>    245                          <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
188                 clock-names = "biu", "ciu", "c    246                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
189                 fifo-depth = <0x100>;             247                 fifo-depth = <0x100>;
190                 interrupts = <GIC_SPI 32 IRQ_T    248                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
191                 resets = <&cru SRST_MMC0>;        249                 resets = <&cru SRST_MMC0>;
192                 reset-names = "reset";            250                 reset-names = "reset";
193                 status = "disabled";              251                 status = "disabled";
194         };                                        252         };
195                                                   253 
196         sdio0: mmc@ff0d0000 {                  !! 254         sdio0: dwmmc@ff0d0000 {
197                 compatible = "rockchip,rk3368-    255                 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
198                 reg = <0x0 0xff0d0000 0x0 0x40    256                 reg = <0x0 0xff0d0000 0x0 0x4000>;
199                 max-frequency = <150000000>;      257                 max-frequency = <150000000>;
200                 clocks = <&cru HCLK_SDIO0>, <&    258                 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>,
201                          <&cru SCLK_SDIO0_DRV>    259                          <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
202                 clock-names = "biu", "ciu", "c !! 260                 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
203                 fifo-depth = <0x100>;             261                 fifo-depth = <0x100>;
204                 interrupts = <GIC_SPI 33 IRQ_T    262                 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
205                 resets = <&cru SRST_SDIO0>;       263                 resets = <&cru SRST_SDIO0>;
206                 reset-names = "reset";            264                 reset-names = "reset";
207                 status = "disabled";              265                 status = "disabled";
208         };                                        266         };
209                                                   267 
210         emmc: mmc@ff0f0000 {                   !! 268         emmc: dwmmc@ff0f0000 {
211                 compatible = "rockchip,rk3368-    269                 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
212                 reg = <0x0 0xff0f0000 0x0 0x40    270                 reg = <0x0 0xff0f0000 0x0 0x4000>;
213                 max-frequency = <150000000>;      271                 max-frequency = <150000000>;
214                 clocks = <&cru HCLK_EMMC>, <&c    272                 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
215                          <&cru SCLK_EMMC_DRV>,    273                          <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
216                 clock-names = "biu", "ciu", "c    274                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
217                 fifo-depth = <0x100>;             275                 fifo-depth = <0x100>;
218                 interrupts = <GIC_SPI 35 IRQ_T    276                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
219                 resets = <&cru SRST_EMMC>;        277                 resets = <&cru SRST_EMMC>;
220                 reset-names = "reset";            278                 reset-names = "reset";
221                 status = "disabled";              279                 status = "disabled";
222         };                                        280         };
223                                                   281 
224         saradc: saradc@ff100000 {                 282         saradc: saradc@ff100000 {
225                 compatible = "rockchip,saradc"    283                 compatible = "rockchip,saradc";
226                 reg = <0x0 0xff100000 0x0 0x10    284                 reg = <0x0 0xff100000 0x0 0x100>;
227                 interrupts = <GIC_SPI 36 IRQ_T    285                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
228                 #io-channel-cells = <1>;          286                 #io-channel-cells = <1>;
229                 clocks = <&cru SCLK_SARADC>, <    287                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
230                 clock-names = "saradc", "apb_p    288                 clock-names = "saradc", "apb_pclk";
231                 resets = <&cru SRST_SARADC>;      289                 resets = <&cru SRST_SARADC>;
232                 reset-names = "saradc-apb";       290                 reset-names = "saradc-apb";
233                 status = "disabled";              291                 status = "disabled";
234         };                                        292         };
235                                                   293 
236         spi0: spi@ff110000 {                      294         spi0: spi@ff110000 {
237                 compatible = "rockchip,rk3368-    295                 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
238                 reg = <0x0 0xff110000 0x0 0x10    296                 reg = <0x0 0xff110000 0x0 0x1000>;
239                 clocks = <&cru SCLK_SPI0>, <&c    297                 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
240                 clock-names = "spiclk", "apb_p    298                 clock-names = "spiclk", "apb_pclk";
241                 interrupts = <GIC_SPI 44 IRQ_T    299                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
242                 pinctrl-names = "default";        300                 pinctrl-names = "default";
243                 pinctrl-0 = <&spi0_clk &spi0_t    301                 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
244                 #address-cells = <1>;             302                 #address-cells = <1>;
245                 #size-cells = <0>;                303                 #size-cells = <0>;
246                 status = "disabled";              304                 status = "disabled";
247         };                                        305         };
248                                                   306 
249         spi1: spi@ff120000 {                      307         spi1: spi@ff120000 {
250                 compatible = "rockchip,rk3368-    308                 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
251                 reg = <0x0 0xff120000 0x0 0x10    309                 reg = <0x0 0xff120000 0x0 0x1000>;
252                 clocks = <&cru SCLK_SPI1>, <&c    310                 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
253                 clock-names = "spiclk", "apb_p    311                 clock-names = "spiclk", "apb_pclk";
254                 interrupts = <GIC_SPI 45 IRQ_T    312                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
255                 pinctrl-names = "default";        313                 pinctrl-names = "default";
256                 pinctrl-0 = <&spi1_clk &spi1_t    314                 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
257                 #address-cells = <1>;             315                 #address-cells = <1>;
258                 #size-cells = <0>;                316                 #size-cells = <0>;
259                 status = "disabled";              317                 status = "disabled";
260         };                                        318         };
261                                                   319 
262         spi2: spi@ff130000 {                      320         spi2: spi@ff130000 {
263                 compatible = "rockchip,rk3368-    321                 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
264                 reg = <0x0 0xff130000 0x0 0x10    322                 reg = <0x0 0xff130000 0x0 0x1000>;
265                 clocks = <&cru SCLK_SPI2>, <&c    323                 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
266                 clock-names = "spiclk", "apb_p    324                 clock-names = "spiclk", "apb_pclk";
267                 interrupts = <GIC_SPI 41 IRQ_T    325                 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
268                 pinctrl-names = "default";        326                 pinctrl-names = "default";
269                 pinctrl-0 = <&spi2_clk &spi2_t    327                 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
270                 #address-cells = <1>;             328                 #address-cells = <1>;
271                 #size-cells = <0>;                329                 #size-cells = <0>;
272                 status = "disabled";              330                 status = "disabled";
273         };                                        331         };
274                                                   332 
275         i2c2: i2c@ff140000 {                      333         i2c2: i2c@ff140000 {
276                 compatible = "rockchip,rk3368-    334                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
277                 reg = <0x0 0xff140000 0x0 0x10    335                 reg = <0x0 0xff140000 0x0 0x1000>;
278                 interrupts = <GIC_SPI 62 IRQ_T    336                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
279                 #address-cells = <1>;             337                 #address-cells = <1>;
280                 #size-cells = <0>;                338                 #size-cells = <0>;
281                 clock-names = "i2c";              339                 clock-names = "i2c";
282                 clocks = <&cru PCLK_I2C2>;        340                 clocks = <&cru PCLK_I2C2>;
283                 pinctrl-names = "default";        341                 pinctrl-names = "default";
284                 pinctrl-0 = <&i2c2_xfer>;         342                 pinctrl-0 = <&i2c2_xfer>;
285                 status = "disabled";              343                 status = "disabled";
286         };                                        344         };
287                                                   345 
288         i2c3: i2c@ff150000 {                      346         i2c3: i2c@ff150000 {
289                 compatible = "rockchip,rk3368-    347                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
290                 reg = <0x0 0xff150000 0x0 0x10    348                 reg = <0x0 0xff150000 0x0 0x1000>;
291                 interrupts = <GIC_SPI 63 IRQ_T    349                 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
292                 #address-cells = <1>;             350                 #address-cells = <1>;
293                 #size-cells = <0>;                351                 #size-cells = <0>;
294                 clock-names = "i2c";              352                 clock-names = "i2c";
295                 clocks = <&cru PCLK_I2C3>;        353                 clocks = <&cru PCLK_I2C3>;
296                 pinctrl-names = "default";        354                 pinctrl-names = "default";
297                 pinctrl-0 = <&i2c3_xfer>;         355                 pinctrl-0 = <&i2c3_xfer>;
298                 status = "disabled";              356                 status = "disabled";
299         };                                        357         };
300                                                   358 
301         i2c4: i2c@ff160000 {                      359         i2c4: i2c@ff160000 {
302                 compatible = "rockchip,rk3368-    360                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
303                 reg = <0x0 0xff160000 0x0 0x10    361                 reg = <0x0 0xff160000 0x0 0x1000>;
304                 interrupts = <GIC_SPI 64 IRQ_T    362                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
305                 #address-cells = <1>;             363                 #address-cells = <1>;
306                 #size-cells = <0>;                364                 #size-cells = <0>;
307                 clock-names = "i2c";              365                 clock-names = "i2c";
308                 clocks = <&cru PCLK_I2C4>;        366                 clocks = <&cru PCLK_I2C4>;
309                 pinctrl-names = "default";        367                 pinctrl-names = "default";
310                 pinctrl-0 = <&i2c4_xfer>;         368                 pinctrl-0 = <&i2c4_xfer>;
311                 status = "disabled";              369                 status = "disabled";
312         };                                        370         };
313                                                   371 
314         i2c5: i2c@ff170000 {                      372         i2c5: i2c@ff170000 {
315                 compatible = "rockchip,rk3368-    373                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
316                 reg = <0x0 0xff170000 0x0 0x10    374                 reg = <0x0 0xff170000 0x0 0x1000>;
317                 interrupts = <GIC_SPI 65 IRQ_T    375                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
318                 #address-cells = <1>;             376                 #address-cells = <1>;
319                 #size-cells = <0>;                377                 #size-cells = <0>;
320                 clock-names = "i2c";              378                 clock-names = "i2c";
321                 clocks = <&cru PCLK_I2C5>;        379                 clocks = <&cru PCLK_I2C5>;
322                 pinctrl-names = "default";        380                 pinctrl-names = "default";
323                 pinctrl-0 = <&i2c5_xfer>;         381                 pinctrl-0 = <&i2c5_xfer>;
324                 status = "disabled";              382                 status = "disabled";
325         };                                        383         };
326                                                   384 
327         uart0: serial@ff180000 {                  385         uart0: serial@ff180000 {
328                 compatible = "rockchip,rk3368-    386                 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
329                 reg = <0x0 0xff180000 0x0 0x10    387                 reg = <0x0 0xff180000 0x0 0x100>;
330                 clock-frequency = <24000000>;     388                 clock-frequency = <24000000>;
331                 clocks = <&cru SCLK_UART0>, <&    389                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
332                 clock-names = "baudclk", "apb_    390                 clock-names = "baudclk", "apb_pclk";
333                 interrupts = <GIC_SPI 55 IRQ_T    391                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
334                 reg-shift = <2>;                  392                 reg-shift = <2>;
335                 reg-io-width = <4>;               393                 reg-io-width = <4>;
336                 status = "disabled";              394                 status = "disabled";
337         };                                        395         };
338                                                   396 
339         uart1: serial@ff190000 {                  397         uart1: serial@ff190000 {
340                 compatible = "rockchip,rk3368-    398                 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
341                 reg = <0x0 0xff190000 0x0 0x10    399                 reg = <0x0 0xff190000 0x0 0x100>;
342                 clock-frequency = <24000000>;     400                 clock-frequency = <24000000>;
343                 clocks = <&cru SCLK_UART1>, <&    401                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
344                 clock-names = "baudclk", "apb_    402                 clock-names = "baudclk", "apb_pclk";
345                 interrupts = <GIC_SPI 56 IRQ_T    403                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
346                 reg-shift = <2>;                  404                 reg-shift = <2>;
347                 reg-io-width = <4>;               405                 reg-io-width = <4>;
348                 status = "disabled";              406                 status = "disabled";
349         };                                        407         };
350                                                   408 
351         uart3: serial@ff1b0000 {                  409         uart3: serial@ff1b0000 {
352                 compatible = "rockchip,rk3368-    410                 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
353                 reg = <0x0 0xff1b0000 0x0 0x10    411                 reg = <0x0 0xff1b0000 0x0 0x100>;
354                 clock-frequency = <24000000>;     412                 clock-frequency = <24000000>;
355                 clocks = <&cru SCLK_UART3>, <&    413                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
356                 clock-names = "baudclk", "apb_    414                 clock-names = "baudclk", "apb_pclk";
357                 interrupts = <GIC_SPI 58 IRQ_T    415                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
358                 reg-shift = <2>;                  416                 reg-shift = <2>;
359                 reg-io-width = <4>;               417                 reg-io-width = <4>;
360                 status = "disabled";              418                 status = "disabled";
361         };                                        419         };
362                                                   420 
363         uart4: serial@ff1c0000 {                  421         uart4: serial@ff1c0000 {
364                 compatible = "rockchip,rk3368-    422                 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
365                 reg = <0x0 0xff1c0000 0x0 0x10    423                 reg = <0x0 0xff1c0000 0x0 0x100>;
366                 clock-frequency = <24000000>;     424                 clock-frequency = <24000000>;
367                 clocks = <&cru SCLK_UART4>, <&    425                 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
368                 clock-names = "baudclk", "apb_    426                 clock-names = "baudclk", "apb_pclk";
369                 interrupts = <GIC_SPI 59 IRQ_T    427                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
370                 reg-shift = <2>;                  428                 reg-shift = <2>;
371                 reg-io-width = <4>;               429                 reg-io-width = <4>;
372                 status = "disabled";              430                 status = "disabled";
373         };                                        431         };
374                                                   432 
375         dmac_peri: dma-controller@ff250000 {   << 
376                 compatible = "arm,pl330", "arm << 
377                 reg = <0x0 0xff250000 0x0 0x40 << 
378                 interrupts = <GIC_SPI 2 IRQ_TY << 
379                              <GIC_SPI 3 IRQ_TY << 
380                 #dma-cells = <1>;              << 
381                 arm,pl330-broken-no-flushp;    << 
382                 arm,pl330-periph-burst;        << 
383                 clocks = <&cru ACLK_DMAC_PERI> << 
384                 clock-names = "apb_pclk";      << 
385         };                                     << 
386                                                << 
387         thermal-zones {                           433         thermal-zones {
388                 cpu_thermal: cpu-thermal {     !! 434                 cpu {
389                         polling-delay-passive     435                         polling-delay-passive = <100>; /* milliseconds */
390                         polling-delay = <5000>    436                         polling-delay = <5000>; /* milliseconds */
391                                                   437 
392                         thermal-sensors = <&ts    438                         thermal-sensors = <&tsadc 0>;
393                                                   439 
394                         trips {                   440                         trips {
395                                 cpu_alert0: cp    441                                 cpu_alert0: cpu_alert0 {
396                                         temper    442                                         temperature = <75000>; /* millicelsius */
397                                         hyster    443                                         hysteresis = <2000>; /* millicelsius */
398                                         type =    444                                         type = "passive";
399                                 };                445                                 };
400                                 cpu_alert1: cp    446                                 cpu_alert1: cpu_alert1 {
401                                         temper    447                                         temperature = <80000>; /* millicelsius */
402                                         hyster    448                                         hysteresis = <2000>; /* millicelsius */
403                                         type =    449                                         type = "passive";
404                                 };                450                                 };
405                                 cpu_crit: cpu_    451                                 cpu_crit: cpu_crit {
406                                         temper    452                                         temperature = <95000>; /* millicelsius */
407                                         hyster    453                                         hysteresis = <2000>; /* millicelsius */
408                                         type =    454                                         type = "critical";
409                                 };                455                                 };
410                         };                        456                         };
411                                                   457 
412                         cooling-maps {            458                         cooling-maps {
413                                 map0 {            459                                 map0 {
414                                         trip =    460                                         trip = <&cpu_alert0>;
415                                         coolin    461                                         cooling-device =
416                                         <&cpu_ !! 462                                         <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
417                                         <&cpu_ << 
418                                         <&cpu_ << 
419                                         <&cpu_ << 
420                                 };                463                                 };
421                                 map1 {            464                                 map1 {
422                                         trip =    465                                         trip = <&cpu_alert1>;
423                                         coolin    466                                         cooling-device =
424                                         <&cpu_ !! 467                                         <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
425                                         <&cpu_ << 
426                                         <&cpu_ << 
427                                         <&cpu_ << 
428                                 };                468                                 };
429                         };                        469                         };
430                 };                                470                 };
431                                                   471 
432                 gpu_thermal: gpu-thermal {     !! 472                 gpu {
433                         polling-delay-passive     473                         polling-delay-passive = <100>; /* milliseconds */
434                         polling-delay = <5000>    474                         polling-delay = <5000>; /* milliseconds */
435                                                   475 
436                         thermal-sensors = <&ts    476                         thermal-sensors = <&tsadc 1>;
437                                                   477 
438                         trips {                   478                         trips {
439                                 gpu_alert0: gp    479                                 gpu_alert0: gpu_alert0 {
440                                         temper    480                                         temperature = <80000>; /* millicelsius */
441                                         hyster    481                                         hysteresis = <2000>; /* millicelsius */
442                                         type =    482                                         type = "passive";
443                                 };                483                                 };
444                                 gpu_crit: gpu_    484                                 gpu_crit: gpu_crit {
445                                         temper    485                                         temperature = <115000>; /* millicelsius */
446                                         hyster    486                                         hysteresis = <2000>; /* millicelsius */
447                                         type =    487                                         type = "critical";
448                                 };                488                                 };
449                         };                        489                         };
450                                                   490 
451                         cooling-maps {            491                         cooling-maps {
452                                 map0 {            492                                 map0 {
453                                         trip =    493                                         trip = <&gpu_alert0>;
454                                         coolin    494                                         cooling-device =
455                                         <&cpu_ !! 495                                         <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
456                                         <&cpu_ << 
457                                         <&cpu_ << 
458                                         <&cpu_ << 
459                                 };                496                                 };
460                         };                        497                         };
461                 };                                498                 };
462         };                                        499         };
463                                                   500 
464         tsadc: tsadc@ff280000 {                   501         tsadc: tsadc@ff280000 {
465                 compatible = "rockchip,rk3368-    502                 compatible = "rockchip,rk3368-tsadc";
466                 reg = <0x0 0xff280000 0x0 0x10    503                 reg = <0x0 0xff280000 0x0 0x100>;
467                 interrupts = <GIC_SPI 37 IRQ_T    504                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
468                 clocks = <&cru SCLK_TSADC>, <&    505                 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
469                 clock-names = "tsadc", "apb_pc    506                 clock-names = "tsadc", "apb_pclk";
470                 resets = <&cru SRST_TSADC>;       507                 resets = <&cru SRST_TSADC>;
471                 reset-names = "tsadc-apb";        508                 reset-names = "tsadc-apb";
472                 pinctrl-names = "init", "defau    509                 pinctrl-names = "init", "default", "sleep";
473                 pinctrl-0 = <&otp_pin>;        !! 510                 pinctrl-0 = <&otp_gpio>;
474                 pinctrl-1 = <&otp_out>;           511                 pinctrl-1 = <&otp_out>;
475                 pinctrl-2 = <&otp_pin>;        !! 512                 pinctrl-2 = <&otp_gpio>;
476                 #thermal-sensor-cells = <1>;      513                 #thermal-sensor-cells = <1>;
477                 rockchip,hw-tshut-temp = <9500    514                 rockchip,hw-tshut-temp = <95000>;
478                 status = "disabled";              515                 status = "disabled";
479         };                                        516         };
480                                                   517 
481         gmac: ethernet@ff290000 {                 518         gmac: ethernet@ff290000 {
482                 compatible = "rockchip,rk3368-    519                 compatible = "rockchip,rk3368-gmac";
483                 reg = <0x0 0xff290000 0x0 0x10    520                 reg = <0x0 0xff290000 0x0 0x10000>;
484                 interrupts = <GIC_SPI 27 IRQ_T    521                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
485                 interrupt-names = "macirq";       522                 interrupt-names = "macirq";
486                 rockchip,grf = <&grf>;            523                 rockchip,grf = <&grf>;
487                 clocks = <&cru SCLK_MAC>,         524                 clocks = <&cru SCLK_MAC>,
488                         <&cru SCLK_MAC_RX>, <&    525                         <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>,
489                         <&cru SCLK_MACREF>, <&    526                         <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>,
490                         <&cru ACLK_GMAC>, <&cr    527                         <&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
491                 clock-names = "stmmaceth",        528                 clock-names = "stmmaceth",
492                         "mac_clk_rx", "mac_clk    529                         "mac_clk_rx", "mac_clk_tx",
493                         "clk_mac_ref", "clk_ma    530                         "clk_mac_ref", "clk_mac_refout",
494                         "aclk_mac", "pclk_mac"    531                         "aclk_mac", "pclk_mac";
495                 status = "disabled";              532                 status = "disabled";
496         };                                        533         };
497                                                   534 
498         usb_host0_ehci: usb@ff500000 {            535         usb_host0_ehci: usb@ff500000 {
499                 compatible = "generic-ehci";      536                 compatible = "generic-ehci";
500                 reg = <0x0 0xff500000 0x0 0x10    537                 reg = <0x0 0xff500000 0x0 0x100>;
501                 interrupts = <GIC_SPI 24 IRQ_T    538                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
502                 clocks = <&cru HCLK_HOST0>;       539                 clocks = <&cru HCLK_HOST0>;
                                                   >> 540                 clock-names = "usbhost";
503                 status = "disabled";              541                 status = "disabled";
504         };                                        542         };
505                                                   543 
506         usb_otg: usb@ff580000 {                   544         usb_otg: usb@ff580000 {
507                 compatible = "rockchip,rk3368-    545                 compatible = "rockchip,rk3368-usb", "rockchip,rk3066-usb",
508                                 "snps,dwc2";      546                                 "snps,dwc2";
509                 reg = <0x0 0xff580000 0x0 0x40    547                 reg = <0x0 0xff580000 0x0 0x40000>;
510                 interrupts = <GIC_SPI 23 IRQ_T    548                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
511                 clocks = <&cru HCLK_OTG0>;        549                 clocks = <&cru HCLK_OTG0>;
512                 clock-names = "otg";              550                 clock-names = "otg";
513                 dr_mode = "otg";                  551                 dr_mode = "otg";
514                 g-np-tx-fifo-size = <16>;         552                 g-np-tx-fifo-size = <16>;
515                 g-rx-fifo-size = <275>;           553                 g-rx-fifo-size = <275>;
516                 g-tx-fifo-size = <256 128 128     554                 g-tx-fifo-size = <256 128 128 64 64 32>;
517                 status = "disabled";              555                 status = "disabled";
518         };                                        556         };
519                                                   557 
520         dmac_bus: dma-controller@ff600000 {    << 
521                 compatible = "arm,pl330", "arm << 
522                 reg = <0x0 0xff600000 0x0 0x40 << 
523                 interrupts = <GIC_SPI 0 IRQ_TY << 
524                              <GIC_SPI 1 IRQ_TY << 
525                 #dma-cells = <1>;              << 
526                 arm,pl330-broken-no-flushp;    << 
527                 arm,pl330-periph-burst;        << 
528                 clocks = <&cru ACLK_DMAC_BUS>; << 
529                 clock-names = "apb_pclk";      << 
530         };                                     << 
531                                                << 
532         i2c0: i2c@ff650000 {                      558         i2c0: i2c@ff650000 {
533                 compatible = "rockchip,rk3368-    559                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
534                 reg = <0x0 0xff650000 0x0 0x10    560                 reg = <0x0 0xff650000 0x0 0x1000>;
535                 clocks = <&cru PCLK_I2C0>;        561                 clocks = <&cru PCLK_I2C0>;
536                 clock-names = "i2c";              562                 clock-names = "i2c";
537                 interrupts = <GIC_SPI 60 IRQ_T    563                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
538                 pinctrl-names = "default";        564                 pinctrl-names = "default";
539                 pinctrl-0 = <&i2c0_xfer>;         565                 pinctrl-0 = <&i2c0_xfer>;
540                 #address-cells = <1>;             566                 #address-cells = <1>;
541                 #size-cells = <0>;                567                 #size-cells = <0>;
542                 status = "disabled";              568                 status = "disabled";
543         };                                        569         };
544                                                   570 
545         i2c1: i2c@ff660000 {                      571         i2c1: i2c@ff660000 {
546                 compatible = "rockchip,rk3368-    572                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
547                 reg = <0x0 0xff660000 0x0 0x10    573                 reg = <0x0 0xff660000 0x0 0x1000>;
548                 interrupts = <GIC_SPI 61 IRQ_T    574                 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
549                 #address-cells = <1>;             575                 #address-cells = <1>;
550                 #size-cells = <0>;                576                 #size-cells = <0>;
551                 clock-names = "i2c";              577                 clock-names = "i2c";
552                 clocks = <&cru PCLK_I2C1>;        578                 clocks = <&cru PCLK_I2C1>;
553                 pinctrl-names = "default";        579                 pinctrl-names = "default";
554                 pinctrl-0 = <&i2c1_xfer>;         580                 pinctrl-0 = <&i2c1_xfer>;
555                 status = "disabled";              581                 status = "disabled";
556         };                                        582         };
557                                                   583 
558         pwm0: pwm@ff680000 {                      584         pwm0: pwm@ff680000 {
559                 compatible = "rockchip,rk3368-    585                 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
560                 reg = <0x0 0xff680000 0x0 0x10    586                 reg = <0x0 0xff680000 0x0 0x10>;
561                 #pwm-cells = <3>;                 587                 #pwm-cells = <3>;
562                 pinctrl-names = "default";        588                 pinctrl-names = "default";
563                 pinctrl-0 = <&pwm0_pin>;          589                 pinctrl-0 = <&pwm0_pin>;
564                 clocks = <&cru PCLK_PWM1>;        590                 clocks = <&cru PCLK_PWM1>;
                                                   >> 591                 clock-names = "pwm";
565                 status = "disabled";              592                 status = "disabled";
566         };                                        593         };
567                                                   594 
568         pwm1: pwm@ff680010 {                      595         pwm1: pwm@ff680010 {
569                 compatible = "rockchip,rk3368-    596                 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
570                 reg = <0x0 0xff680010 0x0 0x10    597                 reg = <0x0 0xff680010 0x0 0x10>;
571                 #pwm-cells = <3>;                 598                 #pwm-cells = <3>;
572                 pinctrl-names = "default";        599                 pinctrl-names = "default";
573                 pinctrl-0 = <&pwm1_pin>;          600                 pinctrl-0 = <&pwm1_pin>;
574                 clocks = <&cru PCLK_PWM1>;        601                 clocks = <&cru PCLK_PWM1>;
                                                   >> 602                 clock-names = "pwm";
575                 status = "disabled";              603                 status = "disabled";
576         };                                        604         };
577                                                   605 
578         pwm2: pwm@ff680020 {                      606         pwm2: pwm@ff680020 {
579                 compatible = "rockchip,rk3368-    607                 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
580                 reg = <0x0 0xff680020 0x0 0x10    608                 reg = <0x0 0xff680020 0x0 0x10>;
581                 #pwm-cells = <3>;                 609                 #pwm-cells = <3>;
582                 clocks = <&cru PCLK_PWM1>;        610                 clocks = <&cru PCLK_PWM1>;
                                                   >> 611                 clock-names = "pwm";
583                 status = "disabled";              612                 status = "disabled";
584         };                                        613         };
585                                                   614 
586         pwm3: pwm@ff680030 {                      615         pwm3: pwm@ff680030 {
587                 compatible = "rockchip,rk3368-    616                 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
588                 reg = <0x0 0xff680030 0x0 0x10    617                 reg = <0x0 0xff680030 0x0 0x10>;
589                 #pwm-cells = <3>;                 618                 #pwm-cells = <3>;
590                 pinctrl-names = "default";        619                 pinctrl-names = "default";
591                 pinctrl-0 = <&pwm3_pin>;          620                 pinctrl-0 = <&pwm3_pin>;
592                 clocks = <&cru PCLK_PWM1>;        621                 clocks = <&cru PCLK_PWM1>;
                                                   >> 622                 clock-names = "pwm";
593                 status = "disabled";              623                 status = "disabled";
594         };                                        624         };
595                                                   625 
596         uart2: serial@ff690000 {                  626         uart2: serial@ff690000 {
597                 compatible = "rockchip,rk3368-    627                 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
598                 reg = <0x0 0xff690000 0x0 0x10    628                 reg = <0x0 0xff690000 0x0 0x100>;
599                 clocks = <&cru SCLK_UART2>, <&    629                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
600                 clock-names = "baudclk", "apb_    630                 clock-names = "baudclk", "apb_pclk";
601                 interrupts = <GIC_SPI 57 IRQ_T    631                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
602                 pinctrl-names = "default";        632                 pinctrl-names = "default";
603                 pinctrl-0 = <&uart2_xfer>;        633                 pinctrl-0 = <&uart2_xfer>;
604                 reg-shift = <2>;                  634                 reg-shift = <2>;
605                 reg-io-width = <4>;               635                 reg-io-width = <4>;
606                 status = "disabled";              636                 status = "disabled";
607         };                                        637         };
608                                                   638 
609         mbox: mbox@ff6b0000 {                     639         mbox: mbox@ff6b0000 {
610                 compatible = "rockchip,rk3368-    640                 compatible = "rockchip,rk3368-mailbox";
611                 reg = <0x0 0xff6b0000 0x0 0x10    641                 reg = <0x0 0xff6b0000 0x0 0x1000>;
612                 interrupts = <GIC_SPI 146 IRQ_    642                 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
613                              <GIC_SPI 147 IRQ_    643                              <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
614                              <GIC_SPI 148 IRQ_    644                              <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
615                              <GIC_SPI 149 IRQ_    645                              <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
616                 clocks = <&cru PCLK_MAILBOX>;     646                 clocks = <&cru PCLK_MAILBOX>;
617                 clock-names = "pclk_mailbox";     647                 clock-names = "pclk_mailbox";
618                 #mbox-cells = <1>;                648                 #mbox-cells = <1>;
619                 status = "disabled";              649                 status = "disabled";
620         };                                        650         };
621                                                   651 
622         pmu: power-management@ff730000 {       << 
623                 compatible = "rockchip,rk3368- << 
624                 reg = <0x0 0xff730000 0x0 0x10 << 
625                                                << 
626                 power: power-controller {      << 
627                         compatible = "rockchip << 
628                         #power-domain-cells =  << 
629                         #address-cells = <1>;  << 
630                         #size-cells = <0>;     << 
631                                                << 
632                         /*                     << 
633                          * Note: Although SCLK << 
634                          * of device without i << 
635                          * synchronous reset.  << 
636                          *                     << 
637                          * The clocks on the w << 
638                          * ACLK_IEP/ACLK_VIP/A << 
639                          * ACLK_ISP/ACLK_VOP1  << 
640                          * ACLK_RGA is on ACLK << 
641                          * The others (HCLK_*, << 
642                          *                     << 
643                          * Which clock are dev << 
644                          *      clocks         << 
645                          *      *_IEP          << 
646                          *      *_ISP          << 
647                          *      *_VIP          << 
648                          *      *_VOP*         << 
649                          *      *_RGA          << 
650                          *      *_EDP*         << 
651                          *      *_DPHY*        << 
652                          *      *_HDMI         << 
653                          *      *_MIPI_*       << 
654                          */                    << 
655                         power-domain@RK3368_PD << 
656                                 reg = <RK3368_ << 
657                                 clocks = <&cru << 
658                                          <&cru << 
659                                          <&cru << 
660                                          <&cru << 
661                                          <&cru << 
662                                          <&cru << 
663                                          <&cru << 
664                                          <&cru << 
665                                          <&cru << 
666                                          <&cru << 
667                                          <&cru << 
668                                          <&cru << 
669                                          <&cru << 
670                                          <&cru << 
671                                          <&cru << 
672                                          <&cru << 
673                                          <&cru << 
674                                          <&cru << 
675                                          <&cru << 
676                                          <&cru << 
677                                          <&cru << 
678                                          <&cru << 
679                                          <&cru << 
680                                          <&cru << 
681                                          <&cru << 
682                                          <&cru << 
683                                          <&cru << 
684                                          <&cru << 
685                                          <&cru << 
686                                          <&cru << 
687                                 pm_qos = <&qos << 
688                                          <&qos << 
689                                          <&qos << 
690                                          <&qos << 
691                                          <&qos << 
692                                          <&qos << 
693                                          <&qos << 
694                                          <&qos << 
695                                          <&qos << 
696                                 #power-domain- << 
697                         };                     << 
698                                                << 
699                         /*                     << 
700                          * Note: ACLK_VCODEC/H << 
701                          * (video endecoder &  << 
702                          * ACLK_VCODEC_NIU and << 
703                          */                    << 
704                         power-domain@RK3368_PD << 
705                                 reg = <RK3368_ << 
706                                 clocks = <&cru << 
707                                          <&cru << 
708                                          <&cru << 
709                                          <&cru << 
710                                 pm_qos = <&qos << 
711                                          <&qos << 
712                                          <&qos << 
713                                 #power-domain- << 
714                         };                     << 
715                                                << 
716                         /*                     << 
717                          * Note: ACLK_GPU is t << 
718                          * and on the ACLK_GPU << 
719                          */                    << 
720                         power-domain@RK3368_PD << 
721                                 reg = <RK3368_ << 
722                                 clocks = <&cru << 
723                                          <&cru << 
724                                          <&cru << 
725                                 pm_qos = <&qos << 
726                                 #power-domain- << 
727                         };                     << 
728                 };                             << 
729         };                                     << 
730                                                << 
731         pmugrf: syscon@ff738000 {                 652         pmugrf: syscon@ff738000 {
732                 compatible = "rockchip,rk3368-    653                 compatible = "rockchip,rk3368-pmugrf", "syscon", "simple-mfd";
733                 reg = <0x0 0xff738000 0x0 0x10    654                 reg = <0x0 0xff738000 0x0 0x1000>;
734                                                   655 
735                 pmu_io_domains: io-domains {      656                 pmu_io_domains: io-domains {
736                         compatible = "rockchip    657                         compatible = "rockchip,rk3368-pmu-io-voltage-domain";
737                         status = "disabled";      658                         status = "disabled";
738                 };                                659                 };
739                                                   660 
740                 reboot-mode {                     661                 reboot-mode {
741                         compatible = "syscon-r    662                         compatible = "syscon-reboot-mode";
742                         offset = <0x200>;         663                         offset = <0x200>;
743                         mode-normal = <BOOT_NO    664                         mode-normal = <BOOT_NORMAL>;
744                         mode-recovery = <BOOT_    665                         mode-recovery = <BOOT_RECOVERY>;
745                         mode-bootloader = <BOO    666                         mode-bootloader = <BOOT_FASTBOOT>;
746                         mode-loader = <BOOT_BL    667                         mode-loader = <BOOT_BL_DOWNLOAD>;
747                 };                                668                 };
748         };                                        669         };
749                                                   670 
750         cru: clock-controller@ff760000 {          671         cru: clock-controller@ff760000 {
751                 compatible = "rockchip,rk3368-    672                 compatible = "rockchip,rk3368-cru";
752                 reg = <0x0 0xff760000 0x0 0x10    673                 reg = <0x0 0xff760000 0x0 0x1000>;
753                 clocks = <&xin24m>;            << 
754                 clock-names = "xin24m";        << 
755                 rockchip,grf = <&grf>;            674                 rockchip,grf = <&grf>;
756                 #clock-cells = <1>;               675                 #clock-cells = <1>;
757                 #reset-cells = <1>;               676                 #reset-cells = <1>;
758         };                                        677         };
759                                                   678 
760         grf: syscon@ff770000 {                    679         grf: syscon@ff770000 {
761                 compatible = "rockchip,rk3368-    680                 compatible = "rockchip,rk3368-grf", "syscon", "simple-mfd";
762                 reg = <0x0 0xff770000 0x0 0x10    681                 reg = <0x0 0xff770000 0x0 0x1000>;
763                                                   682 
764                 io_domains: io-domains {          683                 io_domains: io-domains {
765                         compatible = "rockchip    684                         compatible = "rockchip,rk3368-io-voltage-domain";
766                         status = "disabled";      685                         status = "disabled";
767                 };                                686                 };
768         };                                        687         };
769                                                   688 
770         wdt: watchdog@ff800000 {                  689         wdt: watchdog@ff800000 {
771                 compatible = "rockchip,rk3368-    690                 compatible = "rockchip,rk3368-wdt", "snps,dw-wdt";
772                 reg = <0x0 0xff800000 0x0 0x10    691                 reg = <0x0 0xff800000 0x0 0x100>;
773                 clocks = <&cru PCLK_WDT>;         692                 clocks = <&cru PCLK_WDT>;
774                 interrupts = <GIC_SPI 79 IRQ_T    693                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
775                 status = "disabled";              694                 status = "disabled";
776         };                                        695         };
777                                                   696 
778         timer0: timer@ff810000 {               !! 697         timer@ff810000 {
779                 compatible = "rockchip,rk3368-    698                 compatible = "rockchip,rk3368-timer", "rockchip,rk3288-timer";
780                 reg = <0x0 0xff810000 0x0 0x20    699                 reg = <0x0 0xff810000 0x0 0x20>;
781                 interrupts = <GIC_SPI 66 IRQ_T    700                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
782                 clocks = <&cru PCLK_TIMER0>, < << 
783                 clock-names = "pclk", "timer"; << 
784         };                                     << 
785                                                << 
786         spdif: spdif@ff880000 {                << 
787                 compatible = "rockchip,rk3368- << 
788                 reg = <0x0 0xff880000 0x0 0x10 << 
789                 interrupts = <GIC_SPI 54 IRQ_T << 
790                 clocks = <&cru SCLK_SPDIF_8CH> << 
791                 clock-names = "mclk", "hclk";  << 
792                 dmas = <&dmac_bus 3>;          << 
793                 dma-names = "tx";              << 
794                 pinctrl-names = "default";     << 
795                 pinctrl-0 = <&spdif_tx>;       << 
796                 #sound-dai-cells = <0>;        << 
797                 status = "disabled";           << 
798         };                                        701         };
799                                                   702 
800         i2s_2ch: i2s-2ch@ff890000 {               703         i2s_2ch: i2s-2ch@ff890000 {
801                 compatible = "rockchip,rk3368-    704                 compatible = "rockchip,rk3368-i2s", "rockchip,rk3066-i2s";
802                 reg = <0x0 0xff890000 0x0 0x10    705                 reg = <0x0 0xff890000 0x0 0x1000>;
803                 interrupts = <GIC_SPI 40 IRQ_T    706                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
804                 clock-names = "i2s_clk", "i2s_    707                 clock-names = "i2s_clk", "i2s_hclk";
805                 clocks = <&cru SCLK_I2S_2CH>,     708                 clocks = <&cru SCLK_I2S_2CH>, <&cru HCLK_I2S_2CH>;
806                 dmas = <&dmac_bus 6>, <&dmac_b    709                 dmas = <&dmac_bus 6>, <&dmac_bus 7>;
807                 dma-names = "tx", "rx";           710                 dma-names = "tx", "rx";
808                 #sound-dai-cells = <0>;        << 
809                 status = "disabled";              711                 status = "disabled";
810         };                                        712         };
811                                                   713 
812         i2s_8ch: i2s-8ch@ff898000 {               714         i2s_8ch: i2s-8ch@ff898000 {
813                 compatible = "rockchip,rk3368-    715                 compatible = "rockchip,rk3368-i2s", "rockchip,rk3066-i2s";
814                 reg = <0x0 0xff898000 0x0 0x10    716                 reg = <0x0 0xff898000 0x0 0x1000>;
815                 interrupts = <GIC_SPI 53 IRQ_T    717                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
816                 clock-names = "i2s_clk", "i2s_    718                 clock-names = "i2s_clk", "i2s_hclk";
817                 clocks = <&cru SCLK_I2S_8CH>,     719                 clocks = <&cru SCLK_I2S_8CH>, <&cru HCLK_I2S_8CH>;
818                 dmas = <&dmac_bus 0>, <&dmac_b    720                 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
819                 dma-names = "tx", "rx";           721                 dma-names = "tx", "rx";
820                 pinctrl-names = "default";        722                 pinctrl-names = "default";
821                 pinctrl-0 = <&i2s_8ch_bus>;       723                 pinctrl-0 = <&i2s_8ch_bus>;
822                 #sound-dai-cells = <0>;        << 
823                 status = "disabled";           << 
824         };                                     << 
825                                                << 
826         iep_mmu: iommu@ff900800 {              << 
827                 compatible = "rockchip,iommu"; << 
828                 reg = <0x0 0xff900800 0x0 0x10 << 
829                 interrupts = <GIC_SPI 17 IRQ_T << 
830                 clocks = <&cru ACLK_IEP>, <&cr << 
831                 clock-names = "aclk", "iface"; << 
832                 power-domains = <&power RK3368 << 
833                 #iommu-cells = <0>;            << 
834                 status = "disabled";           << 
835         };                                     << 
836                                                << 
837         isp_mmu: iommu@ff914000 {              << 
838                 compatible = "rockchip,iommu"; << 
839                 reg = <0x0 0xff914000 0x0 0x10 << 
840                       <0x0 0xff915000 0x0 0x10 << 
841                 interrupts = <GIC_SPI 14 IRQ_T << 
842                 clocks = <&cru ACLK_ISP>, <&cr << 
843                 clock-names = "aclk", "iface"; << 
844                 #iommu-cells = <0>;            << 
845                 power-domains = <&power RK3368 << 
846                 rockchip,disable-mmu-reset;    << 
847                 status = "disabled";           << 
848         };                                     << 
849                                                << 
850         vop_mmu: iommu@ff930300 {              << 
851                 compatible = "rockchip,iommu"; << 
852                 reg = <0x0 0xff930300 0x0 0x10 << 
853                 interrupts = <GIC_SPI 15 IRQ_T << 
854                 clocks = <&cru ACLK_VOP>, <&cr << 
855                 clock-names = "aclk", "iface"; << 
856                 power-domains = <&power RK3368 << 
857                 #iommu-cells = <0>;            << 
858                 status = "disabled";           << 
859         };                                     << 
860                                                << 
861         hevc_mmu: iommu@ff9a0440 {             << 
862                 compatible = "rockchip,iommu"; << 
863                 reg = <0x0 0xff9a0440 0x0 0x40 << 
864                       <0x0 0xff9a0480 0x0 0x40 << 
865                 interrupts = <GIC_SPI 12 IRQ_T << 
866                 clocks = <&cru ACLK_VIDEO>, <& << 
867                 clock-names = "aclk", "iface"; << 
868                 #iommu-cells = <0>;            << 
869                 status = "disabled";              724                 status = "disabled";
870         };                                        725         };
871                                                   726 
872         vpu_mmu: iommu@ff9a0800 {              << 
873                 compatible = "rockchip,iommu"; << 
874                 reg = <0x0 0xff9a0800 0x0 0x10 << 
875                 interrupts = <GIC_SPI 9 IRQ_TY << 
876                              <GIC_SPI 10 IRQ_T << 
877                 clocks = <&cru ACLK_VIDEO>, <& << 
878                 clock-names = "aclk", "iface"; << 
879                 #iommu-cells = <0>;            << 
880                 status = "disabled";           << 
881         };                                     << 
882                                                << 
883         qos_iep: qos@ffad0000 {                << 
884                 compatible = "rockchip,rk3368- << 
885                 reg = <0x0 0xffad0000 0x0 0x20 << 
886         };                                     << 
887                                                << 
888         qos_isp_r0: qos@ffad0080 {             << 
889                 compatible = "rockchip,rk3368- << 
890                 reg = <0x0 0xffad0080 0x0 0x20 << 
891         };                                     << 
892                                                << 
893         qos_isp_r1: qos@ffad0100 {             << 
894                 compatible = "rockchip,rk3368- << 
895                 reg = <0x0 0xffad0100 0x0 0x20 << 
896         };                                     << 
897                                                << 
898         qos_isp_w0: qos@ffad0180 {             << 
899                 compatible = "rockchip,rk3368- << 
900                 reg = <0x0 0xffad0180 0x0 0x20 << 
901         };                                     << 
902                                                << 
903         qos_isp_w1: qos@ffad0200 {             << 
904                 compatible = "rockchip,rk3368- << 
905                 reg = <0x0 0xffad0200 0x0 0x20 << 
906         };                                     << 
907                                                << 
908         qos_vip: qos@ffad0280 {                << 
909                 compatible = "rockchip,rk3368- << 
910                 reg = <0x0 0xffad0280 0x0 0x20 << 
911         };                                     << 
912                                                << 
913         qos_vop: qos@ffad0300 {                << 
914                 compatible = "rockchip,rk3368- << 
915                 reg = <0x0 0xffad0300 0x0 0x20 << 
916         };                                     << 
917                                                << 
918         qos_rga_r: qos@ffad0380 {              << 
919                 compatible = "rockchip,rk3368- << 
920                 reg = <0x0 0xffad0380 0x0 0x20 << 
921         };                                     << 
922                                                << 
923         qos_rga_w: qos@ffad0400 {              << 
924                 compatible = "rockchip,rk3368- << 
925                 reg = <0x0 0xffad0400 0x0 0x20 << 
926         };                                     << 
927                                                << 
928         qos_hevc_r: qos@ffae0000 {             << 
929                 compatible = "rockchip,rk3368- << 
930                 reg = <0x0 0xffae0000 0x0 0x20 << 
931         };                                     << 
932                                                << 
933         qos_vpu_r: qos@ffae0100 {              << 
934                 compatible = "rockchip,rk3368- << 
935                 reg = <0x0 0xffae0100 0x0 0x20 << 
936         };                                     << 
937                                                << 
938         qos_vpu_w: qos@ffae0180 {              << 
939                 compatible = "rockchip,rk3368- << 
940                 reg = <0x0 0xffae0180 0x0 0x20 << 
941         };                                     << 
942                                                << 
943         qos_gpu: qos@ffaf0000 {                << 
944                 compatible = "rockchip,rk3368- << 
945                 reg = <0x0 0xffaf0000 0x0 0x20 << 
946         };                                     << 
947                                                << 
948         efuse256: efuse@ffb00000 {             << 
949                 compatible = "rockchip,rk3368- << 
950                 reg = <0x0 0xffb00000 0x0 0x20 << 
951                 #address-cells = <1>;          << 
952                 #size-cells = <1>;             << 
953                 clocks = <&cru PCLK_EFUSE256>; << 
954                 clock-names = "pclk_efuse";    << 
955                                                << 
956                 cpu_leakage: cpu-leakage@17 {  << 
957                         reg = <0x17 0x1>;      << 
958                 };                             << 
959                 temp_adjust: temp-adjust@1f {  << 
960                         reg = <0x1f 0x1>;      << 
961                 };                             << 
962         };                                     << 
963                                                << 
964         gic: interrupt-controller@ffb71000 {      727         gic: interrupt-controller@ffb71000 {
965                 compatible = "arm,gic-400";       728                 compatible = "arm,gic-400";
966                 interrupt-controller;             729                 interrupt-controller;
967                 #interrupt-cells = <3>;           730                 #interrupt-cells = <3>;
968                 #address-cells = <0>;             731                 #address-cells = <0>;
969                                                   732 
970                 reg = <0x0 0xffb71000 0x0 0x10    733                 reg = <0x0 0xffb71000 0x0 0x1000>,
971                       <0x0 0xffb72000 0x0 0x20    734                       <0x0 0xffb72000 0x0 0x2000>,
972                       <0x0 0xffb74000 0x0 0x20    735                       <0x0 0xffb74000 0x0 0x2000>,
973                       <0x0 0xffb76000 0x0 0x20    736                       <0x0 0xffb76000 0x0 0x2000>;
974                 interrupts = <GIC_PPI 9           737                 interrupts = <GIC_PPI 9
975                       (GIC_CPU_MASK_SIMPLE(8)     738                       (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
976         };                                        739         };
977                                                   740 
978         pinctrl: pinctrl {                        741         pinctrl: pinctrl {
979                 compatible = "rockchip,rk3368-    742                 compatible = "rockchip,rk3368-pinctrl";
980                 rockchip,grf = <&grf>;            743                 rockchip,grf = <&grf>;
981                 rockchip,pmu = <&pmugrf>;         744                 rockchip,pmu = <&pmugrf>;
982                 #address-cells = <0x2>;           745                 #address-cells = <0x2>;
983                 #size-cells = <0x2>;              746                 #size-cells = <0x2>;
984                 ranges;                           747                 ranges;
985                                                   748 
986                 gpio0: gpio@ff750000 {         !! 749                 gpio0: gpio0@ff750000 {
987                         compatible = "rockchip    750                         compatible = "rockchip,gpio-bank";
988                         reg = <0x0 0xff750000     751                         reg = <0x0 0xff750000 0x0 0x100>;
989                         clocks = <&cru PCLK_GP    752                         clocks = <&cru PCLK_GPIO0>;
990                         interrupts = <GIC_SPI     753                         interrupts = <GIC_SPI 0x51 IRQ_TYPE_LEVEL_HIGH>;
991                                                   754 
992                         gpio-controller;          755                         gpio-controller;
993                         #gpio-cells = <0x2>;      756                         #gpio-cells = <0x2>;
994                                                   757 
995                         interrupt-controller;     758                         interrupt-controller;
996                         #interrupt-cells = <0x    759                         #interrupt-cells = <0x2>;
997                 };                                760                 };
998                                                   761 
999                 gpio1: gpio@ff780000 {         !! 762                 gpio1: gpio1@ff780000 {
1000                         compatible = "rockchi    763                         compatible = "rockchip,gpio-bank";
1001                         reg = <0x0 0xff780000    764                         reg = <0x0 0xff780000 0x0 0x100>;
1002                         clocks = <&cru PCLK_G    765                         clocks = <&cru PCLK_GPIO1>;
1003                         interrupts = <GIC_SPI    766                         interrupts = <GIC_SPI 0x52 IRQ_TYPE_LEVEL_HIGH>;
1004                                                  767 
1005                         gpio-controller;         768                         gpio-controller;
1006                         #gpio-cells = <0x2>;     769                         #gpio-cells = <0x2>;
1007                                                  770 
1008                         interrupt-controller;    771                         interrupt-controller;
1009                         #interrupt-cells = <0    772                         #interrupt-cells = <0x2>;
1010                 };                               773                 };
1011                                                  774 
1012                 gpio2: gpio@ff790000 {        !! 775                 gpio2: gpio2@ff790000 {
1013                         compatible = "rockchi    776                         compatible = "rockchip,gpio-bank";
1014                         reg = <0x0 0xff790000    777                         reg = <0x0 0xff790000 0x0 0x100>;
1015                         clocks = <&cru PCLK_G    778                         clocks = <&cru PCLK_GPIO2>;
1016                         interrupts = <GIC_SPI    779                         interrupts = <GIC_SPI 0x53 IRQ_TYPE_LEVEL_HIGH>;
1017                                                  780 
1018                         gpio-controller;         781                         gpio-controller;
1019                         #gpio-cells = <0x2>;     782                         #gpio-cells = <0x2>;
1020                                                  783 
1021                         interrupt-controller;    784                         interrupt-controller;
1022                         #interrupt-cells = <0    785                         #interrupt-cells = <0x2>;
1023                 };                               786                 };
1024                                                  787 
1025                 gpio3: gpio@ff7a0000 {        !! 788                 gpio3: gpio3@ff7a0000 {
1026                         compatible = "rockchi    789                         compatible = "rockchip,gpio-bank";
1027                         reg = <0x0 0xff7a0000    790                         reg = <0x0 0xff7a0000 0x0 0x100>;
1028                         clocks = <&cru PCLK_G    791                         clocks = <&cru PCLK_GPIO3>;
1029                         interrupts = <GIC_SPI    792                         interrupts = <GIC_SPI 0x54 IRQ_TYPE_LEVEL_HIGH>;
1030                                                  793 
1031                         gpio-controller;         794                         gpio-controller;
1032                         #gpio-cells = <0x2>;     795                         #gpio-cells = <0x2>;
1033                                                  796 
1034                         interrupt-controller;    797                         interrupt-controller;
1035                         #interrupt-cells = <0    798                         #interrupt-cells = <0x2>;
1036                 };                               799                 };
1037                                                  800 
1038                 pcfg_pull_up: pcfg-pull-up {     801                 pcfg_pull_up: pcfg-pull-up {
1039                         bias-pull-up;            802                         bias-pull-up;
1040                 };                               803                 };
1041                                                  804 
1042                 pcfg_pull_down: pcfg-pull-dow    805                 pcfg_pull_down: pcfg-pull-down {
1043                         bias-pull-down;          806                         bias-pull-down;
1044                 };                               807                 };
1045                                                  808 
1046                 pcfg_pull_none: pcfg-pull-non    809                 pcfg_pull_none: pcfg-pull-none {
1047                         bias-disable;            810                         bias-disable;
1048                 };                               811                 };
1049                                                  812 
1050                 pcfg_pull_none_12ma: pcfg-pul    813                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1051                         bias-disable;            814                         bias-disable;
1052                         drive-strength = <12>    815                         drive-strength = <12>;
1053                 };                               816                 };
1054                                                  817 
1055                 emmc {                           818                 emmc {
1056                         emmc_clk: emmc-clk {     819                         emmc_clk: emmc-clk {
1057                                 rockchip,pins !! 820                                 rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>;
1058                         };                       821                         };
1059                                                  822 
1060                         emmc_cmd: emmc-cmd {     823                         emmc_cmd: emmc-cmd {
1061                                 rockchip,pins !! 824                                 rockchip,pins = <1 26 RK_FUNC_2 &pcfg_pull_up>;
1062                         };                       825                         };
1063                                                  826 
1064                         emmc_pwr: emmc-pwr {     827                         emmc_pwr: emmc-pwr {
1065                                 rockchip,pins !! 828                                 rockchip,pins = <1 27 RK_FUNC_2 &pcfg_pull_up>;
1066                         };                       829                         };
1067                                                  830 
1068                         emmc_bus1: emmc-bus1     831                         emmc_bus1: emmc-bus1 {
1069                                 rockchip,pins !! 832                                 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>;
1070                         };                       833                         };
1071                                                  834 
1072                         emmc_bus4: emmc-bus4     835                         emmc_bus4: emmc-bus4 {
1073                                 rockchip,pins !! 836                                 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>,
1074                                               !! 837                                                 <1 19 RK_FUNC_2 &pcfg_pull_up>,
1075                                               !! 838                                                 <1 20 RK_FUNC_2 &pcfg_pull_up>,
1076                                               !! 839                                                 <1 21 RK_FUNC_2 &pcfg_pull_up>;
1077                         };                       840                         };
1078                                                  841 
1079                         emmc_bus8: emmc-bus8     842                         emmc_bus8: emmc-bus8 {
1080                                 rockchip,pins !! 843                                 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>,
1081                                               !! 844                                                 <1 19 RK_FUNC_2 &pcfg_pull_up>,
1082                                               !! 845                                                 <1 20 RK_FUNC_2 &pcfg_pull_up>,
1083                                               !! 846                                                 <1 21 RK_FUNC_2 &pcfg_pull_up>,
1084                                               !! 847                                                 <1 22 RK_FUNC_2 &pcfg_pull_up>,
1085                                               !! 848                                                 <1 23 RK_FUNC_2 &pcfg_pull_up>,
1086                                               !! 849                                                 <1 24 RK_FUNC_2 &pcfg_pull_up>,
1087                                               !! 850                                                 <1 25 RK_FUNC_2 &pcfg_pull_up>;
1088                         };                       851                         };
1089                 };                               852                 };
1090                                                  853 
1091                 gmac {                           854                 gmac {
1092                         rgmii_pins: rgmii-pin    855                         rgmii_pins: rgmii-pins {
1093                                 rockchip,pins !! 856                                 rockchip,pins = <3 22 RK_FUNC_1 &pcfg_pull_none>,
1094                                               !! 857                                                 <3 24 RK_FUNC_1 &pcfg_pull_none>,
1095                                               !! 858                                                 <3 19 RK_FUNC_1 &pcfg_pull_none>,
1096                                               !! 859                                                 <3 8 RK_FUNC_1 &pcfg_pull_none_12ma>,
1097                                               !! 860                                                 <3 9 RK_FUNC_1 &pcfg_pull_none_12ma>,
1098                                               !! 861                                                 <3 10 RK_FUNC_1 &pcfg_pull_none_12ma>,
1099                                               !! 862                                                 <3 14 RK_FUNC_1 &pcfg_pull_none_12ma>,
1100                                               !! 863                                                 <3 28 RK_FUNC_1 &pcfg_pull_none_12ma>,
1101                                               !! 864                                                 <3 13 RK_FUNC_1 &pcfg_pull_none_12ma>,
1102                                               !! 865                                                 <3 15 RK_FUNC_1 &pcfg_pull_none>,
1103                                               !! 866                                                 <3 16 RK_FUNC_1 &pcfg_pull_none>,
1104                                               !! 867                                                 <3 17 RK_FUNC_1 &pcfg_pull_none>,
1105                                               !! 868                                                 <3 18 RK_FUNC_1 &pcfg_pull_none>,
1106                                               !! 869                                                 <3 25 RK_FUNC_1 &pcfg_pull_none>,
1107                                               !! 870                                                 <3 20 RK_FUNC_1 &pcfg_pull_none>;
1108                         };                       871                         };
1109                                                  872 
1110                         rmii_pins: rmii-pins     873                         rmii_pins: rmii-pins {
1111                                 rockchip,pins !! 874                                 rockchip,pins = <3 22 RK_FUNC_1 &pcfg_pull_none>,
1112                                               !! 875                                                 <3 24 RK_FUNC_1 &pcfg_pull_none>,
1113                                               !! 876                                                 <3 19 RK_FUNC_1 &pcfg_pull_none>,
1114                                               !! 877                                                 <3 8 RK_FUNC_1 &pcfg_pull_none_12ma>,
1115                                               !! 878                                                 <3 9 RK_FUNC_1 &pcfg_pull_none_12ma>,
1116                                               !! 879                                                 <3 13 RK_FUNC_1 &pcfg_pull_none_12ma>,
1117                                               !! 880                                                 <3 15 RK_FUNC_1 &pcfg_pull_none>,
1118                                               !! 881                                                 <3 16 RK_FUNC_1 &pcfg_pull_none>,
1119                                               !! 882                                                 <3 20 RK_FUNC_1 &pcfg_pull_none>,
1120                                               !! 883                                                 <3 21 RK_FUNC_1 &pcfg_pull_none>;
1121                         };                       884                         };
1122                 };                               885                 };
1123                                                  886 
1124                 i2c0 {                           887                 i2c0 {
1125                         i2c0_xfer: i2c0-xfer     888                         i2c0_xfer: i2c0-xfer {
1126                                 rockchip,pins !! 889                                 rockchip,pins = <0 6 RK_FUNC_1 &pcfg_pull_none>,
1127                                               !! 890                                                 <0 7 RK_FUNC_1 &pcfg_pull_none>;
1128                         };                       891                         };
1129                 };                               892                 };
1130                                                  893 
1131                 i2c1 {                           894                 i2c1 {
1132                         i2c1_xfer: i2c1-xfer     895                         i2c1_xfer: i2c1-xfer {
1133                                 rockchip,pins !! 896                                 rockchip,pins = <2 21 RK_FUNC_1 &pcfg_pull_none>,
1134                                               !! 897                                                 <2 22 RK_FUNC_1 &pcfg_pull_none>;
1135                         };                       898                         };
1136                 };                               899                 };
1137                                                  900 
1138                 i2c2 {                           901                 i2c2 {
1139                         i2c2_xfer: i2c2-xfer     902                         i2c2_xfer: i2c2-xfer {
1140                                 rockchip,pins !! 903                                 rockchip,pins = <0 9 RK_FUNC_2 &pcfg_pull_none>,
1141                                               !! 904                                                 <3 31 RK_FUNC_2 &pcfg_pull_none>;
1142                         };                       905                         };
1143                 };                               906                 };
1144                                                  907 
1145                 i2c3 {                           908                 i2c3 {
1146                         i2c3_xfer: i2c3-xfer     909                         i2c3_xfer: i2c3-xfer {
1147                                 rockchip,pins !! 910                                 rockchip,pins = <1 16 RK_FUNC_1 &pcfg_pull_none>,
1148                                               !! 911                                                 <1 17 RK_FUNC_1 &pcfg_pull_none>;
1149                         };                       912                         };
1150                 };                               913                 };
1151                                                  914 
1152                 i2c4 {                           915                 i2c4 {
1153                         i2c4_xfer: i2c4-xfer     916                         i2c4_xfer: i2c4-xfer {
1154                                 rockchip,pins !! 917                                 rockchip,pins = <3 24 RK_FUNC_2 &pcfg_pull_none>,
1155                                               !! 918                                                 <3 25 RK_FUNC_2 &pcfg_pull_none>;
1156                         };                       919                         };
1157                 };                               920                 };
1158                                                  921 
1159                 i2c5 {                           922                 i2c5 {
1160                         i2c5_xfer: i2c5-xfer     923                         i2c5_xfer: i2c5-xfer {
1161                                 rockchip,pins !! 924                                 rockchip,pins = <3 26 RK_FUNC_2 &pcfg_pull_none>,
1162                                               !! 925                                                 <3 27 RK_FUNC_2 &pcfg_pull_none>;
1163                         };                       926                         };
1164                 };                               927                 };
1165                                                  928 
1166                 i2s {                            929                 i2s {
1167                         i2s_8ch_bus: i2s-8ch-    930                         i2s_8ch_bus: i2s-8ch-bus {
1168                                 rockchip,pins !! 931                                 rockchip,pins = <2 12 RK_FUNC_1 &pcfg_pull_none>,
1169                                               !! 932                                                 <2 13 RK_FUNC_1 &pcfg_pull_none>,
1170                                               !! 933                                                 <2 14 RK_FUNC_1 &pcfg_pull_none>,
1171                                               !! 934                                                 <2 15 RK_FUNC_1 &pcfg_pull_none>,
1172                                               !! 935                                                 <2 16 RK_FUNC_1 &pcfg_pull_none>,
1173                                               !! 936                                                 <2 17 RK_FUNC_1 &pcfg_pull_none>,
1174                                               !! 937                                                 <2 18 RK_FUNC_1 &pcfg_pull_none>,
1175                                               !! 938                                                 <2 19 RK_FUNC_1 &pcfg_pull_none>,
1176                                               !! 939                                                 <2 20 RK_FUNC_1 &pcfg_pull_none>;
1177                         };                       940                         };
1178                 };                               941                 };
1179                                                  942 
1180                 pwm0 {                           943                 pwm0 {
1181                         pwm0_pin: pwm0-pin {     944                         pwm0_pin: pwm0-pin {
1182                                 rockchip,pins !! 945                                 rockchip,pins = <3 8 RK_FUNC_2 &pcfg_pull_none>;
1183                         };                       946                         };
1184                 };                               947                 };
1185                                                  948 
1186                 pwm1 {                           949                 pwm1 {
1187                         pwm1_pin: pwm1-pin {     950                         pwm1_pin: pwm1-pin {
1188                                 rockchip,pins !! 951                                 rockchip,pins = <0 8 RK_FUNC_2 &pcfg_pull_none>;
1189                         };                       952                         };
1190                 };                               953                 };
1191                                                  954 
1192                 pwm3 {                           955                 pwm3 {
1193                         pwm3_pin: pwm3-pin {     956                         pwm3_pin: pwm3-pin {
1194                                 rockchip,pins !! 957                                 rockchip,pins = <3 29 RK_FUNC_3 &pcfg_pull_none>;
1195                         };                       958                         };
1196                 };                               959                 };
1197                                                  960 
1198                 sdio0 {                          961                 sdio0 {
1199                         sdio0_bus1: sdio0-bus    962                         sdio0_bus1: sdio0-bus1 {
1200                                 rockchip,pins !! 963                                 rockchip,pins = <2 28 RK_FUNC_1 &pcfg_pull_up>;
1201                         };                       964                         };
1202                                                  965 
1203                         sdio0_bus4: sdio0-bus    966                         sdio0_bus4: sdio0-bus4 {
1204                                 rockchip,pins !! 967                                 rockchip,pins = <2 28 RK_FUNC_1 &pcfg_pull_up>,
1205                                               !! 968                                                 <2 29 RK_FUNC_1 &pcfg_pull_up>,
1206                                               !! 969                                                 <2 30 RK_FUNC_1 &pcfg_pull_up>,
1207                                               !! 970                                                 <2 31 RK_FUNC_1 &pcfg_pull_up>;
1208                         };                       971                         };
1209                                                  972 
1210                         sdio0_cmd: sdio0-cmd     973                         sdio0_cmd: sdio0-cmd {
1211                                 rockchip,pins !! 974                                 rockchip,pins = <3 0 RK_FUNC_1 &pcfg_pull_up>;
1212                         };                       975                         };
1213                                                  976 
1214                         sdio0_clk: sdio0-clk     977                         sdio0_clk: sdio0-clk {
1215                                 rockchip,pins !! 978                                 rockchip,pins = <3 1 RK_FUNC_1 &pcfg_pull_none>;
1216                         };                       979                         };
1217                                                  980 
1218                         sdio0_cd: sdio0-cd {     981                         sdio0_cd: sdio0-cd {
1219                                 rockchip,pins !! 982                                 rockchip,pins = <3 2 RK_FUNC_1 &pcfg_pull_up>;
1220                         };                       983                         };
1221                                                  984 
1222                         sdio0_wp: sdio0-wp {     985                         sdio0_wp: sdio0-wp {
1223                                 rockchip,pins !! 986                                 rockchip,pins = <3 3 RK_FUNC_1 &pcfg_pull_up>;
1224                         };                       987                         };
1225                                                  988 
1226                         sdio0_pwr: sdio0-pwr     989                         sdio0_pwr: sdio0-pwr {
1227                                 rockchip,pins !! 990                                 rockchip,pins = <3 4 RK_FUNC_1 &pcfg_pull_up>;
1228                         };                       991                         };
1229                                                  992 
1230                         sdio0_bkpwr: sdio0-bk    993                         sdio0_bkpwr: sdio0-bkpwr {
1231                                 rockchip,pins !! 994                                 rockchip,pins = <3 5 RK_FUNC_1 &pcfg_pull_up>;
1232                         };                       995                         };
1233                                                  996 
1234                         sdio0_int: sdio0-int     997                         sdio0_int: sdio0-int {
1235                                 rockchip,pins !! 998                                 rockchip,pins = <3 6 RK_FUNC_1 &pcfg_pull_up>;
1236                         };                       999                         };
1237                 };                               1000                 };
1238                                                  1001 
1239                 sdmmc {                          1002                 sdmmc {
1240                         sdmmc_clk: sdmmc-clk     1003                         sdmmc_clk: sdmmc-clk {
1241                                 rockchip,pins !! 1004                                 rockchip,pins = <2 9 RK_FUNC_1 &pcfg_pull_none>;
1242                         };                       1005                         };
1243                                                  1006 
1244                         sdmmc_cmd: sdmmc-cmd     1007                         sdmmc_cmd: sdmmc-cmd {
1245                                 rockchip,pins !! 1008                                 rockchip,pins = <2 10 RK_FUNC_1 &pcfg_pull_up>;
1246                         };                       1009                         };
1247                                                  1010 
1248                         sdmmc_cd: sdmmc-cd {     1011                         sdmmc_cd: sdmmc-cd {
1249                                 rockchip,pins !! 1012                                 rockchip,pins = <2 11 RK_FUNC_1 &pcfg_pull_up>;
1250                         };                       1013                         };
1251                                                  1014 
1252                         sdmmc_bus1: sdmmc-bus    1015                         sdmmc_bus1: sdmmc-bus1 {
1253                                 rockchip,pins !! 1016                                 rockchip,pins = <2 5 RK_FUNC_1 &pcfg_pull_up>;
1254                         };                       1017                         };
1255                                                  1018 
1256                         sdmmc_bus4: sdmmc-bus    1019                         sdmmc_bus4: sdmmc-bus4 {
1257                                 rockchip,pins !! 1020                                 rockchip,pins = <2 5 RK_FUNC_1 &pcfg_pull_up>,
1258                                               !! 1021                                                 <2 6 RK_FUNC_1 &pcfg_pull_up>,
1259                                               !! 1022                                                 <2 7 RK_FUNC_1 &pcfg_pull_up>,
1260                                               !! 1023                                                 <2 8 RK_FUNC_1 &pcfg_pull_up>;
1261                         };                    << 
1262                 };                            << 
1263                                               << 
1264                 spdif {                       << 
1265                         spdif_tx: spdif-tx {  << 
1266                                 rockchip,pins << 
1267                         };                       1024                         };
1268                 };                               1025                 };
1269                                                  1026 
1270                 spi0 {                           1027                 spi0 {
1271                         spi0_clk: spi0-clk {     1028                         spi0_clk: spi0-clk {
1272                                 rockchip,pins !! 1029                                 rockchip,pins = <1 29 RK_FUNC_2 &pcfg_pull_up>;
1273                         };                       1030                         };
1274                         spi0_cs0: spi0-cs0 {     1031                         spi0_cs0: spi0-cs0 {
1275                                 rockchip,pins !! 1032                                 rockchip,pins = <1 24 RK_FUNC_3 &pcfg_pull_up>;
1276                         };                       1033                         };
1277                         spi0_cs1: spi0-cs1 {     1034                         spi0_cs1: spi0-cs1 {
1278                                 rockchip,pins !! 1035                                 rockchip,pins = <1 25 RK_FUNC_3 &pcfg_pull_up>;
1279                         };                       1036                         };
1280                         spi0_tx: spi0-tx {       1037                         spi0_tx: spi0-tx {
1281                                 rockchip,pins !! 1038                                 rockchip,pins = <1 23 RK_FUNC_3 &pcfg_pull_up>;
1282                         };                       1039                         };
1283                         spi0_rx: spi0-rx {       1040                         spi0_rx: spi0-rx {
1284                                 rockchip,pins !! 1041                                 rockchip,pins = <1 22 RK_FUNC_3 &pcfg_pull_up>;
1285                         };                       1042                         };
1286                 };                               1043                 };
1287                                                  1044 
1288                 spi1 {                           1045                 spi1 {
1289                         spi1_clk: spi1-clk {     1046                         spi1_clk: spi1-clk {
1290                                 rockchip,pins !! 1047                                 rockchip,pins = <1 14 RK_FUNC_2 &pcfg_pull_up>;
1291                         };                       1048                         };
1292                         spi1_cs0: spi1-cs0 {     1049                         spi1_cs0: spi1-cs0 {
1293                                 rockchip,pins !! 1050                                 rockchip,pins = <1 15 RK_FUNC_2 &pcfg_pull_up>;
1294                         };                       1051                         };
1295                         spi1_cs1: spi1-cs1 {     1052                         spi1_cs1: spi1-cs1 {
1296                                 rockchip,pins !! 1053                                 rockchip,pins = <3 28 RK_FUNC_2 &pcfg_pull_up>;
1297                         };                       1054                         };
1298                         spi1_rx: spi1-rx {       1055                         spi1_rx: spi1-rx {
1299                                 rockchip,pins !! 1056                                 rockchip,pins = <1 16 RK_FUNC_2 &pcfg_pull_up>;
1300                         };                       1057                         };
1301                         spi1_tx: spi1-tx {       1058                         spi1_tx: spi1-tx {
1302                                 rockchip,pins !! 1059                                 rockchip,pins = <1 17 RK_FUNC_2 &pcfg_pull_up>;
1303                         };                       1060                         };
1304                 };                               1061                 };
1305                                                  1062 
1306                 spi2 {                           1063                 spi2 {
1307                         spi2_clk: spi2-clk {     1064                         spi2_clk: spi2-clk {
1308                                 rockchip,pins !! 1065                                 rockchip,pins = <0 12 RK_FUNC_2 &pcfg_pull_up>;
1309                         };                       1066                         };
1310                         spi2_cs0: spi2-cs0 {     1067                         spi2_cs0: spi2-cs0 {
1311                                 rockchip,pins !! 1068                                 rockchip,pins = <0 13 RK_FUNC_2 &pcfg_pull_up>;
1312                         };                       1069                         };
1313                         spi2_rx: spi2-rx {       1070                         spi2_rx: spi2-rx {
1314                                 rockchip,pins !! 1071                                 rockchip,pins = <0 10 RK_FUNC_2 &pcfg_pull_up>;
1315                         };                       1072                         };
1316                         spi2_tx: spi2-tx {       1073                         spi2_tx: spi2-tx {
1317                                 rockchip,pins !! 1074                                 rockchip,pins = <0 11 RK_FUNC_2 &pcfg_pull_up>;
1318                         };                       1075                         };
1319                 };                               1076                 };
1320                                                  1077 
1321                 tsadc {                          1078                 tsadc {
1322                         otp_pin: otp-pin {    !! 1079                         otp_gpio: otp-gpio {
1323                                 rockchip,pins !! 1080                                 rockchip,pins = <0 3 RK_FUNC_GPIO &pcfg_pull_none>;
1324                         };                       1081                         };
1325                                                  1082 
1326                         otp_out: otp-out {       1083                         otp_out: otp-out {
1327                                 rockchip,pins !! 1084                                 rockchip,pins = <0 3 RK_FUNC_1 &pcfg_pull_none>;
1328                         };                       1085                         };
1329                 };                               1086                 };
1330                                                  1087 
1331                 uart0 {                          1088                 uart0 {
1332                         uart0_xfer: uart0-xfe    1089                         uart0_xfer: uart0-xfer {
1333                                 rockchip,pins !! 1090                                 rockchip,pins = <2 24 RK_FUNC_1 &pcfg_pull_up>,
1334                                               !! 1091                                                 <2 25 RK_FUNC_1 &pcfg_pull_none>;
1335                         };                       1092                         };
1336                                                  1093 
1337                         uart0_cts: uart0-cts     1094                         uart0_cts: uart0-cts {
1338                                 rockchip,pins !! 1095                                 rockchip,pins = <2 26 RK_FUNC_1 &pcfg_pull_none>;
1339                         };                       1096                         };
1340                                                  1097 
1341                         uart0_rts: uart0-rts     1098                         uart0_rts: uart0-rts {
1342                                 rockchip,pins !! 1099                                 rockchip,pins = <2 27 RK_FUNC_1 &pcfg_pull_none>;
1343                         };                       1100                         };
1344                 };                               1101                 };
1345                                                  1102 
1346                 uart1 {                          1103                 uart1 {
1347                         uart1_xfer: uart1-xfe    1104                         uart1_xfer: uart1-xfer {
1348                                 rockchip,pins !! 1105                                 rockchip,pins = <0 20 RK_FUNC_3 &pcfg_pull_up>,
1349                                               !! 1106                                                 <0 21 RK_FUNC_3 &pcfg_pull_none>;
1350                         };                       1107                         };
1351                                                  1108 
1352                         uart1_cts: uart1-cts     1109                         uart1_cts: uart1-cts {
1353                                 rockchip,pins !! 1110                                 rockchip,pins = <0 22 RK_FUNC_3 &pcfg_pull_none>;
1354                         };                       1111                         };
1355                                                  1112 
1356                         uart1_rts: uart1-rts     1113                         uart1_rts: uart1-rts {
1357                                 rockchip,pins !! 1114                                 rockchip,pins = <0 23 RK_FUNC_3 &pcfg_pull_none>;
1358                         };                       1115                         };
1359                 };                               1116                 };
1360                                                  1117 
1361                 uart2 {                          1118                 uart2 {
1362                         uart2_xfer: uart2-xfe    1119                         uart2_xfer: uart2-xfer {
1363                                 rockchip,pins !! 1120                                 rockchip,pins = <2 6 RK_FUNC_2 &pcfg_pull_up>,
1364                                               !! 1121                                                 <2 5 RK_FUNC_2 &pcfg_pull_none>;
1365                         };                       1122                         };
1366                         /* no rts / cts for u    1123                         /* no rts / cts for uart2 */
1367                 };                               1124                 };
1368                                                  1125 
1369                 uart3 {                          1126                 uart3 {
1370                         uart3_xfer: uart3-xfe    1127                         uart3_xfer: uart3-xfer {
1371                                 rockchip,pins !! 1128                                 rockchip,pins = <3 29 RK_FUNC_2 &pcfg_pull_up>,
1372                                               !! 1129                                                 <3 30 RK_FUNC_3 &pcfg_pull_none>;
1373                         };                       1130                         };
1374                                                  1131 
1375                         uart3_cts: uart3-cts     1132                         uart3_cts: uart3-cts {
1376                                 rockchip,pins !! 1133                                 rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_none>;
1377                         };                       1134                         };
1378                                                  1135 
1379                         uart3_rts: uart3-rts     1136                         uart3_rts: uart3-rts {
1380                                 rockchip,pins !! 1137                                 rockchip,pins = <3 17 RK_FUNC_2 &pcfg_pull_none>;
1381                         };                       1138                         };
1382                 };                               1139                 };
1383                                                  1140 
1384                 uart4 {                          1141                 uart4 {
1385                         uart4_xfer: uart4-xfe    1142                         uart4_xfer: uart4-xfer {
1386                                 rockchip,pins !! 1143                                 rockchip,pins = <0 27 RK_FUNC_3 &pcfg_pull_up>,
1387                                               !! 1144                                                 <0 26 RK_FUNC_3 &pcfg_pull_none>;
1388                         };                       1145                         };
1389                                                  1146 
1390                         uart4_cts: uart4-cts     1147                         uart4_cts: uart4-cts {
1391                                 rockchip,pins !! 1148                                 rockchip,pins = <0 24 RK_FUNC_3 &pcfg_pull_none>;
1392                         };                       1149                         };
1393                                                  1150 
1394                         uart4_rts: uart4-rts     1151                         uart4_rts: uart4-rts {
1395                                 rockchip,pins !! 1152                                 rockchip,pins = <0 25 RK_FUNC_3 &pcfg_pull_none>;
1396                         };                       1153                         };
1397                 };                               1154                 };
1398         };                                       1155         };
1399 };                                               1156 };
                                                      

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