1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /* 2 /*
3 * Copyright (c) 2015 Heiko Stuebner <heiko@snt 3 * Copyright (c) 2015 Heiko Stuebner <heiko@sntech.de>
4 */ 4 */
5 5
6 #include <dt-bindings/clock/rk3368-cru.h> 6 #include <dt-bindings/clock/rk3368-cru.h>
7 #include <dt-bindings/gpio/gpio.h> 7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/interrupt-controller/irq 8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/interrupt-controller/arm 9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/pinctrl/rockchip.h> 10 #include <dt-bindings/pinctrl/rockchip.h>
11 #include <dt-bindings/power/rk3368-power.h> <<
12 #include <dt-bindings/soc/rockchip,boot-mode.h 11 #include <dt-bindings/soc/rockchip,boot-mode.h>
13 #include <dt-bindings/thermal/thermal.h> 12 #include <dt-bindings/thermal/thermal.h>
14 13
15 / { 14 / {
16 compatible = "rockchip,rk3368"; 15 compatible = "rockchip,rk3368";
17 interrupt-parent = <&gic>; 16 interrupt-parent = <&gic>;
18 #address-cells = <2>; 17 #address-cells = <2>;
19 #size-cells = <2>; 18 #size-cells = <2>;
20 19
21 aliases { 20 aliases {
22 gpio0 = &gpio0; !! 21 ethernet0 = &gmac;
23 gpio1 = &gpio1; <<
24 gpio2 = &gpio2; <<
25 gpio3 = &gpio3; <<
26 i2c0 = &i2c0; 22 i2c0 = &i2c0;
27 i2c1 = &i2c1; 23 i2c1 = &i2c1;
28 i2c2 = &i2c2; 24 i2c2 = &i2c2;
29 i2c3 = &i2c3; 25 i2c3 = &i2c3;
30 i2c4 = &i2c4; 26 i2c4 = &i2c4;
31 i2c5 = &i2c5; 27 i2c5 = &i2c5;
32 serial0 = &uart0; 28 serial0 = &uart0;
33 serial1 = &uart1; 29 serial1 = &uart1;
34 serial2 = &uart2; 30 serial2 = &uart2;
35 serial3 = &uart3; 31 serial3 = &uart3;
36 serial4 = &uart4; 32 serial4 = &uart4;
37 spi0 = &spi0; 33 spi0 = &spi0;
38 spi1 = &spi1; 34 spi1 = &spi1;
39 spi2 = &spi2; 35 spi2 = &spi2;
40 }; 36 };
41 37
42 cpus { 38 cpus {
43 #address-cells = <0x2>; 39 #address-cells = <0x2>;
44 #size-cells = <0x0>; 40 #size-cells = <0x0>;
45 41
46 cpu-map { 42 cpu-map {
47 cluster0 { 43 cluster0 {
48 core0 { 44 core0 {
49 cpu = 45 cpu = <&cpu_b0>;
50 }; 46 };
51 core1 { 47 core1 {
52 cpu = 48 cpu = <&cpu_b1>;
53 }; 49 };
54 core2 { 50 core2 {
55 cpu = 51 cpu = <&cpu_b2>;
56 }; 52 };
57 core3 { 53 core3 {
58 cpu = 54 cpu = <&cpu_b3>;
59 }; 55 };
60 }; 56 };
61 57
62 cluster1 { 58 cluster1 {
63 core0 { 59 core0 {
64 cpu = 60 cpu = <&cpu_l0>;
65 }; 61 };
66 core1 { 62 core1 {
67 cpu = 63 cpu = <&cpu_l1>;
68 }; 64 };
69 core2 { 65 core2 {
70 cpu = 66 cpu = <&cpu_l2>;
71 }; 67 };
72 core3 { 68 core3 {
73 cpu = 69 cpu = <&cpu_l3>;
74 }; 70 };
75 }; 71 };
76 }; 72 };
77 73
78 cpu_l0: cpu@0 { 74 cpu_l0: cpu@0 {
79 device_type = "cpu"; 75 device_type = "cpu";
80 compatible = "arm,cort 76 compatible = "arm,cortex-a53";
81 reg = <0x0 0x0>; 77 reg = <0x0 0x0>;
82 enable-method = "psci" 78 enable-method = "psci";
83 #cooling-cells = <2>; 79 #cooling-cells = <2>; /* min followed by max */
84 }; 80 };
85 81
86 cpu_l1: cpu@1 { 82 cpu_l1: cpu@1 {
87 device_type = "cpu"; 83 device_type = "cpu";
88 compatible = "arm,cort 84 compatible = "arm,cortex-a53";
89 reg = <0x0 0x1>; 85 reg = <0x0 0x1>;
90 enable-method = "psci" 86 enable-method = "psci";
91 #cooling-cells = <2>; 87 #cooling-cells = <2>; /* min followed by max */
92 }; 88 };
93 89
94 cpu_l2: cpu@2 { 90 cpu_l2: cpu@2 {
95 device_type = "cpu"; 91 device_type = "cpu";
96 compatible = "arm,cort 92 compatible = "arm,cortex-a53";
97 reg = <0x0 0x2>; 93 reg = <0x0 0x2>;
98 enable-method = "psci" 94 enable-method = "psci";
99 #cooling-cells = <2>; 95 #cooling-cells = <2>; /* min followed by max */
100 }; 96 };
101 97
102 cpu_l3: cpu@3 { 98 cpu_l3: cpu@3 {
103 device_type = "cpu"; 99 device_type = "cpu";
104 compatible = "arm,cort 100 compatible = "arm,cortex-a53";
105 reg = <0x0 0x3>; 101 reg = <0x0 0x3>;
106 enable-method = "psci" 102 enable-method = "psci";
107 #cooling-cells = <2>; 103 #cooling-cells = <2>; /* min followed by max */
108 }; 104 };
109 105
110 cpu_b0: cpu@100 { 106 cpu_b0: cpu@100 {
111 device_type = "cpu"; 107 device_type = "cpu";
112 compatible = "arm,cort 108 compatible = "arm,cortex-a53";
113 reg = <0x0 0x100>; 109 reg = <0x0 0x100>;
114 enable-method = "psci" 110 enable-method = "psci";
115 #cooling-cells = <2>; 111 #cooling-cells = <2>; /* min followed by max */
116 }; 112 };
117 113
118 cpu_b1: cpu@101 { 114 cpu_b1: cpu@101 {
119 device_type = "cpu"; 115 device_type = "cpu";
120 compatible = "arm,cort 116 compatible = "arm,cortex-a53";
121 reg = <0x0 0x101>; 117 reg = <0x0 0x101>;
122 enable-method = "psci" 118 enable-method = "psci";
123 #cooling-cells = <2>; 119 #cooling-cells = <2>; /* min followed by max */
124 }; 120 };
125 121
126 cpu_b2: cpu@102 { 122 cpu_b2: cpu@102 {
127 device_type = "cpu"; 123 device_type = "cpu";
128 compatible = "arm,cort 124 compatible = "arm,cortex-a53";
129 reg = <0x0 0x102>; 125 reg = <0x0 0x102>;
130 enable-method = "psci" 126 enable-method = "psci";
131 #cooling-cells = <2>; 127 #cooling-cells = <2>; /* min followed by max */
132 }; 128 };
133 129
134 cpu_b3: cpu@103 { 130 cpu_b3: cpu@103 {
135 device_type = "cpu"; 131 device_type = "cpu";
136 compatible = "arm,cort 132 compatible = "arm,cortex-a53";
137 reg = <0x0 0x103>; 133 reg = <0x0 0x103>;
138 enable-method = "psci" 134 enable-method = "psci";
139 #cooling-cells = <2>; 135 #cooling-cells = <2>; /* min followed by max */
140 }; 136 };
141 }; 137 };
142 138
>> 139 amba: bus {
>> 140 compatible = "simple-bus";
>> 141 #address-cells = <2>;
>> 142 #size-cells = <2>;
>> 143 ranges;
>> 144
>> 145 dmac_peri: dma-controller@ff250000 {
>> 146 compatible = "arm,pl330", "arm,primecell";
>> 147 reg = <0x0 0xff250000 0x0 0x4000>;
>> 148 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
>> 149 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
>> 150 #dma-cells = <1>;
>> 151 arm,pl330-broken-no-flushp;
>> 152 arm,pl330-periph-burst;
>> 153 clocks = <&cru ACLK_DMAC_PERI>;
>> 154 clock-names = "apb_pclk";
>> 155 };
>> 156
>> 157 dmac_bus: dma-controller@ff600000 {
>> 158 compatible = "arm,pl330", "arm,primecell";
>> 159 reg = <0x0 0xff600000 0x0 0x4000>;
>> 160 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
>> 161 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
>> 162 #dma-cells = <1>;
>> 163 arm,pl330-broken-no-flushp;
>> 164 arm,pl330-periph-burst;
>> 165 clocks = <&cru ACLK_DMAC_BUS>;
>> 166 clock-names = "apb_pclk";
>> 167 };
>> 168 };
>> 169
143 arm-pmu { 170 arm-pmu {
144 compatible = "arm,cortex-a53-p !! 171 compatible = "arm,armv8-pmuv3";
145 interrupts = <GIC_SPI 112 IRQ_ 172 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
146 <GIC_SPI 113 IRQ_ 173 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
147 <GIC_SPI 114 IRQ_ 174 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
148 <GIC_SPI 115 IRQ_ 175 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
149 <GIC_SPI 116 IRQ_ 176 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
150 <GIC_SPI 117 IRQ_ 177 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
151 <GIC_SPI 118 IRQ_ 178 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
152 <GIC_SPI 119 IRQ_ 179 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
153 interrupt-affinity = <&cpu_l0> 180 interrupt-affinity = <&cpu_l0>, <&cpu_l1>, <&cpu_l2>,
154 <&cpu_l3> 181 <&cpu_l3>, <&cpu_b0>, <&cpu_b1>,
155 <&cpu_b2> 182 <&cpu_b2>, <&cpu_b3>;
156 }; 183 };
157 184
158 psci { 185 psci {
159 compatible = "arm,psci-0.2"; 186 compatible = "arm,psci-0.2";
160 method = "smc"; 187 method = "smc";
161 }; 188 };
162 189
163 timer { 190 timer {
164 compatible = "arm,armv8-timer" 191 compatible = "arm,armv8-timer";
165 interrupts = <GIC_PPI 13 192 interrupts = <GIC_PPI 13
166 (GIC_CPU_MASK_SIMPLE(8 193 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
167 <GIC_PPI 14 194 <GIC_PPI 14
168 (GIC_CPU_MASK_SIMPLE(8 195 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
169 <GIC_PPI 11 196 <GIC_PPI 11
170 (GIC_CPU_MASK_SIMPLE(8 197 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
171 <GIC_PPI 10 198 <GIC_PPI 10
172 (GIC_CPU_MASK_SIMPLE(8 199 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
173 }; 200 };
174 201
175 xin24m: oscillator { 202 xin24m: oscillator {
176 compatible = "fixed-clock"; 203 compatible = "fixed-clock";
177 clock-frequency = <24000000>; 204 clock-frequency = <24000000>;
178 clock-output-names = "xin24m"; 205 clock-output-names = "xin24m";
179 #clock-cells = <0>; 206 #clock-cells = <0>;
180 }; 207 };
181 208
182 sdmmc: mmc@ff0c0000 { 209 sdmmc: mmc@ff0c0000 {
183 compatible = "rockchip,rk3368- 210 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
184 reg = <0x0 0xff0c0000 0x0 0x40 211 reg = <0x0 0xff0c0000 0x0 0x4000>;
185 max-frequency = <150000000>; 212 max-frequency = <150000000>;
186 clocks = <&cru HCLK_SDMMC>, <& 213 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
187 <&cru SCLK_SDMMC_DRV> 214 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
188 clock-names = "biu", "ciu", "c 215 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
189 fifo-depth = <0x100>; 216 fifo-depth = <0x100>;
190 interrupts = <GIC_SPI 32 IRQ_T 217 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
191 resets = <&cru SRST_MMC0>; 218 resets = <&cru SRST_MMC0>;
192 reset-names = "reset"; 219 reset-names = "reset";
193 status = "disabled"; 220 status = "disabled";
194 }; 221 };
195 222
196 sdio0: mmc@ff0d0000 { 223 sdio0: mmc@ff0d0000 {
197 compatible = "rockchip,rk3368- 224 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
198 reg = <0x0 0xff0d0000 0x0 0x40 225 reg = <0x0 0xff0d0000 0x0 0x4000>;
199 max-frequency = <150000000>; 226 max-frequency = <150000000>;
200 clocks = <&cru HCLK_SDIO0>, <& 227 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>,
201 <&cru SCLK_SDIO0_DRV> 228 <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
202 clock-names = "biu", "ciu", "c 229 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
203 fifo-depth = <0x100>; 230 fifo-depth = <0x100>;
204 interrupts = <GIC_SPI 33 IRQ_T 231 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
205 resets = <&cru SRST_SDIO0>; 232 resets = <&cru SRST_SDIO0>;
206 reset-names = "reset"; 233 reset-names = "reset";
207 status = "disabled"; 234 status = "disabled";
208 }; 235 };
209 236
210 emmc: mmc@ff0f0000 { 237 emmc: mmc@ff0f0000 {
211 compatible = "rockchip,rk3368- 238 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
212 reg = <0x0 0xff0f0000 0x0 0x40 239 reg = <0x0 0xff0f0000 0x0 0x4000>;
213 max-frequency = <150000000>; 240 max-frequency = <150000000>;
214 clocks = <&cru HCLK_EMMC>, <&c 241 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
215 <&cru SCLK_EMMC_DRV>, 242 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
216 clock-names = "biu", "ciu", "c 243 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
217 fifo-depth = <0x100>; 244 fifo-depth = <0x100>;
218 interrupts = <GIC_SPI 35 IRQ_T 245 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
219 resets = <&cru SRST_EMMC>; 246 resets = <&cru SRST_EMMC>;
220 reset-names = "reset"; 247 reset-names = "reset";
221 status = "disabled"; 248 status = "disabled";
222 }; 249 };
223 250
224 saradc: saradc@ff100000 { 251 saradc: saradc@ff100000 {
225 compatible = "rockchip,saradc" 252 compatible = "rockchip,saradc";
226 reg = <0x0 0xff100000 0x0 0x10 253 reg = <0x0 0xff100000 0x0 0x100>;
227 interrupts = <GIC_SPI 36 IRQ_T 254 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
228 #io-channel-cells = <1>; 255 #io-channel-cells = <1>;
229 clocks = <&cru SCLK_SARADC>, < 256 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
230 clock-names = "saradc", "apb_p 257 clock-names = "saradc", "apb_pclk";
231 resets = <&cru SRST_SARADC>; 258 resets = <&cru SRST_SARADC>;
232 reset-names = "saradc-apb"; 259 reset-names = "saradc-apb";
233 status = "disabled"; 260 status = "disabled";
234 }; 261 };
235 262
236 spi0: spi@ff110000 { 263 spi0: spi@ff110000 {
237 compatible = "rockchip,rk3368- 264 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
238 reg = <0x0 0xff110000 0x0 0x10 265 reg = <0x0 0xff110000 0x0 0x1000>;
239 clocks = <&cru SCLK_SPI0>, <&c 266 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
240 clock-names = "spiclk", "apb_p 267 clock-names = "spiclk", "apb_pclk";
241 interrupts = <GIC_SPI 44 IRQ_T 268 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
242 pinctrl-names = "default"; 269 pinctrl-names = "default";
243 pinctrl-0 = <&spi0_clk &spi0_t 270 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
244 #address-cells = <1>; 271 #address-cells = <1>;
245 #size-cells = <0>; 272 #size-cells = <0>;
246 status = "disabled"; 273 status = "disabled";
247 }; 274 };
248 275
249 spi1: spi@ff120000 { 276 spi1: spi@ff120000 {
250 compatible = "rockchip,rk3368- 277 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
251 reg = <0x0 0xff120000 0x0 0x10 278 reg = <0x0 0xff120000 0x0 0x1000>;
252 clocks = <&cru SCLK_SPI1>, <&c 279 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
253 clock-names = "spiclk", "apb_p 280 clock-names = "spiclk", "apb_pclk";
254 interrupts = <GIC_SPI 45 IRQ_T 281 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
255 pinctrl-names = "default"; 282 pinctrl-names = "default";
256 pinctrl-0 = <&spi1_clk &spi1_t 283 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
257 #address-cells = <1>; 284 #address-cells = <1>;
258 #size-cells = <0>; 285 #size-cells = <0>;
259 status = "disabled"; 286 status = "disabled";
260 }; 287 };
261 288
262 spi2: spi@ff130000 { 289 spi2: spi@ff130000 {
263 compatible = "rockchip,rk3368- 290 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
264 reg = <0x0 0xff130000 0x0 0x10 291 reg = <0x0 0xff130000 0x0 0x1000>;
265 clocks = <&cru SCLK_SPI2>, <&c 292 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
266 clock-names = "spiclk", "apb_p 293 clock-names = "spiclk", "apb_pclk";
267 interrupts = <GIC_SPI 41 IRQ_T 294 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
268 pinctrl-names = "default"; 295 pinctrl-names = "default";
269 pinctrl-0 = <&spi2_clk &spi2_t 296 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
270 #address-cells = <1>; 297 #address-cells = <1>;
271 #size-cells = <0>; 298 #size-cells = <0>;
272 status = "disabled"; 299 status = "disabled";
273 }; 300 };
274 301
275 i2c2: i2c@ff140000 { 302 i2c2: i2c@ff140000 {
276 compatible = "rockchip,rk3368- 303 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
277 reg = <0x0 0xff140000 0x0 0x10 304 reg = <0x0 0xff140000 0x0 0x1000>;
278 interrupts = <GIC_SPI 62 IRQ_T 305 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
279 #address-cells = <1>; 306 #address-cells = <1>;
280 #size-cells = <0>; 307 #size-cells = <0>;
281 clock-names = "i2c"; 308 clock-names = "i2c";
282 clocks = <&cru PCLK_I2C2>; 309 clocks = <&cru PCLK_I2C2>;
283 pinctrl-names = "default"; 310 pinctrl-names = "default";
284 pinctrl-0 = <&i2c2_xfer>; 311 pinctrl-0 = <&i2c2_xfer>;
285 status = "disabled"; 312 status = "disabled";
286 }; 313 };
287 314
288 i2c3: i2c@ff150000 { 315 i2c3: i2c@ff150000 {
289 compatible = "rockchip,rk3368- 316 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
290 reg = <0x0 0xff150000 0x0 0x10 317 reg = <0x0 0xff150000 0x0 0x1000>;
291 interrupts = <GIC_SPI 63 IRQ_T 318 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
292 #address-cells = <1>; 319 #address-cells = <1>;
293 #size-cells = <0>; 320 #size-cells = <0>;
294 clock-names = "i2c"; 321 clock-names = "i2c";
295 clocks = <&cru PCLK_I2C3>; 322 clocks = <&cru PCLK_I2C3>;
296 pinctrl-names = "default"; 323 pinctrl-names = "default";
297 pinctrl-0 = <&i2c3_xfer>; 324 pinctrl-0 = <&i2c3_xfer>;
298 status = "disabled"; 325 status = "disabled";
299 }; 326 };
300 327
301 i2c4: i2c@ff160000 { 328 i2c4: i2c@ff160000 {
302 compatible = "rockchip,rk3368- 329 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
303 reg = <0x0 0xff160000 0x0 0x10 330 reg = <0x0 0xff160000 0x0 0x1000>;
304 interrupts = <GIC_SPI 64 IRQ_T 331 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
305 #address-cells = <1>; 332 #address-cells = <1>;
306 #size-cells = <0>; 333 #size-cells = <0>;
307 clock-names = "i2c"; 334 clock-names = "i2c";
308 clocks = <&cru PCLK_I2C4>; 335 clocks = <&cru PCLK_I2C4>;
309 pinctrl-names = "default"; 336 pinctrl-names = "default";
310 pinctrl-0 = <&i2c4_xfer>; 337 pinctrl-0 = <&i2c4_xfer>;
311 status = "disabled"; 338 status = "disabled";
312 }; 339 };
313 340
314 i2c5: i2c@ff170000 { 341 i2c5: i2c@ff170000 {
315 compatible = "rockchip,rk3368- 342 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
316 reg = <0x0 0xff170000 0x0 0x10 343 reg = <0x0 0xff170000 0x0 0x1000>;
317 interrupts = <GIC_SPI 65 IRQ_T 344 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
318 #address-cells = <1>; 345 #address-cells = <1>;
319 #size-cells = <0>; 346 #size-cells = <0>;
320 clock-names = "i2c"; 347 clock-names = "i2c";
321 clocks = <&cru PCLK_I2C5>; 348 clocks = <&cru PCLK_I2C5>;
322 pinctrl-names = "default"; 349 pinctrl-names = "default";
323 pinctrl-0 = <&i2c5_xfer>; 350 pinctrl-0 = <&i2c5_xfer>;
324 status = "disabled"; 351 status = "disabled";
325 }; 352 };
326 353
327 uart0: serial@ff180000 { 354 uart0: serial@ff180000 {
328 compatible = "rockchip,rk3368- 355 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
329 reg = <0x0 0xff180000 0x0 0x10 356 reg = <0x0 0xff180000 0x0 0x100>;
330 clock-frequency = <24000000>; 357 clock-frequency = <24000000>;
331 clocks = <&cru SCLK_UART0>, <& 358 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
332 clock-names = "baudclk", "apb_ 359 clock-names = "baudclk", "apb_pclk";
333 interrupts = <GIC_SPI 55 IRQ_T 360 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
334 reg-shift = <2>; 361 reg-shift = <2>;
335 reg-io-width = <4>; 362 reg-io-width = <4>;
336 status = "disabled"; 363 status = "disabled";
337 }; 364 };
338 365
339 uart1: serial@ff190000 { 366 uart1: serial@ff190000 {
340 compatible = "rockchip,rk3368- 367 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
341 reg = <0x0 0xff190000 0x0 0x10 368 reg = <0x0 0xff190000 0x0 0x100>;
342 clock-frequency = <24000000>; 369 clock-frequency = <24000000>;
343 clocks = <&cru SCLK_UART1>, <& 370 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
344 clock-names = "baudclk", "apb_ 371 clock-names = "baudclk", "apb_pclk";
345 interrupts = <GIC_SPI 56 IRQ_T 372 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
346 reg-shift = <2>; 373 reg-shift = <2>;
347 reg-io-width = <4>; 374 reg-io-width = <4>;
348 status = "disabled"; 375 status = "disabled";
349 }; 376 };
350 377
351 uart3: serial@ff1b0000 { 378 uart3: serial@ff1b0000 {
352 compatible = "rockchip,rk3368- 379 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
353 reg = <0x0 0xff1b0000 0x0 0x10 380 reg = <0x0 0xff1b0000 0x0 0x100>;
354 clock-frequency = <24000000>; 381 clock-frequency = <24000000>;
355 clocks = <&cru SCLK_UART3>, <& 382 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
356 clock-names = "baudclk", "apb_ 383 clock-names = "baudclk", "apb_pclk";
357 interrupts = <GIC_SPI 58 IRQ_T 384 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
358 reg-shift = <2>; 385 reg-shift = <2>;
359 reg-io-width = <4>; 386 reg-io-width = <4>;
360 status = "disabled"; 387 status = "disabled";
361 }; 388 };
362 389
363 uart4: serial@ff1c0000 { 390 uart4: serial@ff1c0000 {
364 compatible = "rockchip,rk3368- 391 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
365 reg = <0x0 0xff1c0000 0x0 0x10 392 reg = <0x0 0xff1c0000 0x0 0x100>;
366 clock-frequency = <24000000>; 393 clock-frequency = <24000000>;
367 clocks = <&cru SCLK_UART4>, <& 394 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
368 clock-names = "baudclk", "apb_ 395 clock-names = "baudclk", "apb_pclk";
369 interrupts = <GIC_SPI 59 IRQ_T 396 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
370 reg-shift = <2>; 397 reg-shift = <2>;
371 reg-io-width = <4>; 398 reg-io-width = <4>;
372 status = "disabled"; 399 status = "disabled";
373 }; 400 };
374 401
375 dmac_peri: dma-controller@ff250000 { <<
376 compatible = "arm,pl330", "arm <<
377 reg = <0x0 0xff250000 0x0 0x40 <<
378 interrupts = <GIC_SPI 2 IRQ_TY <<
379 <GIC_SPI 3 IRQ_TY <<
380 #dma-cells = <1>; <<
381 arm,pl330-broken-no-flushp; <<
382 arm,pl330-periph-burst; <<
383 clocks = <&cru ACLK_DMAC_PERI> <<
384 clock-names = "apb_pclk"; <<
385 }; <<
386 <<
387 thermal-zones { 402 thermal-zones {
388 cpu_thermal: cpu-thermal { !! 403 cpu {
389 polling-delay-passive 404 polling-delay-passive = <100>; /* milliseconds */
390 polling-delay = <5000> 405 polling-delay = <5000>; /* milliseconds */
391 406
392 thermal-sensors = <&ts 407 thermal-sensors = <&tsadc 0>;
393 408
394 trips { 409 trips {
395 cpu_alert0: cp 410 cpu_alert0: cpu_alert0 {
396 temper 411 temperature = <75000>; /* millicelsius */
397 hyster 412 hysteresis = <2000>; /* millicelsius */
398 type = 413 type = "passive";
399 }; 414 };
400 cpu_alert1: cp 415 cpu_alert1: cpu_alert1 {
401 temper 416 temperature = <80000>; /* millicelsius */
402 hyster 417 hysteresis = <2000>; /* millicelsius */
403 type = 418 type = "passive";
404 }; 419 };
405 cpu_crit: cpu_ 420 cpu_crit: cpu_crit {
406 temper 421 temperature = <95000>; /* millicelsius */
407 hyster 422 hysteresis = <2000>; /* millicelsius */
408 type = 423 type = "critical";
409 }; 424 };
410 }; 425 };
411 426
412 cooling-maps { 427 cooling-maps {
413 map0 { 428 map0 {
414 trip = 429 trip = <&cpu_alert0>;
415 coolin 430 cooling-device =
416 <&cpu_ 431 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
417 <&cpu_ 432 <&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
418 <&cpu_ 433 <&cpu_b2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
419 <&cpu_ 434 <&cpu_b3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
420 }; 435 };
421 map1 { 436 map1 {
422 trip = 437 trip = <&cpu_alert1>;
423 coolin 438 cooling-device =
424 <&cpu_ 439 <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
425 <&cpu_ 440 <&cpu_l1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
426 <&cpu_ 441 <&cpu_l2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
427 <&cpu_ 442 <&cpu_l3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
428 }; 443 };
429 }; 444 };
430 }; 445 };
431 446
432 gpu_thermal: gpu-thermal { !! 447 gpu {
433 polling-delay-passive 448 polling-delay-passive = <100>; /* milliseconds */
434 polling-delay = <5000> 449 polling-delay = <5000>; /* milliseconds */
435 450
436 thermal-sensors = <&ts 451 thermal-sensors = <&tsadc 1>;
437 452
438 trips { 453 trips {
439 gpu_alert0: gp 454 gpu_alert0: gpu_alert0 {
440 temper 455 temperature = <80000>; /* millicelsius */
441 hyster 456 hysteresis = <2000>; /* millicelsius */
442 type = 457 type = "passive";
443 }; 458 };
444 gpu_crit: gpu_ 459 gpu_crit: gpu_crit {
445 temper 460 temperature = <115000>; /* millicelsius */
446 hyster 461 hysteresis = <2000>; /* millicelsius */
447 type = 462 type = "critical";
448 }; 463 };
449 }; 464 };
450 465
451 cooling-maps { 466 cooling-maps {
452 map0 { 467 map0 {
453 trip = 468 trip = <&gpu_alert0>;
454 coolin 469 cooling-device =
455 <&cpu_ 470 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
456 <&cpu_ 471 <&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
457 <&cpu_ 472 <&cpu_b2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
458 <&cpu_ 473 <&cpu_b3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
459 }; 474 };
460 }; 475 };
461 }; 476 };
462 }; 477 };
463 478
464 tsadc: tsadc@ff280000 { 479 tsadc: tsadc@ff280000 {
465 compatible = "rockchip,rk3368- 480 compatible = "rockchip,rk3368-tsadc";
466 reg = <0x0 0xff280000 0x0 0x10 481 reg = <0x0 0xff280000 0x0 0x100>;
467 interrupts = <GIC_SPI 37 IRQ_T 482 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
468 clocks = <&cru SCLK_TSADC>, <& 483 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
469 clock-names = "tsadc", "apb_pc 484 clock-names = "tsadc", "apb_pclk";
470 resets = <&cru SRST_TSADC>; 485 resets = <&cru SRST_TSADC>;
471 reset-names = "tsadc-apb"; 486 reset-names = "tsadc-apb";
472 pinctrl-names = "init", "defau 487 pinctrl-names = "init", "default", "sleep";
473 pinctrl-0 = <&otp_pin>; 488 pinctrl-0 = <&otp_pin>;
474 pinctrl-1 = <&otp_out>; 489 pinctrl-1 = <&otp_out>;
475 pinctrl-2 = <&otp_pin>; 490 pinctrl-2 = <&otp_pin>;
476 #thermal-sensor-cells = <1>; 491 #thermal-sensor-cells = <1>;
477 rockchip,hw-tshut-temp = <9500 492 rockchip,hw-tshut-temp = <95000>;
478 status = "disabled"; 493 status = "disabled";
479 }; 494 };
480 495
481 gmac: ethernet@ff290000 { 496 gmac: ethernet@ff290000 {
482 compatible = "rockchip,rk3368- 497 compatible = "rockchip,rk3368-gmac";
483 reg = <0x0 0xff290000 0x0 0x10 498 reg = <0x0 0xff290000 0x0 0x10000>;
484 interrupts = <GIC_SPI 27 IRQ_T 499 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
485 interrupt-names = "macirq"; 500 interrupt-names = "macirq";
486 rockchip,grf = <&grf>; 501 rockchip,grf = <&grf>;
487 clocks = <&cru SCLK_MAC>, 502 clocks = <&cru SCLK_MAC>,
488 <&cru SCLK_MAC_RX>, <& 503 <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>,
489 <&cru SCLK_MACREF>, <& 504 <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>,
490 <&cru ACLK_GMAC>, <&cr 505 <&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
491 clock-names = "stmmaceth", 506 clock-names = "stmmaceth",
492 "mac_clk_rx", "mac_clk 507 "mac_clk_rx", "mac_clk_tx",
493 "clk_mac_ref", "clk_ma 508 "clk_mac_ref", "clk_mac_refout",
494 "aclk_mac", "pclk_mac" 509 "aclk_mac", "pclk_mac";
495 status = "disabled"; 510 status = "disabled";
496 }; 511 };
497 512
498 usb_host0_ehci: usb@ff500000 { 513 usb_host0_ehci: usb@ff500000 {
499 compatible = "generic-ehci"; 514 compatible = "generic-ehci";
500 reg = <0x0 0xff500000 0x0 0x10 515 reg = <0x0 0xff500000 0x0 0x100>;
501 interrupts = <GIC_SPI 24 IRQ_T 516 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
502 clocks = <&cru HCLK_HOST0>; 517 clocks = <&cru HCLK_HOST0>;
503 status = "disabled"; 518 status = "disabled";
504 }; 519 };
505 520
506 usb_otg: usb@ff580000 { 521 usb_otg: usb@ff580000 {
507 compatible = "rockchip,rk3368- 522 compatible = "rockchip,rk3368-usb", "rockchip,rk3066-usb",
508 "snps,dwc2"; 523 "snps,dwc2";
509 reg = <0x0 0xff580000 0x0 0x40 524 reg = <0x0 0xff580000 0x0 0x40000>;
510 interrupts = <GIC_SPI 23 IRQ_T 525 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
511 clocks = <&cru HCLK_OTG0>; 526 clocks = <&cru HCLK_OTG0>;
512 clock-names = "otg"; 527 clock-names = "otg";
513 dr_mode = "otg"; 528 dr_mode = "otg";
514 g-np-tx-fifo-size = <16>; 529 g-np-tx-fifo-size = <16>;
515 g-rx-fifo-size = <275>; 530 g-rx-fifo-size = <275>;
516 g-tx-fifo-size = <256 128 128 531 g-tx-fifo-size = <256 128 128 64 64 32>;
517 status = "disabled"; 532 status = "disabled";
518 }; 533 };
519 534
520 dmac_bus: dma-controller@ff600000 { <<
521 compatible = "arm,pl330", "arm <<
522 reg = <0x0 0xff600000 0x0 0x40 <<
523 interrupts = <GIC_SPI 0 IRQ_TY <<
524 <GIC_SPI 1 IRQ_TY <<
525 #dma-cells = <1>; <<
526 arm,pl330-broken-no-flushp; <<
527 arm,pl330-periph-burst; <<
528 clocks = <&cru ACLK_DMAC_BUS>; <<
529 clock-names = "apb_pclk"; <<
530 }; <<
531 <<
532 i2c0: i2c@ff650000 { 535 i2c0: i2c@ff650000 {
533 compatible = "rockchip,rk3368- 536 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
534 reg = <0x0 0xff650000 0x0 0x10 537 reg = <0x0 0xff650000 0x0 0x1000>;
535 clocks = <&cru PCLK_I2C0>; 538 clocks = <&cru PCLK_I2C0>;
536 clock-names = "i2c"; 539 clock-names = "i2c";
537 interrupts = <GIC_SPI 60 IRQ_T 540 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
538 pinctrl-names = "default"; 541 pinctrl-names = "default";
539 pinctrl-0 = <&i2c0_xfer>; 542 pinctrl-0 = <&i2c0_xfer>;
540 #address-cells = <1>; 543 #address-cells = <1>;
541 #size-cells = <0>; 544 #size-cells = <0>;
542 status = "disabled"; 545 status = "disabled";
543 }; 546 };
544 547
545 i2c1: i2c@ff660000 { 548 i2c1: i2c@ff660000 {
546 compatible = "rockchip,rk3368- 549 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
547 reg = <0x0 0xff660000 0x0 0x10 550 reg = <0x0 0xff660000 0x0 0x1000>;
548 interrupts = <GIC_SPI 61 IRQ_T 551 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
549 #address-cells = <1>; 552 #address-cells = <1>;
550 #size-cells = <0>; 553 #size-cells = <0>;
551 clock-names = "i2c"; 554 clock-names = "i2c";
552 clocks = <&cru PCLK_I2C1>; 555 clocks = <&cru PCLK_I2C1>;
553 pinctrl-names = "default"; 556 pinctrl-names = "default";
554 pinctrl-0 = <&i2c1_xfer>; 557 pinctrl-0 = <&i2c1_xfer>;
555 status = "disabled"; 558 status = "disabled";
556 }; 559 };
557 560
558 pwm0: pwm@ff680000 { 561 pwm0: pwm@ff680000 {
559 compatible = "rockchip,rk3368- 562 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
560 reg = <0x0 0xff680000 0x0 0x10 563 reg = <0x0 0xff680000 0x0 0x10>;
561 #pwm-cells = <3>; 564 #pwm-cells = <3>;
562 pinctrl-names = "default"; 565 pinctrl-names = "default";
563 pinctrl-0 = <&pwm0_pin>; 566 pinctrl-0 = <&pwm0_pin>;
564 clocks = <&cru PCLK_PWM1>; 567 clocks = <&cru PCLK_PWM1>;
>> 568 clock-names = "pwm";
565 status = "disabled"; 569 status = "disabled";
566 }; 570 };
567 571
568 pwm1: pwm@ff680010 { 572 pwm1: pwm@ff680010 {
569 compatible = "rockchip,rk3368- 573 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
570 reg = <0x0 0xff680010 0x0 0x10 574 reg = <0x0 0xff680010 0x0 0x10>;
571 #pwm-cells = <3>; 575 #pwm-cells = <3>;
572 pinctrl-names = "default"; 576 pinctrl-names = "default";
573 pinctrl-0 = <&pwm1_pin>; 577 pinctrl-0 = <&pwm1_pin>;
574 clocks = <&cru PCLK_PWM1>; 578 clocks = <&cru PCLK_PWM1>;
>> 579 clock-names = "pwm";
575 status = "disabled"; 580 status = "disabled";
576 }; 581 };
577 582
578 pwm2: pwm@ff680020 { 583 pwm2: pwm@ff680020 {
579 compatible = "rockchip,rk3368- 584 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
580 reg = <0x0 0xff680020 0x0 0x10 585 reg = <0x0 0xff680020 0x0 0x10>;
581 #pwm-cells = <3>; 586 #pwm-cells = <3>;
582 clocks = <&cru PCLK_PWM1>; 587 clocks = <&cru PCLK_PWM1>;
>> 588 clock-names = "pwm";
583 status = "disabled"; 589 status = "disabled";
584 }; 590 };
585 591
586 pwm3: pwm@ff680030 { 592 pwm3: pwm@ff680030 {
587 compatible = "rockchip,rk3368- 593 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
588 reg = <0x0 0xff680030 0x0 0x10 594 reg = <0x0 0xff680030 0x0 0x10>;
589 #pwm-cells = <3>; 595 #pwm-cells = <3>;
590 pinctrl-names = "default"; 596 pinctrl-names = "default";
591 pinctrl-0 = <&pwm3_pin>; 597 pinctrl-0 = <&pwm3_pin>;
592 clocks = <&cru PCLK_PWM1>; 598 clocks = <&cru PCLK_PWM1>;
>> 599 clock-names = "pwm";
593 status = "disabled"; 600 status = "disabled";
594 }; 601 };
595 602
596 uart2: serial@ff690000 { 603 uart2: serial@ff690000 {
597 compatible = "rockchip,rk3368- 604 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
598 reg = <0x0 0xff690000 0x0 0x10 605 reg = <0x0 0xff690000 0x0 0x100>;
599 clocks = <&cru SCLK_UART2>, <& 606 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
600 clock-names = "baudclk", "apb_ 607 clock-names = "baudclk", "apb_pclk";
601 interrupts = <GIC_SPI 57 IRQ_T 608 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
602 pinctrl-names = "default"; 609 pinctrl-names = "default";
603 pinctrl-0 = <&uart2_xfer>; 610 pinctrl-0 = <&uart2_xfer>;
604 reg-shift = <2>; 611 reg-shift = <2>;
605 reg-io-width = <4>; 612 reg-io-width = <4>;
606 status = "disabled"; 613 status = "disabled";
607 }; 614 };
608 615
609 mbox: mbox@ff6b0000 { 616 mbox: mbox@ff6b0000 {
610 compatible = "rockchip,rk3368- 617 compatible = "rockchip,rk3368-mailbox";
611 reg = <0x0 0xff6b0000 0x0 0x10 618 reg = <0x0 0xff6b0000 0x0 0x1000>;
612 interrupts = <GIC_SPI 146 IRQ_ 619 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
613 <GIC_SPI 147 IRQ_ 620 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
614 <GIC_SPI 148 IRQ_ 621 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
615 <GIC_SPI 149 IRQ_ 622 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
616 clocks = <&cru PCLK_MAILBOX>; 623 clocks = <&cru PCLK_MAILBOX>;
617 clock-names = "pclk_mailbox"; 624 clock-names = "pclk_mailbox";
618 #mbox-cells = <1>; 625 #mbox-cells = <1>;
619 status = "disabled"; 626 status = "disabled";
620 }; 627 };
621 628
622 pmu: power-management@ff730000 { <<
623 compatible = "rockchip,rk3368- <<
624 reg = <0x0 0xff730000 0x0 0x10 <<
625 <<
626 power: power-controller { <<
627 compatible = "rockchip <<
628 #power-domain-cells = <<
629 #address-cells = <1>; <<
630 #size-cells = <0>; <<
631 <<
632 /* <<
633 * Note: Although SCLK <<
634 * of device without i <<
635 * synchronous reset. <<
636 * <<
637 * The clocks on the w <<
638 * ACLK_IEP/ACLK_VIP/A <<
639 * ACLK_ISP/ACLK_VOP1 <<
640 * ACLK_RGA is on ACLK <<
641 * The others (HCLK_*, <<
642 * <<
643 * Which clock are dev <<
644 * clocks <<
645 * *_IEP <<
646 * *_ISP <<
647 * *_VIP <<
648 * *_VOP* <<
649 * *_RGA <<
650 * *_EDP* <<
651 * *_DPHY* <<
652 * *_HDMI <<
653 * *_MIPI_* <<
654 */ <<
655 power-domain@RK3368_PD <<
656 reg = <RK3368_ <<
657 clocks = <&cru <<
658 <&cru <<
659 <&cru <<
660 <&cru <<
661 <&cru <<
662 <&cru <<
663 <&cru <<
664 <&cru <<
665 <&cru <<
666 <&cru <<
667 <&cru <<
668 <&cru <<
669 <&cru <<
670 <&cru <<
671 <&cru <<
672 <&cru <<
673 <&cru <<
674 <&cru <<
675 <&cru <<
676 <&cru <<
677 <&cru <<
678 <&cru <<
679 <&cru <<
680 <&cru <<
681 <&cru <<
682 <&cru <<
683 <&cru <<
684 <&cru <<
685 <&cru <<
686 <&cru <<
687 pm_qos = <&qos <<
688 <&qos <<
689 <&qos <<
690 <&qos <<
691 <&qos <<
692 <&qos <<
693 <&qos <<
694 <&qos <<
695 <&qos <<
696 #power-domain- <<
697 }; <<
698 <<
699 /* <<
700 * Note: ACLK_VCODEC/H <<
701 * (video endecoder & <<
702 * ACLK_VCODEC_NIU and <<
703 */ <<
704 power-domain@RK3368_PD <<
705 reg = <RK3368_ <<
706 clocks = <&cru <<
707 <&cru <<
708 <&cru <<
709 <&cru <<
710 pm_qos = <&qos <<
711 <&qos <<
712 <&qos <<
713 #power-domain- <<
714 }; <<
715 <<
716 /* <<
717 * Note: ACLK_GPU is t <<
718 * and on the ACLK_GPU <<
719 */ <<
720 power-domain@RK3368_PD <<
721 reg = <RK3368_ <<
722 clocks = <&cru <<
723 <&cru <<
724 <&cru <<
725 pm_qos = <&qos <<
726 #power-domain- <<
727 }; <<
728 }; <<
729 }; <<
730 <<
731 pmugrf: syscon@ff738000 { 629 pmugrf: syscon@ff738000 {
732 compatible = "rockchip,rk3368- 630 compatible = "rockchip,rk3368-pmugrf", "syscon", "simple-mfd";
733 reg = <0x0 0xff738000 0x0 0x10 631 reg = <0x0 0xff738000 0x0 0x1000>;
734 632
735 pmu_io_domains: io-domains { 633 pmu_io_domains: io-domains {
736 compatible = "rockchip 634 compatible = "rockchip,rk3368-pmu-io-voltage-domain";
737 status = "disabled"; 635 status = "disabled";
738 }; 636 };
739 637
740 reboot-mode { 638 reboot-mode {
741 compatible = "syscon-r 639 compatible = "syscon-reboot-mode";
742 offset = <0x200>; 640 offset = <0x200>;
743 mode-normal = <BOOT_NO 641 mode-normal = <BOOT_NORMAL>;
744 mode-recovery = <BOOT_ 642 mode-recovery = <BOOT_RECOVERY>;
745 mode-bootloader = <BOO 643 mode-bootloader = <BOOT_FASTBOOT>;
746 mode-loader = <BOOT_BL 644 mode-loader = <BOOT_BL_DOWNLOAD>;
747 }; 645 };
748 }; 646 };
749 647
750 cru: clock-controller@ff760000 { 648 cru: clock-controller@ff760000 {
751 compatible = "rockchip,rk3368- 649 compatible = "rockchip,rk3368-cru";
752 reg = <0x0 0xff760000 0x0 0x10 650 reg = <0x0 0xff760000 0x0 0x1000>;
753 clocks = <&xin24m>; <<
754 clock-names = "xin24m"; <<
755 rockchip,grf = <&grf>; 651 rockchip,grf = <&grf>;
756 #clock-cells = <1>; 652 #clock-cells = <1>;
757 #reset-cells = <1>; 653 #reset-cells = <1>;
758 }; 654 };
759 655
760 grf: syscon@ff770000 { 656 grf: syscon@ff770000 {
761 compatible = "rockchip,rk3368- 657 compatible = "rockchip,rk3368-grf", "syscon", "simple-mfd";
762 reg = <0x0 0xff770000 0x0 0x10 658 reg = <0x0 0xff770000 0x0 0x1000>;
763 659
764 io_domains: io-domains { 660 io_domains: io-domains {
765 compatible = "rockchip 661 compatible = "rockchip,rk3368-io-voltage-domain";
766 status = "disabled"; 662 status = "disabled";
767 }; 663 };
768 }; 664 };
769 665
770 wdt: watchdog@ff800000 { 666 wdt: watchdog@ff800000 {
771 compatible = "rockchip,rk3368- 667 compatible = "rockchip,rk3368-wdt", "snps,dw-wdt";
772 reg = <0x0 0xff800000 0x0 0x10 668 reg = <0x0 0xff800000 0x0 0x100>;
773 clocks = <&cru PCLK_WDT>; 669 clocks = <&cru PCLK_WDT>;
774 interrupts = <GIC_SPI 79 IRQ_T 670 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
775 status = "disabled"; 671 status = "disabled";
776 }; 672 };
777 673
778 timer0: timer@ff810000 { !! 674 timer@ff810000 {
779 compatible = "rockchip,rk3368- 675 compatible = "rockchip,rk3368-timer", "rockchip,rk3288-timer";
780 reg = <0x0 0xff810000 0x0 0x20 676 reg = <0x0 0xff810000 0x0 0x20>;
781 interrupts = <GIC_SPI 66 IRQ_T 677 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
782 clocks = <&cru PCLK_TIMER0>, < <<
783 clock-names = "pclk", "timer"; <<
784 }; 678 };
785 679
786 spdif: spdif@ff880000 { 680 spdif: spdif@ff880000 {
787 compatible = "rockchip,rk3368- 681 compatible = "rockchip,rk3368-spdif";
788 reg = <0x0 0xff880000 0x0 0x10 682 reg = <0x0 0xff880000 0x0 0x1000>;
789 interrupts = <GIC_SPI 54 IRQ_T 683 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
790 clocks = <&cru SCLK_SPDIF_8CH> 684 clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>;
791 clock-names = "mclk", "hclk"; 685 clock-names = "mclk", "hclk";
792 dmas = <&dmac_bus 3>; 686 dmas = <&dmac_bus 3>;
793 dma-names = "tx"; 687 dma-names = "tx";
794 pinctrl-names = "default"; 688 pinctrl-names = "default";
795 pinctrl-0 = <&spdif_tx>; 689 pinctrl-0 = <&spdif_tx>;
796 #sound-dai-cells = <0>; <<
797 status = "disabled"; 690 status = "disabled";
798 }; 691 };
799 692
800 i2s_2ch: i2s-2ch@ff890000 { 693 i2s_2ch: i2s-2ch@ff890000 {
801 compatible = "rockchip,rk3368- 694 compatible = "rockchip,rk3368-i2s", "rockchip,rk3066-i2s";
802 reg = <0x0 0xff890000 0x0 0x10 695 reg = <0x0 0xff890000 0x0 0x1000>;
803 interrupts = <GIC_SPI 40 IRQ_T 696 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
804 clock-names = "i2s_clk", "i2s_ 697 clock-names = "i2s_clk", "i2s_hclk";
805 clocks = <&cru SCLK_I2S_2CH>, 698 clocks = <&cru SCLK_I2S_2CH>, <&cru HCLK_I2S_2CH>;
806 dmas = <&dmac_bus 6>, <&dmac_b 699 dmas = <&dmac_bus 6>, <&dmac_bus 7>;
807 dma-names = "tx", "rx"; 700 dma-names = "tx", "rx";
808 #sound-dai-cells = <0>; <<
809 status = "disabled"; 701 status = "disabled";
810 }; 702 };
811 703
812 i2s_8ch: i2s-8ch@ff898000 { 704 i2s_8ch: i2s-8ch@ff898000 {
813 compatible = "rockchip,rk3368- 705 compatible = "rockchip,rk3368-i2s", "rockchip,rk3066-i2s";
814 reg = <0x0 0xff898000 0x0 0x10 706 reg = <0x0 0xff898000 0x0 0x1000>;
815 interrupts = <GIC_SPI 53 IRQ_T 707 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
816 clock-names = "i2s_clk", "i2s_ 708 clock-names = "i2s_clk", "i2s_hclk";
817 clocks = <&cru SCLK_I2S_8CH>, 709 clocks = <&cru SCLK_I2S_8CH>, <&cru HCLK_I2S_8CH>;
818 dmas = <&dmac_bus 0>, <&dmac_b 710 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
819 dma-names = "tx", "rx"; 711 dma-names = "tx", "rx";
820 pinctrl-names = "default"; 712 pinctrl-names = "default";
821 pinctrl-0 = <&i2s_8ch_bus>; 713 pinctrl-0 = <&i2s_8ch_bus>;
822 #sound-dai-cells = <0>; <<
823 status = "disabled"; 714 status = "disabled";
824 }; 715 };
825 716
826 iep_mmu: iommu@ff900800 { 717 iep_mmu: iommu@ff900800 {
827 compatible = "rockchip,iommu"; 718 compatible = "rockchip,iommu";
828 reg = <0x0 0xff900800 0x0 0x10 719 reg = <0x0 0xff900800 0x0 0x100>;
829 interrupts = <GIC_SPI 17 IRQ_T 720 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
>> 721 interrupt-names = "iep_mmu";
830 clocks = <&cru ACLK_IEP>, <&cr 722 clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
831 clock-names = "aclk", "iface"; 723 clock-names = "aclk", "iface";
832 power-domains = <&power RK3368 <<
833 #iommu-cells = <0>; 724 #iommu-cells = <0>;
834 status = "disabled"; 725 status = "disabled";
835 }; 726 };
836 727
837 isp_mmu: iommu@ff914000 { 728 isp_mmu: iommu@ff914000 {
838 compatible = "rockchip,iommu"; 729 compatible = "rockchip,iommu";
839 reg = <0x0 0xff914000 0x0 0x10 730 reg = <0x0 0xff914000 0x0 0x100>,
840 <0x0 0xff915000 0x0 0x10 731 <0x0 0xff915000 0x0 0x100>;
841 interrupts = <GIC_SPI 14 IRQ_T 732 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
>> 733 interrupt-names = "isp_mmu";
842 clocks = <&cru ACLK_ISP>, <&cr 734 clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>;
843 clock-names = "aclk", "iface"; 735 clock-names = "aclk", "iface";
844 #iommu-cells = <0>; 736 #iommu-cells = <0>;
845 power-domains = <&power RK3368 <<
846 rockchip,disable-mmu-reset; 737 rockchip,disable-mmu-reset;
847 status = "disabled"; 738 status = "disabled";
848 }; 739 };
849 740
850 vop_mmu: iommu@ff930300 { 741 vop_mmu: iommu@ff930300 {
851 compatible = "rockchip,iommu"; 742 compatible = "rockchip,iommu";
852 reg = <0x0 0xff930300 0x0 0x10 743 reg = <0x0 0xff930300 0x0 0x100>;
853 interrupts = <GIC_SPI 15 IRQ_T 744 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
>> 745 interrupt-names = "vop_mmu";
854 clocks = <&cru ACLK_VOP>, <&cr 746 clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
855 clock-names = "aclk", "iface"; 747 clock-names = "aclk", "iface";
856 power-domains = <&power RK3368 <<
857 #iommu-cells = <0>; 748 #iommu-cells = <0>;
858 status = "disabled"; 749 status = "disabled";
859 }; 750 };
860 751
861 hevc_mmu: iommu@ff9a0440 { 752 hevc_mmu: iommu@ff9a0440 {
862 compatible = "rockchip,iommu"; 753 compatible = "rockchip,iommu";
863 reg = <0x0 0xff9a0440 0x0 0x40 754 reg = <0x0 0xff9a0440 0x0 0x40>,
864 <0x0 0xff9a0480 0x0 0x40 755 <0x0 0xff9a0480 0x0 0x40>;
865 interrupts = <GIC_SPI 12 IRQ_T 756 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
>> 757 interrupt-names = "hevc_mmu";
866 clocks = <&cru ACLK_VIDEO>, <& 758 clocks = <&cru ACLK_VIDEO>, <&cru HCLK_VIDEO>;
867 clock-names = "aclk", "iface"; 759 clock-names = "aclk", "iface";
868 #iommu-cells = <0>; 760 #iommu-cells = <0>;
869 status = "disabled"; 761 status = "disabled";
870 }; 762 };
871 763
872 vpu_mmu: iommu@ff9a0800 { 764 vpu_mmu: iommu@ff9a0800 {
873 compatible = "rockchip,iommu"; 765 compatible = "rockchip,iommu";
874 reg = <0x0 0xff9a0800 0x0 0x10 766 reg = <0x0 0xff9a0800 0x0 0x100>;
875 interrupts = <GIC_SPI 9 IRQ_TY 767 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
876 <GIC_SPI 10 IRQ_T 768 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
>> 769 interrupt-names = "vepu_mmu", "vdpu_mmu";
877 clocks = <&cru ACLK_VIDEO>, <& 770 clocks = <&cru ACLK_VIDEO>, <&cru HCLK_VIDEO>;
878 clock-names = "aclk", "iface"; 771 clock-names = "aclk", "iface";
879 #iommu-cells = <0>; 772 #iommu-cells = <0>;
880 status = "disabled"; 773 status = "disabled";
881 }; 774 };
882 775
883 qos_iep: qos@ffad0000 { <<
884 compatible = "rockchip,rk3368- <<
885 reg = <0x0 0xffad0000 0x0 0x20 <<
886 }; <<
887 <<
888 qos_isp_r0: qos@ffad0080 { <<
889 compatible = "rockchip,rk3368- <<
890 reg = <0x0 0xffad0080 0x0 0x20 <<
891 }; <<
892 <<
893 qos_isp_r1: qos@ffad0100 { <<
894 compatible = "rockchip,rk3368- <<
895 reg = <0x0 0xffad0100 0x0 0x20 <<
896 }; <<
897 <<
898 qos_isp_w0: qos@ffad0180 { <<
899 compatible = "rockchip,rk3368- <<
900 reg = <0x0 0xffad0180 0x0 0x20 <<
901 }; <<
902 <<
903 qos_isp_w1: qos@ffad0200 { <<
904 compatible = "rockchip,rk3368- <<
905 reg = <0x0 0xffad0200 0x0 0x20 <<
906 }; <<
907 <<
908 qos_vip: qos@ffad0280 { <<
909 compatible = "rockchip,rk3368- <<
910 reg = <0x0 0xffad0280 0x0 0x20 <<
911 }; <<
912 <<
913 qos_vop: qos@ffad0300 { <<
914 compatible = "rockchip,rk3368- <<
915 reg = <0x0 0xffad0300 0x0 0x20 <<
916 }; <<
917 <<
918 qos_rga_r: qos@ffad0380 { <<
919 compatible = "rockchip,rk3368- <<
920 reg = <0x0 0xffad0380 0x0 0x20 <<
921 }; <<
922 <<
923 qos_rga_w: qos@ffad0400 { <<
924 compatible = "rockchip,rk3368- <<
925 reg = <0x0 0xffad0400 0x0 0x20 <<
926 }; <<
927 <<
928 qos_hevc_r: qos@ffae0000 { <<
929 compatible = "rockchip,rk3368- <<
930 reg = <0x0 0xffae0000 0x0 0x20 <<
931 }; <<
932 <<
933 qos_vpu_r: qos@ffae0100 { <<
934 compatible = "rockchip,rk3368- <<
935 reg = <0x0 0xffae0100 0x0 0x20 <<
936 }; <<
937 <<
938 qos_vpu_w: qos@ffae0180 { <<
939 compatible = "rockchip,rk3368- <<
940 reg = <0x0 0xffae0180 0x0 0x20 <<
941 }; <<
942 <<
943 qos_gpu: qos@ffaf0000 { <<
944 compatible = "rockchip,rk3368- <<
945 reg = <0x0 0xffaf0000 0x0 0x20 <<
946 }; <<
947 <<
948 efuse256: efuse@ffb00000 { 776 efuse256: efuse@ffb00000 {
949 compatible = "rockchip,rk3368- 777 compatible = "rockchip,rk3368-efuse";
950 reg = <0x0 0xffb00000 0x0 0x20 778 reg = <0x0 0xffb00000 0x0 0x20>;
951 #address-cells = <1>; 779 #address-cells = <1>;
952 #size-cells = <1>; 780 #size-cells = <1>;
953 clocks = <&cru PCLK_EFUSE256>; 781 clocks = <&cru PCLK_EFUSE256>;
954 clock-names = "pclk_efuse"; 782 clock-names = "pclk_efuse";
955 783
956 cpu_leakage: cpu-leakage@17 { 784 cpu_leakage: cpu-leakage@17 {
957 reg = <0x17 0x1>; 785 reg = <0x17 0x1>;
958 }; 786 };
959 temp_adjust: temp-adjust@1f { 787 temp_adjust: temp-adjust@1f {
960 reg = <0x1f 0x1>; 788 reg = <0x1f 0x1>;
961 }; 789 };
962 }; 790 };
963 791
964 gic: interrupt-controller@ffb71000 { 792 gic: interrupt-controller@ffb71000 {
965 compatible = "arm,gic-400"; 793 compatible = "arm,gic-400";
966 interrupt-controller; 794 interrupt-controller;
967 #interrupt-cells = <3>; 795 #interrupt-cells = <3>;
968 #address-cells = <0>; 796 #address-cells = <0>;
969 797
970 reg = <0x0 0xffb71000 0x0 0x10 798 reg = <0x0 0xffb71000 0x0 0x1000>,
971 <0x0 0xffb72000 0x0 0x20 799 <0x0 0xffb72000 0x0 0x2000>,
972 <0x0 0xffb74000 0x0 0x20 800 <0x0 0xffb74000 0x0 0x2000>,
973 <0x0 0xffb76000 0x0 0x20 801 <0x0 0xffb76000 0x0 0x2000>;
974 interrupts = <GIC_PPI 9 802 interrupts = <GIC_PPI 9
975 (GIC_CPU_MASK_SIMPLE(8) 803 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
976 }; 804 };
977 805
978 pinctrl: pinctrl { 806 pinctrl: pinctrl {
979 compatible = "rockchip,rk3368- 807 compatible = "rockchip,rk3368-pinctrl";
980 rockchip,grf = <&grf>; 808 rockchip,grf = <&grf>;
981 rockchip,pmu = <&pmugrf>; 809 rockchip,pmu = <&pmugrf>;
982 #address-cells = <0x2>; 810 #address-cells = <0x2>;
983 #size-cells = <0x2>; 811 #size-cells = <0x2>;
984 ranges; 812 ranges;
985 813
986 gpio0: gpio@ff750000 { !! 814 gpio0: gpio0@ff750000 {
987 compatible = "rockchip 815 compatible = "rockchip,gpio-bank";
988 reg = <0x0 0xff750000 816 reg = <0x0 0xff750000 0x0 0x100>;
989 clocks = <&cru PCLK_GP 817 clocks = <&cru PCLK_GPIO0>;
990 interrupts = <GIC_SPI 818 interrupts = <GIC_SPI 0x51 IRQ_TYPE_LEVEL_HIGH>;
991 819
992 gpio-controller; 820 gpio-controller;
993 #gpio-cells = <0x2>; 821 #gpio-cells = <0x2>;
994 822
995 interrupt-controller; 823 interrupt-controller;
996 #interrupt-cells = <0x 824 #interrupt-cells = <0x2>;
997 }; 825 };
998 826
999 gpio1: gpio@ff780000 { !! 827 gpio1: gpio1@ff780000 {
1000 compatible = "rockchi 828 compatible = "rockchip,gpio-bank";
1001 reg = <0x0 0xff780000 829 reg = <0x0 0xff780000 0x0 0x100>;
1002 clocks = <&cru PCLK_G 830 clocks = <&cru PCLK_GPIO1>;
1003 interrupts = <GIC_SPI 831 interrupts = <GIC_SPI 0x52 IRQ_TYPE_LEVEL_HIGH>;
1004 832
1005 gpio-controller; 833 gpio-controller;
1006 #gpio-cells = <0x2>; 834 #gpio-cells = <0x2>;
1007 835
1008 interrupt-controller; 836 interrupt-controller;
1009 #interrupt-cells = <0 837 #interrupt-cells = <0x2>;
1010 }; 838 };
1011 839
1012 gpio2: gpio@ff790000 { !! 840 gpio2: gpio2@ff790000 {
1013 compatible = "rockchi 841 compatible = "rockchip,gpio-bank";
1014 reg = <0x0 0xff790000 842 reg = <0x0 0xff790000 0x0 0x100>;
1015 clocks = <&cru PCLK_G 843 clocks = <&cru PCLK_GPIO2>;
1016 interrupts = <GIC_SPI 844 interrupts = <GIC_SPI 0x53 IRQ_TYPE_LEVEL_HIGH>;
1017 845
1018 gpio-controller; 846 gpio-controller;
1019 #gpio-cells = <0x2>; 847 #gpio-cells = <0x2>;
1020 848
1021 interrupt-controller; 849 interrupt-controller;
1022 #interrupt-cells = <0 850 #interrupt-cells = <0x2>;
1023 }; 851 };
1024 852
1025 gpio3: gpio@ff7a0000 { !! 853 gpio3: gpio3@ff7a0000 {
1026 compatible = "rockchi 854 compatible = "rockchip,gpio-bank";
1027 reg = <0x0 0xff7a0000 855 reg = <0x0 0xff7a0000 0x0 0x100>;
1028 clocks = <&cru PCLK_G 856 clocks = <&cru PCLK_GPIO3>;
1029 interrupts = <GIC_SPI 857 interrupts = <GIC_SPI 0x54 IRQ_TYPE_LEVEL_HIGH>;
1030 858
1031 gpio-controller; 859 gpio-controller;
1032 #gpio-cells = <0x2>; 860 #gpio-cells = <0x2>;
1033 861
1034 interrupt-controller; 862 interrupt-controller;
1035 #interrupt-cells = <0 863 #interrupt-cells = <0x2>;
1036 }; 864 };
1037 865
1038 pcfg_pull_up: pcfg-pull-up { 866 pcfg_pull_up: pcfg-pull-up {
1039 bias-pull-up; 867 bias-pull-up;
1040 }; 868 };
1041 869
1042 pcfg_pull_down: pcfg-pull-dow 870 pcfg_pull_down: pcfg-pull-down {
1043 bias-pull-down; 871 bias-pull-down;
1044 }; 872 };
1045 873
1046 pcfg_pull_none: pcfg-pull-non 874 pcfg_pull_none: pcfg-pull-none {
1047 bias-disable; 875 bias-disable;
1048 }; 876 };
1049 877
1050 pcfg_pull_none_12ma: pcfg-pul 878 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1051 bias-disable; 879 bias-disable;
1052 drive-strength = <12> 880 drive-strength = <12>;
1053 }; 881 };
1054 882
1055 emmc { 883 emmc {
1056 emmc_clk: emmc-clk { 884 emmc_clk: emmc-clk {
1057 rockchip,pins 885 rockchip,pins = <2 RK_PA4 2 &pcfg_pull_none>;
1058 }; 886 };
1059 887
1060 emmc_cmd: emmc-cmd { 888 emmc_cmd: emmc-cmd {
1061 rockchip,pins 889 rockchip,pins = <1 RK_PD2 2 &pcfg_pull_up>;
1062 }; 890 };
1063 891
1064 emmc_pwr: emmc-pwr { 892 emmc_pwr: emmc-pwr {
1065 rockchip,pins 893 rockchip,pins = <1 RK_PD3 2 &pcfg_pull_up>;
1066 }; 894 };
1067 895
1068 emmc_bus1: emmc-bus1 896 emmc_bus1: emmc-bus1 {
1069 rockchip,pins 897 rockchip,pins = <1 RK_PC2 2 &pcfg_pull_up>;
1070 }; 898 };
1071 899
1072 emmc_bus4: emmc-bus4 900 emmc_bus4: emmc-bus4 {
1073 rockchip,pins 901 rockchip,pins = <1 RK_PC2 2 &pcfg_pull_up>,
1074 902 <1 RK_PC3 2 &pcfg_pull_up>,
1075 903 <1 RK_PC4 2 &pcfg_pull_up>,
1076 904 <1 RK_PC5 2 &pcfg_pull_up>;
1077 }; 905 };
1078 906
1079 emmc_bus8: emmc-bus8 907 emmc_bus8: emmc-bus8 {
1080 rockchip,pins 908 rockchip,pins = <1 RK_PC2 2 &pcfg_pull_up>,
1081 909 <1 RK_PC3 2 &pcfg_pull_up>,
1082 910 <1 RK_PC4 2 &pcfg_pull_up>,
1083 911 <1 RK_PC5 2 &pcfg_pull_up>,
1084 912 <1 RK_PC6 2 &pcfg_pull_up>,
1085 913 <1 RK_PC7 2 &pcfg_pull_up>,
1086 914 <1 RK_PD0 2 &pcfg_pull_up>,
1087 915 <1 RK_PD1 2 &pcfg_pull_up>;
1088 }; 916 };
1089 }; 917 };
1090 918
1091 gmac { 919 gmac {
1092 rgmii_pins: rgmii-pin 920 rgmii_pins: rgmii-pins {
1093 rockchip,pins !! 921 rockchip,pins = <3 RK_PC6 1 &pcfg_pull_none>,
1094 922 <3 RK_PD0 1 &pcfg_pull_none>,
1095 923 <3 RK_PC3 1 &pcfg_pull_none>,
1096 924 <3 RK_PB0 1 &pcfg_pull_none_12ma>,
1097 925 <3 RK_PB1 1 &pcfg_pull_none_12ma>,
1098 926 <3 RK_PB2 1 &pcfg_pull_none_12ma>,
1099 927 <3 RK_PB6 1 &pcfg_pull_none_12ma>,
1100 928 <3 RK_PD4 1 &pcfg_pull_none_12ma>,
1101 929 <3 RK_PB5 1 &pcfg_pull_none_12ma>,
1102 930 <3 RK_PB7 1 &pcfg_pull_none>,
1103 931 <3 RK_PC0 1 &pcfg_pull_none>,
1104 932 <3 RK_PC1 1 &pcfg_pull_none>,
1105 933 <3 RK_PC2 1 &pcfg_pull_none>,
1106 934 <3 RK_PD1 1 &pcfg_pull_none>,
1107 935 <3 RK_PC4 1 &pcfg_pull_none>;
1108 }; 936 };
1109 937
1110 rmii_pins: rmii-pins 938 rmii_pins: rmii-pins {
1111 rockchip,pins !! 939 rockchip,pins = <3 RK_PC6 1 &pcfg_pull_none>,
1112 940 <3 RK_PD0 1 &pcfg_pull_none>,
1113 941 <3 RK_PC3 1 &pcfg_pull_none>,
1114 942 <3 RK_PB0 1 &pcfg_pull_none_12ma>,
1115 943 <3 RK_PB1 1 &pcfg_pull_none_12ma>,
1116 944 <3 RK_PB5 1 &pcfg_pull_none_12ma>,
1117 945 <3 RK_PB7 1 &pcfg_pull_none>,
1118 946 <3 RK_PC0 1 &pcfg_pull_none>,
1119 947 <3 RK_PC4 1 &pcfg_pull_none>,
1120 948 <3 RK_PC5 1 &pcfg_pull_none>;
1121 }; 949 };
1122 }; 950 };
1123 951
1124 i2c0 { 952 i2c0 {
1125 i2c0_xfer: i2c0-xfer 953 i2c0_xfer: i2c0-xfer {
1126 rockchip,pins 954 rockchip,pins = <0 RK_PA6 1 &pcfg_pull_none>,
1127 955 <0 RK_PA7 1 &pcfg_pull_none>;
1128 }; 956 };
1129 }; 957 };
1130 958
1131 i2c1 { 959 i2c1 {
1132 i2c1_xfer: i2c1-xfer 960 i2c1_xfer: i2c1-xfer {
1133 rockchip,pins 961 rockchip,pins = <2 RK_PC5 1 &pcfg_pull_none>,
1134 962 <2 RK_PC6 1 &pcfg_pull_none>;
1135 }; 963 };
1136 }; 964 };
1137 965
1138 i2c2 { 966 i2c2 {
1139 i2c2_xfer: i2c2-xfer 967 i2c2_xfer: i2c2-xfer {
1140 rockchip,pins 968 rockchip,pins = <0 RK_PB1 2 &pcfg_pull_none>,
1141 969 <3 RK_PD7 2 &pcfg_pull_none>;
1142 }; 970 };
1143 }; 971 };
1144 972
1145 i2c3 { 973 i2c3 {
1146 i2c3_xfer: i2c3-xfer 974 i2c3_xfer: i2c3-xfer {
1147 rockchip,pins 975 rockchip,pins = <1 RK_PC0 1 &pcfg_pull_none>,
1148 976 <1 RK_PC1 1 &pcfg_pull_none>;
1149 }; 977 };
1150 }; 978 };
1151 979
1152 i2c4 { 980 i2c4 {
1153 i2c4_xfer: i2c4-xfer 981 i2c4_xfer: i2c4-xfer {
1154 rockchip,pins 982 rockchip,pins = <3 RK_PD0 2 &pcfg_pull_none>,
1155 983 <3 RK_PD1 2 &pcfg_pull_none>;
1156 }; 984 };
1157 }; 985 };
1158 986
1159 i2c5 { 987 i2c5 {
1160 i2c5_xfer: i2c5-xfer 988 i2c5_xfer: i2c5-xfer {
1161 rockchip,pins 989 rockchip,pins = <3 RK_PD2 2 &pcfg_pull_none>,
1162 990 <3 RK_PD3 2 &pcfg_pull_none>;
1163 }; 991 };
1164 }; 992 };
1165 993
1166 i2s { 994 i2s {
1167 i2s_8ch_bus: i2s-8ch- 995 i2s_8ch_bus: i2s-8ch-bus {
1168 rockchip,pins 996 rockchip,pins = <2 RK_PB4 1 &pcfg_pull_none>,
1169 997 <2 RK_PB5 1 &pcfg_pull_none>,
1170 998 <2 RK_PB6 1 &pcfg_pull_none>,
1171 999 <2 RK_PB7 1 &pcfg_pull_none>,
1172 1000 <2 RK_PC0 1 &pcfg_pull_none>,
1173 1001 <2 RK_PC1 1 &pcfg_pull_none>,
1174 1002 <2 RK_PC2 1 &pcfg_pull_none>,
1175 1003 <2 RK_PC3 1 &pcfg_pull_none>,
1176 1004 <2 RK_PC4 1 &pcfg_pull_none>;
1177 }; 1005 };
1178 }; 1006 };
1179 1007
1180 pwm0 { 1008 pwm0 {
1181 pwm0_pin: pwm0-pin { 1009 pwm0_pin: pwm0-pin {
1182 rockchip,pins 1010 rockchip,pins = <3 RK_PB0 2 &pcfg_pull_none>;
1183 }; 1011 };
1184 }; 1012 };
1185 1013
1186 pwm1 { 1014 pwm1 {
1187 pwm1_pin: pwm1-pin { 1015 pwm1_pin: pwm1-pin {
1188 rockchip,pins 1016 rockchip,pins = <0 RK_PB0 2 &pcfg_pull_none>;
1189 }; 1017 };
1190 }; 1018 };
1191 1019
1192 pwm3 { 1020 pwm3 {
1193 pwm3_pin: pwm3-pin { 1021 pwm3_pin: pwm3-pin {
1194 rockchip,pins 1022 rockchip,pins = <3 RK_PD5 3 &pcfg_pull_none>;
1195 }; 1023 };
1196 }; 1024 };
1197 1025
1198 sdio0 { 1026 sdio0 {
1199 sdio0_bus1: sdio0-bus 1027 sdio0_bus1: sdio0-bus1 {
1200 rockchip,pins 1028 rockchip,pins = <2 RK_PD4 1 &pcfg_pull_up>;
1201 }; 1029 };
1202 1030
1203 sdio0_bus4: sdio0-bus 1031 sdio0_bus4: sdio0-bus4 {
1204 rockchip,pins 1032 rockchip,pins = <2 RK_PD4 1 &pcfg_pull_up>,
1205 1033 <2 RK_PD5 1 &pcfg_pull_up>,
1206 1034 <2 RK_PD6 1 &pcfg_pull_up>,
1207 1035 <2 RK_PD7 1 &pcfg_pull_up>;
1208 }; 1036 };
1209 1037
1210 sdio0_cmd: sdio0-cmd 1038 sdio0_cmd: sdio0-cmd {
1211 rockchip,pins 1039 rockchip,pins = <3 RK_PA0 1 &pcfg_pull_up>;
1212 }; 1040 };
1213 1041
1214 sdio0_clk: sdio0-clk 1042 sdio0_clk: sdio0-clk {
1215 rockchip,pins 1043 rockchip,pins = <3 RK_PA1 1 &pcfg_pull_none>;
1216 }; 1044 };
1217 1045
1218 sdio0_cd: sdio0-cd { 1046 sdio0_cd: sdio0-cd {
1219 rockchip,pins 1047 rockchip,pins = <3 RK_PA2 1 &pcfg_pull_up>;
1220 }; 1048 };
1221 1049
1222 sdio0_wp: sdio0-wp { 1050 sdio0_wp: sdio0-wp {
1223 rockchip,pins 1051 rockchip,pins = <3 RK_PA3 1 &pcfg_pull_up>;
1224 }; 1052 };
1225 1053
1226 sdio0_pwr: sdio0-pwr 1054 sdio0_pwr: sdio0-pwr {
1227 rockchip,pins 1055 rockchip,pins = <3 RK_PA4 1 &pcfg_pull_up>;
1228 }; 1056 };
1229 1057
1230 sdio0_bkpwr: sdio0-bk 1058 sdio0_bkpwr: sdio0-bkpwr {
1231 rockchip,pins 1059 rockchip,pins = <3 RK_PA5 1 &pcfg_pull_up>;
1232 }; 1060 };
1233 1061
1234 sdio0_int: sdio0-int 1062 sdio0_int: sdio0-int {
1235 rockchip,pins 1063 rockchip,pins = <3 RK_PA6 1 &pcfg_pull_up>;
1236 }; 1064 };
1237 }; 1065 };
1238 1066
1239 sdmmc { 1067 sdmmc {
1240 sdmmc_clk: sdmmc-clk 1068 sdmmc_clk: sdmmc-clk {
1241 rockchip,pins 1069 rockchip,pins = <2 RK_PB1 1 &pcfg_pull_none>;
1242 }; 1070 };
1243 1071
1244 sdmmc_cmd: sdmmc-cmd 1072 sdmmc_cmd: sdmmc-cmd {
1245 rockchip,pins 1073 rockchip,pins = <2 RK_PB2 1 &pcfg_pull_up>;
1246 }; 1074 };
1247 1075
1248 sdmmc_cd: sdmmc-cd { 1076 sdmmc_cd: sdmmc-cd {
1249 rockchip,pins 1077 rockchip,pins = <2 RK_PB3 1 &pcfg_pull_up>;
1250 }; 1078 };
1251 1079
1252 sdmmc_bus1: sdmmc-bus 1080 sdmmc_bus1: sdmmc-bus1 {
1253 rockchip,pins 1081 rockchip,pins = <2 RK_PA5 1 &pcfg_pull_up>;
1254 }; 1082 };
1255 1083
1256 sdmmc_bus4: sdmmc-bus 1084 sdmmc_bus4: sdmmc-bus4 {
1257 rockchip,pins 1085 rockchip,pins = <2 RK_PA5 1 &pcfg_pull_up>,
1258 1086 <2 RK_PA6 1 &pcfg_pull_up>,
1259 1087 <2 RK_PA7 1 &pcfg_pull_up>,
1260 1088 <2 RK_PB0 1 &pcfg_pull_up>;
1261 }; 1089 };
1262 }; 1090 };
1263 1091
1264 spdif { 1092 spdif {
1265 spdif_tx: spdif-tx { 1093 spdif_tx: spdif-tx {
1266 rockchip,pins !! 1094 rockchip,pins = <2 RK_PC7 1 &pcfg_pull_none>;
1267 }; 1095 };
1268 }; 1096 };
1269 1097
1270 spi0 { 1098 spi0 {
1271 spi0_clk: spi0-clk { 1099 spi0_clk: spi0-clk {
1272 rockchip,pins 1100 rockchip,pins = <1 RK_PD5 2 &pcfg_pull_up>;
1273 }; 1101 };
1274 spi0_cs0: spi0-cs0 { 1102 spi0_cs0: spi0-cs0 {
1275 rockchip,pins 1103 rockchip,pins = <1 RK_PD0 3 &pcfg_pull_up>;
1276 }; 1104 };
1277 spi0_cs1: spi0-cs1 { 1105 spi0_cs1: spi0-cs1 {
1278 rockchip,pins 1106 rockchip,pins = <1 RK_PD1 3 &pcfg_pull_up>;
1279 }; 1107 };
1280 spi0_tx: spi0-tx { 1108 spi0_tx: spi0-tx {
1281 rockchip,pins 1109 rockchip,pins = <1 RK_PC7 3 &pcfg_pull_up>;
1282 }; 1110 };
1283 spi0_rx: spi0-rx { 1111 spi0_rx: spi0-rx {
1284 rockchip,pins 1112 rockchip,pins = <1 RK_PC6 3 &pcfg_pull_up>;
1285 }; 1113 };
1286 }; 1114 };
1287 1115
1288 spi1 { 1116 spi1 {
1289 spi1_clk: spi1-clk { 1117 spi1_clk: spi1-clk {
1290 rockchip,pins 1118 rockchip,pins = <1 RK_PB6 2 &pcfg_pull_up>;
1291 }; 1119 };
1292 spi1_cs0: spi1-cs0 { 1120 spi1_cs0: spi1-cs0 {
1293 rockchip,pins 1121 rockchip,pins = <1 RK_PB7 2 &pcfg_pull_up>;
1294 }; 1122 };
1295 spi1_cs1: spi1-cs1 { 1123 spi1_cs1: spi1-cs1 {
1296 rockchip,pins 1124 rockchip,pins = <3 RK_PD4 2 &pcfg_pull_up>;
1297 }; 1125 };
1298 spi1_rx: spi1-rx { 1126 spi1_rx: spi1-rx {
1299 rockchip,pins 1127 rockchip,pins = <1 RK_PC0 2 &pcfg_pull_up>;
1300 }; 1128 };
1301 spi1_tx: spi1-tx { 1129 spi1_tx: spi1-tx {
1302 rockchip,pins 1130 rockchip,pins = <1 RK_PC1 2 &pcfg_pull_up>;
1303 }; 1131 };
1304 }; 1132 };
1305 1133
1306 spi2 { 1134 spi2 {
1307 spi2_clk: spi2-clk { 1135 spi2_clk: spi2-clk {
1308 rockchip,pins 1136 rockchip,pins = <0 RK_PB4 2 &pcfg_pull_up>;
1309 }; 1137 };
1310 spi2_cs0: spi2-cs0 { 1138 spi2_cs0: spi2-cs0 {
1311 rockchip,pins 1139 rockchip,pins = <0 RK_PB5 2 &pcfg_pull_up>;
1312 }; 1140 };
1313 spi2_rx: spi2-rx { 1141 spi2_rx: spi2-rx {
1314 rockchip,pins 1142 rockchip,pins = <0 RK_PB2 2 &pcfg_pull_up>;
1315 }; 1143 };
1316 spi2_tx: spi2-tx { 1144 spi2_tx: spi2-tx {
1317 rockchip,pins 1145 rockchip,pins = <0 RK_PB3 2 &pcfg_pull_up>;
1318 }; 1146 };
1319 }; 1147 };
1320 1148
1321 tsadc { 1149 tsadc {
1322 otp_pin: otp-pin { 1150 otp_pin: otp-pin {
1323 rockchip,pins 1151 rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
1324 }; 1152 };
1325 1153
1326 otp_out: otp-out { 1154 otp_out: otp-out {
1327 rockchip,pins 1155 rockchip,pins = <0 RK_PA3 1 &pcfg_pull_none>;
1328 }; 1156 };
1329 }; 1157 };
1330 1158
1331 uart0 { 1159 uart0 {
1332 uart0_xfer: uart0-xfe 1160 uart0_xfer: uart0-xfer {
1333 rockchip,pins 1161 rockchip,pins = <2 RK_PD0 1 &pcfg_pull_up>,
1334 1162 <2 RK_PD1 1 &pcfg_pull_none>;
1335 }; 1163 };
1336 1164
1337 uart0_cts: uart0-cts 1165 uart0_cts: uart0-cts {
1338 rockchip,pins 1166 rockchip,pins = <2 RK_PD2 1 &pcfg_pull_none>;
1339 }; 1167 };
1340 1168
1341 uart0_rts: uart0-rts 1169 uart0_rts: uart0-rts {
1342 rockchip,pins 1170 rockchip,pins = <2 RK_PD3 1 &pcfg_pull_none>;
1343 }; 1171 };
1344 }; 1172 };
1345 1173
1346 uart1 { 1174 uart1 {
1347 uart1_xfer: uart1-xfe 1175 uart1_xfer: uart1-xfer {
1348 rockchip,pins 1176 rockchip,pins = <0 RK_PC4 3 &pcfg_pull_up>,
1349 1177 <0 RK_PC5 3 &pcfg_pull_none>;
1350 }; 1178 };
1351 1179
1352 uart1_cts: uart1-cts 1180 uart1_cts: uart1-cts {
1353 rockchip,pins 1181 rockchip,pins = <0 RK_PC6 3 &pcfg_pull_none>;
1354 }; 1182 };
1355 1183
1356 uart1_rts: uart1-rts 1184 uart1_rts: uart1-rts {
1357 rockchip,pins 1185 rockchip,pins = <0 RK_PC7 3 &pcfg_pull_none>;
1358 }; 1186 };
1359 }; 1187 };
1360 1188
1361 uart2 { 1189 uart2 {
1362 uart2_xfer: uart2-xfe 1190 uart2_xfer: uart2-xfer {
1363 rockchip,pins 1191 rockchip,pins = <2 RK_PA6 2 &pcfg_pull_up>,
1364 1192 <2 RK_PA5 2 &pcfg_pull_none>;
1365 }; 1193 };
1366 /* no rts / cts for u 1194 /* no rts / cts for uart2 */
1367 }; 1195 };
1368 1196
1369 uart3 { 1197 uart3 {
1370 uart3_xfer: uart3-xfe 1198 uart3_xfer: uart3-xfer {
1371 rockchip,pins 1199 rockchip,pins = <3 RK_PD5 2 &pcfg_pull_up>,
1372 1200 <3 RK_PD6 3 &pcfg_pull_none>;
1373 }; 1201 };
1374 1202
1375 uart3_cts: uart3-cts 1203 uart3_cts: uart3-cts {
1376 rockchip,pins 1204 rockchip,pins = <3 RK_PC0 2 &pcfg_pull_none>;
1377 }; 1205 };
1378 1206
1379 uart3_rts: uart3-rts 1207 uart3_rts: uart3-rts {
1380 rockchip,pins 1208 rockchip,pins = <3 RK_PC1 2 &pcfg_pull_none>;
1381 }; 1209 };
1382 }; 1210 };
1383 1211
1384 uart4 { 1212 uart4 {
1385 uart4_xfer: uart4-xfe 1213 uart4_xfer: uart4-xfer {
1386 rockchip,pins 1214 rockchip,pins = <0 RK_PD3 3 &pcfg_pull_up>,
1387 1215 <0 RK_PD2 3 &pcfg_pull_none>;
1388 }; 1216 };
1389 1217
1390 uart4_cts: uart4-cts 1218 uart4_cts: uart4-cts {
1391 rockchip,pins 1219 rockchip,pins = <0 RK_PD0 3 &pcfg_pull_none>;
1392 }; 1220 };
1393 1221
1394 uart4_rts: uart4-rts 1222 uart4_rts: uart4-rts {
1395 rockchip,pins 1223 rockchip,pins = <0 RK_PD1 3 &pcfg_pull_none>;
1396 }; 1224 };
1397 }; 1225 };
1398 }; 1226 };
1399 }; 1227 };
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