1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /* 2 /*
3 * Copyright (c) 2015 Heiko Stuebner <heiko@snt 3 * Copyright (c) 2015 Heiko Stuebner <heiko@sntech.de>
4 */ 4 */
5 5
6 #include <dt-bindings/clock/rk3368-cru.h> 6 #include <dt-bindings/clock/rk3368-cru.h>
7 #include <dt-bindings/gpio/gpio.h> 7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/interrupt-controller/irq 8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/interrupt-controller/arm 9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/pinctrl/rockchip.h> 10 #include <dt-bindings/pinctrl/rockchip.h>
11 #include <dt-bindings/power/rk3368-power.h> <<
12 #include <dt-bindings/soc/rockchip,boot-mode.h 11 #include <dt-bindings/soc/rockchip,boot-mode.h>
13 #include <dt-bindings/thermal/thermal.h> 12 #include <dt-bindings/thermal/thermal.h>
14 13
15 / { 14 / {
16 compatible = "rockchip,rk3368"; 15 compatible = "rockchip,rk3368";
17 interrupt-parent = <&gic>; 16 interrupt-parent = <&gic>;
18 #address-cells = <2>; 17 #address-cells = <2>;
19 #size-cells = <2>; 18 #size-cells = <2>;
20 19
21 aliases { 20 aliases {
22 gpio0 = &gpio0; !! 21 ethernet0 = &gmac;
23 gpio1 = &gpio1; <<
24 gpio2 = &gpio2; <<
25 gpio3 = &gpio3; <<
26 i2c0 = &i2c0; 22 i2c0 = &i2c0;
27 i2c1 = &i2c1; 23 i2c1 = &i2c1;
28 i2c2 = &i2c2; 24 i2c2 = &i2c2;
29 i2c3 = &i2c3; 25 i2c3 = &i2c3;
30 i2c4 = &i2c4; 26 i2c4 = &i2c4;
31 i2c5 = &i2c5; 27 i2c5 = &i2c5;
32 serial0 = &uart0; 28 serial0 = &uart0;
33 serial1 = &uart1; 29 serial1 = &uart1;
34 serial2 = &uart2; 30 serial2 = &uart2;
35 serial3 = &uart3; 31 serial3 = &uart3;
36 serial4 = &uart4; 32 serial4 = &uart4;
37 spi0 = &spi0; 33 spi0 = &spi0;
38 spi1 = &spi1; 34 spi1 = &spi1;
39 spi2 = &spi2; 35 spi2 = &spi2;
40 }; 36 };
41 37
42 cpus { 38 cpus {
43 #address-cells = <0x2>; 39 #address-cells = <0x2>;
44 #size-cells = <0x0>; 40 #size-cells = <0x0>;
45 41
46 cpu-map { 42 cpu-map {
47 cluster0 { 43 cluster0 {
48 core0 { 44 core0 {
49 cpu = 45 cpu = <&cpu_b0>;
50 }; 46 };
51 core1 { 47 core1 {
52 cpu = 48 cpu = <&cpu_b1>;
53 }; 49 };
54 core2 { 50 core2 {
55 cpu = 51 cpu = <&cpu_b2>;
56 }; 52 };
57 core3 { 53 core3 {
58 cpu = 54 cpu = <&cpu_b3>;
59 }; 55 };
60 }; 56 };
61 57
62 cluster1 { 58 cluster1 {
63 core0 { 59 core0 {
64 cpu = 60 cpu = <&cpu_l0>;
65 }; 61 };
66 core1 { 62 core1 {
67 cpu = 63 cpu = <&cpu_l1>;
68 }; 64 };
69 core2 { 65 core2 {
70 cpu = 66 cpu = <&cpu_l2>;
71 }; 67 };
72 core3 { 68 core3 {
73 cpu = 69 cpu = <&cpu_l3>;
74 }; 70 };
75 }; 71 };
76 }; 72 };
77 73
78 cpu_l0: cpu@0 { 74 cpu_l0: cpu@0 {
79 device_type = "cpu"; 75 device_type = "cpu";
80 compatible = "arm,cort 76 compatible = "arm,cortex-a53";
81 reg = <0x0 0x0>; 77 reg = <0x0 0x0>;
82 enable-method = "psci" 78 enable-method = "psci";
83 #cooling-cells = <2>; 79 #cooling-cells = <2>; /* min followed by max */
84 }; 80 };
85 81
86 cpu_l1: cpu@1 { 82 cpu_l1: cpu@1 {
87 device_type = "cpu"; 83 device_type = "cpu";
88 compatible = "arm,cort 84 compatible = "arm,cortex-a53";
89 reg = <0x0 0x1>; 85 reg = <0x0 0x1>;
90 enable-method = "psci" 86 enable-method = "psci";
91 #cooling-cells = <2>; 87 #cooling-cells = <2>; /* min followed by max */
92 }; 88 };
93 89
94 cpu_l2: cpu@2 { 90 cpu_l2: cpu@2 {
95 device_type = "cpu"; 91 device_type = "cpu";
96 compatible = "arm,cort 92 compatible = "arm,cortex-a53";
97 reg = <0x0 0x2>; 93 reg = <0x0 0x2>;
98 enable-method = "psci" 94 enable-method = "psci";
99 #cooling-cells = <2>; 95 #cooling-cells = <2>; /* min followed by max */
100 }; 96 };
101 97
102 cpu_l3: cpu@3 { 98 cpu_l3: cpu@3 {
103 device_type = "cpu"; 99 device_type = "cpu";
104 compatible = "arm,cort 100 compatible = "arm,cortex-a53";
105 reg = <0x0 0x3>; 101 reg = <0x0 0x3>;
106 enable-method = "psci" 102 enable-method = "psci";
107 #cooling-cells = <2>; 103 #cooling-cells = <2>; /* min followed by max */
108 }; 104 };
109 105
110 cpu_b0: cpu@100 { 106 cpu_b0: cpu@100 {
111 device_type = "cpu"; 107 device_type = "cpu";
112 compatible = "arm,cort 108 compatible = "arm,cortex-a53";
113 reg = <0x0 0x100>; 109 reg = <0x0 0x100>;
114 enable-method = "psci" 110 enable-method = "psci";
115 #cooling-cells = <2>; 111 #cooling-cells = <2>; /* min followed by max */
116 }; 112 };
117 113
118 cpu_b1: cpu@101 { 114 cpu_b1: cpu@101 {
119 device_type = "cpu"; 115 device_type = "cpu";
120 compatible = "arm,cort 116 compatible = "arm,cortex-a53";
121 reg = <0x0 0x101>; 117 reg = <0x0 0x101>;
122 enable-method = "psci" 118 enable-method = "psci";
123 #cooling-cells = <2>; 119 #cooling-cells = <2>; /* min followed by max */
124 }; 120 };
125 121
126 cpu_b2: cpu@102 { 122 cpu_b2: cpu@102 {
127 device_type = "cpu"; 123 device_type = "cpu";
128 compatible = "arm,cort 124 compatible = "arm,cortex-a53";
129 reg = <0x0 0x102>; 125 reg = <0x0 0x102>;
130 enable-method = "psci" 126 enable-method = "psci";
131 #cooling-cells = <2>; 127 #cooling-cells = <2>; /* min followed by max */
132 }; 128 };
133 129
134 cpu_b3: cpu@103 { 130 cpu_b3: cpu@103 {
135 device_type = "cpu"; 131 device_type = "cpu";
136 compatible = "arm,cort 132 compatible = "arm,cortex-a53";
137 reg = <0x0 0x103>; 133 reg = <0x0 0x103>;
138 enable-method = "psci" 134 enable-method = "psci";
139 #cooling-cells = <2>; 135 #cooling-cells = <2>; /* min followed by max */
140 }; 136 };
141 }; 137 };
142 138
143 arm-pmu { 139 arm-pmu {
144 compatible = "arm,cortex-a53-p !! 140 compatible = "arm,armv8-pmuv3";
145 interrupts = <GIC_SPI 112 IRQ_ 141 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
146 <GIC_SPI 113 IRQ_ 142 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
147 <GIC_SPI 114 IRQ_ 143 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
148 <GIC_SPI 115 IRQ_ 144 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
149 <GIC_SPI 116 IRQ_ 145 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
150 <GIC_SPI 117 IRQ_ 146 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
151 <GIC_SPI 118 IRQ_ 147 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
152 <GIC_SPI 119 IRQ_ 148 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
153 interrupt-affinity = <&cpu_l0> 149 interrupt-affinity = <&cpu_l0>, <&cpu_l1>, <&cpu_l2>,
154 <&cpu_l3> 150 <&cpu_l3>, <&cpu_b0>, <&cpu_b1>,
155 <&cpu_b2> 151 <&cpu_b2>, <&cpu_b3>;
156 }; 152 };
157 153
158 psci { 154 psci {
159 compatible = "arm,psci-0.2"; 155 compatible = "arm,psci-0.2";
160 method = "smc"; 156 method = "smc";
161 }; 157 };
162 158
163 timer { 159 timer {
164 compatible = "arm,armv8-timer" 160 compatible = "arm,armv8-timer";
165 interrupts = <GIC_PPI 13 161 interrupts = <GIC_PPI 13
166 (GIC_CPU_MASK_SIMPLE(8 162 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
167 <GIC_PPI 14 163 <GIC_PPI 14
168 (GIC_CPU_MASK_SIMPLE(8 164 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
169 <GIC_PPI 11 165 <GIC_PPI 11
170 (GIC_CPU_MASK_SIMPLE(8 166 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
171 <GIC_PPI 10 167 <GIC_PPI 10
172 (GIC_CPU_MASK_SIMPLE(8 168 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
173 }; 169 };
174 170
175 xin24m: oscillator { 171 xin24m: oscillator {
176 compatible = "fixed-clock"; 172 compatible = "fixed-clock";
177 clock-frequency = <24000000>; 173 clock-frequency = <24000000>;
178 clock-output-names = "xin24m"; 174 clock-output-names = "xin24m";
179 #clock-cells = <0>; 175 #clock-cells = <0>;
180 }; 176 };
181 177
182 sdmmc: mmc@ff0c0000 { 178 sdmmc: mmc@ff0c0000 {
183 compatible = "rockchip,rk3368- 179 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
184 reg = <0x0 0xff0c0000 0x0 0x40 180 reg = <0x0 0xff0c0000 0x0 0x4000>;
185 max-frequency = <150000000>; 181 max-frequency = <150000000>;
186 clocks = <&cru HCLK_SDMMC>, <& 182 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
187 <&cru SCLK_SDMMC_DRV> 183 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
188 clock-names = "biu", "ciu", "c 184 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
189 fifo-depth = <0x100>; 185 fifo-depth = <0x100>;
190 interrupts = <GIC_SPI 32 IRQ_T 186 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
191 resets = <&cru SRST_MMC0>; 187 resets = <&cru SRST_MMC0>;
192 reset-names = "reset"; 188 reset-names = "reset";
193 status = "disabled"; 189 status = "disabled";
194 }; 190 };
195 191
196 sdio0: mmc@ff0d0000 { 192 sdio0: mmc@ff0d0000 {
197 compatible = "rockchip,rk3368- 193 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
198 reg = <0x0 0xff0d0000 0x0 0x40 194 reg = <0x0 0xff0d0000 0x0 0x4000>;
199 max-frequency = <150000000>; 195 max-frequency = <150000000>;
200 clocks = <&cru HCLK_SDIO0>, <& 196 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>,
201 <&cru SCLK_SDIO0_DRV> 197 <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
202 clock-names = "biu", "ciu", "c 198 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
203 fifo-depth = <0x100>; 199 fifo-depth = <0x100>;
204 interrupts = <GIC_SPI 33 IRQ_T 200 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
205 resets = <&cru SRST_SDIO0>; 201 resets = <&cru SRST_SDIO0>;
206 reset-names = "reset"; 202 reset-names = "reset";
207 status = "disabled"; 203 status = "disabled";
208 }; 204 };
209 205
210 emmc: mmc@ff0f0000 { 206 emmc: mmc@ff0f0000 {
211 compatible = "rockchip,rk3368- 207 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
212 reg = <0x0 0xff0f0000 0x0 0x40 208 reg = <0x0 0xff0f0000 0x0 0x4000>;
213 max-frequency = <150000000>; 209 max-frequency = <150000000>;
214 clocks = <&cru HCLK_EMMC>, <&c 210 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
215 <&cru SCLK_EMMC_DRV>, 211 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
216 clock-names = "biu", "ciu", "c 212 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
217 fifo-depth = <0x100>; 213 fifo-depth = <0x100>;
218 interrupts = <GIC_SPI 35 IRQ_T 214 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
219 resets = <&cru SRST_EMMC>; 215 resets = <&cru SRST_EMMC>;
220 reset-names = "reset"; 216 reset-names = "reset";
221 status = "disabled"; 217 status = "disabled";
222 }; 218 };
223 219
224 saradc: saradc@ff100000 { 220 saradc: saradc@ff100000 {
225 compatible = "rockchip,saradc" 221 compatible = "rockchip,saradc";
226 reg = <0x0 0xff100000 0x0 0x10 222 reg = <0x0 0xff100000 0x0 0x100>;
227 interrupts = <GIC_SPI 36 IRQ_T 223 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
228 #io-channel-cells = <1>; 224 #io-channel-cells = <1>;
229 clocks = <&cru SCLK_SARADC>, < 225 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
230 clock-names = "saradc", "apb_p 226 clock-names = "saradc", "apb_pclk";
231 resets = <&cru SRST_SARADC>; 227 resets = <&cru SRST_SARADC>;
232 reset-names = "saradc-apb"; 228 reset-names = "saradc-apb";
233 status = "disabled"; 229 status = "disabled";
234 }; 230 };
235 231
236 spi0: spi@ff110000 { 232 spi0: spi@ff110000 {
237 compatible = "rockchip,rk3368- 233 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
238 reg = <0x0 0xff110000 0x0 0x10 234 reg = <0x0 0xff110000 0x0 0x1000>;
239 clocks = <&cru SCLK_SPI0>, <&c 235 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
240 clock-names = "spiclk", "apb_p 236 clock-names = "spiclk", "apb_pclk";
241 interrupts = <GIC_SPI 44 IRQ_T 237 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
242 pinctrl-names = "default"; 238 pinctrl-names = "default";
243 pinctrl-0 = <&spi0_clk &spi0_t 239 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
244 #address-cells = <1>; 240 #address-cells = <1>;
245 #size-cells = <0>; 241 #size-cells = <0>;
246 status = "disabled"; 242 status = "disabled";
247 }; 243 };
248 244
249 spi1: spi@ff120000 { 245 spi1: spi@ff120000 {
250 compatible = "rockchip,rk3368- 246 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
251 reg = <0x0 0xff120000 0x0 0x10 247 reg = <0x0 0xff120000 0x0 0x1000>;
252 clocks = <&cru SCLK_SPI1>, <&c 248 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
253 clock-names = "spiclk", "apb_p 249 clock-names = "spiclk", "apb_pclk";
254 interrupts = <GIC_SPI 45 IRQ_T 250 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
255 pinctrl-names = "default"; 251 pinctrl-names = "default";
256 pinctrl-0 = <&spi1_clk &spi1_t 252 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
257 #address-cells = <1>; 253 #address-cells = <1>;
258 #size-cells = <0>; 254 #size-cells = <0>;
259 status = "disabled"; 255 status = "disabled";
260 }; 256 };
261 257
262 spi2: spi@ff130000 { 258 spi2: spi@ff130000 {
263 compatible = "rockchip,rk3368- 259 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
264 reg = <0x0 0xff130000 0x0 0x10 260 reg = <0x0 0xff130000 0x0 0x1000>;
265 clocks = <&cru SCLK_SPI2>, <&c 261 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
266 clock-names = "spiclk", "apb_p 262 clock-names = "spiclk", "apb_pclk";
267 interrupts = <GIC_SPI 41 IRQ_T 263 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
268 pinctrl-names = "default"; 264 pinctrl-names = "default";
269 pinctrl-0 = <&spi2_clk &spi2_t 265 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
270 #address-cells = <1>; 266 #address-cells = <1>;
271 #size-cells = <0>; 267 #size-cells = <0>;
272 status = "disabled"; 268 status = "disabled";
273 }; 269 };
274 270
275 i2c2: i2c@ff140000 { 271 i2c2: i2c@ff140000 {
276 compatible = "rockchip,rk3368- 272 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
277 reg = <0x0 0xff140000 0x0 0x10 273 reg = <0x0 0xff140000 0x0 0x1000>;
278 interrupts = <GIC_SPI 62 IRQ_T 274 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
279 #address-cells = <1>; 275 #address-cells = <1>;
280 #size-cells = <0>; 276 #size-cells = <0>;
281 clock-names = "i2c"; 277 clock-names = "i2c";
282 clocks = <&cru PCLK_I2C2>; 278 clocks = <&cru PCLK_I2C2>;
283 pinctrl-names = "default"; 279 pinctrl-names = "default";
284 pinctrl-0 = <&i2c2_xfer>; 280 pinctrl-0 = <&i2c2_xfer>;
285 status = "disabled"; 281 status = "disabled";
286 }; 282 };
287 283
288 i2c3: i2c@ff150000 { 284 i2c3: i2c@ff150000 {
289 compatible = "rockchip,rk3368- 285 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
290 reg = <0x0 0xff150000 0x0 0x10 286 reg = <0x0 0xff150000 0x0 0x1000>;
291 interrupts = <GIC_SPI 63 IRQ_T 287 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
292 #address-cells = <1>; 288 #address-cells = <1>;
293 #size-cells = <0>; 289 #size-cells = <0>;
294 clock-names = "i2c"; 290 clock-names = "i2c";
295 clocks = <&cru PCLK_I2C3>; 291 clocks = <&cru PCLK_I2C3>;
296 pinctrl-names = "default"; 292 pinctrl-names = "default";
297 pinctrl-0 = <&i2c3_xfer>; 293 pinctrl-0 = <&i2c3_xfer>;
298 status = "disabled"; 294 status = "disabled";
299 }; 295 };
300 296
301 i2c4: i2c@ff160000 { 297 i2c4: i2c@ff160000 {
302 compatible = "rockchip,rk3368- 298 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
303 reg = <0x0 0xff160000 0x0 0x10 299 reg = <0x0 0xff160000 0x0 0x1000>;
304 interrupts = <GIC_SPI 64 IRQ_T 300 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
305 #address-cells = <1>; 301 #address-cells = <1>;
306 #size-cells = <0>; 302 #size-cells = <0>;
307 clock-names = "i2c"; 303 clock-names = "i2c";
308 clocks = <&cru PCLK_I2C4>; 304 clocks = <&cru PCLK_I2C4>;
309 pinctrl-names = "default"; 305 pinctrl-names = "default";
310 pinctrl-0 = <&i2c4_xfer>; 306 pinctrl-0 = <&i2c4_xfer>;
311 status = "disabled"; 307 status = "disabled";
312 }; 308 };
313 309
314 i2c5: i2c@ff170000 { 310 i2c5: i2c@ff170000 {
315 compatible = "rockchip,rk3368- 311 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
316 reg = <0x0 0xff170000 0x0 0x10 312 reg = <0x0 0xff170000 0x0 0x1000>;
317 interrupts = <GIC_SPI 65 IRQ_T 313 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
318 #address-cells = <1>; 314 #address-cells = <1>;
319 #size-cells = <0>; 315 #size-cells = <0>;
320 clock-names = "i2c"; 316 clock-names = "i2c";
321 clocks = <&cru PCLK_I2C5>; 317 clocks = <&cru PCLK_I2C5>;
322 pinctrl-names = "default"; 318 pinctrl-names = "default";
323 pinctrl-0 = <&i2c5_xfer>; 319 pinctrl-0 = <&i2c5_xfer>;
324 status = "disabled"; 320 status = "disabled";
325 }; 321 };
326 322
327 uart0: serial@ff180000 { 323 uart0: serial@ff180000 {
328 compatible = "rockchip,rk3368- 324 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
329 reg = <0x0 0xff180000 0x0 0x10 325 reg = <0x0 0xff180000 0x0 0x100>;
330 clock-frequency = <24000000>; 326 clock-frequency = <24000000>;
331 clocks = <&cru SCLK_UART0>, <& 327 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
332 clock-names = "baudclk", "apb_ 328 clock-names = "baudclk", "apb_pclk";
333 interrupts = <GIC_SPI 55 IRQ_T 329 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
334 reg-shift = <2>; 330 reg-shift = <2>;
335 reg-io-width = <4>; 331 reg-io-width = <4>;
336 status = "disabled"; 332 status = "disabled";
337 }; 333 };
338 334
339 uart1: serial@ff190000 { 335 uart1: serial@ff190000 {
340 compatible = "rockchip,rk3368- 336 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
341 reg = <0x0 0xff190000 0x0 0x10 337 reg = <0x0 0xff190000 0x0 0x100>;
342 clock-frequency = <24000000>; 338 clock-frequency = <24000000>;
343 clocks = <&cru SCLK_UART1>, <& 339 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
344 clock-names = "baudclk", "apb_ 340 clock-names = "baudclk", "apb_pclk";
345 interrupts = <GIC_SPI 56 IRQ_T 341 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
346 reg-shift = <2>; 342 reg-shift = <2>;
347 reg-io-width = <4>; 343 reg-io-width = <4>;
348 status = "disabled"; 344 status = "disabled";
349 }; 345 };
350 346
351 uart3: serial@ff1b0000 { 347 uart3: serial@ff1b0000 {
352 compatible = "rockchip,rk3368- 348 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
353 reg = <0x0 0xff1b0000 0x0 0x10 349 reg = <0x0 0xff1b0000 0x0 0x100>;
354 clock-frequency = <24000000>; 350 clock-frequency = <24000000>;
355 clocks = <&cru SCLK_UART3>, <& 351 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
356 clock-names = "baudclk", "apb_ 352 clock-names = "baudclk", "apb_pclk";
357 interrupts = <GIC_SPI 58 IRQ_T 353 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
358 reg-shift = <2>; 354 reg-shift = <2>;
359 reg-io-width = <4>; 355 reg-io-width = <4>;
360 status = "disabled"; 356 status = "disabled";
361 }; 357 };
362 358
363 uart4: serial@ff1c0000 { 359 uart4: serial@ff1c0000 {
364 compatible = "rockchip,rk3368- 360 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
365 reg = <0x0 0xff1c0000 0x0 0x10 361 reg = <0x0 0xff1c0000 0x0 0x100>;
366 clock-frequency = <24000000>; 362 clock-frequency = <24000000>;
367 clocks = <&cru SCLK_UART4>, <& 363 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
368 clock-names = "baudclk", "apb_ 364 clock-names = "baudclk", "apb_pclk";
369 interrupts = <GIC_SPI 59 IRQ_T 365 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
370 reg-shift = <2>; 366 reg-shift = <2>;
371 reg-io-width = <4>; 367 reg-io-width = <4>;
372 status = "disabled"; 368 status = "disabled";
373 }; 369 };
374 370
375 dmac_peri: dma-controller@ff250000 { 371 dmac_peri: dma-controller@ff250000 {
376 compatible = "arm,pl330", "arm 372 compatible = "arm,pl330", "arm,primecell";
377 reg = <0x0 0xff250000 0x0 0x40 373 reg = <0x0 0xff250000 0x0 0x4000>;
378 interrupts = <GIC_SPI 2 IRQ_TY 374 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
379 <GIC_SPI 3 IRQ_TY 375 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
380 #dma-cells = <1>; 376 #dma-cells = <1>;
381 arm,pl330-broken-no-flushp; 377 arm,pl330-broken-no-flushp;
382 arm,pl330-periph-burst; 378 arm,pl330-periph-burst;
383 clocks = <&cru ACLK_DMAC_PERI> 379 clocks = <&cru ACLK_DMAC_PERI>;
384 clock-names = "apb_pclk"; 380 clock-names = "apb_pclk";
385 }; 381 };
386 382
387 thermal-zones { 383 thermal-zones {
388 cpu_thermal: cpu-thermal { 384 cpu_thermal: cpu-thermal {
389 polling-delay-passive 385 polling-delay-passive = <100>; /* milliseconds */
390 polling-delay = <5000> 386 polling-delay = <5000>; /* milliseconds */
391 387
392 thermal-sensors = <&ts 388 thermal-sensors = <&tsadc 0>;
393 389
394 trips { 390 trips {
395 cpu_alert0: cp 391 cpu_alert0: cpu_alert0 {
396 temper 392 temperature = <75000>; /* millicelsius */
397 hyster 393 hysteresis = <2000>; /* millicelsius */
398 type = 394 type = "passive";
399 }; 395 };
400 cpu_alert1: cp 396 cpu_alert1: cpu_alert1 {
401 temper 397 temperature = <80000>; /* millicelsius */
402 hyster 398 hysteresis = <2000>; /* millicelsius */
403 type = 399 type = "passive";
404 }; 400 };
405 cpu_crit: cpu_ 401 cpu_crit: cpu_crit {
406 temper 402 temperature = <95000>; /* millicelsius */
407 hyster 403 hysteresis = <2000>; /* millicelsius */
408 type = 404 type = "critical";
409 }; 405 };
410 }; 406 };
411 407
412 cooling-maps { 408 cooling-maps {
413 map0 { 409 map0 {
414 trip = 410 trip = <&cpu_alert0>;
415 coolin 411 cooling-device =
416 <&cpu_ 412 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
417 <&cpu_ 413 <&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
418 <&cpu_ 414 <&cpu_b2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
419 <&cpu_ 415 <&cpu_b3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
420 }; 416 };
421 map1 { 417 map1 {
422 trip = 418 trip = <&cpu_alert1>;
423 coolin 419 cooling-device =
424 <&cpu_ 420 <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
425 <&cpu_ 421 <&cpu_l1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
426 <&cpu_ 422 <&cpu_l2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
427 <&cpu_ 423 <&cpu_l3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
428 }; 424 };
429 }; 425 };
430 }; 426 };
431 427
432 gpu_thermal: gpu-thermal { 428 gpu_thermal: gpu-thermal {
433 polling-delay-passive 429 polling-delay-passive = <100>; /* milliseconds */
434 polling-delay = <5000> 430 polling-delay = <5000>; /* milliseconds */
435 431
436 thermal-sensors = <&ts 432 thermal-sensors = <&tsadc 1>;
437 433
438 trips { 434 trips {
439 gpu_alert0: gp 435 gpu_alert0: gpu_alert0 {
440 temper 436 temperature = <80000>; /* millicelsius */
441 hyster 437 hysteresis = <2000>; /* millicelsius */
442 type = 438 type = "passive";
443 }; 439 };
444 gpu_crit: gpu_ 440 gpu_crit: gpu_crit {
445 temper 441 temperature = <115000>; /* millicelsius */
446 hyster 442 hysteresis = <2000>; /* millicelsius */
447 type = 443 type = "critical";
448 }; 444 };
449 }; 445 };
450 446
451 cooling-maps { 447 cooling-maps {
452 map0 { 448 map0 {
453 trip = 449 trip = <&gpu_alert0>;
454 coolin 450 cooling-device =
455 <&cpu_ 451 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
456 <&cpu_ 452 <&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
457 <&cpu_ 453 <&cpu_b2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
458 <&cpu_ 454 <&cpu_b3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
459 }; 455 };
460 }; 456 };
461 }; 457 };
462 }; 458 };
463 459
464 tsadc: tsadc@ff280000 { 460 tsadc: tsadc@ff280000 {
465 compatible = "rockchip,rk3368- 461 compatible = "rockchip,rk3368-tsadc";
466 reg = <0x0 0xff280000 0x0 0x10 462 reg = <0x0 0xff280000 0x0 0x100>;
467 interrupts = <GIC_SPI 37 IRQ_T 463 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
468 clocks = <&cru SCLK_TSADC>, <& 464 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
469 clock-names = "tsadc", "apb_pc 465 clock-names = "tsadc", "apb_pclk";
470 resets = <&cru SRST_TSADC>; 466 resets = <&cru SRST_TSADC>;
471 reset-names = "tsadc-apb"; 467 reset-names = "tsadc-apb";
472 pinctrl-names = "init", "defau 468 pinctrl-names = "init", "default", "sleep";
473 pinctrl-0 = <&otp_pin>; 469 pinctrl-0 = <&otp_pin>;
474 pinctrl-1 = <&otp_out>; 470 pinctrl-1 = <&otp_out>;
475 pinctrl-2 = <&otp_pin>; 471 pinctrl-2 = <&otp_pin>;
476 #thermal-sensor-cells = <1>; 472 #thermal-sensor-cells = <1>;
477 rockchip,hw-tshut-temp = <9500 473 rockchip,hw-tshut-temp = <95000>;
478 status = "disabled"; 474 status = "disabled";
479 }; 475 };
480 476
481 gmac: ethernet@ff290000 { 477 gmac: ethernet@ff290000 {
482 compatible = "rockchip,rk3368- 478 compatible = "rockchip,rk3368-gmac";
483 reg = <0x0 0xff290000 0x0 0x10 479 reg = <0x0 0xff290000 0x0 0x10000>;
484 interrupts = <GIC_SPI 27 IRQ_T 480 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
485 interrupt-names = "macirq"; 481 interrupt-names = "macirq";
486 rockchip,grf = <&grf>; 482 rockchip,grf = <&grf>;
487 clocks = <&cru SCLK_MAC>, 483 clocks = <&cru SCLK_MAC>,
488 <&cru SCLK_MAC_RX>, <& 484 <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>,
489 <&cru SCLK_MACREF>, <& 485 <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>,
490 <&cru ACLK_GMAC>, <&cr 486 <&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
491 clock-names = "stmmaceth", 487 clock-names = "stmmaceth",
492 "mac_clk_rx", "mac_clk 488 "mac_clk_rx", "mac_clk_tx",
493 "clk_mac_ref", "clk_ma 489 "clk_mac_ref", "clk_mac_refout",
494 "aclk_mac", "pclk_mac" 490 "aclk_mac", "pclk_mac";
495 status = "disabled"; 491 status = "disabled";
496 }; 492 };
497 493
498 usb_host0_ehci: usb@ff500000 { 494 usb_host0_ehci: usb@ff500000 {
499 compatible = "generic-ehci"; 495 compatible = "generic-ehci";
500 reg = <0x0 0xff500000 0x0 0x10 496 reg = <0x0 0xff500000 0x0 0x100>;
501 interrupts = <GIC_SPI 24 IRQ_T 497 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
502 clocks = <&cru HCLK_HOST0>; 498 clocks = <&cru HCLK_HOST0>;
503 status = "disabled"; 499 status = "disabled";
504 }; 500 };
505 501
506 usb_otg: usb@ff580000 { 502 usb_otg: usb@ff580000 {
507 compatible = "rockchip,rk3368- 503 compatible = "rockchip,rk3368-usb", "rockchip,rk3066-usb",
508 "snps,dwc2"; 504 "snps,dwc2";
509 reg = <0x0 0xff580000 0x0 0x40 505 reg = <0x0 0xff580000 0x0 0x40000>;
510 interrupts = <GIC_SPI 23 IRQ_T 506 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
511 clocks = <&cru HCLK_OTG0>; 507 clocks = <&cru HCLK_OTG0>;
512 clock-names = "otg"; 508 clock-names = "otg";
513 dr_mode = "otg"; 509 dr_mode = "otg";
514 g-np-tx-fifo-size = <16>; 510 g-np-tx-fifo-size = <16>;
515 g-rx-fifo-size = <275>; 511 g-rx-fifo-size = <275>;
516 g-tx-fifo-size = <256 128 128 512 g-tx-fifo-size = <256 128 128 64 64 32>;
517 status = "disabled"; 513 status = "disabled";
518 }; 514 };
519 515
520 dmac_bus: dma-controller@ff600000 { 516 dmac_bus: dma-controller@ff600000 {
521 compatible = "arm,pl330", "arm 517 compatible = "arm,pl330", "arm,primecell";
522 reg = <0x0 0xff600000 0x0 0x40 518 reg = <0x0 0xff600000 0x0 0x4000>;
523 interrupts = <GIC_SPI 0 IRQ_TY 519 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
524 <GIC_SPI 1 IRQ_TY 520 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
525 #dma-cells = <1>; 521 #dma-cells = <1>;
526 arm,pl330-broken-no-flushp; 522 arm,pl330-broken-no-flushp;
527 arm,pl330-periph-burst; 523 arm,pl330-periph-burst;
528 clocks = <&cru ACLK_DMAC_BUS>; 524 clocks = <&cru ACLK_DMAC_BUS>;
529 clock-names = "apb_pclk"; 525 clock-names = "apb_pclk";
530 }; 526 };
531 527
532 i2c0: i2c@ff650000 { 528 i2c0: i2c@ff650000 {
533 compatible = "rockchip,rk3368- 529 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
534 reg = <0x0 0xff650000 0x0 0x10 530 reg = <0x0 0xff650000 0x0 0x1000>;
535 clocks = <&cru PCLK_I2C0>; 531 clocks = <&cru PCLK_I2C0>;
536 clock-names = "i2c"; 532 clock-names = "i2c";
537 interrupts = <GIC_SPI 60 IRQ_T 533 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
538 pinctrl-names = "default"; 534 pinctrl-names = "default";
539 pinctrl-0 = <&i2c0_xfer>; 535 pinctrl-0 = <&i2c0_xfer>;
540 #address-cells = <1>; 536 #address-cells = <1>;
541 #size-cells = <0>; 537 #size-cells = <0>;
542 status = "disabled"; 538 status = "disabled";
543 }; 539 };
544 540
545 i2c1: i2c@ff660000 { 541 i2c1: i2c@ff660000 {
546 compatible = "rockchip,rk3368- 542 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
547 reg = <0x0 0xff660000 0x0 0x10 543 reg = <0x0 0xff660000 0x0 0x1000>;
548 interrupts = <GIC_SPI 61 IRQ_T 544 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
549 #address-cells = <1>; 545 #address-cells = <1>;
550 #size-cells = <0>; 546 #size-cells = <0>;
551 clock-names = "i2c"; 547 clock-names = "i2c";
552 clocks = <&cru PCLK_I2C1>; 548 clocks = <&cru PCLK_I2C1>;
553 pinctrl-names = "default"; 549 pinctrl-names = "default";
554 pinctrl-0 = <&i2c1_xfer>; 550 pinctrl-0 = <&i2c1_xfer>;
555 status = "disabled"; 551 status = "disabled";
556 }; 552 };
557 553
558 pwm0: pwm@ff680000 { 554 pwm0: pwm@ff680000 {
559 compatible = "rockchip,rk3368- 555 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
560 reg = <0x0 0xff680000 0x0 0x10 556 reg = <0x0 0xff680000 0x0 0x10>;
561 #pwm-cells = <3>; 557 #pwm-cells = <3>;
562 pinctrl-names = "default"; 558 pinctrl-names = "default";
563 pinctrl-0 = <&pwm0_pin>; 559 pinctrl-0 = <&pwm0_pin>;
564 clocks = <&cru PCLK_PWM1>; 560 clocks = <&cru PCLK_PWM1>;
565 status = "disabled"; 561 status = "disabled";
566 }; 562 };
567 563
568 pwm1: pwm@ff680010 { 564 pwm1: pwm@ff680010 {
569 compatible = "rockchip,rk3368- 565 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
570 reg = <0x0 0xff680010 0x0 0x10 566 reg = <0x0 0xff680010 0x0 0x10>;
571 #pwm-cells = <3>; 567 #pwm-cells = <3>;
572 pinctrl-names = "default"; 568 pinctrl-names = "default";
573 pinctrl-0 = <&pwm1_pin>; 569 pinctrl-0 = <&pwm1_pin>;
574 clocks = <&cru PCLK_PWM1>; 570 clocks = <&cru PCLK_PWM1>;
575 status = "disabled"; 571 status = "disabled";
576 }; 572 };
577 573
578 pwm2: pwm@ff680020 { 574 pwm2: pwm@ff680020 {
579 compatible = "rockchip,rk3368- 575 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
580 reg = <0x0 0xff680020 0x0 0x10 576 reg = <0x0 0xff680020 0x0 0x10>;
581 #pwm-cells = <3>; 577 #pwm-cells = <3>;
582 clocks = <&cru PCLK_PWM1>; 578 clocks = <&cru PCLK_PWM1>;
583 status = "disabled"; 579 status = "disabled";
584 }; 580 };
585 581
586 pwm3: pwm@ff680030 { 582 pwm3: pwm@ff680030 {
587 compatible = "rockchip,rk3368- 583 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
588 reg = <0x0 0xff680030 0x0 0x10 584 reg = <0x0 0xff680030 0x0 0x10>;
589 #pwm-cells = <3>; 585 #pwm-cells = <3>;
590 pinctrl-names = "default"; 586 pinctrl-names = "default";
591 pinctrl-0 = <&pwm3_pin>; 587 pinctrl-0 = <&pwm3_pin>;
592 clocks = <&cru PCLK_PWM1>; 588 clocks = <&cru PCLK_PWM1>;
593 status = "disabled"; 589 status = "disabled";
594 }; 590 };
595 591
596 uart2: serial@ff690000 { 592 uart2: serial@ff690000 {
597 compatible = "rockchip,rk3368- 593 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
598 reg = <0x0 0xff690000 0x0 0x10 594 reg = <0x0 0xff690000 0x0 0x100>;
599 clocks = <&cru SCLK_UART2>, <& 595 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
600 clock-names = "baudclk", "apb_ 596 clock-names = "baudclk", "apb_pclk";
601 interrupts = <GIC_SPI 57 IRQ_T 597 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
602 pinctrl-names = "default"; 598 pinctrl-names = "default";
603 pinctrl-0 = <&uart2_xfer>; 599 pinctrl-0 = <&uart2_xfer>;
604 reg-shift = <2>; 600 reg-shift = <2>;
605 reg-io-width = <4>; 601 reg-io-width = <4>;
606 status = "disabled"; 602 status = "disabled";
607 }; 603 };
608 604
609 mbox: mbox@ff6b0000 { 605 mbox: mbox@ff6b0000 {
610 compatible = "rockchip,rk3368- 606 compatible = "rockchip,rk3368-mailbox";
611 reg = <0x0 0xff6b0000 0x0 0x10 607 reg = <0x0 0xff6b0000 0x0 0x1000>;
612 interrupts = <GIC_SPI 146 IRQ_ 608 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
613 <GIC_SPI 147 IRQ_ 609 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
614 <GIC_SPI 148 IRQ_ 610 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
615 <GIC_SPI 149 IRQ_ 611 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
616 clocks = <&cru PCLK_MAILBOX>; 612 clocks = <&cru PCLK_MAILBOX>;
617 clock-names = "pclk_mailbox"; 613 clock-names = "pclk_mailbox";
618 #mbox-cells = <1>; 614 #mbox-cells = <1>;
619 status = "disabled"; 615 status = "disabled";
620 }; 616 };
621 617
622 pmu: power-management@ff730000 { <<
623 compatible = "rockchip,rk3368- <<
624 reg = <0x0 0xff730000 0x0 0x10 <<
625 <<
626 power: power-controller { <<
627 compatible = "rockchip <<
628 #power-domain-cells = <<
629 #address-cells = <1>; <<
630 #size-cells = <0>; <<
631 <<
632 /* <<
633 * Note: Although SCLK <<
634 * of device without i <<
635 * synchronous reset. <<
636 * <<
637 * The clocks on the w <<
638 * ACLK_IEP/ACLK_VIP/A <<
639 * ACLK_ISP/ACLK_VOP1 <<
640 * ACLK_RGA is on ACLK <<
641 * The others (HCLK_*, <<
642 * <<
643 * Which clock are dev <<
644 * clocks <<
645 * *_IEP <<
646 * *_ISP <<
647 * *_VIP <<
648 * *_VOP* <<
649 * *_RGA <<
650 * *_EDP* <<
651 * *_DPHY* <<
652 * *_HDMI <<
653 * *_MIPI_* <<
654 */ <<
655 power-domain@RK3368_PD <<
656 reg = <RK3368_ <<
657 clocks = <&cru <<
658 <&cru <<
659 <&cru <<
660 <&cru <<
661 <&cru <<
662 <&cru <<
663 <&cru <<
664 <&cru <<
665 <&cru <<
666 <&cru <<
667 <&cru <<
668 <&cru <<
669 <&cru <<
670 <&cru <<
671 <&cru <<
672 <&cru <<
673 <&cru <<
674 <&cru <<
675 <&cru <<
676 <&cru <<
677 <&cru <<
678 <&cru <<
679 <&cru <<
680 <&cru <<
681 <&cru <<
682 <&cru <<
683 <&cru <<
684 <&cru <<
685 <&cru <<
686 <&cru <<
687 pm_qos = <&qos <<
688 <&qos <<
689 <&qos <<
690 <&qos <<
691 <&qos <<
692 <&qos <<
693 <&qos <<
694 <&qos <<
695 <&qos <<
696 #power-domain- <<
697 }; <<
698 <<
699 /* <<
700 * Note: ACLK_VCODEC/H <<
701 * (video endecoder & <<
702 * ACLK_VCODEC_NIU and <<
703 */ <<
704 power-domain@RK3368_PD <<
705 reg = <RK3368_ <<
706 clocks = <&cru <<
707 <&cru <<
708 <&cru <<
709 <&cru <<
710 pm_qos = <&qos <<
711 <&qos <<
712 <&qos <<
713 #power-domain- <<
714 }; <<
715 <<
716 /* <<
717 * Note: ACLK_GPU is t <<
718 * and on the ACLK_GPU <<
719 */ <<
720 power-domain@RK3368_PD <<
721 reg = <RK3368_ <<
722 clocks = <&cru <<
723 <&cru <<
724 <&cru <<
725 pm_qos = <&qos <<
726 #power-domain- <<
727 }; <<
728 }; <<
729 }; <<
730 <<
731 pmugrf: syscon@ff738000 { 618 pmugrf: syscon@ff738000 {
732 compatible = "rockchip,rk3368- 619 compatible = "rockchip,rk3368-pmugrf", "syscon", "simple-mfd";
733 reg = <0x0 0xff738000 0x0 0x10 620 reg = <0x0 0xff738000 0x0 0x1000>;
734 621
735 pmu_io_domains: io-domains { 622 pmu_io_domains: io-domains {
736 compatible = "rockchip 623 compatible = "rockchip,rk3368-pmu-io-voltage-domain";
737 status = "disabled"; 624 status = "disabled";
738 }; 625 };
739 626
740 reboot-mode { 627 reboot-mode {
741 compatible = "syscon-r 628 compatible = "syscon-reboot-mode";
742 offset = <0x200>; 629 offset = <0x200>;
743 mode-normal = <BOOT_NO 630 mode-normal = <BOOT_NORMAL>;
744 mode-recovery = <BOOT_ 631 mode-recovery = <BOOT_RECOVERY>;
745 mode-bootloader = <BOO 632 mode-bootloader = <BOOT_FASTBOOT>;
746 mode-loader = <BOOT_BL 633 mode-loader = <BOOT_BL_DOWNLOAD>;
747 }; 634 };
748 }; 635 };
749 636
750 cru: clock-controller@ff760000 { 637 cru: clock-controller@ff760000 {
751 compatible = "rockchip,rk3368- 638 compatible = "rockchip,rk3368-cru";
752 reg = <0x0 0xff760000 0x0 0x10 639 reg = <0x0 0xff760000 0x0 0x1000>;
753 clocks = <&xin24m>; <<
754 clock-names = "xin24m"; <<
755 rockchip,grf = <&grf>; 640 rockchip,grf = <&grf>;
756 #clock-cells = <1>; 641 #clock-cells = <1>;
757 #reset-cells = <1>; 642 #reset-cells = <1>;
758 }; 643 };
759 644
760 grf: syscon@ff770000 { 645 grf: syscon@ff770000 {
761 compatible = "rockchip,rk3368- 646 compatible = "rockchip,rk3368-grf", "syscon", "simple-mfd";
762 reg = <0x0 0xff770000 0x0 0x10 647 reg = <0x0 0xff770000 0x0 0x1000>;
763 648
764 io_domains: io-domains { 649 io_domains: io-domains {
765 compatible = "rockchip 650 compatible = "rockchip,rk3368-io-voltage-domain";
766 status = "disabled"; 651 status = "disabled";
767 }; 652 };
768 }; 653 };
769 654
770 wdt: watchdog@ff800000 { 655 wdt: watchdog@ff800000 {
771 compatible = "rockchip,rk3368- 656 compatible = "rockchip,rk3368-wdt", "snps,dw-wdt";
772 reg = <0x0 0xff800000 0x0 0x10 657 reg = <0x0 0xff800000 0x0 0x100>;
773 clocks = <&cru PCLK_WDT>; 658 clocks = <&cru PCLK_WDT>;
774 interrupts = <GIC_SPI 79 IRQ_T 659 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
775 status = "disabled"; 660 status = "disabled";
776 }; 661 };
777 662
778 timer0: timer@ff810000 { 663 timer0: timer@ff810000 {
779 compatible = "rockchip,rk3368- 664 compatible = "rockchip,rk3368-timer", "rockchip,rk3288-timer";
780 reg = <0x0 0xff810000 0x0 0x20 665 reg = <0x0 0xff810000 0x0 0x20>;
781 interrupts = <GIC_SPI 66 IRQ_T 666 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
782 clocks = <&cru PCLK_TIMER0>, < <<
783 clock-names = "pclk", "timer"; <<
784 }; 667 };
785 668
786 spdif: spdif@ff880000 { 669 spdif: spdif@ff880000 {
787 compatible = "rockchip,rk3368- 670 compatible = "rockchip,rk3368-spdif";
788 reg = <0x0 0xff880000 0x0 0x10 671 reg = <0x0 0xff880000 0x0 0x1000>;
789 interrupts = <GIC_SPI 54 IRQ_T 672 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
790 clocks = <&cru SCLK_SPDIF_8CH> 673 clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>;
791 clock-names = "mclk", "hclk"; 674 clock-names = "mclk", "hclk";
792 dmas = <&dmac_bus 3>; 675 dmas = <&dmac_bus 3>;
793 dma-names = "tx"; 676 dma-names = "tx";
794 pinctrl-names = "default"; 677 pinctrl-names = "default";
795 pinctrl-0 = <&spdif_tx>; 678 pinctrl-0 = <&spdif_tx>;
796 #sound-dai-cells = <0>; <<
797 status = "disabled"; 679 status = "disabled";
798 }; 680 };
799 681
800 i2s_2ch: i2s-2ch@ff890000 { 682 i2s_2ch: i2s-2ch@ff890000 {
801 compatible = "rockchip,rk3368- 683 compatible = "rockchip,rk3368-i2s", "rockchip,rk3066-i2s";
802 reg = <0x0 0xff890000 0x0 0x10 684 reg = <0x0 0xff890000 0x0 0x1000>;
803 interrupts = <GIC_SPI 40 IRQ_T 685 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
804 clock-names = "i2s_clk", "i2s_ 686 clock-names = "i2s_clk", "i2s_hclk";
805 clocks = <&cru SCLK_I2S_2CH>, 687 clocks = <&cru SCLK_I2S_2CH>, <&cru HCLK_I2S_2CH>;
806 dmas = <&dmac_bus 6>, <&dmac_b 688 dmas = <&dmac_bus 6>, <&dmac_bus 7>;
807 dma-names = "tx", "rx"; 689 dma-names = "tx", "rx";
808 #sound-dai-cells = <0>; <<
809 status = "disabled"; 690 status = "disabled";
810 }; 691 };
811 692
812 i2s_8ch: i2s-8ch@ff898000 { 693 i2s_8ch: i2s-8ch@ff898000 {
813 compatible = "rockchip,rk3368- 694 compatible = "rockchip,rk3368-i2s", "rockchip,rk3066-i2s";
814 reg = <0x0 0xff898000 0x0 0x10 695 reg = <0x0 0xff898000 0x0 0x1000>;
815 interrupts = <GIC_SPI 53 IRQ_T 696 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
816 clock-names = "i2s_clk", "i2s_ 697 clock-names = "i2s_clk", "i2s_hclk";
817 clocks = <&cru SCLK_I2S_8CH>, 698 clocks = <&cru SCLK_I2S_8CH>, <&cru HCLK_I2S_8CH>;
818 dmas = <&dmac_bus 0>, <&dmac_b 699 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
819 dma-names = "tx", "rx"; 700 dma-names = "tx", "rx";
820 pinctrl-names = "default"; 701 pinctrl-names = "default";
821 pinctrl-0 = <&i2s_8ch_bus>; 702 pinctrl-0 = <&i2s_8ch_bus>;
822 #sound-dai-cells = <0>; <<
823 status = "disabled"; 703 status = "disabled";
824 }; 704 };
825 705
826 iep_mmu: iommu@ff900800 { 706 iep_mmu: iommu@ff900800 {
827 compatible = "rockchip,iommu"; 707 compatible = "rockchip,iommu";
828 reg = <0x0 0xff900800 0x0 0x10 708 reg = <0x0 0xff900800 0x0 0x100>;
829 interrupts = <GIC_SPI 17 IRQ_T 709 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
>> 710 interrupt-names = "iep_mmu";
830 clocks = <&cru ACLK_IEP>, <&cr 711 clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
831 clock-names = "aclk", "iface"; 712 clock-names = "aclk", "iface";
832 power-domains = <&power RK3368 <<
833 #iommu-cells = <0>; 713 #iommu-cells = <0>;
834 status = "disabled"; 714 status = "disabled";
835 }; 715 };
836 716
837 isp_mmu: iommu@ff914000 { 717 isp_mmu: iommu@ff914000 {
838 compatible = "rockchip,iommu"; 718 compatible = "rockchip,iommu";
839 reg = <0x0 0xff914000 0x0 0x10 719 reg = <0x0 0xff914000 0x0 0x100>,
840 <0x0 0xff915000 0x0 0x10 720 <0x0 0xff915000 0x0 0x100>;
841 interrupts = <GIC_SPI 14 IRQ_T 721 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
>> 722 interrupt-names = "isp_mmu";
842 clocks = <&cru ACLK_ISP>, <&cr 723 clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>;
843 clock-names = "aclk", "iface"; 724 clock-names = "aclk", "iface";
844 #iommu-cells = <0>; 725 #iommu-cells = <0>;
845 power-domains = <&power RK3368 <<
846 rockchip,disable-mmu-reset; 726 rockchip,disable-mmu-reset;
847 status = "disabled"; 727 status = "disabled";
848 }; 728 };
849 729
850 vop_mmu: iommu@ff930300 { 730 vop_mmu: iommu@ff930300 {
851 compatible = "rockchip,iommu"; 731 compatible = "rockchip,iommu";
852 reg = <0x0 0xff930300 0x0 0x10 732 reg = <0x0 0xff930300 0x0 0x100>;
853 interrupts = <GIC_SPI 15 IRQ_T 733 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
>> 734 interrupt-names = "vop_mmu";
854 clocks = <&cru ACLK_VOP>, <&cr 735 clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
855 clock-names = "aclk", "iface"; 736 clock-names = "aclk", "iface";
856 power-domains = <&power RK3368 <<
857 #iommu-cells = <0>; 737 #iommu-cells = <0>;
858 status = "disabled"; 738 status = "disabled";
859 }; 739 };
860 740
861 hevc_mmu: iommu@ff9a0440 { 741 hevc_mmu: iommu@ff9a0440 {
862 compatible = "rockchip,iommu"; 742 compatible = "rockchip,iommu";
863 reg = <0x0 0xff9a0440 0x0 0x40 743 reg = <0x0 0xff9a0440 0x0 0x40>,
864 <0x0 0xff9a0480 0x0 0x40 744 <0x0 0xff9a0480 0x0 0x40>;
865 interrupts = <GIC_SPI 12 IRQ_T 745 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
>> 746 interrupt-names = "hevc_mmu";
866 clocks = <&cru ACLK_VIDEO>, <& 747 clocks = <&cru ACLK_VIDEO>, <&cru HCLK_VIDEO>;
867 clock-names = "aclk", "iface"; 748 clock-names = "aclk", "iface";
868 #iommu-cells = <0>; 749 #iommu-cells = <0>;
869 status = "disabled"; 750 status = "disabled";
870 }; 751 };
871 752
872 vpu_mmu: iommu@ff9a0800 { 753 vpu_mmu: iommu@ff9a0800 {
873 compatible = "rockchip,iommu"; 754 compatible = "rockchip,iommu";
874 reg = <0x0 0xff9a0800 0x0 0x10 755 reg = <0x0 0xff9a0800 0x0 0x100>;
875 interrupts = <GIC_SPI 9 IRQ_TY 756 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
876 <GIC_SPI 10 IRQ_T 757 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
>> 758 interrupt-names = "vepu_mmu", "vdpu_mmu";
877 clocks = <&cru ACLK_VIDEO>, <& 759 clocks = <&cru ACLK_VIDEO>, <&cru HCLK_VIDEO>;
878 clock-names = "aclk", "iface"; 760 clock-names = "aclk", "iface";
879 #iommu-cells = <0>; 761 #iommu-cells = <0>;
880 status = "disabled"; 762 status = "disabled";
881 }; 763 };
882 764
883 qos_iep: qos@ffad0000 { <<
884 compatible = "rockchip,rk3368- <<
885 reg = <0x0 0xffad0000 0x0 0x20 <<
886 }; <<
887 <<
888 qos_isp_r0: qos@ffad0080 { <<
889 compatible = "rockchip,rk3368- <<
890 reg = <0x0 0xffad0080 0x0 0x20 <<
891 }; <<
892 <<
893 qos_isp_r1: qos@ffad0100 { <<
894 compatible = "rockchip,rk3368- <<
895 reg = <0x0 0xffad0100 0x0 0x20 <<
896 }; <<
897 <<
898 qos_isp_w0: qos@ffad0180 { <<
899 compatible = "rockchip,rk3368- <<
900 reg = <0x0 0xffad0180 0x0 0x20 <<
901 }; <<
902 <<
903 qos_isp_w1: qos@ffad0200 { <<
904 compatible = "rockchip,rk3368- <<
905 reg = <0x0 0xffad0200 0x0 0x20 <<
906 }; <<
907 <<
908 qos_vip: qos@ffad0280 { <<
909 compatible = "rockchip,rk3368- <<
910 reg = <0x0 0xffad0280 0x0 0x20 <<
911 }; <<
912 <<
913 qos_vop: qos@ffad0300 { <<
914 compatible = "rockchip,rk3368- <<
915 reg = <0x0 0xffad0300 0x0 0x20 <<
916 }; <<
917 <<
918 qos_rga_r: qos@ffad0380 { <<
919 compatible = "rockchip,rk3368- <<
920 reg = <0x0 0xffad0380 0x0 0x20 <<
921 }; <<
922 <<
923 qos_rga_w: qos@ffad0400 { <<
924 compatible = "rockchip,rk3368- <<
925 reg = <0x0 0xffad0400 0x0 0x20 <<
926 }; <<
927 <<
928 qos_hevc_r: qos@ffae0000 { <<
929 compatible = "rockchip,rk3368- <<
930 reg = <0x0 0xffae0000 0x0 0x20 <<
931 }; <<
932 <<
933 qos_vpu_r: qos@ffae0100 { <<
934 compatible = "rockchip,rk3368- <<
935 reg = <0x0 0xffae0100 0x0 0x20 <<
936 }; <<
937 <<
938 qos_vpu_w: qos@ffae0180 { <<
939 compatible = "rockchip,rk3368- <<
940 reg = <0x0 0xffae0180 0x0 0x20 <<
941 }; <<
942 <<
943 qos_gpu: qos@ffaf0000 { <<
944 compatible = "rockchip,rk3368- <<
945 reg = <0x0 0xffaf0000 0x0 0x20 <<
946 }; <<
947 <<
948 efuse256: efuse@ffb00000 { 765 efuse256: efuse@ffb00000 {
949 compatible = "rockchip,rk3368- 766 compatible = "rockchip,rk3368-efuse";
950 reg = <0x0 0xffb00000 0x0 0x20 767 reg = <0x0 0xffb00000 0x0 0x20>;
951 #address-cells = <1>; 768 #address-cells = <1>;
952 #size-cells = <1>; 769 #size-cells = <1>;
953 clocks = <&cru PCLK_EFUSE256>; 770 clocks = <&cru PCLK_EFUSE256>;
954 clock-names = "pclk_efuse"; 771 clock-names = "pclk_efuse";
955 772
956 cpu_leakage: cpu-leakage@17 { 773 cpu_leakage: cpu-leakage@17 {
957 reg = <0x17 0x1>; 774 reg = <0x17 0x1>;
958 }; 775 };
959 temp_adjust: temp-adjust@1f { 776 temp_adjust: temp-adjust@1f {
960 reg = <0x1f 0x1>; 777 reg = <0x1f 0x1>;
961 }; 778 };
962 }; 779 };
963 780
964 gic: interrupt-controller@ffb71000 { 781 gic: interrupt-controller@ffb71000 {
965 compatible = "arm,gic-400"; 782 compatible = "arm,gic-400";
966 interrupt-controller; 783 interrupt-controller;
967 #interrupt-cells = <3>; 784 #interrupt-cells = <3>;
968 #address-cells = <0>; 785 #address-cells = <0>;
969 786
970 reg = <0x0 0xffb71000 0x0 0x10 787 reg = <0x0 0xffb71000 0x0 0x1000>,
971 <0x0 0xffb72000 0x0 0x20 788 <0x0 0xffb72000 0x0 0x2000>,
972 <0x0 0xffb74000 0x0 0x20 789 <0x0 0xffb74000 0x0 0x2000>,
973 <0x0 0xffb76000 0x0 0x20 790 <0x0 0xffb76000 0x0 0x2000>;
974 interrupts = <GIC_PPI 9 791 interrupts = <GIC_PPI 9
975 (GIC_CPU_MASK_SIMPLE(8) 792 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
976 }; 793 };
977 794
978 pinctrl: pinctrl { 795 pinctrl: pinctrl {
979 compatible = "rockchip,rk3368- 796 compatible = "rockchip,rk3368-pinctrl";
980 rockchip,grf = <&grf>; 797 rockchip,grf = <&grf>;
981 rockchip,pmu = <&pmugrf>; 798 rockchip,pmu = <&pmugrf>;
982 #address-cells = <0x2>; 799 #address-cells = <0x2>;
983 #size-cells = <0x2>; 800 #size-cells = <0x2>;
984 ranges; 801 ranges;
985 802
986 gpio0: gpio@ff750000 { !! 803 gpio0: gpio0@ff750000 {
987 compatible = "rockchip 804 compatible = "rockchip,gpio-bank";
988 reg = <0x0 0xff750000 805 reg = <0x0 0xff750000 0x0 0x100>;
989 clocks = <&cru PCLK_GP 806 clocks = <&cru PCLK_GPIO0>;
990 interrupts = <GIC_SPI 807 interrupts = <GIC_SPI 0x51 IRQ_TYPE_LEVEL_HIGH>;
991 808
992 gpio-controller; 809 gpio-controller;
993 #gpio-cells = <0x2>; 810 #gpio-cells = <0x2>;
994 811
995 interrupt-controller; 812 interrupt-controller;
996 #interrupt-cells = <0x 813 #interrupt-cells = <0x2>;
997 }; 814 };
998 815
999 gpio1: gpio@ff780000 { !! 816 gpio1: gpio1@ff780000 {
1000 compatible = "rockchi 817 compatible = "rockchip,gpio-bank";
1001 reg = <0x0 0xff780000 818 reg = <0x0 0xff780000 0x0 0x100>;
1002 clocks = <&cru PCLK_G 819 clocks = <&cru PCLK_GPIO1>;
1003 interrupts = <GIC_SPI 820 interrupts = <GIC_SPI 0x52 IRQ_TYPE_LEVEL_HIGH>;
1004 821
1005 gpio-controller; 822 gpio-controller;
1006 #gpio-cells = <0x2>; 823 #gpio-cells = <0x2>;
1007 824
1008 interrupt-controller; 825 interrupt-controller;
1009 #interrupt-cells = <0 826 #interrupt-cells = <0x2>;
1010 }; 827 };
1011 828
1012 gpio2: gpio@ff790000 { !! 829 gpio2: gpio2@ff790000 {
1013 compatible = "rockchi 830 compatible = "rockchip,gpio-bank";
1014 reg = <0x0 0xff790000 831 reg = <0x0 0xff790000 0x0 0x100>;
1015 clocks = <&cru PCLK_G 832 clocks = <&cru PCLK_GPIO2>;
1016 interrupts = <GIC_SPI 833 interrupts = <GIC_SPI 0x53 IRQ_TYPE_LEVEL_HIGH>;
1017 834
1018 gpio-controller; 835 gpio-controller;
1019 #gpio-cells = <0x2>; 836 #gpio-cells = <0x2>;
1020 837
1021 interrupt-controller; 838 interrupt-controller;
1022 #interrupt-cells = <0 839 #interrupt-cells = <0x2>;
1023 }; 840 };
1024 841
1025 gpio3: gpio@ff7a0000 { !! 842 gpio3: gpio3@ff7a0000 {
1026 compatible = "rockchi 843 compatible = "rockchip,gpio-bank";
1027 reg = <0x0 0xff7a0000 844 reg = <0x0 0xff7a0000 0x0 0x100>;
1028 clocks = <&cru PCLK_G 845 clocks = <&cru PCLK_GPIO3>;
1029 interrupts = <GIC_SPI 846 interrupts = <GIC_SPI 0x54 IRQ_TYPE_LEVEL_HIGH>;
1030 847
1031 gpio-controller; 848 gpio-controller;
1032 #gpio-cells = <0x2>; 849 #gpio-cells = <0x2>;
1033 850
1034 interrupt-controller; 851 interrupt-controller;
1035 #interrupt-cells = <0 852 #interrupt-cells = <0x2>;
1036 }; 853 };
1037 854
1038 pcfg_pull_up: pcfg-pull-up { 855 pcfg_pull_up: pcfg-pull-up {
1039 bias-pull-up; 856 bias-pull-up;
1040 }; 857 };
1041 858
1042 pcfg_pull_down: pcfg-pull-dow 859 pcfg_pull_down: pcfg-pull-down {
1043 bias-pull-down; 860 bias-pull-down;
1044 }; 861 };
1045 862
1046 pcfg_pull_none: pcfg-pull-non 863 pcfg_pull_none: pcfg-pull-none {
1047 bias-disable; 864 bias-disable;
1048 }; 865 };
1049 866
1050 pcfg_pull_none_12ma: pcfg-pul 867 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1051 bias-disable; 868 bias-disable;
1052 drive-strength = <12> 869 drive-strength = <12>;
1053 }; 870 };
1054 871
1055 emmc { 872 emmc {
1056 emmc_clk: emmc-clk { 873 emmc_clk: emmc-clk {
1057 rockchip,pins 874 rockchip,pins = <2 RK_PA4 2 &pcfg_pull_none>;
1058 }; 875 };
1059 876
1060 emmc_cmd: emmc-cmd { 877 emmc_cmd: emmc-cmd {
1061 rockchip,pins 878 rockchip,pins = <1 RK_PD2 2 &pcfg_pull_up>;
1062 }; 879 };
1063 880
1064 emmc_pwr: emmc-pwr { 881 emmc_pwr: emmc-pwr {
1065 rockchip,pins 882 rockchip,pins = <1 RK_PD3 2 &pcfg_pull_up>;
1066 }; 883 };
1067 884
1068 emmc_bus1: emmc-bus1 885 emmc_bus1: emmc-bus1 {
1069 rockchip,pins 886 rockchip,pins = <1 RK_PC2 2 &pcfg_pull_up>;
1070 }; 887 };
1071 888
1072 emmc_bus4: emmc-bus4 889 emmc_bus4: emmc-bus4 {
1073 rockchip,pins 890 rockchip,pins = <1 RK_PC2 2 &pcfg_pull_up>,
1074 891 <1 RK_PC3 2 &pcfg_pull_up>,
1075 892 <1 RK_PC4 2 &pcfg_pull_up>,
1076 893 <1 RK_PC5 2 &pcfg_pull_up>;
1077 }; 894 };
1078 895
1079 emmc_bus8: emmc-bus8 896 emmc_bus8: emmc-bus8 {
1080 rockchip,pins 897 rockchip,pins = <1 RK_PC2 2 &pcfg_pull_up>,
1081 898 <1 RK_PC3 2 &pcfg_pull_up>,
1082 899 <1 RK_PC4 2 &pcfg_pull_up>,
1083 900 <1 RK_PC5 2 &pcfg_pull_up>,
1084 901 <1 RK_PC6 2 &pcfg_pull_up>,
1085 902 <1 RK_PC7 2 &pcfg_pull_up>,
1086 903 <1 RK_PD0 2 &pcfg_pull_up>,
1087 904 <1 RK_PD1 2 &pcfg_pull_up>;
1088 }; 905 };
1089 }; 906 };
1090 907
1091 gmac { 908 gmac {
1092 rgmii_pins: rgmii-pin 909 rgmii_pins: rgmii-pins {
1093 rockchip,pins !! 910 rockchip,pins = <3 RK_PC6 1 &pcfg_pull_none>,
1094 911 <3 RK_PD0 1 &pcfg_pull_none>,
1095 912 <3 RK_PC3 1 &pcfg_pull_none>,
1096 913 <3 RK_PB0 1 &pcfg_pull_none_12ma>,
1097 914 <3 RK_PB1 1 &pcfg_pull_none_12ma>,
1098 915 <3 RK_PB2 1 &pcfg_pull_none_12ma>,
1099 916 <3 RK_PB6 1 &pcfg_pull_none_12ma>,
1100 917 <3 RK_PD4 1 &pcfg_pull_none_12ma>,
1101 918 <3 RK_PB5 1 &pcfg_pull_none_12ma>,
1102 919 <3 RK_PB7 1 &pcfg_pull_none>,
1103 920 <3 RK_PC0 1 &pcfg_pull_none>,
1104 921 <3 RK_PC1 1 &pcfg_pull_none>,
1105 922 <3 RK_PC2 1 &pcfg_pull_none>,
1106 923 <3 RK_PD1 1 &pcfg_pull_none>,
1107 924 <3 RK_PC4 1 &pcfg_pull_none>;
1108 }; 925 };
1109 926
1110 rmii_pins: rmii-pins 927 rmii_pins: rmii-pins {
1111 rockchip,pins !! 928 rockchip,pins = <3 RK_PC6 1 &pcfg_pull_none>,
1112 929 <3 RK_PD0 1 &pcfg_pull_none>,
1113 930 <3 RK_PC3 1 &pcfg_pull_none>,
1114 931 <3 RK_PB0 1 &pcfg_pull_none_12ma>,
1115 932 <3 RK_PB1 1 &pcfg_pull_none_12ma>,
1116 933 <3 RK_PB5 1 &pcfg_pull_none_12ma>,
1117 934 <3 RK_PB7 1 &pcfg_pull_none>,
1118 935 <3 RK_PC0 1 &pcfg_pull_none>,
1119 936 <3 RK_PC4 1 &pcfg_pull_none>,
1120 937 <3 RK_PC5 1 &pcfg_pull_none>;
1121 }; 938 };
1122 }; 939 };
1123 940
1124 i2c0 { 941 i2c0 {
1125 i2c0_xfer: i2c0-xfer 942 i2c0_xfer: i2c0-xfer {
1126 rockchip,pins 943 rockchip,pins = <0 RK_PA6 1 &pcfg_pull_none>,
1127 944 <0 RK_PA7 1 &pcfg_pull_none>;
1128 }; 945 };
1129 }; 946 };
1130 947
1131 i2c1 { 948 i2c1 {
1132 i2c1_xfer: i2c1-xfer 949 i2c1_xfer: i2c1-xfer {
1133 rockchip,pins 950 rockchip,pins = <2 RK_PC5 1 &pcfg_pull_none>,
1134 951 <2 RK_PC6 1 &pcfg_pull_none>;
1135 }; 952 };
1136 }; 953 };
1137 954
1138 i2c2 { 955 i2c2 {
1139 i2c2_xfer: i2c2-xfer 956 i2c2_xfer: i2c2-xfer {
1140 rockchip,pins 957 rockchip,pins = <0 RK_PB1 2 &pcfg_pull_none>,
1141 958 <3 RK_PD7 2 &pcfg_pull_none>;
1142 }; 959 };
1143 }; 960 };
1144 961
1145 i2c3 { 962 i2c3 {
1146 i2c3_xfer: i2c3-xfer 963 i2c3_xfer: i2c3-xfer {
1147 rockchip,pins 964 rockchip,pins = <1 RK_PC0 1 &pcfg_pull_none>,
1148 965 <1 RK_PC1 1 &pcfg_pull_none>;
1149 }; 966 };
1150 }; 967 };
1151 968
1152 i2c4 { 969 i2c4 {
1153 i2c4_xfer: i2c4-xfer 970 i2c4_xfer: i2c4-xfer {
1154 rockchip,pins 971 rockchip,pins = <3 RK_PD0 2 &pcfg_pull_none>,
1155 972 <3 RK_PD1 2 &pcfg_pull_none>;
1156 }; 973 };
1157 }; 974 };
1158 975
1159 i2c5 { 976 i2c5 {
1160 i2c5_xfer: i2c5-xfer 977 i2c5_xfer: i2c5-xfer {
1161 rockchip,pins 978 rockchip,pins = <3 RK_PD2 2 &pcfg_pull_none>,
1162 979 <3 RK_PD3 2 &pcfg_pull_none>;
1163 }; 980 };
1164 }; 981 };
1165 982
1166 i2s { 983 i2s {
1167 i2s_8ch_bus: i2s-8ch- 984 i2s_8ch_bus: i2s-8ch-bus {
1168 rockchip,pins 985 rockchip,pins = <2 RK_PB4 1 &pcfg_pull_none>,
1169 986 <2 RK_PB5 1 &pcfg_pull_none>,
1170 987 <2 RK_PB6 1 &pcfg_pull_none>,
1171 988 <2 RK_PB7 1 &pcfg_pull_none>,
1172 989 <2 RK_PC0 1 &pcfg_pull_none>,
1173 990 <2 RK_PC1 1 &pcfg_pull_none>,
1174 991 <2 RK_PC2 1 &pcfg_pull_none>,
1175 992 <2 RK_PC3 1 &pcfg_pull_none>,
1176 993 <2 RK_PC4 1 &pcfg_pull_none>;
1177 }; 994 };
1178 }; 995 };
1179 996
1180 pwm0 { 997 pwm0 {
1181 pwm0_pin: pwm0-pin { 998 pwm0_pin: pwm0-pin {
1182 rockchip,pins 999 rockchip,pins = <3 RK_PB0 2 &pcfg_pull_none>;
1183 }; 1000 };
1184 }; 1001 };
1185 1002
1186 pwm1 { 1003 pwm1 {
1187 pwm1_pin: pwm1-pin { 1004 pwm1_pin: pwm1-pin {
1188 rockchip,pins 1005 rockchip,pins = <0 RK_PB0 2 &pcfg_pull_none>;
1189 }; 1006 };
1190 }; 1007 };
1191 1008
1192 pwm3 { 1009 pwm3 {
1193 pwm3_pin: pwm3-pin { 1010 pwm3_pin: pwm3-pin {
1194 rockchip,pins 1011 rockchip,pins = <3 RK_PD5 3 &pcfg_pull_none>;
1195 }; 1012 };
1196 }; 1013 };
1197 1014
1198 sdio0 { 1015 sdio0 {
1199 sdio0_bus1: sdio0-bus 1016 sdio0_bus1: sdio0-bus1 {
1200 rockchip,pins 1017 rockchip,pins = <2 RK_PD4 1 &pcfg_pull_up>;
1201 }; 1018 };
1202 1019
1203 sdio0_bus4: sdio0-bus 1020 sdio0_bus4: sdio0-bus4 {
1204 rockchip,pins 1021 rockchip,pins = <2 RK_PD4 1 &pcfg_pull_up>,
1205 1022 <2 RK_PD5 1 &pcfg_pull_up>,
1206 1023 <2 RK_PD6 1 &pcfg_pull_up>,
1207 1024 <2 RK_PD7 1 &pcfg_pull_up>;
1208 }; 1025 };
1209 1026
1210 sdio0_cmd: sdio0-cmd 1027 sdio0_cmd: sdio0-cmd {
1211 rockchip,pins 1028 rockchip,pins = <3 RK_PA0 1 &pcfg_pull_up>;
1212 }; 1029 };
1213 1030
1214 sdio0_clk: sdio0-clk 1031 sdio0_clk: sdio0-clk {
1215 rockchip,pins 1032 rockchip,pins = <3 RK_PA1 1 &pcfg_pull_none>;
1216 }; 1033 };
1217 1034
1218 sdio0_cd: sdio0-cd { 1035 sdio0_cd: sdio0-cd {
1219 rockchip,pins 1036 rockchip,pins = <3 RK_PA2 1 &pcfg_pull_up>;
1220 }; 1037 };
1221 1038
1222 sdio0_wp: sdio0-wp { 1039 sdio0_wp: sdio0-wp {
1223 rockchip,pins 1040 rockchip,pins = <3 RK_PA3 1 &pcfg_pull_up>;
1224 }; 1041 };
1225 1042
1226 sdio0_pwr: sdio0-pwr 1043 sdio0_pwr: sdio0-pwr {
1227 rockchip,pins 1044 rockchip,pins = <3 RK_PA4 1 &pcfg_pull_up>;
1228 }; 1045 };
1229 1046
1230 sdio0_bkpwr: sdio0-bk 1047 sdio0_bkpwr: sdio0-bkpwr {
1231 rockchip,pins 1048 rockchip,pins = <3 RK_PA5 1 &pcfg_pull_up>;
1232 }; 1049 };
1233 1050
1234 sdio0_int: sdio0-int 1051 sdio0_int: sdio0-int {
1235 rockchip,pins 1052 rockchip,pins = <3 RK_PA6 1 &pcfg_pull_up>;
1236 }; 1053 };
1237 }; 1054 };
1238 1055
1239 sdmmc { 1056 sdmmc {
1240 sdmmc_clk: sdmmc-clk 1057 sdmmc_clk: sdmmc-clk {
1241 rockchip,pins 1058 rockchip,pins = <2 RK_PB1 1 &pcfg_pull_none>;
1242 }; 1059 };
1243 1060
1244 sdmmc_cmd: sdmmc-cmd 1061 sdmmc_cmd: sdmmc-cmd {
1245 rockchip,pins 1062 rockchip,pins = <2 RK_PB2 1 &pcfg_pull_up>;
1246 }; 1063 };
1247 1064
1248 sdmmc_cd: sdmmc-cd { 1065 sdmmc_cd: sdmmc-cd {
1249 rockchip,pins 1066 rockchip,pins = <2 RK_PB3 1 &pcfg_pull_up>;
1250 }; 1067 };
1251 1068
1252 sdmmc_bus1: sdmmc-bus 1069 sdmmc_bus1: sdmmc-bus1 {
1253 rockchip,pins 1070 rockchip,pins = <2 RK_PA5 1 &pcfg_pull_up>;
1254 }; 1071 };
1255 1072
1256 sdmmc_bus4: sdmmc-bus 1073 sdmmc_bus4: sdmmc-bus4 {
1257 rockchip,pins 1074 rockchip,pins = <2 RK_PA5 1 &pcfg_pull_up>,
1258 1075 <2 RK_PA6 1 &pcfg_pull_up>,
1259 1076 <2 RK_PA7 1 &pcfg_pull_up>,
1260 1077 <2 RK_PB0 1 &pcfg_pull_up>;
1261 }; 1078 };
1262 }; 1079 };
1263 1080
1264 spdif { 1081 spdif {
1265 spdif_tx: spdif-tx { 1082 spdif_tx: spdif-tx {
1266 rockchip,pins !! 1083 rockchip,pins = <2 RK_PC7 1 &pcfg_pull_none>;
1267 }; 1084 };
1268 }; 1085 };
1269 1086
1270 spi0 { 1087 spi0 {
1271 spi0_clk: spi0-clk { 1088 spi0_clk: spi0-clk {
1272 rockchip,pins 1089 rockchip,pins = <1 RK_PD5 2 &pcfg_pull_up>;
1273 }; 1090 };
1274 spi0_cs0: spi0-cs0 { 1091 spi0_cs0: spi0-cs0 {
1275 rockchip,pins 1092 rockchip,pins = <1 RK_PD0 3 &pcfg_pull_up>;
1276 }; 1093 };
1277 spi0_cs1: spi0-cs1 { 1094 spi0_cs1: spi0-cs1 {
1278 rockchip,pins 1095 rockchip,pins = <1 RK_PD1 3 &pcfg_pull_up>;
1279 }; 1096 };
1280 spi0_tx: spi0-tx { 1097 spi0_tx: spi0-tx {
1281 rockchip,pins 1098 rockchip,pins = <1 RK_PC7 3 &pcfg_pull_up>;
1282 }; 1099 };
1283 spi0_rx: spi0-rx { 1100 spi0_rx: spi0-rx {
1284 rockchip,pins 1101 rockchip,pins = <1 RK_PC6 3 &pcfg_pull_up>;
1285 }; 1102 };
1286 }; 1103 };
1287 1104
1288 spi1 { 1105 spi1 {
1289 spi1_clk: spi1-clk { 1106 spi1_clk: spi1-clk {
1290 rockchip,pins 1107 rockchip,pins = <1 RK_PB6 2 &pcfg_pull_up>;
1291 }; 1108 };
1292 spi1_cs0: spi1-cs0 { 1109 spi1_cs0: spi1-cs0 {
1293 rockchip,pins 1110 rockchip,pins = <1 RK_PB7 2 &pcfg_pull_up>;
1294 }; 1111 };
1295 spi1_cs1: spi1-cs1 { 1112 spi1_cs1: spi1-cs1 {
1296 rockchip,pins 1113 rockchip,pins = <3 RK_PD4 2 &pcfg_pull_up>;
1297 }; 1114 };
1298 spi1_rx: spi1-rx { 1115 spi1_rx: spi1-rx {
1299 rockchip,pins 1116 rockchip,pins = <1 RK_PC0 2 &pcfg_pull_up>;
1300 }; 1117 };
1301 spi1_tx: spi1-tx { 1118 spi1_tx: spi1-tx {
1302 rockchip,pins 1119 rockchip,pins = <1 RK_PC1 2 &pcfg_pull_up>;
1303 }; 1120 };
1304 }; 1121 };
1305 1122
1306 spi2 { 1123 spi2 {
1307 spi2_clk: spi2-clk { 1124 spi2_clk: spi2-clk {
1308 rockchip,pins 1125 rockchip,pins = <0 RK_PB4 2 &pcfg_pull_up>;
1309 }; 1126 };
1310 spi2_cs0: spi2-cs0 { 1127 spi2_cs0: spi2-cs0 {
1311 rockchip,pins 1128 rockchip,pins = <0 RK_PB5 2 &pcfg_pull_up>;
1312 }; 1129 };
1313 spi2_rx: spi2-rx { 1130 spi2_rx: spi2-rx {
1314 rockchip,pins 1131 rockchip,pins = <0 RK_PB2 2 &pcfg_pull_up>;
1315 }; 1132 };
1316 spi2_tx: spi2-tx { 1133 spi2_tx: spi2-tx {
1317 rockchip,pins 1134 rockchip,pins = <0 RK_PB3 2 &pcfg_pull_up>;
1318 }; 1135 };
1319 }; 1136 };
1320 1137
1321 tsadc { 1138 tsadc {
1322 otp_pin: otp-pin { 1139 otp_pin: otp-pin {
1323 rockchip,pins 1140 rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
1324 }; 1141 };
1325 1142
1326 otp_out: otp-out { 1143 otp_out: otp-out {
1327 rockchip,pins 1144 rockchip,pins = <0 RK_PA3 1 &pcfg_pull_none>;
1328 }; 1145 };
1329 }; 1146 };
1330 1147
1331 uart0 { 1148 uart0 {
1332 uart0_xfer: uart0-xfe 1149 uart0_xfer: uart0-xfer {
1333 rockchip,pins 1150 rockchip,pins = <2 RK_PD0 1 &pcfg_pull_up>,
1334 1151 <2 RK_PD1 1 &pcfg_pull_none>;
1335 }; 1152 };
1336 1153
1337 uart0_cts: uart0-cts 1154 uart0_cts: uart0-cts {
1338 rockchip,pins 1155 rockchip,pins = <2 RK_PD2 1 &pcfg_pull_none>;
1339 }; 1156 };
1340 1157
1341 uart0_rts: uart0-rts 1158 uart0_rts: uart0-rts {
1342 rockchip,pins 1159 rockchip,pins = <2 RK_PD3 1 &pcfg_pull_none>;
1343 }; 1160 };
1344 }; 1161 };
1345 1162
1346 uart1 { 1163 uart1 {
1347 uart1_xfer: uart1-xfe 1164 uart1_xfer: uart1-xfer {
1348 rockchip,pins 1165 rockchip,pins = <0 RK_PC4 3 &pcfg_pull_up>,
1349 1166 <0 RK_PC5 3 &pcfg_pull_none>;
1350 }; 1167 };
1351 1168
1352 uart1_cts: uart1-cts 1169 uart1_cts: uart1-cts {
1353 rockchip,pins 1170 rockchip,pins = <0 RK_PC6 3 &pcfg_pull_none>;
1354 }; 1171 };
1355 1172
1356 uart1_rts: uart1-rts 1173 uart1_rts: uart1-rts {
1357 rockchip,pins 1174 rockchip,pins = <0 RK_PC7 3 &pcfg_pull_none>;
1358 }; 1175 };
1359 }; 1176 };
1360 1177
1361 uart2 { 1178 uart2 {
1362 uart2_xfer: uart2-xfe 1179 uart2_xfer: uart2-xfer {
1363 rockchip,pins 1180 rockchip,pins = <2 RK_PA6 2 &pcfg_pull_up>,
1364 1181 <2 RK_PA5 2 &pcfg_pull_none>;
1365 }; 1182 };
1366 /* no rts / cts for u 1183 /* no rts / cts for uart2 */
1367 }; 1184 };
1368 1185
1369 uart3 { 1186 uart3 {
1370 uart3_xfer: uart3-xfe 1187 uart3_xfer: uart3-xfer {
1371 rockchip,pins 1188 rockchip,pins = <3 RK_PD5 2 &pcfg_pull_up>,
1372 1189 <3 RK_PD6 3 &pcfg_pull_none>;
1373 }; 1190 };
1374 1191
1375 uart3_cts: uart3-cts 1192 uart3_cts: uart3-cts {
1376 rockchip,pins 1193 rockchip,pins = <3 RK_PC0 2 &pcfg_pull_none>;
1377 }; 1194 };
1378 1195
1379 uart3_rts: uart3-rts 1196 uart3_rts: uart3-rts {
1380 rockchip,pins 1197 rockchip,pins = <3 RK_PC1 2 &pcfg_pull_none>;
1381 }; 1198 };
1382 }; 1199 };
1383 1200
1384 uart4 { 1201 uart4 {
1385 uart4_xfer: uart4-xfe 1202 uart4_xfer: uart4-xfer {
1386 rockchip,pins 1203 rockchip,pins = <0 RK_PD3 3 &pcfg_pull_up>,
1387 1204 <0 RK_PD2 3 &pcfg_pull_none>;
1388 }; 1205 };
1389 1206
1390 uart4_cts: uart4-cts 1207 uart4_cts: uart4-cts {
1391 rockchip,pins 1208 rockchip,pins = <0 RK_PD0 3 &pcfg_pull_none>;
1392 }; 1209 };
1393 1210
1394 uart4_rts: uart4-rts 1211 uart4_rts: uart4-rts {
1395 rockchip,pins 1212 rockchip,pins = <0 RK_PD1 3 &pcfg_pull_none>;
1396 }; 1213 };
1397 }; 1214 };
1398 }; 1215 };
1399 }; 1216 };
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