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TOMOYO Linux Cross Reference
Linux/scripts/dtc/include-prefixes/arm64/rockchip/rk3368.dtsi

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Diff markup

Differences between /scripts/dtc/include-prefixes/arm64/rockchip/rk3368.dtsi (Version linux-6.12-rc7) and /scripts/dtc/include-prefixes/arm64/rockchip/rk3368.dtsi (Version linux-5.6.19)


  1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)       1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
  2 /*                                                  2 /*
  3  * Copyright (c) 2015 Heiko Stuebner <heiko@snt      3  * Copyright (c) 2015 Heiko Stuebner <heiko@sntech.de>
  4  */                                                 4  */
  5                                                     5 
  6 #include <dt-bindings/clock/rk3368-cru.h>           6 #include <dt-bindings/clock/rk3368-cru.h>
  7 #include <dt-bindings/gpio/gpio.h>                  7 #include <dt-bindings/gpio/gpio.h>
  8 #include <dt-bindings/interrupt-controller/irq      8 #include <dt-bindings/interrupt-controller/irq.h>
  9 #include <dt-bindings/interrupt-controller/arm      9 #include <dt-bindings/interrupt-controller/arm-gic.h>
 10 #include <dt-bindings/pinctrl/rockchip.h>          10 #include <dt-bindings/pinctrl/rockchip.h>
 11 #include <dt-bindings/power/rk3368-power.h>    << 
 12 #include <dt-bindings/soc/rockchip,boot-mode.h     11 #include <dt-bindings/soc/rockchip,boot-mode.h>
 13 #include <dt-bindings/thermal/thermal.h>           12 #include <dt-bindings/thermal/thermal.h>
 14                                                    13 
 15 / {                                                14 / {
 16         compatible = "rockchip,rk3368";            15         compatible = "rockchip,rk3368";
 17         interrupt-parent = <&gic>;                 16         interrupt-parent = <&gic>;
 18         #address-cells = <2>;                      17         #address-cells = <2>;
 19         #size-cells = <2>;                         18         #size-cells = <2>;
 20                                                    19 
 21         aliases {                                  20         aliases {
 22                 gpio0 = &gpio0;                !!  21                 ethernet0 = &gmac;
 23                 gpio1 = &gpio1;                << 
 24                 gpio2 = &gpio2;                << 
 25                 gpio3 = &gpio3;                << 
 26                 i2c0 = &i2c0;                      22                 i2c0 = &i2c0;
 27                 i2c1 = &i2c1;                      23                 i2c1 = &i2c1;
 28                 i2c2 = &i2c2;                      24                 i2c2 = &i2c2;
 29                 i2c3 = &i2c3;                      25                 i2c3 = &i2c3;
 30                 i2c4 = &i2c4;                      26                 i2c4 = &i2c4;
 31                 i2c5 = &i2c5;                      27                 i2c5 = &i2c5;
 32                 serial0 = &uart0;                  28                 serial0 = &uart0;
 33                 serial1 = &uart1;                  29                 serial1 = &uart1;
 34                 serial2 = &uart2;                  30                 serial2 = &uart2;
 35                 serial3 = &uart3;                  31                 serial3 = &uart3;
 36                 serial4 = &uart4;                  32                 serial4 = &uart4;
 37                 spi0 = &spi0;                      33                 spi0 = &spi0;
 38                 spi1 = &spi1;                      34                 spi1 = &spi1;
 39                 spi2 = &spi2;                      35                 spi2 = &spi2;
 40         };                                         36         };
 41                                                    37 
 42         cpus {                                     38         cpus {
 43                 #address-cells = <0x2>;            39                 #address-cells = <0x2>;
 44                 #size-cells = <0x0>;               40                 #size-cells = <0x0>;
 45                                                    41 
 46                 cpu-map {                          42                 cpu-map {
 47                         cluster0 {                 43                         cluster0 {
 48                                 core0 {            44                                 core0 {
 49                                         cpu =      45                                         cpu = <&cpu_b0>;
 50                                 };                 46                                 };
 51                                 core1 {            47                                 core1 {
 52                                         cpu =      48                                         cpu = <&cpu_b1>;
 53                                 };                 49                                 };
 54                                 core2 {            50                                 core2 {
 55                                         cpu =      51                                         cpu = <&cpu_b2>;
 56                                 };                 52                                 };
 57                                 core3 {            53                                 core3 {
 58                                         cpu =      54                                         cpu = <&cpu_b3>;
 59                                 };                 55                                 };
 60                         };                         56                         };
 61                                                    57 
 62                         cluster1 {                 58                         cluster1 {
 63                                 core0 {            59                                 core0 {
 64                                         cpu =      60                                         cpu = <&cpu_l0>;
 65                                 };                 61                                 };
 66                                 core1 {            62                                 core1 {
 67                                         cpu =      63                                         cpu = <&cpu_l1>;
 68                                 };                 64                                 };
 69                                 core2 {            65                                 core2 {
 70                                         cpu =      66                                         cpu = <&cpu_l2>;
 71                                 };                 67                                 };
 72                                 core3 {            68                                 core3 {
 73                                         cpu =      69                                         cpu = <&cpu_l3>;
 74                                 };                 70                                 };
 75                         };                         71                         };
 76                 };                                 72                 };
 77                                                    73 
 78                 cpu_l0: cpu@0 {                    74                 cpu_l0: cpu@0 {
 79                         device_type = "cpu";       75                         device_type = "cpu";
 80                         compatible = "arm,cort     76                         compatible = "arm,cortex-a53";
 81                         reg = <0x0 0x0>;           77                         reg = <0x0 0x0>;
 82                         enable-method = "psci"     78                         enable-method = "psci";
 83                         #cooling-cells = <2>;      79                         #cooling-cells = <2>; /* min followed by max */
 84                 };                                 80                 };
 85                                                    81 
 86                 cpu_l1: cpu@1 {                    82                 cpu_l1: cpu@1 {
 87                         device_type = "cpu";       83                         device_type = "cpu";
 88                         compatible = "arm,cort     84                         compatible = "arm,cortex-a53";
 89                         reg = <0x0 0x1>;           85                         reg = <0x0 0x1>;
 90                         enable-method = "psci"     86                         enable-method = "psci";
 91                         #cooling-cells = <2>;      87                         #cooling-cells = <2>; /* min followed by max */
 92                 };                                 88                 };
 93                                                    89 
 94                 cpu_l2: cpu@2 {                    90                 cpu_l2: cpu@2 {
 95                         device_type = "cpu";       91                         device_type = "cpu";
 96                         compatible = "arm,cort     92                         compatible = "arm,cortex-a53";
 97                         reg = <0x0 0x2>;           93                         reg = <0x0 0x2>;
 98                         enable-method = "psci"     94                         enable-method = "psci";
 99                         #cooling-cells = <2>;      95                         #cooling-cells = <2>; /* min followed by max */
100                 };                                 96                 };
101                                                    97 
102                 cpu_l3: cpu@3 {                    98                 cpu_l3: cpu@3 {
103                         device_type = "cpu";       99                         device_type = "cpu";
104                         compatible = "arm,cort    100                         compatible = "arm,cortex-a53";
105                         reg = <0x0 0x3>;          101                         reg = <0x0 0x3>;
106                         enable-method = "psci"    102                         enable-method = "psci";
107                         #cooling-cells = <2>;     103                         #cooling-cells = <2>; /* min followed by max */
108                 };                                104                 };
109                                                   105 
110                 cpu_b0: cpu@100 {                 106                 cpu_b0: cpu@100 {
111                         device_type = "cpu";      107                         device_type = "cpu";
112                         compatible = "arm,cort    108                         compatible = "arm,cortex-a53";
113                         reg = <0x0 0x100>;        109                         reg = <0x0 0x100>;
114                         enable-method = "psci"    110                         enable-method = "psci";
115                         #cooling-cells = <2>;     111                         #cooling-cells = <2>; /* min followed by max */
116                 };                                112                 };
117                                                   113 
118                 cpu_b1: cpu@101 {                 114                 cpu_b1: cpu@101 {
119                         device_type = "cpu";      115                         device_type = "cpu";
120                         compatible = "arm,cort    116                         compatible = "arm,cortex-a53";
121                         reg = <0x0 0x101>;        117                         reg = <0x0 0x101>;
122                         enable-method = "psci"    118                         enable-method = "psci";
123                         #cooling-cells = <2>;     119                         #cooling-cells = <2>; /* min followed by max */
124                 };                                120                 };
125                                                   121 
126                 cpu_b2: cpu@102 {                 122                 cpu_b2: cpu@102 {
127                         device_type = "cpu";      123                         device_type = "cpu";
128                         compatible = "arm,cort    124                         compatible = "arm,cortex-a53";
129                         reg = <0x0 0x102>;        125                         reg = <0x0 0x102>;
130                         enable-method = "psci"    126                         enable-method = "psci";
131                         #cooling-cells = <2>;     127                         #cooling-cells = <2>; /* min followed by max */
132                 };                                128                 };
133                                                   129 
134                 cpu_b3: cpu@103 {                 130                 cpu_b3: cpu@103 {
135                         device_type = "cpu";      131                         device_type = "cpu";
136                         compatible = "arm,cort    132                         compatible = "arm,cortex-a53";
137                         reg = <0x0 0x103>;        133                         reg = <0x0 0x103>;
138                         enable-method = "psci"    134                         enable-method = "psci";
139                         #cooling-cells = <2>;     135                         #cooling-cells = <2>; /* min followed by max */
140                 };                                136                 };
141         };                                        137         };
142                                                   138 
                                                   >> 139         amba {
                                                   >> 140                 compatible = "simple-bus";
                                                   >> 141                 #address-cells = <2>;
                                                   >> 142                 #size-cells = <2>;
                                                   >> 143                 ranges;
                                                   >> 144 
                                                   >> 145                 dmac_peri: dma-controller@ff250000 {
                                                   >> 146                         compatible = "arm,pl330", "arm,primecell";
                                                   >> 147                         reg = <0x0 0xff250000 0x0 0x4000>;
                                                   >> 148                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
                                                   >> 149                                      <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
                                                   >> 150                         #dma-cells = <1>;
                                                   >> 151                         arm,pl330-broken-no-flushp;
                                                   >> 152                         clocks = <&cru ACLK_DMAC_PERI>;
                                                   >> 153                         clock-names = "apb_pclk";
                                                   >> 154                 };
                                                   >> 155 
                                                   >> 156                 dmac_bus: dma-controller@ff600000 {
                                                   >> 157                         compatible = "arm,pl330", "arm,primecell";
                                                   >> 158                         reg = <0x0 0xff600000 0x0 0x4000>;
                                                   >> 159                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
                                                   >> 160                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
                                                   >> 161                         #dma-cells = <1>;
                                                   >> 162                         arm,pl330-broken-no-flushp;
                                                   >> 163                         clocks = <&cru ACLK_DMAC_BUS>;
                                                   >> 164                         clock-names = "apb_pclk";
                                                   >> 165                 };
                                                   >> 166         };
                                                   >> 167 
143         arm-pmu {                                 168         arm-pmu {
144                 compatible = "arm,cortex-a53-p !! 169                 compatible = "arm,armv8-pmuv3";
145                 interrupts = <GIC_SPI 112 IRQ_    170                 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
146                              <GIC_SPI 113 IRQ_    171                              <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
147                              <GIC_SPI 114 IRQ_    172                              <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
148                              <GIC_SPI 115 IRQ_    173                              <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
149                              <GIC_SPI 116 IRQ_    174                              <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
150                              <GIC_SPI 117 IRQ_    175                              <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
151                              <GIC_SPI 118 IRQ_    176                              <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
152                              <GIC_SPI 119 IRQ_    177                              <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
153                 interrupt-affinity = <&cpu_l0>    178                 interrupt-affinity = <&cpu_l0>, <&cpu_l1>, <&cpu_l2>,
154                                      <&cpu_l3>    179                                      <&cpu_l3>, <&cpu_b0>, <&cpu_b1>,
155                                      <&cpu_b2>    180                                      <&cpu_b2>, <&cpu_b3>;
156         };                                        181         };
157                                                   182 
158         psci {                                    183         psci {
159                 compatible = "arm,psci-0.2";      184                 compatible = "arm,psci-0.2";
160                 method = "smc";                   185                 method = "smc";
161         };                                        186         };
162                                                   187 
163         timer {                                   188         timer {
164                 compatible = "arm,armv8-timer"    189                 compatible = "arm,armv8-timer";
165                 interrupts = <GIC_PPI 13          190                 interrupts = <GIC_PPI 13
166                         (GIC_CPU_MASK_SIMPLE(8    191                         (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
167                              <GIC_PPI 14          192                              <GIC_PPI 14
168                         (GIC_CPU_MASK_SIMPLE(8    193                         (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
169                              <GIC_PPI 11          194                              <GIC_PPI 11
170                         (GIC_CPU_MASK_SIMPLE(8    195                         (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
171                              <GIC_PPI 10          196                              <GIC_PPI 10
172                         (GIC_CPU_MASK_SIMPLE(8    197                         (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
173         };                                        198         };
174                                                   199 
175         xin24m: oscillator {                      200         xin24m: oscillator {
176                 compatible = "fixed-clock";       201                 compatible = "fixed-clock";
177                 clock-frequency = <24000000>;     202                 clock-frequency = <24000000>;
178                 clock-output-names = "xin24m";    203                 clock-output-names = "xin24m";
179                 #clock-cells = <0>;               204                 #clock-cells = <0>;
180         };                                        205         };
181                                                   206 
182         sdmmc: mmc@ff0c0000 {                     207         sdmmc: mmc@ff0c0000 {
183                 compatible = "rockchip,rk3368-    208                 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
184                 reg = <0x0 0xff0c0000 0x0 0x40    209                 reg = <0x0 0xff0c0000 0x0 0x4000>;
185                 max-frequency = <150000000>;      210                 max-frequency = <150000000>;
186                 clocks = <&cru HCLK_SDMMC>, <&    211                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
187                          <&cru SCLK_SDMMC_DRV>    212                          <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
188                 clock-names = "biu", "ciu", "c    213                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
189                 fifo-depth = <0x100>;             214                 fifo-depth = <0x100>;
190                 interrupts = <GIC_SPI 32 IRQ_T    215                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
191                 resets = <&cru SRST_MMC0>;        216                 resets = <&cru SRST_MMC0>;
192                 reset-names = "reset";            217                 reset-names = "reset";
193                 status = "disabled";              218                 status = "disabled";
194         };                                        219         };
195                                                   220 
196         sdio0: mmc@ff0d0000 {                     221         sdio0: mmc@ff0d0000 {
197                 compatible = "rockchip,rk3368-    222                 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
198                 reg = <0x0 0xff0d0000 0x0 0x40    223                 reg = <0x0 0xff0d0000 0x0 0x4000>;
199                 max-frequency = <150000000>;      224                 max-frequency = <150000000>;
200                 clocks = <&cru HCLK_SDIO0>, <&    225                 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>,
201                          <&cru SCLK_SDIO0_DRV>    226                          <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
202                 clock-names = "biu", "ciu", "c    227                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
203                 fifo-depth = <0x100>;             228                 fifo-depth = <0x100>;
204                 interrupts = <GIC_SPI 33 IRQ_T    229                 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
205                 resets = <&cru SRST_SDIO0>;       230                 resets = <&cru SRST_SDIO0>;
206                 reset-names = "reset";            231                 reset-names = "reset";
207                 status = "disabled";              232                 status = "disabled";
208         };                                        233         };
209                                                   234 
210         emmc: mmc@ff0f0000 {                      235         emmc: mmc@ff0f0000 {
211                 compatible = "rockchip,rk3368-    236                 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
212                 reg = <0x0 0xff0f0000 0x0 0x40    237                 reg = <0x0 0xff0f0000 0x0 0x4000>;
213                 max-frequency = <150000000>;      238                 max-frequency = <150000000>;
214                 clocks = <&cru HCLK_EMMC>, <&c    239                 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
215                          <&cru SCLK_EMMC_DRV>,    240                          <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
216                 clock-names = "biu", "ciu", "c    241                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
217                 fifo-depth = <0x100>;             242                 fifo-depth = <0x100>;
218                 interrupts = <GIC_SPI 35 IRQ_T    243                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
219                 resets = <&cru SRST_EMMC>;        244                 resets = <&cru SRST_EMMC>;
220                 reset-names = "reset";            245                 reset-names = "reset";
221                 status = "disabled";              246                 status = "disabled";
222         };                                        247         };
223                                                   248 
224         saradc: saradc@ff100000 {                 249         saradc: saradc@ff100000 {
225                 compatible = "rockchip,saradc"    250                 compatible = "rockchip,saradc";
226                 reg = <0x0 0xff100000 0x0 0x10    251                 reg = <0x0 0xff100000 0x0 0x100>;
227                 interrupts = <GIC_SPI 36 IRQ_T    252                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
228                 #io-channel-cells = <1>;          253                 #io-channel-cells = <1>;
229                 clocks = <&cru SCLK_SARADC>, <    254                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
230                 clock-names = "saradc", "apb_p    255                 clock-names = "saradc", "apb_pclk";
231                 resets = <&cru SRST_SARADC>;      256                 resets = <&cru SRST_SARADC>;
232                 reset-names = "saradc-apb";       257                 reset-names = "saradc-apb";
233                 status = "disabled";              258                 status = "disabled";
234         };                                        259         };
235                                                   260 
236         spi0: spi@ff110000 {                      261         spi0: spi@ff110000 {
237                 compatible = "rockchip,rk3368-    262                 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
238                 reg = <0x0 0xff110000 0x0 0x10    263                 reg = <0x0 0xff110000 0x0 0x1000>;
239                 clocks = <&cru SCLK_SPI0>, <&c    264                 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
240                 clock-names = "spiclk", "apb_p    265                 clock-names = "spiclk", "apb_pclk";
241                 interrupts = <GIC_SPI 44 IRQ_T    266                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
242                 pinctrl-names = "default";        267                 pinctrl-names = "default";
243                 pinctrl-0 = <&spi0_clk &spi0_t    268                 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
244                 #address-cells = <1>;             269                 #address-cells = <1>;
245                 #size-cells = <0>;                270                 #size-cells = <0>;
246                 status = "disabled";              271                 status = "disabled";
247         };                                        272         };
248                                                   273 
249         spi1: spi@ff120000 {                      274         spi1: spi@ff120000 {
250                 compatible = "rockchip,rk3368-    275                 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
251                 reg = <0x0 0xff120000 0x0 0x10    276                 reg = <0x0 0xff120000 0x0 0x1000>;
252                 clocks = <&cru SCLK_SPI1>, <&c    277                 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
253                 clock-names = "spiclk", "apb_p    278                 clock-names = "spiclk", "apb_pclk";
254                 interrupts = <GIC_SPI 45 IRQ_T    279                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
255                 pinctrl-names = "default";        280                 pinctrl-names = "default";
256                 pinctrl-0 = <&spi1_clk &spi1_t    281                 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
257                 #address-cells = <1>;             282                 #address-cells = <1>;
258                 #size-cells = <0>;                283                 #size-cells = <0>;
259                 status = "disabled";              284                 status = "disabled";
260         };                                        285         };
261                                                   286 
262         spi2: spi@ff130000 {                      287         spi2: spi@ff130000 {
263                 compatible = "rockchip,rk3368-    288                 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
264                 reg = <0x0 0xff130000 0x0 0x10    289                 reg = <0x0 0xff130000 0x0 0x1000>;
265                 clocks = <&cru SCLK_SPI2>, <&c    290                 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
266                 clock-names = "spiclk", "apb_p    291                 clock-names = "spiclk", "apb_pclk";
267                 interrupts = <GIC_SPI 41 IRQ_T    292                 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
268                 pinctrl-names = "default";        293                 pinctrl-names = "default";
269                 pinctrl-0 = <&spi2_clk &spi2_t    294                 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
270                 #address-cells = <1>;             295                 #address-cells = <1>;
271                 #size-cells = <0>;                296                 #size-cells = <0>;
272                 status = "disabled";              297                 status = "disabled";
273         };                                        298         };
274                                                   299 
275         i2c2: i2c@ff140000 {                      300         i2c2: i2c@ff140000 {
276                 compatible = "rockchip,rk3368-    301                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
277                 reg = <0x0 0xff140000 0x0 0x10    302                 reg = <0x0 0xff140000 0x0 0x1000>;
278                 interrupts = <GIC_SPI 62 IRQ_T    303                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
279                 #address-cells = <1>;             304                 #address-cells = <1>;
280                 #size-cells = <0>;                305                 #size-cells = <0>;
281                 clock-names = "i2c";              306                 clock-names = "i2c";
282                 clocks = <&cru PCLK_I2C2>;        307                 clocks = <&cru PCLK_I2C2>;
283                 pinctrl-names = "default";        308                 pinctrl-names = "default";
284                 pinctrl-0 = <&i2c2_xfer>;         309                 pinctrl-0 = <&i2c2_xfer>;
285                 status = "disabled";              310                 status = "disabled";
286         };                                        311         };
287                                                   312 
288         i2c3: i2c@ff150000 {                      313         i2c3: i2c@ff150000 {
289                 compatible = "rockchip,rk3368-    314                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
290                 reg = <0x0 0xff150000 0x0 0x10    315                 reg = <0x0 0xff150000 0x0 0x1000>;
291                 interrupts = <GIC_SPI 63 IRQ_T    316                 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
292                 #address-cells = <1>;             317                 #address-cells = <1>;
293                 #size-cells = <0>;                318                 #size-cells = <0>;
294                 clock-names = "i2c";              319                 clock-names = "i2c";
295                 clocks = <&cru PCLK_I2C3>;        320                 clocks = <&cru PCLK_I2C3>;
296                 pinctrl-names = "default";        321                 pinctrl-names = "default";
297                 pinctrl-0 = <&i2c3_xfer>;         322                 pinctrl-0 = <&i2c3_xfer>;
298                 status = "disabled";              323                 status = "disabled";
299         };                                        324         };
300                                                   325 
301         i2c4: i2c@ff160000 {                      326         i2c4: i2c@ff160000 {
302                 compatible = "rockchip,rk3368-    327                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
303                 reg = <0x0 0xff160000 0x0 0x10    328                 reg = <0x0 0xff160000 0x0 0x1000>;
304                 interrupts = <GIC_SPI 64 IRQ_T    329                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
305                 #address-cells = <1>;             330                 #address-cells = <1>;
306                 #size-cells = <0>;                331                 #size-cells = <0>;
307                 clock-names = "i2c";              332                 clock-names = "i2c";
308                 clocks = <&cru PCLK_I2C4>;        333                 clocks = <&cru PCLK_I2C4>;
309                 pinctrl-names = "default";        334                 pinctrl-names = "default";
310                 pinctrl-0 = <&i2c4_xfer>;         335                 pinctrl-0 = <&i2c4_xfer>;
311                 status = "disabled";              336                 status = "disabled";
312         };                                        337         };
313                                                   338 
314         i2c5: i2c@ff170000 {                      339         i2c5: i2c@ff170000 {
315                 compatible = "rockchip,rk3368-    340                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
316                 reg = <0x0 0xff170000 0x0 0x10    341                 reg = <0x0 0xff170000 0x0 0x1000>;
317                 interrupts = <GIC_SPI 65 IRQ_T    342                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
318                 #address-cells = <1>;             343                 #address-cells = <1>;
319                 #size-cells = <0>;                344                 #size-cells = <0>;
320                 clock-names = "i2c";              345                 clock-names = "i2c";
321                 clocks = <&cru PCLK_I2C5>;        346                 clocks = <&cru PCLK_I2C5>;
322                 pinctrl-names = "default";        347                 pinctrl-names = "default";
323                 pinctrl-0 = <&i2c5_xfer>;         348                 pinctrl-0 = <&i2c5_xfer>;
324                 status = "disabled";              349                 status = "disabled";
325         };                                        350         };
326                                                   351 
327         uart0: serial@ff180000 {                  352         uart0: serial@ff180000 {
328                 compatible = "rockchip,rk3368-    353                 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
329                 reg = <0x0 0xff180000 0x0 0x10    354                 reg = <0x0 0xff180000 0x0 0x100>;
330                 clock-frequency = <24000000>;     355                 clock-frequency = <24000000>;
331                 clocks = <&cru SCLK_UART0>, <&    356                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
332                 clock-names = "baudclk", "apb_    357                 clock-names = "baudclk", "apb_pclk";
333                 interrupts = <GIC_SPI 55 IRQ_T    358                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
334                 reg-shift = <2>;                  359                 reg-shift = <2>;
335                 reg-io-width = <4>;               360                 reg-io-width = <4>;
336                 status = "disabled";              361                 status = "disabled";
337         };                                        362         };
338                                                   363 
339         uart1: serial@ff190000 {                  364         uart1: serial@ff190000 {
340                 compatible = "rockchip,rk3368-    365                 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
341                 reg = <0x0 0xff190000 0x0 0x10    366                 reg = <0x0 0xff190000 0x0 0x100>;
342                 clock-frequency = <24000000>;     367                 clock-frequency = <24000000>;
343                 clocks = <&cru SCLK_UART1>, <&    368                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
344                 clock-names = "baudclk", "apb_    369                 clock-names = "baudclk", "apb_pclk";
345                 interrupts = <GIC_SPI 56 IRQ_T    370                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
346                 reg-shift = <2>;                  371                 reg-shift = <2>;
347                 reg-io-width = <4>;               372                 reg-io-width = <4>;
348                 status = "disabled";              373                 status = "disabled";
349         };                                        374         };
350                                                   375 
351         uart3: serial@ff1b0000 {                  376         uart3: serial@ff1b0000 {
352                 compatible = "rockchip,rk3368-    377                 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
353                 reg = <0x0 0xff1b0000 0x0 0x10    378                 reg = <0x0 0xff1b0000 0x0 0x100>;
354                 clock-frequency = <24000000>;     379                 clock-frequency = <24000000>;
355                 clocks = <&cru SCLK_UART3>, <&    380                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
356                 clock-names = "baudclk", "apb_    381                 clock-names = "baudclk", "apb_pclk";
357                 interrupts = <GIC_SPI 58 IRQ_T    382                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
358                 reg-shift = <2>;                  383                 reg-shift = <2>;
359                 reg-io-width = <4>;               384                 reg-io-width = <4>;
360                 status = "disabled";              385                 status = "disabled";
361         };                                        386         };
362                                                   387 
363         uart4: serial@ff1c0000 {                  388         uart4: serial@ff1c0000 {
364                 compatible = "rockchip,rk3368-    389                 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
365                 reg = <0x0 0xff1c0000 0x0 0x10    390                 reg = <0x0 0xff1c0000 0x0 0x100>;
366                 clock-frequency = <24000000>;     391                 clock-frequency = <24000000>;
367                 clocks = <&cru SCLK_UART4>, <&    392                 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
368                 clock-names = "baudclk", "apb_    393                 clock-names = "baudclk", "apb_pclk";
369                 interrupts = <GIC_SPI 59 IRQ_T    394                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
370                 reg-shift = <2>;                  395                 reg-shift = <2>;
371                 reg-io-width = <4>;               396                 reg-io-width = <4>;
372                 status = "disabled";              397                 status = "disabled";
373         };                                        398         };
374                                                   399 
375         dmac_peri: dma-controller@ff250000 {   << 
376                 compatible = "arm,pl330", "arm << 
377                 reg = <0x0 0xff250000 0x0 0x40 << 
378                 interrupts = <GIC_SPI 2 IRQ_TY << 
379                              <GIC_SPI 3 IRQ_TY << 
380                 #dma-cells = <1>;              << 
381                 arm,pl330-broken-no-flushp;    << 
382                 arm,pl330-periph-burst;        << 
383                 clocks = <&cru ACLK_DMAC_PERI> << 
384                 clock-names = "apb_pclk";      << 
385         };                                     << 
386                                                << 
387         thermal-zones {                           400         thermal-zones {
388                 cpu_thermal: cpu-thermal {     !! 401                 cpu {
389                         polling-delay-passive     402                         polling-delay-passive = <100>; /* milliseconds */
390                         polling-delay = <5000>    403                         polling-delay = <5000>; /* milliseconds */
391                                                   404 
392                         thermal-sensors = <&ts    405                         thermal-sensors = <&tsadc 0>;
393                                                   406 
394                         trips {                   407                         trips {
395                                 cpu_alert0: cp    408                                 cpu_alert0: cpu_alert0 {
396                                         temper    409                                         temperature = <75000>; /* millicelsius */
397                                         hyster    410                                         hysteresis = <2000>; /* millicelsius */
398                                         type =    411                                         type = "passive";
399                                 };                412                                 };
400                                 cpu_alert1: cp    413                                 cpu_alert1: cpu_alert1 {
401                                         temper    414                                         temperature = <80000>; /* millicelsius */
402                                         hyster    415                                         hysteresis = <2000>; /* millicelsius */
403                                         type =    416                                         type = "passive";
404                                 };                417                                 };
405                                 cpu_crit: cpu_    418                                 cpu_crit: cpu_crit {
406                                         temper    419                                         temperature = <95000>; /* millicelsius */
407                                         hyster    420                                         hysteresis = <2000>; /* millicelsius */
408                                         type =    421                                         type = "critical";
409                                 };                422                                 };
410                         };                        423                         };
411                                                   424 
412                         cooling-maps {            425                         cooling-maps {
413                                 map0 {            426                                 map0 {
414                                         trip =    427                                         trip = <&cpu_alert0>;
415                                         coolin    428                                         cooling-device =
416                                         <&cpu_    429                                         <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
417                                         <&cpu_    430                                         <&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
418                                         <&cpu_    431                                         <&cpu_b2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
419                                         <&cpu_    432                                         <&cpu_b3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
420                                 };                433                                 };
421                                 map1 {            434                                 map1 {
422                                         trip =    435                                         trip = <&cpu_alert1>;
423                                         coolin    436                                         cooling-device =
424                                         <&cpu_    437                                         <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
425                                         <&cpu_    438                                         <&cpu_l1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
426                                         <&cpu_    439                                         <&cpu_l2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
427                                         <&cpu_    440                                         <&cpu_l3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
428                                 };                441                                 };
429                         };                        442                         };
430                 };                                443                 };
431                                                   444 
432                 gpu_thermal: gpu-thermal {     !! 445                 gpu {
433                         polling-delay-passive     446                         polling-delay-passive = <100>; /* milliseconds */
434                         polling-delay = <5000>    447                         polling-delay = <5000>; /* milliseconds */
435                                                   448 
436                         thermal-sensors = <&ts    449                         thermal-sensors = <&tsadc 1>;
437                                                   450 
438                         trips {                   451                         trips {
439                                 gpu_alert0: gp    452                                 gpu_alert0: gpu_alert0 {
440                                         temper    453                                         temperature = <80000>; /* millicelsius */
441                                         hyster    454                                         hysteresis = <2000>; /* millicelsius */
442                                         type =    455                                         type = "passive";
443                                 };                456                                 };
444                                 gpu_crit: gpu_    457                                 gpu_crit: gpu_crit {
445                                         temper    458                                         temperature = <115000>; /* millicelsius */
446                                         hyster    459                                         hysteresis = <2000>; /* millicelsius */
447                                         type =    460                                         type = "critical";
448                                 };                461                                 };
449                         };                        462                         };
450                                                   463 
451                         cooling-maps {            464                         cooling-maps {
452                                 map0 {            465                                 map0 {
453                                         trip =    466                                         trip = <&gpu_alert0>;
454                                         coolin    467                                         cooling-device =
455                                         <&cpu_    468                                         <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
456                                         <&cpu_    469                                         <&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
457                                         <&cpu_    470                                         <&cpu_b2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
458                                         <&cpu_    471                                         <&cpu_b3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
459                                 };                472                                 };
460                         };                        473                         };
461                 };                                474                 };
462         };                                        475         };
463                                                   476 
464         tsadc: tsadc@ff280000 {                   477         tsadc: tsadc@ff280000 {
465                 compatible = "rockchip,rk3368-    478                 compatible = "rockchip,rk3368-tsadc";
466                 reg = <0x0 0xff280000 0x0 0x10    479                 reg = <0x0 0xff280000 0x0 0x100>;
467                 interrupts = <GIC_SPI 37 IRQ_T    480                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
468                 clocks = <&cru SCLK_TSADC>, <&    481                 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
469                 clock-names = "tsadc", "apb_pc    482                 clock-names = "tsadc", "apb_pclk";
470                 resets = <&cru SRST_TSADC>;       483                 resets = <&cru SRST_TSADC>;
471                 reset-names = "tsadc-apb";        484                 reset-names = "tsadc-apb";
472                 pinctrl-names = "init", "defau    485                 pinctrl-names = "init", "default", "sleep";
473                 pinctrl-0 = <&otp_pin>;        !! 486                 pinctrl-0 = <&otp_gpio>;
474                 pinctrl-1 = <&otp_out>;           487                 pinctrl-1 = <&otp_out>;
475                 pinctrl-2 = <&otp_pin>;        !! 488                 pinctrl-2 = <&otp_gpio>;
476                 #thermal-sensor-cells = <1>;      489                 #thermal-sensor-cells = <1>;
477                 rockchip,hw-tshut-temp = <9500    490                 rockchip,hw-tshut-temp = <95000>;
478                 status = "disabled";              491                 status = "disabled";
479         };                                        492         };
480                                                   493 
481         gmac: ethernet@ff290000 {                 494         gmac: ethernet@ff290000 {
482                 compatible = "rockchip,rk3368-    495                 compatible = "rockchip,rk3368-gmac";
483                 reg = <0x0 0xff290000 0x0 0x10    496                 reg = <0x0 0xff290000 0x0 0x10000>;
484                 interrupts = <GIC_SPI 27 IRQ_T    497                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
485                 interrupt-names = "macirq";       498                 interrupt-names = "macirq";
486                 rockchip,grf = <&grf>;            499                 rockchip,grf = <&grf>;
487                 clocks = <&cru SCLK_MAC>,         500                 clocks = <&cru SCLK_MAC>,
488                         <&cru SCLK_MAC_RX>, <&    501                         <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>,
489                         <&cru SCLK_MACREF>, <&    502                         <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>,
490                         <&cru ACLK_GMAC>, <&cr    503                         <&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
491                 clock-names = "stmmaceth",        504                 clock-names = "stmmaceth",
492                         "mac_clk_rx", "mac_clk    505                         "mac_clk_rx", "mac_clk_tx",
493                         "clk_mac_ref", "clk_ma    506                         "clk_mac_ref", "clk_mac_refout",
494                         "aclk_mac", "pclk_mac"    507                         "aclk_mac", "pclk_mac";
495                 status = "disabled";              508                 status = "disabled";
496         };                                        509         };
497                                                   510 
498         usb_host0_ehci: usb@ff500000 {            511         usb_host0_ehci: usb@ff500000 {
499                 compatible = "generic-ehci";      512                 compatible = "generic-ehci";
500                 reg = <0x0 0xff500000 0x0 0x10    513                 reg = <0x0 0xff500000 0x0 0x100>;
501                 interrupts = <GIC_SPI 24 IRQ_T    514                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
502                 clocks = <&cru HCLK_HOST0>;       515                 clocks = <&cru HCLK_HOST0>;
                                                   >> 516                 clock-names = "usbhost";
503                 status = "disabled";              517                 status = "disabled";
504         };                                        518         };
505                                                   519 
506         usb_otg: usb@ff580000 {                   520         usb_otg: usb@ff580000 {
507                 compatible = "rockchip,rk3368-    521                 compatible = "rockchip,rk3368-usb", "rockchip,rk3066-usb",
508                                 "snps,dwc2";      522                                 "snps,dwc2";
509                 reg = <0x0 0xff580000 0x0 0x40    523                 reg = <0x0 0xff580000 0x0 0x40000>;
510                 interrupts = <GIC_SPI 23 IRQ_T    524                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
511                 clocks = <&cru HCLK_OTG0>;        525                 clocks = <&cru HCLK_OTG0>;
512                 clock-names = "otg";              526                 clock-names = "otg";
513                 dr_mode = "otg";                  527                 dr_mode = "otg";
514                 g-np-tx-fifo-size = <16>;         528                 g-np-tx-fifo-size = <16>;
515                 g-rx-fifo-size = <275>;           529                 g-rx-fifo-size = <275>;
516                 g-tx-fifo-size = <256 128 128     530                 g-tx-fifo-size = <256 128 128 64 64 32>;
517                 status = "disabled";              531                 status = "disabled";
518         };                                        532         };
519                                                   533 
520         dmac_bus: dma-controller@ff600000 {    << 
521                 compatible = "arm,pl330", "arm << 
522                 reg = <0x0 0xff600000 0x0 0x40 << 
523                 interrupts = <GIC_SPI 0 IRQ_TY << 
524                              <GIC_SPI 1 IRQ_TY << 
525                 #dma-cells = <1>;              << 
526                 arm,pl330-broken-no-flushp;    << 
527                 arm,pl330-periph-burst;        << 
528                 clocks = <&cru ACLK_DMAC_BUS>; << 
529                 clock-names = "apb_pclk";      << 
530         };                                     << 
531                                                << 
532         i2c0: i2c@ff650000 {                      534         i2c0: i2c@ff650000 {
533                 compatible = "rockchip,rk3368-    535                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
534                 reg = <0x0 0xff650000 0x0 0x10    536                 reg = <0x0 0xff650000 0x0 0x1000>;
535                 clocks = <&cru PCLK_I2C0>;        537                 clocks = <&cru PCLK_I2C0>;
536                 clock-names = "i2c";              538                 clock-names = "i2c";
537                 interrupts = <GIC_SPI 60 IRQ_T    539                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
538                 pinctrl-names = "default";        540                 pinctrl-names = "default";
539                 pinctrl-0 = <&i2c0_xfer>;         541                 pinctrl-0 = <&i2c0_xfer>;
540                 #address-cells = <1>;             542                 #address-cells = <1>;
541                 #size-cells = <0>;                543                 #size-cells = <0>;
542                 status = "disabled";              544                 status = "disabled";
543         };                                        545         };
544                                                   546 
545         i2c1: i2c@ff660000 {                      547         i2c1: i2c@ff660000 {
546                 compatible = "rockchip,rk3368-    548                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
547                 reg = <0x0 0xff660000 0x0 0x10    549                 reg = <0x0 0xff660000 0x0 0x1000>;
548                 interrupts = <GIC_SPI 61 IRQ_T    550                 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
549                 #address-cells = <1>;             551                 #address-cells = <1>;
550                 #size-cells = <0>;                552                 #size-cells = <0>;
551                 clock-names = "i2c";              553                 clock-names = "i2c";
552                 clocks = <&cru PCLK_I2C1>;        554                 clocks = <&cru PCLK_I2C1>;
553                 pinctrl-names = "default";        555                 pinctrl-names = "default";
554                 pinctrl-0 = <&i2c1_xfer>;         556                 pinctrl-0 = <&i2c1_xfer>;
555                 status = "disabled";              557                 status = "disabled";
556         };                                        558         };
557                                                   559 
558         pwm0: pwm@ff680000 {                      560         pwm0: pwm@ff680000 {
559                 compatible = "rockchip,rk3368-    561                 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
560                 reg = <0x0 0xff680000 0x0 0x10    562                 reg = <0x0 0xff680000 0x0 0x10>;
561                 #pwm-cells = <3>;                 563                 #pwm-cells = <3>;
562                 pinctrl-names = "default";        564                 pinctrl-names = "default";
563                 pinctrl-0 = <&pwm0_pin>;          565                 pinctrl-0 = <&pwm0_pin>;
564                 clocks = <&cru PCLK_PWM1>;        566                 clocks = <&cru PCLK_PWM1>;
                                                   >> 567                 clock-names = "pwm";
565                 status = "disabled";              568                 status = "disabled";
566         };                                        569         };
567                                                   570 
568         pwm1: pwm@ff680010 {                      571         pwm1: pwm@ff680010 {
569                 compatible = "rockchip,rk3368-    572                 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
570                 reg = <0x0 0xff680010 0x0 0x10    573                 reg = <0x0 0xff680010 0x0 0x10>;
571                 #pwm-cells = <3>;                 574                 #pwm-cells = <3>;
572                 pinctrl-names = "default";        575                 pinctrl-names = "default";
573                 pinctrl-0 = <&pwm1_pin>;          576                 pinctrl-0 = <&pwm1_pin>;
574                 clocks = <&cru PCLK_PWM1>;        577                 clocks = <&cru PCLK_PWM1>;
                                                   >> 578                 clock-names = "pwm";
575                 status = "disabled";              579                 status = "disabled";
576         };                                        580         };
577                                                   581 
578         pwm2: pwm@ff680020 {                      582         pwm2: pwm@ff680020 {
579                 compatible = "rockchip,rk3368-    583                 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
580                 reg = <0x0 0xff680020 0x0 0x10    584                 reg = <0x0 0xff680020 0x0 0x10>;
581                 #pwm-cells = <3>;                 585                 #pwm-cells = <3>;
582                 clocks = <&cru PCLK_PWM1>;        586                 clocks = <&cru PCLK_PWM1>;
                                                   >> 587                 clock-names = "pwm";
583                 status = "disabled";              588                 status = "disabled";
584         };                                        589         };
585                                                   590 
586         pwm3: pwm@ff680030 {                      591         pwm3: pwm@ff680030 {
587                 compatible = "rockchip,rk3368-    592                 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
588                 reg = <0x0 0xff680030 0x0 0x10    593                 reg = <0x0 0xff680030 0x0 0x10>;
589                 #pwm-cells = <3>;                 594                 #pwm-cells = <3>;
590                 pinctrl-names = "default";        595                 pinctrl-names = "default";
591                 pinctrl-0 = <&pwm3_pin>;          596                 pinctrl-0 = <&pwm3_pin>;
592                 clocks = <&cru PCLK_PWM1>;        597                 clocks = <&cru PCLK_PWM1>;
                                                   >> 598                 clock-names = "pwm";
593                 status = "disabled";              599                 status = "disabled";
594         };                                        600         };
595                                                   601 
596         uart2: serial@ff690000 {                  602         uart2: serial@ff690000 {
597                 compatible = "rockchip,rk3368-    603                 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
598                 reg = <0x0 0xff690000 0x0 0x10    604                 reg = <0x0 0xff690000 0x0 0x100>;
599                 clocks = <&cru SCLK_UART2>, <&    605                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
600                 clock-names = "baudclk", "apb_    606                 clock-names = "baudclk", "apb_pclk";
601                 interrupts = <GIC_SPI 57 IRQ_T    607                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
602                 pinctrl-names = "default";        608                 pinctrl-names = "default";
603                 pinctrl-0 = <&uart2_xfer>;        609                 pinctrl-0 = <&uart2_xfer>;
604                 reg-shift = <2>;                  610                 reg-shift = <2>;
605                 reg-io-width = <4>;               611                 reg-io-width = <4>;
606                 status = "disabled";              612                 status = "disabled";
607         };                                        613         };
608                                                   614 
609         mbox: mbox@ff6b0000 {                     615         mbox: mbox@ff6b0000 {
610                 compatible = "rockchip,rk3368-    616                 compatible = "rockchip,rk3368-mailbox";
611                 reg = <0x0 0xff6b0000 0x0 0x10    617                 reg = <0x0 0xff6b0000 0x0 0x1000>;
612                 interrupts = <GIC_SPI 146 IRQ_    618                 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
613                              <GIC_SPI 147 IRQ_    619                              <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
614                              <GIC_SPI 148 IRQ_    620                              <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
615                              <GIC_SPI 149 IRQ_    621                              <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
616                 clocks = <&cru PCLK_MAILBOX>;     622                 clocks = <&cru PCLK_MAILBOX>;
617                 clock-names = "pclk_mailbox";     623                 clock-names = "pclk_mailbox";
618                 #mbox-cells = <1>;                624                 #mbox-cells = <1>;
619                 status = "disabled";              625                 status = "disabled";
620         };                                        626         };
621                                                   627 
622         pmu: power-management@ff730000 {       << 
623                 compatible = "rockchip,rk3368- << 
624                 reg = <0x0 0xff730000 0x0 0x10 << 
625                                                << 
626                 power: power-controller {      << 
627                         compatible = "rockchip << 
628                         #power-domain-cells =  << 
629                         #address-cells = <1>;  << 
630                         #size-cells = <0>;     << 
631                                                << 
632                         /*                     << 
633                          * Note: Although SCLK << 
634                          * of device without i << 
635                          * synchronous reset.  << 
636                          *                     << 
637                          * The clocks on the w << 
638                          * ACLK_IEP/ACLK_VIP/A << 
639                          * ACLK_ISP/ACLK_VOP1  << 
640                          * ACLK_RGA is on ACLK << 
641                          * The others (HCLK_*, << 
642                          *                     << 
643                          * Which clock are dev << 
644                          *      clocks         << 
645                          *      *_IEP          << 
646                          *      *_ISP          << 
647                          *      *_VIP          << 
648                          *      *_VOP*         << 
649                          *      *_RGA          << 
650                          *      *_EDP*         << 
651                          *      *_DPHY*        << 
652                          *      *_HDMI         << 
653                          *      *_MIPI_*       << 
654                          */                    << 
655                         power-domain@RK3368_PD << 
656                                 reg = <RK3368_ << 
657                                 clocks = <&cru << 
658                                          <&cru << 
659                                          <&cru << 
660                                          <&cru << 
661                                          <&cru << 
662                                          <&cru << 
663                                          <&cru << 
664                                          <&cru << 
665                                          <&cru << 
666                                          <&cru << 
667                                          <&cru << 
668                                          <&cru << 
669                                          <&cru << 
670                                          <&cru << 
671                                          <&cru << 
672                                          <&cru << 
673                                          <&cru << 
674                                          <&cru << 
675                                          <&cru << 
676                                          <&cru << 
677                                          <&cru << 
678                                          <&cru << 
679                                          <&cru << 
680                                          <&cru << 
681                                          <&cru << 
682                                          <&cru << 
683                                          <&cru << 
684                                          <&cru << 
685                                          <&cru << 
686                                          <&cru << 
687                                 pm_qos = <&qos << 
688                                          <&qos << 
689                                          <&qos << 
690                                          <&qos << 
691                                          <&qos << 
692                                          <&qos << 
693                                          <&qos << 
694                                          <&qos << 
695                                          <&qos << 
696                                 #power-domain- << 
697                         };                     << 
698                                                << 
699                         /*                     << 
700                          * Note: ACLK_VCODEC/H << 
701                          * (video endecoder &  << 
702                          * ACLK_VCODEC_NIU and << 
703                          */                    << 
704                         power-domain@RK3368_PD << 
705                                 reg = <RK3368_ << 
706                                 clocks = <&cru << 
707                                          <&cru << 
708                                          <&cru << 
709                                          <&cru << 
710                                 pm_qos = <&qos << 
711                                          <&qos << 
712                                          <&qos << 
713                                 #power-domain- << 
714                         };                     << 
715                                                << 
716                         /*                     << 
717                          * Note: ACLK_GPU is t << 
718                          * and on the ACLK_GPU << 
719                          */                    << 
720                         power-domain@RK3368_PD << 
721                                 reg = <RK3368_ << 
722                                 clocks = <&cru << 
723                                          <&cru << 
724                                          <&cru << 
725                                 pm_qos = <&qos << 
726                                 #power-domain- << 
727                         };                     << 
728                 };                             << 
729         };                                     << 
730                                                << 
731         pmugrf: syscon@ff738000 {                 628         pmugrf: syscon@ff738000 {
732                 compatible = "rockchip,rk3368-    629                 compatible = "rockchip,rk3368-pmugrf", "syscon", "simple-mfd";
733                 reg = <0x0 0xff738000 0x0 0x10    630                 reg = <0x0 0xff738000 0x0 0x1000>;
734                                                   631 
735                 pmu_io_domains: io-domains {      632                 pmu_io_domains: io-domains {
736                         compatible = "rockchip    633                         compatible = "rockchip,rk3368-pmu-io-voltage-domain";
737                         status = "disabled";      634                         status = "disabled";
738                 };                                635                 };
739                                                   636 
740                 reboot-mode {                     637                 reboot-mode {
741                         compatible = "syscon-r    638                         compatible = "syscon-reboot-mode";
742                         offset = <0x200>;         639                         offset = <0x200>;
743                         mode-normal = <BOOT_NO    640                         mode-normal = <BOOT_NORMAL>;
744                         mode-recovery = <BOOT_    641                         mode-recovery = <BOOT_RECOVERY>;
745                         mode-bootloader = <BOO    642                         mode-bootloader = <BOOT_FASTBOOT>;
746                         mode-loader = <BOOT_BL    643                         mode-loader = <BOOT_BL_DOWNLOAD>;
747                 };                                644                 };
748         };                                        645         };
749                                                   646 
750         cru: clock-controller@ff760000 {          647         cru: clock-controller@ff760000 {
751                 compatible = "rockchip,rk3368-    648                 compatible = "rockchip,rk3368-cru";
752                 reg = <0x0 0xff760000 0x0 0x10    649                 reg = <0x0 0xff760000 0x0 0x1000>;
753                 clocks = <&xin24m>;            << 
754                 clock-names = "xin24m";        << 
755                 rockchip,grf = <&grf>;            650                 rockchip,grf = <&grf>;
756                 #clock-cells = <1>;               651                 #clock-cells = <1>;
757                 #reset-cells = <1>;               652                 #reset-cells = <1>;
758         };                                        653         };
759                                                   654 
760         grf: syscon@ff770000 {                    655         grf: syscon@ff770000 {
761                 compatible = "rockchip,rk3368-    656                 compatible = "rockchip,rk3368-grf", "syscon", "simple-mfd";
762                 reg = <0x0 0xff770000 0x0 0x10    657                 reg = <0x0 0xff770000 0x0 0x1000>;
763                                                   658 
764                 io_domains: io-domains {          659                 io_domains: io-domains {
765                         compatible = "rockchip    660                         compatible = "rockchip,rk3368-io-voltage-domain";
766                         status = "disabled";      661                         status = "disabled";
767                 };                                662                 };
768         };                                        663         };
769                                                   664 
770         wdt: watchdog@ff800000 {                  665         wdt: watchdog@ff800000 {
771                 compatible = "rockchip,rk3368-    666                 compatible = "rockchip,rk3368-wdt", "snps,dw-wdt";
772                 reg = <0x0 0xff800000 0x0 0x10    667                 reg = <0x0 0xff800000 0x0 0x100>;
773                 clocks = <&cru PCLK_WDT>;         668                 clocks = <&cru PCLK_WDT>;
774                 interrupts = <GIC_SPI 79 IRQ_T    669                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
775                 status = "disabled";              670                 status = "disabled";
776         };                                        671         };
777                                                   672 
778         timer0: timer@ff810000 {               !! 673         timer@ff810000 {
779                 compatible = "rockchip,rk3368-    674                 compatible = "rockchip,rk3368-timer", "rockchip,rk3288-timer";
780                 reg = <0x0 0xff810000 0x0 0x20    675                 reg = <0x0 0xff810000 0x0 0x20>;
781                 interrupts = <GIC_SPI 66 IRQ_T    676                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
782                 clocks = <&cru PCLK_TIMER0>, < << 
783                 clock-names = "pclk", "timer"; << 
784         };                                        677         };
785                                                   678 
786         spdif: spdif@ff880000 {                   679         spdif: spdif@ff880000 {
787                 compatible = "rockchip,rk3368-    680                 compatible = "rockchip,rk3368-spdif";
788                 reg = <0x0 0xff880000 0x0 0x10    681                 reg = <0x0 0xff880000 0x0 0x1000>;
789                 interrupts = <GIC_SPI 54 IRQ_T    682                 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
790                 clocks = <&cru SCLK_SPDIF_8CH>    683                 clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>;
791                 clock-names = "mclk", "hclk";     684                 clock-names = "mclk", "hclk";
792                 dmas = <&dmac_bus 3>;             685                 dmas = <&dmac_bus 3>;
793                 dma-names = "tx";                 686                 dma-names = "tx";
794                 pinctrl-names = "default";        687                 pinctrl-names = "default";
795                 pinctrl-0 = <&spdif_tx>;          688                 pinctrl-0 = <&spdif_tx>;
796                 #sound-dai-cells = <0>;        << 
797                 status = "disabled";              689                 status = "disabled";
798         };                                        690         };
799                                                   691 
800         i2s_2ch: i2s-2ch@ff890000 {               692         i2s_2ch: i2s-2ch@ff890000 {
801                 compatible = "rockchip,rk3368-    693                 compatible = "rockchip,rk3368-i2s", "rockchip,rk3066-i2s";
802                 reg = <0x0 0xff890000 0x0 0x10    694                 reg = <0x0 0xff890000 0x0 0x1000>;
803                 interrupts = <GIC_SPI 40 IRQ_T    695                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
804                 clock-names = "i2s_clk", "i2s_    696                 clock-names = "i2s_clk", "i2s_hclk";
805                 clocks = <&cru SCLK_I2S_2CH>,     697                 clocks = <&cru SCLK_I2S_2CH>, <&cru HCLK_I2S_2CH>;
806                 dmas = <&dmac_bus 6>, <&dmac_b    698                 dmas = <&dmac_bus 6>, <&dmac_bus 7>;
807                 dma-names = "tx", "rx";           699                 dma-names = "tx", "rx";
808                 #sound-dai-cells = <0>;        << 
809                 status = "disabled";              700                 status = "disabled";
810         };                                        701         };
811                                                   702 
812         i2s_8ch: i2s-8ch@ff898000 {               703         i2s_8ch: i2s-8ch@ff898000 {
813                 compatible = "rockchip,rk3368-    704                 compatible = "rockchip,rk3368-i2s", "rockchip,rk3066-i2s";
814                 reg = <0x0 0xff898000 0x0 0x10    705                 reg = <0x0 0xff898000 0x0 0x1000>;
815                 interrupts = <GIC_SPI 53 IRQ_T    706                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
816                 clock-names = "i2s_clk", "i2s_    707                 clock-names = "i2s_clk", "i2s_hclk";
817                 clocks = <&cru SCLK_I2S_8CH>,     708                 clocks = <&cru SCLK_I2S_8CH>, <&cru HCLK_I2S_8CH>;
818                 dmas = <&dmac_bus 0>, <&dmac_b    709                 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
819                 dma-names = "tx", "rx";           710                 dma-names = "tx", "rx";
820                 pinctrl-names = "default";        711                 pinctrl-names = "default";
821                 pinctrl-0 = <&i2s_8ch_bus>;       712                 pinctrl-0 = <&i2s_8ch_bus>;
822                 #sound-dai-cells = <0>;        << 
823                 status = "disabled";              713                 status = "disabled";
824         };                                        714         };
825                                                   715 
826         iep_mmu: iommu@ff900800 {                 716         iep_mmu: iommu@ff900800 {
827                 compatible = "rockchip,iommu";    717                 compatible = "rockchip,iommu";
828                 reg = <0x0 0xff900800 0x0 0x10    718                 reg = <0x0 0xff900800 0x0 0x100>;
829                 interrupts = <GIC_SPI 17 IRQ_T    719                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
                                                   >> 720                 interrupt-names = "iep_mmu";
830                 clocks = <&cru ACLK_IEP>, <&cr    721                 clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
831                 clock-names = "aclk", "iface";    722                 clock-names = "aclk", "iface";
832                 power-domains = <&power RK3368 << 
833                 #iommu-cells = <0>;               723                 #iommu-cells = <0>;
834                 status = "disabled";              724                 status = "disabled";
835         };                                        725         };
836                                                   726 
837         isp_mmu: iommu@ff914000 {                 727         isp_mmu: iommu@ff914000 {
838                 compatible = "rockchip,iommu";    728                 compatible = "rockchip,iommu";
839                 reg = <0x0 0xff914000 0x0 0x10    729                 reg = <0x0 0xff914000 0x0 0x100>,
840                       <0x0 0xff915000 0x0 0x10    730                       <0x0 0xff915000 0x0 0x100>;
841                 interrupts = <GIC_SPI 14 IRQ_T    731                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
                                                   >> 732                 interrupt-names = "isp_mmu";
842                 clocks = <&cru ACLK_ISP>, <&cr    733                 clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>;
843                 clock-names = "aclk", "iface";    734                 clock-names = "aclk", "iface";
844                 #iommu-cells = <0>;               735                 #iommu-cells = <0>;
845                 power-domains = <&power RK3368 << 
846                 rockchip,disable-mmu-reset;       736                 rockchip,disable-mmu-reset;
847                 status = "disabled";              737                 status = "disabled";
848         };                                        738         };
849                                                   739 
850         vop_mmu: iommu@ff930300 {                 740         vop_mmu: iommu@ff930300 {
851                 compatible = "rockchip,iommu";    741                 compatible = "rockchip,iommu";
852                 reg = <0x0 0xff930300 0x0 0x10    742                 reg = <0x0 0xff930300 0x0 0x100>;
853                 interrupts = <GIC_SPI 15 IRQ_T    743                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
                                                   >> 744                 interrupt-names = "vop_mmu";
854                 clocks = <&cru ACLK_VOP>, <&cr    745                 clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
855                 clock-names = "aclk", "iface";    746                 clock-names = "aclk", "iface";
856                 power-domains = <&power RK3368 << 
857                 #iommu-cells = <0>;               747                 #iommu-cells = <0>;
858                 status = "disabled";              748                 status = "disabled";
859         };                                        749         };
860                                                   750 
861         hevc_mmu: iommu@ff9a0440 {                751         hevc_mmu: iommu@ff9a0440 {
862                 compatible = "rockchip,iommu";    752                 compatible = "rockchip,iommu";
863                 reg = <0x0 0xff9a0440 0x0 0x40    753                 reg = <0x0 0xff9a0440 0x0 0x40>,
864                       <0x0 0xff9a0480 0x0 0x40    754                       <0x0 0xff9a0480 0x0 0x40>;
865                 interrupts = <GIC_SPI 12 IRQ_T    755                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
                                                   >> 756                 interrupt-names = "hevc_mmu";
866                 clocks = <&cru ACLK_VIDEO>, <&    757                 clocks = <&cru ACLK_VIDEO>, <&cru HCLK_VIDEO>;
867                 clock-names = "aclk", "iface";    758                 clock-names = "aclk", "iface";
868                 #iommu-cells = <0>;               759                 #iommu-cells = <0>;
869                 status = "disabled";              760                 status = "disabled";
870         };                                        761         };
871                                                   762 
872         vpu_mmu: iommu@ff9a0800 {                 763         vpu_mmu: iommu@ff9a0800 {
873                 compatible = "rockchip,iommu";    764                 compatible = "rockchip,iommu";
874                 reg = <0x0 0xff9a0800 0x0 0x10    765                 reg = <0x0 0xff9a0800 0x0 0x100>;
875                 interrupts = <GIC_SPI 9 IRQ_TY    766                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
876                              <GIC_SPI 10 IRQ_T    767                              <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
                                                   >> 768                 interrupt-names = "vepu_mmu", "vdpu_mmu";
877                 clocks = <&cru ACLK_VIDEO>, <&    769                 clocks = <&cru ACLK_VIDEO>, <&cru HCLK_VIDEO>;
878                 clock-names = "aclk", "iface";    770                 clock-names = "aclk", "iface";
879                 #iommu-cells = <0>;               771                 #iommu-cells = <0>;
880                 status = "disabled";              772                 status = "disabled";
881         };                                        773         };
882                                                   774 
883         qos_iep: qos@ffad0000 {                << 
884                 compatible = "rockchip,rk3368- << 
885                 reg = <0x0 0xffad0000 0x0 0x20 << 
886         };                                     << 
887                                                << 
888         qos_isp_r0: qos@ffad0080 {             << 
889                 compatible = "rockchip,rk3368- << 
890                 reg = <0x0 0xffad0080 0x0 0x20 << 
891         };                                     << 
892                                                << 
893         qos_isp_r1: qos@ffad0100 {             << 
894                 compatible = "rockchip,rk3368- << 
895                 reg = <0x0 0xffad0100 0x0 0x20 << 
896         };                                     << 
897                                                << 
898         qos_isp_w0: qos@ffad0180 {             << 
899                 compatible = "rockchip,rk3368- << 
900                 reg = <0x0 0xffad0180 0x0 0x20 << 
901         };                                     << 
902                                                << 
903         qos_isp_w1: qos@ffad0200 {             << 
904                 compatible = "rockchip,rk3368- << 
905                 reg = <0x0 0xffad0200 0x0 0x20 << 
906         };                                     << 
907                                                << 
908         qos_vip: qos@ffad0280 {                << 
909                 compatible = "rockchip,rk3368- << 
910                 reg = <0x0 0xffad0280 0x0 0x20 << 
911         };                                     << 
912                                                << 
913         qos_vop: qos@ffad0300 {                << 
914                 compatible = "rockchip,rk3368- << 
915                 reg = <0x0 0xffad0300 0x0 0x20 << 
916         };                                     << 
917                                                << 
918         qos_rga_r: qos@ffad0380 {              << 
919                 compatible = "rockchip,rk3368- << 
920                 reg = <0x0 0xffad0380 0x0 0x20 << 
921         };                                     << 
922                                                << 
923         qos_rga_w: qos@ffad0400 {              << 
924                 compatible = "rockchip,rk3368- << 
925                 reg = <0x0 0xffad0400 0x0 0x20 << 
926         };                                     << 
927                                                << 
928         qos_hevc_r: qos@ffae0000 {             << 
929                 compatible = "rockchip,rk3368- << 
930                 reg = <0x0 0xffae0000 0x0 0x20 << 
931         };                                     << 
932                                                << 
933         qos_vpu_r: qos@ffae0100 {              << 
934                 compatible = "rockchip,rk3368- << 
935                 reg = <0x0 0xffae0100 0x0 0x20 << 
936         };                                     << 
937                                                << 
938         qos_vpu_w: qos@ffae0180 {              << 
939                 compatible = "rockchip,rk3368- << 
940                 reg = <0x0 0xffae0180 0x0 0x20 << 
941         };                                     << 
942                                                << 
943         qos_gpu: qos@ffaf0000 {                << 
944                 compatible = "rockchip,rk3368- << 
945                 reg = <0x0 0xffaf0000 0x0 0x20 << 
946         };                                     << 
947                                                << 
948         efuse256: efuse@ffb00000 {                775         efuse256: efuse@ffb00000 {
949                 compatible = "rockchip,rk3368-    776                 compatible = "rockchip,rk3368-efuse";
950                 reg = <0x0 0xffb00000 0x0 0x20    777                 reg = <0x0 0xffb00000 0x0 0x20>;
951                 #address-cells = <1>;             778                 #address-cells = <1>;
952                 #size-cells = <1>;                779                 #size-cells = <1>;
953                 clocks = <&cru PCLK_EFUSE256>;    780                 clocks = <&cru PCLK_EFUSE256>;
954                 clock-names = "pclk_efuse";       781                 clock-names = "pclk_efuse";
955                                                   782 
956                 cpu_leakage: cpu-leakage@17 {     783                 cpu_leakage: cpu-leakage@17 {
957                         reg = <0x17 0x1>;         784                         reg = <0x17 0x1>;
958                 };                                785                 };
959                 temp_adjust: temp-adjust@1f {     786                 temp_adjust: temp-adjust@1f {
960                         reg = <0x1f 0x1>;         787                         reg = <0x1f 0x1>;
961                 };                                788                 };
962         };                                        789         };
963                                                   790 
964         gic: interrupt-controller@ffb71000 {      791         gic: interrupt-controller@ffb71000 {
965                 compatible = "arm,gic-400";       792                 compatible = "arm,gic-400";
966                 interrupt-controller;             793                 interrupt-controller;
967                 #interrupt-cells = <3>;           794                 #interrupt-cells = <3>;
968                 #address-cells = <0>;             795                 #address-cells = <0>;
969                                                   796 
970                 reg = <0x0 0xffb71000 0x0 0x10    797                 reg = <0x0 0xffb71000 0x0 0x1000>,
971                       <0x0 0xffb72000 0x0 0x20    798                       <0x0 0xffb72000 0x0 0x2000>,
972                       <0x0 0xffb74000 0x0 0x20    799                       <0x0 0xffb74000 0x0 0x2000>,
973                       <0x0 0xffb76000 0x0 0x20    800                       <0x0 0xffb76000 0x0 0x2000>;
974                 interrupts = <GIC_PPI 9           801                 interrupts = <GIC_PPI 9
975                       (GIC_CPU_MASK_SIMPLE(8)     802                       (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
976         };                                        803         };
977                                                   804 
978         pinctrl: pinctrl {                        805         pinctrl: pinctrl {
979                 compatible = "rockchip,rk3368-    806                 compatible = "rockchip,rk3368-pinctrl";
980                 rockchip,grf = <&grf>;            807                 rockchip,grf = <&grf>;
981                 rockchip,pmu = <&pmugrf>;         808                 rockchip,pmu = <&pmugrf>;
982                 #address-cells = <0x2>;           809                 #address-cells = <0x2>;
983                 #size-cells = <0x2>;              810                 #size-cells = <0x2>;
984                 ranges;                           811                 ranges;
985                                                   812 
986                 gpio0: gpio@ff750000 {         !! 813                 gpio0: gpio0@ff750000 {
987                         compatible = "rockchip    814                         compatible = "rockchip,gpio-bank";
988                         reg = <0x0 0xff750000     815                         reg = <0x0 0xff750000 0x0 0x100>;
989                         clocks = <&cru PCLK_GP    816                         clocks = <&cru PCLK_GPIO0>;
990                         interrupts = <GIC_SPI     817                         interrupts = <GIC_SPI 0x51 IRQ_TYPE_LEVEL_HIGH>;
991                                                   818 
992                         gpio-controller;          819                         gpio-controller;
993                         #gpio-cells = <0x2>;      820                         #gpio-cells = <0x2>;
994                                                   821 
995                         interrupt-controller;     822                         interrupt-controller;
996                         #interrupt-cells = <0x    823                         #interrupt-cells = <0x2>;
997                 };                                824                 };
998                                                   825 
999                 gpio1: gpio@ff780000 {         !! 826                 gpio1: gpio1@ff780000 {
1000                         compatible = "rockchi    827                         compatible = "rockchip,gpio-bank";
1001                         reg = <0x0 0xff780000    828                         reg = <0x0 0xff780000 0x0 0x100>;
1002                         clocks = <&cru PCLK_G    829                         clocks = <&cru PCLK_GPIO1>;
1003                         interrupts = <GIC_SPI    830                         interrupts = <GIC_SPI 0x52 IRQ_TYPE_LEVEL_HIGH>;
1004                                                  831 
1005                         gpio-controller;         832                         gpio-controller;
1006                         #gpio-cells = <0x2>;     833                         #gpio-cells = <0x2>;
1007                                                  834 
1008                         interrupt-controller;    835                         interrupt-controller;
1009                         #interrupt-cells = <0    836                         #interrupt-cells = <0x2>;
1010                 };                               837                 };
1011                                                  838 
1012                 gpio2: gpio@ff790000 {        !! 839                 gpio2: gpio2@ff790000 {
1013                         compatible = "rockchi    840                         compatible = "rockchip,gpio-bank";
1014                         reg = <0x0 0xff790000    841                         reg = <0x0 0xff790000 0x0 0x100>;
1015                         clocks = <&cru PCLK_G    842                         clocks = <&cru PCLK_GPIO2>;
1016                         interrupts = <GIC_SPI    843                         interrupts = <GIC_SPI 0x53 IRQ_TYPE_LEVEL_HIGH>;
1017                                                  844 
1018                         gpio-controller;         845                         gpio-controller;
1019                         #gpio-cells = <0x2>;     846                         #gpio-cells = <0x2>;
1020                                                  847 
1021                         interrupt-controller;    848                         interrupt-controller;
1022                         #interrupt-cells = <0    849                         #interrupt-cells = <0x2>;
1023                 };                               850                 };
1024                                                  851 
1025                 gpio3: gpio@ff7a0000 {        !! 852                 gpio3: gpio3@ff7a0000 {
1026                         compatible = "rockchi    853                         compatible = "rockchip,gpio-bank";
1027                         reg = <0x0 0xff7a0000    854                         reg = <0x0 0xff7a0000 0x0 0x100>;
1028                         clocks = <&cru PCLK_G    855                         clocks = <&cru PCLK_GPIO3>;
1029                         interrupts = <GIC_SPI    856                         interrupts = <GIC_SPI 0x54 IRQ_TYPE_LEVEL_HIGH>;
1030                                                  857 
1031                         gpio-controller;         858                         gpio-controller;
1032                         #gpio-cells = <0x2>;     859                         #gpio-cells = <0x2>;
1033                                                  860 
1034                         interrupt-controller;    861                         interrupt-controller;
1035                         #interrupt-cells = <0    862                         #interrupt-cells = <0x2>;
1036                 };                               863                 };
1037                                                  864 
1038                 pcfg_pull_up: pcfg-pull-up {     865                 pcfg_pull_up: pcfg-pull-up {
1039                         bias-pull-up;            866                         bias-pull-up;
1040                 };                               867                 };
1041                                                  868 
1042                 pcfg_pull_down: pcfg-pull-dow    869                 pcfg_pull_down: pcfg-pull-down {
1043                         bias-pull-down;          870                         bias-pull-down;
1044                 };                               871                 };
1045                                                  872 
1046                 pcfg_pull_none: pcfg-pull-non    873                 pcfg_pull_none: pcfg-pull-none {
1047                         bias-disable;            874                         bias-disable;
1048                 };                               875                 };
1049                                                  876 
1050                 pcfg_pull_none_12ma: pcfg-pul    877                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1051                         bias-disable;            878                         bias-disable;
1052                         drive-strength = <12>    879                         drive-strength = <12>;
1053                 };                               880                 };
1054                                                  881 
1055                 emmc {                           882                 emmc {
1056                         emmc_clk: emmc-clk {     883                         emmc_clk: emmc-clk {
1057                                 rockchip,pins    884                                 rockchip,pins = <2 RK_PA4 2 &pcfg_pull_none>;
1058                         };                       885                         };
1059                                                  886 
1060                         emmc_cmd: emmc-cmd {     887                         emmc_cmd: emmc-cmd {
1061                                 rockchip,pins    888                                 rockchip,pins = <1 RK_PD2 2 &pcfg_pull_up>;
1062                         };                       889                         };
1063                                                  890 
1064                         emmc_pwr: emmc-pwr {     891                         emmc_pwr: emmc-pwr {
1065                                 rockchip,pins    892                                 rockchip,pins = <1 RK_PD3 2 &pcfg_pull_up>;
1066                         };                       893                         };
1067                                                  894 
1068                         emmc_bus1: emmc-bus1     895                         emmc_bus1: emmc-bus1 {
1069                                 rockchip,pins    896                                 rockchip,pins = <1 RK_PC2 2 &pcfg_pull_up>;
1070                         };                       897                         };
1071                                                  898 
1072                         emmc_bus4: emmc-bus4     899                         emmc_bus4: emmc-bus4 {
1073                                 rockchip,pins    900                                 rockchip,pins = <1 RK_PC2 2 &pcfg_pull_up>,
1074                                                  901                                                 <1 RK_PC3 2 &pcfg_pull_up>,
1075                                                  902                                                 <1 RK_PC4 2 &pcfg_pull_up>,
1076                                                  903                                                 <1 RK_PC5 2 &pcfg_pull_up>;
1077                         };                       904                         };
1078                                                  905 
1079                         emmc_bus8: emmc-bus8     906                         emmc_bus8: emmc-bus8 {
1080                                 rockchip,pins    907                                 rockchip,pins = <1 RK_PC2 2 &pcfg_pull_up>,
1081                                                  908                                                 <1 RK_PC3 2 &pcfg_pull_up>,
1082                                                  909                                                 <1 RK_PC4 2 &pcfg_pull_up>,
1083                                                  910                                                 <1 RK_PC5 2 &pcfg_pull_up>,
1084                                                  911                                                 <1 RK_PC6 2 &pcfg_pull_up>,
1085                                                  912                                                 <1 RK_PC7 2 &pcfg_pull_up>,
1086                                                  913                                                 <1 RK_PD0 2 &pcfg_pull_up>,
1087                                                  914                                                 <1 RK_PD1 2 &pcfg_pull_up>;
1088                         };                       915                         };
1089                 };                               916                 };
1090                                                  917 
1091                 gmac {                           918                 gmac {
1092                         rgmii_pins: rgmii-pin    919                         rgmii_pins: rgmii-pins {
1093                                 rockchip,pins !! 920                                 rockchip,pins = <3 RK_PC6 1 &pcfg_pull_none>,
1094                                                  921                                                 <3 RK_PD0 1 &pcfg_pull_none>,
1095                                                  922                                                 <3 RK_PC3 1 &pcfg_pull_none>,
1096                                                  923                                                 <3 RK_PB0 1 &pcfg_pull_none_12ma>,
1097                                                  924                                                 <3 RK_PB1 1 &pcfg_pull_none_12ma>,
1098                                                  925                                                 <3 RK_PB2 1 &pcfg_pull_none_12ma>,
1099                                                  926                                                 <3 RK_PB6 1 &pcfg_pull_none_12ma>,
1100                                                  927                                                 <3 RK_PD4 1 &pcfg_pull_none_12ma>,
1101                                                  928                                                 <3 RK_PB5 1 &pcfg_pull_none_12ma>,
1102                                                  929                                                 <3 RK_PB7 1 &pcfg_pull_none>,
1103                                                  930                                                 <3 RK_PC0 1 &pcfg_pull_none>,
1104                                                  931                                                 <3 RK_PC1 1 &pcfg_pull_none>,
1105                                                  932                                                 <3 RK_PC2 1 &pcfg_pull_none>,
1106                                                  933                                                 <3 RK_PD1 1 &pcfg_pull_none>,
1107                                                  934                                                 <3 RK_PC4 1 &pcfg_pull_none>;
1108                         };                       935                         };
1109                                                  936 
1110                         rmii_pins: rmii-pins     937                         rmii_pins: rmii-pins {
1111                                 rockchip,pins !! 938                                 rockchip,pins = <3 RK_PC6 1 &pcfg_pull_none>,
1112                                                  939                                                 <3 RK_PD0 1 &pcfg_pull_none>,
1113                                                  940                                                 <3 RK_PC3 1 &pcfg_pull_none>,
1114                                                  941                                                 <3 RK_PB0 1 &pcfg_pull_none_12ma>,
1115                                                  942                                                 <3 RK_PB1 1 &pcfg_pull_none_12ma>,
1116                                                  943                                                 <3 RK_PB5 1 &pcfg_pull_none_12ma>,
1117                                                  944                                                 <3 RK_PB7 1 &pcfg_pull_none>,
1118                                                  945                                                 <3 RK_PC0 1 &pcfg_pull_none>,
1119                                                  946                                                 <3 RK_PC4 1 &pcfg_pull_none>,
1120                                                  947                                                 <3 RK_PC5 1 &pcfg_pull_none>;
1121                         };                       948                         };
1122                 };                               949                 };
1123                                                  950 
1124                 i2c0 {                           951                 i2c0 {
1125                         i2c0_xfer: i2c0-xfer     952                         i2c0_xfer: i2c0-xfer {
1126                                 rockchip,pins    953                                 rockchip,pins = <0 RK_PA6 1 &pcfg_pull_none>,
1127                                                  954                                                 <0 RK_PA7 1 &pcfg_pull_none>;
1128                         };                       955                         };
1129                 };                               956                 };
1130                                                  957 
1131                 i2c1 {                           958                 i2c1 {
1132                         i2c1_xfer: i2c1-xfer     959                         i2c1_xfer: i2c1-xfer {
1133                                 rockchip,pins    960                                 rockchip,pins = <2 RK_PC5 1 &pcfg_pull_none>,
1134                                                  961                                                 <2 RK_PC6 1 &pcfg_pull_none>;
1135                         };                       962                         };
1136                 };                               963                 };
1137                                                  964 
1138                 i2c2 {                           965                 i2c2 {
1139                         i2c2_xfer: i2c2-xfer     966                         i2c2_xfer: i2c2-xfer {
1140                                 rockchip,pins    967                                 rockchip,pins = <0 RK_PB1 2 &pcfg_pull_none>,
1141                                                  968                                                 <3 RK_PD7 2 &pcfg_pull_none>;
1142                         };                       969                         };
1143                 };                               970                 };
1144                                                  971 
1145                 i2c3 {                           972                 i2c3 {
1146                         i2c3_xfer: i2c3-xfer     973                         i2c3_xfer: i2c3-xfer {
1147                                 rockchip,pins    974                                 rockchip,pins = <1 RK_PC0 1 &pcfg_pull_none>,
1148                                                  975                                                 <1 RK_PC1 1 &pcfg_pull_none>;
1149                         };                       976                         };
1150                 };                               977                 };
1151                                                  978 
1152                 i2c4 {                           979                 i2c4 {
1153                         i2c4_xfer: i2c4-xfer     980                         i2c4_xfer: i2c4-xfer {
1154                                 rockchip,pins    981                                 rockchip,pins = <3 RK_PD0 2 &pcfg_pull_none>,
1155                                                  982                                                 <3 RK_PD1 2 &pcfg_pull_none>;
1156                         };                       983                         };
1157                 };                               984                 };
1158                                                  985 
1159                 i2c5 {                           986                 i2c5 {
1160                         i2c5_xfer: i2c5-xfer     987                         i2c5_xfer: i2c5-xfer {
1161                                 rockchip,pins    988                                 rockchip,pins = <3 RK_PD2 2 &pcfg_pull_none>,
1162                                                  989                                                 <3 RK_PD3 2 &pcfg_pull_none>;
1163                         };                       990                         };
1164                 };                               991                 };
1165                                                  992 
1166                 i2s {                            993                 i2s {
1167                         i2s_8ch_bus: i2s-8ch-    994                         i2s_8ch_bus: i2s-8ch-bus {
1168                                 rockchip,pins    995                                 rockchip,pins = <2 RK_PB4 1 &pcfg_pull_none>,
1169                                                  996                                                 <2 RK_PB5 1 &pcfg_pull_none>,
1170                                                  997                                                 <2 RK_PB6 1 &pcfg_pull_none>,
1171                                                  998                                                 <2 RK_PB7 1 &pcfg_pull_none>,
1172                                                  999                                                 <2 RK_PC0 1 &pcfg_pull_none>,
1173                                                  1000                                                 <2 RK_PC1 1 &pcfg_pull_none>,
1174                                                  1001                                                 <2 RK_PC2 1 &pcfg_pull_none>,
1175                                                  1002                                                 <2 RK_PC3 1 &pcfg_pull_none>,
1176                                                  1003                                                 <2 RK_PC4 1 &pcfg_pull_none>;
1177                         };                       1004                         };
1178                 };                               1005                 };
1179                                                  1006 
1180                 pwm0 {                           1007                 pwm0 {
1181                         pwm0_pin: pwm0-pin {     1008                         pwm0_pin: pwm0-pin {
1182                                 rockchip,pins    1009                                 rockchip,pins = <3 RK_PB0 2 &pcfg_pull_none>;
1183                         };                       1010                         };
1184                 };                               1011                 };
1185                                                  1012 
1186                 pwm1 {                           1013                 pwm1 {
1187                         pwm1_pin: pwm1-pin {     1014                         pwm1_pin: pwm1-pin {
1188                                 rockchip,pins    1015                                 rockchip,pins = <0 RK_PB0 2 &pcfg_pull_none>;
1189                         };                       1016                         };
1190                 };                               1017                 };
1191                                                  1018 
1192                 pwm3 {                           1019                 pwm3 {
1193                         pwm3_pin: pwm3-pin {     1020                         pwm3_pin: pwm3-pin {
1194                                 rockchip,pins    1021                                 rockchip,pins = <3 RK_PD5 3 &pcfg_pull_none>;
1195                         };                       1022                         };
1196                 };                               1023                 };
1197                                                  1024 
1198                 sdio0 {                          1025                 sdio0 {
1199                         sdio0_bus1: sdio0-bus    1026                         sdio0_bus1: sdio0-bus1 {
1200                                 rockchip,pins    1027                                 rockchip,pins = <2 RK_PD4 1 &pcfg_pull_up>;
1201                         };                       1028                         };
1202                                                  1029 
1203                         sdio0_bus4: sdio0-bus    1030                         sdio0_bus4: sdio0-bus4 {
1204                                 rockchip,pins    1031                                 rockchip,pins = <2 RK_PD4 1 &pcfg_pull_up>,
1205                                                  1032                                                 <2 RK_PD5 1 &pcfg_pull_up>,
1206                                                  1033                                                 <2 RK_PD6 1 &pcfg_pull_up>,
1207                                                  1034                                                 <2 RK_PD7 1 &pcfg_pull_up>;
1208                         };                       1035                         };
1209                                                  1036 
1210                         sdio0_cmd: sdio0-cmd     1037                         sdio0_cmd: sdio0-cmd {
1211                                 rockchip,pins    1038                                 rockchip,pins = <3 RK_PA0 1 &pcfg_pull_up>;
1212                         };                       1039                         };
1213                                                  1040 
1214                         sdio0_clk: sdio0-clk     1041                         sdio0_clk: sdio0-clk {
1215                                 rockchip,pins    1042                                 rockchip,pins = <3 RK_PA1 1 &pcfg_pull_none>;
1216                         };                       1043                         };
1217                                                  1044 
1218                         sdio0_cd: sdio0-cd {     1045                         sdio0_cd: sdio0-cd {
1219                                 rockchip,pins    1046                                 rockchip,pins = <3 RK_PA2 1 &pcfg_pull_up>;
1220                         };                       1047                         };
1221                                                  1048 
1222                         sdio0_wp: sdio0-wp {     1049                         sdio0_wp: sdio0-wp {
1223                                 rockchip,pins    1050                                 rockchip,pins = <3 RK_PA3 1 &pcfg_pull_up>;
1224                         };                       1051                         };
1225                                                  1052 
1226                         sdio0_pwr: sdio0-pwr     1053                         sdio0_pwr: sdio0-pwr {
1227                                 rockchip,pins    1054                                 rockchip,pins = <3 RK_PA4 1 &pcfg_pull_up>;
1228                         };                       1055                         };
1229                                                  1056 
1230                         sdio0_bkpwr: sdio0-bk    1057                         sdio0_bkpwr: sdio0-bkpwr {
1231                                 rockchip,pins    1058                                 rockchip,pins = <3 RK_PA5 1 &pcfg_pull_up>;
1232                         };                       1059                         };
1233                                                  1060 
1234                         sdio0_int: sdio0-int     1061                         sdio0_int: sdio0-int {
1235                                 rockchip,pins    1062                                 rockchip,pins = <3 RK_PA6 1 &pcfg_pull_up>;
1236                         };                       1063                         };
1237                 };                               1064                 };
1238                                                  1065 
1239                 sdmmc {                          1066                 sdmmc {
1240                         sdmmc_clk: sdmmc-clk     1067                         sdmmc_clk: sdmmc-clk {
1241                                 rockchip,pins    1068                                 rockchip,pins = <2 RK_PB1 1 &pcfg_pull_none>;
1242                         };                       1069                         };
1243                                                  1070 
1244                         sdmmc_cmd: sdmmc-cmd     1071                         sdmmc_cmd: sdmmc-cmd {
1245                                 rockchip,pins    1072                                 rockchip,pins = <2 RK_PB2 1 &pcfg_pull_up>;
1246                         };                       1073                         };
1247                                                  1074 
1248                         sdmmc_cd: sdmmc-cd {     1075                         sdmmc_cd: sdmmc-cd {
1249                                 rockchip,pins    1076                                 rockchip,pins = <2 RK_PB3 1 &pcfg_pull_up>;
1250                         };                       1077                         };
1251                                                  1078 
1252                         sdmmc_bus1: sdmmc-bus    1079                         sdmmc_bus1: sdmmc-bus1 {
1253                                 rockchip,pins    1080                                 rockchip,pins = <2 RK_PA5 1 &pcfg_pull_up>;
1254                         };                       1081                         };
1255                                                  1082 
1256                         sdmmc_bus4: sdmmc-bus    1083                         sdmmc_bus4: sdmmc-bus4 {
1257                                 rockchip,pins    1084                                 rockchip,pins = <2 RK_PA5 1 &pcfg_pull_up>,
1258                                                  1085                                                 <2 RK_PA6 1 &pcfg_pull_up>,
1259                                                  1086                                                 <2 RK_PA7 1 &pcfg_pull_up>,
1260                                                  1087                                                 <2 RK_PB0 1 &pcfg_pull_up>;
1261                         };                       1088                         };
1262                 };                               1089                 };
1263                                                  1090 
1264                 spdif {                          1091                 spdif {
1265                         spdif_tx: spdif-tx {     1092                         spdif_tx: spdif-tx {
1266                                 rockchip,pins !! 1093                                 rockchip,pins = <2 RK_PC7 1 &pcfg_pull_none>;
1267                         };                       1094                         };
1268                 };                               1095                 };
1269                                                  1096 
1270                 spi0 {                           1097                 spi0 {
1271                         spi0_clk: spi0-clk {     1098                         spi0_clk: spi0-clk {
1272                                 rockchip,pins    1099                                 rockchip,pins = <1 RK_PD5 2 &pcfg_pull_up>;
1273                         };                       1100                         };
1274                         spi0_cs0: spi0-cs0 {     1101                         spi0_cs0: spi0-cs0 {
1275                                 rockchip,pins    1102                                 rockchip,pins = <1 RK_PD0 3 &pcfg_pull_up>;
1276                         };                       1103                         };
1277                         spi0_cs1: spi0-cs1 {     1104                         spi0_cs1: spi0-cs1 {
1278                                 rockchip,pins    1105                                 rockchip,pins = <1 RK_PD1 3 &pcfg_pull_up>;
1279                         };                       1106                         };
1280                         spi0_tx: spi0-tx {       1107                         spi0_tx: spi0-tx {
1281                                 rockchip,pins    1108                                 rockchip,pins = <1 RK_PC7 3 &pcfg_pull_up>;
1282                         };                       1109                         };
1283                         spi0_rx: spi0-rx {       1110                         spi0_rx: spi0-rx {
1284                                 rockchip,pins    1111                                 rockchip,pins = <1 RK_PC6 3 &pcfg_pull_up>;
1285                         };                       1112                         };
1286                 };                               1113                 };
1287                                                  1114 
1288                 spi1 {                           1115                 spi1 {
1289                         spi1_clk: spi1-clk {     1116                         spi1_clk: spi1-clk {
1290                                 rockchip,pins    1117                                 rockchip,pins = <1 RK_PB6 2 &pcfg_pull_up>;
1291                         };                       1118                         };
1292                         spi1_cs0: spi1-cs0 {     1119                         spi1_cs0: spi1-cs0 {
1293                                 rockchip,pins    1120                                 rockchip,pins = <1 RK_PB7 2 &pcfg_pull_up>;
1294                         };                       1121                         };
1295                         spi1_cs1: spi1-cs1 {     1122                         spi1_cs1: spi1-cs1 {
1296                                 rockchip,pins    1123                                 rockchip,pins = <3 RK_PD4 2 &pcfg_pull_up>;
1297                         };                       1124                         };
1298                         spi1_rx: spi1-rx {       1125                         spi1_rx: spi1-rx {
1299                                 rockchip,pins    1126                                 rockchip,pins = <1 RK_PC0 2 &pcfg_pull_up>;
1300                         };                       1127                         };
1301                         spi1_tx: spi1-tx {       1128                         spi1_tx: spi1-tx {
1302                                 rockchip,pins    1129                                 rockchip,pins = <1 RK_PC1 2 &pcfg_pull_up>;
1303                         };                       1130                         };
1304                 };                               1131                 };
1305                                                  1132 
1306                 spi2 {                           1133                 spi2 {
1307                         spi2_clk: spi2-clk {     1134                         spi2_clk: spi2-clk {
1308                                 rockchip,pins    1135                                 rockchip,pins = <0 RK_PB4 2 &pcfg_pull_up>;
1309                         };                       1136                         };
1310                         spi2_cs0: spi2-cs0 {     1137                         spi2_cs0: spi2-cs0 {
1311                                 rockchip,pins    1138                                 rockchip,pins = <0 RK_PB5 2 &pcfg_pull_up>;
1312                         };                       1139                         };
1313                         spi2_rx: spi2-rx {       1140                         spi2_rx: spi2-rx {
1314                                 rockchip,pins    1141                                 rockchip,pins = <0 RK_PB2 2 &pcfg_pull_up>;
1315                         };                       1142                         };
1316                         spi2_tx: spi2-tx {       1143                         spi2_tx: spi2-tx {
1317                                 rockchip,pins    1144                                 rockchip,pins = <0 RK_PB3 2 &pcfg_pull_up>;
1318                         };                       1145                         };
1319                 };                               1146                 };
1320                                                  1147 
1321                 tsadc {                          1148                 tsadc {
1322                         otp_pin: otp-pin {    !! 1149                         otp_gpio: otp-gpio {
1323                                 rockchip,pins    1150                                 rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
1324                         };                       1151                         };
1325                                                  1152 
1326                         otp_out: otp-out {       1153                         otp_out: otp-out {
1327                                 rockchip,pins    1154                                 rockchip,pins = <0 RK_PA3 1 &pcfg_pull_none>;
1328                         };                       1155                         };
1329                 };                               1156                 };
1330                                                  1157 
1331                 uart0 {                          1158                 uart0 {
1332                         uart0_xfer: uart0-xfe    1159                         uart0_xfer: uart0-xfer {
1333                                 rockchip,pins    1160                                 rockchip,pins = <2 RK_PD0 1 &pcfg_pull_up>,
1334                                                  1161                                                 <2 RK_PD1 1 &pcfg_pull_none>;
1335                         };                       1162                         };
1336                                                  1163 
1337                         uart0_cts: uart0-cts     1164                         uart0_cts: uart0-cts {
1338                                 rockchip,pins    1165                                 rockchip,pins = <2 RK_PD2 1 &pcfg_pull_none>;
1339                         };                       1166                         };
1340                                                  1167 
1341                         uart0_rts: uart0-rts     1168                         uart0_rts: uart0-rts {
1342                                 rockchip,pins    1169                                 rockchip,pins = <2 RK_PD3 1 &pcfg_pull_none>;
1343                         };                       1170                         };
1344                 };                               1171                 };
1345                                                  1172 
1346                 uart1 {                          1173                 uart1 {
1347                         uart1_xfer: uart1-xfe    1174                         uart1_xfer: uart1-xfer {
1348                                 rockchip,pins    1175                                 rockchip,pins = <0 RK_PC4 3 &pcfg_pull_up>,
1349                                                  1176                                                 <0 RK_PC5 3 &pcfg_pull_none>;
1350                         };                       1177                         };
1351                                                  1178 
1352                         uart1_cts: uart1-cts     1179                         uart1_cts: uart1-cts {
1353                                 rockchip,pins    1180                                 rockchip,pins = <0 RK_PC6 3 &pcfg_pull_none>;
1354                         };                       1181                         };
1355                                                  1182 
1356                         uart1_rts: uart1-rts     1183                         uart1_rts: uart1-rts {
1357                                 rockchip,pins    1184                                 rockchip,pins = <0 RK_PC7 3 &pcfg_pull_none>;
1358                         };                       1185                         };
1359                 };                               1186                 };
1360                                                  1187 
1361                 uart2 {                          1188                 uart2 {
1362                         uart2_xfer: uart2-xfe    1189                         uart2_xfer: uart2-xfer {
1363                                 rockchip,pins    1190                                 rockchip,pins = <2 RK_PA6 2 &pcfg_pull_up>,
1364                                                  1191                                                 <2 RK_PA5 2 &pcfg_pull_none>;
1365                         };                       1192                         };
1366                         /* no rts / cts for u    1193                         /* no rts / cts for uart2 */
1367                 };                               1194                 };
1368                                                  1195 
1369                 uart3 {                          1196                 uart3 {
1370                         uart3_xfer: uart3-xfe    1197                         uart3_xfer: uart3-xfer {
1371                                 rockchip,pins    1198                                 rockchip,pins = <3 RK_PD5 2 &pcfg_pull_up>,
1372                                                  1199                                                 <3 RK_PD6 3 &pcfg_pull_none>;
1373                         };                       1200                         };
1374                                                  1201 
1375                         uart3_cts: uart3-cts     1202                         uart3_cts: uart3-cts {
1376                                 rockchip,pins    1203                                 rockchip,pins = <3 RK_PC0 2 &pcfg_pull_none>;
1377                         };                       1204                         };
1378                                                  1205 
1379                         uart3_rts: uart3-rts     1206                         uart3_rts: uart3-rts {
1380                                 rockchip,pins    1207                                 rockchip,pins = <3 RK_PC1 2 &pcfg_pull_none>;
1381                         };                       1208                         };
1382                 };                               1209                 };
1383                                                  1210 
1384                 uart4 {                          1211                 uart4 {
1385                         uart4_xfer: uart4-xfe    1212                         uart4_xfer: uart4-xfer {
1386                                 rockchip,pins    1213                                 rockchip,pins = <0 RK_PD3 3 &pcfg_pull_up>,
1387                                                  1214                                                 <0 RK_PD2 3 &pcfg_pull_none>;
1388                         };                       1215                         };
1389                                                  1216 
1390                         uart4_cts: uart4-cts     1217                         uart4_cts: uart4-cts {
1391                                 rockchip,pins    1218                                 rockchip,pins = <0 RK_PD0 3 &pcfg_pull_none>;
1392                         };                       1219                         };
1393                                                  1220 
1394                         uart4_rts: uart4-rts     1221                         uart4_rts: uart4-rts {
1395                                 rockchip,pins    1222                                 rockchip,pins = <0 RK_PD1 3 &pcfg_pull_none>;
1396                         };                       1223                         };
1397                 };                               1224                 };
1398         };                                       1225         };
1399 };                                               1226 };
                                                      

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