1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /* 2 /*
3 * Copyright (c) 2015 Heiko Stuebner <heiko@snt 3 * Copyright (c) 2015 Heiko Stuebner <heiko@sntech.de>
4 */ 4 */
5 5
6 #include <dt-bindings/clock/rk3368-cru.h> 6 #include <dt-bindings/clock/rk3368-cru.h>
7 #include <dt-bindings/gpio/gpio.h> 7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/interrupt-controller/irq 8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/interrupt-controller/arm 9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/pinctrl/rockchip.h> 10 #include <dt-bindings/pinctrl/rockchip.h>
11 #include <dt-bindings/power/rk3368-power.h> 11 #include <dt-bindings/power/rk3368-power.h>
12 #include <dt-bindings/soc/rockchip,boot-mode.h 12 #include <dt-bindings/soc/rockchip,boot-mode.h>
13 #include <dt-bindings/thermal/thermal.h> 13 #include <dt-bindings/thermal/thermal.h>
14 14
15 / { 15 / {
16 compatible = "rockchip,rk3368"; 16 compatible = "rockchip,rk3368";
17 interrupt-parent = <&gic>; 17 interrupt-parent = <&gic>;
18 #address-cells = <2>; 18 #address-cells = <2>;
19 #size-cells = <2>; 19 #size-cells = <2>;
20 20
21 aliases { 21 aliases {
22 gpio0 = &gpio0; !! 22 ethernet0 = &gmac;
23 gpio1 = &gpio1; <<
24 gpio2 = &gpio2; <<
25 gpio3 = &gpio3; <<
26 i2c0 = &i2c0; 23 i2c0 = &i2c0;
27 i2c1 = &i2c1; 24 i2c1 = &i2c1;
28 i2c2 = &i2c2; 25 i2c2 = &i2c2;
29 i2c3 = &i2c3; 26 i2c3 = &i2c3;
30 i2c4 = &i2c4; 27 i2c4 = &i2c4;
31 i2c5 = &i2c5; 28 i2c5 = &i2c5;
32 serial0 = &uart0; 29 serial0 = &uart0;
33 serial1 = &uart1; 30 serial1 = &uart1;
34 serial2 = &uart2; 31 serial2 = &uart2;
35 serial3 = &uart3; 32 serial3 = &uart3;
36 serial4 = &uart4; 33 serial4 = &uart4;
37 spi0 = &spi0; 34 spi0 = &spi0;
38 spi1 = &spi1; 35 spi1 = &spi1;
39 spi2 = &spi2; 36 spi2 = &spi2;
40 }; 37 };
41 38
42 cpus { 39 cpus {
43 #address-cells = <0x2>; 40 #address-cells = <0x2>;
44 #size-cells = <0x0>; 41 #size-cells = <0x0>;
45 42
46 cpu-map { 43 cpu-map {
47 cluster0 { 44 cluster0 {
48 core0 { 45 core0 {
49 cpu = 46 cpu = <&cpu_b0>;
50 }; 47 };
51 core1 { 48 core1 {
52 cpu = 49 cpu = <&cpu_b1>;
53 }; 50 };
54 core2 { 51 core2 {
55 cpu = 52 cpu = <&cpu_b2>;
56 }; 53 };
57 core3 { 54 core3 {
58 cpu = 55 cpu = <&cpu_b3>;
59 }; 56 };
60 }; 57 };
61 58
62 cluster1 { 59 cluster1 {
63 core0 { 60 core0 {
64 cpu = 61 cpu = <&cpu_l0>;
65 }; 62 };
66 core1 { 63 core1 {
67 cpu = 64 cpu = <&cpu_l1>;
68 }; 65 };
69 core2 { 66 core2 {
70 cpu = 67 cpu = <&cpu_l2>;
71 }; 68 };
72 core3 { 69 core3 {
73 cpu = 70 cpu = <&cpu_l3>;
74 }; 71 };
75 }; 72 };
76 }; 73 };
77 74
78 cpu_l0: cpu@0 { 75 cpu_l0: cpu@0 {
79 device_type = "cpu"; 76 device_type = "cpu";
80 compatible = "arm,cort 77 compatible = "arm,cortex-a53";
81 reg = <0x0 0x0>; 78 reg = <0x0 0x0>;
82 enable-method = "psci" 79 enable-method = "psci";
83 #cooling-cells = <2>; 80 #cooling-cells = <2>; /* min followed by max */
84 }; 81 };
85 82
86 cpu_l1: cpu@1 { 83 cpu_l1: cpu@1 {
87 device_type = "cpu"; 84 device_type = "cpu";
88 compatible = "arm,cort 85 compatible = "arm,cortex-a53";
89 reg = <0x0 0x1>; 86 reg = <0x0 0x1>;
90 enable-method = "psci" 87 enable-method = "psci";
91 #cooling-cells = <2>; 88 #cooling-cells = <2>; /* min followed by max */
92 }; 89 };
93 90
94 cpu_l2: cpu@2 { 91 cpu_l2: cpu@2 {
95 device_type = "cpu"; 92 device_type = "cpu";
96 compatible = "arm,cort 93 compatible = "arm,cortex-a53";
97 reg = <0x0 0x2>; 94 reg = <0x0 0x2>;
98 enable-method = "psci" 95 enable-method = "psci";
99 #cooling-cells = <2>; 96 #cooling-cells = <2>; /* min followed by max */
100 }; 97 };
101 98
102 cpu_l3: cpu@3 { 99 cpu_l3: cpu@3 {
103 device_type = "cpu"; 100 device_type = "cpu";
104 compatible = "arm,cort 101 compatible = "arm,cortex-a53";
105 reg = <0x0 0x3>; 102 reg = <0x0 0x3>;
106 enable-method = "psci" 103 enable-method = "psci";
107 #cooling-cells = <2>; 104 #cooling-cells = <2>; /* min followed by max */
108 }; 105 };
109 106
110 cpu_b0: cpu@100 { 107 cpu_b0: cpu@100 {
111 device_type = "cpu"; 108 device_type = "cpu";
112 compatible = "arm,cort 109 compatible = "arm,cortex-a53";
113 reg = <0x0 0x100>; 110 reg = <0x0 0x100>;
114 enable-method = "psci" 111 enable-method = "psci";
115 #cooling-cells = <2>; 112 #cooling-cells = <2>; /* min followed by max */
116 }; 113 };
117 114
118 cpu_b1: cpu@101 { 115 cpu_b1: cpu@101 {
119 device_type = "cpu"; 116 device_type = "cpu";
120 compatible = "arm,cort 117 compatible = "arm,cortex-a53";
121 reg = <0x0 0x101>; 118 reg = <0x0 0x101>;
122 enable-method = "psci" 119 enable-method = "psci";
123 #cooling-cells = <2>; 120 #cooling-cells = <2>; /* min followed by max */
124 }; 121 };
125 122
126 cpu_b2: cpu@102 { 123 cpu_b2: cpu@102 {
127 device_type = "cpu"; 124 device_type = "cpu";
128 compatible = "arm,cort 125 compatible = "arm,cortex-a53";
129 reg = <0x0 0x102>; 126 reg = <0x0 0x102>;
130 enable-method = "psci" 127 enable-method = "psci";
131 #cooling-cells = <2>; 128 #cooling-cells = <2>; /* min followed by max */
132 }; 129 };
133 130
134 cpu_b3: cpu@103 { 131 cpu_b3: cpu@103 {
135 device_type = "cpu"; 132 device_type = "cpu";
136 compatible = "arm,cort 133 compatible = "arm,cortex-a53";
137 reg = <0x0 0x103>; 134 reg = <0x0 0x103>;
138 enable-method = "psci" 135 enable-method = "psci";
139 #cooling-cells = <2>; 136 #cooling-cells = <2>; /* min followed by max */
140 }; 137 };
141 }; 138 };
142 139
143 arm-pmu { 140 arm-pmu {
144 compatible = "arm,cortex-a53-p !! 141 compatible = "arm,armv8-pmuv3";
145 interrupts = <GIC_SPI 112 IRQ_ 142 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
146 <GIC_SPI 113 IRQ_ 143 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
147 <GIC_SPI 114 IRQ_ 144 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
148 <GIC_SPI 115 IRQ_ 145 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
149 <GIC_SPI 116 IRQ_ 146 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
150 <GIC_SPI 117 IRQ_ 147 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
151 <GIC_SPI 118 IRQ_ 148 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
152 <GIC_SPI 119 IRQ_ 149 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
153 interrupt-affinity = <&cpu_l0> 150 interrupt-affinity = <&cpu_l0>, <&cpu_l1>, <&cpu_l2>,
154 <&cpu_l3> 151 <&cpu_l3>, <&cpu_b0>, <&cpu_b1>,
155 <&cpu_b2> 152 <&cpu_b2>, <&cpu_b3>;
156 }; 153 };
157 154
158 psci { 155 psci {
159 compatible = "arm,psci-0.2"; 156 compatible = "arm,psci-0.2";
160 method = "smc"; 157 method = "smc";
161 }; 158 };
162 159
163 timer { 160 timer {
164 compatible = "arm,armv8-timer" 161 compatible = "arm,armv8-timer";
165 interrupts = <GIC_PPI 13 162 interrupts = <GIC_PPI 13
166 (GIC_CPU_MASK_SIMPLE(8 163 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
167 <GIC_PPI 14 164 <GIC_PPI 14
168 (GIC_CPU_MASK_SIMPLE(8 165 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
169 <GIC_PPI 11 166 <GIC_PPI 11
170 (GIC_CPU_MASK_SIMPLE(8 167 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
171 <GIC_PPI 10 168 <GIC_PPI 10
172 (GIC_CPU_MASK_SIMPLE(8 169 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
173 }; 170 };
174 171
175 xin24m: oscillator { 172 xin24m: oscillator {
176 compatible = "fixed-clock"; 173 compatible = "fixed-clock";
177 clock-frequency = <24000000>; 174 clock-frequency = <24000000>;
178 clock-output-names = "xin24m"; 175 clock-output-names = "xin24m";
179 #clock-cells = <0>; 176 #clock-cells = <0>;
180 }; 177 };
181 178
182 sdmmc: mmc@ff0c0000 { 179 sdmmc: mmc@ff0c0000 {
183 compatible = "rockchip,rk3368- 180 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
184 reg = <0x0 0xff0c0000 0x0 0x40 181 reg = <0x0 0xff0c0000 0x0 0x4000>;
185 max-frequency = <150000000>; 182 max-frequency = <150000000>;
186 clocks = <&cru HCLK_SDMMC>, <& 183 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
187 <&cru SCLK_SDMMC_DRV> 184 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
188 clock-names = "biu", "ciu", "c 185 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
189 fifo-depth = <0x100>; 186 fifo-depth = <0x100>;
190 interrupts = <GIC_SPI 32 IRQ_T 187 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
191 resets = <&cru SRST_MMC0>; 188 resets = <&cru SRST_MMC0>;
192 reset-names = "reset"; 189 reset-names = "reset";
193 status = "disabled"; 190 status = "disabled";
194 }; 191 };
195 192
196 sdio0: mmc@ff0d0000 { 193 sdio0: mmc@ff0d0000 {
197 compatible = "rockchip,rk3368- 194 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
198 reg = <0x0 0xff0d0000 0x0 0x40 195 reg = <0x0 0xff0d0000 0x0 0x4000>;
199 max-frequency = <150000000>; 196 max-frequency = <150000000>;
200 clocks = <&cru HCLK_SDIO0>, <& 197 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>,
201 <&cru SCLK_SDIO0_DRV> 198 <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
202 clock-names = "biu", "ciu", "c 199 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
203 fifo-depth = <0x100>; 200 fifo-depth = <0x100>;
204 interrupts = <GIC_SPI 33 IRQ_T 201 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
205 resets = <&cru SRST_SDIO0>; 202 resets = <&cru SRST_SDIO0>;
206 reset-names = "reset"; 203 reset-names = "reset";
207 status = "disabled"; 204 status = "disabled";
208 }; 205 };
209 206
210 emmc: mmc@ff0f0000 { 207 emmc: mmc@ff0f0000 {
211 compatible = "rockchip,rk3368- 208 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
212 reg = <0x0 0xff0f0000 0x0 0x40 209 reg = <0x0 0xff0f0000 0x0 0x4000>;
213 max-frequency = <150000000>; 210 max-frequency = <150000000>;
214 clocks = <&cru HCLK_EMMC>, <&c 211 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
215 <&cru SCLK_EMMC_DRV>, 212 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
216 clock-names = "biu", "ciu", "c 213 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
217 fifo-depth = <0x100>; 214 fifo-depth = <0x100>;
218 interrupts = <GIC_SPI 35 IRQ_T 215 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
219 resets = <&cru SRST_EMMC>; 216 resets = <&cru SRST_EMMC>;
220 reset-names = "reset"; 217 reset-names = "reset";
221 status = "disabled"; 218 status = "disabled";
222 }; 219 };
223 220
224 saradc: saradc@ff100000 { 221 saradc: saradc@ff100000 {
225 compatible = "rockchip,saradc" 222 compatible = "rockchip,saradc";
226 reg = <0x0 0xff100000 0x0 0x10 223 reg = <0x0 0xff100000 0x0 0x100>;
227 interrupts = <GIC_SPI 36 IRQ_T 224 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
228 #io-channel-cells = <1>; 225 #io-channel-cells = <1>;
229 clocks = <&cru SCLK_SARADC>, < 226 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
230 clock-names = "saradc", "apb_p 227 clock-names = "saradc", "apb_pclk";
231 resets = <&cru SRST_SARADC>; 228 resets = <&cru SRST_SARADC>;
232 reset-names = "saradc-apb"; 229 reset-names = "saradc-apb";
233 status = "disabled"; 230 status = "disabled";
234 }; 231 };
235 232
236 spi0: spi@ff110000 { 233 spi0: spi@ff110000 {
237 compatible = "rockchip,rk3368- 234 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
238 reg = <0x0 0xff110000 0x0 0x10 235 reg = <0x0 0xff110000 0x0 0x1000>;
239 clocks = <&cru SCLK_SPI0>, <&c 236 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
240 clock-names = "spiclk", "apb_p 237 clock-names = "spiclk", "apb_pclk";
241 interrupts = <GIC_SPI 44 IRQ_T 238 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
242 pinctrl-names = "default"; 239 pinctrl-names = "default";
243 pinctrl-0 = <&spi0_clk &spi0_t 240 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
244 #address-cells = <1>; 241 #address-cells = <1>;
245 #size-cells = <0>; 242 #size-cells = <0>;
246 status = "disabled"; 243 status = "disabled";
247 }; 244 };
248 245
249 spi1: spi@ff120000 { 246 spi1: spi@ff120000 {
250 compatible = "rockchip,rk3368- 247 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
251 reg = <0x0 0xff120000 0x0 0x10 248 reg = <0x0 0xff120000 0x0 0x1000>;
252 clocks = <&cru SCLK_SPI1>, <&c 249 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
253 clock-names = "spiclk", "apb_p 250 clock-names = "spiclk", "apb_pclk";
254 interrupts = <GIC_SPI 45 IRQ_T 251 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
255 pinctrl-names = "default"; 252 pinctrl-names = "default";
256 pinctrl-0 = <&spi1_clk &spi1_t 253 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
257 #address-cells = <1>; 254 #address-cells = <1>;
258 #size-cells = <0>; 255 #size-cells = <0>;
259 status = "disabled"; 256 status = "disabled";
260 }; 257 };
261 258
262 spi2: spi@ff130000 { 259 spi2: spi@ff130000 {
263 compatible = "rockchip,rk3368- 260 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
264 reg = <0x0 0xff130000 0x0 0x10 261 reg = <0x0 0xff130000 0x0 0x1000>;
265 clocks = <&cru SCLK_SPI2>, <&c 262 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
266 clock-names = "spiclk", "apb_p 263 clock-names = "spiclk", "apb_pclk";
267 interrupts = <GIC_SPI 41 IRQ_T 264 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
268 pinctrl-names = "default"; 265 pinctrl-names = "default";
269 pinctrl-0 = <&spi2_clk &spi2_t 266 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
270 #address-cells = <1>; 267 #address-cells = <1>;
271 #size-cells = <0>; 268 #size-cells = <0>;
272 status = "disabled"; 269 status = "disabled";
273 }; 270 };
274 271
275 i2c2: i2c@ff140000 { 272 i2c2: i2c@ff140000 {
276 compatible = "rockchip,rk3368- 273 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
277 reg = <0x0 0xff140000 0x0 0x10 274 reg = <0x0 0xff140000 0x0 0x1000>;
278 interrupts = <GIC_SPI 62 IRQ_T 275 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
279 #address-cells = <1>; 276 #address-cells = <1>;
280 #size-cells = <0>; 277 #size-cells = <0>;
281 clock-names = "i2c"; 278 clock-names = "i2c";
282 clocks = <&cru PCLK_I2C2>; 279 clocks = <&cru PCLK_I2C2>;
283 pinctrl-names = "default"; 280 pinctrl-names = "default";
284 pinctrl-0 = <&i2c2_xfer>; 281 pinctrl-0 = <&i2c2_xfer>;
285 status = "disabled"; 282 status = "disabled";
286 }; 283 };
287 284
288 i2c3: i2c@ff150000 { 285 i2c3: i2c@ff150000 {
289 compatible = "rockchip,rk3368- 286 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
290 reg = <0x0 0xff150000 0x0 0x10 287 reg = <0x0 0xff150000 0x0 0x1000>;
291 interrupts = <GIC_SPI 63 IRQ_T 288 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
292 #address-cells = <1>; 289 #address-cells = <1>;
293 #size-cells = <0>; 290 #size-cells = <0>;
294 clock-names = "i2c"; 291 clock-names = "i2c";
295 clocks = <&cru PCLK_I2C3>; 292 clocks = <&cru PCLK_I2C3>;
296 pinctrl-names = "default"; 293 pinctrl-names = "default";
297 pinctrl-0 = <&i2c3_xfer>; 294 pinctrl-0 = <&i2c3_xfer>;
298 status = "disabled"; 295 status = "disabled";
299 }; 296 };
300 297
301 i2c4: i2c@ff160000 { 298 i2c4: i2c@ff160000 {
302 compatible = "rockchip,rk3368- 299 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
303 reg = <0x0 0xff160000 0x0 0x10 300 reg = <0x0 0xff160000 0x0 0x1000>;
304 interrupts = <GIC_SPI 64 IRQ_T 301 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
305 #address-cells = <1>; 302 #address-cells = <1>;
306 #size-cells = <0>; 303 #size-cells = <0>;
307 clock-names = "i2c"; 304 clock-names = "i2c";
308 clocks = <&cru PCLK_I2C4>; 305 clocks = <&cru PCLK_I2C4>;
309 pinctrl-names = "default"; 306 pinctrl-names = "default";
310 pinctrl-0 = <&i2c4_xfer>; 307 pinctrl-0 = <&i2c4_xfer>;
311 status = "disabled"; 308 status = "disabled";
312 }; 309 };
313 310
314 i2c5: i2c@ff170000 { 311 i2c5: i2c@ff170000 {
315 compatible = "rockchip,rk3368- 312 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
316 reg = <0x0 0xff170000 0x0 0x10 313 reg = <0x0 0xff170000 0x0 0x1000>;
317 interrupts = <GIC_SPI 65 IRQ_T 314 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
318 #address-cells = <1>; 315 #address-cells = <1>;
319 #size-cells = <0>; 316 #size-cells = <0>;
320 clock-names = "i2c"; 317 clock-names = "i2c";
321 clocks = <&cru PCLK_I2C5>; 318 clocks = <&cru PCLK_I2C5>;
322 pinctrl-names = "default"; 319 pinctrl-names = "default";
323 pinctrl-0 = <&i2c5_xfer>; 320 pinctrl-0 = <&i2c5_xfer>;
324 status = "disabled"; 321 status = "disabled";
325 }; 322 };
326 323
327 uart0: serial@ff180000 { 324 uart0: serial@ff180000 {
328 compatible = "rockchip,rk3368- 325 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
329 reg = <0x0 0xff180000 0x0 0x10 326 reg = <0x0 0xff180000 0x0 0x100>;
330 clock-frequency = <24000000>; 327 clock-frequency = <24000000>;
331 clocks = <&cru SCLK_UART0>, <& 328 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
332 clock-names = "baudclk", "apb_ 329 clock-names = "baudclk", "apb_pclk";
333 interrupts = <GIC_SPI 55 IRQ_T 330 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
334 reg-shift = <2>; 331 reg-shift = <2>;
335 reg-io-width = <4>; 332 reg-io-width = <4>;
336 status = "disabled"; 333 status = "disabled";
337 }; 334 };
338 335
339 uart1: serial@ff190000 { 336 uart1: serial@ff190000 {
340 compatible = "rockchip,rk3368- 337 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
341 reg = <0x0 0xff190000 0x0 0x10 338 reg = <0x0 0xff190000 0x0 0x100>;
342 clock-frequency = <24000000>; 339 clock-frequency = <24000000>;
343 clocks = <&cru SCLK_UART1>, <& 340 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
344 clock-names = "baudclk", "apb_ 341 clock-names = "baudclk", "apb_pclk";
345 interrupts = <GIC_SPI 56 IRQ_T 342 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
346 reg-shift = <2>; 343 reg-shift = <2>;
347 reg-io-width = <4>; 344 reg-io-width = <4>;
348 status = "disabled"; 345 status = "disabled";
349 }; 346 };
350 347
351 uart3: serial@ff1b0000 { 348 uart3: serial@ff1b0000 {
352 compatible = "rockchip,rk3368- 349 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
353 reg = <0x0 0xff1b0000 0x0 0x10 350 reg = <0x0 0xff1b0000 0x0 0x100>;
354 clock-frequency = <24000000>; 351 clock-frequency = <24000000>;
355 clocks = <&cru SCLK_UART3>, <& 352 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
356 clock-names = "baudclk", "apb_ 353 clock-names = "baudclk", "apb_pclk";
357 interrupts = <GIC_SPI 58 IRQ_T 354 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
358 reg-shift = <2>; 355 reg-shift = <2>;
359 reg-io-width = <4>; 356 reg-io-width = <4>;
360 status = "disabled"; 357 status = "disabled";
361 }; 358 };
362 359
363 uart4: serial@ff1c0000 { 360 uart4: serial@ff1c0000 {
364 compatible = "rockchip,rk3368- 361 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
365 reg = <0x0 0xff1c0000 0x0 0x10 362 reg = <0x0 0xff1c0000 0x0 0x100>;
366 clock-frequency = <24000000>; 363 clock-frequency = <24000000>;
367 clocks = <&cru SCLK_UART4>, <& 364 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
368 clock-names = "baudclk", "apb_ 365 clock-names = "baudclk", "apb_pclk";
369 interrupts = <GIC_SPI 59 IRQ_T 366 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
370 reg-shift = <2>; 367 reg-shift = <2>;
371 reg-io-width = <4>; 368 reg-io-width = <4>;
372 status = "disabled"; 369 status = "disabled";
373 }; 370 };
374 371
375 dmac_peri: dma-controller@ff250000 { 372 dmac_peri: dma-controller@ff250000 {
376 compatible = "arm,pl330", "arm 373 compatible = "arm,pl330", "arm,primecell";
377 reg = <0x0 0xff250000 0x0 0x40 374 reg = <0x0 0xff250000 0x0 0x4000>;
378 interrupts = <GIC_SPI 2 IRQ_TY 375 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
379 <GIC_SPI 3 IRQ_TY 376 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
380 #dma-cells = <1>; 377 #dma-cells = <1>;
381 arm,pl330-broken-no-flushp; 378 arm,pl330-broken-no-flushp;
382 arm,pl330-periph-burst; 379 arm,pl330-periph-burst;
383 clocks = <&cru ACLK_DMAC_PERI> 380 clocks = <&cru ACLK_DMAC_PERI>;
384 clock-names = "apb_pclk"; 381 clock-names = "apb_pclk";
385 }; 382 };
386 383
387 thermal-zones { 384 thermal-zones {
388 cpu_thermal: cpu-thermal { 385 cpu_thermal: cpu-thermal {
389 polling-delay-passive 386 polling-delay-passive = <100>; /* milliseconds */
390 polling-delay = <5000> 387 polling-delay = <5000>; /* milliseconds */
391 388
392 thermal-sensors = <&ts 389 thermal-sensors = <&tsadc 0>;
393 390
394 trips { 391 trips {
395 cpu_alert0: cp 392 cpu_alert0: cpu_alert0 {
396 temper 393 temperature = <75000>; /* millicelsius */
397 hyster 394 hysteresis = <2000>; /* millicelsius */
398 type = 395 type = "passive";
399 }; 396 };
400 cpu_alert1: cp 397 cpu_alert1: cpu_alert1 {
401 temper 398 temperature = <80000>; /* millicelsius */
402 hyster 399 hysteresis = <2000>; /* millicelsius */
403 type = 400 type = "passive";
404 }; 401 };
405 cpu_crit: cpu_ 402 cpu_crit: cpu_crit {
406 temper 403 temperature = <95000>; /* millicelsius */
407 hyster 404 hysteresis = <2000>; /* millicelsius */
408 type = 405 type = "critical";
409 }; 406 };
410 }; 407 };
411 408
412 cooling-maps { 409 cooling-maps {
413 map0 { 410 map0 {
414 trip = 411 trip = <&cpu_alert0>;
415 coolin 412 cooling-device =
416 <&cpu_ 413 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
417 <&cpu_ 414 <&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
418 <&cpu_ 415 <&cpu_b2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
419 <&cpu_ 416 <&cpu_b3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
420 }; 417 };
421 map1 { 418 map1 {
422 trip = 419 trip = <&cpu_alert1>;
423 coolin 420 cooling-device =
424 <&cpu_ 421 <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
425 <&cpu_ 422 <&cpu_l1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
426 <&cpu_ 423 <&cpu_l2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
427 <&cpu_ 424 <&cpu_l3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
428 }; 425 };
429 }; 426 };
430 }; 427 };
431 428
432 gpu_thermal: gpu-thermal { 429 gpu_thermal: gpu-thermal {
433 polling-delay-passive 430 polling-delay-passive = <100>; /* milliseconds */
434 polling-delay = <5000> 431 polling-delay = <5000>; /* milliseconds */
435 432
436 thermal-sensors = <&ts 433 thermal-sensors = <&tsadc 1>;
437 434
438 trips { 435 trips {
439 gpu_alert0: gp 436 gpu_alert0: gpu_alert0 {
440 temper 437 temperature = <80000>; /* millicelsius */
441 hyster 438 hysteresis = <2000>; /* millicelsius */
442 type = 439 type = "passive";
443 }; 440 };
444 gpu_crit: gpu_ 441 gpu_crit: gpu_crit {
445 temper 442 temperature = <115000>; /* millicelsius */
446 hyster 443 hysteresis = <2000>; /* millicelsius */
447 type = 444 type = "critical";
448 }; 445 };
449 }; 446 };
450 447
451 cooling-maps { 448 cooling-maps {
452 map0 { 449 map0 {
453 trip = 450 trip = <&gpu_alert0>;
454 coolin 451 cooling-device =
455 <&cpu_ 452 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
456 <&cpu_ 453 <&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
457 <&cpu_ 454 <&cpu_b2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
458 <&cpu_ 455 <&cpu_b3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
459 }; 456 };
460 }; 457 };
461 }; 458 };
462 }; 459 };
463 460
464 tsadc: tsadc@ff280000 { 461 tsadc: tsadc@ff280000 {
465 compatible = "rockchip,rk3368- 462 compatible = "rockchip,rk3368-tsadc";
466 reg = <0x0 0xff280000 0x0 0x10 463 reg = <0x0 0xff280000 0x0 0x100>;
467 interrupts = <GIC_SPI 37 IRQ_T 464 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
468 clocks = <&cru SCLK_TSADC>, <& 465 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
469 clock-names = "tsadc", "apb_pc 466 clock-names = "tsadc", "apb_pclk";
470 resets = <&cru SRST_TSADC>; 467 resets = <&cru SRST_TSADC>;
471 reset-names = "tsadc-apb"; 468 reset-names = "tsadc-apb";
472 pinctrl-names = "init", "defau 469 pinctrl-names = "init", "default", "sleep";
473 pinctrl-0 = <&otp_pin>; 470 pinctrl-0 = <&otp_pin>;
474 pinctrl-1 = <&otp_out>; 471 pinctrl-1 = <&otp_out>;
475 pinctrl-2 = <&otp_pin>; 472 pinctrl-2 = <&otp_pin>;
476 #thermal-sensor-cells = <1>; 473 #thermal-sensor-cells = <1>;
477 rockchip,hw-tshut-temp = <9500 474 rockchip,hw-tshut-temp = <95000>;
478 status = "disabled"; 475 status = "disabled";
479 }; 476 };
480 477
481 gmac: ethernet@ff290000 { 478 gmac: ethernet@ff290000 {
482 compatible = "rockchip,rk3368- 479 compatible = "rockchip,rk3368-gmac";
483 reg = <0x0 0xff290000 0x0 0x10 480 reg = <0x0 0xff290000 0x0 0x10000>;
484 interrupts = <GIC_SPI 27 IRQ_T 481 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
485 interrupt-names = "macirq"; 482 interrupt-names = "macirq";
486 rockchip,grf = <&grf>; 483 rockchip,grf = <&grf>;
487 clocks = <&cru SCLK_MAC>, 484 clocks = <&cru SCLK_MAC>,
488 <&cru SCLK_MAC_RX>, <& 485 <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>,
489 <&cru SCLK_MACREF>, <& 486 <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>,
490 <&cru ACLK_GMAC>, <&cr 487 <&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
491 clock-names = "stmmaceth", 488 clock-names = "stmmaceth",
492 "mac_clk_rx", "mac_clk 489 "mac_clk_rx", "mac_clk_tx",
493 "clk_mac_ref", "clk_ma 490 "clk_mac_ref", "clk_mac_refout",
494 "aclk_mac", "pclk_mac" 491 "aclk_mac", "pclk_mac";
495 status = "disabled"; 492 status = "disabled";
496 }; 493 };
497 494
498 usb_host0_ehci: usb@ff500000 { 495 usb_host0_ehci: usb@ff500000 {
499 compatible = "generic-ehci"; 496 compatible = "generic-ehci";
500 reg = <0x0 0xff500000 0x0 0x10 497 reg = <0x0 0xff500000 0x0 0x100>;
501 interrupts = <GIC_SPI 24 IRQ_T 498 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
502 clocks = <&cru HCLK_HOST0>; 499 clocks = <&cru HCLK_HOST0>;
503 status = "disabled"; 500 status = "disabled";
504 }; 501 };
505 502
506 usb_otg: usb@ff580000 { 503 usb_otg: usb@ff580000 {
507 compatible = "rockchip,rk3368- 504 compatible = "rockchip,rk3368-usb", "rockchip,rk3066-usb",
508 "snps,dwc2"; 505 "snps,dwc2";
509 reg = <0x0 0xff580000 0x0 0x40 506 reg = <0x0 0xff580000 0x0 0x40000>;
510 interrupts = <GIC_SPI 23 IRQ_T 507 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
511 clocks = <&cru HCLK_OTG0>; 508 clocks = <&cru HCLK_OTG0>;
512 clock-names = "otg"; 509 clock-names = "otg";
513 dr_mode = "otg"; 510 dr_mode = "otg";
514 g-np-tx-fifo-size = <16>; 511 g-np-tx-fifo-size = <16>;
515 g-rx-fifo-size = <275>; 512 g-rx-fifo-size = <275>;
516 g-tx-fifo-size = <256 128 128 513 g-tx-fifo-size = <256 128 128 64 64 32>;
517 status = "disabled"; 514 status = "disabled";
518 }; 515 };
519 516
520 dmac_bus: dma-controller@ff600000 { 517 dmac_bus: dma-controller@ff600000 {
521 compatible = "arm,pl330", "arm 518 compatible = "arm,pl330", "arm,primecell";
522 reg = <0x0 0xff600000 0x0 0x40 519 reg = <0x0 0xff600000 0x0 0x4000>;
523 interrupts = <GIC_SPI 0 IRQ_TY 520 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
524 <GIC_SPI 1 IRQ_TY 521 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
525 #dma-cells = <1>; 522 #dma-cells = <1>;
526 arm,pl330-broken-no-flushp; 523 arm,pl330-broken-no-flushp;
527 arm,pl330-periph-burst; 524 arm,pl330-periph-burst;
528 clocks = <&cru ACLK_DMAC_BUS>; 525 clocks = <&cru ACLK_DMAC_BUS>;
529 clock-names = "apb_pclk"; 526 clock-names = "apb_pclk";
530 }; 527 };
531 528
532 i2c0: i2c@ff650000 { 529 i2c0: i2c@ff650000 {
533 compatible = "rockchip,rk3368- 530 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
534 reg = <0x0 0xff650000 0x0 0x10 531 reg = <0x0 0xff650000 0x0 0x1000>;
535 clocks = <&cru PCLK_I2C0>; 532 clocks = <&cru PCLK_I2C0>;
536 clock-names = "i2c"; 533 clock-names = "i2c";
537 interrupts = <GIC_SPI 60 IRQ_T 534 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
538 pinctrl-names = "default"; 535 pinctrl-names = "default";
539 pinctrl-0 = <&i2c0_xfer>; 536 pinctrl-0 = <&i2c0_xfer>;
540 #address-cells = <1>; 537 #address-cells = <1>;
541 #size-cells = <0>; 538 #size-cells = <0>;
542 status = "disabled"; 539 status = "disabled";
543 }; 540 };
544 541
545 i2c1: i2c@ff660000 { 542 i2c1: i2c@ff660000 {
546 compatible = "rockchip,rk3368- 543 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
547 reg = <0x0 0xff660000 0x0 0x10 544 reg = <0x0 0xff660000 0x0 0x1000>;
548 interrupts = <GIC_SPI 61 IRQ_T 545 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
549 #address-cells = <1>; 546 #address-cells = <1>;
550 #size-cells = <0>; 547 #size-cells = <0>;
551 clock-names = "i2c"; 548 clock-names = "i2c";
552 clocks = <&cru PCLK_I2C1>; 549 clocks = <&cru PCLK_I2C1>;
553 pinctrl-names = "default"; 550 pinctrl-names = "default";
554 pinctrl-0 = <&i2c1_xfer>; 551 pinctrl-0 = <&i2c1_xfer>;
555 status = "disabled"; 552 status = "disabled";
556 }; 553 };
557 554
558 pwm0: pwm@ff680000 { 555 pwm0: pwm@ff680000 {
559 compatible = "rockchip,rk3368- 556 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
560 reg = <0x0 0xff680000 0x0 0x10 557 reg = <0x0 0xff680000 0x0 0x10>;
561 #pwm-cells = <3>; 558 #pwm-cells = <3>;
562 pinctrl-names = "default"; 559 pinctrl-names = "default";
563 pinctrl-0 = <&pwm0_pin>; 560 pinctrl-0 = <&pwm0_pin>;
564 clocks = <&cru PCLK_PWM1>; 561 clocks = <&cru PCLK_PWM1>;
565 status = "disabled"; 562 status = "disabled";
566 }; 563 };
567 564
568 pwm1: pwm@ff680010 { 565 pwm1: pwm@ff680010 {
569 compatible = "rockchip,rk3368- 566 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
570 reg = <0x0 0xff680010 0x0 0x10 567 reg = <0x0 0xff680010 0x0 0x10>;
571 #pwm-cells = <3>; 568 #pwm-cells = <3>;
572 pinctrl-names = "default"; 569 pinctrl-names = "default";
573 pinctrl-0 = <&pwm1_pin>; 570 pinctrl-0 = <&pwm1_pin>;
574 clocks = <&cru PCLK_PWM1>; 571 clocks = <&cru PCLK_PWM1>;
575 status = "disabled"; 572 status = "disabled";
576 }; 573 };
577 574
578 pwm2: pwm@ff680020 { 575 pwm2: pwm@ff680020 {
579 compatible = "rockchip,rk3368- 576 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
580 reg = <0x0 0xff680020 0x0 0x10 577 reg = <0x0 0xff680020 0x0 0x10>;
581 #pwm-cells = <3>; 578 #pwm-cells = <3>;
582 clocks = <&cru PCLK_PWM1>; 579 clocks = <&cru PCLK_PWM1>;
583 status = "disabled"; 580 status = "disabled";
584 }; 581 };
585 582
586 pwm3: pwm@ff680030 { 583 pwm3: pwm@ff680030 {
587 compatible = "rockchip,rk3368- 584 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
588 reg = <0x0 0xff680030 0x0 0x10 585 reg = <0x0 0xff680030 0x0 0x10>;
589 #pwm-cells = <3>; 586 #pwm-cells = <3>;
590 pinctrl-names = "default"; 587 pinctrl-names = "default";
591 pinctrl-0 = <&pwm3_pin>; 588 pinctrl-0 = <&pwm3_pin>;
592 clocks = <&cru PCLK_PWM1>; 589 clocks = <&cru PCLK_PWM1>;
593 status = "disabled"; 590 status = "disabled";
594 }; 591 };
595 592
596 uart2: serial@ff690000 { 593 uart2: serial@ff690000 {
597 compatible = "rockchip,rk3368- 594 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
598 reg = <0x0 0xff690000 0x0 0x10 595 reg = <0x0 0xff690000 0x0 0x100>;
599 clocks = <&cru SCLK_UART2>, <& 596 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
600 clock-names = "baudclk", "apb_ 597 clock-names = "baudclk", "apb_pclk";
601 interrupts = <GIC_SPI 57 IRQ_T 598 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
602 pinctrl-names = "default"; 599 pinctrl-names = "default";
603 pinctrl-0 = <&uart2_xfer>; 600 pinctrl-0 = <&uart2_xfer>;
604 reg-shift = <2>; 601 reg-shift = <2>;
605 reg-io-width = <4>; 602 reg-io-width = <4>;
606 status = "disabled"; 603 status = "disabled";
607 }; 604 };
608 605
609 mbox: mbox@ff6b0000 { 606 mbox: mbox@ff6b0000 {
610 compatible = "rockchip,rk3368- 607 compatible = "rockchip,rk3368-mailbox";
611 reg = <0x0 0xff6b0000 0x0 0x10 608 reg = <0x0 0xff6b0000 0x0 0x1000>;
612 interrupts = <GIC_SPI 146 IRQ_ 609 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
613 <GIC_SPI 147 IRQ_ 610 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
614 <GIC_SPI 148 IRQ_ 611 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
615 <GIC_SPI 149 IRQ_ 612 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
616 clocks = <&cru PCLK_MAILBOX>; 613 clocks = <&cru PCLK_MAILBOX>;
617 clock-names = "pclk_mailbox"; 614 clock-names = "pclk_mailbox";
618 #mbox-cells = <1>; 615 #mbox-cells = <1>;
619 status = "disabled"; 616 status = "disabled";
620 }; 617 };
621 618
622 pmu: power-management@ff730000 { 619 pmu: power-management@ff730000 {
623 compatible = "rockchip,rk3368- 620 compatible = "rockchip,rk3368-pmu", "syscon", "simple-mfd";
624 reg = <0x0 0xff730000 0x0 0x10 621 reg = <0x0 0xff730000 0x0 0x1000>;
625 622
626 power: power-controller { 623 power: power-controller {
627 compatible = "rockchip 624 compatible = "rockchip,rk3368-power-controller";
628 #power-domain-cells = 625 #power-domain-cells = <1>;
629 #address-cells = <1>; 626 #address-cells = <1>;
630 #size-cells = <0>; 627 #size-cells = <0>;
631 628
632 /* 629 /*
633 * Note: Although SCLK 630 * Note: Although SCLK_* are the working clocks
634 * of device without i 631 * of device without including on the NOC, needed for
635 * synchronous reset. 632 * synchronous reset.
636 * 633 *
637 * The clocks on the w 634 * The clocks on the which NOC:
638 * ACLK_IEP/ACLK_VIP/A 635 * ACLK_IEP/ACLK_VIP/ACLK_VOP0 are on ACLK_VIO0_NIU.
639 * ACLK_ISP/ACLK_VOP1 636 * ACLK_ISP/ACLK_VOP1 are on ACLK_VIO1_NIU.
640 * ACLK_RGA is on ACLK 637 * ACLK_RGA is on ACLK_RGA_NIU.
641 * The others (HCLK_*, 638 * The others (HCLK_*,PLCK_*) are on HCLK_VIO_NIU.
642 * 639 *
643 * Which clock are dev 640 * Which clock are device clocks:
644 * clocks 641 * clocks devices
645 * *_IEP 642 * *_IEP IEP:Image Enhancement Processor
646 * *_ISP 643 * *_ISP ISP:Image Signal Processing
647 * *_VIP 644 * *_VIP VIP:Video Input Processor
648 * *_VOP* 645 * *_VOP* VOP:Visual Output Processor
649 * *_RGA 646 * *_RGA RGA
650 * *_EDP* 647 * *_EDP* EDP
651 * *_DPHY* 648 * *_DPHY* LVDS
652 * *_HDMI 649 * *_HDMI HDMI
653 * *_MIPI_* 650 * *_MIPI_* MIPI
654 */ 651 */
655 power-domain@RK3368_PD 652 power-domain@RK3368_PD_VIO {
656 reg = <RK3368_ 653 reg = <RK3368_PD_VIO>;
657 clocks = <&cru 654 clocks = <&cru ACLK_IEP>,
658 <&cru 655 <&cru ACLK_ISP>,
659 <&cru 656 <&cru ACLK_VIP>,
660 <&cru 657 <&cru ACLK_RGA>,
661 <&cru 658 <&cru ACLK_VOP>,
662 <&cru 659 <&cru ACLK_VOP_IEP>,
663 <&cru 660 <&cru DCLK_VOP>,
664 <&cru 661 <&cru HCLK_IEP>,
665 <&cru 662 <&cru HCLK_ISP>,
666 <&cru 663 <&cru HCLK_RGA>,
667 <&cru 664 <&cru HCLK_VIP>,
668 <&cru 665 <&cru HCLK_VOP>,
669 <&cru 666 <&cru HCLK_VIO_HDCPMMU>,
670 <&cru 667 <&cru PCLK_EDP_CTRL>,
671 <&cru 668 <&cru PCLK_HDMI_CTRL>,
672 <&cru 669 <&cru PCLK_HDCP>,
673 <&cru 670 <&cru PCLK_ISP>,
674 <&cru 671 <&cru PCLK_VIP>,
675 <&cru 672 <&cru PCLK_DPHYRX>,
676 <&cru 673 <&cru PCLK_DPHYTX0>,
677 <&cru 674 <&cru PCLK_MIPI_CSI>,
678 <&cru 675 <&cru PCLK_MIPI_DSI0>,
679 <&cru 676 <&cru SCLK_VOP0_PWM>,
680 <&cru 677 <&cru SCLK_EDP_24M>,
681 <&cru 678 <&cru SCLK_EDP>,
682 <&cru 679 <&cru SCLK_HDCP>,
683 <&cru 680 <&cru SCLK_ISP>,
684 <&cru 681 <&cru SCLK_RGA>,
685 <&cru 682 <&cru SCLK_HDMI_CEC>,
686 <&cru 683 <&cru SCLK_HDMI_HDCP>;
687 pm_qos = <&qos 684 pm_qos = <&qos_iep>,
688 <&qos 685 <&qos_isp_r0>,
689 <&qos 686 <&qos_isp_r1>,
690 <&qos 687 <&qos_isp_w0>,
691 <&qos 688 <&qos_isp_w1>,
692 <&qos 689 <&qos_vip>,
693 <&qos 690 <&qos_vop>,
694 <&qos 691 <&qos_rga_r>,
695 <&qos 692 <&qos_rga_w>;
696 #power-domain- 693 #power-domain-cells = <0>;
697 }; 694 };
698 695
699 /* 696 /*
700 * Note: ACLK_VCODEC/H 697 * Note: ACLK_VCODEC/HCLK_VCODEC are VCODEC
701 * (video endecoder & 698 * (video endecoder & decoder) clocks that on the
702 * ACLK_VCODEC_NIU and 699 * ACLK_VCODEC_NIU and HCLK_VCODEC_NIU (NOC).
703 */ 700 */
704 power-domain@RK3368_PD 701 power-domain@RK3368_PD_VIDEO {
705 reg = <RK3368_ 702 reg = <RK3368_PD_VIDEO>;
706 clocks = <&cru 703 clocks = <&cru ACLK_VIDEO>,
707 <&cru 704 <&cru HCLK_VIDEO>,
708 <&cru 705 <&cru SCLK_HEVC_CABAC>,
709 <&cru 706 <&cru SCLK_HEVC_CORE>;
710 pm_qos = <&qos 707 pm_qos = <&qos_hevc_r>,
711 <&qos 708 <&qos_vpu_r>,
712 <&qos 709 <&qos_vpu_w>;
713 #power-domain- 710 #power-domain-cells = <0>;
714 }; 711 };
715 712
716 /* 713 /*
717 * Note: ACLK_GPU is t 714 * Note: ACLK_GPU is the GPU clock,
718 * and on the ACLK_GPU 715 * and on the ACLK_GPU_NIU (NOC).
719 */ 716 */
720 power-domain@RK3368_PD 717 power-domain@RK3368_PD_GPU_1 {
721 reg = <RK3368_ 718 reg = <RK3368_PD_GPU_1>;
722 clocks = <&cru 719 clocks = <&cru ACLK_GPU_CFG>,
723 <&cru 720 <&cru ACLK_GPU_MEM>,
724 <&cru 721 <&cru SCLK_GPU_CORE>;
725 pm_qos = <&qos 722 pm_qos = <&qos_gpu>;
726 #power-domain- 723 #power-domain-cells = <0>;
727 }; 724 };
728 }; 725 };
729 }; 726 };
730 727
731 pmugrf: syscon@ff738000 { 728 pmugrf: syscon@ff738000 {
732 compatible = "rockchip,rk3368- 729 compatible = "rockchip,rk3368-pmugrf", "syscon", "simple-mfd";
733 reg = <0x0 0xff738000 0x0 0x10 730 reg = <0x0 0xff738000 0x0 0x1000>;
734 731
735 pmu_io_domains: io-domains { 732 pmu_io_domains: io-domains {
736 compatible = "rockchip 733 compatible = "rockchip,rk3368-pmu-io-voltage-domain";
737 status = "disabled"; 734 status = "disabled";
738 }; 735 };
739 736
740 reboot-mode { 737 reboot-mode {
741 compatible = "syscon-r 738 compatible = "syscon-reboot-mode";
742 offset = <0x200>; 739 offset = <0x200>;
743 mode-normal = <BOOT_NO 740 mode-normal = <BOOT_NORMAL>;
744 mode-recovery = <BOOT_ 741 mode-recovery = <BOOT_RECOVERY>;
745 mode-bootloader = <BOO 742 mode-bootloader = <BOOT_FASTBOOT>;
746 mode-loader = <BOOT_BL 743 mode-loader = <BOOT_BL_DOWNLOAD>;
747 }; 744 };
748 }; 745 };
749 746
750 cru: clock-controller@ff760000 { 747 cru: clock-controller@ff760000 {
751 compatible = "rockchip,rk3368- 748 compatible = "rockchip,rk3368-cru";
752 reg = <0x0 0xff760000 0x0 0x10 749 reg = <0x0 0xff760000 0x0 0x1000>;
753 clocks = <&xin24m>; 750 clocks = <&xin24m>;
754 clock-names = "xin24m"; 751 clock-names = "xin24m";
755 rockchip,grf = <&grf>; 752 rockchip,grf = <&grf>;
756 #clock-cells = <1>; 753 #clock-cells = <1>;
757 #reset-cells = <1>; 754 #reset-cells = <1>;
758 }; 755 };
759 756
760 grf: syscon@ff770000 { 757 grf: syscon@ff770000 {
761 compatible = "rockchip,rk3368- 758 compatible = "rockchip,rk3368-grf", "syscon", "simple-mfd";
762 reg = <0x0 0xff770000 0x0 0x10 759 reg = <0x0 0xff770000 0x0 0x1000>;
763 760
764 io_domains: io-domains { 761 io_domains: io-domains {
765 compatible = "rockchip 762 compatible = "rockchip,rk3368-io-voltage-domain";
766 status = "disabled"; 763 status = "disabled";
767 }; 764 };
768 }; 765 };
769 766
770 wdt: watchdog@ff800000 { 767 wdt: watchdog@ff800000 {
771 compatible = "rockchip,rk3368- 768 compatible = "rockchip,rk3368-wdt", "snps,dw-wdt";
772 reg = <0x0 0xff800000 0x0 0x10 769 reg = <0x0 0xff800000 0x0 0x100>;
773 clocks = <&cru PCLK_WDT>; 770 clocks = <&cru PCLK_WDT>;
774 interrupts = <GIC_SPI 79 IRQ_T 771 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
775 status = "disabled"; 772 status = "disabled";
776 }; 773 };
777 774
778 timer0: timer@ff810000 { 775 timer0: timer@ff810000 {
779 compatible = "rockchip,rk3368- 776 compatible = "rockchip,rk3368-timer", "rockchip,rk3288-timer";
780 reg = <0x0 0xff810000 0x0 0x20 777 reg = <0x0 0xff810000 0x0 0x20>;
781 interrupts = <GIC_SPI 66 IRQ_T 778 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
782 clocks = <&cru PCLK_TIMER0>, < 779 clocks = <&cru PCLK_TIMER0>, <&cru SCLK_TIMER00>;
783 clock-names = "pclk", "timer"; 780 clock-names = "pclk", "timer";
784 }; 781 };
785 782
786 spdif: spdif@ff880000 { 783 spdif: spdif@ff880000 {
787 compatible = "rockchip,rk3368- 784 compatible = "rockchip,rk3368-spdif";
788 reg = <0x0 0xff880000 0x0 0x10 785 reg = <0x0 0xff880000 0x0 0x1000>;
789 interrupts = <GIC_SPI 54 IRQ_T 786 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
790 clocks = <&cru SCLK_SPDIF_8CH> 787 clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>;
791 clock-names = "mclk", "hclk"; 788 clock-names = "mclk", "hclk";
792 dmas = <&dmac_bus 3>; 789 dmas = <&dmac_bus 3>;
793 dma-names = "tx"; 790 dma-names = "tx";
794 pinctrl-names = "default"; 791 pinctrl-names = "default";
795 pinctrl-0 = <&spdif_tx>; 792 pinctrl-0 = <&spdif_tx>;
796 #sound-dai-cells = <0>; 793 #sound-dai-cells = <0>;
797 status = "disabled"; 794 status = "disabled";
798 }; 795 };
799 796
800 i2s_2ch: i2s-2ch@ff890000 { 797 i2s_2ch: i2s-2ch@ff890000 {
801 compatible = "rockchip,rk3368- 798 compatible = "rockchip,rk3368-i2s", "rockchip,rk3066-i2s";
802 reg = <0x0 0xff890000 0x0 0x10 799 reg = <0x0 0xff890000 0x0 0x1000>;
803 interrupts = <GIC_SPI 40 IRQ_T 800 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
804 clock-names = "i2s_clk", "i2s_ 801 clock-names = "i2s_clk", "i2s_hclk";
805 clocks = <&cru SCLK_I2S_2CH>, 802 clocks = <&cru SCLK_I2S_2CH>, <&cru HCLK_I2S_2CH>;
806 dmas = <&dmac_bus 6>, <&dmac_b 803 dmas = <&dmac_bus 6>, <&dmac_bus 7>;
807 dma-names = "tx", "rx"; 804 dma-names = "tx", "rx";
808 #sound-dai-cells = <0>; 805 #sound-dai-cells = <0>;
809 status = "disabled"; 806 status = "disabled";
810 }; 807 };
811 808
812 i2s_8ch: i2s-8ch@ff898000 { 809 i2s_8ch: i2s-8ch@ff898000 {
813 compatible = "rockchip,rk3368- 810 compatible = "rockchip,rk3368-i2s", "rockchip,rk3066-i2s";
814 reg = <0x0 0xff898000 0x0 0x10 811 reg = <0x0 0xff898000 0x0 0x1000>;
815 interrupts = <GIC_SPI 53 IRQ_T 812 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
816 clock-names = "i2s_clk", "i2s_ 813 clock-names = "i2s_clk", "i2s_hclk";
817 clocks = <&cru SCLK_I2S_8CH>, 814 clocks = <&cru SCLK_I2S_8CH>, <&cru HCLK_I2S_8CH>;
818 dmas = <&dmac_bus 0>, <&dmac_b 815 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
819 dma-names = "tx", "rx"; 816 dma-names = "tx", "rx";
820 pinctrl-names = "default"; 817 pinctrl-names = "default";
821 pinctrl-0 = <&i2s_8ch_bus>; 818 pinctrl-0 = <&i2s_8ch_bus>;
822 #sound-dai-cells = <0>; 819 #sound-dai-cells = <0>;
823 status = "disabled"; 820 status = "disabled";
824 }; 821 };
825 822
826 iep_mmu: iommu@ff900800 { 823 iep_mmu: iommu@ff900800 {
827 compatible = "rockchip,iommu"; 824 compatible = "rockchip,iommu";
828 reg = <0x0 0xff900800 0x0 0x10 825 reg = <0x0 0xff900800 0x0 0x100>;
829 interrupts = <GIC_SPI 17 IRQ_T 826 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
830 clocks = <&cru ACLK_IEP>, <&cr 827 clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
831 clock-names = "aclk", "iface"; 828 clock-names = "aclk", "iface";
832 power-domains = <&power RK3368 829 power-domains = <&power RK3368_PD_VIO>;
833 #iommu-cells = <0>; 830 #iommu-cells = <0>;
834 status = "disabled"; 831 status = "disabled";
835 }; 832 };
836 833
837 isp_mmu: iommu@ff914000 { 834 isp_mmu: iommu@ff914000 {
838 compatible = "rockchip,iommu"; 835 compatible = "rockchip,iommu";
839 reg = <0x0 0xff914000 0x0 0x10 836 reg = <0x0 0xff914000 0x0 0x100>,
840 <0x0 0xff915000 0x0 0x10 837 <0x0 0xff915000 0x0 0x100>;
841 interrupts = <GIC_SPI 14 IRQ_T 838 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
842 clocks = <&cru ACLK_ISP>, <&cr 839 clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>;
843 clock-names = "aclk", "iface"; 840 clock-names = "aclk", "iface";
844 #iommu-cells = <0>; 841 #iommu-cells = <0>;
845 power-domains = <&power RK3368 842 power-domains = <&power RK3368_PD_VIO>;
846 rockchip,disable-mmu-reset; 843 rockchip,disable-mmu-reset;
847 status = "disabled"; 844 status = "disabled";
848 }; 845 };
849 846
850 vop_mmu: iommu@ff930300 { 847 vop_mmu: iommu@ff930300 {
851 compatible = "rockchip,iommu"; 848 compatible = "rockchip,iommu";
852 reg = <0x0 0xff930300 0x0 0x10 849 reg = <0x0 0xff930300 0x0 0x100>;
853 interrupts = <GIC_SPI 15 IRQ_T 850 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
854 clocks = <&cru ACLK_VOP>, <&cr 851 clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
855 clock-names = "aclk", "iface"; 852 clock-names = "aclk", "iface";
856 power-domains = <&power RK3368 853 power-domains = <&power RK3368_PD_VIO>;
857 #iommu-cells = <0>; 854 #iommu-cells = <0>;
858 status = "disabled"; 855 status = "disabled";
859 }; 856 };
860 857
861 hevc_mmu: iommu@ff9a0440 { 858 hevc_mmu: iommu@ff9a0440 {
862 compatible = "rockchip,iommu"; 859 compatible = "rockchip,iommu";
863 reg = <0x0 0xff9a0440 0x0 0x40 860 reg = <0x0 0xff9a0440 0x0 0x40>,
864 <0x0 0xff9a0480 0x0 0x40 861 <0x0 0xff9a0480 0x0 0x40>;
865 interrupts = <GIC_SPI 12 IRQ_T 862 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
866 clocks = <&cru ACLK_VIDEO>, <& 863 clocks = <&cru ACLK_VIDEO>, <&cru HCLK_VIDEO>;
867 clock-names = "aclk", "iface"; 864 clock-names = "aclk", "iface";
868 #iommu-cells = <0>; 865 #iommu-cells = <0>;
869 status = "disabled"; 866 status = "disabled";
870 }; 867 };
871 868
872 vpu_mmu: iommu@ff9a0800 { 869 vpu_mmu: iommu@ff9a0800 {
873 compatible = "rockchip,iommu"; 870 compatible = "rockchip,iommu";
874 reg = <0x0 0xff9a0800 0x0 0x10 871 reg = <0x0 0xff9a0800 0x0 0x100>;
875 interrupts = <GIC_SPI 9 IRQ_TY 872 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
876 <GIC_SPI 10 IRQ_T 873 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
877 clocks = <&cru ACLK_VIDEO>, <& 874 clocks = <&cru ACLK_VIDEO>, <&cru HCLK_VIDEO>;
878 clock-names = "aclk", "iface"; 875 clock-names = "aclk", "iface";
879 #iommu-cells = <0>; 876 #iommu-cells = <0>;
880 status = "disabled"; 877 status = "disabled";
881 }; 878 };
882 879
883 qos_iep: qos@ffad0000 { 880 qos_iep: qos@ffad0000 {
884 compatible = "rockchip,rk3368- 881 compatible = "rockchip,rk3368-qos", "syscon";
885 reg = <0x0 0xffad0000 0x0 0x20 882 reg = <0x0 0xffad0000 0x0 0x20>;
886 }; 883 };
887 884
888 qos_isp_r0: qos@ffad0080 { 885 qos_isp_r0: qos@ffad0080 {
889 compatible = "rockchip,rk3368- 886 compatible = "rockchip,rk3368-qos", "syscon";
890 reg = <0x0 0xffad0080 0x0 0x20 887 reg = <0x0 0xffad0080 0x0 0x20>;
891 }; 888 };
892 889
893 qos_isp_r1: qos@ffad0100 { 890 qos_isp_r1: qos@ffad0100 {
894 compatible = "rockchip,rk3368- 891 compatible = "rockchip,rk3368-qos", "syscon";
895 reg = <0x0 0xffad0100 0x0 0x20 892 reg = <0x0 0xffad0100 0x0 0x20>;
896 }; 893 };
897 894
898 qos_isp_w0: qos@ffad0180 { 895 qos_isp_w0: qos@ffad0180 {
899 compatible = "rockchip,rk3368- 896 compatible = "rockchip,rk3368-qos", "syscon";
900 reg = <0x0 0xffad0180 0x0 0x20 897 reg = <0x0 0xffad0180 0x0 0x20>;
901 }; 898 };
902 899
903 qos_isp_w1: qos@ffad0200 { 900 qos_isp_w1: qos@ffad0200 {
904 compatible = "rockchip,rk3368- 901 compatible = "rockchip,rk3368-qos", "syscon";
905 reg = <0x0 0xffad0200 0x0 0x20 902 reg = <0x0 0xffad0200 0x0 0x20>;
906 }; 903 };
907 904
908 qos_vip: qos@ffad0280 { 905 qos_vip: qos@ffad0280 {
909 compatible = "rockchip,rk3368- 906 compatible = "rockchip,rk3368-qos", "syscon";
910 reg = <0x0 0xffad0280 0x0 0x20 907 reg = <0x0 0xffad0280 0x0 0x20>;
911 }; 908 };
912 909
913 qos_vop: qos@ffad0300 { 910 qos_vop: qos@ffad0300 {
914 compatible = "rockchip,rk3368- 911 compatible = "rockchip,rk3368-qos", "syscon";
915 reg = <0x0 0xffad0300 0x0 0x20 912 reg = <0x0 0xffad0300 0x0 0x20>;
916 }; 913 };
917 914
918 qos_rga_r: qos@ffad0380 { 915 qos_rga_r: qos@ffad0380 {
919 compatible = "rockchip,rk3368- 916 compatible = "rockchip,rk3368-qos", "syscon";
920 reg = <0x0 0xffad0380 0x0 0x20 917 reg = <0x0 0xffad0380 0x0 0x20>;
921 }; 918 };
922 919
923 qos_rga_w: qos@ffad0400 { 920 qos_rga_w: qos@ffad0400 {
924 compatible = "rockchip,rk3368- 921 compatible = "rockchip,rk3368-qos", "syscon";
925 reg = <0x0 0xffad0400 0x0 0x20 922 reg = <0x0 0xffad0400 0x0 0x20>;
926 }; 923 };
927 924
928 qos_hevc_r: qos@ffae0000 { 925 qos_hevc_r: qos@ffae0000 {
929 compatible = "rockchip,rk3368- 926 compatible = "rockchip,rk3368-qos", "syscon";
930 reg = <0x0 0xffae0000 0x0 0x20 927 reg = <0x0 0xffae0000 0x0 0x20>;
931 }; 928 };
932 929
933 qos_vpu_r: qos@ffae0100 { 930 qos_vpu_r: qos@ffae0100 {
934 compatible = "rockchip,rk3368- 931 compatible = "rockchip,rk3368-qos", "syscon";
935 reg = <0x0 0xffae0100 0x0 0x20 932 reg = <0x0 0xffae0100 0x0 0x20>;
936 }; 933 };
937 934
938 qos_vpu_w: qos@ffae0180 { 935 qos_vpu_w: qos@ffae0180 {
939 compatible = "rockchip,rk3368- 936 compatible = "rockchip,rk3368-qos", "syscon";
940 reg = <0x0 0xffae0180 0x0 0x20 937 reg = <0x0 0xffae0180 0x0 0x20>;
941 }; 938 };
942 939
943 qos_gpu: qos@ffaf0000 { 940 qos_gpu: qos@ffaf0000 {
944 compatible = "rockchip,rk3368- 941 compatible = "rockchip,rk3368-qos", "syscon";
945 reg = <0x0 0xffaf0000 0x0 0x20 942 reg = <0x0 0xffaf0000 0x0 0x20>;
946 }; 943 };
947 944
948 efuse256: efuse@ffb00000 { 945 efuse256: efuse@ffb00000 {
949 compatible = "rockchip,rk3368- 946 compatible = "rockchip,rk3368-efuse";
950 reg = <0x0 0xffb00000 0x0 0x20 947 reg = <0x0 0xffb00000 0x0 0x20>;
951 #address-cells = <1>; 948 #address-cells = <1>;
952 #size-cells = <1>; 949 #size-cells = <1>;
953 clocks = <&cru PCLK_EFUSE256>; 950 clocks = <&cru PCLK_EFUSE256>;
954 clock-names = "pclk_efuse"; 951 clock-names = "pclk_efuse";
955 952
956 cpu_leakage: cpu-leakage@17 { 953 cpu_leakage: cpu-leakage@17 {
957 reg = <0x17 0x1>; 954 reg = <0x17 0x1>;
958 }; 955 };
959 temp_adjust: temp-adjust@1f { 956 temp_adjust: temp-adjust@1f {
960 reg = <0x1f 0x1>; 957 reg = <0x1f 0x1>;
961 }; 958 };
962 }; 959 };
963 960
964 gic: interrupt-controller@ffb71000 { 961 gic: interrupt-controller@ffb71000 {
965 compatible = "arm,gic-400"; 962 compatible = "arm,gic-400";
966 interrupt-controller; 963 interrupt-controller;
967 #interrupt-cells = <3>; 964 #interrupt-cells = <3>;
968 #address-cells = <0>; 965 #address-cells = <0>;
969 966
970 reg = <0x0 0xffb71000 0x0 0x10 967 reg = <0x0 0xffb71000 0x0 0x1000>,
971 <0x0 0xffb72000 0x0 0x20 968 <0x0 0xffb72000 0x0 0x2000>,
972 <0x0 0xffb74000 0x0 0x20 969 <0x0 0xffb74000 0x0 0x2000>,
973 <0x0 0xffb76000 0x0 0x20 970 <0x0 0xffb76000 0x0 0x2000>;
974 interrupts = <GIC_PPI 9 971 interrupts = <GIC_PPI 9
975 (GIC_CPU_MASK_SIMPLE(8) 972 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
976 }; 973 };
977 974
978 pinctrl: pinctrl { 975 pinctrl: pinctrl {
979 compatible = "rockchip,rk3368- 976 compatible = "rockchip,rk3368-pinctrl";
980 rockchip,grf = <&grf>; 977 rockchip,grf = <&grf>;
981 rockchip,pmu = <&pmugrf>; 978 rockchip,pmu = <&pmugrf>;
982 #address-cells = <0x2>; 979 #address-cells = <0x2>;
983 #size-cells = <0x2>; 980 #size-cells = <0x2>;
984 ranges; 981 ranges;
985 982
986 gpio0: gpio@ff750000 { 983 gpio0: gpio@ff750000 {
987 compatible = "rockchip 984 compatible = "rockchip,gpio-bank";
988 reg = <0x0 0xff750000 985 reg = <0x0 0xff750000 0x0 0x100>;
989 clocks = <&cru PCLK_GP 986 clocks = <&cru PCLK_GPIO0>;
990 interrupts = <GIC_SPI 987 interrupts = <GIC_SPI 0x51 IRQ_TYPE_LEVEL_HIGH>;
991 988
992 gpio-controller; 989 gpio-controller;
993 #gpio-cells = <0x2>; 990 #gpio-cells = <0x2>;
994 991
995 interrupt-controller; 992 interrupt-controller;
996 #interrupt-cells = <0x 993 #interrupt-cells = <0x2>;
997 }; 994 };
998 995
999 gpio1: gpio@ff780000 { 996 gpio1: gpio@ff780000 {
1000 compatible = "rockchi 997 compatible = "rockchip,gpio-bank";
1001 reg = <0x0 0xff780000 998 reg = <0x0 0xff780000 0x0 0x100>;
1002 clocks = <&cru PCLK_G 999 clocks = <&cru PCLK_GPIO1>;
1003 interrupts = <GIC_SPI 1000 interrupts = <GIC_SPI 0x52 IRQ_TYPE_LEVEL_HIGH>;
1004 1001
1005 gpio-controller; 1002 gpio-controller;
1006 #gpio-cells = <0x2>; 1003 #gpio-cells = <0x2>;
1007 1004
1008 interrupt-controller; 1005 interrupt-controller;
1009 #interrupt-cells = <0 1006 #interrupt-cells = <0x2>;
1010 }; 1007 };
1011 1008
1012 gpio2: gpio@ff790000 { 1009 gpio2: gpio@ff790000 {
1013 compatible = "rockchi 1010 compatible = "rockchip,gpio-bank";
1014 reg = <0x0 0xff790000 1011 reg = <0x0 0xff790000 0x0 0x100>;
1015 clocks = <&cru PCLK_G 1012 clocks = <&cru PCLK_GPIO2>;
1016 interrupts = <GIC_SPI 1013 interrupts = <GIC_SPI 0x53 IRQ_TYPE_LEVEL_HIGH>;
1017 1014
1018 gpio-controller; 1015 gpio-controller;
1019 #gpio-cells = <0x2>; 1016 #gpio-cells = <0x2>;
1020 1017
1021 interrupt-controller; 1018 interrupt-controller;
1022 #interrupt-cells = <0 1019 #interrupt-cells = <0x2>;
1023 }; 1020 };
1024 1021
1025 gpio3: gpio@ff7a0000 { 1022 gpio3: gpio@ff7a0000 {
1026 compatible = "rockchi 1023 compatible = "rockchip,gpio-bank";
1027 reg = <0x0 0xff7a0000 1024 reg = <0x0 0xff7a0000 0x0 0x100>;
1028 clocks = <&cru PCLK_G 1025 clocks = <&cru PCLK_GPIO3>;
1029 interrupts = <GIC_SPI 1026 interrupts = <GIC_SPI 0x54 IRQ_TYPE_LEVEL_HIGH>;
1030 1027
1031 gpio-controller; 1028 gpio-controller;
1032 #gpio-cells = <0x2>; 1029 #gpio-cells = <0x2>;
1033 1030
1034 interrupt-controller; 1031 interrupt-controller;
1035 #interrupt-cells = <0 1032 #interrupt-cells = <0x2>;
1036 }; 1033 };
1037 1034
1038 pcfg_pull_up: pcfg-pull-up { 1035 pcfg_pull_up: pcfg-pull-up {
1039 bias-pull-up; 1036 bias-pull-up;
1040 }; 1037 };
1041 1038
1042 pcfg_pull_down: pcfg-pull-dow 1039 pcfg_pull_down: pcfg-pull-down {
1043 bias-pull-down; 1040 bias-pull-down;
1044 }; 1041 };
1045 1042
1046 pcfg_pull_none: pcfg-pull-non 1043 pcfg_pull_none: pcfg-pull-none {
1047 bias-disable; 1044 bias-disable;
1048 }; 1045 };
1049 1046
1050 pcfg_pull_none_12ma: pcfg-pul 1047 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1051 bias-disable; 1048 bias-disable;
1052 drive-strength = <12> 1049 drive-strength = <12>;
1053 }; 1050 };
1054 1051
1055 emmc { 1052 emmc {
1056 emmc_clk: emmc-clk { 1053 emmc_clk: emmc-clk {
1057 rockchip,pins 1054 rockchip,pins = <2 RK_PA4 2 &pcfg_pull_none>;
1058 }; 1055 };
1059 1056
1060 emmc_cmd: emmc-cmd { 1057 emmc_cmd: emmc-cmd {
1061 rockchip,pins 1058 rockchip,pins = <1 RK_PD2 2 &pcfg_pull_up>;
1062 }; 1059 };
1063 1060
1064 emmc_pwr: emmc-pwr { 1061 emmc_pwr: emmc-pwr {
1065 rockchip,pins 1062 rockchip,pins = <1 RK_PD3 2 &pcfg_pull_up>;
1066 }; 1063 };
1067 1064
1068 emmc_bus1: emmc-bus1 1065 emmc_bus1: emmc-bus1 {
1069 rockchip,pins 1066 rockchip,pins = <1 RK_PC2 2 &pcfg_pull_up>;
1070 }; 1067 };
1071 1068
1072 emmc_bus4: emmc-bus4 1069 emmc_bus4: emmc-bus4 {
1073 rockchip,pins 1070 rockchip,pins = <1 RK_PC2 2 &pcfg_pull_up>,
1074 1071 <1 RK_PC3 2 &pcfg_pull_up>,
1075 1072 <1 RK_PC4 2 &pcfg_pull_up>,
1076 1073 <1 RK_PC5 2 &pcfg_pull_up>;
1077 }; 1074 };
1078 1075
1079 emmc_bus8: emmc-bus8 1076 emmc_bus8: emmc-bus8 {
1080 rockchip,pins 1077 rockchip,pins = <1 RK_PC2 2 &pcfg_pull_up>,
1081 1078 <1 RK_PC3 2 &pcfg_pull_up>,
1082 1079 <1 RK_PC4 2 &pcfg_pull_up>,
1083 1080 <1 RK_PC5 2 &pcfg_pull_up>,
1084 1081 <1 RK_PC6 2 &pcfg_pull_up>,
1085 1082 <1 RK_PC7 2 &pcfg_pull_up>,
1086 1083 <1 RK_PD0 2 &pcfg_pull_up>,
1087 1084 <1 RK_PD1 2 &pcfg_pull_up>;
1088 }; 1085 };
1089 }; 1086 };
1090 1087
1091 gmac { 1088 gmac {
1092 rgmii_pins: rgmii-pin 1089 rgmii_pins: rgmii-pins {
1093 rockchip,pins 1090 rockchip,pins = <3 RK_PC6 1 &pcfg_pull_none>,
1094 1091 <3 RK_PD0 1 &pcfg_pull_none>,
1095 1092 <3 RK_PC3 1 &pcfg_pull_none>,
1096 1093 <3 RK_PB0 1 &pcfg_pull_none_12ma>,
1097 1094 <3 RK_PB1 1 &pcfg_pull_none_12ma>,
1098 1095 <3 RK_PB2 1 &pcfg_pull_none_12ma>,
1099 1096 <3 RK_PB6 1 &pcfg_pull_none_12ma>,
1100 1097 <3 RK_PD4 1 &pcfg_pull_none_12ma>,
1101 1098 <3 RK_PB5 1 &pcfg_pull_none_12ma>,
1102 1099 <3 RK_PB7 1 &pcfg_pull_none>,
1103 1100 <3 RK_PC0 1 &pcfg_pull_none>,
1104 1101 <3 RK_PC1 1 &pcfg_pull_none>,
1105 1102 <3 RK_PC2 1 &pcfg_pull_none>,
1106 1103 <3 RK_PD1 1 &pcfg_pull_none>,
1107 1104 <3 RK_PC4 1 &pcfg_pull_none>;
1108 }; 1105 };
1109 1106
1110 rmii_pins: rmii-pins 1107 rmii_pins: rmii-pins {
1111 rockchip,pins 1108 rockchip,pins = <3 RK_PC6 1 &pcfg_pull_none>,
1112 1109 <3 RK_PD0 1 &pcfg_pull_none>,
1113 1110 <3 RK_PC3 1 &pcfg_pull_none>,
1114 1111 <3 RK_PB0 1 &pcfg_pull_none_12ma>,
1115 1112 <3 RK_PB1 1 &pcfg_pull_none_12ma>,
1116 1113 <3 RK_PB5 1 &pcfg_pull_none_12ma>,
1117 1114 <3 RK_PB7 1 &pcfg_pull_none>,
1118 1115 <3 RK_PC0 1 &pcfg_pull_none>,
1119 1116 <3 RK_PC4 1 &pcfg_pull_none>,
1120 1117 <3 RK_PC5 1 &pcfg_pull_none>;
1121 }; 1118 };
1122 }; 1119 };
1123 1120
1124 i2c0 { 1121 i2c0 {
1125 i2c0_xfer: i2c0-xfer 1122 i2c0_xfer: i2c0-xfer {
1126 rockchip,pins 1123 rockchip,pins = <0 RK_PA6 1 &pcfg_pull_none>,
1127 1124 <0 RK_PA7 1 &pcfg_pull_none>;
1128 }; 1125 };
1129 }; 1126 };
1130 1127
1131 i2c1 { 1128 i2c1 {
1132 i2c1_xfer: i2c1-xfer 1129 i2c1_xfer: i2c1-xfer {
1133 rockchip,pins 1130 rockchip,pins = <2 RK_PC5 1 &pcfg_pull_none>,
1134 1131 <2 RK_PC6 1 &pcfg_pull_none>;
1135 }; 1132 };
1136 }; 1133 };
1137 1134
1138 i2c2 { 1135 i2c2 {
1139 i2c2_xfer: i2c2-xfer 1136 i2c2_xfer: i2c2-xfer {
1140 rockchip,pins 1137 rockchip,pins = <0 RK_PB1 2 &pcfg_pull_none>,
1141 1138 <3 RK_PD7 2 &pcfg_pull_none>;
1142 }; 1139 };
1143 }; 1140 };
1144 1141
1145 i2c3 { 1142 i2c3 {
1146 i2c3_xfer: i2c3-xfer 1143 i2c3_xfer: i2c3-xfer {
1147 rockchip,pins 1144 rockchip,pins = <1 RK_PC0 1 &pcfg_pull_none>,
1148 1145 <1 RK_PC1 1 &pcfg_pull_none>;
1149 }; 1146 };
1150 }; 1147 };
1151 1148
1152 i2c4 { 1149 i2c4 {
1153 i2c4_xfer: i2c4-xfer 1150 i2c4_xfer: i2c4-xfer {
1154 rockchip,pins 1151 rockchip,pins = <3 RK_PD0 2 &pcfg_pull_none>,
1155 1152 <3 RK_PD1 2 &pcfg_pull_none>;
1156 }; 1153 };
1157 }; 1154 };
1158 1155
1159 i2c5 { 1156 i2c5 {
1160 i2c5_xfer: i2c5-xfer 1157 i2c5_xfer: i2c5-xfer {
1161 rockchip,pins 1158 rockchip,pins = <3 RK_PD2 2 &pcfg_pull_none>,
1162 1159 <3 RK_PD3 2 &pcfg_pull_none>;
1163 }; 1160 };
1164 }; 1161 };
1165 1162
1166 i2s { 1163 i2s {
1167 i2s_8ch_bus: i2s-8ch- 1164 i2s_8ch_bus: i2s-8ch-bus {
1168 rockchip,pins 1165 rockchip,pins = <2 RK_PB4 1 &pcfg_pull_none>,
1169 1166 <2 RK_PB5 1 &pcfg_pull_none>,
1170 1167 <2 RK_PB6 1 &pcfg_pull_none>,
1171 1168 <2 RK_PB7 1 &pcfg_pull_none>,
1172 1169 <2 RK_PC0 1 &pcfg_pull_none>,
1173 1170 <2 RK_PC1 1 &pcfg_pull_none>,
1174 1171 <2 RK_PC2 1 &pcfg_pull_none>,
1175 1172 <2 RK_PC3 1 &pcfg_pull_none>,
1176 1173 <2 RK_PC4 1 &pcfg_pull_none>;
1177 }; 1174 };
1178 }; 1175 };
1179 1176
1180 pwm0 { 1177 pwm0 {
1181 pwm0_pin: pwm0-pin { 1178 pwm0_pin: pwm0-pin {
1182 rockchip,pins 1179 rockchip,pins = <3 RK_PB0 2 &pcfg_pull_none>;
1183 }; 1180 };
1184 }; 1181 };
1185 1182
1186 pwm1 { 1183 pwm1 {
1187 pwm1_pin: pwm1-pin { 1184 pwm1_pin: pwm1-pin {
1188 rockchip,pins 1185 rockchip,pins = <0 RK_PB0 2 &pcfg_pull_none>;
1189 }; 1186 };
1190 }; 1187 };
1191 1188
1192 pwm3 { 1189 pwm3 {
1193 pwm3_pin: pwm3-pin { 1190 pwm3_pin: pwm3-pin {
1194 rockchip,pins 1191 rockchip,pins = <3 RK_PD5 3 &pcfg_pull_none>;
1195 }; 1192 };
1196 }; 1193 };
1197 1194
1198 sdio0 { 1195 sdio0 {
1199 sdio0_bus1: sdio0-bus 1196 sdio0_bus1: sdio0-bus1 {
1200 rockchip,pins 1197 rockchip,pins = <2 RK_PD4 1 &pcfg_pull_up>;
1201 }; 1198 };
1202 1199
1203 sdio0_bus4: sdio0-bus 1200 sdio0_bus4: sdio0-bus4 {
1204 rockchip,pins 1201 rockchip,pins = <2 RK_PD4 1 &pcfg_pull_up>,
1205 1202 <2 RK_PD5 1 &pcfg_pull_up>,
1206 1203 <2 RK_PD6 1 &pcfg_pull_up>,
1207 1204 <2 RK_PD7 1 &pcfg_pull_up>;
1208 }; 1205 };
1209 1206
1210 sdio0_cmd: sdio0-cmd 1207 sdio0_cmd: sdio0-cmd {
1211 rockchip,pins 1208 rockchip,pins = <3 RK_PA0 1 &pcfg_pull_up>;
1212 }; 1209 };
1213 1210
1214 sdio0_clk: sdio0-clk 1211 sdio0_clk: sdio0-clk {
1215 rockchip,pins 1212 rockchip,pins = <3 RK_PA1 1 &pcfg_pull_none>;
1216 }; 1213 };
1217 1214
1218 sdio0_cd: sdio0-cd { 1215 sdio0_cd: sdio0-cd {
1219 rockchip,pins 1216 rockchip,pins = <3 RK_PA2 1 &pcfg_pull_up>;
1220 }; 1217 };
1221 1218
1222 sdio0_wp: sdio0-wp { 1219 sdio0_wp: sdio0-wp {
1223 rockchip,pins 1220 rockchip,pins = <3 RK_PA3 1 &pcfg_pull_up>;
1224 }; 1221 };
1225 1222
1226 sdio0_pwr: sdio0-pwr 1223 sdio0_pwr: sdio0-pwr {
1227 rockchip,pins 1224 rockchip,pins = <3 RK_PA4 1 &pcfg_pull_up>;
1228 }; 1225 };
1229 1226
1230 sdio0_bkpwr: sdio0-bk 1227 sdio0_bkpwr: sdio0-bkpwr {
1231 rockchip,pins 1228 rockchip,pins = <3 RK_PA5 1 &pcfg_pull_up>;
1232 }; 1229 };
1233 1230
1234 sdio0_int: sdio0-int 1231 sdio0_int: sdio0-int {
1235 rockchip,pins 1232 rockchip,pins = <3 RK_PA6 1 &pcfg_pull_up>;
1236 }; 1233 };
1237 }; 1234 };
1238 1235
1239 sdmmc { 1236 sdmmc {
1240 sdmmc_clk: sdmmc-clk 1237 sdmmc_clk: sdmmc-clk {
1241 rockchip,pins 1238 rockchip,pins = <2 RK_PB1 1 &pcfg_pull_none>;
1242 }; 1239 };
1243 1240
1244 sdmmc_cmd: sdmmc-cmd 1241 sdmmc_cmd: sdmmc-cmd {
1245 rockchip,pins 1242 rockchip,pins = <2 RK_PB2 1 &pcfg_pull_up>;
1246 }; 1243 };
1247 1244
1248 sdmmc_cd: sdmmc-cd { 1245 sdmmc_cd: sdmmc-cd {
1249 rockchip,pins 1246 rockchip,pins = <2 RK_PB3 1 &pcfg_pull_up>;
1250 }; 1247 };
1251 1248
1252 sdmmc_bus1: sdmmc-bus 1249 sdmmc_bus1: sdmmc-bus1 {
1253 rockchip,pins 1250 rockchip,pins = <2 RK_PA5 1 &pcfg_pull_up>;
1254 }; 1251 };
1255 1252
1256 sdmmc_bus4: sdmmc-bus 1253 sdmmc_bus4: sdmmc-bus4 {
1257 rockchip,pins 1254 rockchip,pins = <2 RK_PA5 1 &pcfg_pull_up>,
1258 1255 <2 RK_PA6 1 &pcfg_pull_up>,
1259 1256 <2 RK_PA7 1 &pcfg_pull_up>,
1260 1257 <2 RK_PB0 1 &pcfg_pull_up>;
1261 }; 1258 };
1262 }; 1259 };
1263 1260
1264 spdif { 1261 spdif {
1265 spdif_tx: spdif-tx { 1262 spdif_tx: spdif-tx {
1266 rockchip,pins 1263 rockchip,pins = <2 RK_PC7 1 &pcfg_pull_none>;
1267 }; 1264 };
1268 }; 1265 };
1269 1266
1270 spi0 { 1267 spi0 {
1271 spi0_clk: spi0-clk { 1268 spi0_clk: spi0-clk {
1272 rockchip,pins 1269 rockchip,pins = <1 RK_PD5 2 &pcfg_pull_up>;
1273 }; 1270 };
1274 spi0_cs0: spi0-cs0 { 1271 spi0_cs0: spi0-cs0 {
1275 rockchip,pins 1272 rockchip,pins = <1 RK_PD0 3 &pcfg_pull_up>;
1276 }; 1273 };
1277 spi0_cs1: spi0-cs1 { 1274 spi0_cs1: spi0-cs1 {
1278 rockchip,pins 1275 rockchip,pins = <1 RK_PD1 3 &pcfg_pull_up>;
1279 }; 1276 };
1280 spi0_tx: spi0-tx { 1277 spi0_tx: spi0-tx {
1281 rockchip,pins 1278 rockchip,pins = <1 RK_PC7 3 &pcfg_pull_up>;
1282 }; 1279 };
1283 spi0_rx: spi0-rx { 1280 spi0_rx: spi0-rx {
1284 rockchip,pins 1281 rockchip,pins = <1 RK_PC6 3 &pcfg_pull_up>;
1285 }; 1282 };
1286 }; 1283 };
1287 1284
1288 spi1 { 1285 spi1 {
1289 spi1_clk: spi1-clk { 1286 spi1_clk: spi1-clk {
1290 rockchip,pins 1287 rockchip,pins = <1 RK_PB6 2 &pcfg_pull_up>;
1291 }; 1288 };
1292 spi1_cs0: spi1-cs0 { 1289 spi1_cs0: spi1-cs0 {
1293 rockchip,pins 1290 rockchip,pins = <1 RK_PB7 2 &pcfg_pull_up>;
1294 }; 1291 };
1295 spi1_cs1: spi1-cs1 { 1292 spi1_cs1: spi1-cs1 {
1296 rockchip,pins 1293 rockchip,pins = <3 RK_PD4 2 &pcfg_pull_up>;
1297 }; 1294 };
1298 spi1_rx: spi1-rx { 1295 spi1_rx: spi1-rx {
1299 rockchip,pins 1296 rockchip,pins = <1 RK_PC0 2 &pcfg_pull_up>;
1300 }; 1297 };
1301 spi1_tx: spi1-tx { 1298 spi1_tx: spi1-tx {
1302 rockchip,pins 1299 rockchip,pins = <1 RK_PC1 2 &pcfg_pull_up>;
1303 }; 1300 };
1304 }; 1301 };
1305 1302
1306 spi2 { 1303 spi2 {
1307 spi2_clk: spi2-clk { 1304 spi2_clk: spi2-clk {
1308 rockchip,pins 1305 rockchip,pins = <0 RK_PB4 2 &pcfg_pull_up>;
1309 }; 1306 };
1310 spi2_cs0: spi2-cs0 { 1307 spi2_cs0: spi2-cs0 {
1311 rockchip,pins 1308 rockchip,pins = <0 RK_PB5 2 &pcfg_pull_up>;
1312 }; 1309 };
1313 spi2_rx: spi2-rx { 1310 spi2_rx: spi2-rx {
1314 rockchip,pins 1311 rockchip,pins = <0 RK_PB2 2 &pcfg_pull_up>;
1315 }; 1312 };
1316 spi2_tx: spi2-tx { 1313 spi2_tx: spi2-tx {
1317 rockchip,pins 1314 rockchip,pins = <0 RK_PB3 2 &pcfg_pull_up>;
1318 }; 1315 };
1319 }; 1316 };
1320 1317
1321 tsadc { 1318 tsadc {
1322 otp_pin: otp-pin { 1319 otp_pin: otp-pin {
1323 rockchip,pins 1320 rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
1324 }; 1321 };
1325 1322
1326 otp_out: otp-out { 1323 otp_out: otp-out {
1327 rockchip,pins 1324 rockchip,pins = <0 RK_PA3 1 &pcfg_pull_none>;
1328 }; 1325 };
1329 }; 1326 };
1330 1327
1331 uart0 { 1328 uart0 {
1332 uart0_xfer: uart0-xfe 1329 uart0_xfer: uart0-xfer {
1333 rockchip,pins 1330 rockchip,pins = <2 RK_PD0 1 &pcfg_pull_up>,
1334 1331 <2 RK_PD1 1 &pcfg_pull_none>;
1335 }; 1332 };
1336 1333
1337 uart0_cts: uart0-cts 1334 uart0_cts: uart0-cts {
1338 rockchip,pins 1335 rockchip,pins = <2 RK_PD2 1 &pcfg_pull_none>;
1339 }; 1336 };
1340 1337
1341 uart0_rts: uart0-rts 1338 uart0_rts: uart0-rts {
1342 rockchip,pins 1339 rockchip,pins = <2 RK_PD3 1 &pcfg_pull_none>;
1343 }; 1340 };
1344 }; 1341 };
1345 1342
1346 uart1 { 1343 uart1 {
1347 uart1_xfer: uart1-xfe 1344 uart1_xfer: uart1-xfer {
1348 rockchip,pins 1345 rockchip,pins = <0 RK_PC4 3 &pcfg_pull_up>,
1349 1346 <0 RK_PC5 3 &pcfg_pull_none>;
1350 }; 1347 };
1351 1348
1352 uart1_cts: uart1-cts 1349 uart1_cts: uart1-cts {
1353 rockchip,pins 1350 rockchip,pins = <0 RK_PC6 3 &pcfg_pull_none>;
1354 }; 1351 };
1355 1352
1356 uart1_rts: uart1-rts 1353 uart1_rts: uart1-rts {
1357 rockchip,pins 1354 rockchip,pins = <0 RK_PC7 3 &pcfg_pull_none>;
1358 }; 1355 };
1359 }; 1356 };
1360 1357
1361 uart2 { 1358 uart2 {
1362 uart2_xfer: uart2-xfe 1359 uart2_xfer: uart2-xfer {
1363 rockchip,pins 1360 rockchip,pins = <2 RK_PA6 2 &pcfg_pull_up>,
1364 1361 <2 RK_PA5 2 &pcfg_pull_none>;
1365 }; 1362 };
1366 /* no rts / cts for u 1363 /* no rts / cts for uart2 */
1367 }; 1364 };
1368 1365
1369 uart3 { 1366 uart3 {
1370 uart3_xfer: uart3-xfe 1367 uart3_xfer: uart3-xfer {
1371 rockchip,pins 1368 rockchip,pins = <3 RK_PD5 2 &pcfg_pull_up>,
1372 1369 <3 RK_PD6 3 &pcfg_pull_none>;
1373 }; 1370 };
1374 1371
1375 uart3_cts: uart3-cts 1372 uart3_cts: uart3-cts {
1376 rockchip,pins 1373 rockchip,pins = <3 RK_PC0 2 &pcfg_pull_none>;
1377 }; 1374 };
1378 1375
1379 uart3_rts: uart3-rts 1376 uart3_rts: uart3-rts {
1380 rockchip,pins 1377 rockchip,pins = <3 RK_PC1 2 &pcfg_pull_none>;
1381 }; 1378 };
1382 }; 1379 };
1383 1380
1384 uart4 { 1381 uart4 {
1385 uart4_xfer: uart4-xfe 1382 uart4_xfer: uart4-xfer {
1386 rockchip,pins 1383 rockchip,pins = <0 RK_PD3 3 &pcfg_pull_up>,
1387 1384 <0 RK_PD2 3 &pcfg_pull_none>;
1388 }; 1385 };
1389 1386
1390 uart4_cts: uart4-cts 1387 uart4_cts: uart4-cts {
1391 rockchip,pins 1388 rockchip,pins = <0 RK_PD0 3 &pcfg_pull_none>;
1392 }; 1389 };
1393 1390
1394 uart4_rts: uart4-rts 1391 uart4_rts: uart4-rts {
1395 rockchip,pins 1392 rockchip,pins = <0 RK_PD1 3 &pcfg_pull_none>;
1396 }; 1393 };
1397 }; 1394 };
1398 }; 1395 };
1399 }; 1396 };
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