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TOMOYO Linux Cross Reference
Linux/scripts/dtc/include-prefixes/arm64/rockchip/rk3368.dtsi

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Diff markup

Differences between /scripts/dtc/include-prefixes/arm64/rockchip/rk3368.dtsi (Architecture i386) and /scripts/dtc/include-prefixes/arm64/rockchip/rk3368.dtsi (Architecture ppc)


  1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)       1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
  2 /*                                                  2 /*
  3  * Copyright (c) 2015 Heiko Stuebner <heiko@snt      3  * Copyright (c) 2015 Heiko Stuebner <heiko@sntech.de>
  4  */                                                 4  */
  5                                                     5 
  6 #include <dt-bindings/clock/rk3368-cru.h>           6 #include <dt-bindings/clock/rk3368-cru.h>
  7 #include <dt-bindings/gpio/gpio.h>                  7 #include <dt-bindings/gpio/gpio.h>
  8 #include <dt-bindings/interrupt-controller/irq      8 #include <dt-bindings/interrupt-controller/irq.h>
  9 #include <dt-bindings/interrupt-controller/arm      9 #include <dt-bindings/interrupt-controller/arm-gic.h>
 10 #include <dt-bindings/pinctrl/rockchip.h>          10 #include <dt-bindings/pinctrl/rockchip.h>
 11 #include <dt-bindings/power/rk3368-power.h>        11 #include <dt-bindings/power/rk3368-power.h>
 12 #include <dt-bindings/soc/rockchip,boot-mode.h     12 #include <dt-bindings/soc/rockchip,boot-mode.h>
 13 #include <dt-bindings/thermal/thermal.h>           13 #include <dt-bindings/thermal/thermal.h>
 14                                                    14 
 15 / {                                                15 / {
 16         compatible = "rockchip,rk3368";            16         compatible = "rockchip,rk3368";
 17         interrupt-parent = <&gic>;                 17         interrupt-parent = <&gic>;
 18         #address-cells = <2>;                      18         #address-cells = <2>;
 19         #size-cells = <2>;                         19         #size-cells = <2>;
 20                                                    20 
 21         aliases {                                  21         aliases {
 22                 gpio0 = &gpio0;                    22                 gpio0 = &gpio0;
 23                 gpio1 = &gpio1;                    23                 gpio1 = &gpio1;
 24                 gpio2 = &gpio2;                    24                 gpio2 = &gpio2;
 25                 gpio3 = &gpio3;                    25                 gpio3 = &gpio3;
 26                 i2c0 = &i2c0;                      26                 i2c0 = &i2c0;
 27                 i2c1 = &i2c1;                      27                 i2c1 = &i2c1;
 28                 i2c2 = &i2c2;                      28                 i2c2 = &i2c2;
 29                 i2c3 = &i2c3;                      29                 i2c3 = &i2c3;
 30                 i2c4 = &i2c4;                      30                 i2c4 = &i2c4;
 31                 i2c5 = &i2c5;                      31                 i2c5 = &i2c5;
 32                 serial0 = &uart0;                  32                 serial0 = &uart0;
 33                 serial1 = &uart1;                  33                 serial1 = &uart1;
 34                 serial2 = &uart2;                  34                 serial2 = &uart2;
 35                 serial3 = &uart3;                  35                 serial3 = &uart3;
 36                 serial4 = &uart4;                  36                 serial4 = &uart4;
 37                 spi0 = &spi0;                      37                 spi0 = &spi0;
 38                 spi1 = &spi1;                      38                 spi1 = &spi1;
 39                 spi2 = &spi2;                      39                 spi2 = &spi2;
 40         };                                         40         };
 41                                                    41 
 42         cpus {                                     42         cpus {
 43                 #address-cells = <0x2>;            43                 #address-cells = <0x2>;
 44                 #size-cells = <0x0>;               44                 #size-cells = <0x0>;
 45                                                    45 
 46                 cpu-map {                          46                 cpu-map {
 47                         cluster0 {                 47                         cluster0 {
 48                                 core0 {            48                                 core0 {
 49                                         cpu =      49                                         cpu = <&cpu_b0>;
 50                                 };                 50                                 };
 51                                 core1 {            51                                 core1 {
 52                                         cpu =      52                                         cpu = <&cpu_b1>;
 53                                 };                 53                                 };
 54                                 core2 {            54                                 core2 {
 55                                         cpu =      55                                         cpu = <&cpu_b2>;
 56                                 };                 56                                 };
 57                                 core3 {            57                                 core3 {
 58                                         cpu =      58                                         cpu = <&cpu_b3>;
 59                                 };                 59                                 };
 60                         };                         60                         };
 61                                                    61 
 62                         cluster1 {                 62                         cluster1 {
 63                                 core0 {            63                                 core0 {
 64                                         cpu =      64                                         cpu = <&cpu_l0>;
 65                                 };                 65                                 };
 66                                 core1 {            66                                 core1 {
 67                                         cpu =      67                                         cpu = <&cpu_l1>;
 68                                 };                 68                                 };
 69                                 core2 {            69                                 core2 {
 70                                         cpu =      70                                         cpu = <&cpu_l2>;
 71                                 };                 71                                 };
 72                                 core3 {            72                                 core3 {
 73                                         cpu =      73                                         cpu = <&cpu_l3>;
 74                                 };                 74                                 };
 75                         };                         75                         };
 76                 };                                 76                 };
 77                                                    77 
 78                 cpu_l0: cpu@0 {                    78                 cpu_l0: cpu@0 {
 79                         device_type = "cpu";       79                         device_type = "cpu";
 80                         compatible = "arm,cort     80                         compatible = "arm,cortex-a53";
 81                         reg = <0x0 0x0>;           81                         reg = <0x0 0x0>;
 82                         enable-method = "psci"     82                         enable-method = "psci";
 83                         #cooling-cells = <2>;      83                         #cooling-cells = <2>; /* min followed by max */
 84                 };                                 84                 };
 85                                                    85 
 86                 cpu_l1: cpu@1 {                    86                 cpu_l1: cpu@1 {
 87                         device_type = "cpu";       87                         device_type = "cpu";
 88                         compatible = "arm,cort     88                         compatible = "arm,cortex-a53";
 89                         reg = <0x0 0x1>;           89                         reg = <0x0 0x1>;
 90                         enable-method = "psci"     90                         enable-method = "psci";
 91                         #cooling-cells = <2>;      91                         #cooling-cells = <2>; /* min followed by max */
 92                 };                                 92                 };
 93                                                    93 
 94                 cpu_l2: cpu@2 {                    94                 cpu_l2: cpu@2 {
 95                         device_type = "cpu";       95                         device_type = "cpu";
 96                         compatible = "arm,cort     96                         compatible = "arm,cortex-a53";
 97                         reg = <0x0 0x2>;           97                         reg = <0x0 0x2>;
 98                         enable-method = "psci"     98                         enable-method = "psci";
 99                         #cooling-cells = <2>;      99                         #cooling-cells = <2>; /* min followed by max */
100                 };                                100                 };
101                                                   101 
102                 cpu_l3: cpu@3 {                   102                 cpu_l3: cpu@3 {
103                         device_type = "cpu";      103                         device_type = "cpu";
104                         compatible = "arm,cort    104                         compatible = "arm,cortex-a53";
105                         reg = <0x0 0x3>;          105                         reg = <0x0 0x3>;
106                         enable-method = "psci"    106                         enable-method = "psci";
107                         #cooling-cells = <2>;     107                         #cooling-cells = <2>; /* min followed by max */
108                 };                                108                 };
109                                                   109 
110                 cpu_b0: cpu@100 {                 110                 cpu_b0: cpu@100 {
111                         device_type = "cpu";      111                         device_type = "cpu";
112                         compatible = "arm,cort    112                         compatible = "arm,cortex-a53";
113                         reg = <0x0 0x100>;        113                         reg = <0x0 0x100>;
114                         enable-method = "psci"    114                         enable-method = "psci";
115                         #cooling-cells = <2>;     115                         #cooling-cells = <2>; /* min followed by max */
116                 };                                116                 };
117                                                   117 
118                 cpu_b1: cpu@101 {                 118                 cpu_b1: cpu@101 {
119                         device_type = "cpu";      119                         device_type = "cpu";
120                         compatible = "arm,cort    120                         compatible = "arm,cortex-a53";
121                         reg = <0x0 0x101>;        121                         reg = <0x0 0x101>;
122                         enable-method = "psci"    122                         enable-method = "psci";
123                         #cooling-cells = <2>;     123                         #cooling-cells = <2>; /* min followed by max */
124                 };                                124                 };
125                                                   125 
126                 cpu_b2: cpu@102 {                 126                 cpu_b2: cpu@102 {
127                         device_type = "cpu";      127                         device_type = "cpu";
128                         compatible = "arm,cort    128                         compatible = "arm,cortex-a53";
129                         reg = <0x0 0x102>;        129                         reg = <0x0 0x102>;
130                         enable-method = "psci"    130                         enable-method = "psci";
131                         #cooling-cells = <2>;     131                         #cooling-cells = <2>; /* min followed by max */
132                 };                                132                 };
133                                                   133 
134                 cpu_b3: cpu@103 {                 134                 cpu_b3: cpu@103 {
135                         device_type = "cpu";      135                         device_type = "cpu";
136                         compatible = "arm,cort    136                         compatible = "arm,cortex-a53";
137                         reg = <0x0 0x103>;        137                         reg = <0x0 0x103>;
138                         enable-method = "psci"    138                         enable-method = "psci";
139                         #cooling-cells = <2>;     139                         #cooling-cells = <2>; /* min followed by max */
140                 };                                140                 };
141         };                                        141         };
142                                                   142 
143         arm-pmu {                                 143         arm-pmu {
144                 compatible = "arm,cortex-a53-p    144                 compatible = "arm,cortex-a53-pmu";
145                 interrupts = <GIC_SPI 112 IRQ_    145                 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
146                              <GIC_SPI 113 IRQ_    146                              <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
147                              <GIC_SPI 114 IRQ_    147                              <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
148                              <GIC_SPI 115 IRQ_    148                              <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
149                              <GIC_SPI 116 IRQ_    149                              <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
150                              <GIC_SPI 117 IRQ_    150                              <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
151                              <GIC_SPI 118 IRQ_    151                              <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
152                              <GIC_SPI 119 IRQ_    152                              <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
153                 interrupt-affinity = <&cpu_l0>    153                 interrupt-affinity = <&cpu_l0>, <&cpu_l1>, <&cpu_l2>,
154                                      <&cpu_l3>    154                                      <&cpu_l3>, <&cpu_b0>, <&cpu_b1>,
155                                      <&cpu_b2>    155                                      <&cpu_b2>, <&cpu_b3>;
156         };                                        156         };
157                                                   157 
158         psci {                                    158         psci {
159                 compatible = "arm,psci-0.2";      159                 compatible = "arm,psci-0.2";
160                 method = "smc";                   160                 method = "smc";
161         };                                        161         };
162                                                   162 
163         timer {                                   163         timer {
164                 compatible = "arm,armv8-timer"    164                 compatible = "arm,armv8-timer";
165                 interrupts = <GIC_PPI 13          165                 interrupts = <GIC_PPI 13
166                         (GIC_CPU_MASK_SIMPLE(8    166                         (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
167                              <GIC_PPI 14          167                              <GIC_PPI 14
168                         (GIC_CPU_MASK_SIMPLE(8    168                         (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
169                              <GIC_PPI 11          169                              <GIC_PPI 11
170                         (GIC_CPU_MASK_SIMPLE(8    170                         (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
171                              <GIC_PPI 10          171                              <GIC_PPI 10
172                         (GIC_CPU_MASK_SIMPLE(8    172                         (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
173         };                                        173         };
174                                                   174 
175         xin24m: oscillator {                      175         xin24m: oscillator {
176                 compatible = "fixed-clock";       176                 compatible = "fixed-clock";
177                 clock-frequency = <24000000>;     177                 clock-frequency = <24000000>;
178                 clock-output-names = "xin24m";    178                 clock-output-names = "xin24m";
179                 #clock-cells = <0>;               179                 #clock-cells = <0>;
180         };                                        180         };
181                                                   181 
182         sdmmc: mmc@ff0c0000 {                     182         sdmmc: mmc@ff0c0000 {
183                 compatible = "rockchip,rk3368-    183                 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
184                 reg = <0x0 0xff0c0000 0x0 0x40    184                 reg = <0x0 0xff0c0000 0x0 0x4000>;
185                 max-frequency = <150000000>;      185                 max-frequency = <150000000>;
186                 clocks = <&cru HCLK_SDMMC>, <&    186                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
187                          <&cru SCLK_SDMMC_DRV>    187                          <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
188                 clock-names = "biu", "ciu", "c    188                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
189                 fifo-depth = <0x100>;             189                 fifo-depth = <0x100>;
190                 interrupts = <GIC_SPI 32 IRQ_T    190                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
191                 resets = <&cru SRST_MMC0>;        191                 resets = <&cru SRST_MMC0>;
192                 reset-names = "reset";            192                 reset-names = "reset";
193                 status = "disabled";              193                 status = "disabled";
194         };                                        194         };
195                                                   195 
196         sdio0: mmc@ff0d0000 {                     196         sdio0: mmc@ff0d0000 {
197                 compatible = "rockchip,rk3368-    197                 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
198                 reg = <0x0 0xff0d0000 0x0 0x40    198                 reg = <0x0 0xff0d0000 0x0 0x4000>;
199                 max-frequency = <150000000>;      199                 max-frequency = <150000000>;
200                 clocks = <&cru HCLK_SDIO0>, <&    200                 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>,
201                          <&cru SCLK_SDIO0_DRV>    201                          <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
202                 clock-names = "biu", "ciu", "c    202                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
203                 fifo-depth = <0x100>;             203                 fifo-depth = <0x100>;
204                 interrupts = <GIC_SPI 33 IRQ_T    204                 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
205                 resets = <&cru SRST_SDIO0>;       205                 resets = <&cru SRST_SDIO0>;
206                 reset-names = "reset";            206                 reset-names = "reset";
207                 status = "disabled";              207                 status = "disabled";
208         };                                        208         };
209                                                   209 
210         emmc: mmc@ff0f0000 {                      210         emmc: mmc@ff0f0000 {
211                 compatible = "rockchip,rk3368-    211                 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
212                 reg = <0x0 0xff0f0000 0x0 0x40    212                 reg = <0x0 0xff0f0000 0x0 0x4000>;
213                 max-frequency = <150000000>;      213                 max-frequency = <150000000>;
214                 clocks = <&cru HCLK_EMMC>, <&c    214                 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
215                          <&cru SCLK_EMMC_DRV>,    215                          <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
216                 clock-names = "biu", "ciu", "c    216                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
217                 fifo-depth = <0x100>;             217                 fifo-depth = <0x100>;
218                 interrupts = <GIC_SPI 35 IRQ_T    218                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
219                 resets = <&cru SRST_EMMC>;        219                 resets = <&cru SRST_EMMC>;
220                 reset-names = "reset";            220                 reset-names = "reset";
221                 status = "disabled";              221                 status = "disabled";
222         };                                        222         };
223                                                   223 
224         saradc: saradc@ff100000 {                 224         saradc: saradc@ff100000 {
225                 compatible = "rockchip,saradc"    225                 compatible = "rockchip,saradc";
226                 reg = <0x0 0xff100000 0x0 0x10    226                 reg = <0x0 0xff100000 0x0 0x100>;
227                 interrupts = <GIC_SPI 36 IRQ_T    227                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
228                 #io-channel-cells = <1>;          228                 #io-channel-cells = <1>;
229                 clocks = <&cru SCLK_SARADC>, <    229                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
230                 clock-names = "saradc", "apb_p    230                 clock-names = "saradc", "apb_pclk";
231                 resets = <&cru SRST_SARADC>;      231                 resets = <&cru SRST_SARADC>;
232                 reset-names = "saradc-apb";       232                 reset-names = "saradc-apb";
233                 status = "disabled";              233                 status = "disabled";
234         };                                        234         };
235                                                   235 
236         spi0: spi@ff110000 {                      236         spi0: spi@ff110000 {
237                 compatible = "rockchip,rk3368-    237                 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
238                 reg = <0x0 0xff110000 0x0 0x10    238                 reg = <0x0 0xff110000 0x0 0x1000>;
239                 clocks = <&cru SCLK_SPI0>, <&c    239                 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
240                 clock-names = "spiclk", "apb_p    240                 clock-names = "spiclk", "apb_pclk";
241                 interrupts = <GIC_SPI 44 IRQ_T    241                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
242                 pinctrl-names = "default";        242                 pinctrl-names = "default";
243                 pinctrl-0 = <&spi0_clk &spi0_t    243                 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
244                 #address-cells = <1>;             244                 #address-cells = <1>;
245                 #size-cells = <0>;                245                 #size-cells = <0>;
246                 status = "disabled";              246                 status = "disabled";
247         };                                        247         };
248                                                   248 
249         spi1: spi@ff120000 {                      249         spi1: spi@ff120000 {
250                 compatible = "rockchip,rk3368-    250                 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
251                 reg = <0x0 0xff120000 0x0 0x10    251                 reg = <0x0 0xff120000 0x0 0x1000>;
252                 clocks = <&cru SCLK_SPI1>, <&c    252                 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
253                 clock-names = "spiclk", "apb_p    253                 clock-names = "spiclk", "apb_pclk";
254                 interrupts = <GIC_SPI 45 IRQ_T    254                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
255                 pinctrl-names = "default";        255                 pinctrl-names = "default";
256                 pinctrl-0 = <&spi1_clk &spi1_t    256                 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
257                 #address-cells = <1>;             257                 #address-cells = <1>;
258                 #size-cells = <0>;                258                 #size-cells = <0>;
259                 status = "disabled";              259                 status = "disabled";
260         };                                        260         };
261                                                   261 
262         spi2: spi@ff130000 {                      262         spi2: spi@ff130000 {
263                 compatible = "rockchip,rk3368-    263                 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
264                 reg = <0x0 0xff130000 0x0 0x10    264                 reg = <0x0 0xff130000 0x0 0x1000>;
265                 clocks = <&cru SCLK_SPI2>, <&c    265                 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
266                 clock-names = "spiclk", "apb_p    266                 clock-names = "spiclk", "apb_pclk";
267                 interrupts = <GIC_SPI 41 IRQ_T    267                 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
268                 pinctrl-names = "default";        268                 pinctrl-names = "default";
269                 pinctrl-0 = <&spi2_clk &spi2_t    269                 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
270                 #address-cells = <1>;             270                 #address-cells = <1>;
271                 #size-cells = <0>;                271                 #size-cells = <0>;
272                 status = "disabled";              272                 status = "disabled";
273         };                                        273         };
274                                                   274 
275         i2c2: i2c@ff140000 {                      275         i2c2: i2c@ff140000 {
276                 compatible = "rockchip,rk3368-    276                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
277                 reg = <0x0 0xff140000 0x0 0x10    277                 reg = <0x0 0xff140000 0x0 0x1000>;
278                 interrupts = <GIC_SPI 62 IRQ_T    278                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
279                 #address-cells = <1>;             279                 #address-cells = <1>;
280                 #size-cells = <0>;                280                 #size-cells = <0>;
281                 clock-names = "i2c";              281                 clock-names = "i2c";
282                 clocks = <&cru PCLK_I2C2>;        282                 clocks = <&cru PCLK_I2C2>;
283                 pinctrl-names = "default";        283                 pinctrl-names = "default";
284                 pinctrl-0 = <&i2c2_xfer>;         284                 pinctrl-0 = <&i2c2_xfer>;
285                 status = "disabled";              285                 status = "disabled";
286         };                                        286         };
287                                                   287 
288         i2c3: i2c@ff150000 {                      288         i2c3: i2c@ff150000 {
289                 compatible = "rockchip,rk3368-    289                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
290                 reg = <0x0 0xff150000 0x0 0x10    290                 reg = <0x0 0xff150000 0x0 0x1000>;
291                 interrupts = <GIC_SPI 63 IRQ_T    291                 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
292                 #address-cells = <1>;             292                 #address-cells = <1>;
293                 #size-cells = <0>;                293                 #size-cells = <0>;
294                 clock-names = "i2c";              294                 clock-names = "i2c";
295                 clocks = <&cru PCLK_I2C3>;        295                 clocks = <&cru PCLK_I2C3>;
296                 pinctrl-names = "default";        296                 pinctrl-names = "default";
297                 pinctrl-0 = <&i2c3_xfer>;         297                 pinctrl-0 = <&i2c3_xfer>;
298                 status = "disabled";              298                 status = "disabled";
299         };                                        299         };
300                                                   300 
301         i2c4: i2c@ff160000 {                      301         i2c4: i2c@ff160000 {
302                 compatible = "rockchip,rk3368-    302                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
303                 reg = <0x0 0xff160000 0x0 0x10    303                 reg = <0x0 0xff160000 0x0 0x1000>;
304                 interrupts = <GIC_SPI 64 IRQ_T    304                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
305                 #address-cells = <1>;             305                 #address-cells = <1>;
306                 #size-cells = <0>;                306                 #size-cells = <0>;
307                 clock-names = "i2c";              307                 clock-names = "i2c";
308                 clocks = <&cru PCLK_I2C4>;        308                 clocks = <&cru PCLK_I2C4>;
309                 pinctrl-names = "default";        309                 pinctrl-names = "default";
310                 pinctrl-0 = <&i2c4_xfer>;         310                 pinctrl-0 = <&i2c4_xfer>;
311                 status = "disabled";              311                 status = "disabled";
312         };                                        312         };
313                                                   313 
314         i2c5: i2c@ff170000 {                      314         i2c5: i2c@ff170000 {
315                 compatible = "rockchip,rk3368-    315                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
316                 reg = <0x0 0xff170000 0x0 0x10    316                 reg = <0x0 0xff170000 0x0 0x1000>;
317                 interrupts = <GIC_SPI 65 IRQ_T    317                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
318                 #address-cells = <1>;             318                 #address-cells = <1>;
319                 #size-cells = <0>;                319                 #size-cells = <0>;
320                 clock-names = "i2c";              320                 clock-names = "i2c";
321                 clocks = <&cru PCLK_I2C5>;        321                 clocks = <&cru PCLK_I2C5>;
322                 pinctrl-names = "default";        322                 pinctrl-names = "default";
323                 pinctrl-0 = <&i2c5_xfer>;         323                 pinctrl-0 = <&i2c5_xfer>;
324                 status = "disabled";              324                 status = "disabled";
325         };                                        325         };
326                                                   326 
327         uart0: serial@ff180000 {                  327         uart0: serial@ff180000 {
328                 compatible = "rockchip,rk3368-    328                 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
329                 reg = <0x0 0xff180000 0x0 0x10    329                 reg = <0x0 0xff180000 0x0 0x100>;
330                 clock-frequency = <24000000>;     330                 clock-frequency = <24000000>;
331                 clocks = <&cru SCLK_UART0>, <&    331                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
332                 clock-names = "baudclk", "apb_    332                 clock-names = "baudclk", "apb_pclk";
333                 interrupts = <GIC_SPI 55 IRQ_T    333                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
334                 reg-shift = <2>;                  334                 reg-shift = <2>;
335                 reg-io-width = <4>;               335                 reg-io-width = <4>;
336                 status = "disabled";              336                 status = "disabled";
337         };                                        337         };
338                                                   338 
339         uart1: serial@ff190000 {                  339         uart1: serial@ff190000 {
340                 compatible = "rockchip,rk3368-    340                 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
341                 reg = <0x0 0xff190000 0x0 0x10    341                 reg = <0x0 0xff190000 0x0 0x100>;
342                 clock-frequency = <24000000>;     342                 clock-frequency = <24000000>;
343                 clocks = <&cru SCLK_UART1>, <&    343                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
344                 clock-names = "baudclk", "apb_    344                 clock-names = "baudclk", "apb_pclk";
345                 interrupts = <GIC_SPI 56 IRQ_T    345                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
346                 reg-shift = <2>;                  346                 reg-shift = <2>;
347                 reg-io-width = <4>;               347                 reg-io-width = <4>;
348                 status = "disabled";              348                 status = "disabled";
349         };                                        349         };
350                                                   350 
351         uart3: serial@ff1b0000 {                  351         uart3: serial@ff1b0000 {
352                 compatible = "rockchip,rk3368-    352                 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
353                 reg = <0x0 0xff1b0000 0x0 0x10    353                 reg = <0x0 0xff1b0000 0x0 0x100>;
354                 clock-frequency = <24000000>;     354                 clock-frequency = <24000000>;
355                 clocks = <&cru SCLK_UART3>, <&    355                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
356                 clock-names = "baudclk", "apb_    356                 clock-names = "baudclk", "apb_pclk";
357                 interrupts = <GIC_SPI 58 IRQ_T    357                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
358                 reg-shift = <2>;                  358                 reg-shift = <2>;
359                 reg-io-width = <4>;               359                 reg-io-width = <4>;
360                 status = "disabled";              360                 status = "disabled";
361         };                                        361         };
362                                                   362 
363         uart4: serial@ff1c0000 {                  363         uart4: serial@ff1c0000 {
364                 compatible = "rockchip,rk3368-    364                 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
365                 reg = <0x0 0xff1c0000 0x0 0x10    365                 reg = <0x0 0xff1c0000 0x0 0x100>;
366                 clock-frequency = <24000000>;     366                 clock-frequency = <24000000>;
367                 clocks = <&cru SCLK_UART4>, <&    367                 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
368                 clock-names = "baudclk", "apb_    368                 clock-names = "baudclk", "apb_pclk";
369                 interrupts = <GIC_SPI 59 IRQ_T    369                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
370                 reg-shift = <2>;                  370                 reg-shift = <2>;
371                 reg-io-width = <4>;               371                 reg-io-width = <4>;
372                 status = "disabled";              372                 status = "disabled";
373         };                                        373         };
374                                                   374 
375         dmac_peri: dma-controller@ff250000 {      375         dmac_peri: dma-controller@ff250000 {
376                 compatible = "arm,pl330", "arm    376                 compatible = "arm,pl330", "arm,primecell";
377                 reg = <0x0 0xff250000 0x0 0x40    377                 reg = <0x0 0xff250000 0x0 0x4000>;
378                 interrupts = <GIC_SPI 2 IRQ_TY    378                 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
379                              <GIC_SPI 3 IRQ_TY    379                              <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
380                 #dma-cells = <1>;                 380                 #dma-cells = <1>;
381                 arm,pl330-broken-no-flushp;       381                 arm,pl330-broken-no-flushp;
382                 arm,pl330-periph-burst;           382                 arm,pl330-periph-burst;
383                 clocks = <&cru ACLK_DMAC_PERI>    383                 clocks = <&cru ACLK_DMAC_PERI>;
384                 clock-names = "apb_pclk";         384                 clock-names = "apb_pclk";
385         };                                        385         };
386                                                   386 
387         thermal-zones {                           387         thermal-zones {
388                 cpu_thermal: cpu-thermal {        388                 cpu_thermal: cpu-thermal {
389                         polling-delay-passive     389                         polling-delay-passive = <100>; /* milliseconds */
390                         polling-delay = <5000>    390                         polling-delay = <5000>; /* milliseconds */
391                                                   391 
392                         thermal-sensors = <&ts    392                         thermal-sensors = <&tsadc 0>;
393                                                   393 
394                         trips {                   394                         trips {
395                                 cpu_alert0: cp    395                                 cpu_alert0: cpu_alert0 {
396                                         temper    396                                         temperature = <75000>; /* millicelsius */
397                                         hyster    397                                         hysteresis = <2000>; /* millicelsius */
398                                         type =    398                                         type = "passive";
399                                 };                399                                 };
400                                 cpu_alert1: cp    400                                 cpu_alert1: cpu_alert1 {
401                                         temper    401                                         temperature = <80000>; /* millicelsius */
402                                         hyster    402                                         hysteresis = <2000>; /* millicelsius */
403                                         type =    403                                         type = "passive";
404                                 };                404                                 };
405                                 cpu_crit: cpu_    405                                 cpu_crit: cpu_crit {
406                                         temper    406                                         temperature = <95000>; /* millicelsius */
407                                         hyster    407                                         hysteresis = <2000>; /* millicelsius */
408                                         type =    408                                         type = "critical";
409                                 };                409                                 };
410                         };                        410                         };
411                                                   411 
412                         cooling-maps {            412                         cooling-maps {
413                                 map0 {            413                                 map0 {
414                                         trip =    414                                         trip = <&cpu_alert0>;
415                                         coolin    415                                         cooling-device =
416                                         <&cpu_    416                                         <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
417                                         <&cpu_    417                                         <&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
418                                         <&cpu_    418                                         <&cpu_b2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
419                                         <&cpu_    419                                         <&cpu_b3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
420                                 };                420                                 };
421                                 map1 {            421                                 map1 {
422                                         trip =    422                                         trip = <&cpu_alert1>;
423                                         coolin    423                                         cooling-device =
424                                         <&cpu_    424                                         <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
425                                         <&cpu_    425                                         <&cpu_l1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
426                                         <&cpu_    426                                         <&cpu_l2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
427                                         <&cpu_    427                                         <&cpu_l3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
428                                 };                428                                 };
429                         };                        429                         };
430                 };                                430                 };
431                                                   431 
432                 gpu_thermal: gpu-thermal {        432                 gpu_thermal: gpu-thermal {
433                         polling-delay-passive     433                         polling-delay-passive = <100>; /* milliseconds */
434                         polling-delay = <5000>    434                         polling-delay = <5000>; /* milliseconds */
435                                                   435 
436                         thermal-sensors = <&ts    436                         thermal-sensors = <&tsadc 1>;
437                                                   437 
438                         trips {                   438                         trips {
439                                 gpu_alert0: gp    439                                 gpu_alert0: gpu_alert0 {
440                                         temper    440                                         temperature = <80000>; /* millicelsius */
441                                         hyster    441                                         hysteresis = <2000>; /* millicelsius */
442                                         type =    442                                         type = "passive";
443                                 };                443                                 };
444                                 gpu_crit: gpu_    444                                 gpu_crit: gpu_crit {
445                                         temper    445                                         temperature = <115000>; /* millicelsius */
446                                         hyster    446                                         hysteresis = <2000>; /* millicelsius */
447                                         type =    447                                         type = "critical";
448                                 };                448                                 };
449                         };                        449                         };
450                                                   450 
451                         cooling-maps {            451                         cooling-maps {
452                                 map0 {            452                                 map0 {
453                                         trip =    453                                         trip = <&gpu_alert0>;
454                                         coolin    454                                         cooling-device =
455                                         <&cpu_    455                                         <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
456                                         <&cpu_    456                                         <&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
457                                         <&cpu_    457                                         <&cpu_b2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
458                                         <&cpu_    458                                         <&cpu_b3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
459                                 };                459                                 };
460                         };                        460                         };
461                 };                                461                 };
462         };                                        462         };
463                                                   463 
464         tsadc: tsadc@ff280000 {                   464         tsadc: tsadc@ff280000 {
465                 compatible = "rockchip,rk3368-    465                 compatible = "rockchip,rk3368-tsadc";
466                 reg = <0x0 0xff280000 0x0 0x10    466                 reg = <0x0 0xff280000 0x0 0x100>;
467                 interrupts = <GIC_SPI 37 IRQ_T    467                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
468                 clocks = <&cru SCLK_TSADC>, <&    468                 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
469                 clock-names = "tsadc", "apb_pc    469                 clock-names = "tsadc", "apb_pclk";
470                 resets = <&cru SRST_TSADC>;       470                 resets = <&cru SRST_TSADC>;
471                 reset-names = "tsadc-apb";        471                 reset-names = "tsadc-apb";
472                 pinctrl-names = "init", "defau    472                 pinctrl-names = "init", "default", "sleep";
473                 pinctrl-0 = <&otp_pin>;           473                 pinctrl-0 = <&otp_pin>;
474                 pinctrl-1 = <&otp_out>;           474                 pinctrl-1 = <&otp_out>;
475                 pinctrl-2 = <&otp_pin>;           475                 pinctrl-2 = <&otp_pin>;
476                 #thermal-sensor-cells = <1>;      476                 #thermal-sensor-cells = <1>;
477                 rockchip,hw-tshut-temp = <9500    477                 rockchip,hw-tshut-temp = <95000>;
478                 status = "disabled";              478                 status = "disabled";
479         };                                        479         };
480                                                   480 
481         gmac: ethernet@ff290000 {                 481         gmac: ethernet@ff290000 {
482                 compatible = "rockchip,rk3368-    482                 compatible = "rockchip,rk3368-gmac";
483                 reg = <0x0 0xff290000 0x0 0x10    483                 reg = <0x0 0xff290000 0x0 0x10000>;
484                 interrupts = <GIC_SPI 27 IRQ_T    484                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
485                 interrupt-names = "macirq";       485                 interrupt-names = "macirq";
486                 rockchip,grf = <&grf>;            486                 rockchip,grf = <&grf>;
487                 clocks = <&cru SCLK_MAC>,         487                 clocks = <&cru SCLK_MAC>,
488                         <&cru SCLK_MAC_RX>, <&    488                         <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>,
489                         <&cru SCLK_MACREF>, <&    489                         <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>,
490                         <&cru ACLK_GMAC>, <&cr    490                         <&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
491                 clock-names = "stmmaceth",        491                 clock-names = "stmmaceth",
492                         "mac_clk_rx", "mac_clk    492                         "mac_clk_rx", "mac_clk_tx",
493                         "clk_mac_ref", "clk_ma    493                         "clk_mac_ref", "clk_mac_refout",
494                         "aclk_mac", "pclk_mac"    494                         "aclk_mac", "pclk_mac";
495                 status = "disabled";              495                 status = "disabled";
496         };                                        496         };
497                                                   497 
498         usb_host0_ehci: usb@ff500000 {            498         usb_host0_ehci: usb@ff500000 {
499                 compatible = "generic-ehci";      499                 compatible = "generic-ehci";
500                 reg = <0x0 0xff500000 0x0 0x10    500                 reg = <0x0 0xff500000 0x0 0x100>;
501                 interrupts = <GIC_SPI 24 IRQ_T    501                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
502                 clocks = <&cru HCLK_HOST0>;       502                 clocks = <&cru HCLK_HOST0>;
503                 status = "disabled";              503                 status = "disabled";
504         };                                        504         };
505                                                   505 
506         usb_otg: usb@ff580000 {                   506         usb_otg: usb@ff580000 {
507                 compatible = "rockchip,rk3368-    507                 compatible = "rockchip,rk3368-usb", "rockchip,rk3066-usb",
508                                 "snps,dwc2";      508                                 "snps,dwc2";
509                 reg = <0x0 0xff580000 0x0 0x40    509                 reg = <0x0 0xff580000 0x0 0x40000>;
510                 interrupts = <GIC_SPI 23 IRQ_T    510                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
511                 clocks = <&cru HCLK_OTG0>;        511                 clocks = <&cru HCLK_OTG0>;
512                 clock-names = "otg";              512                 clock-names = "otg";
513                 dr_mode = "otg";                  513                 dr_mode = "otg";
514                 g-np-tx-fifo-size = <16>;         514                 g-np-tx-fifo-size = <16>;
515                 g-rx-fifo-size = <275>;           515                 g-rx-fifo-size = <275>;
516                 g-tx-fifo-size = <256 128 128     516                 g-tx-fifo-size = <256 128 128 64 64 32>;
517                 status = "disabled";              517                 status = "disabled";
518         };                                        518         };
519                                                   519 
520         dmac_bus: dma-controller@ff600000 {       520         dmac_bus: dma-controller@ff600000 {
521                 compatible = "arm,pl330", "arm    521                 compatible = "arm,pl330", "arm,primecell";
522                 reg = <0x0 0xff600000 0x0 0x40    522                 reg = <0x0 0xff600000 0x0 0x4000>;
523                 interrupts = <GIC_SPI 0 IRQ_TY    523                 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
524                              <GIC_SPI 1 IRQ_TY    524                              <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
525                 #dma-cells = <1>;                 525                 #dma-cells = <1>;
526                 arm,pl330-broken-no-flushp;       526                 arm,pl330-broken-no-flushp;
527                 arm,pl330-periph-burst;           527                 arm,pl330-periph-burst;
528                 clocks = <&cru ACLK_DMAC_BUS>;    528                 clocks = <&cru ACLK_DMAC_BUS>;
529                 clock-names = "apb_pclk";         529                 clock-names = "apb_pclk";
530         };                                        530         };
531                                                   531 
532         i2c0: i2c@ff650000 {                      532         i2c0: i2c@ff650000 {
533                 compatible = "rockchip,rk3368-    533                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
534                 reg = <0x0 0xff650000 0x0 0x10    534                 reg = <0x0 0xff650000 0x0 0x1000>;
535                 clocks = <&cru PCLK_I2C0>;        535                 clocks = <&cru PCLK_I2C0>;
536                 clock-names = "i2c";              536                 clock-names = "i2c";
537                 interrupts = <GIC_SPI 60 IRQ_T    537                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
538                 pinctrl-names = "default";        538                 pinctrl-names = "default";
539                 pinctrl-0 = <&i2c0_xfer>;         539                 pinctrl-0 = <&i2c0_xfer>;
540                 #address-cells = <1>;             540                 #address-cells = <1>;
541                 #size-cells = <0>;                541                 #size-cells = <0>;
542                 status = "disabled";              542                 status = "disabled";
543         };                                        543         };
544                                                   544 
545         i2c1: i2c@ff660000 {                      545         i2c1: i2c@ff660000 {
546                 compatible = "rockchip,rk3368-    546                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
547                 reg = <0x0 0xff660000 0x0 0x10    547                 reg = <0x0 0xff660000 0x0 0x1000>;
548                 interrupts = <GIC_SPI 61 IRQ_T    548                 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
549                 #address-cells = <1>;             549                 #address-cells = <1>;
550                 #size-cells = <0>;                550                 #size-cells = <0>;
551                 clock-names = "i2c";              551                 clock-names = "i2c";
552                 clocks = <&cru PCLK_I2C1>;        552                 clocks = <&cru PCLK_I2C1>;
553                 pinctrl-names = "default";        553                 pinctrl-names = "default";
554                 pinctrl-0 = <&i2c1_xfer>;         554                 pinctrl-0 = <&i2c1_xfer>;
555                 status = "disabled";              555                 status = "disabled";
556         };                                        556         };
557                                                   557 
558         pwm0: pwm@ff680000 {                      558         pwm0: pwm@ff680000 {
559                 compatible = "rockchip,rk3368-    559                 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
560                 reg = <0x0 0xff680000 0x0 0x10    560                 reg = <0x0 0xff680000 0x0 0x10>;
561                 #pwm-cells = <3>;                 561                 #pwm-cells = <3>;
562                 pinctrl-names = "default";        562                 pinctrl-names = "default";
563                 pinctrl-0 = <&pwm0_pin>;          563                 pinctrl-0 = <&pwm0_pin>;
564                 clocks = <&cru PCLK_PWM1>;        564                 clocks = <&cru PCLK_PWM1>;
565                 status = "disabled";              565                 status = "disabled";
566         };                                        566         };
567                                                   567 
568         pwm1: pwm@ff680010 {                      568         pwm1: pwm@ff680010 {
569                 compatible = "rockchip,rk3368-    569                 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
570                 reg = <0x0 0xff680010 0x0 0x10    570                 reg = <0x0 0xff680010 0x0 0x10>;
571                 #pwm-cells = <3>;                 571                 #pwm-cells = <3>;
572                 pinctrl-names = "default";        572                 pinctrl-names = "default";
573                 pinctrl-0 = <&pwm1_pin>;          573                 pinctrl-0 = <&pwm1_pin>;
574                 clocks = <&cru PCLK_PWM1>;        574                 clocks = <&cru PCLK_PWM1>;
575                 status = "disabled";              575                 status = "disabled";
576         };                                        576         };
577                                                   577 
578         pwm2: pwm@ff680020 {                      578         pwm2: pwm@ff680020 {
579                 compatible = "rockchip,rk3368-    579                 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
580                 reg = <0x0 0xff680020 0x0 0x10    580                 reg = <0x0 0xff680020 0x0 0x10>;
581                 #pwm-cells = <3>;                 581                 #pwm-cells = <3>;
582                 clocks = <&cru PCLK_PWM1>;        582                 clocks = <&cru PCLK_PWM1>;
583                 status = "disabled";              583                 status = "disabled";
584         };                                        584         };
585                                                   585 
586         pwm3: pwm@ff680030 {                      586         pwm3: pwm@ff680030 {
587                 compatible = "rockchip,rk3368-    587                 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
588                 reg = <0x0 0xff680030 0x0 0x10    588                 reg = <0x0 0xff680030 0x0 0x10>;
589                 #pwm-cells = <3>;                 589                 #pwm-cells = <3>;
590                 pinctrl-names = "default";        590                 pinctrl-names = "default";
591                 pinctrl-0 = <&pwm3_pin>;          591                 pinctrl-0 = <&pwm3_pin>;
592                 clocks = <&cru PCLK_PWM1>;        592                 clocks = <&cru PCLK_PWM1>;
593                 status = "disabled";              593                 status = "disabled";
594         };                                        594         };
595                                                   595 
596         uart2: serial@ff690000 {                  596         uart2: serial@ff690000 {
597                 compatible = "rockchip,rk3368-    597                 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
598                 reg = <0x0 0xff690000 0x0 0x10    598                 reg = <0x0 0xff690000 0x0 0x100>;
599                 clocks = <&cru SCLK_UART2>, <&    599                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
600                 clock-names = "baudclk", "apb_    600                 clock-names = "baudclk", "apb_pclk";
601                 interrupts = <GIC_SPI 57 IRQ_T    601                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
602                 pinctrl-names = "default";        602                 pinctrl-names = "default";
603                 pinctrl-0 = <&uart2_xfer>;        603                 pinctrl-0 = <&uart2_xfer>;
604                 reg-shift = <2>;                  604                 reg-shift = <2>;
605                 reg-io-width = <4>;               605                 reg-io-width = <4>;
606                 status = "disabled";              606                 status = "disabled";
607         };                                        607         };
608                                                   608 
609         mbox: mbox@ff6b0000 {                     609         mbox: mbox@ff6b0000 {
610                 compatible = "rockchip,rk3368-    610                 compatible = "rockchip,rk3368-mailbox";
611                 reg = <0x0 0xff6b0000 0x0 0x10    611                 reg = <0x0 0xff6b0000 0x0 0x1000>;
612                 interrupts = <GIC_SPI 146 IRQ_    612                 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
613                              <GIC_SPI 147 IRQ_    613                              <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
614                              <GIC_SPI 148 IRQ_    614                              <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
615                              <GIC_SPI 149 IRQ_    615                              <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
616                 clocks = <&cru PCLK_MAILBOX>;     616                 clocks = <&cru PCLK_MAILBOX>;
617                 clock-names = "pclk_mailbox";     617                 clock-names = "pclk_mailbox";
618                 #mbox-cells = <1>;                618                 #mbox-cells = <1>;
619                 status = "disabled";              619                 status = "disabled";
620         };                                        620         };
621                                                   621 
622         pmu: power-management@ff730000 {          622         pmu: power-management@ff730000 {
623                 compatible = "rockchip,rk3368-    623                 compatible = "rockchip,rk3368-pmu", "syscon", "simple-mfd";
624                 reg = <0x0 0xff730000 0x0 0x10    624                 reg = <0x0 0xff730000 0x0 0x1000>;
625                                                   625 
626                 power: power-controller {         626                 power: power-controller {
627                         compatible = "rockchip    627                         compatible = "rockchip,rk3368-power-controller";
628                         #power-domain-cells =     628                         #power-domain-cells = <1>;
629                         #address-cells = <1>;     629                         #address-cells = <1>;
630                         #size-cells = <0>;        630                         #size-cells = <0>;
631                                                   631 
632                         /*                        632                         /*
633                          * Note: Although SCLK    633                          * Note: Although SCLK_* are the working clocks
634                          * of device without i    634                          * of device without including on the NOC, needed for
635                          * synchronous reset.     635                          * synchronous reset.
636                          *                        636                          *
637                          * The clocks on the w    637                          * The clocks on the which NOC:
638                          * ACLK_IEP/ACLK_VIP/A    638                          * ACLK_IEP/ACLK_VIP/ACLK_VOP0 are on ACLK_VIO0_NIU.
639                          * ACLK_ISP/ACLK_VOP1     639                          * ACLK_ISP/ACLK_VOP1 are on ACLK_VIO1_NIU.
640                          * ACLK_RGA is on ACLK    640                          * ACLK_RGA is on ACLK_RGA_NIU.
641                          * The others (HCLK_*,    641                          * The others (HCLK_*,PLCK_*) are on HCLK_VIO_NIU.
642                          *                        642                          *
643                          * Which clock are dev    643                          * Which clock are device clocks:
644                          *      clocks            644                          *      clocks          devices
645                          *      *_IEP             645                          *      *_IEP           IEP:Image Enhancement Processor
646                          *      *_ISP             646                          *      *_ISP           ISP:Image Signal Processing
647                          *      *_VIP             647                          *      *_VIP           VIP:Video Input Processor
648                          *      *_VOP*            648                          *      *_VOP*          VOP:Visual Output Processor
649                          *      *_RGA             649                          *      *_RGA           RGA
650                          *      *_EDP*            650                          *      *_EDP*          EDP
651                          *      *_DPHY*           651                          *      *_DPHY*         LVDS
652                          *      *_HDMI            652                          *      *_HDMI          HDMI
653                          *      *_MIPI_*          653                          *      *_MIPI_*        MIPI
654                          */                       654                          */
655                         power-domain@RK3368_PD    655                         power-domain@RK3368_PD_VIO {
656                                 reg = <RK3368_    656                                 reg = <RK3368_PD_VIO>;
657                                 clocks = <&cru    657                                 clocks = <&cru ACLK_IEP>,
658                                          <&cru    658                                          <&cru ACLK_ISP>,
659                                          <&cru    659                                          <&cru ACLK_VIP>,
660                                          <&cru    660                                          <&cru ACLK_RGA>,
661                                          <&cru    661                                          <&cru ACLK_VOP>,
662                                          <&cru    662                                          <&cru ACLK_VOP_IEP>,
663                                          <&cru    663                                          <&cru DCLK_VOP>,
664                                          <&cru    664                                          <&cru HCLK_IEP>,
665                                          <&cru    665                                          <&cru HCLK_ISP>,
666                                          <&cru    666                                          <&cru HCLK_RGA>,
667                                          <&cru    667                                          <&cru HCLK_VIP>,
668                                          <&cru    668                                          <&cru HCLK_VOP>,
669                                          <&cru    669                                          <&cru HCLK_VIO_HDCPMMU>,
670                                          <&cru    670                                          <&cru PCLK_EDP_CTRL>,
671                                          <&cru    671                                          <&cru PCLK_HDMI_CTRL>,
672                                          <&cru    672                                          <&cru PCLK_HDCP>,
673                                          <&cru    673                                          <&cru PCLK_ISP>,
674                                          <&cru    674                                          <&cru PCLK_VIP>,
675                                          <&cru    675                                          <&cru PCLK_DPHYRX>,
676                                          <&cru    676                                          <&cru PCLK_DPHYTX0>,
677                                          <&cru    677                                          <&cru PCLK_MIPI_CSI>,
678                                          <&cru    678                                          <&cru PCLK_MIPI_DSI0>,
679                                          <&cru    679                                          <&cru SCLK_VOP0_PWM>,
680                                          <&cru    680                                          <&cru SCLK_EDP_24M>,
681                                          <&cru    681                                          <&cru SCLK_EDP>,
682                                          <&cru    682                                          <&cru SCLK_HDCP>,
683                                          <&cru    683                                          <&cru SCLK_ISP>,
684                                          <&cru    684                                          <&cru SCLK_RGA>,
685                                          <&cru    685                                          <&cru SCLK_HDMI_CEC>,
686                                          <&cru    686                                          <&cru SCLK_HDMI_HDCP>;
687                                 pm_qos = <&qos    687                                 pm_qos = <&qos_iep>,
688                                          <&qos    688                                          <&qos_isp_r0>,
689                                          <&qos    689                                          <&qos_isp_r1>,
690                                          <&qos    690                                          <&qos_isp_w0>,
691                                          <&qos    691                                          <&qos_isp_w1>,
692                                          <&qos    692                                          <&qos_vip>,
693                                          <&qos    693                                          <&qos_vop>,
694                                          <&qos    694                                          <&qos_rga_r>,
695                                          <&qos    695                                          <&qos_rga_w>;
696                                 #power-domain-    696                                 #power-domain-cells = <0>;
697                         };                        697                         };
698                                                   698 
699                         /*                        699                         /*
700                          * Note: ACLK_VCODEC/H    700                          * Note: ACLK_VCODEC/HCLK_VCODEC are VCODEC
701                          * (video endecoder &     701                          * (video endecoder & decoder) clocks that on the
702                          * ACLK_VCODEC_NIU and    702                          * ACLK_VCODEC_NIU and HCLK_VCODEC_NIU (NOC).
703                          */                       703                          */
704                         power-domain@RK3368_PD    704                         power-domain@RK3368_PD_VIDEO {
705                                 reg = <RK3368_    705                                 reg = <RK3368_PD_VIDEO>;
706                                 clocks = <&cru    706                                 clocks = <&cru ACLK_VIDEO>,
707                                          <&cru    707                                          <&cru HCLK_VIDEO>,
708                                          <&cru    708                                          <&cru SCLK_HEVC_CABAC>,
709                                          <&cru    709                                          <&cru SCLK_HEVC_CORE>;
710                                 pm_qos = <&qos    710                                 pm_qos = <&qos_hevc_r>,
711                                          <&qos    711                                          <&qos_vpu_r>,
712                                          <&qos    712                                          <&qos_vpu_w>;
713                                 #power-domain-    713                                 #power-domain-cells = <0>;
714                         };                        714                         };
715                                                   715 
716                         /*                        716                         /*
717                          * Note: ACLK_GPU is t    717                          * Note: ACLK_GPU is the GPU clock,
718                          * and on the ACLK_GPU    718                          * and on the ACLK_GPU_NIU (NOC).
719                          */                       719                          */
720                         power-domain@RK3368_PD    720                         power-domain@RK3368_PD_GPU_1 {
721                                 reg = <RK3368_    721                                 reg = <RK3368_PD_GPU_1>;
722                                 clocks = <&cru    722                                 clocks = <&cru ACLK_GPU_CFG>,
723                                          <&cru    723                                          <&cru ACLK_GPU_MEM>,
724                                          <&cru    724                                          <&cru SCLK_GPU_CORE>;
725                                 pm_qos = <&qos    725                                 pm_qos = <&qos_gpu>;
726                                 #power-domain-    726                                 #power-domain-cells = <0>;
727                         };                        727                         };
728                 };                                728                 };
729         };                                        729         };
730                                                   730 
731         pmugrf: syscon@ff738000 {                 731         pmugrf: syscon@ff738000 {
732                 compatible = "rockchip,rk3368-    732                 compatible = "rockchip,rk3368-pmugrf", "syscon", "simple-mfd";
733                 reg = <0x0 0xff738000 0x0 0x10    733                 reg = <0x0 0xff738000 0x0 0x1000>;
734                                                   734 
735                 pmu_io_domains: io-domains {      735                 pmu_io_domains: io-domains {
736                         compatible = "rockchip    736                         compatible = "rockchip,rk3368-pmu-io-voltage-domain";
737                         status = "disabled";      737                         status = "disabled";
738                 };                                738                 };
739                                                   739 
740                 reboot-mode {                     740                 reboot-mode {
741                         compatible = "syscon-r    741                         compatible = "syscon-reboot-mode";
742                         offset = <0x200>;         742                         offset = <0x200>;
743                         mode-normal = <BOOT_NO    743                         mode-normal = <BOOT_NORMAL>;
744                         mode-recovery = <BOOT_    744                         mode-recovery = <BOOT_RECOVERY>;
745                         mode-bootloader = <BOO    745                         mode-bootloader = <BOOT_FASTBOOT>;
746                         mode-loader = <BOOT_BL    746                         mode-loader = <BOOT_BL_DOWNLOAD>;
747                 };                                747                 };
748         };                                        748         };
749                                                   749 
750         cru: clock-controller@ff760000 {          750         cru: clock-controller@ff760000 {
751                 compatible = "rockchip,rk3368-    751                 compatible = "rockchip,rk3368-cru";
752                 reg = <0x0 0xff760000 0x0 0x10    752                 reg = <0x0 0xff760000 0x0 0x1000>;
753                 clocks = <&xin24m>;               753                 clocks = <&xin24m>;
754                 clock-names = "xin24m";           754                 clock-names = "xin24m";
755                 rockchip,grf = <&grf>;            755                 rockchip,grf = <&grf>;
756                 #clock-cells = <1>;               756                 #clock-cells = <1>;
757                 #reset-cells = <1>;               757                 #reset-cells = <1>;
758         };                                        758         };
759                                                   759 
760         grf: syscon@ff770000 {                    760         grf: syscon@ff770000 {
761                 compatible = "rockchip,rk3368-    761                 compatible = "rockchip,rk3368-grf", "syscon", "simple-mfd";
762                 reg = <0x0 0xff770000 0x0 0x10    762                 reg = <0x0 0xff770000 0x0 0x1000>;
763                                                   763 
764                 io_domains: io-domains {          764                 io_domains: io-domains {
765                         compatible = "rockchip    765                         compatible = "rockchip,rk3368-io-voltage-domain";
766                         status = "disabled";      766                         status = "disabled";
767                 };                                767                 };
768         };                                        768         };
769                                                   769 
770         wdt: watchdog@ff800000 {                  770         wdt: watchdog@ff800000 {
771                 compatible = "rockchip,rk3368-    771                 compatible = "rockchip,rk3368-wdt", "snps,dw-wdt";
772                 reg = <0x0 0xff800000 0x0 0x10    772                 reg = <0x0 0xff800000 0x0 0x100>;
773                 clocks = <&cru PCLK_WDT>;         773                 clocks = <&cru PCLK_WDT>;
774                 interrupts = <GIC_SPI 79 IRQ_T    774                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
775                 status = "disabled";              775                 status = "disabled";
776         };                                        776         };
777                                                   777 
778         timer0: timer@ff810000 {                  778         timer0: timer@ff810000 {
779                 compatible = "rockchip,rk3368-    779                 compatible = "rockchip,rk3368-timer", "rockchip,rk3288-timer";
780                 reg = <0x0 0xff810000 0x0 0x20    780                 reg = <0x0 0xff810000 0x0 0x20>;
781                 interrupts = <GIC_SPI 66 IRQ_T    781                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
782                 clocks = <&cru PCLK_TIMER0>, <    782                 clocks = <&cru PCLK_TIMER0>, <&cru SCLK_TIMER00>;
783                 clock-names = "pclk", "timer";    783                 clock-names = "pclk", "timer";
784         };                                        784         };
785                                                   785 
786         spdif: spdif@ff880000 {                   786         spdif: spdif@ff880000 {
787                 compatible = "rockchip,rk3368-    787                 compatible = "rockchip,rk3368-spdif";
788                 reg = <0x0 0xff880000 0x0 0x10    788                 reg = <0x0 0xff880000 0x0 0x1000>;
789                 interrupts = <GIC_SPI 54 IRQ_T    789                 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
790                 clocks = <&cru SCLK_SPDIF_8CH>    790                 clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>;
791                 clock-names = "mclk", "hclk";     791                 clock-names = "mclk", "hclk";
792                 dmas = <&dmac_bus 3>;             792                 dmas = <&dmac_bus 3>;
793                 dma-names = "tx";                 793                 dma-names = "tx";
794                 pinctrl-names = "default";        794                 pinctrl-names = "default";
795                 pinctrl-0 = <&spdif_tx>;          795                 pinctrl-0 = <&spdif_tx>;
796                 #sound-dai-cells = <0>;           796                 #sound-dai-cells = <0>;
797                 status = "disabled";              797                 status = "disabled";
798         };                                        798         };
799                                                   799 
800         i2s_2ch: i2s-2ch@ff890000 {               800         i2s_2ch: i2s-2ch@ff890000 {
801                 compatible = "rockchip,rk3368-    801                 compatible = "rockchip,rk3368-i2s", "rockchip,rk3066-i2s";
802                 reg = <0x0 0xff890000 0x0 0x10    802                 reg = <0x0 0xff890000 0x0 0x1000>;
803                 interrupts = <GIC_SPI 40 IRQ_T    803                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
804                 clock-names = "i2s_clk", "i2s_    804                 clock-names = "i2s_clk", "i2s_hclk";
805                 clocks = <&cru SCLK_I2S_2CH>,     805                 clocks = <&cru SCLK_I2S_2CH>, <&cru HCLK_I2S_2CH>;
806                 dmas = <&dmac_bus 6>, <&dmac_b    806                 dmas = <&dmac_bus 6>, <&dmac_bus 7>;
807                 dma-names = "tx", "rx";           807                 dma-names = "tx", "rx";
808                 #sound-dai-cells = <0>;           808                 #sound-dai-cells = <0>;
809                 status = "disabled";              809                 status = "disabled";
810         };                                        810         };
811                                                   811 
812         i2s_8ch: i2s-8ch@ff898000 {               812         i2s_8ch: i2s-8ch@ff898000 {
813                 compatible = "rockchip,rk3368-    813                 compatible = "rockchip,rk3368-i2s", "rockchip,rk3066-i2s";
814                 reg = <0x0 0xff898000 0x0 0x10    814                 reg = <0x0 0xff898000 0x0 0x1000>;
815                 interrupts = <GIC_SPI 53 IRQ_T    815                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
816                 clock-names = "i2s_clk", "i2s_    816                 clock-names = "i2s_clk", "i2s_hclk";
817                 clocks = <&cru SCLK_I2S_8CH>,     817                 clocks = <&cru SCLK_I2S_8CH>, <&cru HCLK_I2S_8CH>;
818                 dmas = <&dmac_bus 0>, <&dmac_b    818                 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
819                 dma-names = "tx", "rx";           819                 dma-names = "tx", "rx";
820                 pinctrl-names = "default";        820                 pinctrl-names = "default";
821                 pinctrl-0 = <&i2s_8ch_bus>;       821                 pinctrl-0 = <&i2s_8ch_bus>;
822                 #sound-dai-cells = <0>;           822                 #sound-dai-cells = <0>;
823                 status = "disabled";              823                 status = "disabled";
824         };                                        824         };
825                                                   825 
826         iep_mmu: iommu@ff900800 {                 826         iep_mmu: iommu@ff900800 {
827                 compatible = "rockchip,iommu";    827                 compatible = "rockchip,iommu";
828                 reg = <0x0 0xff900800 0x0 0x10    828                 reg = <0x0 0xff900800 0x0 0x100>;
829                 interrupts = <GIC_SPI 17 IRQ_T    829                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
830                 clocks = <&cru ACLK_IEP>, <&cr    830                 clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
831                 clock-names = "aclk", "iface";    831                 clock-names = "aclk", "iface";
832                 power-domains = <&power RK3368    832                 power-domains = <&power RK3368_PD_VIO>;
833                 #iommu-cells = <0>;               833                 #iommu-cells = <0>;
834                 status = "disabled";              834                 status = "disabled";
835         };                                        835         };
836                                                   836 
837         isp_mmu: iommu@ff914000 {                 837         isp_mmu: iommu@ff914000 {
838                 compatible = "rockchip,iommu";    838                 compatible = "rockchip,iommu";
839                 reg = <0x0 0xff914000 0x0 0x10    839                 reg = <0x0 0xff914000 0x0 0x100>,
840                       <0x0 0xff915000 0x0 0x10    840                       <0x0 0xff915000 0x0 0x100>;
841                 interrupts = <GIC_SPI 14 IRQ_T    841                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
842                 clocks = <&cru ACLK_ISP>, <&cr    842                 clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>;
843                 clock-names = "aclk", "iface";    843                 clock-names = "aclk", "iface";
844                 #iommu-cells = <0>;               844                 #iommu-cells = <0>;
845                 power-domains = <&power RK3368    845                 power-domains = <&power RK3368_PD_VIO>;
846                 rockchip,disable-mmu-reset;       846                 rockchip,disable-mmu-reset;
847                 status = "disabled";              847                 status = "disabled";
848         };                                        848         };
849                                                   849 
850         vop_mmu: iommu@ff930300 {                 850         vop_mmu: iommu@ff930300 {
851                 compatible = "rockchip,iommu";    851                 compatible = "rockchip,iommu";
852                 reg = <0x0 0xff930300 0x0 0x10    852                 reg = <0x0 0xff930300 0x0 0x100>;
853                 interrupts = <GIC_SPI 15 IRQ_T    853                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
854                 clocks = <&cru ACLK_VOP>, <&cr    854                 clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
855                 clock-names = "aclk", "iface";    855                 clock-names = "aclk", "iface";
856                 power-domains = <&power RK3368    856                 power-domains = <&power RK3368_PD_VIO>;
857                 #iommu-cells = <0>;               857                 #iommu-cells = <0>;
858                 status = "disabled";              858                 status = "disabled";
859         };                                        859         };
860                                                   860 
861         hevc_mmu: iommu@ff9a0440 {                861         hevc_mmu: iommu@ff9a0440 {
862                 compatible = "rockchip,iommu";    862                 compatible = "rockchip,iommu";
863                 reg = <0x0 0xff9a0440 0x0 0x40    863                 reg = <0x0 0xff9a0440 0x0 0x40>,
864                       <0x0 0xff9a0480 0x0 0x40    864                       <0x0 0xff9a0480 0x0 0x40>;
865                 interrupts = <GIC_SPI 12 IRQ_T    865                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
866                 clocks = <&cru ACLK_VIDEO>, <&    866                 clocks = <&cru ACLK_VIDEO>, <&cru HCLK_VIDEO>;
867                 clock-names = "aclk", "iface";    867                 clock-names = "aclk", "iface";
868                 #iommu-cells = <0>;               868                 #iommu-cells = <0>;
869                 status = "disabled";              869                 status = "disabled";
870         };                                        870         };
871                                                   871 
872         vpu_mmu: iommu@ff9a0800 {                 872         vpu_mmu: iommu@ff9a0800 {
873                 compatible = "rockchip,iommu";    873                 compatible = "rockchip,iommu";
874                 reg = <0x0 0xff9a0800 0x0 0x10    874                 reg = <0x0 0xff9a0800 0x0 0x100>;
875                 interrupts = <GIC_SPI 9 IRQ_TY    875                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
876                              <GIC_SPI 10 IRQ_T    876                              <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
877                 clocks = <&cru ACLK_VIDEO>, <&    877                 clocks = <&cru ACLK_VIDEO>, <&cru HCLK_VIDEO>;
878                 clock-names = "aclk", "iface";    878                 clock-names = "aclk", "iface";
879                 #iommu-cells = <0>;               879                 #iommu-cells = <0>;
880                 status = "disabled";              880                 status = "disabled";
881         };                                        881         };
882                                                   882 
883         qos_iep: qos@ffad0000 {                   883         qos_iep: qos@ffad0000 {
884                 compatible = "rockchip,rk3368-    884                 compatible = "rockchip,rk3368-qos", "syscon";
885                 reg = <0x0 0xffad0000 0x0 0x20    885                 reg = <0x0 0xffad0000 0x0 0x20>;
886         };                                        886         };
887                                                   887 
888         qos_isp_r0: qos@ffad0080 {                888         qos_isp_r0: qos@ffad0080 {
889                 compatible = "rockchip,rk3368-    889                 compatible = "rockchip,rk3368-qos", "syscon";
890                 reg = <0x0 0xffad0080 0x0 0x20    890                 reg = <0x0 0xffad0080 0x0 0x20>;
891         };                                        891         };
892                                                   892 
893         qos_isp_r1: qos@ffad0100 {                893         qos_isp_r1: qos@ffad0100 {
894                 compatible = "rockchip,rk3368-    894                 compatible = "rockchip,rk3368-qos", "syscon";
895                 reg = <0x0 0xffad0100 0x0 0x20    895                 reg = <0x0 0xffad0100 0x0 0x20>;
896         };                                        896         };
897                                                   897 
898         qos_isp_w0: qos@ffad0180 {                898         qos_isp_w0: qos@ffad0180 {
899                 compatible = "rockchip,rk3368-    899                 compatible = "rockchip,rk3368-qos", "syscon";
900                 reg = <0x0 0xffad0180 0x0 0x20    900                 reg = <0x0 0xffad0180 0x0 0x20>;
901         };                                        901         };
902                                                   902 
903         qos_isp_w1: qos@ffad0200 {                903         qos_isp_w1: qos@ffad0200 {
904                 compatible = "rockchip,rk3368-    904                 compatible = "rockchip,rk3368-qos", "syscon";
905                 reg = <0x0 0xffad0200 0x0 0x20    905                 reg = <0x0 0xffad0200 0x0 0x20>;
906         };                                        906         };
907                                                   907 
908         qos_vip: qos@ffad0280 {                   908         qos_vip: qos@ffad0280 {
909                 compatible = "rockchip,rk3368-    909                 compatible = "rockchip,rk3368-qos", "syscon";
910                 reg = <0x0 0xffad0280 0x0 0x20    910                 reg = <0x0 0xffad0280 0x0 0x20>;
911         };                                        911         };
912                                                   912 
913         qos_vop: qos@ffad0300 {                   913         qos_vop: qos@ffad0300 {
914                 compatible = "rockchip,rk3368-    914                 compatible = "rockchip,rk3368-qos", "syscon";
915                 reg = <0x0 0xffad0300 0x0 0x20    915                 reg = <0x0 0xffad0300 0x0 0x20>;
916         };                                        916         };
917                                                   917 
918         qos_rga_r: qos@ffad0380 {                 918         qos_rga_r: qos@ffad0380 {
919                 compatible = "rockchip,rk3368-    919                 compatible = "rockchip,rk3368-qos", "syscon";
920                 reg = <0x0 0xffad0380 0x0 0x20    920                 reg = <0x0 0xffad0380 0x0 0x20>;
921         };                                        921         };
922                                                   922 
923         qos_rga_w: qos@ffad0400 {                 923         qos_rga_w: qos@ffad0400 {
924                 compatible = "rockchip,rk3368-    924                 compatible = "rockchip,rk3368-qos", "syscon";
925                 reg = <0x0 0xffad0400 0x0 0x20    925                 reg = <0x0 0xffad0400 0x0 0x20>;
926         };                                        926         };
927                                                   927 
928         qos_hevc_r: qos@ffae0000 {                928         qos_hevc_r: qos@ffae0000 {
929                 compatible = "rockchip,rk3368-    929                 compatible = "rockchip,rk3368-qos", "syscon";
930                 reg = <0x0 0xffae0000 0x0 0x20    930                 reg = <0x0 0xffae0000 0x0 0x20>;
931         };                                        931         };
932                                                   932 
933         qos_vpu_r: qos@ffae0100 {                 933         qos_vpu_r: qos@ffae0100 {
934                 compatible = "rockchip,rk3368-    934                 compatible = "rockchip,rk3368-qos", "syscon";
935                 reg = <0x0 0xffae0100 0x0 0x20    935                 reg = <0x0 0xffae0100 0x0 0x20>;
936         };                                        936         };
937                                                   937 
938         qos_vpu_w: qos@ffae0180 {                 938         qos_vpu_w: qos@ffae0180 {
939                 compatible = "rockchip,rk3368-    939                 compatible = "rockchip,rk3368-qos", "syscon";
940                 reg = <0x0 0xffae0180 0x0 0x20    940                 reg = <0x0 0xffae0180 0x0 0x20>;
941         };                                        941         };
942                                                   942 
943         qos_gpu: qos@ffaf0000 {                   943         qos_gpu: qos@ffaf0000 {
944                 compatible = "rockchip,rk3368-    944                 compatible = "rockchip,rk3368-qos", "syscon";
945                 reg = <0x0 0xffaf0000 0x0 0x20    945                 reg = <0x0 0xffaf0000 0x0 0x20>;
946         };                                        946         };
947                                                   947 
948         efuse256: efuse@ffb00000 {                948         efuse256: efuse@ffb00000 {
949                 compatible = "rockchip,rk3368-    949                 compatible = "rockchip,rk3368-efuse";
950                 reg = <0x0 0xffb00000 0x0 0x20    950                 reg = <0x0 0xffb00000 0x0 0x20>;
951                 #address-cells = <1>;             951                 #address-cells = <1>;
952                 #size-cells = <1>;                952                 #size-cells = <1>;
953                 clocks = <&cru PCLK_EFUSE256>;    953                 clocks = <&cru PCLK_EFUSE256>;
954                 clock-names = "pclk_efuse";       954                 clock-names = "pclk_efuse";
955                                                   955 
956                 cpu_leakage: cpu-leakage@17 {     956                 cpu_leakage: cpu-leakage@17 {
957                         reg = <0x17 0x1>;         957                         reg = <0x17 0x1>;
958                 };                                958                 };
959                 temp_adjust: temp-adjust@1f {     959                 temp_adjust: temp-adjust@1f {
960                         reg = <0x1f 0x1>;         960                         reg = <0x1f 0x1>;
961                 };                                961                 };
962         };                                        962         };
963                                                   963 
964         gic: interrupt-controller@ffb71000 {      964         gic: interrupt-controller@ffb71000 {
965                 compatible = "arm,gic-400";       965                 compatible = "arm,gic-400";
966                 interrupt-controller;             966                 interrupt-controller;
967                 #interrupt-cells = <3>;           967                 #interrupt-cells = <3>;
968                 #address-cells = <0>;             968                 #address-cells = <0>;
969                                                   969 
970                 reg = <0x0 0xffb71000 0x0 0x10    970                 reg = <0x0 0xffb71000 0x0 0x1000>,
971                       <0x0 0xffb72000 0x0 0x20    971                       <0x0 0xffb72000 0x0 0x2000>,
972                       <0x0 0xffb74000 0x0 0x20    972                       <0x0 0xffb74000 0x0 0x2000>,
973                       <0x0 0xffb76000 0x0 0x20    973                       <0x0 0xffb76000 0x0 0x2000>;
974                 interrupts = <GIC_PPI 9           974                 interrupts = <GIC_PPI 9
975                       (GIC_CPU_MASK_SIMPLE(8)     975                       (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
976         };                                        976         };
977                                                   977 
978         pinctrl: pinctrl {                        978         pinctrl: pinctrl {
979                 compatible = "rockchip,rk3368-    979                 compatible = "rockchip,rk3368-pinctrl";
980                 rockchip,grf = <&grf>;            980                 rockchip,grf = <&grf>;
981                 rockchip,pmu = <&pmugrf>;         981                 rockchip,pmu = <&pmugrf>;
982                 #address-cells = <0x2>;           982                 #address-cells = <0x2>;
983                 #size-cells = <0x2>;              983                 #size-cells = <0x2>;
984                 ranges;                           984                 ranges;
985                                                   985 
986                 gpio0: gpio@ff750000 {            986                 gpio0: gpio@ff750000 {
987                         compatible = "rockchip    987                         compatible = "rockchip,gpio-bank";
988                         reg = <0x0 0xff750000     988                         reg = <0x0 0xff750000 0x0 0x100>;
989                         clocks = <&cru PCLK_GP    989                         clocks = <&cru PCLK_GPIO0>;
990                         interrupts = <GIC_SPI     990                         interrupts = <GIC_SPI 0x51 IRQ_TYPE_LEVEL_HIGH>;
991                                                   991 
992                         gpio-controller;          992                         gpio-controller;
993                         #gpio-cells = <0x2>;      993                         #gpio-cells = <0x2>;
994                                                   994 
995                         interrupt-controller;     995                         interrupt-controller;
996                         #interrupt-cells = <0x    996                         #interrupt-cells = <0x2>;
997                 };                                997                 };
998                                                   998 
999                 gpio1: gpio@ff780000 {            999                 gpio1: gpio@ff780000 {
1000                         compatible = "rockchi    1000                         compatible = "rockchip,gpio-bank";
1001                         reg = <0x0 0xff780000    1001                         reg = <0x0 0xff780000 0x0 0x100>;
1002                         clocks = <&cru PCLK_G    1002                         clocks = <&cru PCLK_GPIO1>;
1003                         interrupts = <GIC_SPI    1003                         interrupts = <GIC_SPI 0x52 IRQ_TYPE_LEVEL_HIGH>;
1004                                                  1004 
1005                         gpio-controller;         1005                         gpio-controller;
1006                         #gpio-cells = <0x2>;     1006                         #gpio-cells = <0x2>;
1007                                                  1007 
1008                         interrupt-controller;    1008                         interrupt-controller;
1009                         #interrupt-cells = <0    1009                         #interrupt-cells = <0x2>;
1010                 };                               1010                 };
1011                                                  1011 
1012                 gpio2: gpio@ff790000 {           1012                 gpio2: gpio@ff790000 {
1013                         compatible = "rockchi    1013                         compatible = "rockchip,gpio-bank";
1014                         reg = <0x0 0xff790000    1014                         reg = <0x0 0xff790000 0x0 0x100>;
1015                         clocks = <&cru PCLK_G    1015                         clocks = <&cru PCLK_GPIO2>;
1016                         interrupts = <GIC_SPI    1016                         interrupts = <GIC_SPI 0x53 IRQ_TYPE_LEVEL_HIGH>;
1017                                                  1017 
1018                         gpio-controller;         1018                         gpio-controller;
1019                         #gpio-cells = <0x2>;     1019                         #gpio-cells = <0x2>;
1020                                                  1020 
1021                         interrupt-controller;    1021                         interrupt-controller;
1022                         #interrupt-cells = <0    1022                         #interrupt-cells = <0x2>;
1023                 };                               1023                 };
1024                                                  1024 
1025                 gpio3: gpio@ff7a0000 {           1025                 gpio3: gpio@ff7a0000 {
1026                         compatible = "rockchi    1026                         compatible = "rockchip,gpio-bank";
1027                         reg = <0x0 0xff7a0000    1027                         reg = <0x0 0xff7a0000 0x0 0x100>;
1028                         clocks = <&cru PCLK_G    1028                         clocks = <&cru PCLK_GPIO3>;
1029                         interrupts = <GIC_SPI    1029                         interrupts = <GIC_SPI 0x54 IRQ_TYPE_LEVEL_HIGH>;
1030                                                  1030 
1031                         gpio-controller;         1031                         gpio-controller;
1032                         #gpio-cells = <0x2>;     1032                         #gpio-cells = <0x2>;
1033                                                  1033 
1034                         interrupt-controller;    1034                         interrupt-controller;
1035                         #interrupt-cells = <0    1035                         #interrupt-cells = <0x2>;
1036                 };                               1036                 };
1037                                                  1037 
1038                 pcfg_pull_up: pcfg-pull-up {     1038                 pcfg_pull_up: pcfg-pull-up {
1039                         bias-pull-up;            1039                         bias-pull-up;
1040                 };                               1040                 };
1041                                                  1041 
1042                 pcfg_pull_down: pcfg-pull-dow    1042                 pcfg_pull_down: pcfg-pull-down {
1043                         bias-pull-down;          1043                         bias-pull-down;
1044                 };                               1044                 };
1045                                                  1045 
1046                 pcfg_pull_none: pcfg-pull-non    1046                 pcfg_pull_none: pcfg-pull-none {
1047                         bias-disable;            1047                         bias-disable;
1048                 };                               1048                 };
1049                                                  1049 
1050                 pcfg_pull_none_12ma: pcfg-pul    1050                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1051                         bias-disable;            1051                         bias-disable;
1052                         drive-strength = <12>    1052                         drive-strength = <12>;
1053                 };                               1053                 };
1054                                                  1054 
1055                 emmc {                           1055                 emmc {
1056                         emmc_clk: emmc-clk {     1056                         emmc_clk: emmc-clk {
1057                                 rockchip,pins    1057                                 rockchip,pins = <2 RK_PA4 2 &pcfg_pull_none>;
1058                         };                       1058                         };
1059                                                  1059 
1060                         emmc_cmd: emmc-cmd {     1060                         emmc_cmd: emmc-cmd {
1061                                 rockchip,pins    1061                                 rockchip,pins = <1 RK_PD2 2 &pcfg_pull_up>;
1062                         };                       1062                         };
1063                                                  1063 
1064                         emmc_pwr: emmc-pwr {     1064                         emmc_pwr: emmc-pwr {
1065                                 rockchip,pins    1065                                 rockchip,pins = <1 RK_PD3 2 &pcfg_pull_up>;
1066                         };                       1066                         };
1067                                                  1067 
1068                         emmc_bus1: emmc-bus1     1068                         emmc_bus1: emmc-bus1 {
1069                                 rockchip,pins    1069                                 rockchip,pins = <1 RK_PC2 2 &pcfg_pull_up>;
1070                         };                       1070                         };
1071                                                  1071 
1072                         emmc_bus4: emmc-bus4     1072                         emmc_bus4: emmc-bus4 {
1073                                 rockchip,pins    1073                                 rockchip,pins = <1 RK_PC2 2 &pcfg_pull_up>,
1074                                                  1074                                                 <1 RK_PC3 2 &pcfg_pull_up>,
1075                                                  1075                                                 <1 RK_PC4 2 &pcfg_pull_up>,
1076                                                  1076                                                 <1 RK_PC5 2 &pcfg_pull_up>;
1077                         };                       1077                         };
1078                                                  1078 
1079                         emmc_bus8: emmc-bus8     1079                         emmc_bus8: emmc-bus8 {
1080                                 rockchip,pins    1080                                 rockchip,pins = <1 RK_PC2 2 &pcfg_pull_up>,
1081                                                  1081                                                 <1 RK_PC3 2 &pcfg_pull_up>,
1082                                                  1082                                                 <1 RK_PC4 2 &pcfg_pull_up>,
1083                                                  1083                                                 <1 RK_PC5 2 &pcfg_pull_up>,
1084                                                  1084                                                 <1 RK_PC6 2 &pcfg_pull_up>,
1085                                                  1085                                                 <1 RK_PC7 2 &pcfg_pull_up>,
1086                                                  1086                                                 <1 RK_PD0 2 &pcfg_pull_up>,
1087                                                  1087                                                 <1 RK_PD1 2 &pcfg_pull_up>;
1088                         };                       1088                         };
1089                 };                               1089                 };
1090                                                  1090 
1091                 gmac {                           1091                 gmac {
1092                         rgmii_pins: rgmii-pin    1092                         rgmii_pins: rgmii-pins {
1093                                 rockchip,pins    1093                                 rockchip,pins = <3 RK_PC6 1 &pcfg_pull_none>,
1094                                                  1094                                                 <3 RK_PD0 1 &pcfg_pull_none>,
1095                                                  1095                                                 <3 RK_PC3 1 &pcfg_pull_none>,
1096                                                  1096                                                 <3 RK_PB0 1 &pcfg_pull_none_12ma>,
1097                                                  1097                                                 <3 RK_PB1 1 &pcfg_pull_none_12ma>,
1098                                                  1098                                                 <3 RK_PB2 1 &pcfg_pull_none_12ma>,
1099                                                  1099                                                 <3 RK_PB6 1 &pcfg_pull_none_12ma>,
1100                                                  1100                                                 <3 RK_PD4 1 &pcfg_pull_none_12ma>,
1101                                                  1101                                                 <3 RK_PB5 1 &pcfg_pull_none_12ma>,
1102                                                  1102                                                 <3 RK_PB7 1 &pcfg_pull_none>,
1103                                                  1103                                                 <3 RK_PC0 1 &pcfg_pull_none>,
1104                                                  1104                                                 <3 RK_PC1 1 &pcfg_pull_none>,
1105                                                  1105                                                 <3 RK_PC2 1 &pcfg_pull_none>,
1106                                                  1106                                                 <3 RK_PD1 1 &pcfg_pull_none>,
1107                                                  1107                                                 <3 RK_PC4 1 &pcfg_pull_none>;
1108                         };                       1108                         };
1109                                                  1109 
1110                         rmii_pins: rmii-pins     1110                         rmii_pins: rmii-pins {
1111                                 rockchip,pins    1111                                 rockchip,pins = <3 RK_PC6 1 &pcfg_pull_none>,
1112                                                  1112                                                 <3 RK_PD0 1 &pcfg_pull_none>,
1113                                                  1113                                                 <3 RK_PC3 1 &pcfg_pull_none>,
1114                                                  1114                                                 <3 RK_PB0 1 &pcfg_pull_none_12ma>,
1115                                                  1115                                                 <3 RK_PB1 1 &pcfg_pull_none_12ma>,
1116                                                  1116                                                 <3 RK_PB5 1 &pcfg_pull_none_12ma>,
1117                                                  1117                                                 <3 RK_PB7 1 &pcfg_pull_none>,
1118                                                  1118                                                 <3 RK_PC0 1 &pcfg_pull_none>,
1119                                                  1119                                                 <3 RK_PC4 1 &pcfg_pull_none>,
1120                                                  1120                                                 <3 RK_PC5 1 &pcfg_pull_none>;
1121                         };                       1121                         };
1122                 };                               1122                 };
1123                                                  1123 
1124                 i2c0 {                           1124                 i2c0 {
1125                         i2c0_xfer: i2c0-xfer     1125                         i2c0_xfer: i2c0-xfer {
1126                                 rockchip,pins    1126                                 rockchip,pins = <0 RK_PA6 1 &pcfg_pull_none>,
1127                                                  1127                                                 <0 RK_PA7 1 &pcfg_pull_none>;
1128                         };                       1128                         };
1129                 };                               1129                 };
1130                                                  1130 
1131                 i2c1 {                           1131                 i2c1 {
1132                         i2c1_xfer: i2c1-xfer     1132                         i2c1_xfer: i2c1-xfer {
1133                                 rockchip,pins    1133                                 rockchip,pins = <2 RK_PC5 1 &pcfg_pull_none>,
1134                                                  1134                                                 <2 RK_PC6 1 &pcfg_pull_none>;
1135                         };                       1135                         };
1136                 };                               1136                 };
1137                                                  1137 
1138                 i2c2 {                           1138                 i2c2 {
1139                         i2c2_xfer: i2c2-xfer     1139                         i2c2_xfer: i2c2-xfer {
1140                                 rockchip,pins    1140                                 rockchip,pins = <0 RK_PB1 2 &pcfg_pull_none>,
1141                                                  1141                                                 <3 RK_PD7 2 &pcfg_pull_none>;
1142                         };                       1142                         };
1143                 };                               1143                 };
1144                                                  1144 
1145                 i2c3 {                           1145                 i2c3 {
1146                         i2c3_xfer: i2c3-xfer     1146                         i2c3_xfer: i2c3-xfer {
1147                                 rockchip,pins    1147                                 rockchip,pins = <1 RK_PC0 1 &pcfg_pull_none>,
1148                                                  1148                                                 <1 RK_PC1 1 &pcfg_pull_none>;
1149                         };                       1149                         };
1150                 };                               1150                 };
1151                                                  1151 
1152                 i2c4 {                           1152                 i2c4 {
1153                         i2c4_xfer: i2c4-xfer     1153                         i2c4_xfer: i2c4-xfer {
1154                                 rockchip,pins    1154                                 rockchip,pins = <3 RK_PD0 2 &pcfg_pull_none>,
1155                                                  1155                                                 <3 RK_PD1 2 &pcfg_pull_none>;
1156                         };                       1156                         };
1157                 };                               1157                 };
1158                                                  1158 
1159                 i2c5 {                           1159                 i2c5 {
1160                         i2c5_xfer: i2c5-xfer     1160                         i2c5_xfer: i2c5-xfer {
1161                                 rockchip,pins    1161                                 rockchip,pins = <3 RK_PD2 2 &pcfg_pull_none>,
1162                                                  1162                                                 <3 RK_PD3 2 &pcfg_pull_none>;
1163                         };                       1163                         };
1164                 };                               1164                 };
1165                                                  1165 
1166                 i2s {                            1166                 i2s {
1167                         i2s_8ch_bus: i2s-8ch-    1167                         i2s_8ch_bus: i2s-8ch-bus {
1168                                 rockchip,pins    1168                                 rockchip,pins = <2 RK_PB4 1 &pcfg_pull_none>,
1169                                                  1169                                                 <2 RK_PB5 1 &pcfg_pull_none>,
1170                                                  1170                                                 <2 RK_PB6 1 &pcfg_pull_none>,
1171                                                  1171                                                 <2 RK_PB7 1 &pcfg_pull_none>,
1172                                                  1172                                                 <2 RK_PC0 1 &pcfg_pull_none>,
1173                                                  1173                                                 <2 RK_PC1 1 &pcfg_pull_none>,
1174                                                  1174                                                 <2 RK_PC2 1 &pcfg_pull_none>,
1175                                                  1175                                                 <2 RK_PC3 1 &pcfg_pull_none>,
1176                                                  1176                                                 <2 RK_PC4 1 &pcfg_pull_none>;
1177                         };                       1177                         };
1178                 };                               1178                 };
1179                                                  1179 
1180                 pwm0 {                           1180                 pwm0 {
1181                         pwm0_pin: pwm0-pin {     1181                         pwm0_pin: pwm0-pin {
1182                                 rockchip,pins    1182                                 rockchip,pins = <3 RK_PB0 2 &pcfg_pull_none>;
1183                         };                       1183                         };
1184                 };                               1184                 };
1185                                                  1185 
1186                 pwm1 {                           1186                 pwm1 {
1187                         pwm1_pin: pwm1-pin {     1187                         pwm1_pin: pwm1-pin {
1188                                 rockchip,pins    1188                                 rockchip,pins = <0 RK_PB0 2 &pcfg_pull_none>;
1189                         };                       1189                         };
1190                 };                               1190                 };
1191                                                  1191 
1192                 pwm3 {                           1192                 pwm3 {
1193                         pwm3_pin: pwm3-pin {     1193                         pwm3_pin: pwm3-pin {
1194                                 rockchip,pins    1194                                 rockchip,pins = <3 RK_PD5 3 &pcfg_pull_none>;
1195                         };                       1195                         };
1196                 };                               1196                 };
1197                                                  1197 
1198                 sdio0 {                          1198                 sdio0 {
1199                         sdio0_bus1: sdio0-bus    1199                         sdio0_bus1: sdio0-bus1 {
1200                                 rockchip,pins    1200                                 rockchip,pins = <2 RK_PD4 1 &pcfg_pull_up>;
1201                         };                       1201                         };
1202                                                  1202 
1203                         sdio0_bus4: sdio0-bus    1203                         sdio0_bus4: sdio0-bus4 {
1204                                 rockchip,pins    1204                                 rockchip,pins = <2 RK_PD4 1 &pcfg_pull_up>,
1205                                                  1205                                                 <2 RK_PD5 1 &pcfg_pull_up>,
1206                                                  1206                                                 <2 RK_PD6 1 &pcfg_pull_up>,
1207                                                  1207                                                 <2 RK_PD7 1 &pcfg_pull_up>;
1208                         };                       1208                         };
1209                                                  1209 
1210                         sdio0_cmd: sdio0-cmd     1210                         sdio0_cmd: sdio0-cmd {
1211                                 rockchip,pins    1211                                 rockchip,pins = <3 RK_PA0 1 &pcfg_pull_up>;
1212                         };                       1212                         };
1213                                                  1213 
1214                         sdio0_clk: sdio0-clk     1214                         sdio0_clk: sdio0-clk {
1215                                 rockchip,pins    1215                                 rockchip,pins = <3 RK_PA1 1 &pcfg_pull_none>;
1216                         };                       1216                         };
1217                                                  1217 
1218                         sdio0_cd: sdio0-cd {     1218                         sdio0_cd: sdio0-cd {
1219                                 rockchip,pins    1219                                 rockchip,pins = <3 RK_PA2 1 &pcfg_pull_up>;
1220                         };                       1220                         };
1221                                                  1221 
1222                         sdio0_wp: sdio0-wp {     1222                         sdio0_wp: sdio0-wp {
1223                                 rockchip,pins    1223                                 rockchip,pins = <3 RK_PA3 1 &pcfg_pull_up>;
1224                         };                       1224                         };
1225                                                  1225 
1226                         sdio0_pwr: sdio0-pwr     1226                         sdio0_pwr: sdio0-pwr {
1227                                 rockchip,pins    1227                                 rockchip,pins = <3 RK_PA4 1 &pcfg_pull_up>;
1228                         };                       1228                         };
1229                                                  1229 
1230                         sdio0_bkpwr: sdio0-bk    1230                         sdio0_bkpwr: sdio0-bkpwr {
1231                                 rockchip,pins    1231                                 rockchip,pins = <3 RK_PA5 1 &pcfg_pull_up>;
1232                         };                       1232                         };
1233                                                  1233 
1234                         sdio0_int: sdio0-int     1234                         sdio0_int: sdio0-int {
1235                                 rockchip,pins    1235                                 rockchip,pins = <3 RK_PA6 1 &pcfg_pull_up>;
1236                         };                       1236                         };
1237                 };                               1237                 };
1238                                                  1238 
1239                 sdmmc {                          1239                 sdmmc {
1240                         sdmmc_clk: sdmmc-clk     1240                         sdmmc_clk: sdmmc-clk {
1241                                 rockchip,pins    1241                                 rockchip,pins = <2 RK_PB1 1 &pcfg_pull_none>;
1242                         };                       1242                         };
1243                                                  1243 
1244                         sdmmc_cmd: sdmmc-cmd     1244                         sdmmc_cmd: sdmmc-cmd {
1245                                 rockchip,pins    1245                                 rockchip,pins = <2 RK_PB2 1 &pcfg_pull_up>;
1246                         };                       1246                         };
1247                                                  1247 
1248                         sdmmc_cd: sdmmc-cd {     1248                         sdmmc_cd: sdmmc-cd {
1249                                 rockchip,pins    1249                                 rockchip,pins = <2 RK_PB3 1 &pcfg_pull_up>;
1250                         };                       1250                         };
1251                                                  1251 
1252                         sdmmc_bus1: sdmmc-bus    1252                         sdmmc_bus1: sdmmc-bus1 {
1253                                 rockchip,pins    1253                                 rockchip,pins = <2 RK_PA5 1 &pcfg_pull_up>;
1254                         };                       1254                         };
1255                                                  1255 
1256                         sdmmc_bus4: sdmmc-bus    1256                         sdmmc_bus4: sdmmc-bus4 {
1257                                 rockchip,pins    1257                                 rockchip,pins = <2 RK_PA5 1 &pcfg_pull_up>,
1258                                                  1258                                                 <2 RK_PA6 1 &pcfg_pull_up>,
1259                                                  1259                                                 <2 RK_PA7 1 &pcfg_pull_up>,
1260                                                  1260                                                 <2 RK_PB0 1 &pcfg_pull_up>;
1261                         };                       1261                         };
1262                 };                               1262                 };
1263                                                  1263 
1264                 spdif {                          1264                 spdif {
1265                         spdif_tx: spdif-tx {     1265                         spdif_tx: spdif-tx {
1266                                 rockchip,pins    1266                                 rockchip,pins = <2 RK_PC7 1 &pcfg_pull_none>;
1267                         };                       1267                         };
1268                 };                               1268                 };
1269                                                  1269 
1270                 spi0 {                           1270                 spi0 {
1271                         spi0_clk: spi0-clk {     1271                         spi0_clk: spi0-clk {
1272                                 rockchip,pins    1272                                 rockchip,pins = <1 RK_PD5 2 &pcfg_pull_up>;
1273                         };                       1273                         };
1274                         spi0_cs0: spi0-cs0 {     1274                         spi0_cs0: spi0-cs0 {
1275                                 rockchip,pins    1275                                 rockchip,pins = <1 RK_PD0 3 &pcfg_pull_up>;
1276                         };                       1276                         };
1277                         spi0_cs1: spi0-cs1 {     1277                         spi0_cs1: spi0-cs1 {
1278                                 rockchip,pins    1278                                 rockchip,pins = <1 RK_PD1 3 &pcfg_pull_up>;
1279                         };                       1279                         };
1280                         spi0_tx: spi0-tx {       1280                         spi0_tx: spi0-tx {
1281                                 rockchip,pins    1281                                 rockchip,pins = <1 RK_PC7 3 &pcfg_pull_up>;
1282                         };                       1282                         };
1283                         spi0_rx: spi0-rx {       1283                         spi0_rx: spi0-rx {
1284                                 rockchip,pins    1284                                 rockchip,pins = <1 RK_PC6 3 &pcfg_pull_up>;
1285                         };                       1285                         };
1286                 };                               1286                 };
1287                                                  1287 
1288                 spi1 {                           1288                 spi1 {
1289                         spi1_clk: spi1-clk {     1289                         spi1_clk: spi1-clk {
1290                                 rockchip,pins    1290                                 rockchip,pins = <1 RK_PB6 2 &pcfg_pull_up>;
1291                         };                       1291                         };
1292                         spi1_cs0: spi1-cs0 {     1292                         spi1_cs0: spi1-cs0 {
1293                                 rockchip,pins    1293                                 rockchip,pins = <1 RK_PB7 2 &pcfg_pull_up>;
1294                         };                       1294                         };
1295                         spi1_cs1: spi1-cs1 {     1295                         spi1_cs1: spi1-cs1 {
1296                                 rockchip,pins    1296                                 rockchip,pins = <3 RK_PD4 2 &pcfg_pull_up>;
1297                         };                       1297                         };
1298                         spi1_rx: spi1-rx {       1298                         spi1_rx: spi1-rx {
1299                                 rockchip,pins    1299                                 rockchip,pins = <1 RK_PC0 2 &pcfg_pull_up>;
1300                         };                       1300                         };
1301                         spi1_tx: spi1-tx {       1301                         spi1_tx: spi1-tx {
1302                                 rockchip,pins    1302                                 rockchip,pins = <1 RK_PC1 2 &pcfg_pull_up>;
1303                         };                       1303                         };
1304                 };                               1304                 };
1305                                                  1305 
1306                 spi2 {                           1306                 spi2 {
1307                         spi2_clk: spi2-clk {     1307                         spi2_clk: spi2-clk {
1308                                 rockchip,pins    1308                                 rockchip,pins = <0 RK_PB4 2 &pcfg_pull_up>;
1309                         };                       1309                         };
1310                         spi2_cs0: spi2-cs0 {     1310                         spi2_cs0: spi2-cs0 {
1311                                 rockchip,pins    1311                                 rockchip,pins = <0 RK_PB5 2 &pcfg_pull_up>;
1312                         };                       1312                         };
1313                         spi2_rx: spi2-rx {       1313                         spi2_rx: spi2-rx {
1314                                 rockchip,pins    1314                                 rockchip,pins = <0 RK_PB2 2 &pcfg_pull_up>;
1315                         };                       1315                         };
1316                         spi2_tx: spi2-tx {       1316                         spi2_tx: spi2-tx {
1317                                 rockchip,pins    1317                                 rockchip,pins = <0 RK_PB3 2 &pcfg_pull_up>;
1318                         };                       1318                         };
1319                 };                               1319                 };
1320                                                  1320 
1321                 tsadc {                          1321                 tsadc {
1322                         otp_pin: otp-pin {       1322                         otp_pin: otp-pin {
1323                                 rockchip,pins    1323                                 rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
1324                         };                       1324                         };
1325                                                  1325 
1326                         otp_out: otp-out {       1326                         otp_out: otp-out {
1327                                 rockchip,pins    1327                                 rockchip,pins = <0 RK_PA3 1 &pcfg_pull_none>;
1328                         };                       1328                         };
1329                 };                               1329                 };
1330                                                  1330 
1331                 uart0 {                          1331                 uart0 {
1332                         uart0_xfer: uart0-xfe    1332                         uart0_xfer: uart0-xfer {
1333                                 rockchip,pins    1333                                 rockchip,pins = <2 RK_PD0 1 &pcfg_pull_up>,
1334                                                  1334                                                 <2 RK_PD1 1 &pcfg_pull_none>;
1335                         };                       1335                         };
1336                                                  1336 
1337                         uart0_cts: uart0-cts     1337                         uart0_cts: uart0-cts {
1338                                 rockchip,pins    1338                                 rockchip,pins = <2 RK_PD2 1 &pcfg_pull_none>;
1339                         };                       1339                         };
1340                                                  1340 
1341                         uart0_rts: uart0-rts     1341                         uart0_rts: uart0-rts {
1342                                 rockchip,pins    1342                                 rockchip,pins = <2 RK_PD3 1 &pcfg_pull_none>;
1343                         };                       1343                         };
1344                 };                               1344                 };
1345                                                  1345 
1346                 uart1 {                          1346                 uart1 {
1347                         uart1_xfer: uart1-xfe    1347                         uart1_xfer: uart1-xfer {
1348                                 rockchip,pins    1348                                 rockchip,pins = <0 RK_PC4 3 &pcfg_pull_up>,
1349                                                  1349                                                 <0 RK_PC5 3 &pcfg_pull_none>;
1350                         };                       1350                         };
1351                                                  1351 
1352                         uart1_cts: uart1-cts     1352                         uart1_cts: uart1-cts {
1353                                 rockchip,pins    1353                                 rockchip,pins = <0 RK_PC6 3 &pcfg_pull_none>;
1354                         };                       1354                         };
1355                                                  1355 
1356                         uart1_rts: uart1-rts     1356                         uart1_rts: uart1-rts {
1357                                 rockchip,pins    1357                                 rockchip,pins = <0 RK_PC7 3 &pcfg_pull_none>;
1358                         };                       1358                         };
1359                 };                               1359                 };
1360                                                  1360 
1361                 uart2 {                          1361                 uart2 {
1362                         uart2_xfer: uart2-xfe    1362                         uart2_xfer: uart2-xfer {
1363                                 rockchip,pins    1363                                 rockchip,pins = <2 RK_PA6 2 &pcfg_pull_up>,
1364                                                  1364                                                 <2 RK_PA5 2 &pcfg_pull_none>;
1365                         };                       1365                         };
1366                         /* no rts / cts for u    1366                         /* no rts / cts for uart2 */
1367                 };                               1367                 };
1368                                                  1368 
1369                 uart3 {                          1369                 uart3 {
1370                         uart3_xfer: uart3-xfe    1370                         uart3_xfer: uart3-xfer {
1371                                 rockchip,pins    1371                                 rockchip,pins = <3 RK_PD5 2 &pcfg_pull_up>,
1372                                                  1372                                                 <3 RK_PD6 3 &pcfg_pull_none>;
1373                         };                       1373                         };
1374                                                  1374 
1375                         uart3_cts: uart3-cts     1375                         uart3_cts: uart3-cts {
1376                                 rockchip,pins    1376                                 rockchip,pins = <3 RK_PC0 2 &pcfg_pull_none>;
1377                         };                       1377                         };
1378                                                  1378 
1379                         uart3_rts: uart3-rts     1379                         uart3_rts: uart3-rts {
1380                                 rockchip,pins    1380                                 rockchip,pins = <3 RK_PC1 2 &pcfg_pull_none>;
1381                         };                       1381                         };
1382                 };                               1382                 };
1383                                                  1383 
1384                 uart4 {                          1384                 uart4 {
1385                         uart4_xfer: uart4-xfe    1385                         uart4_xfer: uart4-xfer {
1386                                 rockchip,pins    1386                                 rockchip,pins = <0 RK_PD3 3 &pcfg_pull_up>,
1387                                                  1387                                                 <0 RK_PD2 3 &pcfg_pull_none>;
1388                         };                       1388                         };
1389                                                  1389 
1390                         uart4_cts: uart4-cts     1390                         uart4_cts: uart4-cts {
1391                                 rockchip,pins    1391                                 rockchip,pins = <0 RK_PD0 3 &pcfg_pull_none>;
1392                         };                       1392                         };
1393                                                  1393 
1394                         uart4_rts: uart4-rts     1394                         uart4_rts: uart4-rts {
1395                                 rockchip,pins    1395                                 rockchip,pins = <0 RK_PD1 3 &pcfg_pull_none>;
1396                         };                       1396                         };
1397                 };                               1397                 };
1398         };                                       1398         };
1399 };                                               1399 };
                                                      

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